diff --git a/README.md b/README.md index 5c4fc236e8ab7..bdb01a7a4755d 100644 --- a/README.md +++ b/README.md @@ -166,6 +166,8 @@ CircuitPython: corresponding module. * `shared-module` Shared implementation of Python modules that may be based on `common-hal`. +* `supervisor` Code and headers related to the supervisor which monitors and + runs individual MicroPython virtual machines (from code in `py`). * `tests` Test framework and test scripts. * `tools` Various tools, including the pyboard.py module. @@ -210,4 +212,4 @@ rest are here to maintain compatibility with the [Adafruit Feather M0 Adalogger]: https://www.adafruit.com/product/2796 [Arduino Zero]: https://www.arduino.cc/en/Main/ArduinoBoardZero [MicroPython]: https://github.com/micropython/micropython -[Code of Conduct]: https://github.com/adafruit/circuitpython/blob/master/CODE_OF_CONDUCT.md \ No newline at end of file +[Code of Conduct]: https://github.com/adafruit/circuitpython/blob/master/CODE_OF_CONDUCT.md diff --git a/atmel-samd/Makefile b/atmel-samd/Makefile index 1e5fe110d0f62..7792b3bdc8c27 100644 --- a/atmel-samd/Makefile +++ b/atmel-samd/Makefile @@ -1,6 +1,6 @@ # Select the board to build for: if not given on the command line, # then default to PYBV10. -BOARD ?= arduino_zero +BOARD ?= metro_m0_express ifeq ($(wildcard boards/$(BOARD)/.),) $(error Invalid BOARD specified) endif @@ -14,76 +14,44 @@ include ../py/mkenv.mk include boards/$(BOARD)/mpconfigboard.mk # qstr definitions (must come before including py.mk) -# TODO(tannewt): Support friendly pin names like the stmhal implementations do. -# Add $(BUILD)/pins_qstr.h $(BUILD)/modstm_qstr.h QSTR_DEFS = qstrdefsport.h # include py core make definitions include $(TOP)/py/py.mk +include $(TOP)/supervisor/supervisor.mk + CROSS_COMPILE = arm-none-eabi- BOSSAC := tools/bossac_osx HAL_DIR=hal/$(MCU_SERIES) -INC += -I. -INC += -I$(TOP) -INC += -I$(TOP)/lib/mp-readline -INC += -I$(TOP)/lib/timeutils -INC += -Iasf_conf/ -INC += -Iasf/common/boards/ -INC += -Iasf/common/services/sleepmgr/ -INC += -Iasf/common/services/storage/ctrl_access/ -INC += -Iasf/common/services/usb/ -INC += -Iasf/common/services/usb/class/cdc/ -INC += -Iasf/common/services/usb/class/cdc/device/ -INC += -Iasf/common/services/usb/class/hid/ -INC += -Iasf/common/services/usb/class/hid/device/ -INC += -Iasf/common/services/usb/class/hid/device/kbd/ -INC += -Iasf/common/services/usb/class/hid/device/mouse/ -INC += -Iasf/common/services/usb/class/msc/ -INC += -Iasf/common/services/usb/class/msc/device/ -INC += -Iasf/common/services/usb/udc/ -INC += -Iasf/common/utils -INC += -Iasf/common2/services/delay/ -INC += $(addprefix -Iasf/sam0/,\ - drivers/events \ - drivers/extint \ - drivers/port \ - drivers/system \ - drivers/adc/adc_sam_d_r \ - drivers/dac \ - drivers/dac/dac_sam_d_c \ - drivers/sercom \ - drivers/sercom/i2c \ - drivers/system/clock \ - drivers/system/clock/clock_samd21_r21_da \ - drivers/system/interrupt \ - drivers/system/interrupt/system_interrupt_samd21 \ - drivers/system/pinmux \ - drivers/system/power/power_sam_d_r \ - drivers/system/reset/reset_sam_d_r \ - drivers/tc \ - drivers/usb \ - utils \ - utils/cmsis/samd21/include \ - utils/cmsis/samd21/source \ - utils/header_files \ - utils/preprocessor \ - ) -INC += -Iasf/thirdparty/CMSIS/Include -INC += -Iboards -INC += -Iboards/$(BOARD)/ -INC += -Ifreetouch/ -INC += -I$(BUILD) - -CFLAGS_CORTEX_M0 = \ - -mthumb \ - -mabi=aapcs-linux \ - -mcpu=cortex-m0plus \ - -msoft-float \ - -mfloat-abi=soft \ +INC += -I. \ + -I.. \ + -I../lib/mp-readline \ + -I../lib/timeutils \ + -Iasf4/$(CHIP_FAMILY) \ + -Iasf4/$(CHIP_FAMILY)/hal/include \ + -Iasf4/$(CHIP_FAMILY)/hal/utils/include \ + -Iasf4/$(CHIP_FAMILY)/hri \ + -Iasf4/$(CHIP_FAMILY)/hpl/core \ + -Iasf4/$(CHIP_FAMILY)/hpl/pm \ + -Iasf4/$(CHIP_FAMILY)/hpl/port \ + -Iasf4/$(CHIP_FAMILY)/hpl/tc \ + -Iasf4/$(CHIP_FAMILY)/include \ + -Iasf4/$(CHIP_FAMILY)/CMSIS/Include \ + -Iasf4/$(CHIP_FAMILY)/usb \ + -Iasf4/$(CHIP_FAMILY)/usb/class/cdc \ + -Iasf4/$(CHIP_FAMILY)/usb/class/hid \ + -Iasf4/$(CHIP_FAMILY)/usb/device \ + -Iasf4_conf/$(CHIP_FAMILY) \ + -Iboards/$(BOARD) \ + -Iboards/ \ + -Ifreetouch \ + -I$(BUILD) + +BASE_CFLAGS = \ -fsingle-precision-constant \ -fno-strict-aliasing \ -Wdouble-promotion \ @@ -102,42 +70,49 @@ CFLAGS_CORTEX_M0 = \ -Wnested-externs \ -Wunreachable-code \ -Wcast-align \ + -Wno-error=lto-type-mismatch \ -D__$(CHIP_VARIANT)__ \ - -DUSB_DEVICE_PRODUCT_ID=$(USB_PID) \ - -DUSB_DEVICE_VENDOR_ID=$(USB_VID) \ - -DBOARD=USER_BOARD \ + -DCONF_USB_COMPOSITE_IDPRODUCT=$(USB_PID) \ + -DCONF_USB_COMPOSITE_IDVENDER=$(USB_VID) \ -ffunction-sections \ -fdata-sections \ -fshort-enums \ - -D ARM_MATH_CM0PLUS=true \ - -DSYSTICK_MODE \ - -DEXTINT_CALLBACK_MODE=true \ - -DUDD_ENABLE \ - -DUSART_CALLBACK_MODE=false \ - -DSPI_CALLBACK_MODE=false \ - -DI2C_MASTER_CALLBACK_MODE=false \ - -DDAC_CALLBACK_MODE=false \ - -DTCC_ASYNC=false \ - -DADC_CALLBACK_MODE=false \ - -DEVENTS_INTERRUPT_HOOKS_MODE=false \ - -DI2S_CALLBACK_MODE=false \ - -DTC_ASYNC=true \ - -DUSB_DEVICE_LPM_SUPPORT \ - -DCIRCUITPY_CANARY_WORD=0xADAF00 \ - -DCIRCUITPY_SAFE_RESTART_WORD=0xDEADBEEF \ --param max-inline-insns-single=500 -CFLAGS = $(INC) -Wall -Werror -std=gnu11 -nostdlib $(CFLAGS_CORTEX_M0) $(CFLAGS_MOD) $(COPT) #Debugging/Optimization ifeq ($(DEBUG), 1) # NDEBUG disables assert() statements. This reduces code size pretty dramatically, per tannewt. # Turn on Python modules useful for debugging (e.g. uheap, ustack). -# -DMICROPY_DEBUG_MODULES may also be added to an -flto build, if you wish. -CFLAGS += -Os -ggdb -DNDEBUG -DENABLE_MICRO_TRACE_BUFFER -DMICROPY_DEBUG_MODULES +CFLAGS = -O1 -ggdb -DNDEBUG +ifeq ($(CHIP_FAMILY), samd21) +CFLAGS += -DENABLE_MICRO_TRACE_BUFFER +endif else # -finline-limit can shrink the image size. -finline-limit=80 or so is similar to not having it on. # There is no simple default value, though. -CFLAGS += -Os -DNDEBUG -flto -finline-limit=49 +CFLAGS = -Os -DNDEBUG -flto -finline-limit=49 +endif + +CFLAGS += $(INC) -Wall -Werror -std=gnu11 -nostdlib $(BASE_CFLAGS) $(CFLAGS_MOD) $(COPT) + +ifeq ($(CHIP_FAMILY), samd21) +CFLAGS += \ + -mthumb \ + -mabi=aapcs-linux \ + -mcpu=cortex-m0plus \ + -msoft-float \ + -mfloat-abi=soft \ + -DSAMD21 +endif +ifeq ($(CHIP_FAMILY), samd51) +CFLAGS += \ + -mthumb \ + -mabi=aapcs-linux \ + -mlong-calls \ + -mcpu=cortex-m4 \ + -mfloat-abi=softfp \ + -mfpu=fpv4-sp-d16 \ + -DSAMD51 endif ifneq ($(FROZEN_DIR),) @@ -158,69 +133,71 @@ CFLAGS += -Wno-error=lto-type-mismatch endif #LIBM_FILE_NAME = $(shell $(CC) $(CFLAGS) -print-file-name=libm.a) -LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -mthumb -mcpu=cortex-m0plus -Lasf/thirdparty/CMSIS/Lib/GCC/ -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs -LIBS = -larm_cortexM0l_math -lm -lgcc -lc - -SRC_ASF = $(addprefix asf/sam0/,\ - drivers/adc/adc_sam_d_r/adc.c \ - drivers/dac/dac_sam_d_c/dac.c \ - drivers/dma/dma.c \ - drivers/events/events_sam_d_r/events.c \ - drivers/extint/extint_callback.c \ - drivers/extint/extint_sam_d_r/extint.c \ - drivers/i2s/i2s.c \ - drivers/nvm/nvm.c \ - drivers/port/port.c \ - drivers/sercom/i2c/i2c_sam0/i2c_master.c \ - drivers/sercom/sercom.c \ - drivers/sercom/sercom_interrupt.c \ - drivers/sercom/spi/spi.c \ - drivers/sercom/usart/usart.c \ - drivers/system/clock/clock_samd21_r21_da/clock.c \ - drivers/system/clock/clock_samd21_r21_da/gclk.c \ - drivers/system/interrupt/system_interrupt.c \ - drivers/system/pinmux/pinmux.c \ - drivers/system/system.c \ - drivers/tc/tc_interrupt.c \ - drivers/tc/tc_sam_d_r/tc.c \ - drivers/tcc/tcc.c \ - drivers/usb/stack_interface/usb_device_udd.c \ - drivers/usb/stack_interface/usb_dual.c \ - drivers/usb/usb_sam_d_r/usb.c \ - ) +LDFLAGS = $(CFLAGS) -nostartfiles -fshort-enums -Wl,-nostdlib -Wl,-T,$(LD_FILE) -Wl,-Map=$@.map -Wl,-cref -Wl,-gc-sections -specs=nano.specs +LIBS := -lgcc -lc + + +ifeq ($(CHIP_FAMILY), samd21) +LDFLAGS += -mthumb -mcpu=cortex-m0plus -Lasf/thirdparty/CMSIS/Lib/GCC/ +LIBS := -lm $(LIBS) # -larm_cortexM0l_math +else ifeq ($(CHIP_FAMILY), samd51) +LDFLAGS += -mthumb -mcpu=cortex-m4 +LIBS := -lm $(LIBS) +endif + +SRC_ASF := \ + gcc/gcc/startup_$(CHIP_FAMILY).c \ + gcc/system_$(CHIP_FAMILY).c \ + hal/src/hal_atomic.c \ + hal/src/hal_delay.c \ + hal/src/hal_sleep.c \ + hal/src/hal_timer.c \ + hal/src/hal_usb_device.c \ + hpl/core/hpl_init.c \ + hpl/gclk/hpl_gclk.c \ + hpl/pm/hpl_pm.c \ + hpl/rtc/hpl_rtc.c \ + hpl/systick/hpl_systick.c \ + hpl/tc/hpl_tc.c \ + hpl/usb/hpl_usb.c \ + usb/class/cdc/device/cdcdf_acm.c \ + usb/device/usbdc.c \ + usb/usb_protocol.c \ + hal/utils/src/utils_list.c \ + +ifeq ($(CHIP_FAMILY), samd21) +SRC_ASF += \ + hpl/core/hpl_core_m0plus_base.c \ + hpl/sysctrl/hpl_sysctrl.c \ + +else ifeq ($(CHIP_FAMILY), samd51) +SRC_ASF += \ + hpl/core/hpl_core_m4.c \ + hpl/mclk/hpl_mclk.c \ + hpl/osc32kctrl/hpl_osc32kctrl.c \ + hpl/oscctrl/hpl_oscctrl.c \ + +endif + +SRC_ASF := $(addprefix asf4/$(CHIP_FAMILY)/, $(SRC_ASF)) + +# Skip this source for now. +# access_vfs.c \ + shared_dma.c \ + $(FLASH_IMPL) \ SRC_C = \ - access_vfs.c \ - autoreload.c \ background.c \ fatfs_port.c \ flash_api.c \ - main.c \ mphalport.c \ reset.c \ - samd21_pins.c \ - shared_dma.c \ - rgb_led_status.c \ + $(CHIP_FAMILY)_pins.c \ tick.c \ - $(FLASH_IMPL) \ + usb.c \ bindings/samd/__init__.c \ - asf/common/services/sleepmgr/samd/sleepmgr.c \ - asf/common/services/storage/ctrl_access/ctrl_access.c \ - asf/common/services/usb/class/cdc/device/udi_cdc.c \ - asf/common/services/usb/class/composite/device/udi_composite_desc.c \ - asf/common/services/usb/class/hid/device/udi_hid.c \ - asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse.c \ - asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd.c \ - asf/common/services/usb/class/msc/device/udi_msc.c \ - asf/common/services/usb/udc/udc.c \ - asf/common/utils/interrupt/interrupt_sam_nvic.c \ - asf/common2/services/delay/sam0/systick_counter.c \ - asf/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c \ - asf/sam0/utils/cmsis/samd21/source/system_samd21.c \ - asf/sam0/utils/syscalls/gcc/syscalls.c \ boards/$(BOARD)/board.c \ boards/$(BOARD)/pins.c \ - freetouch/adafruit_ptc.c \ lib/oofatfs/ff.c \ lib/oofatfs/option/ccsbcs.c \ lib/timeutils/timeutils.c \ @@ -231,26 +208,27 @@ SRC_C = \ lib/utils/stdout_helpers.c \ lib/utils/sys_stdio_mphal.c \ lib/libc/string0.c \ - lib/mp-readline/readline.c + lib/mp-readline/readline.c \ + # freetouch/adafruit_ptc.c \ SRC_COMMON_HAL = \ - analogio/__init__.c \ + board/__init__.c \ + microcontroller/__init__.c \ + microcontroller/Pin.c \ + microcontroller/Processor.c \ + digitalio/__init__.c \ + digitalio/DigitalInOut.c +# analogio/__init__.c \ analogio/AnalogIn.c \ analogio/AnalogOut.c \ audiobusio/__init__.c \ audiobusio/PDMIn.c \ audioio/__init__.c \ audioio/AudioOut.c \ - board/__init__.c \ busio/__init__.c \ busio/I2C.c \ busio/SPI.c \ busio/UART.c \ - digitalio/__init__.c \ - digitalio/DigitalInOut.c \ - microcontroller/__init__.c \ - microcontroller/Pin.c \ - microcontroller/Processor.c \ neopixel_write/__init__.c \ nvm/__init__.c \ nvm/ByteArray.c \ @@ -293,12 +271,12 @@ SRC_SHARED_MODULE = \ SRC_SHARED_MODULE_EXPANDED = $(addprefix shared-bindings/, $(SRC_SHARED_MODULE)) \ $(addprefix shared-module/, $(SRC_SHARED_MODULE)) -OBJ = $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) +OBJ = $(PY_O) $(SUPERVISOR_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_ASF:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_COMMON_HAL_EXPANDED:.c=.o)) OBJ += $(addprefix $(BUILD)/, $(SRC_SHARED_MODULE_EXPANDED:.c=.o)) -SRC_QSTR += $(SRC_C) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED) $(STM_SRC_C) +SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED) $(STM_SRC_C) all: $(BUILD)/firmware.bin $(BUILD)/firmware.uf2 diff --git a/atmel-samd/access_vfs.c b/atmel-samd/access_vfs.c index 9c9c0c0346a80..b2e21f78339ed 100644 --- a/atmel-samd/access_vfs.c +++ b/atmel-samd/access_vfs.c @@ -29,7 +29,6 @@ #include "access_vfs.h" #include "autoreload.h" -#include "asf/common/services/usb/class/msc/device/udi_msc.h" #include "extmod/vfs.h" #include "extmod/vfs_fat.h" #include "lib/oofatfs/ff.h" diff --git a/atmel-samd/access_vfs.h b/atmel-samd/access_vfs.h index 9e64fed7ed80c..fac50632fcff6 100644 --- a/atmel-samd/access_vfs.h +++ b/atmel-samd/access_vfs.h @@ -30,8 +30,6 @@ #ifndef MICROPY_INCLUDED_ATMEL_SAMD_ROM_FS_H #define MICROPY_INCLUDED_ATMEL_SAMD_ROM_FS_H -#include "asf/common/services/storage/ctrl_access/ctrl_access.h" - Ctrl_status vfs_test_unit_ready(void); Ctrl_status vfs_read_capacity(uint32_t *u32_nb_sector); bool vfs_wr_protect(void); diff --git a/atmel-samd/asf/asf-releasenotes-3.32.0.pdf b/atmel-samd/asf/asf-releasenotes-3.32.0.pdf deleted file mode 100644 index 0a17a3bc282aa..0000000000000 Binary files a/atmel-samd/asf/asf-releasenotes-3.32.0.pdf and /dev/null differ diff --git a/atmel-samd/asf/common/boards/board.h b/atmel-samd/asf/common/boards/board.h deleted file mode 100644 index 6e83398526099..0000000000000 --- a/atmel-samd/asf/common/boards/board.h +++ /dev/null @@ -1,445 +0,0 @@ -/** - * \file - * - * \brief Standard board header file. - * - * This file includes the appropriate board header file according to the - * defined board (parameter BOARD). - * - * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _BOARD_H_ -#define _BOARD_H_ - -/** - * \defgroup group_common_boards Generic board support - * - * The generic board support module includes board-specific definitions - * and function prototypes, such as the board initialization function. - * - * \{ - */ - -#include "compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/*! \name Base Boards - */ -//! @{ -#define EVK1100 1 //!< AT32UC3A EVK1100 board. -#define EVK1101 2 //!< AT32UC3B EVK1101 board. -#define UC3C_EK 3 //!< AT32UC3C UC3C-EK board. -#define EVK1104 4 //!< AT32UC3A3 EVK1104 board. -#define EVK1105 5 //!< AT32UC3A EVK1105 board. -#define STK600_RCUC3L0 6 //!< STK600 RCUC3L0 board. -#define UC3L_EK 7 //!< AT32UC3L-EK board. -#define XPLAIN 8 //!< ATxmega128A1 Xplain board. -#define STK600_RC064X 10 //!< ATxmega256A3 STK600 board. -#define STK600_RC100X 11 //!< ATxmega128A1 STK600 board. -#define UC3_A3_XPLAINED 13 //!< ATUC3A3 UC3-A3 Xplained board. -#define UC3_L0_XPLAINED 15 //!< ATUC3L0 UC3-L0 Xplained board. -#define STK600_RCUC3D 16 //!< STK600 RCUC3D board. -#define STK600_RCUC3C0 17 //!< STK600 RCUC3C board. -#define XMEGA_B1_XPLAINED 18 //!< ATxmega128B1 Xplained board. -#define XMEGA_A1_XPLAINED 19 //!< ATxmega128A1 Xplain-A1 board. -#define XMEGA_A1U_XPLAINED_PRO 20 //!< ATxmega128A1U XMEGA-A1U Xplained Pro board. -#define STK600_RCUC3L4 21 //!< ATUCL4 STK600 board. -#define UC3_L0_XPLAINED_BC 22 //!< ATUC3L0 UC3-L0 Xplained board controller board. -#define MEGA1284P_XPLAINED_BC 23 //!< ATmega1284P-Xplained board controller board. -#define STK600_RC044X 24 //!< STK600 with RC044X routing card board. -#define STK600_RCUC3B0 25 //!< STK600 RCUC3B0 board. -#define UC3_L0_QT600 26 //!< QT600 UC3L0 MCU board. -#define XMEGA_A3BU_XPLAINED 27 //!< ATxmega256A3BU Xplained board. -#define STK600_RC064X_LCDX 28 //!< XMEGAB3 STK600 RC064X LCDX board. -#define STK600_RC100X_LCDX 29 //!< XMEGAB1 STK600 RC100X LCDX board. -#define UC3B_BOARD_CONTROLLER 30 //!< AT32UC3B1 board controller for Atmel boards. -#define RZ600 31 //!< AT32UC3A RZ600 MCU board. -#define SAM3S_EK 32 //!< SAM3S-EK board. -#define SAM3U_EK 33 //!< SAM3U-EK board. -#define SAM3X_EK 34 //!< SAM3X-EK board. -#define SAM3N_EK 35 //!< SAM3N-EK board. -#define SAM3S_EK2 36 //!< SAM3S-EK2 board. -#define SAM4S_EK 37 //!< SAM4S-EK board. -#define STK600_RCUC3A0 38 //!< STK600 RCUC3A0 board. -#define STK600_MEGA 39 //!< STK600 MEGA board. -#define MEGA_1284P_XPLAINED 40 //!< ATmega1284P Xplained board. -#define SAM4S_XPLAINED 41 //!< SAM4S Xplained board. -#define ATXMEGA128A1_QT600 42 //!< QT600 ATXMEGA128A1 MCU board. -#define ARDUINO_DUE_X 43 //!< Arduino Due/X board. -#define STK600_RCUC3L3 44 //!< ATUCL3 STK600 board. -#define SAM4L_EK 45 //!< SAM4L-EK board. -#define STK600_MEGA_RF 46 //!< STK600 MEGA RF EVK board. -#define XMEGA_C3_XPLAINED 47 //!< ATxmega384C3 Xplained board. -#define STK600_RC032X 48 //!< STK600 with RC032X routing card board. -#define SAM4S_EK2 49 //!< SAM4S-EK2 board. -#define XMEGA_E5_XPLAINED 50 //!< ATxmega32E5 Xplained board. -#define SAM4E_EK 51 //!< SAM4E-EK board. -#define ATMEGA256RFR2_XPLAINED_PRO 52 //!< ATmega256RFR2 Xplained Pro board. -#define SAM4S_XPLAINED_PRO 53 //!< SAM4S Xplained Pro board. -#define SAM4L_XPLAINED_PRO 54 //!< SAM4L Xplained Pro board. -#define ATMEGA256RFR2_ZIGBIT 55 //!< ATmega256RFR2 zigbit. -#define XMEGA_RF233_ZIGBIT 56 //!< ATxmega256A3U with AT86RF233 Zigbit. -#define XMEGA_RF212B_ZIGBIT 57 //!< ATxmega256A3U with AT86RF212B Zigbit. -#define SAM4S_WPIR_RD 58 //!< SAM4S-WPIR-RD board. -#define SAMD20_XPLAINED_PRO 59 //!< SAM D20 Xplained Pro board. -#define SAM4L8_XPLAINED_PRO 60 //!< SAM4L8 Xplained Pro board. -#define SAM4N_XPLAINED_PRO 61 //!< SAM4N Xplained Pro board. -#define XMEGA_A3_REB_CBB 62 //!< XMEGA REB Controller Base board. -#define ATMEGARFX_RCB 63 //!< RFR2 & RFA1 RCB. -#define SAM4C_EK 64 //!< SAM4C-EK board. -#define RCB256RFR2_XPRO 65 //!< RFR2 RCB Xplained Pro board. -#define SAMG53_XPLAINED_PRO 66 //!< SAMG53 Xplained Pro board. -#define SAM4CP16BMB 67 //!< SAM4CP16BMB board. -#define SAM4E_XPLAINED_PRO 68 //!< SAM4E Xplained Pro board. -#define SAMD21_XPLAINED_PRO 69 //!< SAM D21 Xplained Pro board. -#define SAMR21_XPLAINED_PRO 70 //!< SAM R21 Xplained Pro board. -#define SAM4CMP_DB 71 //!< SAM4CMP demo board. -#define SAM4CMS_DB 72 //!< SAM4CMS demo board. -#define ATPL230AMB 73 //!< ATPL230AMB board. -#define SAMD11_XPLAINED_PRO 74 //!< SAM D11 Xplained Pro board. -#define SAMG55_XPLAINED_PRO 75 //!< SAMG55 Xplained Pro board. -#define SAML21_XPLAINED_PRO 76 //!< SAM L21 Xplained Pro board. -#define SAMD10_XPLAINED_MINI 77 //!< SAM D10 Xplained Mini board. -#define SAMDA1_XPLAINED_PRO 78 //!< SAM DA1 Xplained Pro board. -#define SAMW25_XPLAINED_PRO 79 //!< SAMW25 Xplained Pro board. -#define SAMC21_XPLAINED_PRO 80 //!< SAM C21 Xplained Pro board. -#define SAMV71_XPLAINED_ULTRA 81 //!< SAMV71 Xplained Ultra board. -#define ATMEGA328P_XPLAINED_MINI 82 //!< ATMEGA328P Xplained MINI board. -#define ATMEGA328PB_XPLAINED_MINI 83 //!< ATMEGA328PB Xplained MINI board. -#define SAMB11_XPLAINED_PRO 84 //!< SAM B11 Xplained Pro board. -#define SAME70_XPLAINED 85 //!< SAME70 Xplained board. -#define SAML22_XPLAINED_PRO 86 //!< SAM L22 Xplained Pro board. -#define SAML22_XPLAINED_PRO_B 87 //!< SAM L22 Xplained Pro board. -#define SAMR21ZLL_EK 88 //!< SAMR21ZLL-EK board. -#define ATMEGA168PB_XPLAINED_MINI 89 //!< ATMEGA168PB Xplained MINI board. -#define ATMEGA324PB_XPLAINED_PRO 90 //!< ATMEGA324PB Xplained Pro board. -#define SAMB11CSP_XPLAINED_PRO 91 //!< SAM B11 CSP Xplained Pro board. -#define SAMB11ZR_XPLAINED_PRO 92 //!< SAM B11 ZR Xplained Pro board. -#define SAMR30_XPLAINED_PRO 93 //!< SAM R30 Xplained Pro board. -#define SIMULATOR_XMEGA_A1 97 //!< Simulator for XMEGA A1 devices. -#define AVR_SIMULATOR_UC3 98 //!< Simulator for the AVR UC3 device family. -#define USER_BOARD 99 //!< User-reserved board (if any). -#define DUMMY_BOARD 100 //!< Dummy board to support board-independent applications (e.g. bootloader). -//! @} - -/*! \name Extension Boards - */ -//! @{ -#define EXT1102 1 //!< AT32UC3B EXT1102 board -#define MC300 2 //!< AT32UC3 MC300 board -#define SENSORS_XPLAINED_INERTIAL_1 3 //!< Xplained inertial sensor board 1 -#define SENSORS_XPLAINED_INERTIAL_2 4 //!< Xplained inertial sensor board 2 -#define SENSORS_XPLAINED_PRESSURE_1 5 //!< Xplained pressure sensor board -#define SENSORS_XPLAINED_LIGHTPROX_1 6 //!< Xplained light & proximity sensor board -#define SENSORS_XPLAINED_INERTIAL_A1 7 //!< Xplained inertial sensor board "A" -#define RZ600_AT86RF231 8 //!< AT86RF231 RF board in RZ600 -#define RZ600_AT86RF230B 9 //!< AT86RF230B RF board in RZ600 -#define RZ600_AT86RF212 10 //!< AT86RF212 RF board in RZ600 -#define SENSORS_XPLAINED_BREADBOARD 11 //!< Xplained sensor development breadboard -#define SECURITY_XPLAINED 12 //!< Xplained ATSHA204 board -#define USER_EXT_BOARD 99 //!< User-reserved extension board (if any). -//! @} - -#if BOARD == EVK1100 -# include "evk1100/evk1100.h" -#elif BOARD == EVK1101 -# include "evk1101/evk1101.h" -#elif BOARD == UC3C_EK -# include "uc3c_ek/uc3c_ek.h" -#elif BOARD == EVK1104 -# include "evk1104/evk1104.h" -#elif BOARD == EVK1105 -# include "evk1105/evk1105.h" -#elif BOARD == STK600_RCUC3L0 -# include "stk600/rcuc3l0/stk600_rcuc3l0.h" -#elif BOARD == UC3L_EK -# include "uc3l_ek/uc3l_ek.h" -#elif BOARD == STK600_RCUC3L4 -# include "stk600/rcuc3l4/stk600_rcuc3l4.h" -#elif BOARD == XPLAIN -# include "xplain/xplain.h" -#elif BOARD == STK600_MEGA - /*No header-file to include*/ -#elif BOARD == STK600_MEGA_RF -# include "stk600.h" -#elif BOARD == ATMEGA256RFR2_XPLAINED_PRO -# include "atmega256rfr2_xplained_pro/atmega256rfr2_xplained_pro.h" -#elif BOARD == ATMEGA256RFR2_ZIGBIT -# include "atmega256rfr2_zigbit/atmega256rfr2_zigbit.h" -#elif BOARD == STK600_RC032X -# include "stk600/rc032x/stk600_rc032x.h" -#elif BOARD == STK600_RC044X -# include "stk600/rc044x/stk600_rc044x.h" -#elif BOARD == STK600_RC064X -# include "stk600/rc064x/stk600_rc064x.h" -#elif BOARD == STK600_RC100X -# include "stk600/rc100x/stk600_rc100x.h" -#elif BOARD == UC3_A3_XPLAINED -# include "uc3_a3_xplained/uc3_a3_xplained.h" -#elif BOARD == UC3_L0_XPLAINED -# include "uc3_l0_xplained/uc3_l0_xplained.h" -#elif BOARD == STK600_RCUC3B0 -# include "stk600/rcuc3b0/stk600_rcuc3b0.h" -#elif BOARD == STK600_RCUC3D -# include "stk600/rcuc3d/stk600_rcuc3d.h" -#elif BOARD == STK600_RCUC3C0 -# include "stk600/rcuc3c0/stk600_rcuc3c0.h" -#elif BOARD == SAMG53_XPLAINED_PRO -# include "samg53_xplained_pro/samg53_xplained_pro.h" -#elif BOARD == SAMG55_XPLAINED_PRO -# include "samg55_xplained_pro/samg55_xplained_pro.h" -#elif BOARD == XMEGA_B1_XPLAINED -# include "xmega_b1_xplained/xmega_b1_xplained.h" -#elif BOARD == STK600_RC064X_LCDX -# include "stk600/rc064x_lcdx/stk600_rc064x_lcdx.h" -#elif BOARD == STK600_RC100X_LCDX -# include "stk600/rc100x_lcdx/stk600_rc100x_lcdx.h" -#elif BOARD == XMEGA_A1_XPLAINED -# include "xmega_a1_xplained/xmega_a1_xplained.h" -#elif BOARD == XMEGA_A1U_XPLAINED_PRO -# include "xmega_a1u_xplained_pro/xmega_a1u_xplained_pro.h" -#elif BOARD == UC3_L0_XPLAINED_BC -# include "uc3_l0_xplained_bc/uc3_l0_xplained_bc.h" -#elif BOARD == SAM3S_EK -# include "sam3s_ek/sam3s_ek.h" -# include "system_sam3s.h" -#elif BOARD == SAM3S_EK2 -# include "sam3s_ek2/sam3s_ek2.h" -# include "system_sam3sd8.h" -#elif BOARD == SAM3U_EK -# include "sam3u_ek/sam3u_ek.h" -# include "system_sam3u.h" -#elif BOARD == SAM3X_EK -# include "sam3x_ek/sam3x_ek.h" -# include "system_sam3x.h" -#elif BOARD == SAM3N_EK -# include "sam3n_ek/sam3n_ek.h" -# include "system_sam3n.h" -#elif BOARD == SAM4S_EK -# include "sam4s_ek/sam4s_ek.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_WPIR_RD -# include "sam4s_wpir_rd/sam4s_wpir_rd.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_XPLAINED -# include "sam4s_xplained/sam4s_xplained.h" -# include "system_sam4s.h" -#elif BOARD == SAM4S_EK2 -# include "sam4s_ek2/sam4s_ek2.h" -# include "system_sam4s.h" -#elif BOARD == MEGA_1284P_XPLAINED - /*No header-file to include*/ -#elif BOARD == ARDUINO_DUE_X -# include "arduino_due_x/arduino_due_x.h" -# include "system_sam3x.h" -#elif BOARD == SAM4L_EK -# include "sam4l_ek/sam4l_ek.h" -#elif BOARD == SAM4E_EK -# include "sam4e_ek/sam4e_ek.h" -#elif BOARD == SAMD20_XPLAINED_PRO -# include "samd20_xplained_pro/samd20_xplained_pro.h" -#elif BOARD == SAMD21_XPLAINED_PRO -# include "samd21_xplained_pro/samd21_xplained_pro.h" -#elif BOARD == SAMR21_XPLAINED_PRO -# include "samr21_xplained_pro/samr21_xplained_pro.h" -#elif BOARD == SAMR30_XPLAINED_PRO -# include "samr30_xplained_pro/samr30_xplained_pro.h" -#elif BOARD == SAMR21ZLL_EK -# include "samr21zll_ek/samr21zll_ek.h" -#elif BOARD == SAMD11_XPLAINED_PRO -# include "samd11_xplained_pro/samd11_xplained_pro.h" -#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18A__) -# include "saml21_xplained_pro/saml21_xplained_pro.h" -#elif BOARD == SAML22_XPLAINED_PRO -# include "saml22_xplained_pro/saml22_xplained_pro.h" -#elif BOARD == SAML22_XPLAINED_PRO_B -# include "saml22_xplained_pro_b/saml22_xplained_pro_b.h" -#elif BOARD == SAML21_XPLAINED_PRO && defined(__SAML21J18B__) -# include "saml21_xplained_pro_b/saml21_xplained_pro.h" -#elif BOARD == SAMD10_XPLAINED_MINI -# include "samd10_xplained_mini/samd10_xplained_mini.h" -#elif BOARD == SAMDA1_XPLAINED_PRO -# include "samda1_xplained_pro/samda1_xplained_pro.h" -#elif BOARD == SAMC21_XPLAINED_PRO -# include "samc21_xplained_pro/samc21_xplained_pro.h" -#elif BOARD == SAM4N_XPLAINED_PRO -# include "sam4n_xplained_pro/sam4n_xplained_pro.h" -#elif BOARD == SAMW25_XPLAINED_PRO -# include "samw25_xplained_pro/samw25_xplained_pro.h" -#elif BOARD == SAMV71_XPLAINED_ULTRA -# include "samv71_xplained_ultra/samv71_xplained_ultra.h" -#elif BOARD == MEGA1284P_XPLAINED_BC -# include "mega1284p_xplained_bc/mega1284p_xplained_bc.h" -#elif BOARD == UC3_L0_QT600 -# include "uc3_l0_qt600/uc3_l0_qt600.h" -#elif BOARD == XMEGA_A3BU_XPLAINED -# include "xmega_a3bu_xplained/xmega_a3bu_xplained.h" -#elif BOARD == XMEGA_E5_XPLAINED -# include "xmega_e5_xplained/xmega_e5_xplained.h" -#elif BOARD == UC3B_BOARD_CONTROLLER -# include "uc3b_board_controller/uc3b_board_controller.h" -#elif BOARD == RZ600 -# include "rz600/rz600.h" -#elif BOARD == STK600_RCUC3A0 -# include "stk600/rcuc3a0/stk600_rcuc3a0.h" -#elif BOARD == ATXMEGA128A1_QT600 -# include "atxmega128a1_qt600/atxmega128a1_qt600.h" -#elif BOARD == STK600_RCUC3L3 -# include "stk600/rcuc3l3/stk600_rcuc3l3.h" -#elif BOARD == SAM4S_XPLAINED_PRO -# include "sam4s_xplained_pro/sam4s_xplained_pro.h" -#elif BOARD == SAM4L_XPLAINED_PRO -# include "sam4l_xplained_pro/sam4l_xplained_pro.h" -#elif BOARD == SAM4L8_XPLAINED_PRO -# include "sam4l8_xplained_pro/sam4l8_xplained_pro.h" -#elif BOARD == SAM4C_EK -# include "sam4c_ek/sam4c_ek.h" -#elif BOARD == SAM4CMP_DB -# include "sam4cmp_db/sam4cmp_db.h" -#elif BOARD == SAM4CMS_DB -# include "sam4cms_db/sam4cms_db.h" -#elif BOARD == SAM4CP16BMB -# include "sam4cp16bmb/sam4cp16bmb.h" -#elif BOARD == ATPL230AMB -# include "atpl230amb/atpl230amb.h" -#elif BOARD == XMEGA_C3_XPLAINED -# include "xmega_c3_xplained/xmega_c3_xplained.h" -#elif BOARD == XMEGA_RF233_ZIGBIT -# include "xmega_rf233_zigbit/xmega_rf233_zigbit.h" -#elif BOARD == XMEGA_A3_REB_CBB -# include "xmega_a3_reb_cbb/xmega_a3_reb_cbb.h" -#elif BOARD == ATMEGARFX_RCB -# include "atmegarfx_rcb/atmegarfx_rcb.h" -#elif BOARD == RCB256RFR2_XPRO -# include "atmega256rfr2_rcb_xpro/atmega256rfr2_rcb_xpro.h" -#elif BOARD == XMEGA_RF212B_ZIGBIT -# include "xmega_rf212b_zigbit/xmega_rf212b_zigbit.h" -#elif BOARD == SAM4E_XPLAINED_PRO -# include "sam4e_xplained_pro/sam4e_xplained_pro.h" -#elif BOARD == ATMEGA328P_XPLAINED_MINI -# include "atmega328p_xplained_mini/atmega328p_xplained_mini.h" -#elif BOARD == ATMEGA328PB_XPLAINED_MINI -# include "atmega328pb_xplained_mini/atmega328pb_xplained_mini.h" -#elif BOARD == SAMB11_XPLAINED_PRO -# include "samb11_xplained_pro/samb11_xplained_pro.h" -#elif BOARD == SAME70_XPLAINED -# include "same70_xplained/same70_xplained.h" -#elif BOARD == ATMEGA168PB_XPLAINED_MINI -# include "atmega168pb_xplained_mini/atmega168pb_xplained_mini.h" -#elif BOARD == ATMEGA324PB_XPLAINED_PRO -# include "atmega324pb_xplained_pro/atmega324pb_xplained_pro.h" -#elif BOARD == SAMB11CSP_XPLAINED_PRO -# include "samb11csp_xplained_pro/samb11csp_xplained_pro.h" -#elif BOARD == SAMB11ZR_XPLAINED_PRO -# include "samb11zr_xplained_pro/samb11zr_xplained_pro.h" -#elif BOARD == SIMULATOR_XMEGA_A1 -# include "simulator/xmega_a1/simulator_xmega_a1.h" -#elif BOARD == AVR_SIMULATOR_UC3 -# include "avr_simulator_uc3/avr_simulator_uc3.h" -#elif BOARD == USER_BOARD - // User-reserved area: #include the header file of your board here (if any). -# include "user_board.h" -#elif BOARD == DUMMY_BOARD -# include "dummy/dummy_board.h" -#else -# error No known Atmel board defined -#endif - -#if (defined EXT_BOARD) -# if EXT_BOARD == MC300 -# include "mc300/mc300.h" -# elif (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_2) || \ - (EXT_BOARD == SENSORS_XPLAINED_INERTIAL_A1) || \ - (EXT_BOARD == SENSORS_XPLAINED_PRESSURE_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_LIGHTPROX_1) || \ - (EXT_BOARD == SENSORS_XPLAINED_BREADBOARD) -# include "sensors_xplained/sensors_xplained.h" -# elif EXT_BOARD == RZ600_AT86RF231 -# include "at86rf231/at86rf231.h" -# elif EXT_BOARD == RZ600_AT86RF230B -# include "at86rf230b/at86rf230b.h" -# elif EXT_BOARD == RZ600_AT86RF212 -# include "at86rf212/at86rf212.h" -# elif EXT_BOARD == SECURITY_XPLAINED -# include "security_xplained.h" -# elif EXT_BOARD == USER_EXT_BOARD - // User-reserved area: #include the header file of your extension board here - // (if any). -# endif -#endif - - -#if (defined(__GNUC__) && defined(__AVR32__)) || (defined(__ICCAVR32__) || defined(__AAVR32__)) -#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. - -/*! \brief This function initializes the board target resources - * - * This function should be called to ensure proper initialization of the target - * board hardware connected to the part. - */ -extern void board_init(void); - -#endif // #ifdef __AVR32_ABI_COMPILER__ -#else -/*! \brief This function initializes the board target resources - * - * This function should be called to ensure proper initialization of the target - * board hardware connected to the part. - */ -extern void board_init(void); -#endif - - -#ifdef __cplusplus -} -#endif - -/** - * \} - */ - -#endif // _BOARD_H_ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_0/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_0/doxyfile.doxygen deleted file mode 100644 index e01ab10c2ced8..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_0/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../uc3/sleepmgr.c ../../sleepmgr.h ../../uc3/sleepmgr.h ../../uc3/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_0/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_0/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_0/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_1/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_1/doxyfile.doxygen deleted file mode 100644 index 992c4136cba1f..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_1/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Sleep manager - XMEGA A/AU/B/D implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../xmega/sleepmgr.c ../../sleepmgr.h ../../xmega/sleepmgr.h ../../xmega/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_1/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_1/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_1/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_2/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_2/doxyfile.doxygen deleted file mode 100644 index 7d8b6d3ec45e2..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_2/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Sleep manager - SAM implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../sam/sleepmgr.c ../../sam/sleepmgr.h ../../sleepmgr.h ../../sam/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_2/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_2/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_2/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_3/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_3/doxyfile.doxygen deleted file mode 100644 index def59a226abdf..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_3/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Sleep manager - SAM4L implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../sam4l/sleepmgr.c ../../sam4l/sleepmgr.h ../../sleepmgr.h ../../sam4l/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_3/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_3/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_3/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_4/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_4/doxyfile.doxygen deleted file mode 100644 index c3a777a9a6a48..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_4/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Sleep manager - MEGARF implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../mega/sleepmgr.c ../../mega/sleepmgr.h ../../sleepmgr.h ../../mega/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_4/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_4/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_4/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_5/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_5/doxyfile.doxygen deleted file mode 100644 index f5416f10466f4..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_5/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Sleep manager - SAMD implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../samd/sleepmgr.c ../../samd/sleepmgr.h ../../sleepmgr.h ../../samd/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_5/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_5/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_5/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_6/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_6/doxyfile.doxygen deleted file mode 100644 index 16452f7377f8f..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_6/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Sleep manager - SAML implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../saml/sleepmgr.c ../../saml/sleepmgr.h ../../sleepmgr.h ../../saml/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_6/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_6/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_6/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_7/doxyfile.doxygen b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_7/doxyfile.doxygen deleted file mode 100644 index 6bc656537cf33..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_7/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Sleep manager - SAMC implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../samc/sleepmgr.c ../../samc/sleepmgr.h ../../sleepmgr.h ../../samc/module_config/conf_sleepmgr.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_7/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_7/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/doxygen/common.services.basic.sleepmgr_7/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/sleepmgr/mega/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/mega/module_config/conf_sleepmgr.h deleted file mode 100644 index ef326f4d82c68..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/mega/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_H -#define CONF_SLEEPMGR_H - -/* Sleep manager options */ -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/sleepmgr/mega/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/mega/sleepmgr.c deleted file mode 100644 index e506f96ce0ce9..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/mega/sleepmgr.c +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief Sleep manager - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -enum SLEEP_SMODE_enum sleepmgr_configs[SLEEPMGR_NR_OF_MODES] = { - SLEEP_SMODE_IDLE, - SLEEP_SMODE_ADC_NOISE_REDUCTION, - SLEEP_SMODE_ESTDBY, - SLEEP_SMODE_PSAVE, - SLEEP_SMODE_STDBY, - SLEEP_SMODE_PDOWN, -}; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/mega/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/mega/sleepmgr.h deleted file mode 100644 index cd451b9703913..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/mega/sleepmgr.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - * \file - * - * \brief AVR MEGA Sleep manager implementation - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef MEGA_SLEEPMGR_H -#define MEGA_SLEEPMGR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -# include - -/** - * \weakgroup sleepmgr_group - * @{ - */ - -enum sleepmgr_mode { - /* Active mode. */ - SLEEPMGR_ACTIVE = 0, - /* Idle mode. */ - SLEEPMGR_IDLE, - /* ADC Noise reduction mode. */ - SLEEPMGR_ADC_NOISE_REDUCTION, - /* Extended Standby mode. */ - SLEEPMGR_ESTDBY, - /* Power Save mode. */ - SLEEPMGR_PSAVE, - /* Standby mode. */ - SLEEPMGR_STDBY, - /* Power Down mode. */ - SLEEPMGR_PDOWN, - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -/* ! Sleep mode lock counters */ -extern uint8_t sleepmgr_locks[]; - -/** - * \brief Look-up table with sleep mode configurations - * \note This is located in program memory (Flash) as it is constant. - */ -extern enum SLEEP_SMODE_enum sleepmgr_configs[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -/* ! @} */ - -/** - * \brief Enter the sleep with interrupt enabled - * - * \param mode Sleep mode to be entered - */ -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - sleep_set_mode(sleepmgr_configs[sleep_mode - 1]); - sleep_enable(); - - cpu_irq_enable(); - sleep_enter(); - - sleep_disable(); -#else - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/* ! @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* MEGA_SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h deleted file mode 100644 index 0f6efbc456f03..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/sam/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_H -#define CONF_SLEEPMGR_H - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/sleepmgr/sam/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/sam/sleepmgr.c deleted file mode 100644 index 8531f56163ab4..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/sam/sleepmgr.c +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief SAM3/SAM4 Sleep manager implementation. - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/sam/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/sam/sleepmgr.h deleted file mode 100644 index a39bfd32fbe4c..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/sam/sleepmgr.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - * \file - * - * \brief SAM3/SAM4 Sleep manager implementation. - * - * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAM_SLEEPMGR_INCLUDED -#define SAM_SLEEPMGR_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include - -/** - * \weakgroup sleepmgr_group - * @{ - */ -enum sleepmgr_mode { - //! Active mode. - SLEEPMGR_ACTIVE = 0, - /*! WFE sleep mode. - * Potential Wake Up sources: - * fast startup events (USB, RTC, RTT, WKUPs), - * interrupt, and events. */ - SLEEPMGR_SLEEP_WFE, - /*! WFI sleep mode. - * Potential Wake Up sources: fast startup events and interrupt. */ - SLEEPMGR_SLEEP_WFI, - /*! Wait mode, wakeup fast (in 3ms). - * XTAL is not disabled when sleep. - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT_FAST, - /*! Wait mode. - * Potential Wake Up sources: fast startup events */ - SLEEPMGR_WAIT, -#if (!(SAMG51 || SAMG53 || SAMG54)) - //! Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC. - SLEEPMGR_BACKUP, -#endif - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -//! Sleep mode lock counters -extern uint8_t sleepmgr_locks[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -//! @} - - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - cpu_irq_disable(); - - // Atomically enable the global interrupts and enter the sleep mode. - pmc_sleep(sleep_mode); -#else - UNUSED(sleep_mode); - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ - -} - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/sam4l/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/sam4l/module_config/conf_sleepmgr.h deleted file mode 100644 index 2ccd8b3f7f67a..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/sam4l/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_INCLUDED -#define CONF_SLEEPMGR_INCLUDED - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/sam4l/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/sam4l/sleepmgr.c deleted file mode 100644 index 4da613c849d77..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/sam4l/sleepmgr.c +++ /dev/null @@ -1,53 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/sam4l/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/sam4l/sleepmgr.h deleted file mode 100644 index 8d3b08de76013..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/sam4l/sleepmgr.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAM_SLEEPMGR_INCLUDED -#define SAM_SLEEPMGR_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include "bpm.h" - -/** - * \weakgroup sleepmgr_group - * @{ - */ - -enum sleepmgr_mode { - /** Active mode. */ - SLEEPMGR_ACTIVE = 0, - - /** - * Sleep mode. - * Potential Wake Up sources: fast startup events and interrupt. - */ - SLEEPMGR_SLEEP_0, - SLEEPMGR_SLEEP_1, - SLEEPMGR_SLEEP_2, - SLEEPMGR_SLEEP_3, - - /** - * Wait mode. - * Potential Wake Up sources: fast startup events - */ - SLEEPMGR_WAIT, - - /** - * Retention mode. - * Potential Wake Up sources: fast startup events - */ - SLEEPMGR_RET, - - /** Backup mode. Potential Wake Up sources: WKUPs, SM, RTT, RTC. */ - SLEEPMGR_BACKUP, - - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -/** Sleep mode lock counters */ -extern uint8_t sleepmgr_locks[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -/** @} */ - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - cpu_irq_disable(); - - /* Enter the sleep mode. */ - bpm_sleep(BPM, sleep_mode); -#else - UNUSED(sleep_mode); - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/samc/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/samc/module_config/conf_sleepmgr.h deleted file mode 100644 index 0a22e0bcfe0ea..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/samc/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef CONF_SLEEPMGR_INCLUDED -#define CONF_SLEEPMGR_INCLUDED - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/samc/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/samc/sleepmgr.c deleted file mode 100644 index 05af08c95a72a..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/samc/sleepmgr.c +++ /dev/null @@ -1,50 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/samc/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/samc/sleepmgr.h deleted file mode 100644 index 28494c6723ec0..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/samc/sleepmgr.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef SAM_SLEEPMGR_INCLUDED -#define SAM_SLEEPMGR_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include "system.h" - -/** - * \weakgroup sleepmgr_group - * @{ - */ - -enum sleepmgr_mode { - /** Active mode. */ - SLEEPMGR_ACTIVE = 0, - - /** - * Idle 0 mode. - * Potential Wake Up sources: IRQ. - */ - SLEEPMGR_IDLE_0, - - /** - * Idle 1 mode. - * Potential Wake Up sources: IRQ. - */ - SLEEPMGR_IDLE_1, - - /** - * Idle 2 mode. - * Potential Wake Up sources: IRQ. - */ - SLEEPMGR_IDLE_2, - - /** - * Standby mode. - * Potential Wake Up sources: Asynchronous IRQ (or Sync IRQ in APB sleep-walking). - */ - SLEEPMGR_STANDBY, - - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -/** Sleep mode lock counters */ -extern uint8_t sleepmgr_locks[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -/** @} */ - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - cpu_irq_disable(); - - /* Enter the sleep mode. */ - switch (sleep_mode) { - case SLEEPMGR_IDLE_0: - system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE_0); - cpu_irq_enable(); - system_sleep(); - break; - case SLEEPMGR_IDLE_1: - system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE_1); - cpu_irq_enable(); - system_sleep(); - break; - case SLEEPMGR_IDLE_2: - system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE_2); - cpu_irq_enable(); - system_sleep(); - break; - case SLEEPMGR_STANDBY: - system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY); - cpu_irq_enable(); - system_sleep(); - break; - default: - cpu_irq_enable(); - break; - } -#else - UNUSED(sleep_mode); - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h deleted file mode 100644 index 2ccd8b3f7f67a..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/samd/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_INCLUDED -#define CONF_SLEEPMGR_INCLUDED - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/samd/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/samd/sleepmgr.c deleted file mode 100644 index 4da613c849d77..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/samd/sleepmgr.c +++ /dev/null @@ -1,53 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/samd/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/samd/sleepmgr.h deleted file mode 100644 index 8cb94ddb5b004..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/samd/sleepmgr.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAM_SLEEPMGR_INCLUDED -#define SAM_SLEEPMGR_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include "system.h" - -/** - * \weakgroup sleepmgr_group - * @{ - */ - -enum sleepmgr_mode { - /** Active mode. */ - SLEEPMGR_ACTIVE = 0, - - /** - * Idle 0 mode. - * Potential Wake Up sources: Synchronous(APB, AHB), asynchronous. - */ - SLEEPMGR_IDLE_0, - - /** - * Idle 1 mode. - * Potential Wake Up sources: Synchronous (APB), asynchronous - */ - SLEEPMGR_IDLE_1, - - /** - * Idle 2 mode. - * Potential Wake Up sources: Asynchronous - */ - SLEEPMGR_IDLE_2, - - /** - * Standby mode. - * Potential Wake Up sources: Asynchronous - */ - SLEEPMGR_STANDBY, - - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -/** Sleep mode lock counters */ -extern uint8_t sleepmgr_locks[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -/** @} */ - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - cpu_irq_disable(); - - /* Enter the sleep mode. */ - system_set_sleepmode((enum system_sleepmode)(sleep_mode - 1)); - cpu_irq_enable(); - system_sleep(); -#else - UNUSED(sleep_mode); - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/saml/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/saml/module_config/conf_sleepmgr.h deleted file mode 100644 index 2ccd8b3f7f67a..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/saml/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_INCLUDED -#define CONF_SLEEPMGR_INCLUDED - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/saml/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/saml/sleepmgr.c deleted file mode 100644 index 4da613c849d77..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/saml/sleepmgr.c +++ /dev/null @@ -1,53 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/saml/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/saml/sleepmgr.h deleted file mode 100644 index 105421ff7806b..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/saml/sleepmgr.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SAM_SLEEPMGR_INCLUDED -#define SAM_SLEEPMGR_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include "system.h" - -/** - * \weakgroup sleepmgr_group - * @{ - */ - -enum sleepmgr_mode { - /** Active mode. */ - SLEEPMGR_ACTIVE = 0, - - /** - * Idle mode. - * Potential Wake Up sources: Synchronous(APB, AHB), asynchronous. - */ - SLEEPMGR_IDLE, - - /** - * Standby mode. - * Potential Wake Up sources: Asynchronous. - */ - SLEEPMGR_STANDBY, - - /** - * Backup mode. - * Potential Wake Up sources: Backup reset detected by the RSTC. - */ - SLEEPMGR_BACKUP, - - /** - * Off mode. - * Potential Wake Up sources: External reset. - */ - SLEEPMGR_OFF, - - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -/** Sleep mode lock counters */ -extern uint8_t sleepmgr_locks[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -/** @} */ - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - cpu_irq_disable(); - - /* Enter the sleep mode. */ - switch (sleep_mode) { - case SLEEPMGR_IDLE: - system_set_sleepmode(SYSTEM_SLEEPMODE_IDLE); - cpu_irq_enable(); - system_sleep(); - break; - case SLEEPMGR_STANDBY: - system_set_sleepmode(SYSTEM_SLEEPMODE_STANDBY); - cpu_irq_enable(); - system_sleep(); - break; - case SLEEPMGR_BACKUP: - system_set_sleepmode(SYSTEM_SLEEPMODE_BACKUP); - cpu_irq_enable(); - system_sleep(); - break; - case SLEEPMGR_OFF: - system_set_sleepmode(SYSTEM_SLEEPMODE_OFF); - cpu_irq_enable(); - system_sleep(); - break; - default: - cpu_irq_enable(); - break; - } -#else - UNUSED(sleep_mode); - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* SAM_SLEEPMGR_INCLUDED */ diff --git a/atmel-samd/asf/common/services/sleepmgr/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/sleepmgr.h deleted file mode 100644 index ae38de13611b3..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/sleepmgr.h +++ /dev/null @@ -1,273 +0,0 @@ -/** - * \file - * - * \brief Sleep manager - * - * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SLEEPMGR_H -#define SLEEPMGR_H - -#include -#include - -#if (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4E || SAM4N || SAM4C || SAMG || SAM4CP || SAM4CM || SAMV71 || SAMV70 || SAMS70 || SAME70) -# include "sam/sleepmgr.h" -#elif XMEGA -# include "xmega/sleepmgr.h" -#elif UC3 -# include "uc3/sleepmgr.h" -#elif SAM4L -# include "sam4l/sleepmgr.h" -#elif MEGA -# include "mega/sleepmgr.h" -#elif (SAMD20 || SAMD21 || SAMR21 || SAMD11 || SAMDA1) -# include "samd/sleepmgr.h" -#elif (SAML21 || SAML22 || SAMR30) -# include "saml/sleepmgr.h" -#elif (SAMC21) -# include "samc/sleepmgr.h" -#else -# error Unsupported device. -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup sleepmgr_group Sleep manager - * - * The sleep manager is a service for ensuring that the device is not put to - * sleep in deeper sleep modes than the system (e.g., peripheral drivers, - * services or the application) allows at any given time. - * - * It is based on the use of lock counting for the individual sleep modes, and - * will put the device to sleep in the shallowest sleep mode that has a non-zero - * lock count. The drivers/services/application can change these counts by use - * of \ref sleepmgr_lock_mode and \ref sleepmgr_unlock_mode. - * Refer to \ref sleepmgr_mode for a list of the sleep modes available for - * locking, and the device datasheet for information on their effect. - * - * The application must supply the file \ref conf_sleepmgr.h. - * - * For the sleep manager to be enabled, the symbol \ref CONFIG_SLEEPMGR_ENABLE - * must be defined, e.g., in \ref conf_sleepmgr.h. If this symbol is not - * defined, the functions are replaced with dummy functions and no RAM is used. - * - * @{ - */ - -/** - * \def CONFIG_SLEEPMGR_ENABLE - * \brief Configuration symbol for enabling the sleep manager - * - * If this symbol is not defined, the functions of this service are replaced - * with dummy functions. This is useful for reducing code size and execution - * time if the sleep manager is not needed in the application. - * - * This symbol may be defined in \ref conf_sleepmgr.h. - */ -#if defined(__DOXYGEN__) && !defined(CONFIG_SLEEPMGR_ENABLE) -# define CONFIG_SLEEPMGR_ENABLE -#endif - -/** - * \enum sleepmgr_mode - * \brief Sleep mode locks - * - * Identifiers for the different sleep mode locks. - */ - -/** - * \brief Initialize the lock counts - * - * Sets all lock counts to 0, except the very last one, which is set to 1. This - * is done to simplify the algorithm for finding the deepest allowable sleep - * mode in \ref sleepmgr_enter_sleep. - */ -static inline void sleepmgr_init(void) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - uint8_t i; - - for (i = 0; i < SLEEPMGR_NR_OF_MODES - 1; i++) { - sleepmgr_locks[i] = 0; - } - sleepmgr_locks[SLEEPMGR_NR_OF_MODES - 1] = 1; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** - * \brief Increase lock count for a sleep mode - * - * Increases the lock count for \a mode to ensure that the sleep manager does - * not put the device to sleep in the deeper sleep modes. - * - * \param mode Sleep mode to lock. - */ -static inline void sleepmgr_lock_mode(enum sleepmgr_mode mode) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - irqflags_t flags; - - if(sleepmgr_locks[mode] >= 0xff) { - while (true) { - // Warning: maximum value of sleepmgr_locks buffer is no more than 255. - // Check APP or change the data type to uint16_t. - } - } - - // Enter a critical section - flags = cpu_irq_save(); - - ++sleepmgr_locks[mode]; - - // Leave the critical section - cpu_irq_restore(flags); -#else - UNUSED(mode); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - -/** - * \brief Decrease lock count for a sleep mode - * - * Decreases the lock count for \a mode. If the lock count reaches 0, the sleep - * manager can put the device to sleep in the deeper sleep modes. - * - * \param mode Sleep mode to unlock. - */ -static inline void sleepmgr_unlock_mode(enum sleepmgr_mode mode) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - irqflags_t flags; - - if(sleepmgr_locks[mode] == 0) { - while (true) { - // Warning: minimum value of sleepmgr_locks buffer is no less than 0. - // Check APP. - } - } - - // Enter a critical section - flags = cpu_irq_save(); - - --sleepmgr_locks[mode]; - - // Leave the critical section - cpu_irq_restore(flags); -#else - UNUSED(mode); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - - /** - * \brief Retrieves the deepest allowable sleep mode - * - * Searches through the sleep mode lock counts, starting at the shallowest sleep - * mode, until the first non-zero lock count is found. The deepest allowable - * sleep mode is then returned. - */ -static inline enum sleepmgr_mode sleepmgr_get_sleep_mode(void) -{ - enum sleepmgr_mode sleep_mode = SLEEPMGR_ACTIVE; - -#ifdef CONFIG_SLEEPMGR_ENABLE - uint8_t *lock_ptr = sleepmgr_locks; - - // Find first non-zero lock count, starting with the shallowest modes. - while (!(*lock_ptr)) { - lock_ptr++; - sleep_mode = (enum sleepmgr_mode)(sleep_mode + 1); - } - - // Catch the case where one too many sleepmgr_unlock_mode() call has been - // performed on the deepest sleep mode. - Assert((uintptr_t)(lock_ptr - sleepmgr_locks) < SLEEPMGR_NR_OF_MODES); - -#endif /* CONFIG_SLEEPMGR_ENABLE */ - - return sleep_mode; -} - -/** - * \fn sleepmgr_enter_sleep - * \brief Go to sleep in the deepest allowed mode - * - * Searches through the sleep mode lock counts, starting at the shallowest sleep - * mode, until the first non-zero lock count is found. The device is then put to - * sleep in the sleep mode that corresponds to the lock. - * - * \note This function enables interrupts before going to sleep, and will leave - * them enabled upon return. This also applies if sleep is skipped due to ACTIVE - * mode being locked. - */ - -static inline void sleepmgr_enter_sleep(void) -{ -#ifdef CONFIG_SLEEPMGR_ENABLE - enum sleepmgr_mode sleep_mode; - - cpu_irq_disable(); - - // Find the deepest allowable sleep mode - sleep_mode = sleepmgr_get_sleep_mode(); - // Return right away if first mode (ACTIVE) is locked. - if (sleep_mode==SLEEPMGR_ACTIVE) { - cpu_irq_enable(); - return; - } - // Enter the deepest allowable sleep mode with interrupts enabled - sleepmgr_sleep(sleep_mode); -#else - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ -} - - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/sleepmgr/uc3/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/uc3/module_config/conf_sleepmgr.h deleted file mode 100644 index e68e013213da5..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/uc3/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_H -#define CONF_SLEEPMGR_H - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/sleepmgr/uc3/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/uc3/sleepmgr.c deleted file mode 100644 index b527f18f9d83d..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/uc3/sleepmgr.c +++ /dev/null @@ -1,53 +0,0 @@ -/** - * \file - * - * \brief AVR UC3 Sleep manager implementation - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/uc3/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/uc3/sleepmgr.h deleted file mode 100644 index 5fc0c0ae84ad5..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/uc3/sleepmgr.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * \file - * - * \brief AVR UC3 Sleep manager implementation - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UC3_SLEEPMGR_H -#define UC3_SLEEPMGR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \weakgroup sleepmgr_group - * @{ - */ - -enum sleepmgr_mode { - //! Active mode. - SLEEPMGR_ACTIVE = 0, - //! Idle mode. - SLEEPMGR_IDLE, - //! Frozen mode. - SLEEPMGR_FROZEN, - //! Standby mode. - SLEEPMGR_STDBY, - //! Stop mode. - SLEEPMGR_STOP, - //! Deep Stop mode. - SLEEPMGR_DEEPSTOP, - //! Static mode. - SLEEPMGR_STATIC, -#if UC3L - //! Shutdown mode. - SLEEPMGR_SHUTDOWN, -#endif - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -//! Sleep mode lock counters -extern uint8_t sleepmgr_locks[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -//! @} - - - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - cpu_irq_disable(); - - // Atomically enable the global interrupts and enter the sleep mode. - pm_sleep(AVR32_PM_SMODE_GMCLEAR_MASK | (sleep_mode-1)); -#else - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ - -} - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* UC3_SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/sleepmgr/xmega/module_config/conf_sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/xmega/module_config/conf_sleepmgr.h deleted file mode 100644 index e68e013213da5..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/xmega/module_config/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Chip-specific sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_SLEEPMGR_H -#define CONF_SLEEPMGR_H - -// Sleep manager options -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/sleepmgr/xmega/sleepmgr.c b/atmel-samd/asf/common/services/sleepmgr/xmega/sleepmgr.c deleted file mode 100644 index 0877e284b4e07..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/xmega/sleepmgr.c +++ /dev/null @@ -1,61 +0,0 @@ -/** - * \file - * - * \brief Sleep manager - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include - -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) - -uint8_t sleepmgr_locks[SLEEPMGR_NR_OF_MODES]; - -enum SLEEP_SMODE_enum sleepmgr_configs[SLEEPMGR_NR_OF_MODES] = { - SLEEP_SMODE_IDLE_gc, - SLEEP_SMODE_ESTDBY_gc, - SLEEP_SMODE_PSAVE_gc, - SLEEP_SMODE_STDBY_gc, - SLEEP_SMODE_PDOWN_gc, -}; - -#endif /* CONFIG_SLEEPMGR_ENABLE */ diff --git a/atmel-samd/asf/common/services/sleepmgr/xmega/sleepmgr.h b/atmel-samd/asf/common/services/sleepmgr/xmega/sleepmgr.h deleted file mode 100644 index 7ca322738b55b..0000000000000 --- a/atmel-samd/asf/common/services/sleepmgr/xmega/sleepmgr.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * \file - * - * \brief AVR XMEGA Sleep manager implementation - * - * Copyright (c) 2010-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef XMEGA_SLEEPMGR_H -#define XMEGA_SLEEPMGR_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \weakgroup sleepmgr_group - * @{ - */ - -enum sleepmgr_mode { - //! Active mode. - SLEEPMGR_ACTIVE = 0, - //! Idle mode. - SLEEPMGR_IDLE, - //! Extended Standby mode. - SLEEPMGR_ESTDBY, - //! Power Save mode. - SLEEPMGR_PSAVE, - //! Standby mode. - SLEEPMGR_STDBY, - //! Power Down mode. - SLEEPMGR_PDOWN, - SLEEPMGR_NR_OF_MODES, -}; - -/** - * \internal - * \name Internal arrays - * @{ - */ -#if defined(CONFIG_SLEEPMGR_ENABLE) || defined(__DOXYGEN__) -//! Sleep mode lock counters -extern uint8_t sleepmgr_locks[]; -/** - * \brief Look-up table with sleep mode configurations - * \note This is located in program memory (Flash) as it is constant. - */ -extern enum SLEEP_SMODE_enum sleepmgr_configs[]; -#endif /* CONFIG_SLEEPMGR_ENABLE */ -//! @} - -static inline void sleepmgr_sleep(const enum sleepmgr_mode sleep_mode) -{ - Assert(sleep_mode != SLEEPMGR_ACTIVE); -#ifdef CONFIG_SLEEPMGR_ENABLE - sleep_set_mode(sleepmgr_configs[sleep_mode-1]); - sleep_enable(); - - cpu_irq_enable(); - sleep_enter(); - - sleep_disable(); -#else - cpu_irq_enable(); -#endif /* CONFIG_SLEEPMGR_ENABLE */ - -} - -//! @} - -#ifdef __cplusplus -} -#endif - -#endif /* XMEGA_SLEEPMGR_H */ diff --git a/atmel-samd/asf/common/services/storage/ctrl_access/ctrl_access.c b/atmel-samd/asf/common/services/storage/ctrl_access/ctrl_access.c deleted file mode 100644 index 9b3b52b703574..0000000000000 --- a/atmel-samd/asf/common/services/storage/ctrl_access/ctrl_access.c +++ /dev/null @@ -1,644 +0,0 @@ -/***************************************************************************** - * - * \file - * - * \brief Abstraction layer for memory interfaces. - * - * This module contains the interfaces: - * - MEM <-> USB; - * - MEM <-> RAM; - * - MEM <-> MEM. - * - * This module may be configured and expanded to support the following features: - * - write-protected globals; - * - password-protected data; - * - specific features; - * - etc. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - ******************************************************************************/ -/* - * Support and FAQ: visit Atmel Support - */ - - -//_____ I N C L U D E S ____________________________________________________ - -#include "compiler.h" -#include "preprocessor.h" -#ifdef FREERTOS_USED -#include "FreeRTOS.h" -#include "semphr.h" -#endif -#include "ctrl_access.h" - - -//_____ D E F I N I T I O N S ______________________________________________ - -#ifdef FREERTOS_USED - -/*! \name LUN Access Protection Macros - */ -//! @{ - -/*! \brief Locks accesses to LUNs. - * - * \return \c true if the access was successfully locked, else \c false. - */ -#define Ctrl_access_lock() ctrl_access_lock() - -/*! \brief Unlocks accesses to LUNs. - */ -#define Ctrl_access_unlock() xSemaphoreGive(ctrl_access_semphr) - -//! @} - -//! Handle to the semaphore protecting accesses to LUNs. -static xSemaphoreHandle ctrl_access_semphr = NULL; - -#else - -/*! \name LUN Access Protection Macros - */ -//! @{ - -/*! \brief Locks accesses to LUNs. - * - * \return \c true if the access was successfully locked, else \c false. - */ -#define Ctrl_access_lock() true - -/*! \brief Unlocks accesses to LUNs. - */ -#define Ctrl_access_unlock() - -//! @} - -#endif // FREERTOS_USED - - -#if MAX_LUN - -/*! \brief Initializes an entry of the LUN descriptor table. - * - * \param lun Logical Unit Number. - * - * \return LUN descriptor table entry initializer. - */ -#if ACCESS_USB == true && ACCESS_MEM_TO_RAM == true -#define Lun_desc_entry(lun) \ - {\ - TPASTE3(Lun_, lun, _test_unit_ready),\ - TPASTE3(Lun_, lun, _read_capacity),\ - TPASTE3(Lun_, lun, _unload),\ - TPASTE3(Lun_, lun, _wr_protect),\ - TPASTE3(Lun_, lun, _removal),\ - TPASTE3(Lun_, lun, _usb_read_10),\ - TPASTE3(Lun_, lun, _usb_write_10),\ - TPASTE3(Lun_, lun, _mem_2_ram),\ - TPASTE3(Lun_, lun, _ram_2_mem),\ - TPASTE3(LUN_, lun, _NAME)\ - } -#elif ACCESS_USB == true -#define Lun_desc_entry(lun) \ - {\ - TPASTE3(Lun_, lun, _test_unit_ready),\ - TPASTE3(Lun_, lun, _read_capacity),\ - TPASTE3(Lun_, lun, _unload),\ - TPASTE3(Lun_, lun, _wr_protect),\ - TPASTE3(Lun_, lun, _removal),\ - TPASTE3(Lun_, lun, _usb_read_10),\ - TPASTE3(Lun_, lun, _usb_write_10),\ - TPASTE3(LUN_, lun, _NAME)\ - } -#elif ACCESS_MEM_TO_RAM == true -#define Lun_desc_entry(lun) \ - {\ - TPASTE3(Lun_, lun, _test_unit_ready),\ - TPASTE3(Lun_, lun, _read_capacity),\ - TPASTE3(Lun_, lun, _unload),\ - TPASTE3(Lun_, lun, _wr_protect),\ - TPASTE3(Lun_, lun, _removal),\ - TPASTE3(Lun_, lun, _mem_2_ram),\ - TPASTE3(Lun_, lun, _ram_2_mem),\ - TPASTE3(LUN_, lun, _NAME)\ - } -#else -#define Lun_desc_entry(lun) \ - {\ - TPASTE3(Lun_, lun, _test_unit_ready),\ - TPASTE3(Lun_, lun, _read_capacity),\ - TPASTE3(Lun_, lun, _unload),\ - TPASTE3(Lun_, lun, _wr_protect),\ - TPASTE3(Lun_, lun, _removal),\ - TPASTE3(LUN_, lun, _NAME)\ - } -#endif - -//! LUN descriptor table. -static const struct -{ - Ctrl_status (*test_unit_ready)(void); - Ctrl_status (*read_capacity)(U32 *); - bool (*unload)(bool); - bool (*wr_protect)(void); - bool (*removal)(void); -#if ACCESS_USB == true - Ctrl_status (*usb_read_10)(U32, U16); - Ctrl_status (*usb_write_10)(U32, U16); -#endif -#if ACCESS_MEM_TO_RAM == true - Ctrl_status (*mem_2_ram)(U32, void *); - Ctrl_status (*ram_2_mem)(U32, const void *); -#endif - const char *name; -} lun_desc[MAX_LUN] = -{ -#if LUN_0 == ENABLE -# ifndef Lun_0_unload -# define Lun_0_unload NULL -# endif - Lun_desc_entry(0), -#endif -#if LUN_1 == ENABLE -# ifndef Lun_1_unload -# define Lun_1_unload NULL -# endif - Lun_desc_entry(1), -#endif -#if LUN_2 == ENABLE -# ifndef Lun_2_unload -# define Lun_2_unload NULL -# endif - Lun_desc_entry(2), -#endif -#if LUN_3 == ENABLE -# ifndef Lun_3_unload -# define Lun_3_unload NULL -# endif - Lun_desc_entry(3), -#endif -#if LUN_4 == ENABLE -# ifndef Lun_4_unload -# define Lun_4_unload NULL -# endif - Lun_desc_entry(4), -#endif -#if LUN_5 == ENABLE -# ifndef Lun_5_unload -# define Lun_5_unload NULL -# endif - Lun_desc_entry(5), -#endif -#if LUN_6 == ENABLE -# ifndef Lun_6_unload -# define Lun_6_unload NULL -# endif - Lun_desc_entry(6), -#endif -#if LUN_7 == ENABLE -# ifndef Lun_7_unload -# define Lun_7_unload NULL -# endif - Lun_desc_entry(7) -#endif -}; - -#endif - - -#if GLOBAL_WR_PROTECT == true -bool g_wr_protect; -#endif - - -/*! \name Control Interface - */ -//! @{ - - -#ifdef FREERTOS_USED - -bool ctrl_access_init(void) -{ - // If the handle to the protecting semaphore is not valid, - if (!ctrl_access_semphr) - { - // try to create the semaphore. - vSemaphoreCreateBinary(ctrl_access_semphr); - - // If the semaphore could not be created, there is no backup solution. - if (!ctrl_access_semphr) return false; - } - - return true; -} - - -/*! \brief Locks accesses to LUNs. - * - * \return \c true if the access was successfully locked, else \c false. - */ -static bool ctrl_access_lock(void) -{ - // If the semaphore could not be created, there is no backup solution. - if (!ctrl_access_semphr) return false; - - // Wait for the semaphore. - while (!xSemaphoreTake(ctrl_access_semphr, portMAX_DELAY)); - - return true; -} - -#endif // FREERTOS_USED - - -U8 get_nb_lun(void) -{ -#if MEM_USB == ENABLE -# ifndef Lun_usb_get_lun -# define Lun_usb_get_lun() host_get_lun() -# endif - U8 nb_lun; - - if (!Ctrl_access_lock()) return MAX_LUN; - - nb_lun = MAX_LUN + Lun_usb_get_lun(); - - Ctrl_access_unlock(); - - return nb_lun; -#else - return MAX_LUN; -#endif -} - - -U8 get_cur_lun(void) -{ - return LUN_ID_0; -} - - -Ctrl_status mem_test_unit_ready(U8 lun) -{ - Ctrl_status status; - - if (!Ctrl_access_lock()) return CTRL_FAIL; - - status = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].test_unit_ready() : -#endif -#if LUN_USB == ENABLE - Lun_usb_test_unit_ready(lun - LUN_ID_USB); -#else - CTRL_FAIL; -#endif - - Ctrl_access_unlock(); - - return status; -} - - -Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector) -{ - Ctrl_status status; - - if (!Ctrl_access_lock()) return CTRL_FAIL; - - status = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].read_capacity(u32_nb_sector) : -#endif -#if LUN_USB == ENABLE - Lun_usb_read_capacity(lun - LUN_ID_USB, u32_nb_sector); -#else - CTRL_FAIL; -#endif - - Ctrl_access_unlock(); - - return status; -} - - -U8 mem_sector_size(U8 lun) -{ - U8 sector_size; - - if (!Ctrl_access_lock()) return 0; - - sector_size = -#if MAX_LUN - (lun < MAX_LUN) ? 1 : -#endif -#if LUN_USB == ENABLE - Lun_usb_read_sector_size(lun - LUN_ID_USB); -#else - 0; -#endif - - Ctrl_access_unlock(); - - return sector_size; -} - - -bool mem_unload(U8 lun, bool unload) -{ - bool unloaded; -#if !MAX_LUN || !defined(Lun_usb_unload) - UNUSED(lun); -#endif - - if (!Ctrl_access_lock()) return false; - - unloaded = -#if MAX_LUN - (lun < MAX_LUN) ? - (lun_desc[lun].unload ? - lun_desc[lun].unload(unload) : !unload) : -#endif -#if LUN_USB == ENABLE -# if defined(Lun_usb_unload) - Lun_usb_unload(lun - LUN_ID_USB, unload); -# else - !unload; /* Can not unload: load success, unload fail */ -# endif -#else - false; /* No mem, unload/load fail */ -#endif - - Ctrl_access_unlock(); - - return unloaded; -} - -bool mem_wr_protect(U8 lun) -{ - bool wr_protect; - - if (!Ctrl_access_lock()) return true; - - wr_protect = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].wr_protect() : -#endif -#if LUN_USB == ENABLE - Lun_usb_wr_protect(lun - LUN_ID_USB); -#else - true; -#endif - - Ctrl_access_unlock(); - - return wr_protect; -} - - -bool mem_removal(U8 lun) -{ - bool removal; -#if MAX_LUN==0 - UNUSED(lun); -#endif - - if (!Ctrl_access_lock()) return true; - - removal = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].removal() : -#endif -#if LUN_USB == ENABLE - Lun_usb_removal(); -#else - true; -#endif - - Ctrl_access_unlock(); - - return removal; -} - - -const char *mem_name(U8 lun) -{ -#if MAX_LUN==0 - UNUSED(lun); -#endif - return -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].name : -#endif -#if LUN_USB == ENABLE - LUN_USB_NAME; -#else - NULL; -#endif -} - - -//! @} - - -#if ACCESS_USB == true - -/*! \name MEM <-> USB Interface - */ -//! @{ - - -Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector) -{ - Ctrl_status status; - - if (!Ctrl_access_lock()) return CTRL_FAIL; - - memory_start_read_action(nb_sector); - status = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].usb_read_10(addr, nb_sector) : -#endif - CTRL_FAIL; - memory_stop_read_action(); - - Ctrl_access_unlock(); - - return status; -} - - -Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector) -{ - Ctrl_status status; - - if (!Ctrl_access_lock()) return CTRL_FAIL; - - memory_start_write_action(nb_sector); - status = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].usb_write_10(addr, nb_sector) : -#endif - CTRL_FAIL; - memory_stop_write_action(); - - Ctrl_access_unlock(); - - return status; -} - - -//! @} - -#endif // ACCESS_USB == true - - -#if ACCESS_MEM_TO_RAM == true - -/*! \name MEM <-> RAM Interface - */ -//! @{ - - -Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram) -{ - Ctrl_status status; -#if MAX_LUN==0 - UNUSED(lun); -#endif - - if (!Ctrl_access_lock()) return CTRL_FAIL; - - memory_start_read_action(1); - status = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].mem_2_ram(addr, ram) : -#endif -#if LUN_USB == ENABLE - Lun_usb_mem_2_ram(addr, ram); -#else - CTRL_FAIL; -#endif - memory_stop_read_action(); - - Ctrl_access_unlock(); - - return status; -} - - -Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram) -{ - Ctrl_status status; -#if MAX_LUN==0 - UNUSED(lun); -#endif - - if (!Ctrl_access_lock()) return CTRL_FAIL; - - memory_start_write_action(1); - status = -#if MAX_LUN - (lun < MAX_LUN) ? lun_desc[lun].ram_2_mem(addr, ram) : -#endif -#if LUN_USB == ENABLE - Lun_usb_ram_2_mem(addr, ram); -#else - CTRL_FAIL; -#endif - memory_stop_write_action(); - - Ctrl_access_unlock(); - - return status; -} - - -//! @} - -#endif // ACCESS_MEM_TO_RAM == true - - -#if ACCESS_STREAM == true - -/*! \name Streaming MEM <-> MEM Interface - */ -//! @{ - - - #if ACCESS_MEM_TO_MEM == true - -#include "fat.h" - -Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector) -{ - COMPILER_ALIGNED(4) - static U8 sector_buf[FS_512B]; - Ctrl_status status = CTRL_GOOD; - - while (nb_sector--) - { - if ((status = memory_2_ram(src_lun, src_addr++, sector_buf)) != CTRL_GOOD) break; - if ((status = ram_2_memory(dest_lun, dest_addr++, sector_buf)) != CTRL_GOOD) break; - } - - return status; -} - - #endif // ACCESS_MEM_TO_MEM == true - - -Ctrl_status stream_state(U8 id) -{ - UNUSED(id); - return CTRL_GOOD; -} - - -U16 stream_stop(U8 id) -{ - UNUSED(id); - return 0; -} - - -//! @} - -#endif // ACCESS_STREAM == true diff --git a/atmel-samd/asf/common/services/storage/ctrl_access/ctrl_access.h b/atmel-samd/asf/common/services/storage/ctrl_access/ctrl_access.h deleted file mode 100644 index af6c8ceb963ef..0000000000000 --- a/atmel-samd/asf/common/services/storage/ctrl_access/ctrl_access.h +++ /dev/null @@ -1,402 +0,0 @@ -/***************************************************************************** - * - * \file - * - * \brief Abstraction layer for memory interfaces. - * - * This module contains the interfaces: - * - MEM <-> USB; - * - MEM <-> RAM; - * - MEM <-> MEM. - * - * This module may be configured and expanded to support the following features: - * - write-protected globals; - * - password-protected data; - * - specific features; - * - etc. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - ******************************************************************************/ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef _CTRL_ACCESS_H_ -#define _CTRL_ACCESS_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup group_common_services_storage_ctrl_access Memory Control Access - * - * Common abstraction layer for memory interfaces. It provides interfaces between: - * Memory and USB, Memory and RAM, Memory and Memory. Common API for XMEGA and UC3. - * - * \{ - */ - -#include "compiler.h" -#include "conf_access.h" - -#ifndef SECTOR_SIZE -#define SECTOR_SIZE 512 -#endif - -//! Status returned by CTRL_ACCESS interfaces. -typedef enum -{ - CTRL_GOOD = PASS, //!< Success, memory ready. - CTRL_FAIL = FAIL, //!< An error occurred. - CTRL_NO_PRESENT = FAIL + 1, //!< Memory unplugged. - CTRL_BUSY = FAIL + 2 //!< Memory not initialized or changed. -} Ctrl_status; - - -// FYI: Each Logical Unit Number (LUN) corresponds to a memory. - -// Check LUN defines. -#ifndef LUN_0 - #error LUN_0 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_1 - #error LUN_1 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_2 - #error LUN_2 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_3 - #error LUN_3 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_4 - #error LUN_4 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_5 - #error LUN_5 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_6 - #error LUN_6 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_7 - #error LUN_7 must be defined as ENABLE or DISABLE in conf_access.h -#endif -#ifndef LUN_USB - #error LUN_USB must be defined as ENABLE or DISABLE in conf_access.h -#endif - -/*! \name LUN IDs - */ -//! @{ -#define LUN_ID_0 (0) //!< First static LUN. -#define LUN_ID_1 (LUN_ID_0 + LUN_0) -#define LUN_ID_2 (LUN_ID_1 + LUN_1) -#define LUN_ID_3 (LUN_ID_2 + LUN_2) -#define LUN_ID_4 (LUN_ID_3 + LUN_3) -#define LUN_ID_5 (LUN_ID_4 + LUN_4) -#define LUN_ID_6 (LUN_ID_5 + LUN_5) -#define LUN_ID_7 (LUN_ID_6 + LUN_6) -#define MAX_LUN (LUN_ID_7 + LUN_7) //!< Number of static LUNs. -#define LUN_ID_USB (MAX_LUN) //!< First dynamic LUN (USB host mass storage). -//! @} - - -// Include LUN header files. -#if LUN_0 == ENABLE - #include LUN_0_INCLUDE -#endif -#if LUN_1 == ENABLE - #include LUN_1_INCLUDE -#endif -#if LUN_2 == ENABLE - #include LUN_2_INCLUDE -#endif -#if LUN_3 == ENABLE - #include LUN_3_INCLUDE -#endif -#if LUN_4 == ENABLE - #include LUN_4_INCLUDE -#endif -#if LUN_5 == ENABLE - #include LUN_5_INCLUDE -#endif -#if LUN_6 == ENABLE - #include LUN_6_INCLUDE -#endif -#if LUN_7 == ENABLE - #include LUN_7_INCLUDE -#endif -#if LUN_USB == ENABLE - #include LUN_USB_INCLUDE -#endif - - -// Check the configuration of write protection in conf_access.h. -#ifndef GLOBAL_WR_PROTECT - #error GLOBAL_WR_PROTECT must be defined as true or false in conf_access.h -#endif - - -#if GLOBAL_WR_PROTECT == true - -//! Write protect. -extern bool g_wr_protect; - -#endif - - -/*! \name Control Interface - */ -//! @{ - -#ifdef FREERTOS_USED - -/*! \brief Initializes the LUN access locker. - * - * \return \c true if the locker was successfully initialized, else \c false. - */ -extern bool ctrl_access_init(void); - -#endif // FREERTOS_USED - -/*! \brief Returns the number of LUNs. - * - * \return Number of LUNs in the system. - */ -extern U8 get_nb_lun(void); - -/*! \brief Returns the current LUN. - * - * \return Current LUN. - * - * \todo Implement. - */ -extern U8 get_cur_lun(void); - -/*! \brief Tests the memory state and initializes the memory if required. - * - * The TEST UNIT READY SCSI primary command allows an application client to poll - * a LUN until it is ready without having to allocate memory for returned data. - * - * This command may be used to check the media status of LUNs with removable - * media. - * - * \param lun Logical Unit Number. - * - * \return Status. - */ -extern Ctrl_status mem_test_unit_ready(U8 lun); - -/*! \brief Returns the address of the last valid sector (512 bytes) in the - * memory. - * - * \param lun Logical Unit Number. - * \param u32_nb_sector Pointer to the address of the last valid sector. - * - * \return Status. - */ -extern Ctrl_status mem_read_capacity(U8 lun, U32 *u32_nb_sector); - -/*! \brief Returns the size of the physical sector. - * - * \param lun Logical Unit Number. - * - * \return Sector size (unit: 512 bytes). - */ -extern U8 mem_sector_size(U8 lun); - -/*! \brief Unload/load the medium. - * - * \param lun Logical Unit Number. - * \param unload \c true to unload the medium, \c false to load the medium. - * - * \return \c true if unload/load success, else \c false. - */ -extern bool mem_unload(U8 lun, bool unload); - -/*! \brief Returns the write-protection state of the memory. - * - * \param lun Logical Unit Number. - * - * \return \c true if the memory is write-protected, else \c false. - * - * \note Only used by removable memories with hardware-specific write - * protection. - */ -extern bool mem_wr_protect(U8 lun); - -/*! \brief Tells whether the memory is removable. - * - * \param lun Logical Unit Number. - * - * \return \c true if the memory is removable, else \c false. - */ -extern bool mem_removal(U8 lun); - -/*! \brief Returns a pointer to the LUN name. - * - * \param lun Logical Unit Number. - * - * \return Pointer to the LUN name string. - */ -extern const char *mem_name(U8 lun); - -//! @} - - -#if ACCESS_USB == true - -/*! \name MEM <-> USB Interface - */ -//! @{ - -/*! \brief Transfers data from the memory to USB. - * - * \param lun Logical Unit Number. - * \param addr Address of first memory sector to read. - * \param nb_sector Number of sectors to transfer. - * - * \return Status. - */ -extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector); - -/*! \brief Transfers data from USB to the memory. - * - * \param lun Logical Unit Number. - * \param addr Address of first memory sector to write. - * \param nb_sector Number of sectors to transfer. - * - * \return Status. - */ -extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector); - -//! @} - -#endif // ACCESS_USB == true - - -#if ACCESS_MEM_TO_RAM == true - -/*! \name MEM <-> RAM Interface - */ -//! @{ - -/*! \brief Copies 1 data sector from the memory to RAM. - * - * \param lun Logical Unit Number. - * \param addr Address of first memory sector to read. - * \param ram Pointer to RAM buffer to write. - * - * \return Status. - */ -extern Ctrl_status memory_2_ram(U8 lun, U32 addr, void *ram); - -/*! \brief Copies 1 data sector from RAM to the memory. - * - * \param lun Logical Unit Number. - * \param addr Address of first memory sector to write. - * \param ram Pointer to RAM buffer to read. - * - * \return Status. - */ -extern Ctrl_status ram_2_memory(U8 lun, U32 addr, const void *ram); - -//! @} - -#endif // ACCESS_MEM_TO_RAM == true - - -#if ACCESS_STREAM == true - -/*! \name Streaming MEM <-> MEM Interface - */ -//! @{ - -//! Erroneous streaming data transfer ID. -#define ID_STREAM_ERR 0xFF - - #if ACCESS_MEM_TO_MEM == true - -/*! \brief Copies data from one memory to another. - * - * \param src_lun Source Logical Unit Number. - * \param src_addr Source address of first memory sector to read. - * \param dest_lun Destination Logical Unit Number. - * \param dest_addr Destination address of first memory sector to write. - * \param nb_sector Number of sectors to copy. - * - * \return Status. - */ -extern Ctrl_status stream_mem_to_mem(U8 src_lun, U32 src_addr, U8 dest_lun, U32 dest_addr, U16 nb_sector); - - #endif // ACCESS_MEM_TO_MEM == true - -/*! \brief Returns the state of a streaming data transfer. - * - * \param id Transfer ID. - * - * \return Status. - * - * \todo Implement. - */ -extern Ctrl_status stream_state(U8 id); - -/*! \brief Stops a streaming data transfer. - * - * \param id Transfer ID. - * - * \return Number of remaining sectors. - * - * \todo Implement. - */ -extern U16 stream_stop(U8 id); - -//! @} - -#endif // ACCESS_STREAM == true - -/** - * \} - */ - -#ifdef __cplusplus -} -#endif - -#endif // _CTRL_ACCESS_H_ diff --git a/atmel-samd/asf/common/services/storage/ctrl_access/doxygen/common.services.storage.ctrl_access/doxyfile.doxygen b/atmel-samd/asf/common/services/storage/ctrl_access/doxygen/common.services.storage.ctrl_access/doxyfile.doxygen deleted file mode 100644 index 87de4eaf91767..0000000000000 --- a/atmel-samd/asf/common/services/storage/ctrl_access/doxygen/common.services.storage.ctrl_access/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Memory Control Access Interface" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../ctrl_access.c ../../ctrl_access.h ../../module_config/conf_access.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. 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The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/storage/ctrl_access/doxygen/common.services.storage.ctrl_access/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/storage/ctrl_access/doxygen/common.services.storage.ctrl_access/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/storage/ctrl_access/doxygen/common.services.storage.ctrl_access/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/storage/ctrl_access/module_config/conf_access.h b/atmel-samd/asf/common/services/storage/ctrl_access/module_config/conf_access.h deleted file mode 100644 index 25e376c84a1c5..0000000000000 --- a/atmel-samd/asf/common/services/storage/ctrl_access/module_config/conf_access.h +++ /dev/null @@ -1,282 +0,0 @@ -/***************************************************************************** - * - * \file - * - * \brief Memory access control configuration file. - * - * This file contains the possible external configuration of the memory access - * control. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - ******************************************************************************/ -/* - * Support and FAQ: visit Atmel Support - */ - - - //! Configuration of ctrl_access which is an abstraction layer for memory interfaces (common/services/storage/ctrl_access) - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#ifdef VIRTUAL_MEMORY_ENABLE -#define LUN_0 ENABLE //!< Enable On-Chip Virtual Memory. -#else -#define LUN_0 DISABLE //!< Disable On-Chip Virtual Memory. -#endif - -#ifdef AT45DBX_ENABLE -#define LUN_1 ENABLE //!< Enable AT45DBX Data Flash. -#else -#define LUN_1 DISABLE //!< Disable AT45DBX Data Flash. -#endif - -//! New setting for SD/MMC stack in common folder -#ifdef SD_MMC_ENABLE -#define LUN_2 ENABLE //!< Enable common SD/MMC stack -#define LUN_3 ENABLE -#else -#define LUN_2 DISABLE //!< Disable common SD/MMC stack -#define LUN_3 DISABLE -#endif - -//! Old setting for SD/MMC stack in AVR folder -#ifdef SD_MMC_SPI_ENABLE -#define LUN_4 ENABLE //!< Enable SD/MMC Card over SPI or SPI. -#else -#define LUN_4 DISABLE //!< Disable SD/MMC Card over SPI or SPI. -#endif - -//! Old setting for SD/MMC stack in AVR folder -#ifdef SD_MMC_MCI_ENABLE -#define LUN_5 ENABLE //!< Enable SD/MMC Card over MCI or MCI. -#else -#define LUN_5 DISABLE //!< Disable SD/MMC Card over MCI or MCI. -#endif - -#define LUN_6 DISABLE -#define LUN_7 DISABLE - -#ifdef USB_MASS_STORAGE_ENABLE -#define LUN_USB ENABLE //!< Enable Host Mass-Storage Memory. -#else -#define LUN_USB DISABLE //!< Disable Host Mass-Storage Memory. -#endif - -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define VIRTUAL_MEM LUN_0 -#define LUN_ID_VIRTUAL_MEM LUN_ID_0 -#define LUN_0_INCLUDE "virtual_mem.h" -#define Lun_0_test_unit_ready virtual_test_unit_ready -#define Lun_0_read_capacity virtual_read_capacity -#define Lun_0_unload NULL /* Can not be unloaded */ -#define Lun_0_wr_protect virtual_wr_protect -#define Lun_0_removal virtual_removal -#define Lun_0_usb_read_10 virtual_usb_read_10 -#define Lun_0_usb_write_10 virtual_usb_write_10 -#define Lun_0_mem_2_ram virtual_mem_2_ram -#define Lun_0_ram_2_mem virtual_ram_2_mem -#define LUN_0_NAME "\"On-Chip Virtual Memory\"" -//! @} - -/*! \name LUN 1 Definitions - */ -//! @{ -#define AT45DBX_MEM LUN_1 -#define LUN_ID_AT45DBX_MEM LUN_ID_1 -#define LUN_1_INCLUDE "at45dbx_mem.h" -#define Lun_1_test_unit_ready at45dbx_test_unit_ready -#define Lun_1_read_capacity at45dbx_read_capacity -#define Lun_1_unload NULL /* Can not be unloaded */ -#define Lun_1_wr_protect at45dbx_wr_protect -#define Lun_1_removal at45dbx_removal -#define Lun_1_usb_read_10 at45dbx_usb_read_10 -#define Lun_1_usb_write_10 at45dbx_usb_write_10 -#define Lun_1_mem_2_ram at45dbx_df_2_ram -#define Lun_1_ram_2_mem at45dbx_ram_2_df -#define LUN_1_NAME "\"AT45DBX Data Flash\"" -//! @} - -/*! \name LUN 2 Definitions - */ -//! @{ -#define SD_MMC_0_MEM LUN_2 -#define LUN_ID_SD_MMC_0_MEM LUN_ID_2 -#define LUN_2_INCLUDE "sd_mmc_mem.h" -#define Lun_2_test_unit_ready sd_mmc_test_unit_ready_0 -#define Lun_2_read_capacity sd_mmc_read_capacity_0 -#define Lun_2_unload sd_mmc_unload_0 -#define Lun_2_wr_protect sd_mmc_wr_protect_0 -#define Lun_2_removal sd_mmc_removal_0 -#define Lun_2_usb_read_10 sd_mmc_usb_read_10_0 -#define Lun_2_usb_write_10 sd_mmc_usb_write_10_0 -#define Lun_2_mem_2_ram sd_mmc_mem_2_ram_0 -#define Lun_2_ram_2_mem sd_mmc_ram_2_mem_0 -#define LUN_2_NAME "\"SD/MMC Card Slot 0\"" -//! @} - -/*! \name LUN 3 Definitions - */ -//! @{ -#define SD_MMC_1_MEM LUN_3 -#define LUN_ID_SD_MMC_1_MEM LUN_ID_3 -#define LUN_3_INCLUDE "sd_mmc_mem.h" -#define Lun_3_test_unit_ready sd_mmc_test_unit_ready_1 -#define Lun_3_read_capacity sd_mmc_read_capacity_1 -#define Lun_3_unload sd_mmc_unload_1 -#define Lun_3_wr_protect sd_mmc_wr_protect_1 -#define Lun_3_removal sd_mmc_removal_1 -#define Lun_3_usb_read_10 sd_mmc_usb_read_10_1 -#define Lun_3_usb_write_10 sd_mmc_usb_write_10_1 -#define Lun_3_mem_2_ram sd_mmc_mem_2_ram_1 -#define Lun_3_ram_2_mem sd_mmc_ram_2_mem_1 -#define LUN_3_NAME "\"SD/MMC Card Slot 1\"" -//! @} - -/*! \name LUN 4 Definitions - */ -//! @{ -#define SD_MMC_SPI_MEM LUN_4 -#define LUN_ID_SD_MMC_SPI_MEM LUN_ID_4 -#define LUN_4_INCLUDE "sd_mmc_spi_mem.h" -#define Lun_4_test_unit_ready sd_mmc_spi_test_unit_ready -#define Lun_4_read_capacity sd_mmc_spi_read_capacity -#define Lun_4_unload NULL -#define Lun_4_wr_protect sd_mmc_spi_wr_protect -#define Lun_4_removal sd_mmc_spi_removal -#define Lun_4_usb_read_10 sd_mmc_spi_usb_read_10 -#define Lun_4_usb_write_10 sd_mmc_spi_usb_write_10 -#define Lun_4_mem_2_ram sd_mmc_spi_mem_2_ram -#define Lun_4_ram_2_mem sd_mmc_spi_ram_2_mem -#define LUN_4_NAME "\"SD/MMC Card over SPI\"" -//! @} - -/*! \name LUN 5 Definitions - */ -//! @{ -#define SD_MMC_MCI_0_MEM LUN_5 -#define LUN_ID_SD_MMC_MCI_0_MEM LUN_ID_5 -#define LUN_5_INCLUDE "sd_mmc_mci_mem.h" -#define Lun_5_test_unit_ready sd_mmc_mci_test_unit_ready_0 -#define Lun_5_read_capacity sd_mmc_mci_read_capacity_0 -#define Lun_5_unload NULL -#define Lun_5_wr_protect sd_mmc_mci_wr_protect_0 -#define Lun_5_removal sd_mmc_mci_removal_0 -#define Lun_5_usb_read_10 sd_mmc_mci_usb_read_10_0 -#define Lun_5_usb_write_10 sd_mmc_mci_usb_write_10_0 -#define Lun_5_mem_2_ram sd_mmc_mci_mem_2_ram_0 -#define Lun_5_ram_2_mem sd_mmc_mci_ram_2_mem_0 -#define LUN_5_NAME "\"SD/MMC Card over MCI Slot 0\"" -//! @} - -/*! \name USB LUNs Definitions - */ -//! @{ -#define MEM_USB LUN_USB -#define LUN_ID_MEM_USB LUN_ID_USB -#define LUN_USB_INCLUDE "uhi_msc_mem.h" -#define Lun_usb_get_lun() uhi_msc_mem_get_lun() -#define Lun_usb_test_unit_ready(lun) uhi_msc_mem_test_unit_ready(lun) -#define Lun_usb_read_capacity(lun, nb_sect) uhi_msc_mem_read_capacity(lun, nb_sect) -#define Lun_usb_read_sector_size(lun) uhi_msc_mem_read_sector_size(lun) -#define Lun_usb_unload NULL -#define Lun_usb_wr_protect(lun) uhi_msc_mem_wr_protect(lun) -#define Lun_usb_removal() uhi_msc_mem_removal() -#define Lun_usb_mem_2_ram(addr, ram) uhi_msc_mem_read_10_ram(addr, ram) -#define Lun_usb_ram_2_mem(addr, ram) uhi_msc_mem_write_10_ram(addr, ram) -#define LUN_USB_NAME "\"Host Mass-Storage Memory\"" -//! @} - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#ifdef ACCESS_USB_ENABLED -#define ACCESS_USB true //!< MEM <-> USB interface. -#else -#define ACCESS_USB false //!< MEM <-> USB interface. -#endif - -#ifdef ACCESS_MEM_TO_RAM_ENABLED -#define ACCESS_MEM_TO_RAM true //!< MEM <-> RAM interface. -#else -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#endif - -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - -/*! \name Sector size option for different storage media. - */ -//! @{ -#define SECTOR_SIZE 512 -//! @} - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/atmel_devices_cdc.cat b/atmel-samd/asf/common/services/usb/class/cdc/device/atmel_devices_cdc.cat deleted file mode 100644 index 09a0673b21a59..0000000000000 Binary files a/atmel-samd/asf/common/services/usb/class/cdc/device/atmel_devices_cdc.cat and /dev/null differ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/atmel_devices_cdc.inf b/atmel-samd/asf/common/services/usb/class/cdc/device/atmel_devices_cdc.inf deleted file mode 100644 index d2df608e6b8d7..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/atmel_devices_cdc.inf +++ /dev/null @@ -1,182 +0,0 @@ -; Windows 2000, XP, Vista, 7 and 8 (x32 and x64) setup file for Atmel CDC Devices -; Copyright (c) 2000-2013 ATMEL, Inc. - -[Version] -Signature = "$Windows NT$" -Class = Ports -ClassGuid = {4D36E978-E325-11CE-BFC1-08002BE10318} - -Provider = %Manufacturer% -LayoutFile = layout.inf -CatalogFile = atmel_devices_cdc.cat -DriverVer = 01/08/2013,6.0.0.0 - -;---------------------------------------------------------- -; Targets -;---------------------------------------------------------- -[Manufacturer] -%Manufacturer%=DeviceList, NTAMD64, NTIA64, NT - -[DeviceList] -%ATMEL_CDC_XPLAINED%=DriverInstall, USB\VID_03EB&PID_2122 -%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall, USB\VID_03EB&PID_214B -%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall, USB\VID_03EB&PID_214A -%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2307 -%ATMEL_CDC_EVK1XXX%=DriverInstall, USB\VID_03EB&PID_2310 -%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall, USB\VID_03EB&PID_2404 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall, USB\VID_03EB&PID_2421&MI_00 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall, USB\VID_03EB&PID_2424&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall, USB\VID_03EB&PID_2425&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall, USB\VID_03EB&PID_2425&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall, USB\VID_03EB&PID_2426&MI_00 -%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall, USB\VID_03EB&PID_2426&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall, USB\VID_03EB&PID_2426&MI_04 -%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall, USB\VID_03EB&PID_2426&MI_06 -%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall, USB\VID_03EB&PID_2426&MI_08 -%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall, USB\VID_03EB&PID_2426&MI_0A -%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall, USB\VID_03EB&PID_2426&MI_0C - -[DeviceList.NTAMD64] -%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122 -%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B -%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A -%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307 -%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310 -%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00 -%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04 -%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06 -%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08 -%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A -%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C - -[DeviceList.NTIA64] -%ATMEL_CDC_XPLAINED%=DriverInstall.NTamd64, USB\VID_03EB&PID_2122 -%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NTamd64, USB\VID_03EB&PID_214B -%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NTamd64, USB\VID_03EB&PID_214A -%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2307 -%ATMEL_CDC_EVK1XXX%=DriverInstall.NTamd64, USB\VID_03EB&PID_2310 -%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NTamd64, USB\VID_03EB&PID_2404 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2421&MI_00 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2424&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2425&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_00 -%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_04 -%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_06 -%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_08 -%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0A -%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NTamd64, USB\VID_03EB&PID_2426&MI_0C - -[DeviceList.NT] -%ATMEL_CDC_XPLAINED%=DriverInstall.NT, USB\VID_03EB&PID_2122 -%ATMEL_CDC_USB_ZIGBIT_Sub%=DriverInstall.NT, USB\VID_03EB&PID_214B -%ATMEL_CDC_USB_ZIGBIT_2_4%=DriverInstall.NT, USB\VID_03EB&PID_214A -%ATMEL_CDC_SFW_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2307 -%ATMEL_CDC_EVK1XXX%=DriverInstall.NT, USB\VID_03EB&PID_2310 -%ATMEL_CDC_ASF_EXAMPLE%=DriverInstall.NT, USB\VID_03EB&PID_2404 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2%=DriverInstall.NT, USB\VID_03EB&PID_2421&MI_00 -%ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4%=DriverInstall.NT, USB\VID_03EB&PID_2424&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_00 -%ATMEL_CDC_ASF_EXAMPLE2_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2425&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM1%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_00 -%ATMEL_CDC_ASF_EXAMPLE3_COM2%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_02 -%ATMEL_CDC_ASF_EXAMPLE3_COM3%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_04 -%ATMEL_CDC_ASF_EXAMPLE3_COM4%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_06 -%ATMEL_CDC_ASF_EXAMPLE3_COM5%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_08 -%ATMEL_CDC_ASF_EXAMPLE3_COM6%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0A -%ATMEL_CDC_ASF_EXAMPLE3_COM7%=DriverInstall.NT, USB\VID_03EB&PID_2426&MI_0C - -;---------------------------------------------------------- -; Windows 2000, XP, Vista, Windows 7, Windows 8 - 32bit -;---------------------------------------------------------- -[Reader_Install.NTx86] - - -[DestinationDirs] -DefaultDestDir=12 -DriverInstall.NT.Copy=12 - -[DriverInstall.NT] -include=mdmcpq.inf -CopyFiles=DriverInstall.NT.Copy -AddReg=DriverInstall.NT.AddReg - -[DriverInstall.NT.Copy] -usbser.sys - -[DriverInstall.NT.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[DriverInstall.NT.Services] -AddService = usbser, 0x00000002, DriverService.NT - -[DriverService.NT] -DisplayName = %Serial.SvcDesc% -ServiceType = 1 ; SERVICE_KERNEL_DRIVER -StartType = 3 ; SERVICE_DEMAND_START -ErrorControl = 1 ; SERVICE_ERROR_NORMAL -ServiceBinary = %12%\usbser.sys -LoadOrderGroup = Base - -;---------------------------------------------------------- -; Windows XP, Vista, Windows 7, Windows 8 - 64bit -;---------------------------------------------------------- - -[DriverInstall.NTamd64] -include=mdmcpq.inf -CopyFiles=DriverCopyFiles.NTamd64 -AddReg=DriverInstall.NTamd64.AddReg - -[DriverCopyFiles.NTamd64] -usbser.sys,,,0x20 - -[DriverInstall.NTamd64.AddReg] -HKR,,DevLoader,,*ntkern -HKR,,NTMPDriver,,usbser.sys -HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" - -[DriverInstall.NTamd64.Services] -AddService=usbser, 0x00000002, DriverService.NTamd64 - -[DriverService.NTamd64] -DisplayName=%Serial.SvcDesc% -ServiceType=1 -StartType=3 -ErrorControl=1 -ServiceBinary=%12%\usbser.sys - -;---------------------------------------------------------- -; String -;---------------------------------------------------------- - -[Strings] -Manufacturer = "ATMEL, Inc." -ATMEL_CDC_XPLAINED = "XPLAINED Virtual Com Port" -ATMEL_CDC_USB_ZIGBIT_Sub = "ZigBit SubGHz USBstick Com Port" -ATMEL_CDC_USB_ZIGBIT_2_4 = "ZigBit 2.4GHz USBstick Com Port" -ATMEL_CDC_SFW_EXAMPLE = "Communication Device Class SFW example" -ATMEL_CDC_EVK1XXX = "EVK1XXX Virtual Com Port" -ATMEL_CDC_ASF_EXAMPLE = "Communication Device Class ASF example" -ATMEL_CDC_ASF_COMPOSITE_EXAMPLE2 = "Communication Device Class ASF composite example 2" -ATMEL_CDC_ASF_COMPOSITE_EXAMPLE4 = "Communication Device Class ASF composite example 4" -ATMEL_CDC_ASF_EXAMPLE2_COM1 = "Communication Device Class ASF example2, COM1" -ATMEL_CDC_ASF_EXAMPLE2_COM2 = "Communication Device Class ASF example2, COM2" -ATMEL_CDC_ASF_EXAMPLE3_COM1 = "Communication Device Class ASF example3, COM1" -ATMEL_CDC_ASF_EXAMPLE3_COM2 = "Communication Device Class ASF example3, COM2" -ATMEL_CDC_ASF_EXAMPLE3_COM3 = "Communication Device Class ASF example3, COM3" -ATMEL_CDC_ASF_EXAMPLE3_COM4 = "Communication Device Class ASF example3, COM4" -ATMEL_CDC_ASF_EXAMPLE3_COM5 = "Communication Device Class ASF example3, COM5" -ATMEL_CDC_ASF_EXAMPLE3_COM6 = "Communication Device Class ASF example3, COM6" -ATMEL_CDC_ASF_EXAMPLE3_COM7 = "Communication Device Class ASF example3, COM7" - -Serial.SvcDesc = "USB Serial emulation driver" - diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite.common/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite.common/doxyfile.doxygen deleted file mode 100644 index 08ef0d093fb26..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite.common/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC (Composite Device)" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../udi_cdc.c ../../udi_cdc.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite.common/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite.common/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite.common/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_disable/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_disable/doxyfile.doxygen deleted file mode 100644 index 40be54b271571..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_disable/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC disabled" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_disable/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_disable/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_disable/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_enable/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_enable/doxyfile.doxygen deleted file mode 100644 index a93f26ff92653..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_enable/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC (Composite Device)" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_enable/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_enable/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.composite_enable/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.single/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.single/doxyfile.doxygen deleted file mode 100644 index 7bddeb6f2b2cc..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.single/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC (Single Interface Device)" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../udi_cdc.c ../../udi_cdc_desc.c ../../udi_cdc.h ../../udi_cdc_conf.h ../../module_config/conf_usb.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. 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This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.single/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.single/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/doxygen/common.services.usb.class.cdc.device.single/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
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- * - * \section main_licence License - *
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  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/module_config/conf_usb.h b/atmel-samd/asf/common/services/usb/class/cdc/device/module_config/conf_usb.h deleted file mode 100644 index 4959618a8927c..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/module_config/conf_usb.h +++ /dev/null @@ -1,172 +0,0 @@ -/** - * \file - * - * \brief USB configuration file for CDC application - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_USB_H_ -#define _CONF_USB_H_ - -#include "compiler.h" - -#warning You must refill the following definitions with a correct values - -/** - * USB Device Configuration - * @{ - */ - -//! Device definition (mandatory) -#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL -#define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_ASF_CDC -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" -// #define USB_DEVICE_PRODUCT_NAME "Product name" -// #define USB_DEVICE_SERIAL_NAME "12...EF" - - -/** - * Device speeds support - * Low speed not supported by CDC - * @{ - */ -//! To authorize the High speed -#if (UC3A3||UC3A4) -#define USB_DEVICE_HS_SUPPORT -#endif -//@} - - -/** - * USB Device Callbacks definitions (Optional) - * @{ - */ -// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high) -// extern void user_callback_vbus_action(bool b_vbus_high); -// #define UDC_SOF_EVENT() user_callback_sof_action() -// extern void user_callback_sof_action(void); -// #define UDC_SUSPEND_EVENT() user_callback_suspend_action() -// extern void user_callback_suspend_action(void); -// #define UDC_RESUME_EVENT() user_callback_resume_action() -// extern void user_callback_resume_action(void); -// Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature -// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() -// extern void user_callback_remotewakeup_enable(void); -// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() -// extern void user_callback_remotewakeup_disable(void); -// When a extra string descriptor must be supported -// other than manufacturer, product and serial string -// #define UDC_GET_EXTRA_STRING() -//@} - -//@} - - -/** - * USB Interface Configuration - * @{ - */ -/** - * Configuration of CDC interface - * @{ - */ - -//! Number of communication port used (1 to 3) -#define UDI_CDC_PORT_NB 1 - -//! Interface callback definition -#define UDI_CDC_ENABLE_EXT(port) true -#define UDI_CDC_DISABLE_EXT(port) -#define UDI_CDC_RX_NOTIFY(port) -#define UDI_CDC_TX_EMPTY_NOTIFY(port) -#define UDI_CDC_SET_CODING_EXT(port,cfg) -#define UDI_CDC_SET_DTR_EXT(port,set) -#define UDI_CDC_SET_RTS_EXT(port,set) - -// #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() -// extern bool my_callback_cdc_enable(void); -// #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() -// extern void my_callback_cdc_disable(void); -// #define UDI_CDC_RX_NOTIFY(port) my_callback_rx_notify(port) -// extern void my_callback_rx_notify(uint8_t port); -// #define UDI_CDC_TX_EMPTY_NOTIFY(port) my_callback_tx_empty_notify(port) -// extern void my_callback_tx_empty_notify(uint8_t port); -// #define UDI_CDC_SET_CODING_EXT(port,cfg) my_callback_config(port,cfg) -// extern void my_callback_config(uint8_t port, usb_cdc_line_coding_t * cfg); -// #define UDI_CDC_SET_DTR_EXT(port,set) my_callback_cdc_set_dtr(port,set) -// extern void my_callback_cdc_set_dtr(uint8_t port, bool b_enable); -// #define UDI_CDC_SET_RTS_EXT(port,set) my_callback_cdc_set_rts(port,set) -// extern void my_callback_cdc_set_rts(uint8_t port, bool b_enable); - -//! Define it when the transfer CDC Device to Host is a low rate (<512000 bauds) -//! to reduce CDC buffers size -#define UDI_CDC_LOW_RATE - -//! Default configuration of communication port -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 -//@} -//@} - - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc_conf.h" - -#endif // _CONF_USB_H_ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc.c b/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc.c deleted file mode 100644 index 848f2409710ec..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc.c +++ /dev/null @@ -1,1153 +0,0 @@ -/** - * \file - * - * \brief USB Device Communication Device Class (CDC) interface. - * - * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_cdc.h" -#include "udd.h" -#include "udc.h" -#include "udi_cdc.h" -#include - -#ifdef UDI_CDC_LOW_RATE -# ifdef USB_DEVICE_HS_SUPPORT -# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) -# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) -# else -# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE) -# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_FS_SIZE) -# endif -#else -# ifdef USB_DEVICE_HS_SUPPORT -# define UDI_CDC_TX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) -# define UDI_CDC_RX_BUFFERS (UDI_CDC_DATA_EPS_HS_SIZE) -# else -# define UDI_CDC_TX_BUFFERS (5*UDI_CDC_DATA_EPS_FS_SIZE) -# define UDI_CDC_RX_BUFFERS (5*UDI_CDC_DATA_EPS_FS_SIZE) -# endif -#endif - -#ifndef UDI_CDC_TX_EMPTY_NOTIFY -# define UDI_CDC_TX_EMPTY_NOTIFY(port) -#endif - -/** - * \ingroup udi_cdc_group - * \defgroup udi_cdc_group_udc Interface with USB Device Core (UDC) - * - * Structures and functions required by UDC. - * - * @{ - */ -bool udi_cdc_comm_enable(void); -void udi_cdc_comm_disable(void); -bool udi_cdc_comm_setup(void); -bool udi_cdc_data_enable(void); -void udi_cdc_data_disable(void); -bool udi_cdc_data_setup(void); -uint8_t udi_cdc_getsetting(void); -void udi_cdc_data_sof_notify(void); -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm = { - .enable = udi_cdc_comm_enable, - .disable = udi_cdc_comm_disable, - .setup = udi_cdc_comm_setup, - .getsetting = udi_cdc_getsetting, -}; -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udi_api_t udi_api_cdc_data = { - .enable = udi_cdc_data_enable, - .disable = udi_cdc_data_disable, - .setup = udi_cdc_data_setup, - .getsetting = udi_cdc_getsetting, - .sof_notify = udi_cdc_data_sof_notify, -}; -//@} - -/** - * \ingroup udi_cdc_group - * \defgroup udi_cdc_group_internal Implementation of UDI CDC - * - * Class internal implementation - * @{ - */ - -/** - * \name Internal routines - */ -//@{ - -/** - * \name Routines to control serial line - */ -//@{ - -/** - * \brief Returns the port number corresponding at current setup request - * - * \return port number - */ -static uint8_t udi_cdc_setup_to_port(void); - -/** - * \brief Sends line coding to application - * - * Called after SETUP request when line coding data is received. - */ -static void udi_cdc_line_coding_received(void); - -/** - * \brief Records new state - * - * \param port Communication port number to manage - * \param b_set State is enabled if true, else disabled - * \param bit_mask Field to process (see CDC_SERIAL_STATE_ defines) - */ -static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask); - -/** - * \brief Check and eventually notify the USB host of new state - * - * \param port Communication port number to manage - * \param ep Port communication endpoint - */ -static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep); - -/** - * \brief Ack sent of serial state message - * Callback called after serial state message sent - * - * \param status UDD_EP_TRANSFER_OK, if transfer finished - * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted - * \param n number of data transfered - */ -static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep); - -//@} - -/** - * \name Routines to process data transfer - */ -//@{ - -/** - * \brief Enable the reception of data from the USB host - * - * The value udi_cdc_rx_trans_sel indicate the RX buffer to fill. - * - * \param port Communication port number to manage - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -static bool udi_cdc_rx_start(uint8_t port); - -/** - * \brief Update rx buffer management with a new data - * Callback called after data reception on USB line - * - * \param status UDD_EP_TRANSFER_OK, if transfer finish - * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted - * \param n number of data received - */ -static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep); - -/** - * \brief Ack sent of tx buffer - * Callback called after data transfer on USB line - * - * \param status UDD_EP_TRANSFER_OK, if transfer finished - * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted - * \param n number of data transfered - */ -static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep); - -/** - * \brief Send buffer on line or wait a SOF event - * - * \param port Communication port number to manage - */ -static void udi_cdc_tx_send(uint8_t port); - -//@} - -//@} - -/** - * \name Information about configuration of communication line - */ -//@{ -COMPILER_WORD_ALIGNED - static usb_cdc_line_coding_t udi_cdc_line_coding[UDI_CDC_PORT_NB]; -static bool udi_cdc_serial_state_msg_ongoing[UDI_CDC_PORT_NB]; -static volatile le16_t udi_cdc_state[UDI_CDC_PORT_NB]; -COMPILER_WORD_ALIGNED static usb_cdc_notify_serial_state_t uid_cdc_state_msg[UDI_CDC_PORT_NB]; - -//! Status of CDC COMM interfaces -static volatile uint8_t udi_cdc_nb_comm_enabled = 0; -//@} - -/** - * \name Variables to manage RX/TX transfer requests - * Two buffers for each sense are used to optimize the speed. - */ -//@{ - -//! Status of CDC DATA interfaces -static volatile uint8_t udi_cdc_nb_data_enabled = 0; -static volatile bool udi_cdc_data_running = false; -//! Buffer to receive data -COMPILER_WORD_ALIGNED static uint8_t udi_cdc_rx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_RX_BUFFERS]; -//! Data available in RX buffers -static volatile uint16_t udi_cdc_rx_buf_nb[UDI_CDC_PORT_NB][2]; -//! Give the current RX buffer used (rx0 if 0, rx1 if 1) -static volatile uint8_t udi_cdc_rx_buf_sel[UDI_CDC_PORT_NB]; -//! Read position in current RX buffer -static volatile uint16_t udi_cdc_rx_pos[UDI_CDC_PORT_NB]; -//! Signal a transfer on-going -static volatile bool udi_cdc_rx_trans_ongoing[UDI_CDC_PORT_NB]; - -//! Define a transfer halted -#define UDI_CDC_TRANS_HALTED 2 - -//! Buffer to send data -COMPILER_WORD_ALIGNED static uint8_t udi_cdc_tx_buf[UDI_CDC_PORT_NB][2][UDI_CDC_TX_BUFFERS]; -//! Data available in TX buffers -static uint16_t udi_cdc_tx_buf_nb[UDI_CDC_PORT_NB][2]; -//! Give current TX buffer used (tx0 if 0, tx1 if 1) -static volatile uint8_t udi_cdc_tx_buf_sel[UDI_CDC_PORT_NB]; -//! Value of SOF during last TX transfer -static uint16_t udi_cdc_tx_sof_num[UDI_CDC_PORT_NB]; -//! Signal a transfer on-going -static volatile bool udi_cdc_tx_trans_ongoing[UDI_CDC_PORT_NB]; -//! Signal that both buffer content data to send -static volatile bool udi_cdc_tx_both_buf_to_send[UDI_CDC_PORT_NB]; - -//@} - -bool udi_cdc_comm_enable(void) -{ - uint8_t port; - uint8_t iface_comm_num; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; - udi_cdc_nb_comm_enabled = 0; -#else - if (udi_cdc_nb_comm_enabled > UDI_CDC_PORT_NB) { - udi_cdc_nb_comm_enabled = 0; - } - port = udi_cdc_nb_comm_enabled; -#endif - - // Initialize control signal management - udi_cdc_state[port] = CPU_TO_LE16(0); - - uid_cdc_state_msg[port].header.bmRequestType = - USB_REQ_DIR_IN | USB_REQ_TYPE_CLASS | - USB_REQ_RECIP_INTERFACE; - uid_cdc_state_msg[port].header.bNotification = USB_REQ_CDC_NOTIFY_SERIAL_STATE; - uid_cdc_state_msg[port].header.wValue = LE16(0); - - switch (port) { -#define UDI_CDC_PORT_TO_IFACE_COMM(index, unused) \ - case index: \ - iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_##index; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_IFACE_COMM, ~) -#undef UDI_CDC_PORT_TO_IFACE_COMM - default: - iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_0; - break; - } - - uid_cdc_state_msg[port].header.wIndex = LE16(iface_comm_num); - uid_cdc_state_msg[port].header.wLength = LE16(2); - uid_cdc_state_msg[port].value = CPU_TO_LE16(0); - - udi_cdc_line_coding[port].dwDTERate = CPU_TO_LE32(UDI_CDC_DEFAULT_RATE); - udi_cdc_line_coding[port].bCharFormat = UDI_CDC_DEFAULT_STOPBITS; - udi_cdc_line_coding[port].bParityType = UDI_CDC_DEFAULT_PARITY; - udi_cdc_line_coding[port].bDataBits = UDI_CDC_DEFAULT_DATABITS; - // Call application callback - // to initialize memories or indicate that interface is enabled - UDI_CDC_SET_CODING_EXT(port,(&udi_cdc_line_coding[port])); - if (!UDI_CDC_ENABLE_EXT(port)) { - return false; - } - udi_cdc_nb_comm_enabled++; - return true; -} - -bool udi_cdc_data_enable(void) -{ - uint8_t port; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; - udi_cdc_nb_data_enabled = 0; -#else - if (udi_cdc_nb_data_enabled > UDI_CDC_PORT_NB) { - udi_cdc_nb_data_enabled = 0; - } - port = udi_cdc_nb_data_enabled; -#endif - - // Initialize TX management - udi_cdc_tx_trans_ongoing[port] = false; - udi_cdc_tx_both_buf_to_send[port] = false; - udi_cdc_tx_buf_sel[port] = 0; - udi_cdc_tx_buf_nb[port][0] = 0; - udi_cdc_tx_buf_nb[port][1] = 0; - udi_cdc_tx_sof_num[port] = 0; - udi_cdc_tx_send(port); - - // Initialize RX management - udi_cdc_rx_trans_ongoing[port] = false; - udi_cdc_rx_buf_sel[port] = 0; - udi_cdc_rx_buf_nb[port][0] = 0; - udi_cdc_rx_buf_nb[port][1] = 0; - udi_cdc_rx_pos[port] = 0; - if (!udi_cdc_rx_start(port)) { - return false; - } - udi_cdc_nb_data_enabled++; - if (udi_cdc_nb_data_enabled == UDI_CDC_PORT_NB) { - udi_cdc_data_running = true; - } - return true; -} - -void udi_cdc_comm_disable(void) -{ - Assert(udi_cdc_nb_comm_enabled != 0); - udi_cdc_nb_comm_enabled--; -} - -void udi_cdc_data_disable(void) -{ - uint8_t port; - - Assert(udi_cdc_nb_data_enabled != 0); - udi_cdc_nb_data_enabled--; - port = udi_cdc_nb_data_enabled; - UDI_CDC_DISABLE_EXT(port); - udi_cdc_data_running = false; -} - -bool udi_cdc_comm_setup(void) -{ - uint8_t port = udi_cdc_setup_to_port(); - - if (Udd_setup_is_in()) { - // GET Interface Requests - if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { - // Requests Class Interface Get - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_CDC_GET_LINE_CODING: - // Get configuration of CDC line - if (sizeof(usb_cdc_line_coding_t) != - udd_g_ctrlreq.req.wLength) - return false; // Error for USB host - udd_g_ctrlreq.payload = - (uint8_t *) & - udi_cdc_line_coding[port]; - udd_g_ctrlreq.payload_size = - sizeof(usb_cdc_line_coding_t); - return true; - } - } - } - if (Udd_setup_is_out()) { - // SET Interface Requests - if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { - // Requests Class Interface Set - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_CDC_SET_LINE_CODING: - // Change configuration of CDC line - if (sizeof(usb_cdc_line_coding_t) != - udd_g_ctrlreq.req.wLength) - return false; // Error for USB host - udd_g_ctrlreq.callback = - udi_cdc_line_coding_received; - udd_g_ctrlreq.payload = - (uint8_t *) & - udi_cdc_line_coding[port]; - udd_g_ctrlreq.payload_size = - sizeof(usb_cdc_line_coding_t); - return true; - case USB_REQ_CDC_SET_CONTROL_LINE_STATE: - // According cdc spec 1.1 chapter 6.2.14 - UDI_CDC_SET_DTR_EXT(port, (0 != - (udd_g_ctrlreq.req.wValue - & CDC_CTRL_SIGNAL_DTE_PRESENT))); - UDI_CDC_SET_RTS_EXT(port, (0 != - (udd_g_ctrlreq.req.wValue - & CDC_CTRL_SIGNAL_ACTIVATE_CARRIER))); - return true; - } - } - } - return false; // request Not supported -} - -bool udi_cdc_data_setup(void) -{ - return false; // request Not supported -} - -uint8_t udi_cdc_getsetting(void) -{ - return 0; // CDC don't have multiple alternate setting -} - -void udi_cdc_data_sof_notify(void) -{ - static uint8_t port_notify = 0; - - // A call of udi_cdc_data_sof_notify() is done for each port - udi_cdc_tx_send(port_notify); -#if UDI_CDC_PORT_NB != 1 // To optimize code - port_notify++; - if (port_notify >= UDI_CDC_PORT_NB) { - port_notify = 0; - } -#endif -} - - -//------------------------------------------------- -//------- Internal routines to control serial line - -static uint8_t udi_cdc_setup_to_port(void) -{ - uint8_t port; - - switch (udd_g_ctrlreq.req.wIndex & 0xFF) { -#define UDI_CDC_IFACE_COMM_TO_PORT(iface, unused) \ - case UDI_CDC_COMM_IFACE_NUMBER_##iface: \ - port = iface; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_IFACE_COMM_TO_PORT, ~) -#undef UDI_CDC_IFACE_COMM_TO_PORT - default: - port = 0; - break; - } - return port; -} - -static void udi_cdc_line_coding_received(void) -{ - uint8_t port = udi_cdc_setup_to_port(); - UNUSED(port); - - UDI_CDC_SET_CODING_EXT(port, (&udi_cdc_line_coding[port])); -} - -static void udi_cdc_ctrl_state_change(uint8_t port, bool b_set, le16_t bit_mask) -{ - irqflags_t flags; - udd_ep_id_t ep_comm; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - // Update state - flags = cpu_irq_save(); // Protect udi_cdc_state - if (b_set) { - udi_cdc_state[port] |= bit_mask; - } else { - udi_cdc_state[port] &= ~(unsigned)bit_mask; - } - cpu_irq_restore(flags); - - // Send it if possible and state changed - switch (port) { -#define UDI_CDC_PORT_TO_COMM_EP(index, unused) \ - case index: \ - ep_comm = UDI_CDC_COMM_EP_##index; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_COMM_EP, ~) -#undef UDI_CDC_PORT_TO_COMM_EP - default: - ep_comm = UDI_CDC_COMM_EP_0; - break; - } - udi_cdc_ctrl_state_notify(port, ep_comm); -} - - -static void udi_cdc_ctrl_state_notify(uint8_t port, udd_ep_id_t ep) -{ -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - // Send it if possible and state changed - if ((!udi_cdc_serial_state_msg_ongoing[port]) - && (udi_cdc_state[port] != uid_cdc_state_msg[port].value)) { - // Fill notification message - uid_cdc_state_msg[port].value = udi_cdc_state[port]; - // Send notification message - udi_cdc_serial_state_msg_ongoing[port] = - udd_ep_run(ep, - false, - (uint8_t *) & uid_cdc_state_msg[port], - sizeof(uid_cdc_state_msg[0]), - udi_cdc_serial_state_msg_sent); - } -} - - -static void udi_cdc_serial_state_msg_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) -{ - uint8_t port; - UNUSED(n); - UNUSED(status); - - switch (ep) { -#define UDI_CDC_GET_PORT_FROM_COMM_EP(iface, unused) \ - case UDI_CDC_COMM_EP_##iface: \ - port = iface; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_GET_PORT_FROM_COMM_EP, ~) -#undef UDI_CDC_GET_PORT_FROM_COMM_EP - default: - port = 0; - break; - } - - udi_cdc_serial_state_msg_ongoing[port] = false; - - // For the irregular signals like break, the incoming ring signal, - // or the overrun error state, this will reset their values to zero - // and again will not send another notification until their state changes. - udi_cdc_state[port] &= ~(CDC_SERIAL_STATE_BREAK | - CDC_SERIAL_STATE_RING | - CDC_SERIAL_STATE_FRAMING | - CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN); - uid_cdc_state_msg[port].value &= ~(CDC_SERIAL_STATE_BREAK | - CDC_SERIAL_STATE_RING | - CDC_SERIAL_STATE_FRAMING | - CDC_SERIAL_STATE_PARITY | CDC_SERIAL_STATE_OVERRUN); - // Send it if possible and state changed - udi_cdc_ctrl_state_notify(port, ep); -} - - -//------------------------------------------------- -//------- Internal routines to process data transfer - - -static bool udi_cdc_rx_start(uint8_t port) -{ - irqflags_t flags; - uint8_t buf_sel_trans; - udd_ep_id_t ep; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - flags = cpu_irq_save(); - buf_sel_trans = udi_cdc_rx_buf_sel[port]; - if (udi_cdc_rx_trans_ongoing[port] || - (udi_cdc_rx_pos[port] < udi_cdc_rx_buf_nb[port][buf_sel_trans])) { - // Transfer already on-going or current buffer no empty - cpu_irq_restore(flags); - return false; - } - - // Change current buffer - udi_cdc_rx_pos[port] = 0; - udi_cdc_rx_buf_sel[port] = (buf_sel_trans==0)?1:0; - - // Start transfer on RX - udi_cdc_rx_trans_ongoing[port] = true; - cpu_irq_restore(flags); - - if (udi_cdc_multi_is_rx_ready(port)) { - UDI_CDC_RX_NOTIFY(port); - } - // Send the buffer with enable of short packet - switch (port) { -#define UDI_CDC_PORT_TO_DATA_EP_OUT(index, unused) \ - case index: \ - ep = UDI_CDC_DATA_EP_OUT_##index; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_OUT, ~) -#undef UDI_CDC_PORT_TO_DATA_EP_OUT - default: - ep = UDI_CDC_DATA_EP_OUT_0; - break; - } - return udd_ep_run(ep, - true, - udi_cdc_rx_buf[port][buf_sel_trans], - UDI_CDC_RX_BUFFERS, - udi_cdc_data_received); -} - - -static void udi_cdc_data_received(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) -{ - uint8_t buf_sel_trans; - uint8_t port; - - switch (ep) { -#define UDI_CDC_DATA_EP_OUT_TO_PORT(index, unused) \ - case UDI_CDC_DATA_EP_OUT_##index: \ - port = index; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_OUT_TO_PORT, ~) -#undef UDI_CDC_DATA_EP_OUT_TO_PORT - default: - port = 0; - break; - } - - if (UDD_EP_TRANSFER_OK != status) { - // Abort reception - return; - } - buf_sel_trans = (udi_cdc_rx_buf_sel[port]==0)?1:0; - if (!n) { - udd_ep_run( ep, - true, - udi_cdc_rx_buf[port][buf_sel_trans], - UDI_CDC_RX_BUFFERS, - udi_cdc_data_received); - return; - } - udi_cdc_rx_buf_nb[port][buf_sel_trans] = n; - udi_cdc_rx_trans_ongoing[port] = false; - udi_cdc_rx_start(port); -} - - -static void udi_cdc_data_sent(udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep) -{ - uint8_t port; - UNUSED(n); - - switch (ep) { -#define UDI_CDC_DATA_EP_IN_TO_PORT(index, unused) \ - case UDI_CDC_DATA_EP_IN_##index: \ - port = index; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DATA_EP_IN_TO_PORT, ~) -#undef UDI_CDC_DATA_EP_IN_TO_PORT - default: - port = 0; - break; - } - - if (UDD_EP_TRANSFER_OK != status) { - // Abort transfer - return; - } - udi_cdc_tx_buf_nb[port][(udi_cdc_tx_buf_sel[port]==0)?1:0] = 0; - udi_cdc_tx_both_buf_to_send[port] = false; - udi_cdc_tx_trans_ongoing[port] = false; - - if (n != 0) { - UDI_CDC_TX_EMPTY_NOTIFY(port); - } - udi_cdc_tx_send(port); -} - - -static void udi_cdc_tx_send(uint8_t port) -{ - irqflags_t flags; - uint8_t buf_sel_trans; - bool b_short_packet; - udd_ep_id_t ep; - static uint16_t sof_zlp_counter = 0; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - if (udi_cdc_tx_trans_ongoing[port]) { - return; // Already on going or wait next SOF to send next data - } - if (udd_is_high_speed()) { - if (udi_cdc_tx_sof_num[port] == udd_get_micro_frame_number()) { - return; // Wait next SOF to send next data - } - }else{ - if (udi_cdc_tx_sof_num[port] == udd_get_frame_number()) { - return; // Wait next SOF to send next data - } - } - - flags = cpu_irq_save(); // to protect udi_cdc_tx_buf_sel - buf_sel_trans = udi_cdc_tx_buf_sel[port]; - if (udi_cdc_tx_buf_nb[port][buf_sel_trans] == 0) { - sof_zlp_counter++; - if (((!udd_is_high_speed()) && (sof_zlp_counter < 100)) - || (udd_is_high_speed() && (sof_zlp_counter < 800))) { - cpu_irq_restore(flags); - return; - } - } - sof_zlp_counter = 0; - - if (!udi_cdc_tx_both_buf_to_send[port]) { - // Send current Buffer - // and switch the current buffer - udi_cdc_tx_buf_sel[port] = (buf_sel_trans==0)?1:0; - }else{ - // Send the other Buffer - // and no switch the current buffer - buf_sel_trans = (buf_sel_trans==0)?1:0; - } - udi_cdc_tx_trans_ongoing[port] = true; - cpu_irq_restore(flags); - - b_short_packet = (udi_cdc_tx_buf_nb[port][buf_sel_trans] != UDI_CDC_TX_BUFFERS); - if (b_short_packet) { - if (udd_is_high_speed()) { - udi_cdc_tx_sof_num[port] = udd_get_micro_frame_number(); - }else{ - udi_cdc_tx_sof_num[port] = udd_get_frame_number(); - } - }else{ - udi_cdc_tx_sof_num[port] = 0; // Force next transfer without wait SOF - } - - // Send the buffer with enable of short packet - switch (port) { -#define UDI_CDC_PORT_TO_DATA_EP_IN(index, unused) \ - case index: \ - ep = UDI_CDC_DATA_EP_IN_##index; \ - break; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_DATA_EP_IN, ~) -#undef UDI_CDC_PORT_TO_DATA_EP_IN - default: - ep = UDI_CDC_DATA_EP_IN_0; - break; - } - udd_ep_run( ep, - b_short_packet, - udi_cdc_tx_buf[port][buf_sel_trans], - udi_cdc_tx_buf_nb[port][buf_sel_trans], - udi_cdc_data_sent); -} - - -//--------------------------------------------- -//------- Application interface - - -//------- Application interface - -void udi_cdc_ctrl_signal_dcd(bool b_set) -{ - udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DCD); -} - -void udi_cdc_ctrl_signal_dsr(bool b_set) -{ - udi_cdc_ctrl_state_change(0, b_set, CDC_SERIAL_STATE_DSR); -} - -void udi_cdc_signal_framing_error(void) -{ - udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_FRAMING); -} - -void udi_cdc_signal_parity_error(void) -{ - udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_PARITY); -} - -void udi_cdc_signal_overrun(void) -{ - udi_cdc_ctrl_state_change(0, true, CDC_SERIAL_STATE_OVERRUN); -} - -void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set) -{ - udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DCD); -} - -void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set) -{ - udi_cdc_ctrl_state_change(port, b_set, CDC_SERIAL_STATE_DSR); -} - -void udi_cdc_multi_signal_framing_error(uint8_t port) -{ - udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_FRAMING); -} - -void udi_cdc_multi_signal_parity_error(uint8_t port) -{ - udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_PARITY); -} - -void udi_cdc_multi_signal_overrun(uint8_t port) -{ - udi_cdc_ctrl_state_change(port, true, CDC_SERIAL_STATE_OVERRUN); -} - -iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port) -{ - irqflags_t flags; - uint16_t pos; - iram_size_t nb_received; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - flags = cpu_irq_save(); - pos = udi_cdc_rx_pos[port]; - nb_received = udi_cdc_rx_buf_nb[port][udi_cdc_rx_buf_sel[port]] - pos; - cpu_irq_restore(flags); - return nb_received; -} - -iram_size_t udi_cdc_get_nb_received_data(void) -{ - return udi_cdc_multi_get_nb_received_data(0); -} - -bool udi_cdc_multi_is_rx_ready(uint8_t port) -{ - return (udi_cdc_multi_get_nb_received_data(port) > 0); -} - -bool udi_cdc_is_rx_ready(void) -{ - return udi_cdc_multi_is_rx_ready(0); -} - -int udi_cdc_multi_getc(uint8_t port) -{ - irqflags_t flags; - int rx_data = 0; - bool b_databit_9; - uint16_t pos; - uint8_t buf_sel; - bool again; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits); - -udi_cdc_getc_process_one_byte: - // Check available data - flags = cpu_irq_save(); - pos = udi_cdc_rx_pos[port]; - buf_sel = udi_cdc_rx_buf_sel[port]; - again = pos >= udi_cdc_rx_buf_nb[port][buf_sel]; - cpu_irq_restore(flags); - while (again) { - if (!udi_cdc_data_running) { - return 0; - } - goto udi_cdc_getc_process_one_byte; - } - - // Read data - rx_data |= udi_cdc_rx_buf[port][buf_sel][pos]; - udi_cdc_rx_pos[port] = pos+1; - - udi_cdc_rx_start(port); - - if (b_databit_9) { - // Receive MSB - b_databit_9 = false; - rx_data = rx_data << 8; - goto udi_cdc_getc_process_one_byte; - } - return rx_data; -} - -int udi_cdc_getc(void) -{ - return udi_cdc_multi_getc(0); -} - -iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size) -{ - irqflags_t flags; - uint8_t *ptr_buf = (uint8_t *)buf; - iram_size_t copy_nb; - uint16_t pos; - uint8_t buf_sel; - bool again; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - -udi_cdc_read_buf_loop_wait: - // Check available data - flags = cpu_irq_save(); - pos = udi_cdc_rx_pos[port]; - buf_sel = udi_cdc_rx_buf_sel[port]; - again = pos >= udi_cdc_rx_buf_nb[port][buf_sel]; - cpu_irq_restore(flags); - while (again) { - if (!udi_cdc_data_running) { - return size; - } - goto udi_cdc_read_buf_loop_wait; - } - - // Read data - copy_nb = udi_cdc_rx_buf_nb[port][buf_sel] - pos; - if (copy_nb>size) { - copy_nb = size; - } - memcpy(ptr_buf, &udi_cdc_rx_buf[port][buf_sel][pos], copy_nb); - udi_cdc_rx_pos[port] += copy_nb; - ptr_buf += copy_nb; - size -= copy_nb; - udi_cdc_rx_start(port); - - if (size) { - goto udi_cdc_read_buf_loop_wait; - } - return 0; -} - -static iram_size_t udi_cdc_multi_read_no_polling(uint8_t port, void* buf, iram_size_t size) -{ - uint8_t *ptr_buf = (uint8_t *)buf; - iram_size_t nb_avail_data; - uint16_t pos; - uint8_t buf_sel; - irqflags_t flags; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - //Data interface not started... exit - if (!udi_cdc_data_running) { - return 0; - } - - //Get number of available data - // Check available data - flags = cpu_irq_save(); // to protect udi_cdc_rx_pos & udi_cdc_rx_buf_sel - pos = udi_cdc_rx_pos[port]; - buf_sel = udi_cdc_rx_buf_sel[port]; - nb_avail_data = udi_cdc_rx_buf_nb[port][buf_sel] - pos; - cpu_irq_restore(flags); - //If the buffer contains less than the requested number of data, - //adjust read size - if(nb_avail_data0) { - memcpy(ptr_buf, &udi_cdc_rx_buf[port][buf_sel][pos], size); - flags = cpu_irq_save(); // to protect udi_cdc_rx_pos - udi_cdc_rx_pos[port] += size; - cpu_irq_restore(flags); - - ptr_buf += size; - udi_cdc_rx_start(port); - } - return(nb_avail_data); -} - -iram_size_t udi_cdc_read_no_polling(void* buf, iram_size_t size) -{ - return udi_cdc_multi_read_no_polling(0, buf, size); -} - -iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size) -{ - return udi_cdc_multi_read_buf(0, buf, size); -} - -iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port) -{ - irqflags_t flags; - iram_size_t buf_sel_nb, retval; - uint8_t buf_sel; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - flags = cpu_irq_save(); - buf_sel = udi_cdc_tx_buf_sel[port]; - buf_sel_nb = udi_cdc_tx_buf_nb[port][buf_sel]; - if (buf_sel_nb == UDI_CDC_TX_BUFFERS) { - if ((!udi_cdc_tx_trans_ongoing[port]) - && (!udi_cdc_tx_both_buf_to_send[port])) { - /* One buffer is full, but the other buffer is not used. - * (not used = transfer on-going) - * then move to the other buffer to store data */ - udi_cdc_tx_both_buf_to_send[port] = true; - udi_cdc_tx_buf_sel[port] = (buf_sel == 0)? 1 : 0; - buf_sel_nb = 0; - } - } - retval = UDI_CDC_TX_BUFFERS - buf_sel_nb; - cpu_irq_restore(flags); - return retval; -} - -iram_size_t udi_cdc_get_free_tx_buffer(void) -{ - return udi_cdc_multi_get_free_tx_buffer(0); -} - -bool udi_cdc_multi_is_tx_ready(uint8_t port) -{ - return (udi_cdc_multi_get_free_tx_buffer(port) != 0); -} - -bool udi_cdc_is_tx_ready(void) -{ - return udi_cdc_multi_is_tx_ready(0); -} - -int udi_cdc_multi_putc(uint8_t port, int value) -{ - irqflags_t flags; - bool b_databit_9; - uint8_t buf_sel; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - b_databit_9 = (9 == udi_cdc_line_coding[port].bDataBits); - -udi_cdc_putc_process_one_byte: - // Check available space - if (!udi_cdc_multi_is_tx_ready(port)) { - if (!udi_cdc_data_running) { - return false; - } - goto udi_cdc_putc_process_one_byte; - } - - // Write value - flags = cpu_irq_save(); - buf_sel = udi_cdc_tx_buf_sel[port]; - udi_cdc_tx_buf[port][buf_sel][udi_cdc_tx_buf_nb[port][buf_sel]++] = value; - cpu_irq_restore(flags); - - if (b_databit_9) { - // Send MSB - b_databit_9 = false; - value = value >> 8; - goto udi_cdc_putc_process_one_byte; - } - return true; -} - -int udi_cdc_putc(int value) -{ - return udi_cdc_multi_putc(0, value); -} - -iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size) -{ - irqflags_t flags; - uint8_t buf_sel; - uint16_t buf_nb; - iram_size_t copy_nb; - uint8_t *ptr_buf = (uint8_t *)buf; - -#if UDI_CDC_PORT_NB == 1 // To optimize code - port = 0; -#endif - - if (9 == udi_cdc_line_coding[port].bDataBits) { - size *=2; - } - -udi_cdc_write_buf_loop_wait: - // Check available space - if (!udi_cdc_multi_is_tx_ready(port)) { - if (!udi_cdc_data_running) { - return size; - } - goto udi_cdc_write_buf_loop_wait; - } - - // Write values - flags = cpu_irq_save(); - buf_sel = udi_cdc_tx_buf_sel[port]; - buf_nb = udi_cdc_tx_buf_nb[port][buf_sel]; - copy_nb = UDI_CDC_TX_BUFFERS - buf_nb; - if (copy_nb > size) { - copy_nb = size; - } - memcpy(&udi_cdc_tx_buf[port][buf_sel][buf_nb], ptr_buf, copy_nb); - udi_cdc_tx_buf_nb[port][buf_sel] = buf_nb + copy_nb; - cpu_irq_restore(flags); - - // Update buffer pointer - ptr_buf = ptr_buf + copy_nb; - size -= copy_nb; - - if (size) { - goto udi_cdc_write_buf_loop_wait; - } - - return 0; -} - -iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size) -{ - return udi_cdc_multi_write_buf(0, buf, size); -} - -//@} diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc.h b/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc.h deleted file mode 100644 index 45c5cef5ae581..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc.h +++ /dev/null @@ -1,810 +0,0 @@ -/** - * \file - * - * \brief USB Device Communication Device Class (CDC) interface definitions. - * - * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_CDC_H_ -#define _UDI_CDC_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_cdc.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi.h" - -// Check the number of port -#ifndef UDI_CDC_PORT_NB -# define UDI_CDC_PORT_NB 1 -#endif -#if (UDI_CDC_PORT_NB < 1) || (UDI_CDC_PORT_NB > 7) -# error UDI_CDC_PORT_NB must be between 1 and 7 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup udi_cdc_group_udc - * @{ - */ - -//! Global structure which contains standard UDI API for UDC -extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_comm; -extern UDC_DESC_STORAGE udi_api_t udi_api_cdc_data; -//@} - -/** - * \ingroup udi_cdc_group - * \defgroup udi_cdc_group_desc USB interface descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - */ -//@{ - -/** - * \brief Communication Class interface descriptor - * - * Interface descriptor with associated functional and endpoint - * descriptors for the CDC Communication Class interface. - */ -typedef struct { - //! Standard interface descriptor - usb_iface_desc_t iface; - //! CDC Header functional descriptor - usb_cdc_hdr_desc_t header; - //! CDC Abstract Control Model functional descriptor - usb_cdc_acm_desc_t acm; - //! CDC Union functional descriptor - usb_cdc_union_desc_t union_desc; - //! CDC Call Management functional descriptor - usb_cdc_call_mgmt_desc_t call_mgmt; - //! Notification endpoint descriptor - usb_ep_desc_t ep_notify; -} udi_cdc_comm_desc_t; - - -/** - * \brief Data Class interface descriptor - * - * Interface descriptor with associated endpoint descriptors for the - * CDC Data Class interface. - */ -typedef struct { - //! Standard interface descriptor - usb_iface_desc_t iface; - //! Data IN/OUT endpoint descriptors - usb_ep_desc_t ep_in; - usb_ep_desc_t ep_out; -} udi_cdc_data_desc_t; - - -//! CDC communication endpoints size for all speeds -#define UDI_CDC_COMM_EP_SIZE 64 -//! CDC data endpoints size for FS speed (8B, 16B, 32B, 64B) -#define UDI_CDC_DATA_EPS_FS_SIZE 64 -//! CDC data endpoints size for HS speed (512B only) -#define UDI_CDC_DATA_EPS_HS_SIZE 512 - -/** - * \name Content of interface descriptors - * Up to 7 CDC interfaces can be implemented on a USB device. - */ -//@{ -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_0 -#define UDI_CDC_IAD_STRING_ID_0 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_0 -#define UDI_CDC_COMM_STRING_ID_0 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_0 -#define UDI_CDC_DATA_STRING_ID_0 0 -#endif -#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0) -#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0) -#define UDI_CDC_DATA_DESC_0_FS UDI_CDC_DATA_DESC_FS(0) -#define UDI_CDC_DATA_DESC_0_HS UDI_CDC_DATA_DESC_HS(0) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_1 -#define UDI_CDC_IAD_STRING_ID_1 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_1 -#define UDI_CDC_COMM_STRING_ID_1 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_1 -#define UDI_CDC_DATA_STRING_ID_1 0 -#endif -#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1) -#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1) -#define UDI_CDC_DATA_DESC_1_FS UDI_CDC_DATA_DESC_FS(1) -#define UDI_CDC_DATA_DESC_1_HS UDI_CDC_DATA_DESC_HS(1) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_2 -#define UDI_CDC_IAD_STRING_ID_2 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_2 -#define UDI_CDC_COMM_STRING_ID_2 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_2 -#define UDI_CDC_DATA_STRING_ID_2 0 -#endif -#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2) -#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2) -#define UDI_CDC_DATA_DESC_2_FS UDI_CDC_DATA_DESC_FS(2) -#define UDI_CDC_DATA_DESC_2_HS UDI_CDC_DATA_DESC_HS(2) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_3 -#define UDI_CDC_IAD_STRING_ID_3 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_3 -#define UDI_CDC_COMM_STRING_ID_3 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_3 -#define UDI_CDC_DATA_STRING_ID_3 0 -#endif -#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3) -#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3) -#define UDI_CDC_DATA_DESC_3_FS UDI_CDC_DATA_DESC_FS(3) -#define UDI_CDC_DATA_DESC_3_HS UDI_CDC_DATA_DESC_HS(3) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_4 -#define UDI_CDC_IAD_STRING_ID_4 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_4 -#define UDI_CDC_COMM_STRING_ID_4 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_4 -#define UDI_CDC_DATA_STRING_ID_4 0 -#endif -#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4) -#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4) -#define UDI_CDC_DATA_DESC_4_FS UDI_CDC_DATA_DESC_FS(4) -#define UDI_CDC_DATA_DESC_4_HS UDI_CDC_DATA_DESC_HS(4) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_5 -#define UDI_CDC_IAD_STRING_ID_5 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_5 -#define UDI_CDC_COMM_STRING_ID_5 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_5 -#define UDI_CDC_DATA_STRING_ID_5 0 -#endif -#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5) -#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5) -#define UDI_CDC_DATA_DESC_5_FS UDI_CDC_DATA_DESC_FS(5) -#define UDI_CDC_DATA_DESC_5_HS UDI_CDC_DATA_DESC_HS(5) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_6 -#define UDI_CDC_IAD_STRING_ID_6 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_6 -#define UDI_CDC_COMM_STRING_ID_6 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_6 -#define UDI_CDC_DATA_STRING_ID_6 0 -#endif -#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6) -#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6) -#define UDI_CDC_DATA_DESC_6_FS UDI_CDC_DATA_DESC_FS(6) -#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6) -//@} - - -//! Content of CDC IAD interface descriptor for all speeds -#define UDI_CDC_IAD_DESC(port) { \ - .bLength = sizeof(usb_iad_desc_t),\ - .bDescriptorType = USB_DT_IAD,\ - .bInterfaceCount = 2,\ - .bFunctionClass = CDC_CLASS_COMM,\ - .bFunctionSubClass = CDC_SUBCLASS_ACM,\ - .bFunctionProtocol = CDC_PROTOCOL_V25TER,\ - .bFirstInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\ - .iFunction = UDI_CDC_IAD_STRING_ID_##port,\ - } - -//! Content of CDC COMM interface descriptor for all speeds -#define UDI_CDC_COMM_DESC(port) { \ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 1,\ - .iface.bInterfaceClass = CDC_CLASS_COMM,\ - .iface.bInterfaceSubClass = CDC_SUBCLASS_ACM,\ - .iface.bInterfaceProtocol = CDC_PROTOCOL_V25TER,\ - .header.bFunctionLength = sizeof(usb_cdc_hdr_desc_t),\ - .header.bDescriptorType = CDC_CS_INTERFACE,\ - .header.bDescriptorSubtype = CDC_SCS_HEADER,\ - .header.bcdCDC = LE16(0x0110),\ - .call_mgmt.bFunctionLength = sizeof(usb_cdc_call_mgmt_desc_t),\ - .call_mgmt.bDescriptorType = CDC_CS_INTERFACE,\ - .call_mgmt.bDescriptorSubtype = CDC_SCS_CALL_MGMT,\ - .call_mgmt.bmCapabilities = \ - CDC_CALL_MGMT_SUPPORTED | CDC_CALL_MGMT_OVER_DCI,\ - .acm.bFunctionLength = sizeof(usb_cdc_acm_desc_t),\ - .acm.bDescriptorType = CDC_CS_INTERFACE,\ - .acm.bDescriptorSubtype = CDC_SCS_ACM,\ - .acm.bmCapabilities = CDC_ACM_SUPPORT_LINE_REQUESTS,\ - .union_desc.bFunctionLength = sizeof(usb_cdc_union_desc_t),\ - .union_desc.bDescriptorType = CDC_CS_INTERFACE,\ - .union_desc.bDescriptorSubtype= CDC_SCS_UNION,\ - .ep_notify.bLength = sizeof(usb_ep_desc_t),\ - .ep_notify.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_notify.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep_notify.wMaxPacketSize = LE16(UDI_CDC_COMM_EP_SIZE),\ - .ep_notify.bInterval = 0x10,\ - .ep_notify.bEndpointAddress = UDI_CDC_COMM_EP_##port,\ - .iface.bInterfaceNumber = UDI_CDC_COMM_IFACE_NUMBER_##port,\ - .call_mgmt.bDataInterface = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .union_desc.bMasterInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\ - .union_desc.bSlaveInterface0 = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .iface.iInterface = UDI_CDC_COMM_STRING_ID_##port,\ - } - -//! Content of CDC DATA interface descriptors -#define UDI_CDC_DATA_DESC_COMMON \ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 2,\ - .iface.bInterfaceClass = CDC_CLASS_DATA,\ - .iface.bInterfaceSubClass = 0,\ - .iface.bInterfaceProtocol = 0,\ - .ep_in.bLength = sizeof(usb_ep_desc_t),\ - .ep_in.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_in.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_in.bInterval = 0,\ - .ep_out.bLength = sizeof(usb_ep_desc_t),\ - .ep_out.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_out.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_out.bInterval = 0, - -#define UDI_CDC_DATA_DESC_FS(port) { \ - UDI_CDC_DATA_DESC_COMMON \ - .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\ - .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\ - .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\ - .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\ - .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\ - } - -#define UDI_CDC_DATA_DESC_HS(port) { \ - UDI_CDC_DATA_DESC_COMMON \ - .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\ - .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\ - .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\ - .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\ - .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\ - } - -//@} - -/** - * \ingroup udi_group - * \defgroup udi_cdc_group USB Device Interface (UDI) for Communication Class Device (CDC) - * - * Common APIs used by high level application to use this USB class. - * - * These routines are used to transfer and control data - * to/from USB CDC endpoint. - * - * See \ref udi_cdc_quickstart. - * @{ - */ - -/** - * \name Interface for application with single CDC interface support - */ -//@{ - -/** - * \brief Notify a state change of DCD signal - * - * \param b_set DCD is enabled if true, else disabled - */ -void udi_cdc_ctrl_signal_dcd(bool b_set); - -/** - * \brief Notify a state change of DSR signal - * - * \param b_set DSR is enabled if true, else disabled - */ -void udi_cdc_ctrl_signal_dsr(bool b_set); - -/** - * \brief Notify a framing error - */ -void udi_cdc_signal_framing_error(void); - -/** - * \brief Notify a parity error - */ -void udi_cdc_signal_parity_error(void); - -/** - * \brief Notify a overrun - */ -void udi_cdc_signal_overrun(void); - -/** - * \brief Gets the number of byte received - * - * \return the number of data available - */ -iram_size_t udi_cdc_get_nb_received_data(void); - -/** - * \brief This function checks if a character has been received on the CDC line - * - * \return \c 1 if a byte is ready to be read. - */ -bool udi_cdc_is_rx_ready(void); - -/** - * \brief Waits and gets a value on CDC line - * - * \return value read on CDC line - */ -int udi_cdc_getc(void); - -/** - * \brief Reads a RAM buffer on CDC line - * - * \param buf Values read - * \param size Number of value read - * - * \return the number of data remaining - */ -iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size); - -/** - * \brief Non polling reads of a up to 'size' data from CDC line - * - * \param port Communication port number to manage - * \param buf Buffer where to store read data - * \param size Maximum number of data to read (size of buffer) - * - * \return the number of data effectively read - */ -iram_size_t udi_cdc_read_no_polling(void* buf, iram_size_t size); - -/** - * \brief Gets the number of free byte in TX buffer - * - * \return the number of free byte in TX buffer - */ -iram_size_t udi_cdc_get_free_tx_buffer(void); - -/** - * \brief This function checks if a new character sent is possible - * The type int is used to support scanf redirection from compiler LIB. - * - * \return \c 1 if a new character can be sent - */ -bool udi_cdc_is_tx_ready(void); - -/** - * \brief Puts a byte on CDC line - * The type int is used to support printf redirection from compiler LIB. - * - * \param value Value to put - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -int udi_cdc_putc(int value); - -/** - * \brief Writes a RAM buffer on CDC line - * - * \param buf Values to write - * \param size Number of value to write - * - * \return the number of data remaining - */ -iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size); -//@} - -/** - * \name Interface for application with multi CDC interfaces support - */ -//@{ - -/** - * \brief Notify a state change of DCD signal - * - * \param port Communication port number to manage - * \param b_set DCD is enabled if true, else disabled - */ -void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set); - -/** - * \brief Notify a state change of DSR signal - * - * \param port Communication port number to manage - * \param b_set DSR is enabled if true, else disabled - */ -void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set); - -/** - * \brief Notify a framing error - * - * \param port Communication port number to manage - */ -void udi_cdc_multi_signal_framing_error(uint8_t port); - -/** - * \brief Notify a parity error - * - * \param port Communication port number to manage - */ -void udi_cdc_multi_signal_parity_error(uint8_t port); - -/** - * \brief Notify a overrun - * - * \param port Communication port number to manage - */ -void udi_cdc_multi_signal_overrun(uint8_t port); - -/** - * \brief Gets the number of byte received - * - * \param port Communication port number to manage - * - * \return the number of data available - */ -iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port); - -/** - * \brief This function checks if a character has been received on the CDC line - * - * \param port Communication port number to manage - * - * \return \c 1 if a byte is ready to be read. - */ -bool udi_cdc_multi_is_rx_ready(uint8_t port); - -/** - * \brief Waits and gets a value on CDC line - * - * \param port Communication port number to manage - * - * \return value read on CDC line - */ -int udi_cdc_multi_getc(uint8_t port); - -/** - * \brief Reads a RAM buffer on CDC line - * - * \param port Communication port number to manage - * \param buf Values read - * \param size Number of values read - * - * \return the number of data remaining - */ -iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size); - -/** - * \brief Gets the number of free byte in TX buffer - * - * \param port Communication port number to manage - * - * \return the number of free byte in TX buffer - */ -iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port); - -/** - * \brief This function checks if a new character sent is possible - * The type int is used to support scanf redirection from compiler LIB. - * - * \param port Communication port number to manage - * - * \return \c 1 if a new character can be sent - */ -bool udi_cdc_multi_is_tx_ready(uint8_t port); - -/** - * \brief Puts a byte on CDC line - * The type int is used to support printf redirection from compiler LIB. - * - * \param port Communication port number to manage - * \param value Value to put - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -int udi_cdc_multi_putc(uint8_t port, int value); - -/** - * \brief Writes a RAM buffer on CDC line - * - * \param port Communication port number to manage - * \param buf Values to write - * \param size Number of value to write - * - * \return the number of data remaining - */ -iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size); -//@} - -//@} - -/** - * \page udi_cdc_quickstart Quick start guide for USB device Communication Class Device module (UDI CDC) - * - * This is the quick start guide for the \ref udi_cdc_group - * "USB device interface CDC module (UDI CDC)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section udi_cdc_basic_use_case Basic use case - * In this basic use case, the "USB CDC (Single Interface Device)" module is used - * with only one communication port. - * The "USB CDC (Composite Device)" module usage is described in \ref udi_cdc_use_cases - * "Advanced use cases". - * - * \section udi_cdc_basic_use_case_setup Setup steps - * \subsection udi_cdc_basic_use_case_setup_prereq Prerequisites - * \copydetails udc_basic_use_case_setup_prereq - * \subsection udi_cdc_basic_use_case_setup_code Example code - * \copydetails udc_basic_use_case_setup_code - * \subsection udi_cdc_basic_use_case_setup_flow Workflow - * \copydetails udc_basic_use_case_setup_flow - * - * \section udi_cdc_basic_use_case_usage Usage steps - * - * \subsection udi_cdc_basic_use_case_usage_code Example code - * Content of conf_usb.h: - * \code - #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() - extern bool my_callback_cdc_enable(void); - #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() - extern void my_callback_cdc_disable(void); - #define UDI_CDC_LOW_RATE - - #define UDI_CDC_DEFAULT_RATE 115200 - #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 - #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE - #define UDI_CDC_DEFAULT_DATABITS 8 - - #include "udi_cdc_conf.h" // At the end of conf_usb.h file -\endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_cdc_transfert = false; - bool my_callback_cdc_enable(void) - { - my_flag_autorize_cdc_transfert = true; - return true; - } - void my_callback_cdc_disable(void) - { - my_flag_autorize_cdc_transfert = false; - } - - void task(void) - { - if (my_flag_autorize_cdc_transfert) { - udi_cdc_putc('A'); - udi_cdc_getc(); - } - } -\endcode - * - * \subsection udi_cdc_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration, - * which is the USB device CDC configuration: - * - \code #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for CDC \endcode - * \note The USB serial number is mandatory when a CDC interface is used. - * - \code #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() - extern bool my_callback_cdc_enable(void); \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB CDC interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_CDC_ENABLE_EXT() callback function is called and return true. - * Thus, when this event is received, the data transfer on CDC interface are authorized. - * - \code #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() - extern void my_callback_cdc_disable(void); \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_CDC_DISABLE_EXT() callback function - * is called. Thus, the data transfer must be stopped on CDC interface. - * - \code #define UDI_CDC_LOW_RATE \endcode - * \note Define it when the transfer CDC Device to Host is a low rate - * (<512000 bauds) to reduce CDC buffers size. - * - \code #define UDI_CDC_DEFAULT_RATE 115200 - #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 - #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE - #define UDI_CDC_DEFAULT_DATABITS 8 \endcode - * \note Default configuration of communication port at startup. - * -# Send or wait data on CDC line: - * - \code // Waits and gets a value on CDC line - int udi_cdc_getc(void); - // Reads a RAM buffer on CDC line - iram_size_t udi_cdc_read_buf(int* buf, iram_size_t size); - // Puts a byte on CDC line - int udi_cdc_putc(int value); - // Writes a RAM buffer on CDC line - iram_size_t udi_cdc_write_buf(const int* buf, iram_size_t size); \endcode - * - * \section udi_cdc_use_cases Advanced use cases - * For more advanced use of the UDI CDC module, see the following use cases: - * - \subpage udi_cdc_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_4 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - */ - -/** - * \page udi_cdc_use_case_composite CDC in a composite device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB CDC (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB HID Mouse (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_cdc_use_case_composite_setup Setup steps - * For the setup code of this use case to work, the - * \ref udi_cdc_basic_use_case "basic use case" must be followed. - * - * \section udi_cdc_use_case_composite_usage Usage steps - * - * \subsection udi_cdc_use_case_composite_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+2) - #define USB_DEVICE_MAX_EP (X+3) - - #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX - #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX - #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint - #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0 - #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 - - #define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - ... -\endcode - * - * \subsection udi_cdc_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * - \code // Endpoint control size, This must be: - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 2 for CDC. - #define USB_DEVICE_NB_INTERFACE (X+2) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 3 for CDC. - #define USB_DEVICE_MAX_EP (X+3) \endcode - * -# Ensure that conf_usb.h contains the description of - * composite device: - * - \code // The endpoint numbers chosen by you for the CDC. - // The endpoint numbers starting from 1. - #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX - #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX - #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint - // The interface index of an interface starting from 0 - #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0 - #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * - \code // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - ... \endcode - * - \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines.\n - * Also, the CDC requires a USB Interface Association Descriptor (IAD) for - * composite device. - */ - -#ifdef __cplusplus -} -#endif -#endif // _UDI_CDC_H_ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_conf.h b/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_conf.h deleted file mode 100644 index b99d6111713a9..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_conf.h +++ /dev/null @@ -1,156 +0,0 @@ -/** - * \file - * - * \brief Default CDC configuration for a USB Device with a single interface - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_CDC_CONF_H_ -#define _UDI_CDC_CONF_H_ - -#include "usb_protocol_cdc.h" -#include "conf_usb.h" - -#ifndef UDI_CDC_PORT_NB -# define UDI_CDC_PORT_NB 1 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup udi_cdc_group_single_desc - * @{ - */ - -//! Control endpoint size (Endpoint 0) -#define USB_DEVICE_EP_CTRL_SIZE 64 - -#if XMEGA -/** - * \name Endpoint configuration on XMEGA - * The XMEGA supports a IN and OUT endpoint with the same number endpoint, - * thus XMEGA can support up to 7 CDC interfaces. - */ -//@{ -#define UDI_CDC_DATA_EP_IN_0 ( 1 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 ( 2 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_0 ( 2 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_1 ( 3 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_1 ( 4 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_1 ( 4 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_2 ( 5 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_2 ( 6 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_2 ( 6 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_3 ( 7 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_3 ( 8 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_3 ( 8 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_4 ( 9 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_4 (10 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_4 (10 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_5 (11 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_5 (12 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_5 (12 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_6 (13 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_6 (14 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_6 (14 | USB_EP_DIR_IN) // Notify endpoint -//! 2 endpoints numbers used per CDC interface -#define USB_DEVICE_MAX_EP (2*UDI_CDC_PORT_NB) -//@} - -#else - -/** - * \name Default endpoint configuration - * The USBB, UDP, UDPHS and UOTGHS interfaces can support up to 2 CDC interfaces. - */ -//@{ -# if UDI_CDC_PORT_NB > 2 -# error USBB, UDP, UDPHS and UOTGHS interfaces have not enought endpoints. -# endif -#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -# if SAM3U - /* For 3U max endpoint size of 4 is 64, use 5 and 6 as bulk tx and rx */ -# define UDI_CDC_DATA_EP_IN_1 (6 | USB_EP_DIR_IN) // TX -# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX -# define UDI_CDC_COMM_EP_1 (4 | USB_EP_DIR_IN) // Notify -# else -# define UDI_CDC_DATA_EP_IN_1 (4 | USB_EP_DIR_IN) // TX -# define UDI_CDC_DATA_EP_OUT_1 (5 | USB_EP_DIR_OUT) // RX -# define UDI_CDC_COMM_EP_1 (6 | USB_EP_DIR_IN) // Notify -# endif -//! 3 endpoints used per CDC interface -#undef USB_DEVICE_MAX_EP // undefine this definition in header file -#define USB_DEVICE_MAX_EP (3*UDI_CDC_PORT_NB) -//@} - -#endif - -/** - * \name Default Interface numbers - */ -//@{ -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 -#define UDI_CDC_COMM_IFACE_NUMBER_1 2 -#define UDI_CDC_DATA_IFACE_NUMBER_1 3 -#define UDI_CDC_COMM_IFACE_NUMBER_2 4 -#define UDI_CDC_DATA_IFACE_NUMBER_2 5 -#define UDI_CDC_COMM_IFACE_NUMBER_3 6 -#define UDI_CDC_DATA_IFACE_NUMBER_3 7 -#define UDI_CDC_COMM_IFACE_NUMBER_4 8 -#define UDI_CDC_DATA_IFACE_NUMBER_4 9 -#define UDI_CDC_COMM_IFACE_NUMBER_5 10 -#define UDI_CDC_DATA_IFACE_NUMBER_5 11 -#define UDI_CDC_COMM_IFACE_NUMBER_6 12 -#define UDI_CDC_DATA_IFACE_NUMBER_6 13 -//@} - -//@} - -#ifdef __cplusplus -} -#endif -#endif // _UDI_CDC_CONF_H_ diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_desc.c b/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_desc.c deleted file mode 100644 index 46e72c290f38e..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_desc.c +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief Default descriptors for a USB Device with a single interface CDC - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi_cdc.h" - - -/** - * \defgroup udi_cdc_group_single_desc USB device descriptors for a single interface - * - * The following structures provide the USB device descriptors required for - * USB Device with a single interface CDC. - * - * It is ready to use and do not require more definition. - * - * @{ - */ - -//! Two interfaces for a CDC device -#define USB_DEVICE_NB_INTERFACE (2*UDI_CDC_PORT_NB) - -#ifdef USB_DEVICE_LPM_SUPPORT -# define USB_VERSION USB_V2_1 -#else -# define USB_VERSION USB_V2_0 -#endif - -//! USB Device Descriptor -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = { - .bLength = sizeof(usb_dev_desc_t), - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = LE16(USB_VERSION), -#if UDI_CDC_PORT_NB > 1 - .bDeviceClass = 0, -#else - .bDeviceClass = CDC_CLASS_DEVICE, -#endif - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .idVendor = LE16(USB_DEVICE_VENDOR_ID), - .idProduct = LE16(USB_DEVICE_PRODUCT_ID), - .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8) - | USB_DEVICE_MINOR_VERSION), -#ifdef USB_DEVICE_MANUFACTURE_NAME - .iManufacturer = 1, -#else - .iManufacturer = 0, // No manufacture string -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - .iProduct = 2, -#else - .iProduct = 0, // No product string -#endif -#ifdef USB_DEVICE_SERIAL_NAME - .iSerialNumber = 3, -#else - .iSerialNumber = 0, // No serial string -#endif - .bNumConfigurations = 1 -}; - - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Qualifier Descriptor for HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = { - .bLength = sizeof(usb_dev_qual_desc_t), - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = LE16(USB_VERSION), -#if UDI_CDC_PORT_NB > 1 - .bDeviceClass = 0, -#else - .bDeviceClass = CDC_CLASS_DEVICE, -#endif - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .bNumConfigurations = 1 -}; -#endif - -#ifdef USB_DEVICE_LPM_SUPPORT -//! USB Device Qualifier Descriptor -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_lpm_desc_t udc_device_lpm = { - .bos.bLength = sizeof(usb_dev_bos_desc_t), - .bos.bDescriptorType = USB_DT_BOS, - .bos.wTotalLength = LE16(sizeof(usb_dev_bos_desc_t) + sizeof(usb_dev_capa_ext_desc_t)), - .bos.bNumDeviceCaps = 1, - .capa_ext.bLength = sizeof(usb_dev_capa_ext_desc_t), - .capa_ext.bDescriptorType = USB_DT_DEVICE_CAPABILITY, - .capa_ext.bDevCapabilityType = USB_DC_USB20_EXTENSION, - .capa_ext.bmAttributes = USB_DC_EXT_LPM, -}; -#endif - -//! Structure for USB Device Configuration Descriptor -COMPILER_PACK_SET(1) -typedef struct { - usb_conf_desc_t conf; -#if UDI_CDC_PORT_NB == 1 - udi_cdc_comm_desc_t udi_cdc_comm_0; - udi_cdc_data_desc_t udi_cdc_data_0; -#else -# define UDI_CDC_DESC_STRUCTURE(index, unused) \ - usb_iad_desc_t udi_cdc_iad_##index; \ - udi_cdc_comm_desc_t udi_cdc_comm_##index; \ - udi_cdc_data_desc_t udi_cdc_data_##index; - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_STRUCTURE, ~) -# undef UDI_CDC_DESC_STRUCTURE -#endif -} udc_desc_t; -COMPILER_PACK_RESET() - -//! USB Device Configuration Descriptor filled for full and high speed -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_desc_t udc_desc_fs = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), -#if UDI_CDC_PORT_NB == 1 - .udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0, - .udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_FS, -#else -# define UDI_CDC_DESC_FS(index, unused) \ - .udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index,\ - .udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index,\ - .udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_FS, - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_FS, ~) -# undef UDI_CDC_DESC_FS -#endif -}; - -#ifdef USB_DEVICE_HS_SUPPORT -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_desc_t udc_desc_hs = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), -#if UDI_CDC_PORT_NB == 1 - .udi_cdc_comm_0 = UDI_CDC_COMM_DESC_0, - .udi_cdc_data_0 = UDI_CDC_DATA_DESC_0_HS, -#else -# define UDI_CDC_DESC_HS(index, unused) \ - .udi_cdc_iad_##index = UDI_CDC_IAD_DESC_##index, \ - .udi_cdc_comm_##index = UDI_CDC_COMM_DESC_##index, \ - .udi_cdc_data_##index = UDI_CDC_DATA_DESC_##index##_HS, - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_DESC_HS, ~) -# undef UDI_CDC_DESC_HS -#endif -}; -#endif - -/** - * \name UDC structures which content all USB Device definitions - */ -//@{ - -//! Associate an UDI for each USB interface -UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = { -# define UDI_CDC_API(index, unused) \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, - MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_API, ~) -# undef UDI_CDC_API -}; - -//! Add UDI with USB Descriptors FS & HS -UDC_DESC_STORAGE udc_config_speed_t udc_config_fs[1] = { { - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs, - .udi_apis = udi_apis, -}}; -#ifdef USB_DEVICE_HS_SUPPORT -UDC_DESC_STORAGE udc_config_speed_t udc_config_hs[1] = { { - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs, - .udi_apis = udi_apis, -}}; -#endif - -//! Add all information about USB Device in global structure for UDC -UDC_DESC_STORAGE udc_config_t udc_config = { - .confdev_lsfs = &udc_device_desc, - .conf_lsfs = udc_config_fs, -#ifdef USB_DEVICE_HS_SUPPORT - .confdev_hs = &udc_device_desc, - .qualifier = &udc_device_qual, - .conf_hs = udc_config_hs, -#endif -#ifdef USB_DEVICE_LPM_SUPPORT - .conf_bos = &udc_device_lpm.bos, -#else - .conf_bos = NULL, -#endif -}; - -//@} -//@} diff --git a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_doc.h b/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_doc.h deleted file mode 100644 index 9ba6ada9913fb..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/device/udi_cdc_doc.h +++ /dev/null @@ -1,894 +0,0 @@ -/** - * \file - * - * \brief USB Device Communication Device Class (CDC) interface documentation. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup asfdoc_udi_cdc_group USB Device Interface (UDI) for Communication Class Device (CDC) - * - * USB Device Interface (UDI) for Communication Class Device (CDC) provides an - * interface for the configuration and management of USB CDC serial device. - * - * The outline of this documentation is as follows: - * - \ref asfdoc_udi_cdc_api_overview - * - \ref asfdoc_udi_cdc_exqsg - * - \ref asfdoc_udi_cdc_config_examples - * - * For more details for Atmel® Software Framework (ASF) USB Device Stack and - * USB Device CDC, refer to following application notes: - * - - * AVR4900: ASF - USB Device Stack - * - - * AVR4907: ASF - USB Device CDC Application - * - - * AVR4920: ASF - USB Device Stack - Compliance and Performance Figures - * - - * AVR4921: ASF - USB Device Stack Differences between ASF V1 and V2 - * - * \section asfdoc_udi_cdc_api_overview API Overview - * @{ - */ - -/** - * \brief Communication Class interface descriptor - * - * Interface descriptor with associated functional and endpoint - * descriptors for the CDC Communication Class interface. - */ -typedef struct { - /** Standard interface descriptor */ - usb_iface_desc_t iface; - /** CDC Header functional descriptor */ - usb_cdc_hdr_desc_t header; - /** CDC Abstract Control Model functional descriptor */ - usb_cdc_acm_desc_t acm; - /** CDC Union functional descriptor */ - usb_cdc_union_desc_t union_desc; - /** CDC Call Management functional descriptor */ - usb_cdc_call_mgmt_desc_t call_mgmt; - /** Notification endpoint descriptor */ - usb_ep_desc_t ep_notify; -} udi_cdc_comm_desc_t; - -/** - * \brief Data Class interface descriptor - * - * Interface descriptor with associated endpoint descriptors for the - * CDC Data Class interface. - */ -typedef struct { - /** Standard interface descriptor */ - usb_iface_desc_t iface; - /** Data IN endpoint descriptors */ - usb_ep_desc_t ep_in; - /** Data OUT endpoint descriptors */ - usb_ep_desc_t ep_out; -} udi_cdc_data_desc_t; - -/** CDC communication endpoints size for all speeds. */ -/* - * Support and FAQ: visit Atmel Support - */ -#define UDI_CDC_COMM_EP_SIZE 64 -/** CDC data endpoints size for FS speed (8B, 16B, 32B, 64B). */ -#define UDI_CDC_DATA_EPS_FS_SIZE 64 -/** CDC data endpoints size for HS speed (512B only). */ -#define UDI_CDC_DATA_EPS_HS_SIZE 512 - -/** - * \name Content of Interface Descriptors - * Up to seven CDC interfaces can be implemented on a USB device. - * @{ - */ - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_0 -/** No string associated to IAD interface. */ -#define UDI_CDC_IAD_STRING_ID_0 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_0 -/** No string associated to COMM interface. */ -#define UDI_CDC_COMM_STRING_ID_0 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_0 -/** No string associated to DATA interface. */ -#define UDI_CDC_DATA_STRING_ID_0 0 -#endif -/** IAD descriptor for port 0. */ -#define UDI_CDC_IAD_DESC_0 UDI_CDC_IAD_DESC(0) -/** COMM descriptors for port 0. */ -#define UDI_CDC_COMM_DESC_0 UDI_CDC_COMM_DESC(0) -/** DATA descriptor for port 0 of a full speed device. */ -#define UDI_CDC_DATA_DESC_0_FS UDI_CDC_DATA_DESC_FS(0) -/** DATA descriptor for port 0 of a high speed device. */ -#define UDI_CDC_DATA_DESC_0_HS UDI_CDC_DATA_DESC_HS(0) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_1 -/** No string associated to IAD interface. */ -#define UDI_CDC_IAD_STRING_ID_1 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_1 -/** No string associated to COMM interface. */ -#define UDI_CDC_COMM_STRING_ID_1 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_1 -#define UDI_CDC_DATA_STRING_ID_1 0 -#endif -#define UDI_CDC_IAD_DESC_1 UDI_CDC_IAD_DESC(1) -#define UDI_CDC_COMM_DESC_1 UDI_CDC_COMM_DESC(1) -#define UDI_CDC_DATA_DESC_1_FS UDI_CDC_DATA_DESC_FS(1) -#define UDI_CDC_DATA_DESC_1_HS UDI_CDC_DATA_DESC_HS(1) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_2 -/** No string associated to IAD interface. */ -#define UDI_CDC_IAD_STRING_ID_2 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_2 -/** No string associated to COMM interface. */ -#define UDI_CDC_COMM_STRING_ID_2 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_2 -#define UDI_CDC_DATA_STRING_ID_2 0 -#endif -#define UDI_CDC_IAD_DESC_2 UDI_CDC_IAD_DESC(2) -#define UDI_CDC_COMM_DESC_2 UDI_CDC_COMM_DESC(2) -#define UDI_CDC_DATA_DESC_2_FS UDI_CDC_DATA_DESC_FS(2) -#define UDI_CDC_DATA_DESC_2_HS UDI_CDC_DATA_DESC_HS(2) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_3 -/** No string associated to IAD interface. */ -#define UDI_CDC_IAD_STRING_ID_3 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_3 -/** No string associated to COMM interface. */ -#define UDI_CDC_COMM_STRING_ID_3 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_3 -#define UDI_CDC_DATA_STRING_ID_3 0 -#endif -#define UDI_CDC_IAD_DESC_3 UDI_CDC_IAD_DESC(3) -#define UDI_CDC_COMM_DESC_3 UDI_CDC_COMM_DESC(3) -#define UDI_CDC_DATA_DESC_3_FS UDI_CDC_DATA_DESC_FS(3) -#define UDI_CDC_DATA_DESC_3_HS UDI_CDC_DATA_DESC_HS(3) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_4 -/** No string associated to IAD interface. */ -#define UDI_CDC_IAD_STRING_ID_4 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_4 -/** No string associated to COMM interface. */ -#define UDI_CDC_COMM_STRING_ID_4 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_4 -#define UDI_CDC_DATA_STRING_ID_4 0 -#endif -#define UDI_CDC_IAD_DESC_4 UDI_CDC_IAD_DESC(4) -#define UDI_CDC_COMM_DESC_4 UDI_CDC_COMM_DESC(4) -#define UDI_CDC_DATA_DESC_4_FS UDI_CDC_DATA_DESC_FS(4) -#define UDI_CDC_DATA_DESC_4_HS UDI_CDC_DATA_DESC_HS(4) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_5 -/** No string associated to IAD interface. */ -#define UDI_CDC_IAD_STRING_ID_5 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_5 -/** No string associated to COMM interface. */ -#define UDI_CDC_COMM_STRING_ID_5 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_5 -#define UDI_CDC_DATA_STRING_ID_5 0 -#endif -#define UDI_CDC_IAD_DESC_5 UDI_CDC_IAD_DESC(5) -#define UDI_CDC_COMM_DESC_5 UDI_CDC_COMM_DESC(5) -#define UDI_CDC_DATA_DESC_5_FS UDI_CDC_DATA_DESC_FS(5) -#define UDI_CDC_DATA_DESC_5_HS UDI_CDC_DATA_DESC_HS(5) - -//! By default no string associated to these interfaces -#ifndef UDI_CDC_IAD_STRING_ID_6 -/** No string associated to IAD interface. */ -#define UDI_CDC_IAD_STRING_ID_6 0 -#endif -#ifndef UDI_CDC_COMM_STRING_ID_6 -#define UDI_CDC_COMM_STRING_ID_6 0 -#endif -#ifndef UDI_CDC_DATA_STRING_ID_6 -#define UDI_CDC_DATA_STRING_ID_6 0 -#endif -#define UDI_CDC_IAD_DESC_6 UDI_CDC_IAD_DESC(6) -#define UDI_CDC_COMM_DESC_6 UDI_CDC_COMM_DESC(6) -#define UDI_CDC_DATA_DESC_6_FS UDI_CDC_DATA_DESC_FS(6) -#define UDI_CDC_DATA_DESC_6_HS UDI_CDC_DATA_DESC_HS(6) -//@} - -/** Content of CDC IAD interface descriptor for all speeds. */ -#define UDI_CDC_IAD_DESC(port) { \ - .bLength = sizeof(usb_iad_desc_t),\ - .bDescriptorType = USB_DT_IAD,\ - .bInterfaceCount = 2,\ - .bFunctionClass = CDC_CLASS_COMM,\ - .bFunctionSubClass = CDC_SUBCLASS_ACM,\ - .bFunctionProtocol = CDC_PROTOCOL_V25TER,\ - .bFirstInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\ - .iFunction = UDI_CDC_IAD_STRING_ID_##port,\ - } - -/** Content of CDC COMM interface descriptor for all speeds. */ -#define UDI_CDC_COMM_DESC(port) { \ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 1,\ - .iface.bInterfaceClass = CDC_CLASS_COMM,\ - .iface.bInterfaceSubClass = CDC_SUBCLASS_ACM,\ - .iface.bInterfaceProtocol = CDC_PROTOCOL_V25TER,\ - .header.bFunctionLength = sizeof(usb_cdc_hdr_desc_t),\ - .header.bDescriptorType = CDC_CS_INTERFACE,\ - .header.bDescriptorSubtype = CDC_SCS_HEADER,\ - .header.bcdCDC = LE16(0x0110),\ - .call_mgmt.bFunctionLength = sizeof(usb_cdc_call_mgmt_desc_t),\ - .call_mgmt.bDescriptorType = CDC_CS_INTERFACE,\ - .call_mgmt.bDescriptorSubtype = CDC_SCS_CALL_MGMT,\ - .call_mgmt.bmCapabilities = \ - CDC_CALL_MGMT_SUPPORTED | CDC_CALL_MGMT_OVER_DCI,\ - .acm.bFunctionLength = sizeof(usb_cdc_acm_desc_t),\ - .acm.bDescriptorType = CDC_CS_INTERFACE,\ - .acm.bDescriptorSubtype = CDC_SCS_ACM,\ - .acm.bmCapabilities = CDC_ACM_SUPPORT_LINE_REQUESTS,\ - .union_desc.bFunctionLength = sizeof(usb_cdc_union_desc_t),\ - .union_desc.bDescriptorType = CDC_CS_INTERFACE,\ - .union_desc.bDescriptorSubtype= CDC_SCS_UNION,\ - .ep_notify.bLength = sizeof(usb_ep_desc_t),\ - .ep_notify.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_notify.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep_notify.wMaxPacketSize = LE16(UDI_CDC_COMM_EP_SIZE),\ - .ep_notify.bInterval = 0x10,\ - .ep_notify.bEndpointAddress = UDI_CDC_COMM_EP_##port,\ - .iface.bInterfaceNumber = UDI_CDC_COMM_IFACE_NUMBER_##port,\ - .call_mgmt.bDataInterface = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .union_desc.bMasterInterface = UDI_CDC_COMM_IFACE_NUMBER_##port,\ - .union_desc.bSlaveInterface0 = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .iface.iInterface = UDI_CDC_COMM_STRING_ID_##port,\ - } - -/** Content of CDC DATA interface descriptors. */ -#define UDI_CDC_DATA_DESC_COMMON \ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 2,\ - .iface.bInterfaceClass = CDC_CLASS_DATA,\ - .iface.bInterfaceSubClass = 0,\ - .iface.bInterfaceProtocol = 0,\ - .ep_in.bLength = sizeof(usb_ep_desc_t),\ - .ep_in.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_in.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_in.bInterval = 0,\ - .ep_out.bLength = sizeof(usb_ep_desc_t),\ - .ep_out.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_out.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_out.bInterval = 0, - -/** Content of CDC DATA interface descriptors for FS. */ -#define UDI_CDC_DATA_DESC_FS(port) { \ - UDI_CDC_DATA_DESC_COMMON \ - .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\ - .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_FS_SIZE),\ - .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\ - .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\ - .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\ - } - -/** Content of CDC DATA interface descriptors for HS. */ -#define UDI_CDC_DATA_DESC_HS(port) { \ - UDI_CDC_DATA_DESC_COMMON \ - .ep_in.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\ - .ep_out.wMaxPacketSize = LE16(UDI_CDC_DATA_EPS_HS_SIZE),\ - .ep_in.bEndpointAddress = UDI_CDC_DATA_EP_IN_##port,\ - .ep_out.bEndpointAddress = UDI_CDC_DATA_EP_OUT_##port,\ - .iface.bInterfaceNumber = UDI_CDC_DATA_IFACE_NUMBER_##port,\ - .iface.iInterface = UDI_CDC_DATA_STRING_ID_##port,\ - } - -/** - * \name Interface for Application with Single CDC Interface Support - */ -//!@{ - -/** - * \brief Notify a state change of Data Carrier Detect (DCD) signal - * - * \param[in] b_set DCD is enabled if true, else disabled - */ -void udi_cdc_ctrl_signal_dcd(bool b_set); - -/** - * \brief Notify a state change of Data Set Ready (DSR) signal - * - * \param[in] b_set DSR is enabled if true, else disabled - */ -void udi_cdc_ctrl_signal_dsr(bool b_set); - -/** - * \brief Notify a framing error - */ -void udi_cdc_signal_framing_error(void); - -/** - * \brief Notify a parity error - */ -void udi_cdc_signal_parity_error(void); - -/** - * \brief Notify a overrun - */ -void udi_cdc_signal_overrun(void); - -/** - * \brief Gets the number of byte received - * - * \return The number of data available. - */ -iram_size_t udi_cdc_get_nb_received_data(void); - -/** - * \brief This function checks if a character has been received on the CDC line - * - * \return \c 1 if a byte is ready to be read. - */ -bool udi_cdc_is_rx_ready(void); - -/** - * \brief Waits and gets a value on CDC line - * - * \return Value read on CDC line. - */ -int udi_cdc_getc(void); - -/** - * \brief Reads a RAM buffer on CDC line - * - * \param[out] buf Values read - * \param[in] size Number of value read - * - * \return The number of data remaining. - */ -iram_size_t udi_cdc_read_buf(void* buf, iram_size_t size); - -/** - * \brief Gets the number of free byte in TX buffer - * - * \return The number of free byte in TX buffer. - */ -iram_size_t udi_cdc_get_free_tx_buffer(void); - -/** - * \brief This function checks if a new character sent is possible. - * The type int is used to support scanf redirection from compiler .lib file. - * - * \return \c 1 if a new character can be sent. - */ -bool udi_cdc_is_tx_ready(void); - -/** - * \brief Puts a byte on CDC line - * - * The type int is used to support printf redirection from compiler LIB. - * - * \param[in] value Value to put - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -int udi_cdc_putc(int value); - -/** - * \brief Writes a RAM buffer on CDC line - * - * \param[in] buf Values to write - * \param[in] size Number of value to write - * - * \return The number of data remaining. - */ -iram_size_t udi_cdc_write_buf(const void* buf, iram_size_t size); -//@} - -/** - * \name Interface for Application with Multi CDC Interfaces Support - */ -//@{ - -/** - * \brief Notify a state change of DCD signal - * - * \param[in] port Communication port number to manage - * \param[in] b_set DCD is enabled if true, else disabled - */ -void udi_cdc_multi_ctrl_signal_dcd(uint8_t port, bool b_set); - -/** - * \brief Notify a state change of DSR signal - * - * \param[in] port Communication port number to manage - * \param[in] b_set DSR is enabled if true, else disabled - */ -void udi_cdc_multi_ctrl_signal_dsr(uint8_t port, bool b_set); - -/** - * \brief Notify a framing error - * - * \param[in] port Communication port number to manage - */ -void udi_cdc_multi_signal_framing_error(uint8_t port); - -/** - * \brief Notify a parity error - * - * \param[in] port Communication port number to manage - */ -void udi_cdc_multi_signal_parity_error(uint8_t port); - -/** - * \brief Notify a overrun - * - * \param[in] port Communication port number to manage - */ -void udi_cdc_multi_signal_overrun(uint8_t port); - -/** - * \brief Gets the number of byte received - * - * \param[in] port Communication port number to manage - * - * \return The number of data available. - */ -iram_size_t udi_cdc_multi_get_nb_received_data(uint8_t port); - -/** - * \brief This function checks if a character has been received on the CDC line - * - * \param[in] port Communication port number to manage - * - * \return \c 1 if a byte is ready to be read. - */ -bool udi_cdc_multi_is_rx_ready(uint8_t port); - -/** - * \brief Waits and gets a value on CDC line - * - * \param[in] port Communication port number to manage - * - * \return Value read on CDC line. - */ -int udi_cdc_multi_getc(uint8_t port); - -/** - * \brief Reads a RAM buffer on CDC line - * - * \param[in] port Communication port number to manage - * \param[out] buf Values read - * \param[in] size Number of values read - * - * \return The number of data remaining. - */ -iram_size_t udi_cdc_multi_read_buf(uint8_t port, void* buf, iram_size_t size); - -/** - * \brief Gets the number of free byte in TX buffer - * - * \param[in] port Communication port number to manage - * - * \return The number of free byte in TX buffer. - */ -iram_size_t udi_cdc_multi_get_free_tx_buffer(uint8_t port); - -/** - * \brief This function checks if a new character sent is possible - * - * The type int is used to support scanf redirection from compiler LIB. - * - * \param[in] port Communication port number to manage - * - * \return \c 1 if a new character can be sent. - */ -bool udi_cdc_multi_is_tx_ready(uint8_t port); - -/** - * \brief Puts a byte on CDC line, and the type int is used to support - * printf redirection from compiler LIB. - * - * \param[in] port Communication port number to manage - * \param[in] value Value to put - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -int udi_cdc_multi_putc(uint8_t port, int value); - -/** - * \brief Writes a RAM buffer on CDC line - * - * \param[in] port Communication port number to manage - * \param[in] buf Values to write - * \param[in] size Number of value to write - * - * \return The number of data remaining. - */ -iram_size_t udi_cdc_multi_write_buf(uint8_t port, const void* buf, iram_size_t size); -//@} - -//@} - -/** - * \page asfdoc_udi_cdc_exqsg Quick Start Guide for USB Device Communication Class Device Module (UDI CDC) - * - * This is the quick start guide for the \ref asfdoc_udi_cdc_group - * "USB Device Interface CDC Module (UDI CDC)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain or highlights several code fragments. - * The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section udi_cdc_basic_use_case Basic Use Case - * In this basic use case, the "USB CDC (Single Interface Device)" module is used - * with only one communication port. - * The "USB CDC (Composite Device)" module usage is described in \ref udi_cdc_use_cases - * "Advanced Use Cases". - * - * \subsection udi_cdc_basic_use_case_setup Setup Steps - * As a USB device, it follows common USB device setup steps. Refer to - * \ref asfdoc_udc_basic_use_case_setup "USB Device Basic Setup". - * - * \subsection udi_cdc_basic_use_case_usage Usage Steps - * - * \subsubsection udi_cdc_basic_use_case_usage_code Example Code - * Content of conf_usb.h: - * \code - #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() - extern bool my_callback_cdc_enable(void); - #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() - extern void my_callback_cdc_disable(void); - #define UDI_CDC_LOW_RATE - - #define UDI_CDC_DEFAULT_RATE 115200 - #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 - #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE - #define UDI_CDC_DEFAULT_DATABITS 8 - - #include "udi_cdc_conf.h" // At the end of conf_usb.h file - \endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_cdc_transfert = false; - bool my_callback_cdc_enable(void) - { - my_flag_autorize_cdc_transfert = true; - return true; - } - - void my_callback_cdc_disable(void) - { - my_flag_autorize_cdc_transfert = false; - } - - void task(void) - { - if (my_flag_autorize_cdc_transfert) { - udi_cdc_putc('A'); - udi_cdc_getc(); - } - } - \endcode - * - * \subsubsection udi_cdc_basic_use_case_setup_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration, - * which is the USB device CDC configuration: - * \code - #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for CDC - \endcode - * \note The USB serial number is mandatory when a CDC interface is used. - * - * \code - #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() - extern bool my_callback_cdc_enable(void); - \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB CDC interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_CDC_ENABLE_EXT() callback function is called and return true. - * Thus, when this event is received, the data transfer on CDC interface are authorized. - * - * \code - #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() - extern void my_callback_cdc_disable(void); - \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_CDC_DISABLE_EXT() callback function - * is called. Thus, the data transfer must be stopped on CDC interface. - * - * \code - #define UDI_CDC_LOW_RATE - \endcode - * \note Define it when the transfer CDC Device to Host is a low rate - * (<512000 bauds) to reduce CDC buffers size. - * - * \code - #define UDI_CDC_DEFAULT_RATE 115200 - #define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 - #define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE - #define UDI_CDC_DEFAULT_DATABITS 8 - \endcode - * \note Default configuration of communication port at startup. - * - * -# Send or wait data on CDC line: - * \code - // Waits and gets a value on CDC line - int udi_cdc_getc(void); - // Reads a RAM buffer on CDC line - iram_size_t udi_cdc_read_buf(int* buf, iram_size_t size); - // Puts a byte on CDC line - int udi_cdc_putc(int value); - // Writes a RAM buffer on CDC line - iram_size_t udi_cdc_write_buf(const int* buf, iram_size_t size); - \endcode - * - * \section udi_cdc_use_cases Advanced Use Cases - * \ifnot ASF_MANUAL - * For more advanced use of the UDI CDC module, see the following use cases: - * - \subpage udi_cdc_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - * - \subpage asfdoc_udc_device_cfg - * - \subpage asfdoc_udc_vbus_monitoring - * \else - * For multiple interface use of UDI CDC module, see the following: - * - \subpage udi_cdc_use_case_composite - * - * For more advanced use of the UDI CDC module, see the following: - * - \ref asfdoc_udc_use_cases - * \endif - */ - -/** - * \page udi_cdc_use_case_composite CDC in a Composite Device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB CDC (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB HID Mouse (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_cdc_use_case_composite_setup Setup Steps - * For the setup code of this use case to work, the - * \ref udi_cdc_basic_use_case "Basic Use Case" must be followed. - * - * \section udi_cdc_use_case_composite_usage Usage Steps - * - * \subsection udi_cdc_use_case_composite_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+2) - #define USB_DEVICE_MAX_EP (X+3) - - #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX - #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX - #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint - #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0 - #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 - - #define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - ... - \endcode - * - * \subsection udi_cdc_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * \code - // Endpoint control size, This must be: - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 2 for CDC. - #define USB_DEVICE_NB_INTERFACE (X+2) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 3 for CDC. - #define USB_DEVICE_MAX_EP (X+3) - \endcode - * -# Ensure that conf_usb.h contains the description of - * composite device: - * \code - // The endpoint numbers chosen by you for the CDC. - // The endpoint numbers starting from 1. - #define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX - #define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX - #define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint - // The interface index of an interface starting from 0 - #define UDI_CDC_COMM_IFACE_NUMBER_0 X+0 - #define UDI_CDC_DATA_IFACE_NUMBER_0 X+1 - \endcode - * - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * \code - // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - ... - \endcode - * \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - * Also, the CDC requires a USB Interface Association Descriptor (IAD) for - * composite device. - */ - -/** - * \page asfdoc_udi_cdc_config_examples Configuration File Examples - * - * \section asfdoc_udi_cdc_config_examples_1 conf_usb.h - * \subsection asfdoc_udi_cdc_config_examples_1_1 UDI CDC Single - * \include module_config/conf_usb.h - * \subsection asfdoc_udi_cdc_config_examples_1_2 UDI CDC Multiple (Composite) - * \include composite/device/module_config/conf_usb.h - * - * \section asfdoc_udi_cdc_config_examples_2 conf_clock.h - * - * \subsection asfdoc_udi_cdc_config_examples_2_1 XMEGA (USB) - * \include example/atxmega128b1_xmega_b1_xplained/conf_clock.h - * - * \subsection asfdoc_udi_cdc_config_examples_2_2 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_clock.h - * - * \subsection asfdoc_udi_cdc_config_examples_2_3 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_clock.h - * - * \subsection asfdoc_udi_cdc_config_examples_2_4 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_clock.h - * - * \subsection asfdoc_udi_cdc_config_examples_2_5 SAM3S, SAM3SD, SAM4S Devices (UPD: USB Peripheral Device) - * \include example/sam3s4c_sam3s_ek/conf_clock.h - * - * \subsection asfdoc_udi_cdc_config_examples_2_6 SAM3U Device (UPDHS: USB Peripheral Device High Speed) - * \include example/sam3u4e_sam3u_ek/conf_clock.h - * - * \subsection asfdoc_udi_cdc_config_examples_2_7 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_clock.h - * - * \section asfdoc_udi_cdc_config_examples_3 conf_clocks.h - * - * \subsection asfdoc_udi_cdc_config_examples_3_1 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_clocks.h - * - * \section asfdoc_udi_cdc_config_examples_4 conf_board.h - * - * \subsection asfdoc_udi_cdc_config_examples_4_1 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_board.h - * - * \subsection asfdoc_udi_cdc_config_examples_4_2 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_board.h - * - * \subsection asfdoc_udi_cdc_config_examples_4_3 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_board.h - * - * \subsection asfdoc_udi_cdc_config_examples_4_4 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_board.h - * - * \subsection asfdoc_udi_cdc_config_examples_4_5 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_board.h - */ - -/** - * \page asfdoc_udi_cdc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42337B12/2015Fixed typos
42337A12/2014Initial release
- */ - diff --git a/atmel-samd/asf/common/services/usb/class/cdc/usb_protocol_cdc.h b/atmel-samd/asf/common/services/usb/class/cdc/usb_protocol_cdc.h deleted file mode 100644 index 875e7e4dda962..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/cdc/usb_protocol_cdc.h +++ /dev/null @@ -1,318 +0,0 @@ -/** - * \file - * - * \brief USB Communication Device Class (CDC) protocol definitions - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _USB_PROTOCOL_CDC_H_ -#define _USB_PROTOCOL_CDC_H_ - -#include "compiler.h" - -/** - * \ingroup usb_protocol_group - * \defgroup cdc_protocol_group Communication Device Class Definitions - * @{ - */ - -/** - * \name Possible values of class - */ -//@{ -#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class -#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface -#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface -//@} - -//! \name USB CDC Subclass IDs -//@{ -#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model -#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model -#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model -#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model -#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model -#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model -#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model -//@} - -//! \name USB CDC Communication Interface Protocol IDs -//@{ -#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands -//@} - -//! \name USB CDC Data Interface Protocol IDs -//@{ -#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI -#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC -#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent -#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol -#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol -#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor -#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures -#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control -#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN -#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands -#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver -/** - * \brief Describes the Protocol Unit Functional Descriptors [sic] - * on Communication Class Interface - */ -#define CDC_PROTOCOL_PUFD 0xFE -//@} - -//! \name USB CDC Functional Descriptor Types -//@{ -#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor -#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor -//@} - -//! \name USB CDC Functional Descriptor Subtypes -//@{ -#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor -#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management -#define CDC_SCS_ACM 0x02 //!< Abstract Control Management -#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor -//@} - -//! \name USB CDC Request IDs -//@{ -#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define USB_REQ_CDC_SET_COMM_FEATURE 0x02 -#define USB_REQ_CDC_GET_COMM_FEATURE 0x03 -#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04 -#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10 -#define USB_REQ_CDC_SET_HOOK_STATE 0x11 -#define USB_REQ_CDC_PULSE_SETUP 0x12 -#define USB_REQ_CDC_SEND_PULSE 0x13 -#define USB_REQ_CDC_SET_PULSE_TIME 0x14 -#define USB_REQ_CDC_RING_AUX_JACK 0x15 -#define USB_REQ_CDC_SET_LINE_CODING 0x20 -#define USB_REQ_CDC_GET_LINE_CODING 0x21 -#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22 -#define USB_REQ_CDC_SEND_BREAK 0x23 -#define USB_REQ_CDC_SET_RINGER_PARMS 0x30 -#define USB_REQ_CDC_GET_RINGER_PARMS 0x31 -#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32 -#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33 -#define USB_REQ_CDC_SET_LINE_PARMS 0x34 -#define USB_REQ_CDC_GET_LINE_PARMS 0x35 -#define USB_REQ_CDC_DIAL_DIGITS 0x36 -#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37 -#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38 -#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39 -#define USB_REQ_CDC_GET_PROFILE 0x3A -#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 -#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41 -#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42 -#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43 -#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44 -#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50 -#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51 -#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52 -#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53 -// Added bNotification codes according cdc spec 1.1 chapter 6.3 -#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09 -#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20 -#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 -#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 -//@} - -/* - * Need to pack structures tightly, or the compiler might insert padding - * and violate the spec-mandated layout. - */ -COMPILER_PACK_SET(1) - -//! \name USB CDC Descriptors -//@{ - - -//! CDC Header Functional Descriptor -typedef struct { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - le16_t bcdCDC; -} usb_cdc_hdr_desc_t; - -//! CDC Call Management Functional Descriptor -typedef struct { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; - uint8_t bDataInterface; -} usb_cdc_call_mgmt_desc_t; - -//! CDC ACM Functional Descriptor -typedef struct { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; -} usb_cdc_acm_desc_t; - -//! CDC Union Functional Descriptor -typedef struct { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bMasterInterface; - uint8_t bSlaveInterface0; -} usb_cdc_union_desc_t; - - -//! \name USB CDC Call Management Capabilities -//@{ -//! Device handles call management itself -#define CDC_CALL_MGMT_SUPPORTED (1 << 0) -//! Device can send/receive call management info over a Data Class interface -#define CDC_CALL_MGMT_OVER_DCI (1 << 1) -//@} - -//! \name USB CDC ACM Capabilities -//@{ -//! Device supports the request combination of -//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. -#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0) -//! Device supports the request combination of -//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, -//! and the notification Serial_State. -#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1) -//! Device supports the request Send_Break -#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2) -//! Device supports the notification Network_Connection. -#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3) -//@} -//@} - -//! \name USB CDC line control -//@{ - -//! \name USB CDC line coding -//@{ -//! Line Coding structure -typedef struct { - le32_t dwDTERate; - uint8_t bCharFormat; - uint8_t bParityType; - uint8_t bDataBits; -} usb_cdc_line_coding_t; -//! Possible values of bCharFormat -enum cdc_char_format { - CDC_STOP_BITS_1 = 0, //!< 1 stop bit - CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits - CDC_STOP_BITS_2 = 2, //!< 2 stop bits -}; -//! Possible values of bParityType -enum cdc_parity { - CDC_PAR_NONE = 0, //!< No parity - CDC_PAR_ODD = 1, //!< Odd parity - CDC_PAR_EVEN = 2, //!< Even parity - CDC_PAR_MARK = 3, //!< Parity forced to 0 (space) - CDC_PAR_SPACE = 4, //!< Parity forced to 1 (mark) -}; -//@} - -//! \name USB CDC control signals -//! spec 1.1 chapter 6.2.14 -//@{ - -//! Control signal structure -typedef struct { - uint16_t value; -} usb_cdc_control_signal_t; - -//! \name Possible values in usb_cdc_control_signal_t -//@{ -//! Carrier control for half duplex modems. -//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS. -//! The device ignores the value of this bit -//! when operating in full duplex mode. -#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1) -//! Indicates to DCE if DTE is present or not. -//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. -#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0) -//@} -//@} - - -//! \name USB CDC notification message -//@{ - -typedef struct { - uint8_t bmRequestType; - uint8_t bNotification; - le16_t wValue; - le16_t wIndex; - le16_t wLength; -} usb_cdc_notify_msg_t; - -//! \name USB CDC serial state -//@{* - -//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5) -typedef struct { - usb_cdc_notify_msg_t header; - le16_t value; -} usb_cdc_notify_serial_state_t; - -//! \name Possible values in usb_cdc_notify_serial_state_t -//@{ -#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1<<0)) -#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1<<1)) -#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1<<2)) -#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1<<3)) -#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1<<4)) -#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1<<5)) -#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1<<6)) -//@} -//! @} - -//! @} - -COMPILER_PACK_RESET() - -//! @} - -#endif // _USB_PROTOCOL_CDC_H_ diff --git a/atmel-samd/asf/common/services/usb/class/composite/device/doxygen/common.services.usb.class.composite.device/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/composite/device/doxygen/common.services.usb.class.composite.device/doxyfile.doxygen deleted file mode 100644 index 43b0dcb31543f..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/composite/device/doxygen/common.services.usb.class.composite.device/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Composite Device" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. 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For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. 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The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../udi_composite_desc.c ../../udi_composite_conf.h ../../module_config/conf_usb.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. 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This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/composite/device/doxygen/common.services.usb.class.composite.device/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/composite/device/doxygen/common.services.usb.class.composite.device/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/composite/device/doxygen/common.services.usb.class.composite.device/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
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  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/composite/device/module_config/conf_usb.h b/atmel-samd/asf/common/services/usb/class/composite/device/module_config/conf_usb.h deleted file mode 100644 index c64b8ae6cb003..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/composite/device/module_config/conf_usb.h +++ /dev/null @@ -1,531 +0,0 @@ -/** - * \file - * - * \brief USB configuration file - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_USB_H_ -#define _CONF_USB_H_ - -#include "compiler.h" - -#warning You must refill the following definitions with a correct values - -/** - * USB Device Configuration - * @{ - */ - -//! Device definition (mandatory) -#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL -#define USB_DEVICE_PRODUCT_ID 0xFFFF -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on VBUS line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" -// #define USB_DEVICE_PRODUCT_NAME "Product name" -// #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC - -/** - * Device speeds support - * @{ - */ -//! To define a Low speed device -//#define USB_DEVICE_LOW_SPEED - -//! To authorize the High speed -#if (UC3A3||UC3A4) -//#define USB_DEVICE_HS_SUPPORT -#endif -//@} - -/** - * USB Device Callbacks definitions (Optional) - * @{ - */ -// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high) -// extern void user_callback_vbus_action(bool b_vbus_high); -// #define UDC_SOF_EVENT() user_callback_sof_action() -// extern void user_callback_sof_action(void); -// #define UDC_SUSPEND_EVENT() user_callback_suspend_action() -// extern void user_callback_suspend_action(void); -// #define UDC_RESUME_EVENT() user_callback_resume_action() -// extern void user_callback_resume_action(void); -//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature -// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() -// extern void user_callback_remotewakeup_enable(void); -// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() -// extern void user_callback_remotewakeup_disable(void); -//! When a extra string descriptor must be supported -//! other than manufacturer, product and serial string -// #define UDC_GET_EXTRA_STRING() -//@} - -/** - * USB Device low level configuration - * When only one interface is used, these configurations are defined by the class module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Number of interfaces for this device -#define USB_DEVICE_NB_INTERFACE 1 // 1 or more - -//! Total endpoint used by all interfaces -//! Note: -//! It is possible to define an IN and OUT endpoints with the same number on XMEGA product only -//! E.g. MSC class can be have IN endpoint 0x81 and OUT endpoint 0x01 -#define USB_DEVICE_MAX_EP 1 // 0 to max endpoint requested by interfaces -//@} - -//@} - - -/** - * USB Interface Configuration - * @{ - */ - -/** - * Configuration of CDC interface (if used) - * @{ - */ - -//! Number of communication port used (1 to 3) -#define UDI_CDC_PORT_NB 1 - -//! Interface callback definition -#define UDI_CDC_ENABLE_EXT(port) true -#define UDI_CDC_DISABLE_EXT(port) -#define UDI_CDC_RX_NOTIFY(port) -#define UDI_CDC_TX_EMPTY_NOTIFY(port) -#define UDI_CDC_SET_CODING_EXT(port,cfg) -#define UDI_CDC_SET_DTR_EXT(port,set) -#define UDI_CDC_SET_RTS_EXT(port,set) -/* - * #define UDI_CDC_ENABLE_EXT(port) my_callback_cdc_enable() - * extern bool my_callback_cdc_enable(void); - * #define UDI_CDC_DISABLE_EXT(port) my_callback_cdc_disable() - * extern void my_callback_cdc_disable(void); - * #define UDI_CDC_RX_NOTIFY(port) my_callback_rx_notify(port) - * extern void my_callback_rx_notify(uint8_t port); - * #define UDI_CDC_TX_EMPTY_NOTIFY(port) my_callback_tx_empty_notify(port) - * extern void my_callback_tx_empty_notify(uint8_t port); - * #define UDI_CDC_SET_CODING_EXT(port,cfg) my_callback_config(port,cfg) - * extern void my_callback_config(uint8_t port, usb_cdc_line_coding_t * cfg); - * #define UDI_CDC_SET_DTR_EXT(port,set) my_callback_cdc_set_dtr(port,set) - * extern void my_callback_cdc_set_dtr(uint8_t port, bool b_enable); - * #define UDI_CDC_SET_RTS_EXT(port,set) my_callback_cdc_set_rts(port,set) - * extern void my_callback_cdc_set_rts(uint8_t port, bool b_enable); - */ - -//! Define it when the transfer CDC Device to Host is a low rate (<512000 bauds) -//! to reduce CDC buffers size -#define UDI_CDC_LOW_RATE - -//! Default configuration of communication port -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoints' numbers used by single or first CDC port -#define UDI_CDC_DATA_EP_IN_0 (1 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (2 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -//! Endpoints' numbers used by second CDC port (Optional) -#define UDI_CDC_DATA_EP_IN_2 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_2 (5 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_2 (6 | USB_EP_DIR_IN) // Notify endpoint -//! Endpoints' numbers used by third CDC port (Optional) -#define UDI_CDC_DATA_EP_IN_3 (7 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_3 (8 | USB_EP_DIR_OUT) // RX -#define UDI_CDC_COMM_EP_3 (9 | USB_EP_DIR_IN) // Notify endpoint - -//! Interface numbers used by single or first CDC port -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 -//! Interface numbers used by second CDC port (Optional) -#define UDI_CDC_COMM_IFACE_NUMBER_2 2 -#define UDI_CDC_DATA_IFACE_NUMBER_2 3 -//! Interface numbers used by third CDC port (Optional) -#define UDI_CDC_COMM_IFACE_NUMBER_3 4 -#define UDI_CDC_DATA_IFACE_NUMBER_3 5 -//@} -//@} - - -/** - * Configuration of MSC interface (if used) - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() true -#define UDI_MSC_DISABLE_EXT() -#define UDI_MSC_NOTIFY_TRANS_EXT() -/* - * #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable() - * extern bool my_callback_msc_enable(void); - * #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable() - * extern void my_callback_msc_disable(void); - * #define UDI_MSC_NOTIFY_TRANS_EXT() msc_notify_trans() - * extern void msc_notify_trans(void) { - */ - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 0 -//@} -//@} - - -/** - * Configuration of HID Mouse interface (if used) - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() true -#define UDI_HID_MOUSE_DISABLE_EXT() -// #define UDI_HID_MOUSE_ENABLE_EXT() my_callback_mouse_enable() -// extern bool my_callback_mouse_enable(void); -// #define UDI_HID_MOUSE_DISABLE_EXT() my_callback_mouse_disable() -// extern void my_callback_mouse_disable(void); - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (1 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 0 -//@} -//@} - - -/** - * Configuration of HID Keyboard interface (if used) - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() true -#define UDI_HID_KBD_DISABLE_EXT() -// #define UDI_HID_KBD_ENABLE_EXT() my_callback_keyboard_enable() -// extern bool my_callback_keyboard_enable(void); -// #define UDI_HID_KBD_DISABLE_EXT() my_callback_keyboard_disable() -// extern void my_callback_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) -// #define UDI_HID_KBD_CHANGE_LED(value) my_callback_keyboard_led(value) -// extern void my_callback_keyboard_led(uint8_t value) - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (1 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 0 -//@} -//@} - - -/** - * Configuration of HID Generic interface (if used) - * @{ - */ -//! Interface callback definition -#define UDI_HID_GENERIC_ENABLE_EXT() true -#define UDI_HID_GENERIC_DISABLE_EXT() -#define UDI_HID_GENERIC_REPORT_OUT(ptr) -#define UDI_HID_GENERIC_SET_FEATURE(f) -/* - * #define UDI_HID_GENERIC_ENABLE_EXT() my_callback_generic_enable() - * extern bool my_callback_generic_enable(void); - * #define UDI_HID_GENERIC_DISABLE_EXT() my_callback_generic_disable() - * extern void my_callback_generic_disable(void); - * #define UDI_HID_GENERIC_REPORT_OUT(ptr) my_callback_generic_report_out(ptr) - * extern void my_callback_generic_report_out(uint8_t *report); - * #define UDI_HID_GENERIC_SET_FEATURE(f) my_callback_generic_set_feature(f) - * extern void my_callback_generic_set_feature(uint8_t *report_feature); - */ -#define UDI_HID_REPORT_IN_SIZE 64 -#define UDI_HID_REPORT_OUT_SIZE 64 -#define UDI_HID_REPORT_FEATURE_SIZE 4 -#define UDI_HID_GENERIC_EP_SIZE 64 - -/** - * USB HID Generic low level configuration - * In standalone these configurations are defined by the HID generic module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_GENERIC_EP_OUT (2 | USB_EP_DIR_OUT) -#define UDI_HID_GENERIC_EP_IN (1 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_GENERIC_IFACE_NUMBER 0 -//@} -//@} - - -/** - * Configuration of PHDC interface (if used) - * @{ - */ - -//! Interface callback definition -#define UDI_PHDC_ENABLE_EXT() true -#define UDI_PHDC_DISABLE_EXT() - -//! Select data format of application -//! USB_PHDC_DATAMSG_FORMAT_VENDOR or USB_PHDC_DATAMSG_FORMAT_11073_20601 -#define UDI_PHDC_DATAMSG_FORMAT USB_PHDC_DATAMSG_FORMAT_11073_20601 -//! If USB_PHDC_DATAMSG_FORMAT_11073_20601 then define specialization(s) -#define UDI_PHDC_SPECIALIZATION {0x2345} // Define in 11073_20601 - -//! Defines the QOS need for each transfer direction -#define UDI_PHDC_QOS_OUT \ - (USB_PHDC_QOS_MEDIUM_BETTER|USB_PHDC_QOS_HIGH_BEST) -#define UDI_PHDC_QOS_IN \ - (USB_PHDC_QOS_LOW_GOOD|USB_PHDC_QOS_MEDIUM_BETTER|USB_PHDC_QOS_MEDIUM_BEST) - -//! The following METADATAs can be send during USB enumeration -//! for each endpoints (optional). -//! It can define the Opaque data format of each endpoints -//! These must be up to 253 and recommended <30 -#define UDI_PHDC_METADATA_DESC_BULK_IN {0x01,0x02,0x03} -#define UDI_PHDC_METADATA_DESC_BULK_OUT {0x01,0x02,0x03} -#define UDI_PHDC_METADATA_DESC_INT_IN {0x01,0x02,0x03} - -/** - * USB PHDC low level configuration - * In standalone these configurations are defined by the PHDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_PHDC_EP_BULK_OUT (1 | USB_EP_DIR_OUT) -#define UDI_PHDC_EP_BULK_IN (2 | USB_EP_DIR_IN) -#if ((UDI_PHDC_QOS_IN&USB_PHDC_QOS_LOW_GOOD)==USB_PHDC_QOS_LOW_GOOD) -// Only if UDI_PHDC_QOS_IN include USB_PHDC_QOS_LOW_GOOD -# define UDI_PHDC_EP_INTERRUPT_IN (3 | USB_EP_DIR_IN) -#endif - -//! Endpoint sizes -#define UDI_PHDC_EP_SIZE_BULK_OUT 32 -#define UDI_PHDC_EP_SIZE_BULK_IN 32 -#define UDI_PHDC_EP_SIZE_INT_IN 8 - - -//! Interface number -#define UDI_PHDC_IFACE_NUMBER 0 -//@} -//@} - -/** - * Configuration of Class Vendor interface (if used) - * @{ - */ - -//! Interface callback definition -#define UDI_VENDOR_ENABLE_EXT() true -#define UDI_VENDOR_DISABLE_EXT() -#define UDI_VENDOR_SETUP_OUT_RECEIVED() false -#define UDI_VENDOR_SETUP_IN_RECEIVED() false -/* - * #define UDI_VENDOR_ENABLE_EXT() my_callback_vendor_enable() - * extern bool my_callback_vendor_enable(void); - * #define UDI_VENDOR_DISABLE_EXT() my_callback_vendor_disable() - * extern void my_callback_vendor_disable(void); - * - * #define UDI_VENDOR_SETUP_OUT_RECEIVED() my_vendor_setup_out_received() - * extern bool my_vendor_setup_out_received(void); - * #define UDI_VENDOR_SETUP_IN_RECEIVED() my_vendor_setup_in_received() - * extern bool my_vendor_setup_in_received(void); - */ - -//! endpoints size for full speed -#define UDI_VENDOR_EPS_SIZE_INT_FS 64 -#define UDI_VENDOR_EPS_SIZE_BULK_FS 64 -#define UDI_VENDOR_EPS_SIZE_ISO_FS 256 - -//! endpoints size for high speed -#define UDI_VENDOR_EPS_SIZE_INT_HS 64 -#define UDI_VENDOR_EPS_SIZE_BULK_HS 512 -#define UDI_VENDOR_EPS_SIZE_ISO_HS 64 - -/** - * USB Class Vendor low level configuration - * In standalone these configurations are defined by the Class Vendor module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_VENDOR_EP_INTERRUPT_IN (1 | USB_EP_DIR_IN) -#define UDI_VENDOR_EP_INTERRUPT_OUT (2 | USB_EP_DIR_OUT) -#define UDI_VENDOR_EP_BULK_IN (3 | USB_EP_DIR_IN) -#define UDI_VENDOR_EP_BULK_OUT (4 | USB_EP_DIR_OUT) -#define UDI_VENDOR_EP_ISO_IN (5 | USB_EP_DIR_IN) -#define UDI_VENDOR_EP_ISO_OUT (6 | USB_EP_DIR_OUT) - - -//! Interface number -#define UDI_VENDOR_IFACE_NUMBER 0 -//@} -//@} - -//... Eventually add other Interface Configuration - -//@} - - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS - -//! USB Interface APIs -#define UDI_COMPOSITE_API - -/* Example for device with cdc, msc and hid mouse interface -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse -*/ - -//@} - - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error - -/* Example of include for interface -#include "udi_msc.h" -#include "udi_hid_kbd.h" -#include "udi_hid_mouse.h" -#include "udi_cdc.h" -#include "udi_phdc.h" -#include "udi_vendor.h" -*/ -/* Declaration of callbacks used by USB -#include "callback_def.h" -*/ - -#endif // _CONF_USB_H_ diff --git a/atmel-samd/asf/common/services/usb/class/composite/device/udi_composite_conf.h b/atmel-samd/asf/common/services/usb/class/composite/device/udi_composite_conf.h deleted file mode 100644 index 57af5da5d8af1..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/composite/device/udi_composite_conf.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * \file - * - * \brief Descriptors for an USB Composite Device MSC and HID mouse - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_COMPOSITE_CONF_H_ -#define _UDI_COMPOSITE_CONF_H_ - -#endif // _UDI_COMPOSITE_CONF_H_ diff --git a/atmel-samd/asf/common/services/usb/class/composite/device/udi_composite_desc.c b/atmel-samd/asf/common/services/usb/class/composite/device/udi_composite_desc.c deleted file mode 100644 index 5df1f8364efa4..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/composite/device/udi_composite_desc.c +++ /dev/null @@ -1,184 +0,0 @@ -/** - * \file - * - * \brief Descriptors for an USB Composite Device - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "udd.h" -#include "udc_desc.h" - -/** - * \defgroup udi_group_desc Descriptors for a USB Device - * composite - * - * @{ - */ - -/**INDENT-OFF**/ - -//! USB Device Descriptor -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = { - .bLength = sizeof(usb_dev_desc_t), - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .idVendor = LE16(USB_DEVICE_VENDOR_ID), - .idProduct = LE16(USB_DEVICE_PRODUCT_ID), - .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8) - | USB_DEVICE_MINOR_VERSION), -#ifdef USB_DEVICE_MANUFACTURE_NAME - .iManufacturer = 1, -#else - .iManufacturer = 0, // No manufacture string -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - .iProduct = 2, -#else - .iProduct = 0, // No product string -#endif -#ifdef USB_DEVICE_SERIAL_NAME - .iSerialNumber = 3, -#else - .iSerialNumber = 0, // No serial string -#endif - .bNumConfigurations = 1 -}; - - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Qualifier Descriptor for HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = { - .bLength = sizeof(usb_dev_qual_desc_t), - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .bNumConfigurations = 1 -}; -#endif - -//! Structure for USB Device Configuration Descriptor -COMPILER_PACK_SET(1) -typedef struct { - usb_conf_desc_t conf; - UDI_COMPOSITE_DESC_T; -} udc_desc_t; -COMPILER_PACK_RESET() - -//! USB Device Configuration Descriptor filled for FS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_desc_t udc_desc_fs = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), - UDI_COMPOSITE_DESC_FS -}; - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Configuration Descriptor filled for HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_desc_t udc_desc_hs = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), - UDI_COMPOSITE_DESC_HS -}; -#endif - - -/** - * \name UDC structures which contains all USB Device definitions - */ -//@{ - -//! Associate an UDI for each USB interface -UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = { - UDI_COMPOSITE_API -}; - -//! Add UDI with USB Descriptors FS -UDC_DESC_STORAGE udc_config_speed_t udc_config_lsfs[1] = {{ - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs, - .udi_apis = udi_apis, -}}; - -#ifdef USB_DEVICE_HS_SUPPORT -//! Add UDI with USB Descriptors HS -UDC_DESC_STORAGE udc_config_speed_t udc_config_hs[1] = {{ - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs, - .udi_apis = udi_apis, -}}; -#endif - -//! Add all information about USB Device in global structure for UDC -UDC_DESC_STORAGE udc_config_t udc_config = { - .confdev_lsfs = &udc_device_desc, - .conf_lsfs = udc_config_lsfs, -#ifdef USB_DEVICE_HS_SUPPORT - .confdev_hs = &udc_device_desc, - .qualifier = &udc_device_qual, - .conf_hs = udc_config_hs, -#endif -}; - -//@} -/**INDENT-ON**/ -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/generic/module_config/conf_usb.h b/atmel-samd/asf/common/services/usb/class/hid/device/generic/module_config/conf_usb.h deleted file mode 100644 index 1430da240db64..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/generic/module_config/conf_usb.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - * \file - * - * \brief USB configuration file - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_USB_H_ -#define _CONF_USB_H_ - -#include "compiler.h" - -#warning You must refill the following definitions with a correct values - -/** - * USB Device Configuration - * @{ - */ - -//! Device definition (mandatory) -#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL -#define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_ASF_HIDGENERIC -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" -// #define USB_DEVICE_PRODUCT_NAME "Product name" -// #define USB_DEVICE_SERIAL_NAME "12...EF" - -/** - * Device speeds support - * @{ - */ -//! To define a Low speed device -//#define USB_DEVICE_LOW_SPEED - -//! To authorize the High speed -#if (UC3A3||UC3A4) -//#define USB_DEVICE_HS_SUPPORT -#endif -//@} - -/** - * USB Device Callbacks definitions (Optional) - * @{ - */ -// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high) -// extern void user_callback_vbus_action(bool b_vbus_high); -// #define UDC_SOF_EVENT() user_callback_sof_action() -// extern void user_callback_sof_action(void); -// #define UDC_SUSPEND_EVENT() user_callback_suspend_action() -// extern void user_callback_suspend_action(void); -// #define UDC_RESUME_EVENT() user_callback_resume_action() -// extern void user_callback_resume_action(void); -//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature -// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() -// extern void user_callback_remotewakeup_enable(void); -// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() -// extern void user_callback_remotewakeup_disable(void); -//! When a extra string descriptor must be supported -//! other than manufacturer, product and serial string -// #define UDC_GET_EXTRA_STRING() -//@} - -//@} - - -/** - * USB Interface Configuration - * @{ - */ -/** - * Configuration of HID Generic interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_GENERIC_ENABLE_EXT() true -#define UDI_HID_GENERIC_DISABLE_EXT() -#define UDI_HID_GENERIC_REPORT_OUT(ptr) -#define UDI_HID_GENERIC_SET_FEATURE(f) -/* - * #define UDI_HID_GENERIC_ENABLE_EXT() my_callback_generic_enable() - * extern bool my_callback_generic_enable(void); - * #define UDI_HID_GENERIC_DISABLE_EXT() my_callback_generic_disable() - * extern void my_callback_generic_disable(void); - * #define UDI_HID_GENERIC_REPORT_OUT(ptr) my_callback_generic_report_out(ptr) - * extern void my_callback_generic_report_out(uint8_t *report); - * #define UDI_HID_GENERIC_SET_FEATURE(f) my_callback_generic_set_feature(f) - * extern void my_callback_generic_set_feature(uint8_t *report_feature); - */ - -//! Sizes of I/O reports -#define UDI_HID_REPORT_IN_SIZE 64 -#define UDI_HID_REPORT_OUT_SIZE 64 -#define UDI_HID_REPORT_FEATURE_SIZE 4 - -//! Sizes of I/O endpoints -#define UDI_HID_GENERIC_EP_SIZE 64 -//@} -//@} - - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_hid_generic_conf.h" - -#endif // _CONF_USB_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic.c b/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic.c deleted file mode 100644 index aa0df32f95714..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic.c +++ /dev/null @@ -1,313 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) generic interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udd.h" -#include "udc.h" -#include "udi_hid.h" -#include "udi_hid_generic.h" -#include - -/** - * \ingroup udi_hid_generic_group - * \defgroup udi_hid_generic_group_udc Interface with USB Device Core (UDC) - * - * Structures and functions required by UDC. - * - * @{ - */ -bool udi_hid_generic_enable(void); -void udi_hid_generic_disable(void); -bool udi_hid_generic_setup(void); -uint8_t udi_hid_generic_getsetting(void); - -//! Global structure which contains standard UDI interface for UDC -UDC_DESC_STORAGE udi_api_t udi_api_hid_generic = { - .enable = (bool(*)(void))udi_hid_generic_enable, - .disable = (void (*)(void))udi_hid_generic_disable, - .setup = (bool(*)(void))udi_hid_generic_setup, - .getsetting = (uint8_t(*)(void))udi_hid_generic_getsetting, - .sof_notify = NULL, -}; -//@} - - -/** - * \ingroup udi_hid_generic_group - * \defgroup udi_hid_generic_group_internal Implementation of UDI HID Generic - * - * Class internal implementation - * @{ - */ - -/** - * \name Internal defines and variables to manage HID generic - */ -//@{ - -//! To store current rate of HID generic -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_generic_rate; -//! To store current protocol of HID generic -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_generic_protocol; -//! To signal if the report IN buffer is free (no transfer on going) -static bool udi_hid_generic_b_report_in_free; -//! Report to send -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_generic_report_in[UDI_HID_REPORT_IN_SIZE]; -//! Report to receive -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_generic_report_out[UDI_HID_REPORT_OUT_SIZE]; -//! Report to receive via SetFeature -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_generic_report_feature[UDI_HID_REPORT_FEATURE_SIZE]; - -//@} - -//! HID report descriptor for standard HID generic -UDC_DESC_STORAGE udi_hid_generic_report_desc_t udi_hid_generic_report_desc = { { - 0x06, 0xFF, 0xFF, // 04|2 , Usage Page (vendor defined?) - 0x09, 0x01, // 08|1 , Usage (vendor defined - 0xA1, 0x01, // A0|1 , Collection (Application) - // IN report - 0x09, 0x02, // 08|1 , Usage (vendor defined) - 0x09, 0x03, // 08|1 , Usage (vendor defined) - 0x15, 0x00, // 14|1 , Logical Minimum(0 for signed byte?) - 0x26, 0xFF, 0x00, // 24|1 , Logical Maximum(255 for signed byte?) - 0x75, 0x08, // 74|1 , Report Size(8) = field size in bits = 1 byte - // 94|1 , ReportCount(size) = repeat count of previous item - 0x95, sizeof(udi_hid_generic_report_in), - 0x81, 0x02, // 80|1 , IN report (Data,Variable, Absolute) - // OUT report - 0x09, 0x04, // 08|1 , Usage (vendor defined) - 0x09, 0x05, // 08|1 , Usage (vendor defined) - 0x15, 0x00, // 14|1 , Logical Minimum(0 for signed byte?) - 0x26, 0xFF, 0x00, // 24|1 , Logical Maximum(255 for signed byte?) - 0x75, 0x08, // 74|1 , Report Size(8) = field size in bits = 1 byte - // 94|1 , ReportCount(size) = repeat count of previous item - 0x95, sizeof(udi_hid_generic_report_out), - 0x91, 0x02, // 90|1 , OUT report (Data,Variable, Absolute) - // Feature report - 0x09, 0x06, // 08|1 , Usage (vendor defined) - 0x09, 0x07, // 08|1 , Usage (vendor defined) - 0x15, 0x00, // 14|1 , LogicalMinimum(0 for signed byte) - 0x26, 0xFF, 0x00, // 24|1 , Logical Maximum(255 for signed byte) - 0x75, 0x08, // 74|1 , Report Size(8) =field size in bits = 1 byte - 0x95, sizeof(udi_hid_generic_report_feature), // 94|x , ReportCount in byte - 0xB1, 0x02, // B0|1 , Feature report - 0xC0 // C0|0 , End Collection - } -}; - -/** - * \name Internal routines - */ -//@{ - -/** - * \brief Send a report to HID interface - * - */ -static bool udi_hid_generic_setreport(void); - -/** - * \brief Initialize UDD to receive setfeature data - */ -static void udi_hid_generic_setfeature_valid(void); - -/** - * \brief Callback called when the report is received - * - * \param status UDD_EP_TRANSFER_OK, if transfer is completed - * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted - * \param nb_sent number of data received - */ -static void udi_hid_generic_report_out_received(udd_ep_status_t status, - iram_size_t nb_received, udd_ep_id_t ep); - -/** - * \brief Enable reception of out report - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -static bool udi_hid_generic_report_out_enable(void); - -/** - * \brief Callback called when the report is sent - * - * \param status UDD_EP_TRANSFER_OK, if transfer is completed - * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted - * \param nb_sent number of data transfered - */ -static void udi_hid_generic_report_in_sent(udd_ep_status_t status, - iram_size_t nb_sent, udd_ep_id_t ep); - -//@} - - -//-------------------------------------------- -//------ Interface for UDI HID level - -bool udi_hid_generic_enable(void) -{ - // Initialize internal values - udi_hid_generic_rate = 0; - udi_hid_generic_protocol = 0; - udi_hid_generic_b_report_in_free = true; - if (!udi_hid_generic_report_out_enable()) - return false; - return UDI_HID_GENERIC_ENABLE_EXT(); -} - - -void udi_hid_generic_disable(void) -{ - UDI_HID_GENERIC_DISABLE_EXT(); -} - - -bool udi_hid_generic_setup(void) -{ - return udi_hid_setup(&udi_hid_generic_rate, - &udi_hid_generic_protocol, - (uint8_t *) &udi_hid_generic_report_desc, - udi_hid_generic_setreport); -} - - -uint8_t udi_hid_generic_getsetting(void) -{ - return 0; -} - - -static bool udi_hid_generic_setreport(void) -{ - if ((USB_HID_REPORT_TYPE_FEATURE == (udd_g_ctrlreq.req.wValue >> 8)) - && (0 == (0xFF & udd_g_ctrlreq.req.wValue)) - && (sizeof(udi_hid_generic_report_feature) == - udd_g_ctrlreq.req.wLength)) { - // Feature type on report ID 0 - udd_g_ctrlreq.payload = - (uint8_t *) & udi_hid_generic_report_feature; - udd_g_ctrlreq.callback = udi_hid_generic_setfeature_valid; - udd_g_ctrlreq.payload_size = - sizeof(udi_hid_generic_report_feature); - return true; - } - return false; -} - -//-------------------------------------------- -//------ Interface for application - -bool udi_hid_generic_send_report_in(uint8_t *data) -{ - if (!udi_hid_generic_b_report_in_free) - return false; - irqflags_t flags = cpu_irq_save(); - // Fill report - memset(&udi_hid_generic_report_in, 0, - sizeof(udi_hid_generic_report_in)); - memcpy(&udi_hid_generic_report_in, data, - sizeof(udi_hid_generic_report_in)); - udi_hid_generic_b_report_in_free = - !udd_ep_run(UDI_HID_GENERIC_EP_IN, - false, - (uint8_t *) & udi_hid_generic_report_in, - sizeof(udi_hid_generic_report_in), - udi_hid_generic_report_in_sent); - cpu_irq_restore(flags); - return !udi_hid_generic_b_report_in_free; - -} - -//-------------------------------------------- -//------ Internal routines - -static void udi_hid_generic_setfeature_valid(void) -{ - if (sizeof(udi_hid_generic_report_feature) != udd_g_ctrlreq.payload_size) - return; // Bad data - UDI_HID_GENERIC_SET_FEATURE(udi_hid_generic_report_feature); -} - -static void udi_hid_generic_report_out_received(udd_ep_status_t status, - iram_size_t nb_received, udd_ep_id_t ep) -{ - UNUSED(ep); - if (UDD_EP_TRANSFER_OK != status) - return; // Abort reception - - if (sizeof(udi_hid_generic_report_out) == nb_received) { - UDI_HID_GENERIC_REPORT_OUT(udi_hid_generic_report_out); - } - udi_hid_generic_report_out_enable(); -} - - -static bool udi_hid_generic_report_out_enable(void) -{ - return udd_ep_run(UDI_HID_GENERIC_EP_OUT, - false, - (uint8_t *) & udi_hid_generic_report_out, - sizeof(udi_hid_generic_report_out), - udi_hid_generic_report_out_received); -} - - -static void udi_hid_generic_report_in_sent(udd_ep_status_t status, - iram_size_t nb_sent, udd_ep_id_t ep) -{ - UNUSED(status); - UNUSED(nb_sent); - UNUSED(ep); - udi_hid_generic_b_report_in_free = true; -} - -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic.h b/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic.h deleted file mode 100644 index d09e9c47cc1fc..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic.h +++ /dev/null @@ -1,384 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) generic interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_HID_GENERIC_H_ -#define _UDI_HID_GENERIC_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_hid.h" -#include "udc_desc.h" -#include "udi.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup udi_hid_generic_group_udc - * @{ - */ -//! Global structure which contains standard UDI API for UDC -extern UDC_DESC_STORAGE udi_api_t udi_api_hid_generic; -//@} - -/** - * \ingroup udi_hid_generic_group - * \defgroup udi_hid_generic_group_desc USB interface descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - */ -//@{ - -//! Interface descriptor structure for HID generic -typedef struct { - usb_iface_desc_t iface; - usb_hid_descriptor_t hid; - usb_ep_desc_t ep_in; - usb_ep_desc_t ep_out; -} udi_hid_generic_desc_t; - -//! Report descriptor for HID generic -typedef struct { - uint8_t array[53]; -} udi_hid_generic_report_desc_t; - - -//! By default no string associated to this interface -#ifndef UDI_HID_GENERIC_STRING_ID -#define UDI_HID_GENERIC_STRING_ID 0 -#endif - - - -//! Content of HID generic interface descriptor for all speed -#define UDI_HID_GENERIC_DESC {\ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_HID_GENERIC_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 2,\ - .iface.bInterfaceClass = HID_CLASS,\ - .iface.bInterfaceSubClass = HID_SUB_CLASS_NOBOOT,\ - .iface.bInterfaceProtocol = HID_PROTOCOL_GENERIC,\ - .iface.iInterface = UDI_HID_GENERIC_STRING_ID,\ - .hid.bLength = sizeof(usb_hid_descriptor_t),\ - .hid.bDescriptorType = USB_DT_HID,\ - .hid.bcdHID = LE16(USB_HID_BDC_V1_11),\ - .hid.bCountryCode = USB_HID_NO_COUNTRY_CODE,\ - .hid.bNumDescriptors = USB_HID_NUM_DESC,\ - .hid.bRDescriptorType = USB_DT_HID_REPORT,\ - .hid.wDescriptorLength = LE16(sizeof(udi_hid_generic_report_desc_t)),\ - .ep_in.bLength = sizeof(usb_ep_desc_t),\ - .ep_in.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_in.bEndpointAddress = UDI_HID_GENERIC_EP_IN,\ - .ep_in.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep_in.wMaxPacketSize = LE16(UDI_HID_GENERIC_EP_SIZE),\ - .ep_in.bInterval = 4,\ - .ep_out.bLength = sizeof(usb_ep_desc_t),\ - .ep_out.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_out.bEndpointAddress = UDI_HID_GENERIC_EP_OUT,\ - .ep_out.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep_out.wMaxPacketSize = LE16(UDI_HID_GENERIC_EP_SIZE),\ - .ep_out.bInterval = 4,\ - } -//@} - - -/** - * \ingroup udi_hid_group - * \defgroup udi_hid_generic_group USB Device Interface (UDI) for Human Interface Device (HID) Generic Class - * - * Common APIs used by high level application to use this USB class. - * - * See \ref udi_hid_generic_quickstart. - * @{ - */ - -/** - * \brief Routine used to send a report to USB Host - * - * \param data Pointer on the report to send (size = UDI_HID_REPORT_IN_SIZE) - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_generic_send_report_in(uint8_t *data); - -//@} - - -#ifdef __cplusplus -} -#endif - - -/** - * \page udi_hid_generic_quickstart Quick start guide for USB device generic module (UDI generic) - * - * This is the quick start guide for the \ref udi_hid_generic_group - * "USB device generic module (UDI generic)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * Also, you can refer to application note - * - * AVR4905: ASF - USB Device HID Generic Application. - * - * \section udi_hid_generic_basic_use_case Basic use case - * In this basic use case, the "USB HID Generic (Single Interface Device)" module is used. - * The "USB HID Generic (Composite Device)" module usage is described in \ref udi_hid_generic_use_cases - * "Advanced use cases". - * - * \section udi_hid_generic_basic_use_case_setup Setup steps - * \subsection udi_hid_generic_basic_use_case_setup_prereq Prerequisites - * \copydetails udc_basic_use_case_setup_prereq - * \subsection udi_hid_generic_basic_use_case_setup_code Example code - * \copydetails udc_basic_use_case_setup_code - * \subsection udi_hid_generic_basic_use_case_setup_flow Workflow - * \copydetails udc_basic_use_case_setup_flow - * - * \section udi_hid_generic_basic_use_case_usage Usage steps - * - * \subsection udi_hid_generic_basic_use_case_usage_code Example code - * Content of conf_usb.h: - * \code - #define UDI_HID_GENERIC_ENABLE_EXT() my_callback_generic_enable() - extern bool my_callback_generic_enable(void); - #define UDI_HID_GENERIC_DISABLE_EXT() my_callback_generic_disable() - extern void my_callback_generic_disable(void); - #define UDI_HID_GENERIC_REPORT_OUT(ptr) my_callback_generic_report_out(ptr) - extern void my_callback_generic_report_out(uint8_t *report); - #define UDI_HID_GENERIC_SET_FEATURE(f) my_callback_generic_set_feature(f) - extern void my_callback_generic_set_feature(uint8_t *report_feature); - - #define UDI_HID_REPORT_IN_SIZE 64 - #define UDI_HID_REPORT_OUT_SIZE 64 - #define UDI_HID_REPORT_FEATURE_SIZE 4 - #define UDI_HID_GENERIC_EP_SIZE 64 - - #include "udi_hid_generic_conf.h" // At the end of conf_usb.h file -\endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_generic_events = false; - bool my_callback_generic_enable(void) - { - my_flag_autorize_generic_events = true; - return true; - } - void my_callback_generic_disable(void) - { - my_flag_autorize_generic_events = false; - } - - void my_button_press_event(void) - { - if (!my_flag_autorize_generic_events) { - return; - } - uint8_t report[] = {0x00,0x01,0x02...}; - udi_hid_generic_send_report_in(report); - } - - void my_callback_generic_report_out(uint8_t *report) - { - if ((report[0] == MY_VALUE_0) - (report[1] == MY_VALUE_1)) { - // The report is correct - } - } - - void my_callback_generic_set_feature(uint8_t *report_feature) - { - if ((report_feature[0] == MY_VALUE_0) - (report_feature[1] == MY_VALUE_1)) { - // The report feature is correct - } - } -\endcode - * - * \subsection udi_hid_generic_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration - * which is the USB device generic configuration: - * - \code #define UDI_HID_GENERIC_ENABLE_EXT() my_callback_generic_enable() - extern bool my_callback_generic_enable(void); \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB generic interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_HID_GENERIC_ENABLE_EXT() callback function is called and return true. - * Thus, it is recommended to enable sensors used by the generic in this function. - * - \code #define UDI_HID_GENERIC_DISABLE_EXT() my_callback_generic_disable() - extern void my_callback_generic_disable(void); \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_HID_GENERIC_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable sensors used by the HID generic - * interface in this function. - * - \code #define UDI_HID_GENERIC_REPORT_OUT(ptr) my_callback_generic_report_out(ptr) - extern void my_callback_generic_report_out(uint8_t *report); \endcode - * \note Callback used to receive the OUT report. - * - \code #define UDI_HID_GENERIC_SET_FEATURE(f) my_callback_generic_set_feature(f) - extern void my_callback_generic_set_feature(uint8_t *report_feature); \endcode - * \note Callback used to receive the SET FEATURE report. - * - \code #define UDI_HID_REPORT_IN_SIZE 64 - #define UDI_HID_REPORT_OUT_SIZE 64 - #define UDI_HID_REPORT_FEATURE_SIZE 4 \endcode - * \note The report size are defined by the final application. - * - \code #define UDI_HID_GENERIC_EP_SIZE 64 \endcode - * \note The interrupt endpoint size is defined by the final application. - - * -# Send a IN report: - * - \code uint8_t report[] = {0x00,0x01,0x02...}; - udi_hid_generic_send_report_in(report); \endcode - * - * \section udi_hid_generic_use_cases Advanced use cases - * For more advanced use of the UDI HID generic module, see the following use cases: - * - \subpage udi_hid_generic_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - */ - -/** - * \page udi_hid_generic_use_case_composite HID generic in a composite device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB HID Generic (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB MSC (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_hid_generic_use_case_composite_setup Setup steps - * For the setup code of this use case to work, the - * \ref udi_hid_generic_basic_use_case "basic use case" must be followed. - * - * \section udi_hid_generic_use_case_composite_usage Usage steps - * - * \subsection udi_hid_generic_use_case_composite_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+2) - - #define UDI_HID_GENERIC_EP_IN (1 | USB_EP_DIR_IN) - #define UDI_HID_GENERIC_EP_OUT (2 | USB_EP_DIR_OUT) - #define UDI_HID_GENERIC_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_hid_generic_desc_t udi_hid_generic; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_hid_generic, \ - ... -\endcode - * - * \subsection udi_hid_generic_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * - \code // Endpoint control size, This must be: - // - 8 for low speed - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for HID generic. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 1 for HID generic. - #define USB_DEVICE_MAX_EP (X+2) \endcode - * -# Ensure that conf_usb.h contains the description of - * composite device: - * - \code // The endpoint number chosen by you for the generic. - // The endpoint number starting from 1. - #define UDI_HID_GENERIC_EP_IN (1 | USB_EP_DIR_IN) - #define UDI_HID_GENERIC_EP_OUT (2 | USB_EP_DIR_OUT) - // The interface index of an interface starting from 0 - #define UDI_HID_GENERIC_IFACE_NUMBER X \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * - \code // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_hid_generic_desc_t udi_hid_generic; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_hid_generic, \ - ... \endcode - * - \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -#endif // _UDI_HID_GENERIC_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_conf.h b/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_conf.h deleted file mode 100644 index 06a69b5bc2526..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_conf.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * \file - * - * \brief Default HID generic configuration for a USB Device - * with a single interface HID - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_HID_GENERIC_CONF_H_ -#define _UDI_HID_GENERIC_CONF_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup udi_hid_generic_group_single_desc - * @{ - */ - -//! Control endpoint size -#ifdef USB_DEVICE_HS_SUPPORT -# define USB_DEVICE_EP_CTRL_SIZE 64 -#else -# define USB_DEVICE_EP_CTRL_SIZE 8 -#endif - -//! Endpoint number used by HID generic interface -#define UDI_HID_GENERIC_EP_OUT (2 | USB_EP_DIR_OUT) -#define UDI_HID_GENERIC_EP_IN (1 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_GENERIC_IFACE_NUMBER 0 - - -/** - * \name UDD Configuration - */ -//@{ -//! 2 endpoints used by HID generic standard interface -#undef USB_DEVICE_MAX_EP // undefine this definition in header file -#define USB_DEVICE_MAX_EP 2 -//@} - -//@} - -#ifdef __cplusplus -} -#endif - -#include "udi_hid_generic.h" - -#endif // _UDI_HID_GENERIC_CONF_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_desc.c b/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_desc.c deleted file mode 100644 index 49b72ca592581..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_desc.c +++ /dev/null @@ -1,169 +0,0 @@ -/** - * \file - * - * \brief Default descriptors for a USB Device - * with a single interface HID generic - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi_hid.h" -#include "udi_hid_generic.h" - -/** - * \ingroup udi_hid_generic_group - * \defgroup udi_hid_generic_group_single_desc USB device descriptors for a single interface - * - * The following structures provide the USB device descriptors required - * for USB Device with a single interface HID generic. - * - * It is ready to use and do not require more definition. - * - * @{ - */ - -//! Only one interface for this device -#define USB_DEVICE_NB_INTERFACE 1 - -//! USB Device Descriptor -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = { - .bLength = sizeof(usb_dev_desc_t), - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .idVendor = LE16(USB_DEVICE_VENDOR_ID), - .idProduct = LE16(USB_DEVICE_PRODUCT_ID), - .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8) - | USB_DEVICE_MINOR_VERSION), -#ifdef USB_DEVICE_MANUFACTURE_NAME - .iManufacturer = 1, -#else - .iManufacturer = 0, // No manufacture string -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - .iProduct = 2, -#else - .iProduct = 0, // No product string -#endif -#ifdef USB_DEVICE_SERIAL_NAME - .iSerialNumber = 3, -#else - .iSerialNumber = 0, // No serial string -#endif - .bNumConfigurations = 1 -}; - - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Qualifier Descriptor for HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = { - .bLength = sizeof(usb_dev_qual_desc_t), - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .bNumConfigurations = 1 -}; -#endif - -//! Structure for USB Device Configuration Descriptor -COMPILER_PACK_SET(1) -typedef struct { - usb_conf_desc_t conf; - udi_hid_generic_desc_t hid_generic; -} udc_desc_t; -COMPILER_PACK_RESET() - -//! USB Device Configuration Descriptor filled for FS and HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_desc_t udc_desc = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), - .hid_generic = UDI_HID_GENERIC_DESC, -}; - - -/** - * \name UDC structures which contains all USB Device definitions - */ -//@{ - -//! Associate an UDI for each USB interface -UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = { - &udi_api_hid_generic, -}; - -//! Add UDI with USB Descriptors FS & HS -UDC_DESC_STORAGE udc_config_speed_t udc_config_fshs[1] = { { - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc, - .udi_apis = udi_apis, -}}; - -//! Add all information about USB Device in global structure for UDC -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_config_t udc_config = { - .confdev_lsfs = &udc_device_desc, - .conf_lsfs = udc_config_fshs, -#ifdef USB_DEVICE_HS_SUPPORT - .confdev_hs = &udc_device_desc, - .qualifier = &udc_device_qual, - .conf_hs = udc_config_fshs, -#endif -}; - -//@} -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_doc.h b/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_doc.h deleted file mode 100644 index b3397d7fff8b2..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/generic/udi_hid_generic_doc.h +++ /dev/null @@ -1,482 +0,0 @@ -/** - * \file - * - * \brief USB device driver for Human Interface Device (HID) generic interface. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup asfdoc_udi_hid_generic_group USB Device Interface (UDI) for Human Interface Device Generic (HID Generic) - * - * USB Device Interface (UDI) for Human Interface Device generic (HID generic) provides an - * interface for the configuration and management of USB HID generic device. - * - * The outline of this documentation is as follows: - * - \ref asfdoc_udi_hid_generic_api_overview - * - \ref asfdoc_udi_hid_generic_exqsg - * - \ref asfdoc_udi_hid_generic_config_examples - * - * For more details for Atmel® Software Framework (ASF) USB Device Stack and - * USB Device HID generic, refer to following application notes: - * - - * AVR4900: ASF - USB Device Stack - * - - * AVR4905: ASF - USB Device HID Generic Application - * - - * AVR4920: ASF - USB Device Stack - Compliance and Performance Figures - * - - * AVR4921: ASF - USB Device Stack Differences between ASF V1 and V2 - * - * \section asfdoc_udi_hid_generic_api_overview API Overview - * @{ - */ - -/** - * \name Interface with USB Device Core (UDC) - * - * Structure required by UDC. - * - * @{ - */ - -/** Global structure which contains standard UDI API for UDC. */ -extern UDC_DESC_STORAGE udi_api_t udi_api_hid_generic; -/**@}*/ - -/** - * \name USB Interface Descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - * - * @{ - */ - - /** Interface descriptor structure for HID generic. */ -typedef struct { - /** Standard USB interface descriptor structure */ - usb_iface_desc_t iface; - /** HID Descriptor */ - usb_hid_descriptor_t hid; - /** Standard USB endpoint descriptor structure */ - usb_ep_desc_t ep_in; - /** Standard USB endpoint descriptor structure */ - usb_ep_desc_t ep_out; -} udi_hid_generic_desc_t; - -/** Report descriptor for HID generic. */ -typedef struct { - /** Array to put detailed report data */ - uint8_t array[53]; -} udi_hid_generic_report_desc_t; - - -/** By default no string associated to this interface. */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UDI_HID_GENERIC_STRING_ID -#define UDI_HID_GENERIC_STRING_ID 0 -#endif - -/** Content of HID generic interface descriptor for all speed. */ -#define UDI_HID_GENERIC_DESC {\ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_HID_GENERIC_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 2,\ - .iface.bInterfaceClass = HID_CLASS,\ - .iface.bInterfaceSubClass = HID_SUB_CLASS_NOBOOT,\ - .iface.bInterfaceProtocol = HID_PROTOCOL_GENERIC,\ - .iface.iInterface = UDI_HID_GENERIC_STRING_ID,\ - .hid.bLength = sizeof(usb_hid_descriptor_t),\ - .hid.bDescriptorType = USB_DT_HID,\ - .hid.bcdHID = LE16(USB_HID_BDC_V1_11),\ - .hid.bCountryCode = USB_HID_NO_COUNTRY_CODE,\ - .hid.bNumDescriptors = USB_HID_NUM_DESC,\ - .hid.bRDescriptorType = USB_DT_HID_REPORT,\ - .hid.wDescriptorLength = LE16(sizeof(udi_hid_generic_report_desc_t)),\ - .ep_in.bLength = sizeof(usb_ep_desc_t),\ - .ep_in.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_in.bEndpointAddress = UDI_HID_GENERIC_EP_IN,\ - .ep_in.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep_in.wMaxPacketSize = LE16(UDI_HID_GENERIC_EP_SIZE),\ - .ep_in.bInterval = 4,\ - .ep_out.bLength = sizeof(usb_ep_desc_t),\ - .ep_out.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_out.bEndpointAddress = UDI_HID_GENERIC_EP_OUT,\ - .ep_out.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep_out.wMaxPacketSize = LE16(UDI_HID_GENERIC_EP_SIZE),\ - .ep_out.bInterval = 4,\ - } -/**@}*/ - -/** - * \name USB Device Interface (UDI) for Human Interface Device (HID) Generic Class - * - * Common APIs used by high level application to use this USB class. - * @{ - */ - -/** - * \brief Routine used to send a report to USB Host - * - * \param[in] data Pointer on the report to send (size = UDI_HID_REPORT_IN_SIZE) - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_generic_send_report_in(uint8_t *data); -/**@}*/ -/**@}*/ - -/** - * \page asfdoc_udi_hid_generic_exqsg Quick Start Guide for USB Device Generic Module (UDI Generic) - * - * This is the quick start guide for the \ref asfdoc_udi_hid_generic_group - * "USB Device Generic Module (UDI Generic)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section udi_hid_generic_basic_use_case Basic Use Case - * In this basic use case, the "USB HID generic (Single Interface Device)" module is used. - * The "USB HID generic (Composite Device)" module usage is described in \ref udi_hid_generic_use_cases - * "Advanced Use Cases". - * - * \section udi_hid_generic_basic_use_case_setup Setup Steps - * As a USB device, it follows common USB device setup steps. Refer to - * \ref asfdoc_udc_basic_use_case_setup "USB Device Basic Setup". - * - * \section udi_hid_generic_basic_use_case_usage Usage Steps - * - * \subsection udi_hid_generic_basic_use_case_usage_code Example Code - * Content of conf_usb.h: - * \code - #define UDI_HID_generic_ENABLE_EXT() my_callback_generic_enable() - extern bool my_callback_generic_enable(void); - #define UDI_HID_generic_DISABLE_EXT() my_callback_generic_disable() - extern void my_callback_generic_disable(void); - #include "udi_hid_generic_conf.h" // At the end of conf_usb.h file - \endcode - * - * Add to application C-file: - * \code - #define UDI_HID_GENERIC_ENABLE_EXT() my_callback_generic_enable() - extern bool my_callback_generic_enable(void); - #define UDI_HID_GENERIC_DISABLE_EXT() my_callback_generic_disable() - extern void my_callback_generic_disable(void); - #define UDI_HID_GENERIC_REPORT_OUT(ptr) my_callback_generic_report_out(ptr) - extern void my_callback_generic_report_out(uint8_t *report); - #define UDI_HID_GENERIC_SET_FEATURE(f) my_callback_generic_set_feature(f) - extern void my_callback_generic_set_feature(uint8_t *report_feature); - - #define UDI_HID_REPORT_IN_SIZE 64 - #define UDI_HID_REPORT_OUT_SIZE 64 - #define UDI_HID_REPORT_FEATURE_SIZE 4 - #define UDI_HID_GENERIC_EP_SIZE 64 - - #include "udi_hid_generic_conf.h" // At the end of conf_usb.h file - \endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_generic_events = false; - bool my_callback_generic_enable(void) - { - my_flag_autorize_generic_events = true; - return true; - } - void my_callback_generic_disable(void) - { - my_flag_autorize_generic_events = false; - } - - void my_button_press_event(void) - { - if (!my_flag_autorize_generic_events) { - return; - } - uint8_t report[] = {0x00,0x01,0x02...}; - udi_hid_generic_send_report_in(report); - } - - void my_callback_generic_report_out(uint8_t *report) - { - if ((report[0] == MY_VALUE_0) - (report[1] == MY_VALUE_1)) { - // The report is correct - } - } - - void my_callback_generic_set_feature(uint8_t *report_feature) - { - if ((report_feature[0] == MY_VALUE_0) - (report_feature[1] == MY_VALUE_1)) { - // The report feature is correct - } - } - \endcode - * - * \subsection udi_hid_generic_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration - * which is the USB device generic configuration: - * \code - #define UDI_HID_GENERIC_ENABLE_EXT() my_callback_generic_enable() - extern bool my_callback_generic_enable(void); - \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB generic interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_HID_GENERIC_ENABLE_EXT() callback function is called and return true. - * Thus, it is recommended to enable sensors used by the generic in this function. - * - * \code - #define UDI_HID_GENERIC_DISABLE_EXT() my_callback_generic_disable() - extern void my_callback_generic_disable(void); - \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_HID_GENERIC_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable sensors used by the HID generic - * interface in this function. - * - * \code - #define UDI_HID_GENERIC_REPORT_OUT(ptr) my_callback_generic_report_out(ptr) - extern void my_callback_generic_report_out(uint8_t *report); - \endcode - * \note Callback used to receive the OUT report. - * - * \code - #define UDI_HID_GENERIC_SET_FEATURE(f) my_callback_generic_set_feature(f) - extern void my_callback_generic_set_feature(uint8_t *report_feature); - \endcode - * \note Callback used to receive the SET FEATURE report. - * - * \code - #define UDI_HID_REPORT_IN_SIZE 64 - #define UDI_HID_REPORT_OUT_SIZE 64 - #define UDI_HID_REPORT_FEATURE_SIZE 4 - \endcode - * \note The report size are defined by the final application. - * - * \code - #define UDI_HID_GENERIC_EP_SIZE 64 - \endcode - * \note The interrupt endpoint size is defined by the final application. - - * -# Send a IN report: - * \code - uint8_t report[] = {0x00,0x01,0x02...}; - udi_hid_generic_send_report_in(report); - \endcode - * - * \section udi_hid_generic_use_cases Advanced Use Cases - * \ifnot ASF_MANUAL - * For more advanced use of the UHI HID generic module, see the following use cases: - * - \subpage udi_hid_generic_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - * \else - * For multiple interface use of UDI HID module, see the following: - * - \subpage udi_hid_generic_use_case_composite - * - * For more advanced use of the UDI HID generic module, see the following: - * - \ref asfdoc_udc_use_cases - * \endif - */ - -/** - * \page udi_hid_generic_use_case_composite HID Generic in a Composite Device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB HID Generic (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB MSC (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_hid_generic_use_case_composite_setup Setup Steps - * For the setup code of this use case to work, the - * \ref udi_hid_generic_basic_use_case "Basic Use Case" must be followed. - * - * \section udi_hid_generic_use_case_composite_usage Usage Steps - * - * \subsection udi_hid_generic_use_case_composite_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+2) - - #define UDI_HID_GENERIC_EP_IN (1 | USB_EP_DIR_IN) - #define UDI_HID_GENERIC_EP_OUT (2 | USB_EP_DIR_OUT) - #define UDI_HID_GENERIC_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_hid_generic_desc_t udi_hid_generic; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_hid_generic, \ - ... - \endcode - * - * \subsection udi_hid_generic_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * \code - // Endpoint control size, This must be: - // - 8 for low speed - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for HID generic. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 1 for HID generic. - #define USB_DEVICE_MAX_EP (X+2) - \endcode - * -# Ensure that conf_usb.h contains the description of - * composite device: - * \code - // The endpoint number chosen by you for the generic. - // The endpoint number starting from 1. - #define UDI_HID_GENERIC_EP_IN (1 | USB_EP_DIR_IN) - #define UDI_HID_GENERIC_EP_OUT (2 | USB_EP_DIR_OUT) - // The interface index of an interface starting from 0 - #define UDI_HID_GENERIC_IFACE_NUMBER X - \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * \code - // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_hid_generic_desc_t udi_hid_generic; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_hid_generic = UDI_HID_GENERIC_DESC, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_hid_generic, \ - ... - \endcode - * \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -/** - * \page asfdoc_udi_hid_generic_config_examples Configuration File Examples - * - * \section asfdoc_udi_hid_generic_config_examples_1 conf_usb.h - * \subsection asfdoc_udi_hid_generic_config_examples_1_1 UDI HID GENERIC Single - * \include module_config/conf_usb.h - * \subsection asfdoc_udi_hid_generic_config_examples_1_2 UDI HID GENERIC Multiple (Composite) - * \include composite/device/module_config/conf_usb.h - * - * \section asfdoc_udi_hid_generic_config_examples_2 conf_clock.h - * - * \subsection asfdoc_udi_hid_generic_config_examples_2_1 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_clock.h - * - * \subsection asfdoc_udi_hid_generic_config_examples_2_2 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_clock.h - * - * \section asfdoc_udi_hid_generic_config_examples_3 conf_clocks.h - * - * \subsection asfdoc_udi_hid_generic_config_examples_3_1 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_clocks.h - * - * \section asfdoc_udi_hid_generic_config_examples_4 conf_board.h - * - * \subsection asfdoc_udi_hid_generic_config_examples_4_1 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_board.h - * - * \subsection asfdoc_udi_hid_generic_config_examples_4_2 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_board.h - * - * \subsection asfdoc_udi_hid_generic_config_examples_4_3 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_board.h - */ - -/** - * \page asfdoc_udi_hid_generic_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42339B12/2015Fixed typos
42339A12/2014Initial release
- */ \ No newline at end of file diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/module_config/conf_usb.h b/atmel-samd/asf/common/services/usb/class/hid/device/kbd/module_config/conf_usb.h deleted file mode 100644 index 85a4ac05814f0..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/module_config/conf_usb.h +++ /dev/null @@ -1,145 +0,0 @@ -/** - * \file - * - * \brief USB configuration file - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_USB_H_ -#define _CONF_USB_H_ - -#include "compiler.h" - -#warning You must refill the following definitions with a correct values - -/** - * USB Device Configuration - * @{ - */ - -//! Device definition (mandatory) -#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL -#define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_ASF_HIDKEYBOARD -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" -// #define USB_DEVICE_PRODUCT_NAME "Product name" -// #define USB_DEVICE_SERIAL_NAME "12...EF" - -/** - * Device speeds support - * @{ - */ -//! To define a Low speed device -//#define USB_DEVICE_LOW_SPEED - -//! To authorize the High speed -#if (UC3A3||UC3A4) -//#define USB_DEVICE_HS_SUPPORT -#endif -//@} - -/** - * USB Device Callbacks definitions (Optional) - * @{ - */ -// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high) -// extern void user_callback_vbus_action(bool b_vbus_high); -// #define UDC_SOF_EVENT() user_callback_sof_action() -// extern void user_callback_sof_action(void); -// #define UDC_SUSPEND_EVENT() user_callback_suspend_action() -// extern void user_callback_suspend_action(void); -// #define UDC_RESUME_EVENT() user_callback_resume_action() -// extern void user_callback_resume_action(void); -//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature -// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() -// extern void user_callback_remotewakeup_enable(void); -// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() -// extern void user_callback_remotewakeup_disable(void); -//! When a extra string descriptor must be supported -//! other than manufacturer, product and serial string -// #define UDC_GET_EXTRA_STRING() -//@} - -//@} - - -/** - * USB Interface Configuration - * @{ - */ -/** - * Configuration of HID Keyboard interface (if used) - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() true -#define UDI_HID_KBD_DISABLE_EXT() -// #define UDI_HID_KBD_ENABLE_EXT() my_callback_keyboard_enable() -// extern bool my_callback_keyboard_enable(void); -// #define UDI_HID_KBD_DISABLE_EXT() my_callback_keyboard_disable() -// extern void my_callback_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) -// #define UDI_HID_KBD_CHANGE_LED(value) my_callback_keyboard_led(value) -// extern void my_callback_keyboard_led(uint8_t value) -//@} -//@} - - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_hid_kbd_conf.h" - -#endif // _CONF_USB_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd.c b/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd.c deleted file mode 100644 index 8b4cd5bb1c175..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd.c +++ /dev/null @@ -1,395 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) keyboard interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udd.h" -#include "udc.h" -#include "udi_hid.h" -#include "udi_hid_kbd.h" -#include - -/** - * \ingroup udi_hid_keyboard_group - * \defgroup udi_hid_keyboard_group_udc Interface with USB Device Core (UDC) - * - * Structures and functions required by UDC. - * - * @{ - */ - -bool udi_hid_kbd_enable(void); -void udi_hid_kbd_disable(void); -bool udi_hid_kbd_setup(void); -uint8_t udi_hid_kbd_getsetting(void); - -//! Global structure which contains standard UDI interface for UDC -// CircuitPython fix: UDC_DESC_STORAGE must be COMPILER_WORD_ALIGNED -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udi_api_t udi_api_hid_kbd = { - .enable = (bool(*)(void))udi_hid_kbd_enable, - .disable = (void (*)(void))udi_hid_kbd_disable, - .setup = (bool(*)(void))udi_hid_kbd_setup, - .getsetting = (uint8_t(*)(void))udi_hid_kbd_getsetting, - .sof_notify = NULL, -}; -//@} - - -/** - * \ingroup udi_hid_keyboard_group - * \defgroup udi_hid_keyboard_group_internal Implementation of UDI HID keyboard - * - * Class internal implementation - * @{ - */ - -/** - * \name Internal defines and variables to manage HID keyboard - */ -//@{ - -//! Size of report for standard HID keyboard -#define UDI_HID_KBD_REPORT_SIZE 8 - - -//! To store current rate of HID keyboard -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_kbd_rate; -//! To store current protocol of HID keyboard -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_kbd_protocol; -//! To store report feedback from USB host -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_kbd_report_set; -//! To signal if a valid report is ready to send -static bool udi_hid_kbd_b_report_valid; -//! Report ready to send -static uint8_t udi_hid_kbd_report[UDI_HID_KBD_REPORT_SIZE]; -//! Signal if a report transfer is on going -static bool udi_hid_kbd_b_report_trans_ongoing; -//! Buffer used to send report -COMPILER_WORD_ALIGNED - static uint8_t - udi_hid_kbd_report_trans[UDI_HID_KBD_REPORT_SIZE]; - -//@} - -//! HID report descriptor for standard HID keyboard -// CircuitPython fix: UDC_DESC_STORAGE must be COMPILER_WORD_ALIGNED -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udi_hid_kbd_report_desc_t udi_hid_kbd_report_desc = { - { - 0x05, 0x01, /* Usage Page (Generic Desktop) */ - 0x09, 0x06, /* Usage (Keyboard) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x05, 0x07, /* Usage Page (Keyboard) */ - 0x19, 224, /* Usage Minimum (224) */ - 0x29, 231, /* Usage Maximum (231) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x08, /* Report Count (8) */ - 0x81, 0x02, /* Input (Data, Variable, Absolute) */ - 0x81, 0x01, /* Input (Constant) */ - 0x19, 0x00, /* Usage Minimum (0) */ - 0x29, 101, /* Usage Maximum (101) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 101, /* Logical Maximum (101) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x06, /* Report Count (6) */ - 0x81, 0x00, /* Input (Data, Array) */ - 0x05, 0x08, /* Usage Page (LED) */ - 0x19, 0x01, /* Usage Minimum (1) */ - 0x29, 0x05, /* Usage Maximum (5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x05, /* Report Count (5) */ - 0x91, 0x02, /* Output (Data, Variable, Absolute) */ - 0x95, 0x03, /* Report Count (3) */ - 0x91, 0x01, /* Output (Constant) */ - 0xC0 /* End Collection */ - } -}; - -/** - * \name Internal routines - */ -//@{ - -/** - * \brief Changes keyboard report states (like LEDs) - * - * \param rate New rate value - * - */ -static bool udi_hid_kbd_setreport(void); - -/** - * \brief Send the report - * - * \return \c 1 if send on going, \c 0 if delay. - */ -static bool udi_hid_kbd_send_report(void); - -/** - * \brief Callback called when the report is sent - * - * \param status UDD_EP_TRANSFER_OK, if transfer is completed - * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted - * \param nb_sent number of data transfered - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -static void udi_hid_kbd_report_sent(udd_ep_status_t status, iram_size_t nb_sent, - udd_ep_id_t ep); - -/** - * \brief Callback called to update report from USB host - * udi_hid_kbd_report_set is updated before callback execution - */ -static void udi_hid_kbd_setreport_valid(void); - -//@} - - -//-------------------------------------------- -//------ Interface for UDI HID level - -bool udi_hid_kbd_enable(void) -{ - // Initialize internal values - udi_hid_kbd_rate = 0; - udi_hid_kbd_protocol = 0; - udi_hid_kbd_b_report_trans_ongoing = false; - memset(udi_hid_kbd_report, 0, UDI_HID_KBD_REPORT_SIZE); - udi_hid_kbd_b_report_valid = false; - return UDI_HID_KBD_ENABLE_EXT(); -} - - -void udi_hid_kbd_disable(void) -{ - UDI_HID_KBD_DISABLE_EXT(); -} - - -bool udi_hid_kbd_setup(void) -{ - return udi_hid_setup(&udi_hid_kbd_rate, - &udi_hid_kbd_protocol, - (uint8_t *) &udi_hid_kbd_report_desc, - udi_hid_kbd_setreport); -} - - -uint8_t udi_hid_kbd_getsetting(void) -{ - return 0; -} - - -static bool udi_hid_kbd_setreport(void) -{ - if ((USB_HID_REPORT_TYPE_OUTPUT == (udd_g_ctrlreq.req.wValue >> 8)) - && (0 == (0xFF & udd_g_ctrlreq.req.wValue)) - && (1 == udd_g_ctrlreq.req.wLength)) { - // Report OUT type on report ID 0 from USB Host - udd_g_ctrlreq.payload = &udi_hid_kbd_report_set; - udd_g_ctrlreq.callback = udi_hid_kbd_setreport_valid; - udd_g_ctrlreq.payload_size = 1; - return true; - } - return false; -} - - -//-------------------------------------------- -//------ Interface for application - -bool udi_hid_kbd_modifier_up(uint8_t modifier_id) -{ - irqflags_t flags = cpu_irq_save(); - - // Fill report - udi_hid_kbd_report[0] &= ~(unsigned)modifier_id; - udi_hid_kbd_b_report_valid = true; - - // Send report - udi_hid_kbd_send_report(); - - cpu_irq_restore(flags); - return true; -} - - -bool udi_hid_kbd_modifier_down(uint8_t modifier_id) -{ - irqflags_t flags = cpu_irq_save(); - - // Fill report - udi_hid_kbd_report[0] |= modifier_id; - udi_hid_kbd_b_report_valid = true; - - // Send report - udi_hid_kbd_send_report(); - - cpu_irq_restore(flags); - return true; -} - - -bool udi_hid_kbd_up(uint8_t key_id) -{ - uint8_t i; - - irqflags_t flags = cpu_irq_save(); - - // Fill report - for (i = 2; i < UDI_HID_KBD_REPORT_SIZE; i++) { - if (0 == udi_hid_kbd_report[i]) { - // Already removed - cpu_irq_restore(flags); - return true; - } - if (key_id == udi_hid_kbd_report[i]) - break; - } - if (UDI_HID_KBD_REPORT_SIZE == i) { - // Already removed - cpu_irq_restore(flags); - return true; - } - // Remove key and shift - while (i < (UDI_HID_KBD_REPORT_SIZE - 1)) { - udi_hid_kbd_report[i] = udi_hid_kbd_report[i + 1]; - i++; - } - udi_hid_kbd_report[UDI_HID_KBD_REPORT_SIZE - 1] = 0x00; - udi_hid_kbd_b_report_valid = true; - - // Send report - udi_hid_kbd_send_report(); - - cpu_irq_restore(flags); - return true; -} - - -bool udi_hid_kbd_down(uint8_t key_id) -{ - uint8_t i; - - irqflags_t flags = cpu_irq_save(); - - // Fill report - for (i = 2; i < UDI_HID_KBD_REPORT_SIZE; i++) { - if (0 == udi_hid_kbd_report[i]) - break; - if (key_id == udi_hid_kbd_report[i]) { - // Already in array - cpu_irq_restore(flags); - return true; - } - } - - if (UDI_HID_KBD_REPORT_SIZE == i) { - // Array full - // TODO manage more than UDI_HID_KBD_REPORT_SIZE key pressed in same time - cpu_irq_restore(flags); - return false; - } - // Add key at the end of array - udi_hid_kbd_report[i] = key_id; - udi_hid_kbd_b_report_valid = true; - - // Send report - udi_hid_kbd_send_report(); - - // Enable IT - cpu_irq_restore(flags); - return true; -} - - -//-------------------------------------------- -//------ Internal routines - -static bool udi_hid_kbd_send_report(void) -{ - if (udi_hid_kbd_b_report_trans_ongoing) - return false; - memcpy(udi_hid_kbd_report_trans, udi_hid_kbd_report, - UDI_HID_KBD_REPORT_SIZE); - udi_hid_kbd_b_report_valid = false; - udi_hid_kbd_b_report_trans_ongoing = - udd_ep_run( UDI_HID_KBD_EP_IN, - false, - udi_hid_kbd_report_trans, - UDI_HID_KBD_REPORT_SIZE, - udi_hid_kbd_report_sent); - return udi_hid_kbd_b_report_trans_ongoing; -} - -static void udi_hid_kbd_report_sent(udd_ep_status_t status, iram_size_t nb_sent, - udd_ep_id_t ep) -{ - UNUSED(status); - UNUSED(nb_sent); - UNUSED(ep); - udi_hid_kbd_b_report_trans_ongoing = false; - if (udi_hid_kbd_b_report_valid) { - udi_hid_kbd_send_report(); - } -} - -static void udi_hid_kbd_setreport_valid(void) -{ - UDI_HID_KBD_CHANGE_LED(udi_hid_kbd_report_set); -} - -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd.h b/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd.h deleted file mode 100644 index 15818949fe002..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd.h +++ /dev/null @@ -1,367 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) keyboard interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDC_HID_KBD_H_ -#define _UDC_HID_KBD_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_hid.h" -#include "udc_desc.h" -#include "udi.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup udi_hid_keyboard_group_udc - * @{ - */ -//! Global structure which contains standard UDI API for UDC -extern UDC_DESC_STORAGE udi_api_t udi_api_hid_kbd; -//@} - -/** - * \ingroup udi_hid_keyboard_group - * \defgroup udi_hid_keyboard_group_desc USB interface descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - */ -//@{ - -//! Interface descriptor structure for HID keyboard -typedef struct { - usb_iface_desc_t iface; - usb_hid_descriptor_t hid; - usb_ep_desc_t ep; -} udi_hid_kbd_desc_t; - -//! Report descriptor for HID keyboard -typedef struct { - uint8_t array[59]; -} udi_hid_kbd_report_desc_t; - - -//! By default no string associated to this interface -#ifndef UDI_HID_KBD_STRING_ID -#define UDI_HID_KBD_STRING_ID 0 -#endif - -//! HID keyboard endpoints size -#define UDI_HID_KBD_EP_SIZE 8 - -//! Content of HID keyboard interface descriptor for all speed -#define UDI_HID_KBD_DESC {\ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_HID_KBD_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 1,\ - .iface.bInterfaceClass = HID_CLASS,\ - .iface.bInterfaceSubClass = HID_SUB_CLASS_NOBOOT,\ - .iface.bInterfaceProtocol = HID_PROTOCOL_KEYBOARD,\ - .iface.iInterface = UDI_HID_KBD_STRING_ID,\ - .hid.bLength = sizeof(usb_hid_descriptor_t),\ - .hid.bDescriptorType = USB_DT_HID,\ - .hid.bcdHID = LE16(USB_HID_BDC_V1_11),\ - .hid.bCountryCode = USB_HID_NO_COUNTRY_CODE,\ - .hid.bNumDescriptors = USB_HID_NUM_DESC,\ - .hid.bRDescriptorType = USB_DT_HID_REPORT,\ - .hid.wDescriptorLength = LE16(sizeof(udi_hid_kbd_report_desc_t)),\ - .ep.bLength = sizeof(usb_ep_desc_t),\ - .ep.bDescriptorType = USB_DT_ENDPOINT,\ - .ep.bEndpointAddress = UDI_HID_KBD_EP_IN,\ - .ep.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep.wMaxPacketSize = LE16(UDI_HID_KBD_EP_SIZE),\ - .ep.bInterval = 2,\ - } -//@} - - -/** - * \ingroup udi_hid_group - * \defgroup udi_hid_keyboard_group USB Device Interface (UDI) for Human Interface Device (HID) Keyboard Class - * - * Common APIs used by high level application to use this USB class. - * - * See \ref udi_hid_keyboard_quickstart. - * @{ - */ - -/** - * \brief Send events key modifier released - * - * \param modifier_id ID of key modifier - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_kbd_modifier_up(uint8_t modifier_id); - -/** - * \brief Send events key modifier pressed - * - * \param modifier_id ID of key modifier - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_kbd_modifier_down(uint8_t modifier_id); - - -/** - * \brief Send events key released - * - * \param key_id ID of key - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_kbd_up(uint8_t key_id); - -/** - * \brief Send events key pressed - * - * \param key_id ID of key - * - */ -bool udi_hid_kbd_down(uint8_t key_id); - -//@} - -#ifdef __cplusplus -} -#endif - -/** - * \page udi_hid_keyboard_quickstart Quick start guide for USB device keyboard module (UDI keyboard) - * - * This is the quick start guide for the \ref udi_hid_keyboard_group - * "USB device keyboard module (UDI keyboard)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * Also, you can refer to application note - * - * AVR4904: ASF - USB Device HID Keyboard Application. - * - * \section udi_hid_keyboard_basic_use_case Basic use case - * In this basic use case, the "USB HID Keyboard (Single Interface Device)" module is used. - * The "USB HID Keyboard (Composite Device)" module usage is described in \ref udi_hid_keyboard_use_cases - * "Advanced use cases". - * - * \section udi_hid_keyboard_basic_use_case_setup Setup steps - * \subsection udi_hid_keyboard_basic_use_case_setup_prereq Prerequisites - * \copydetails udc_basic_use_case_setup_prereq - * \subsection udi_hid_keyboard_basic_use_case_setup_code Example code - * \copydetails udc_basic_use_case_setup_code - * \subsection udi_hid_keyboard_basic_use_case_setup_flow Workflow - * \copydetails udc_basic_use_case_setup_flow - * - * \section udi_hid_keyboard_basic_use_case_usage Usage steps - * - * \subsection udi_hid_keyboard_basic_use_case_usage_code Example code - * Content of conf_usb.h: - * \code - #define UDI_HID_KBD_ENABLE_EXT() my_callback_keyboard_enable() - extern bool my_callback_keyboard_enable(void); - #define UDI_HID_KBD_DISABLE_EXT() my_callback_keyboard_disable() - extern void my_callback_keyboard_disable(void); - #include "udi_hid_keyboard_conf.h" // At the end of conf_usb.h file -\endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_keyboard_events = false; - bool my_callback_keyboard_enable(void) - { - my_flag_autorize_keyboard_events = true; - return true; - } - void my_callback_keyboard_disable(void) - { - my_flag_autorize_keyboard_events = false; - } - - void my_key_A_press_event(void) - { - if (!my_flag_autorize_keyboard_events) { - return; - } - udi_hid_kbd_up(HID_A); - } -\endcode - * - * \subsection udi_hid_keyboard_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration - * which is the USB device keyboard configuration: - * - \code #define UDI_HID_KBD_ENABLE_EXT() my_callback_keyboard_enable() - extern bool my_callback_keyboard_enable(void); \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB keyboard interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_HID_KBD_ENABLE_EXT() callback function is called and return true. - * Thus, it is recommended to enable sensors used by the keyboard in this function. - * - \code #define UDI_HID_KBD_DISABLE_EXT() my_callback_keyboard_disable() - extern void my_callback_keyboard_disable(void); \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_HID_KBD_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable sensors used by the keyboard - * in this function. - * -# send keyboard events: - * - \code // Send events key modifier released - udi_hid_kbd_modifier_up(uint8_t modifier_id); - // Send events key modifier pressed - udi_hid_kbd_modifier_down(uint8_t modifier_id); - // Send events key released - udi_hid_kbd_up(uint8_t key_id); - // Send events key pressed - udi_hid_kbd_down(uint8_t key_id); \endcode - * - * \section udi_hid_keyboard_use_cases Advanced use cases - * For more advanced use of the UDI HID keyboard module, see the following use cases: - * - \subpage udi_hid_keyboard_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - */ - -/** - * \page udi_hid_keyboard_use_case_composite HID keyboard in a composite device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB HID Keyboard (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB MSC (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_hid_keyboard_use_case_composite_setup Setup steps - * For the setup code of this use case to work, the - * \ref udi_hid_keyboard_basic_use_case "basic use case" must be followed. - * - * \section udi_hid_keyboard_use_case_composite_usage Usage steps - * - * \subsection udi_hid_keyboard_use_case_composite_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+1) - - #define UDI_HID_KBD_EP_IN (X | USB_EP_DIR_IN) - #define UDI_HID_KBD_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_hid_kbd_desc_t udi_hid_kbd; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_hid_kbd, \ - ... -\endcode - * - * \subsection udi_hid_keyboard_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * - \code // Endpoint control size, This must be: - // - 8 for low speed - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for HID keyboard. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 1 for HID keyboard. - #define USB_DEVICE_MAX_EP (X+1) \endcode - * -# Ensure that conf_usb.h contains the description of - * composite device: - * - \code // The endpoint number chosen by you for the keyboard. - // The endpoint number starting from 1. - #define UDI_HID_KBD_EP_IN (X | USB_EP_DIR_IN) - // The interface index of an interface starting from 0 - #define UDI_HID_KBD_IFACE_NUMBER X \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * - \code // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_hid_kbd_desc_t udi_hid_kbd; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_hid_kbd, \ - ... \endcode - * - \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -#endif // _UDC_HID_KBD_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_conf.h b/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_conf.h deleted file mode 100644 index f423ea1c4e4ad..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_conf.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - * \file - * - * \brief Default HID keyboard configuration for a USB Device - * with a single interface HID keyboard - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_HID_KBD_CONF_H_ -#define _UDI_HID_KBD_CONF_H_ - -/** - * \addtogroup udi_hid_keyboard_group_single_desc - * @{ - */ - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 8 - -//! Endpoint number used by HID keyboard interface -#define UDI_HID_KBD_EP_IN (1 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 0 - -/** - * \name UDD Configuration - */ -//@{ -//! 1 endpoint used by HID keyboard standard interface -#undef USB_DEVICE_MAX_EP // undefine this definition in header file -#define USB_DEVICE_MAX_EP 1 -//@} - -//@} - -#include "udi_hid_kbd.h" - -#endif // _UDI_HID_KBD_CONF_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_desc.c b/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_desc.c deleted file mode 100644 index 639ed27402dc5..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_desc.c +++ /dev/null @@ -1,167 +0,0 @@ -/** - * \file - * - * \brief Default descriptors for a USB Device - * with a single interface HID keyboard - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi_hid.h" -#include "udi_hid_kbd.h" - -/** - * \ingroup udi_hid_keyboard_group - * \defgroup udi_hid_keyboard_group_single_desc USB device descriptors for a single interface - * - * The following structures provide the USB device descriptors required - * for USB Device with a single interface HID keyboard. - * - * It is ready to use and do not require more definition. - * @{ - */ - -//! Only one interface for this device -#define USB_DEVICE_NB_INTERFACE 1 - -//! USB Device Descriptor -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = { - .bLength = sizeof(usb_dev_desc_t), - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .idVendor = LE16(USB_DEVICE_VENDOR_ID), - .idProduct = LE16(USB_DEVICE_PRODUCT_ID), - .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8) - | USB_DEVICE_MINOR_VERSION), -#ifdef USB_DEVICE_MANUFACTURE_NAME - .iManufacturer = 1, -#else - .iManufacturer = 0, // No manufacture string -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - .iProduct = 2, -#else - .iProduct = 0, // No product string -#endif -#ifdef USB_DEVICE_SERIAL_NAME - .iSerialNumber = 3, -#else - .iSerialNumber = 0, // No serial string -#endif - .bNumConfigurations = 1 -}; - - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Qualifier Descriptor for HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = { - .bLength = sizeof(usb_dev_qual_desc_t), - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .bNumConfigurations = 1 -}; -#endif - -//! Structure for USB Device Configuration Descriptor -COMPILER_PACK_SET(1) -typedef struct { - usb_conf_desc_t conf; - udi_hid_kbd_desc_t hid_kbd; -} udc_desc_t; -COMPILER_PACK_RESET() - -//! USB Device Configuration Descriptor filled for FS and HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_desc_t udc_desc = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), - .hid_kbd = UDI_HID_KBD_DESC, -}; - - -/** - * \name UDC structures which contains all USB Device definitions - */ -//@{ - -//! Associate an UDI for each USB interface -UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = { - &udi_api_hid_kbd, -}; - -//! Add UDI with USB Descriptors FS & HS -UDC_DESC_STORAGE udc_config_speed_t udc_config_fshs[1] = {{ - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc, - .udi_apis = udi_apis, -}}; - -//! Add all information about USB Device in global structure for UDC -UDC_DESC_STORAGE udc_config_t udc_config = { - .confdev_lsfs = &udc_device_desc, - .conf_lsfs = udc_config_fshs, -#ifdef USB_DEVICE_HS_SUPPORT - .confdev_hs = &udc_device_desc, - .qualifier = &udc_device_qual, - .conf_hs = udc_config_fshs, -#endif -}; - -//@} -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_doc.h b/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_doc.h deleted file mode 100644 index 68e88620d68e8..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/kbd/udi_hid_kbd_doc.h +++ /dev/null @@ -1,457 +0,0 @@ -/** - * \file - * - * \brief USB device driver for Human Interface Device (HID) keyboard interface. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup asfdoc_udi_hid_keyboard_group USB Device Interface (UDI) for Human Interface Device Keyboard (HID Keyboard) - * - * USB Device Interface (UDI) for Human Interface Device Keyboard (HID keyboard) provides an - * interface for the configuration and management of USB HID keyboard device. - * - * The outline of this documentation is as follows: - * - \ref asfdoc_udi_hid_keyboard_api_overview - * - \ref asfdoc_udi_hid_keyboard_exqsg - * - \ref asfdoc_udi_hid_keyboard_config_examples - * - * For more details for Atmel® Software Framework (ASF) USB Device Stack and - * USB Device HID keyboard, refer to following application notes: - * - - * AVR4900: ASF - USB Device Stack - * - - * AVR4904: ASF - USB Device HID Keyboard Application - * - - * AVR4920: ASF - USB Device Stack - Compliance and Performance Figures - * - - * AVR4921: ASF - USB Device Stack Differences between ASF V1 and V2 - * - * \section asfdoc_udi_hid_keyboard_api_overview API Overview - * @{ - */ - -/** - * \name Interface with USB Device Core (UDC) - * - * Variable required by UDC. - * - * @{ - */ - -/** Global structure which contains standard UDI API for UDC. */ -extern UDC_DESC_STORAGE udi_api_t udi_api_hid_kbd; -/**@}*/ - -/** - * \name USB Interface Descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - * - * @{ - */ - - /** Interface descriptor structure for HID keyboard. */ -typedef struct { - /** Standard USB interface descriptor structure */ - usb_iface_desc_t iface; - /** HID Descriptor */ - usb_hid_descriptor_t hid; - /** Standard USB endpoint descriptor structure */ - usb_ep_desc_t ep; -} udi_hid_kbd_desc_t; - -/** Report descriptor for HID keyboard. */ -typedef struct { - /** Array to put detailed report data */ - uint8_t array[59]; -} udi_hid_kbd_report_desc_t; - - -/** By default no string associated to this interface. */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UDI_HID_KBD_STRING_ID -#define UDI_HID_KBD_STRING_ID 0 -#endif - -/** HID keyboard endpoints size. */ -#define UDI_HID_KBD_EP_SIZE 8 - -/** Content of HID keyboard interface descriptor for all speed. */ -#define UDI_HID_KBD_DESC {\ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_HID_KBD_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 1,\ - .iface.bInterfaceClass = HID_CLASS,\ - .iface.bInterfaceSubClass = HID_SUB_CLASS_NOBOOT,\ - .iface.bInterfaceProtocol = HID_PROTOCOL_KEYBOARD,\ - .iface.iInterface = UDI_HID_KBD_STRING_ID,\ - .hid.bLength = sizeof(usb_hid_descriptor_t),\ - .hid.bDescriptorType = USB_DT_HID,\ - .hid.bcdHID = LE16(USB_HID_BDC_V1_11),\ - .hid.bCountryCode = USB_HID_NO_COUNTRY_CODE,\ - .hid.bNumDescriptors = USB_HID_NUM_DESC,\ - .hid.bRDescriptorType = USB_DT_HID_REPORT,\ - .hid.wDescriptorLength = LE16(sizeof(udi_hid_kbd_report_desc_t)),\ - .ep.bLength = sizeof(usb_ep_desc_t),\ - .ep.bDescriptorType = USB_DT_ENDPOINT,\ - .ep.bEndpointAddress = UDI_HID_KBD_EP_IN,\ - .ep.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep.wMaxPacketSize = LE16(UDI_HID_KBD_EP_SIZE),\ - .ep.bInterval = 2,\ - } -/**@}*/ - -/** - * \name USB Device Interface (UDI) for Human Interface Device (HID) Keyboard Class - * - * Common APIs used by high level application to use this USB class. - * @{ - */ - -/** - * \brief Send events key modifier released - * - * \param[in] modifier_id ID of key modifier - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_kbd_modifier_up(uint8_t modifier_id); - -/** - * \brief Send events key modifier pressed - * - * \param[in] modifier_id ID of key modifier - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_kbd_modifier_down(uint8_t modifier_id); - - -/** - * \brief Send events key released - * - * \param[in] key_id ID of key - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_kbd_up(uint8_t key_id); - -/** - * \brief Send events key pressed - * - * \param[in] key_id ID of key - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_kbd_down(uint8_t key_id); -/**@}*/ -/**@}*/ - -/** - * \page asfdoc_udi_hid_keyboard_exqsg Quick Start Guide for USB Device Keyboard Module (UDI Keyboard) - * - * This is the quick start guide for the \ref asfdoc_udi_hid_keyboard_group - * "USB Device Keyboard Module (UDI Keyboard)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section udi_hid_keyboard_basic_use_case Basic Use Case - * In this basic use case, the "USB HID keyboard (Single Interface Device)" module is used. - * The "USB HID keyboard (Composite Device)" module usage is described in \ref udi_hid_keyboard_use_cases - * "Advanced Use Cases". - * - * \section udi_hid_keyboard_basic_use_case_setup Setup Steps - * As a USB device, it follows common USB device setup steps. Refer to - * \ref asfdoc_udc_basic_use_case_setup "USB Device Basic Setup". - * - * \section udi_hid_keyboard_basic_use_case_usage Usage Steps - * - * \subsection udi_hid_keyboard_basic_use_case_usage_code Example Code - * Content of conf_usb.h: - * \code - #define UDI_HID_KBD_ENABLE_EXT() my_callback_keyboard_enable() - extern bool my_callback_keyboard_enable(void); - #define UDI_HID_KBD_DISABLE_EXT() my_callback_keyboard_disable() - extern void my_callback_keyboard_disable(void); - #include "udi_hid_keyboard_conf.h" // At the end of conf_usb.h file - \endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_keyboard_events = false; - bool my_callback_keyboard_enable(void) - { - my_flag_autorize_keyboard_events = true; - return true; - } - void my_callback_keyboard_disable(void) - { - my_flag_autorize_keyboard_events = false; - } - - void my_key_A_press_event(void) - { - if (!my_flag_autorize_keyboard_events) { - return; - } - udi_hid_kbd_up(HID_A); - } - \endcode - * - * \subsection udi_hid_keyboard_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration - * which is the USB device keyboard configuration: - * \code - #define UDI_HID_KBD_ENABLE_EXT() my_callback_keyboard_enable() - extern bool my_callback_keyboard_enable(void); - \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB keyboard interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_HID_KBD_ENABLE_EXT() callback function is called and return true. - * Thus, it is recommended to enable sensors used by the keyboard in this function. - * - * \code - #define UDI_HID_KBD_DISABLE_EXT() my_callback_keyboard_disable() - extern void my_callback_keyboard_disable(void); - \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_HID_KBD_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable sensors used by the keyboard - * in this function. - * - * -# Send keyboard events: - * \code - // Send events key modifier released - udi_hid_kbd_modifier_up(uint8_t modifier_id); - // Send events key modifier pressed - udi_hid_kbd_modifier_down(uint8_t modifier_id); - // Send events key released - udi_hid_kbd_up(uint8_t key_id); - // Send events key pressed - udi_hid_kbd_down(uint8_t key_id); - \endcode - * - * \section udi_hid_keyboard_use_cases Advanced Use Cases - * \ifnot ASF_MANUAL - * For more advanced use of the UHI HID keyboard module, see the following use cases: - * - \subpage udi_hid_keyboard_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - * \else - * For multiple interface use of UDI HID module, see the following: - * - \subpage udi_hid_keyboard_use_case_composite - * - * For more advanced use of the UDI HID keyboard module, see the following: - * - \ref asfdoc_udc_use_cases - * \endif - */ - -/** - * \page udi_hid_keyboard_use_case_composite HID Keyboard in a Composite Device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB HID Keyboard (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB MSC (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_hid_keyboard_use_case_composite_setup Setup Steps - * For the setup code of this use case to work, the - * \ref udi_hid_keyboard_basic_use_case "Basic Use Case" must be followed. - * - * \section udi_hid_keyboard_use_case_composite_usage Usage Steps - * - * \subsection udi_hid_keyboard_use_case_composite_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+1) - - #define UDI_HID_KBD_EP_IN (X | USB_EP_DIR_IN) - #define UDI_HID_KBD_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_hid_kbd_desc_t udi_hid_kbd; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_hid_kbd, \ - ... - \endcode - * - * \subsection udi_hid_keyboard_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * \code - // Endpoint control size, This must be: - // - 8 for low speed - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for HID keyboard. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 1 for HID keyboard. - #define USB_DEVICE_MAX_EP (X+1) - \endcode - * - * -# Ensure that conf_usb.h contains the description of - * composite device: - * \code - // The endpoint number chosen by you for the keyboard. - // The endpoint number starting from 1. - #define UDI_HID_KBD_EP_IN (X | USB_EP_DIR_IN) - // The interface index of an interface starting from 0 - #define UDI_HID_KBD_IFACE_NUMBER X - \endcode - * - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * \code - // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_hid_kbd_desc_t udi_hid_kbd; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_hid_kbd = UDI_HID_KBD_DESC, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_hid_kbd, \ - ... - \endcode - * \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -/** - * \page asfdoc_udi_hid_keyboard_config_examples Configuration File Examples - * - * \section asfdoc_udi_hid_keyboard_config_examples_1 conf_usb.h - * \subsection asfdoc_udi_hid_keyboard_config_examples_1_1 UDI HID KBD Single - * \include module_config/conf_usb.h - * \subsection asfdoc_udi_hid_keyboard_config_examples_1_2 UDI HID KBD Multiple (Composite) - * \include composite/device/module_config/conf_usb.h - * - * \section asfdoc_udi_hid_keyboard_config_examples_2 conf_clock.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_2_1 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3b0256_evk1101/conf_clock.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_2_2 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/atuc128d3_stk600-rcuc3d/conf_clock.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_2_3 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_clock.h - * - * \section asfdoc_udi_hid_keyboard_config_examples_3 conf_clocks.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_3_1 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_clocks.h - * - * \section asfdoc_udi_hid_keyboard_config_examples_4 conf_board.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_4_1 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3b0256_evk1101/conf_board.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_4_2 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/atuc128d3_stk600-rcuc3d/conf_board.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_4_3 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_board.h - * - * \subsection asfdoc_udi_hid_keyboard_config_examples_4_4 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_board.h - */ - -/** - * \page asfdoc_udi_hid_kbd_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42340B12/2015Fixed typos
42340A12/2014Initial release
- */ \ No newline at end of file diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/module_config/conf_usb.h b/atmel-samd/asf/common/services/usb/class/hid/device/mouse/module_config/conf_usb.h deleted file mode 100644 index 82549337a5ff8..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/module_config/conf_usb.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief USB configuration file - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_USB_H_ -#define _CONF_USB_H_ - -#include "compiler.h" - -#warning You must refill the following definitions with a correct values - -/** - * USB Device Configuration - * @{ - */ - -//! Device definition (mandatory) -#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL -#define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_ASF_HIDMOUSE -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" -// #define USB_DEVICE_PRODUCT_NAME "Product name" -// #define USB_DEVICE_SERIAL_NAME "12...EF" - -/** - * Device speeds support - * @{ - */ -//! To define a Low speed device -//#define USB_DEVICE_LOW_SPEED - -//! To authorize the High speed -#if (UC3A3||UC3A4) -//#define USB_DEVICE_HS_SUPPORT -#endif -//@} - -/** - * USB Device Callbacks definitions (Optional) - * @{ - */ -// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high) -// extern void user_callback_vbus_action(bool b_vbus_high); -// #define UDC_SOF_EVENT() user_callback_sof_action() -// extern void user_callback_sof_action(void); -// #define UDC_SUSPEND_EVENT() user_callback_suspend_action() -// extern void user_callback_suspend_action(void); -// #define UDC_RESUME_EVENT() user_callback_resume_action() -// extern void user_callback_resume_action(void); -//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature -// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() -// extern void user_callback_remotewakeup_enable(void); -// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() -// extern void user_callback_remotewakeup_disable(void); -//! When a extra string descriptor must be supported -//! other than manufacturer, product and serial string -// #define UDC_GET_EXTRA_STRING() -//@} - -//@} - - -/** - * USB Interface Configuration - * @{ - */ -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() true -#define UDI_HID_MOUSE_DISABLE_EXT() -// #define UDI_HID_MOUSE_ENABLE_EXT() my_callback_mouse_enable() -// extern bool my_callback_mouse_enable(void); -// #define UDI_HID_MOUSE_DISABLE_EXT() my_callback_mouse_disable() -// extern void my_callback_mouse_disable(void); -//@} -//@} - - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_hid_mouse_conf.h" - -#endif // _CONF_USB_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse.c b/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse.c deleted file mode 100644 index f8db062522f24..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse.c +++ /dev/null @@ -1,360 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) mouse interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udd.h" -#include "udc.h" -#include "udi_hid.h" -#include "udi_hid_mouse.h" -#include - -/** - * \ingroup udi_hid_mouse_group - * \defgroup udi_hid_mouse_group_udc Interface with USB Device Core (UDC) - * - * Structures and functions required by UDC. - * - * @{ - */ -bool udi_hid_mouse_enable(void); -void udi_hid_mouse_disable(void); -bool udi_hid_mouse_setup(void); -uint8_t udi_hid_mouse_getsetting(void); - -//! Global structure which contains standard UDI interface for UDC -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udi_api_t udi_api_hid_mouse = { - .enable = (bool(*)(void))udi_hid_mouse_enable, - .disable = (void (*)(void))udi_hid_mouse_disable, - .setup = (bool(*)(void))udi_hid_mouse_setup, - .getsetting = (uint8_t(*)(void))udi_hid_mouse_getsetting, - .sof_notify = NULL, -}; -//@} - - -/** - * \ingroup udi_hid_mouse_group - * \defgroup udi_hid_mouse_group_internal Implementation of UDI HID Mouse - * - * Class internal implementation - * @{ - */ - -/** - * \name Internal defines and variables to manage HID mouse - */ -//@{ - -//! Size of report for standard HID mouse -#define UDI_HID_MOUSE_REPORT_SIZE 4 -//! To store current rate of HID mouse -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_mouse_rate; -//! To store current protocol of HID mouse -COMPILER_WORD_ALIGNED - static uint8_t udi_hid_mouse_protocol; -//! To signal if a valid report is ready to send -static bool udi_hid_mouse_b_report_valid; -//! Report ready to send -static uint8_t udi_hid_mouse_report[UDI_HID_MOUSE_REPORT_SIZE]; -//! Signal if a report transfer is on going -static bool udi_hid_mouse_report_trans_ongoing; -//! Buffer used to send report -COMPILER_WORD_ALIGNED - static uint8_t - udi_hid_mouse_report_trans[UDI_HID_MOUSE_REPORT_SIZE]; - - -/** - * \brief Callback for set report setup request - * - * \return \c 1 always, because it is not used on mouse interface - */ -static bool udi_hid_mouse_setreport(void); - -//@} - -//! HID report descriptor for standard HID mouse -//*** CircuitPython: added COMPILER_WORD_ALIGNED to ensure descriptor is word aligned. -// Without this, descriptor sent to host was garbled. -// It appears this is necessary but frequently omitted in UDC_DESC_STORAGE declarations -// in ASF code. -// See comments about buffer alignment in asf/common/services/usb/udc/udd.h -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udi_hid_mouse_report_desc_t udi_hid_mouse_report_desc = { - { - 0x05, 0x01, /* Usage Page (Generic Desktop), */ - 0x09, 0x02, /* Usage (Mouse), */ - 0xA1, 0x01, /* Collection (Application), */ - 0x09, 0x01, /* Usage (Pointer), */ - 0xA1, 0x00, /* Collection (Physical), */ - 0x05, 0x09, /* Usage Page (Buttons), */ - 0x19, 0x01, /* Usage Minimum (01), */ - 0x29, 0x03, /* Usage Maximum (03), */ - 0x15, 0x00, /* Logical Minimum (0), */ - 0x25, 0x01, /* Logical Maximum (1), */ - 0x75, 0x01, /* Report Size (1), */ - 0x95, 0x03, /* Report Count (3), */ - 0x81, 0x02, /* Input (Data, Variable, Absolute) */ - 0x75, 0x05, /* Report Size (5), */ - 0x95, 0x01, /* Report Count (1), */ - 0x81, 0x01, /* Input (Constant), */ - 0x05, 0x01, /* Usage Page (Generic Desktop), */ - 0x09, 0x30, /* Usage (X), */ - 0x09, 0x31, /* Usage (Y), */ - 0x09, 0x38, /* Usage (Scroll), */ - 0x15, 0x81, /* Logical Minimum (-127), */ - 0x25, 0x7F, /* Logical Maximum (127), */ - 0x75, 0x08, /* Report Size (8), */ - 0x95, 0x03, /* Report Count (3), */ - 0x81, 0x06, /* Input (Data, Variable, Relative) */ - 0xC0, /* End Collection, */ - 0xC0, /* End Collection */ - } -}; - -/** - * \name Internal routines - */ -//@{ - -/** - * \brief Moves an axe - * - * \param pos Signed value to move - * \param index_report Index of report to move - * (3=scroll wheel, 2=axe Y, 1=axe X)) - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -static bool udi_hid_mouse_move(int8_t pos, uint8_t index_report); - -/** - * \brief Changes a button state - * - * \param b_state New button state - * \param btn Index of button to change (4=middle, 2=right, 1=left) - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -static bool udi_hid_mouse_btn(bool b_state, uint8_t btn); - -/** - * \brief Send the report - * - * \return \c 1 if send on going, \c 0 if delay. - */ -static bool udi_hid_mouse_send_report(void); - -/** - * \brief Callback called when the report is sent - * - * \param status UDD_EP_TRANSFER_OK, if transfer finish - * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted - * \param nb_sent number of data transfered - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -static void udi_hid_mouse_report_sent(udd_ep_status_t status, - iram_size_t nb_sent, udd_ep_id_t ep); - -//@} - - -//-------------------------------------------- -//------ Interface for UDI HID level - -bool udi_hid_mouse_enable(void) -{ - // Initialize internal value - udi_hid_mouse_rate = 0; - udi_hid_mouse_protocol = 0; - udi_hid_mouse_report_trans_ongoing = false; - memset(udi_hid_mouse_report, 0, UDI_HID_MOUSE_REPORT_SIZE); - udi_hid_mouse_b_report_valid = false; - return UDI_HID_MOUSE_ENABLE_EXT(); -} - - -void udi_hid_mouse_disable(void) -{ - UDI_HID_MOUSE_DISABLE_EXT(); -} - - -bool udi_hid_mouse_setup(void) -{ - return udi_hid_setup(&udi_hid_mouse_rate, - &udi_hid_mouse_protocol, - (uint8_t *) &udi_hid_mouse_report_desc, - udi_hid_mouse_setreport); -} - - -uint8_t udi_hid_mouse_getsetting(void) -{ - return 0; -} - - -static bool udi_hid_mouse_setreport(void) -{ - return false; -} - - -//-------------------------------------------- -//------ Interface for application - -bool udi_hid_mouse_moveScroll(int8_t pos) -{ - return udi_hid_mouse_move(pos, 3); -} - -bool udi_hid_mouse_moveY(int8_t pos_y) -{ - return udi_hid_mouse_move(pos_y, 2); -} - -bool udi_hid_mouse_moveX(int8_t pos_x) -{ - return udi_hid_mouse_move(pos_x, 1); -} - -bool udi_hid_mouse_btnmiddle(bool b_state) -{ - return udi_hid_mouse_btn(b_state, 0x04); -} - -bool udi_hid_mouse_btnright(bool b_state) -{ - return udi_hid_mouse_btn(b_state, 0x02); -} - -bool udi_hid_mouse_btnleft(bool b_state) -{ - return udi_hid_mouse_btn(b_state, 0x01); -} - - -//-------------------------------------------- -//------ Internal routines - -static bool udi_hid_mouse_move(int8_t pos, uint8_t index_report) -{ - int16_t s16_newpos; - - irqflags_t flags = cpu_irq_save(); - - // Add position in HID mouse report - s16_newpos = (int8_t) udi_hid_mouse_report[index_report]; - s16_newpos += pos; - if ((-127 > s16_newpos) || (127 < s16_newpos)) { - cpu_irq_restore(flags); - return false; // Overflow of report - } - udi_hid_mouse_report[index_report] = (uint8_t) s16_newpos; - - // Valid and send report - udi_hid_mouse_b_report_valid = true; - udi_hid_mouse_send_report(); - - cpu_irq_restore(flags); - return true; -} - - -static bool udi_hid_mouse_btn(bool b_state, uint8_t btn) -{ - // Modify buttons report - if (HID_MOUSE_BTN_DOWN == b_state) - udi_hid_mouse_report[0] |= btn; - else - udi_hid_mouse_report[0] &= ~(unsigned)btn; - // Use mouse move routine - return udi_hid_mouse_move(0, 1); -} - - -static bool udi_hid_mouse_send_report(void) -{ - if (udi_hid_mouse_report_trans_ongoing) - return false; // Transfer on going then send this one after transfer complete - - // Copy report on other array used only for transfer - memcpy(udi_hid_mouse_report_trans, udi_hid_mouse_report, - UDI_HID_MOUSE_REPORT_SIZE); - memset(&udi_hid_mouse_report[1], 0, 3); // Keep status of btn for next report - udi_hid_mouse_b_report_valid = false; - - // Send report - udi_hid_mouse_report_trans_ongoing = - udd_ep_run( UDI_HID_MOUSE_EP_IN, - false, - udi_hid_mouse_report_trans, - UDI_HID_MOUSE_REPORT_SIZE, - udi_hid_mouse_report_sent); - return udi_hid_mouse_report_trans_ongoing; -} - - -static void udi_hid_mouse_report_sent(udd_ep_status_t status, - iram_size_t nb_sent, udd_ep_id_t ep) -{ - UNUSED(ep); - UNUSED(status); - UNUSED(nb_sent); - // Valid report sending - udi_hid_mouse_report_trans_ongoing = false; - if (udi_hid_mouse_b_report_valid) { - // Send new valid report - udi_hid_mouse_send_report(); - } -} - -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse.h b/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse.h deleted file mode 100644 index 75b966f6e1765..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse.h +++ /dev/null @@ -1,407 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) mouse interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_HID_MOUSE_H_ -#define _UDI_HID_MOUSE_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_hid.h" -#include "udc_desc.h" -#include "udi.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup udi_hid_mouse_group_udc - * @{ - */ -//! Global structure which contains standard UDI API for UDC -extern UDC_DESC_STORAGE udi_api_t udi_api_hid_mouse; -//@} - -/** - * \ingroup udi_hid_mouse_group - * \defgroup udi_hid_mouse_group_desc USB interface descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - */ -//@{ - -//! Interface descriptor structure for HID mouse -typedef struct { - usb_iface_desc_t iface; - usb_hid_descriptor_t hid; - usb_ep_desc_t ep; -} udi_hid_mouse_desc_t; - -//! Report descriptor for HID mouse -typedef struct { - uint8_t array[25 * 2 + 2 * 1]; -} udi_hid_mouse_report_desc_t; - - -//! By default no string associated to this interface -#ifndef UDI_HID_MOUSE_STRING_ID -#define UDI_HID_MOUSE_STRING_ID 0 -#endif - -//! HID mouse endpoints size -#define UDI_HID_MOUSE_EP_SIZE 8 - -//! Content of HID mouse interface descriptor for all speed -#define UDI_HID_MOUSE_DESC {\ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_HID_MOUSE_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 1,\ - .iface.bInterfaceClass = HID_CLASS,\ - .iface.bInterfaceSubClass = HID_SUB_CLASS_BOOT,\ - .iface.bInterfaceProtocol = HID_PROTOCOL_MOUSE,\ - .iface.iInterface = UDI_HID_MOUSE_STRING_ID,\ - .hid.bLength = sizeof(usb_hid_descriptor_t),\ - .hid.bDescriptorType = USB_DT_HID,\ - .hid.bcdHID = LE16(USB_HID_BDC_V1_11),\ - .hid.bCountryCode = USB_HID_NO_COUNTRY_CODE,\ - .hid.bNumDescriptors = USB_HID_NUM_DESC,\ - .hid.bRDescriptorType = USB_DT_HID_REPORT,\ - .hid.wDescriptorLength = LE16(sizeof(udi_hid_mouse_report_desc_t)),\ - .ep.bLength = sizeof(usb_ep_desc_t),\ - .ep.bDescriptorType = USB_DT_ENDPOINT,\ - .ep.bEndpointAddress = UDI_HID_MOUSE_EP_IN,\ - .ep.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep.wMaxPacketSize = LE16(UDI_HID_MOUSE_EP_SIZE),\ - .ep.bInterval = 10,\ - } -//@} -//@} - - -/** - * \ingroup udi_hid_group - * \defgroup udi_hid_mouse_group USB Device Interface (UDI) for Human Interface Device (HID) Mouse Class - * - * Common APIs used by high level application to use this USB class. - * - * See \ref udi_hid_mouse_quickstart. - * @{ - */ - -/** - * \name Interfaces for mouse events - */ -//@{ - -/** - * \brief Move the scroll wheel - * - * \param pos Signed value to move - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_moveScroll(int8_t pos); - -/** - * \brief Move the mouse pointer on Y axe - * - * \param pos_y Signed value to move - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_moveY(int8_t pos_y); - -/** - * \brief Move the mouse pointer on X axe - * - * \param pos_x Signed value to move - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_moveX(int8_t pos_x); -//@} - -/** - * \name Interfaces for buttons events - */ -//@{ - -//! Value to signal a button down (pressed) -#define HID_MOUSE_BTN_DOWN true -//! Value to signal a button up (released) -#define HID_MOUSE_BTN_UP false - -/** - * \brief Changes middle button state - * - * \param b_state New button state - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_btnmiddle(bool b_state); - -/** - * \brief Changes right button state - * - * \param b_state New button state - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_btnright(bool b_state); - -/** - * \brief Changes left button state - * - * \param b_state New button state - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_btnleft(bool b_state); -//@} - -//@} - -#ifdef __cplusplus -} -#endif - -/** - * \page udi_hid_mouse_quickstart Quick start guide for USB device mouse module (UDI mouse) - * - * This is the quick start guide for the \ref udi_hid_mouse_group - * "USB device mouse module (UDI mouse)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * Also, you can refer to application note - * - * AVR4903: ASF - USB Device HID Mouse Application. - * - * \section udi_hid_mouse_basic_use_case Basic use case - * In this basic use case, the "USB HID Mouse (Single Interface Device)" module is used. - * The "USB HID Mouse (Composite Device)" module usage is described in \ref udi_hid_mouse_use_cases - * "Advanced use cases". - * - * \section udi_hid_mouse_basic_use_case_setup Setup steps - * \subsection udi_hid_mouse_basic_use_case_setup_prereq Prerequisites - * \copydetails udc_basic_use_case_setup_prereq - * \subsection udi_hid_mouse_basic_use_case_setup_code Example code - * \copydetails udc_basic_use_case_setup_code - * \subsection udi_hid_mouse_basic_use_case_setup_flow Workflow - * \copydetails udc_basic_use_case_setup_flow - * - * \section udi_hid_mouse_basic_use_case_usage Usage steps - * - * \subsection udi_hid_mouse_basic_use_case_usage_code Example code - * Content of conf_usb.h: - * \code - #define UDI_HID_MOUSE_ENABLE_EXT() my_callback_mouse_enable() - extern bool my_callback_mouse_enable(void); - #define UDI_HID_MOUSE_DISABLE_EXT() my_callback_mouse_disable() - extern void my_callback_mouse_disable(void); - #include "udi_hid_mouse_conf.h" // At the end of conf_usb.h file -\endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_mouse_events = false; - bool my_callback_mouse_enable(void) - { - my_flag_autorize_mouse_events = true; - return true; - } - void my_callback_mouse_disable(void) - { - my_flag_autorize_mouse_events = false; - } - - void my_button_press_event(void) - { - if (!my_flag_autorize_mouse_events) { - return; - } - udi_hid_mouse_btnleft(HID_MOUSE_BTN_DOWN); - } -\endcode - * - * \subsection udi_hid_mouse_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration - * which is the USB device mouse configuration: - * - \code #define UDI_HID_MOUSE_ENABLE_EXT() my_callback_mouse_enable() - extern bool my_callback_mouse_enable(void); \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB mouse interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_HID_MOUSE_ENABLE_EXT() callback function is called and return true. - * Thus, it is recommended to enable sensors used by the mouse in this function. - * - \code #define UDI_HID_MOUSE_DISABLE_EXT() my_callback_mouse_disable() - extern void my_callback_mouse_disable(void); \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_HID_MOUSE_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable sensors used by the mouse - * in this function. - * -# send mouse events: - * - \code // Sends a value at scroll wheel - udi_hid_mouse_moveScroll(int8_t pos); - // Sends an Y axis value at mouse pointer - udi_hid_mouse_moveY(int8_t pos_y); - // Sends an X axis value at mouse pointer - udi_hid_mouse_moveX(int8_t pos_x); - // Sends a middle click event - udi_hid_mouse_btnmiddle(bool b_state); - // Sends a right click event - udi_hid_mouse_btnright(bool b_state); - // Sends a left click event - udi_hid_mouse_btnleft(bool b_state); \endcode - * - * \section udi_hid_mouse_use_cases Advanced use cases - * For more advanced use of the UDI HID mouse module, see the following use cases: - * - \subpage udi_hid_mouse_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - */ - -/** - * \page udi_hid_mouse_use_case_composite HID mouse in a composite device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB HID Mouse (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB MSC (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_hid_mouse_use_case_composite_setup Setup steps - * For the setup code of this use case to work, the - * \ref udi_hid_mouse_basic_use_case "basic use case" must be followed. - * - * \section udi_hid_mouse_use_case_composite_usage Usage steps - * - * \subsection udi_hid_mouse_use_case_composite_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+1) - - #define UDI_HID_MOUSE_EP_IN (X | USB_EP_DIR_IN) - #define UDI_HID_MOUSE_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_hid_mouse, \ - ... -\endcode - * - * \subsection udi_hid_mouse_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * - \code // Endpoint control size, This must be: - // - 8 for low speed - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for HID mouse. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 1 for HID mouse. - #define USB_DEVICE_MAX_EP (X+1) \endcode - * -# Ensure that conf_usb.h contains the description of - * composite device: - * - \code // The endpoint number chosen by you for the mouse. - // The endpoint number starting from 1. - #define UDI_HID_MOUSE_EP_IN (X | USB_EP_DIR_IN) - // The interface index of an interface starting from 0 - #define UDI_HID_MOUSE_IFACE_NUMBER X \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * - \code // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_hid_mouse_desc_t udi_hid_mouse; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_hid_mouse, \ - ... \endcode - * - \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -#endif // _UDI_HID_MOUSE_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_conf.h b/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_conf.h deleted file mode 100644 index 58006c585c1eb..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_conf.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \file - * - * \brief Default HID mouse configuration for a USB Device - * with a single interface HID mouse - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_HID_MOUSE_CONF_H_ -#define _UDI_HID_MOUSE_CONF_H_ - -/** - * \addtogroup udi_hid_mouse_group_single_desc - * @{ - */ - -//! Control endpoint size -#ifdef USB_DEVICE_HS_SUPPORT -# define USB_DEVICE_EP_CTRL_SIZE 64 -#else -# define USB_DEVICE_EP_CTRL_SIZE 8 -#endif - - -//! Endpoint number used by HID mouse interface -#define UDI_HID_MOUSE_EP_IN (1 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 0 - - -/** - * \name UDD Configuration - */ -//@{ -#undef USB_DEVICE_MAX_EP // undefine this definition in header file -//! 1 endpoint used by HID mouse standard interface -#define USB_DEVICE_MAX_EP 1 -//@} - -//@} - -#include "udi_hid_mouse.h" - -#endif // _UDI_HID_MOUSE_CONF_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_desc.c b/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_desc.c deleted file mode 100644 index 4610726967f19..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_desc.c +++ /dev/null @@ -1,193 +0,0 @@ -/** - * \file - * - * \brief Default descriptors for a USB Device with a single interface HID mouse - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi_hid.h" -#include "udi_hid_mouse.h" - -/** - * \ingroup udi_hid_mouse_group - * \defgroup udi_hid_mouse_group_single_desc USB device descriptors for a single interface - * - * The following structures provide the USB device descriptors required - * for USB Device with a single interface HID mouse. - * - * It is ready to use and do not require more definition. - * - * @{ - */ - -//! Only one interface for this device -#define USB_DEVICE_NB_INTERFACE 1 - -#ifdef USB_DEVICE_LPM_SUPPORT -# define USB_VERSION USB_V2_1 -#else -# define USB_VERSION USB_V2_0 -#endif - -//! USB Device Descriptor -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = { - .bLength = sizeof(usb_dev_desc_t), - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = LE16(USB_VERSION), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .idVendor = LE16(USB_DEVICE_VENDOR_ID), - .idProduct = LE16(USB_DEVICE_PRODUCT_ID), - .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8) - | USB_DEVICE_MINOR_VERSION), -#ifdef USB_DEVICE_MANUFACTURE_NAME - .iManufacturer = 1, -#else - .iManufacturer = 0, // No manufacture string -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - .iProduct = 2, -#else - .iProduct = 0, // No product string -#endif -#ifdef USB_DEVICE_SERIAL_NAME - .iSerialNumber = 3, -#else - .iSerialNumber = 0, // No serial string -#endif - .bNumConfigurations = 1 -}; - - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Qualifier Descriptor for HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = { - .bLength = sizeof(usb_dev_qual_desc_t), - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = LE16(USB_VERSION), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .bNumConfigurations = 1 -}; -#endif - -#ifdef USB_DEVICE_LPM_SUPPORT -//! USB Device Qualifier Descriptor -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE usb_dev_lpm_desc_t udc_device_lpm = { - .bos.bLength = sizeof(usb_dev_bos_desc_t), - .bos.bDescriptorType = USB_DT_BOS, - .bos.wTotalLength = LE16(sizeof(usb_dev_bos_desc_t) + sizeof(usb_dev_capa_ext_desc_t)), - .bos.bNumDeviceCaps = 1, - .capa_ext.bLength = sizeof(usb_dev_capa_ext_desc_t), - .capa_ext.bDescriptorType = USB_DT_DEVICE_CAPABILITY, - .capa_ext.bDevCapabilityType = USB_DC_USB20_EXTENSION, - .capa_ext.bmAttributes = USB_DC_EXT_LPM, -}; -#endif - -//! Structure for USB Device Configuration Descriptor -COMPILER_PACK_SET(1) -typedef struct { - usb_conf_desc_t conf; - udi_hid_mouse_desc_t hid_mouse; -} udc_desc_t; -COMPILER_PACK_RESET() - -//! USB Device Configuration Descriptor filled for FS and HS -COMPILER_WORD_ALIGNED -UDC_DESC_STORAGE udc_desc_t udc_desc = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), - .hid_mouse = UDI_HID_MOUSE_DESC, -}; - - -/** - * \name UDC structures which contains all USB Device definitions - */ -//@{ - -//! Associate an UDI for each USB interface -UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = { - &udi_api_hid_mouse, -}; - -//! Add UDI with USB Descriptors FS & HS -UDC_DESC_STORAGE udc_config_speed_t udc_config_fshs[1] = { { - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc, - .udi_apis = udi_apis, -}}; - -//! Add all information about USB Device in global structure for UDC -UDC_DESC_STORAGE udc_config_t udc_config = { - .confdev_lsfs = &udc_device_desc, - .conf_lsfs = udc_config_fshs, -#ifdef USB_DEVICE_HS_SUPPORT - .confdev_hs = &udc_device_desc, - .qualifier = &udc_device_qual, - .conf_hs = udc_config_fshs, -#endif -#ifdef USB_DEVICE_LPM_SUPPORT - .conf_bos = &udc_device_lpm.bos, -#else - .conf_bos = NULL, -#endif -}; - -//@} -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_doc.h b/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_doc.h deleted file mode 100644 index 41e805f46f886..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/mouse/udi_hid_mouse_doc.h +++ /dev/null @@ -1,497 +0,0 @@ -/** - * \file - * - * \brief USB device driver for Human Interface Device (HID) mouse interface. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup asfdoc_udi_hid_mouse_group USB Device Interface (UDI) for Human Interface Device Mouse (HID Mouse) - * - * USB Device Interface (UDI) for Human Interface Device Mouse (HID mouse) provides an - * interface for the configuration and management of USB HID mouse device. - * - * The outline of this documentation is as follows: - * - \ref asfdoc_udi_hid_mouse_api_overview - * - \ref asfdoc_udi_hid_mouse_exqsg - * - \ref asfdoc_udi_hid_mouse_config_examples - * - * For more details for Atmel® Software Framework (ASF) USB Device Stack and - * USB Device HID Mouse, refer to following application notes: - * - - * AVR4900: ASF - USB Device Stack - * - - * AVR4903: ASF - USB Device HID Mouse Application - * - - * AVR4920: ASF - USB Device Stack - Compliance and Performance Figures - * - - * AVR4921: ASF - USB Device Stack Differences between ASF V1 and V2 - * - * \section asfdoc_udi_hid_mouse_api_overview API Overview - * @{ - */ - -/** - * \name Interface with USB Device Core (UDC) - * - * Structure required by UDC. - * - * @{ - */ - -/** Global structure which contains standard UDI API for UDC. */ -extern UDC_DESC_STORAGE udi_api_t udi_api_hid_mouse; -/**@}*/ - -/** - * \name USB Interface Descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - * - * @{ - */ - - /** Interface descriptor structure for HID mouse. */ -typedef struct { - /** Standard USB interface descriptor structure */ - usb_iface_desc_t iface; - /** HID Descriptor */ - usb_hid_descriptor_t hid; - /** Standard USB endpoint descriptor structure */ - usb_ep_desc_t ep; -} udi_hid_mouse_desc_t; - -/** Report descriptor for HID mouse. */ -typedef struct { - /** Array to put detailed report data */ - uint8_t array[25 * 2 + 2 * 1]; -} udi_hid_mouse_report_desc_t; - - -/** By default no string associated to this interface. */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UDI_HID_MOUSE_STRING_ID -#define UDI_HID_MOUSE_STRING_ID 0 -#endif - -/** HID mouse endpoints size. */ -#define UDI_HID_MOUSE_EP_SIZE 8 - -/** Content of HID mouse interface descriptor for all speed. */ -#define UDI_HID_MOUSE_DESC {\ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_HID_MOUSE_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 1,\ - .iface.bInterfaceClass = HID_CLASS,\ - .iface.bInterfaceSubClass = HID_SUB_CLASS_BOOT,\ - .iface.bInterfaceProtocol = HID_PROTOCOL_MOUSE,\ - .iface.iInterface = UDI_HID_MOUSE_STRING_ID,\ - .hid.bLength = sizeof(usb_hid_descriptor_t),\ - .hid.bDescriptorType = USB_DT_HID,\ - .hid.bcdHID = LE16(USB_HID_BDC_V1_11),\ - .hid.bCountryCode = USB_HID_NO_COUNTRY_CODE,\ - .hid.bNumDescriptors = USB_HID_NUM_DESC,\ - .hid.bRDescriptorType = USB_DT_HID_REPORT,\ - .hid.wDescriptorLength = LE16(sizeof(udi_hid_mouse_report_desc_t)),\ - .ep.bLength = sizeof(usb_ep_desc_t),\ - .ep.bDescriptorType = USB_DT_ENDPOINT,\ - .ep.bEndpointAddress = UDI_HID_MOUSE_EP_IN,\ - .ep.bmAttributes = USB_EP_TYPE_INTERRUPT,\ - .ep.wMaxPacketSize = LE16(UDI_HID_MOUSE_EP_SIZE),\ - .ep.bInterval = 10,\ - } -/**@}*/ - -/** - * \name Interfaces for Mouse Events - * - * @{ - */ - -/** - * \brief Move the scroll wheel - * - * \param[in] pos Signed value to move - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_moveScroll(int8_t pos); - -/** - * \brief Move the mouse pointer on Y axe - * - * \param[in] pos_y Signed value to move - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_moveY(int8_t pos_y); - -/** - * \brief Move the mouse pointer on X axe - * - * \param[in] pos_x Signed value to move - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_moveX(int8_t pos_x); -/**@}*/ - -/** - * \name Interfaces for Buttons Events - * - * @{ - */ - -/** Value to signal a button down (pressed). */ -#define HID_MOUSE_BTN_DOWN true - -/** Value to signal a button up (released). */ -#define HID_MOUSE_BTN_UP false - -/** - * \brief Changes middle button state - * - * \param[in] b_state New button state - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_btnmiddle(bool b_state); - -/** - * \brief Changes right button state - * - * \param[in] b_state New button state - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_btnright(bool b_state); - -/** - * \brief Changes left button state - * - * \param[in] b_state New button state - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_mouse_btnleft(bool b_state); -/**@}*/ -/**@}*/ - -/** - * \page asfdoc_udi_hid_mouse_exqsg Quick Start Guide for USB Device Mouse Module (UDI Mouse) - * - * This is the quick start guide for the \ref asfdoc_udi_hid_mouse_group - * "USB Device Mouse Module (UDI Mouse)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section udi_hid_mouse_basic_use_case Basic Use Case - * In this basic use case, the "USB HID Mouse (Single Interface Device)" module is used. - * The "USB HID Mouse (Composite Device)" module usage is described in \ref udi_hid_mouse_use_cases - * "Advanced Use Cases". - * - * \section udi_hid_mouse_basic_use_case_setup Setup Steps - * As a USB device, it follows common USB device setup steps. Refer to - * \ref asfdoc_udc_basic_use_case_setup "USB Device Basic Setup". - * - * \section udi_hid_mouse_basic_use_case_usage Usage Steps - * - * \subsection udi_hid_mouse_basic_use_case_usage_code Example Code - * Content of conf_usb.h: - * \code - #define UDI_HID_MOUSE_ENABLE_EXT() my_callback_mouse_enable() - extern bool my_callback_mouse_enable(void); - #define UDI_HID_MOUSE_DISABLE_EXT() my_callback_mouse_disable() - extern void my_callback_mouse_disable(void); - #include "udi_hid_mouse_conf.h" // At the end of conf_usb.h file - \endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_mouse_events = false; - bool my_callback_mouse_enable(void) - { - my_flag_autorize_mouse_events = true; - return true; - } - void my_callback_mouse_disable(void) - { - my_flag_autorize_mouse_events = false; - } - - void my_button_press_event(void) - { - if (!my_flag_autorize_mouse_events) { - return; - } - udi_hid_mouse_btnleft(HID_MOUSE_BTN_DOWN); - } - \endcode - * - * \subsection udi_hid_mouse_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration - * which is the USB device mouse configuration: - * \code - #define UDI_HID_MOUSE_ENABLE_EXT() my_callback_mouse_enable() - extern bool my_callback_mouse_enable(void); - \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB mouse interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_HID_MOUSE_ENABLE_EXT() callback function is called and return true. - * Thus, it is recommended to enable sensors used by the mouse in this function. - * - * \code - #define UDI_HID_MOUSE_DISABLE_EXT() my_callback_mouse_disable() - extern void my_callback_mouse_disable(void); - \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_HID_MOUSE_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable sensors used by the mouse - * in this function. - * - * -# Send mouse events: - * \code - // Sends a value at scroll wheel - udi_hid_mouse_moveScroll(int8_t pos); - // Sends an Y axis value at mouse pointer - udi_hid_mouse_moveY(int8_t pos_y); - // Sends an X axis value at mouse pointer - udi_hid_mouse_moveX(int8_t pos_x); - // Sends a middle click event - udi_hid_mouse_btnmiddle(bool b_state); - // Sends a right click event - udi_hid_mouse_btnright(bool b_state); - // Sends a left click event - udi_hid_mouse_btnleft(bool b_state); - \endcode - * - * \section udi_hid_mouse_use_cases Advanced Use Cases - * \ifnot ASF_MANUAL - * For more advanced use of the UHI HID mouse module, see the following use cases: - * - \subpage udi_hid_mouse_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - * \else - * For multiple interface use of UDI HID module, see the following: - * - \subpage udi_hid_mouse_use_case_composite - * - * For more advanced use of the UDI HID mouse module, see the following: - * - \ref asfdoc_udc_use_cases - * \endif - */ - -/** - * \page udi_hid_mouse_use_case_composite HID Mouse in a Composite Device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB HID Mouse (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB MSC (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_hid_mouse_use_case_composite_setup Setup Steps - * For the setup code of this use case to work, the - * \ref udi_hid_mouse_basic_use_case "Basic Use Case" must be followed. - * - * \section udi_hid_mouse_use_case_composite_usage Usage Steps - * - * \subsection udi_hid_mouse_use_case_composite_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+1) - - #define UDI_HID_MOUSE_EP_IN (X | USB_EP_DIR_IN) - #define UDI_HID_MOUSE_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_hid_mouse, \ - ... - \endcode - * - * - * \subsection udi_hid_mouse_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * \code - // Endpoint control size, This must be: - // - 8 for low speed - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for HID mouse. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 1 for HID mouse. - #define USB_DEVICE_MAX_EP (X+1) - \endcode - - * -# Ensure that conf_usb.h contains the description of - * composite device: - * \code - // The endpoint number chosen by you for the mouse. - // The endpoint number starting from 1. - #define UDI_HID_MOUSE_EP_IN (X | USB_EP_DIR_IN) - // The interface index of an interface starting from 0 - #define UDI_HID_MOUSE_IFACE_NUMBER X - \endcode - * - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * \code - // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_hid_mouse_desc_t udi_hid_mouse; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_hid_mouse, \ - ... - \endcode - * \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -/** - * \page asfdoc_udi_hid_mouse_config_examples Configuration File Examples - * - * \section asfdoc_udi_hid_mouse_config_examples_1 conf_usb.h - * \subsection asfdoc_udi_hid_mouse_config_examples_1_1 UDI HID MOUSE Single - * \include module_config/conf_usb.h - * \subsection asfdoc_udi_hid_mouse_config_examples_1_2 UDI HID MOUSE Multiple (Composite) - * \include composite/device/module_config/conf_usb.h - * - * \section asfdoc_udi_hid_mouse_config_examples_2 conf_clock.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_2_1 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_clock.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_2_2 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_clock.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_2_3 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_clock.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_2_4 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_clock.h - * - * \section asfdoc_udi_hid_mouse_config_examples_3 conf_clocks.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_3_1 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_clocks.h - * - * \section asfdoc_udi_hid_mouse_config_examples_4 conf_board.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_4_1 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_board.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_4_2 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_board.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_4_3 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_board.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_4_4 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_board.h - * - * \subsection asfdoc_udi_hid_mouse_config_examples_4_5 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_board.h - */ - -/** - * \page asfdoc_udi_hid_mouse_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42341B12/2015Fixed typos
42341A12/2014Initial release
- */ \ No newline at end of file diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/udi_hid.c b/atmel-samd/asf/common/services/usb/class/hid/device/udi_hid.c deleted file mode 100644 index 3694b0f0173b8..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/udi_hid.c +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udd.h" -#include "udc.h" -#include "udi_hid.h" - - -/** - * \ingroup udi_hid_group - * \defgroup udi_hid_group_internal Implementation of HID common library - * @{ - */ - -/** - * \brief Send the specific descriptors requested by SETUP request - * - * \retval true if the descriptor is supported - */ -static bool udi_hid_reqstdifaceget_descriptor(uint8_t *report_desc); - -bool udi_hid_setup( uint8_t *rate, uint8_t *protocol, uint8_t *report_desc, bool (*setup_report)(void) ) -{ - if (Udd_setup_is_in()) { - // Requests Interface GET - if (Udd_setup_type() == USB_REQ_TYPE_STANDARD) { - // Requests Standard Interface Get - switch (udd_g_ctrlreq.req.bRequest) { - - case USB_REQ_GET_DESCRIPTOR: - return udi_hid_reqstdifaceget_descriptor(report_desc); - } - } - if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { - // Requests Class Interface Get - switch (udd_g_ctrlreq.req.bRequest) { - - case USB_REQ_HID_GET_REPORT: - return setup_report(); - - case USB_REQ_HID_GET_IDLE: - udd_g_ctrlreq.payload = rate; - udd_g_ctrlreq.payload_size = 1; - return true; - - case USB_REQ_HID_GET_PROTOCOL: - udd_g_ctrlreq.payload = protocol; - udd_g_ctrlreq.payload_size = 1; - return true; - } - } - } - if (Udd_setup_is_out()) { - // Requests Interface SET - if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { - // Requests Class Interface Set - switch (udd_g_ctrlreq.req.bRequest) { - - case USB_REQ_HID_SET_REPORT: - return setup_report(); - - case USB_REQ_HID_SET_IDLE: - *rate = udd_g_ctrlreq.req.wValue >> 8; - return true; - - case USB_REQ_HID_SET_PROTOCOL: - if (0 != udd_g_ctrlreq.req.wLength) - return false; - *protocol = udd_g_ctrlreq.req.wValue; - return true; - } - } - } - return false; // Request not supported -} - - -//--------------------------------------------- -//------- Internal routines - -static bool udi_hid_reqstdifaceget_descriptor(uint8_t *report_desc) -{ - usb_hid_descriptor_t UDC_DESC_STORAGE *ptr_hid_desc; - - // Get the USB descriptor which is located after the interface descriptor - // This descriptor must be the HID descriptor - ptr_hid_desc = (usb_hid_descriptor_t UDC_DESC_STORAGE *) ((uint8_t *) - udc_get_interface_desc() + sizeof(usb_iface_desc_t)); - if (USB_DT_HID != ptr_hid_desc->bDescriptorType) - return false; - - // The SETUP request can ask for: - // - an USB_DT_HID descriptor - // - or USB_DT_HID_REPORT descriptor - // - or USB_DT_HID_PHYSICAL descriptor - if (USB_DT_HID == (uint8_t) (udd_g_ctrlreq.req.wValue >> 8)) { - // USB_DT_HID descriptor requested then send it - udd_g_ctrlreq.payload = (uint8_t *) ptr_hid_desc; - udd_g_ctrlreq.payload_size = - min(udd_g_ctrlreq.req.wLength, - ptr_hid_desc->bLength); - return true; - } - // The HID_X descriptor requested must correspond to report type - // included in the HID descriptor - if (ptr_hid_desc->bRDescriptorType == - (uint8_t) (udd_g_ctrlreq.req.wValue >> 8)) { - // Send HID Report descriptor given by high level - udd_g_ctrlreq.payload = report_desc; - udd_g_ctrlreq.payload_size = - min(udd_g_ctrlreq.req.wLength, - le16_to_cpu(ptr_hid_desc->wDescriptorLength)); - return true; - } - return false; -} - -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/device/udi_hid.h b/atmel-samd/asf/common/services/usb/class/hid/device/udi_hid.h deleted file mode 100644 index 0edb09c1c3d3b..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/device/udi_hid.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file - * - * \brief USB Device Human Interface Device (HID) interface definitions. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_HID_H_ -#define _UDI_HID_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_hid.h" -#include "udd.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup udi_group - * \defgroup udi_hid_group USB Device Interface (UDI) for Human Interface Device (HID) - * - * Common library for all Human Interface Device (HID) implementation. - * - * @{ - */ - -/** - * \brief Decode HID setup request - * - * \param rate Pointer on rate of current HID interface - * \param protocol Pointer on protocol of current HID interface - * \param report_desc Pointer on report descriptor of current HID interface - * \param set_report Pointer on set_report callback of current HID interface - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_hid_setup( uint8_t *rate, uint8_t *protocol, uint8_t *report_desc, bool (*setup_report)(void) ); - -//@} - -#ifdef __cplusplus -} -#endif -#endif // _UDI_HID_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/module_config/conf_usb_host.h b/atmel-samd/asf/common/services/usb/class/hid/host/mouse/module_config/conf_usb_host.h deleted file mode 100644 index 030ee12cd993d..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/module_config/conf_usb_host.h +++ /dev/null @@ -1,132 +0,0 @@ -/** - * \file - * - * \brief USB host configuration file - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_USB_HOST_H_ -#define _CONF_USB_HOST_H_ - -#include "compiler.h" - -/** - * USB Host Configuration - * @{ - */ - -//! Array of UHI APIs Define the list of UHI supported by USB host. -#define USB_HOST_UHI UHI_HID_MOUSE - -//! Maximum current allowed on Vbus (mA) -#define USB_HOST_POWER_MAX 500 - -//! Authorize the USB HUB support -// #define USB_HOST_HUB_SUPPORT - -//! Authorize the USB host to run in High Speed -#if (UC3A3 || UC3A4) -# define USB_HOST_HS_SUPPORT -#endif - -/** - * USB Host callbacks - * @{ - */ - -//! To notify that the USB mode are switched automatically. -//! This is possible only when ID pin is available. -//#define UHC_MODE_CHANGE(b_host_mode) usb_host_mode_change(b_host_mode) - -//! To notify that the Vbus level has changed -//! Available only in USB hardware with Vbus monitoring. -//#define UHC_VBUS_CHANGE(b_present) usb_host_vbus_change(b_present) - -//! To notify that a Vbus error has occurred -//! Available only in USB hardware with Vbus monitoring. -//#define UHC_VBUS_ERROR() usb_host_vbus_error() - -//! To notify that a device has been connected or disconnected. -//#define UHC_CONNECTION_EVENT(dev,b_present) usb_host_connection_event(dev,b_present) - -//! Called when a USB device or the host have wake up the USB line. -//#define UHC_WAKEUP_EVENT() usb_host_wakeup_event() - -//! Called for each received SOF each 1 ms -//! Note: Available in High and Full speed mode -//#define UHC_SOF_EVENT() usb_host_sof_event() - -//! Called when a USB device configuration must be chosen. -//! Thus, the application can choose either a configuration number for this device -//! or a configuration number 0 to reject it. -//! If callback not defined the configuration 1 is chosen. -//#define UHC_DEVICE_CONF(dev) uint8_t usb_host_device_conf(dev) - -//! Called when a USB device enumeration is completed. -//#define UHC_ENUM_EVENT(dev,b_status) usb_host_enum_event(dev,b_status) - - -//@} - - - -/** - * USB Interface Configuration - * @{ - */ -/** - * Configuration of HID Mouse interface - * @{ - */ -#define UHI_HID_MOUSE_CHANGE(dev,b_plug) -#define UHI_HID_MOUSE_EVENT_BTN_LEFT(b_state) -#define UHI_HID_MOUSE_EVENT_BTN_RIGHT(b_state) -#define UHI_HID_MOUSE_EVENT_BTN_MIDDLE(b_state) -#define UHI_HID_MOUSE_EVENT_MOUVE(x,y,scroll) -//@} -//@} - -//@} - -#include "uhi_hid_mouse.h" - -#endif // _CONF_USB_HOST_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse.c b/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse.c deleted file mode 100644 index 25fbc3f9953d1..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse.c +++ /dev/null @@ -1,268 +0,0 @@ -/** - * \file - * - * \brief USB host Human Interface Device (HID) mouse driver. - * - * Copyright (C) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb_host.h" -#include "usb_protocol.h" -#include "uhd.h" -#include "uhc.h" -#include "uhi_hid_mouse.h" -#include - -#ifdef USB_HOST_HUB_SUPPORT -# error USB HUB support is not implemented on UHI mouse -#endif - -/** - * \ingroup uhi_hid_mouse_group - * \defgroup uhi_hid_mouse_group_internal Implementation of UHI HID Mouse - * - * Class internal implementation - * @{ - */ - -/** - * \name Index in HID report for usual HID mouse events - * @{ - */ -#define UHI_HID_MOUSE_BTN 0 -#define UHI_HID_MOUSE_MOV_X 1 -#define UHI_HID_MOUSE_MOV_Y 2 -#define UHI_HID_MOUSE_MOV_SCROLL 3 -//@} - -/** - * \name Structure to store information about USB Device HID mouse - */ -//@{ -typedef struct { - uhc_device_t *dev; - usb_ep_t ep_in; - uint8_t report_size; - uint8_t *report; - uint8_t report_btn_prev; -}uhi_hid_mouse_dev_t; - -static uhi_hid_mouse_dev_t uhi_hid_mouse_dev = { - .dev = NULL, - .report = NULL, - }; - -//@} - - -/** - * \name Internal routines - */ -//@{ -static void uhi_hid_mouse_start_trans_report(usb_add_t add); -static void uhi_hid_mouse_report_reception( - usb_add_t add, - usb_ep_t ep, - uhd_trans_status_t status, - iram_size_t nb_transfered); -//@} - - -/** - * \name Functions required by UHC - * @{ - */ - -uhc_enum_status_t uhi_hid_mouse_install(uhc_device_t* dev) -{ - bool b_iface_supported; - uint16_t conf_desc_lgt; - usb_iface_desc_t *ptr_iface; - - if (uhi_hid_mouse_dev.dev != NULL) { - return UHC_ENUM_SOFTWARE_LIMIT; // Device already allocated - } - conf_desc_lgt = le16_to_cpu(dev->conf_desc->wTotalLength); - ptr_iface = (usb_iface_desc_t*)dev->conf_desc; - b_iface_supported = false; - while(conf_desc_lgt) { - switch (ptr_iface->bDescriptorType) { - - case USB_DT_INTERFACE: - if ((ptr_iface->bInterfaceClass == HID_CLASS) - && (ptr_iface->bInterfaceProtocol == HID_PROTOCOL_MOUSE) ) { - // USB HID Mouse interface found - // Start allocation endpoint(s) - b_iface_supported = true; - } else { - // Stop allocation endpoint(s) - b_iface_supported = false; - } - break; - - case USB_DT_ENDPOINT: - // Allocation of the endpoint - if (!b_iface_supported) { - break; - } - if (!uhd_ep_alloc(dev->address, (usb_ep_desc_t*)ptr_iface)) { - return UHC_ENUM_HARDWARE_LIMIT; // Endpoint allocation fail - } - Assert(((usb_ep_desc_t*)ptr_iface)->bEndpointAddress & USB_EP_DIR_IN); - uhi_hid_mouse_dev.ep_in = ((usb_ep_desc_t*)ptr_iface)->bEndpointAddress; - uhi_hid_mouse_dev.report_size = - le16_to_cpu(((usb_ep_desc_t*)ptr_iface)->wMaxPacketSize); - uhi_hid_mouse_dev.report = malloc(uhi_hid_mouse_dev.report_size); - if (uhi_hid_mouse_dev.report == NULL) { - Assert(false); - return UHC_ENUM_MEMORY_LIMIT; // Internal RAM allocation fail - } - uhi_hid_mouse_dev.dev = dev; - // All endpoints of all interfaces supported allocated - return UHC_ENUM_SUCCESS; - - default: - // Ignore descriptor - break; - } - Assert(conf_desc_lgt>=ptr_iface->bLength); - conf_desc_lgt -= ptr_iface->bLength; - ptr_iface = (usb_iface_desc_t*)((uint8_t*)ptr_iface + ptr_iface->bLength); - } - return UHC_ENUM_UNSUPPORTED; // No interface supported -} - -void uhi_hid_mouse_enable(uhc_device_t* dev) -{ - if (uhi_hid_mouse_dev.dev != dev) { - return; // No interface to enable - } - - // Init value - uhi_hid_mouse_dev.report_btn_prev = 0; - uhi_hid_mouse_start_trans_report(dev->address); - UHI_HID_MOUSE_CHANGE(dev, true); -} - -void uhi_hid_mouse_uninstall(uhc_device_t* dev) -{ - if (uhi_hid_mouse_dev.dev != dev) { - return; // Device not enabled in this interface - } - uhi_hid_mouse_dev.dev = NULL; - Assert(uhi_hid_mouse_dev.report!=NULL); - free(uhi_hid_mouse_dev.report); - UHI_HID_MOUSE_CHANGE(dev, false); -} -//@} - -/** - * \name Internal routines - */ -//@{ - -/** - * \brief Starts the reception of the HID mouse report - * - * \param add USB address to use - */ -static void uhi_hid_mouse_start_trans_report(usb_add_t add) -{ - // Start transfer on interrupt endpoint IN - uhd_ep_run(add, uhi_hid_mouse_dev.ep_in, true, uhi_hid_mouse_dev.report, - uhi_hid_mouse_dev.report_size, 0, uhi_hid_mouse_report_reception); -} - -/** - * \brief Decodes the HID mouse report received - * - * \param add USB address used by the transfer - * \param status Transfer status - * \param nb_transfered Number of data transfered - */ -static void uhi_hid_mouse_report_reception( - usb_add_t add, - usb_ep_t ep, - uhd_trans_status_t status, - iram_size_t nb_transfered) -{ - uint8_t state_prev; - uint8_t state_new; - UNUSED(ep); - - if ((status == UHD_TRANS_NOTRESPONDING) || (status == UHD_TRANS_TIMEOUT)) { - uhi_hid_mouse_start_trans_report(add); - return; // HID mouse transfer restart - } - - if ((status != UHD_TRANS_NOERROR) || (nb_transfered < 4)) { - return; // HID mouse transfer aborted - } - - // Decode buttons - state_prev = uhi_hid_mouse_dev.report_btn_prev; - state_new = uhi_hid_mouse_dev.report[UHI_HID_MOUSE_BTN]; - if ((state_prev & 0x01) != (state_new & 0x01)) { - UHI_HID_MOUSE_EVENT_BTN_LEFT((state_new & 0x01) ? true : false); - } - if ((state_prev & 0x02) != (state_new & 0x02)) { - UHI_HID_MOUSE_EVENT_BTN_RIGHT((state_new & 0x02) ? true : false); - } - if ((state_prev & 0x04) != (state_new & 0x04)) { - UHI_HID_MOUSE_EVENT_BTN_MIDDLE((state_new & 0x04) ? true : false); - } - uhi_hid_mouse_dev.report_btn_prev = state_new; - - // Decode moves - if ((uhi_hid_mouse_dev.report[UHI_HID_MOUSE_MOV_X] != 0) - || (uhi_hid_mouse_dev.report[UHI_HID_MOUSE_MOV_Y] != 0) - || (uhi_hid_mouse_dev.report[UHI_HID_MOUSE_MOV_SCROLL] != 0)) { - UHI_HID_MOUSE_EVENT_MOUVE( - (int8_t)uhi_hid_mouse_dev.report[UHI_HID_MOUSE_MOV_X], - (int8_t)uhi_hid_mouse_dev.report[UHI_HID_MOUSE_MOV_Y], - (int8_t)uhi_hid_mouse_dev.report[UHI_HID_MOUSE_MOV_SCROLL]); - } - - uhi_hid_mouse_start_trans_report(add); -} -//@} - -//@} diff --git a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse.h b/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse.h deleted file mode 100644 index a30ca5c40a90d..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse.h +++ /dev/null @@ -1,216 +0,0 @@ -/** - * \file - * - * \brief USB host driver for Human Interface Device (HID) mouse interface. - * - * Copyright (C) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UHI_HID_MOUSE_H_ -#define _UHI_HID_MOUSE_H_ - -#include "conf_usb_host.h" -#include "usb_protocol.h" -#include "usb_protocol_hid.h" -#include "uhi.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup uhi_hid_mouse_group - * \defgroup uhi_hid_mouse_group_uhc Interface with USB Host Core (UHC) - * - * Define and functions required by UHC. - * - * @{ - */ - -//! Global define which contains standard UHI API for UHC -//! It must be added in USB_HOST_UHI define from conf_usb_host.h file. -#define UHI_HID_MOUSE { \ - .install = uhi_hid_mouse_install, \ - .enable = uhi_hid_mouse_enable, \ - .uninstall = uhi_hid_mouse_uninstall, \ - .sof_notify = NULL, \ -} - -/** - * \name Functions required by UHC - * @{ - */ -extern uhc_enum_status_t uhi_hid_mouse_install(uhc_device_t* dev); -extern void uhi_hid_mouse_enable(uhc_device_t* dev); -extern void uhi_hid_mouse_uninstall(uhc_device_t* dev); -//@} -//@} - -/** - * \ingroup uhi_group - * \defgroup uhi_hid_mouse_group UHI for Human Interface Device Mouse Class - * - * Common APIs used by high level application to use this USB host class. - * - * This API requires only callback definitions in conf_usb_host.h file - * through following defines: - * - \code #define UHI_HID_MOUSE_CHANGE(dev,b_plug) - #define UHI_HID_MOUSE_EVENT_BTN_LEFT(b_state) - #define UHI_HID_MOUSE_EVENT_BTN_RIGHT(b_state) - #define UHI_HID_MOUSE_EVENT_BTN_MIDDLE(b_state) - #define UHI_HID_MOUSE_EVENT_MOUVE(x,y,scroll) \endcode - * - * See \ref uhi_hid_mouse_quickstart. - * @{ - */ -//@} - - -/** - * \page uhi_hid_mouse_quickstart Quick start guide for USB host mouse module (UHI mouse) - * - * This is the quick start guide for the \ref uhi_hid_mouse_group - * "USB host mouse module (UHI mouse)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section uhi_hid_mouse_basic_use_case Basic use case - * In this basic use case, the "USB Host HID Mouse (Single Class support)" module is used. - * The "USB Host HID Mouse (Multiple Classes support)" module usage is described - * in \ref uhi_hid_mouse_use_cases "Advanced use cases". - * - * \section uhi_hid_mouse_basic_use_case_setup Setup steps - * \subsection uhi_hid_mouse_basic_use_case_setup_prereq Prerequisites - * \copydetails uhc_basic_use_case_setup_prereq - * \subsection uhi_hid_mouse_basic_use_case_setup_code Example code - * \copydetails uhc_basic_use_case_setup_code - * \subsection uhi_hid_mouse_basic_use_case_setup_flow Workflow - * \copydetails uhc_basic_use_case_setup_flow - * - * \section uhi_hid_mouse_basic_use_case_usage Usage steps - * - * \subsection uhi_hid_mouse_basic_use_case_usage_code Example code - * Content of conf_usb_host.h: - * \code - #define USB_HOST_UHI UHI_HID_MOUSE - #define UHI_HID_MOUSE_CHANGE(dev, b_plug) my_callback_mouse_change(dev, b_plug) - extern bool my_callback_mouse_change(uhc_device_t* dev, bool b_plug); - #define UHI_HID_MOUSE_EVENT_BTN_LEFT(b_state) my_callback_event_btn_left(b_state) - extern void my_callback_event_btn_left(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_RIGHT(b_state) my_callback_event_btn_right(b_state) - extern void my_callback_event_btn_right(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_MIDDLE(b_state) my_callback_event_btn_middle(b_state) - extern void my_callback_event_btn_middle(bool b_state); - #define UHI_HID_MOUSE_EVENT_MOUVE(x, y, scroll) my_callback_event_mouse(x, y, scroll) - extern void my_callback_event_mouse(int8_t x, int8_t y, int8_t scroll); - #include "uhi_hid_mouse.h" // At the end of conf_usb_host.h file -\endcode - * - * Add to application C-file: - * \code - bool my_callback_mouse_change(uhc_device_t* dev, bool b_plug) - { - if (b_plug) { - my_display_on_mouse_icon(); - } else { - my_display_off_mouse_icon(); - } - } - - void my_callback_event_btn_left(bool b_state) - { - if (b_state) { - // Here mouse button left pressed - } else { - // Here mouse button left released - } - } - - void my_callback_event_mouse(int8_t x, int8_t y, int8_t scroll) - { - if (!x) { - // Here mouse are moved on axe X - cursor_x += x; - } - if (!y) { - // Here mouse are moved on axe Y - cursor_y += y; - } - if (!scroll) { - // Here mouse are moved the wheel - wheel += scroll; - } - } -\endcode - * - * \subsection uhi_hid_mouse_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb_host.h is available and contains the following configuration - * which is the USB host mouse configuration: - * - \code #define USB_HOST_UHI UHI_HID_MOUSE \endcode - * \note It defines the list of UHI supported by USB host. - * - \code #define UHI_HID_MOUSE_CHANGE(dev, b_plug) my_callback_mouse_change(dev, b_plug) - extern bool my_callback_mouse_change(uhc_device_t* dev, bool b_plug); \endcode - * \note This callback is called when a USB device mouse is plugged or unplugged. - * - \code #define UHI_HID_MOUSE_EVENT_BTN_LEFT(b_state) my_callback_event_btn_left(b_state) - extern void my_callback_event_btn_left(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_RIGHT(b_state) my_callback_event_btn_right(b_state) - extern void my_callback_event_btn_right(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_MIDDLE(b_state) my_callback_event_btn_middle(b_state) - extern void my_callback_event_btn_middle(bool b_state); - #define UHI_HID_MOUSE_EVENT_MOUVE(x, y, scroll) my_callback_event_mouse(x, y, scroll) - extern void my_callback_event_mouse(int8_t x, int8_t y, int8_t scroll) \endcode - * \note These callbacks are called when a USB device mouse event is received. - * - * \section uhi_hid_mouse_use_cases Advanced use cases - * For more advanced use of the UHI HID mouse module, see the following use cases: - * - \subpage uhc_use_case_1 - * - \subpage uhc_use_case_2 - * - \subpage uhc_use_case_3 - */ - - -#ifdef __cplusplus -} -#endif -#endif // _UHI_HID_MOUSE_H_ diff --git a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse_doc.h b/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse_doc.h deleted file mode 100644 index 2348d7e22d05c..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/host/mouse/uhi_hid_mouse_doc.h +++ /dev/null @@ -1,325 +0,0 @@ -/** - * \file - * - * \brief USB host driver for Human Interface Device (HID) mouse interface. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup asfdoc_uhi_hid_mouse_group USB Host Interface (UHI) for Human Interface Device Mouse (HID Mouse) - * - * USB Host Interface (UHI) for Human Interface Device Mouse (HID Mouse) provides an - * interface for the configuration and management of USB HID mouse host. - * - * The outline of this documentation is as follows: - * - \ref asfdoc_uhi_hid_mouse_api_overview - * - \ref asfdoc_uhi_hid_mouse_exqsg - * - \ref asfdoc_uhi_hid_mouse_config_examples - * - * For more details for Atmel® Software Framework (ASF) USB Host Stack, - * refer to following application note: - * - - * AVR4950: ASF - USB Host Stack - * - * \section asfdoc_uhi_hid_mouse_api_overview API Overview - * @{ - */ - -/** - * \name Interface with USB Host Core (UHC) - * - * Define and functions required by UHC. - * - * @{ - */ - -/** Global define which contains standard UHI API for UHC. - * - * It must be added in USB_HOST_UHI define from conf_usb_host.h file. */ -/* - * Support and FAQ: visit Atmel Support - */ -#define UHI_HID_MOUSE { \ - .install = uhi_hid_mouse_install, \ - .enable = uhi_hid_mouse_enable, \ - .uninstall = uhi_hid_mouse_uninstall, \ - .sof_notify = NULL, \ -} -/**@}*/ - -/** - * \name Functions Required by UHC - * @{ - */ - -/** - * \brief Install interface - * Allocate interface endpoints if supported. - * - * \param[in] uhc_device_t Device to request - * - * \return Status of the install. - */ -extern uhc_enum_status_t uhi_hid_mouse_install(uhc_device_t* dev); - -/** - * \brief Enable the interface. - * - * Enable a USB interface corresponding to UHI. - * - * \param[in] uhc_device_t Device to request - */ -extern void uhi_hid_mouse_enable(uhc_device_t* dev); - -/** - * \brief Uninstall the interface (if installed). - * - * \param[in] uhc_device_t Device to request - */ -extern void uhi_hid_mouse_uninstall(uhc_device_t* dev); -/**@}*/ - - -/** - * \name UHI for Human Interface Device Mouse Class - * - * Common APIs used by high level application to use this USB host class. - * - * These APIs require only callback definitions in conf_usb_host.h file - * through following defines: - * @{ - */ -#define UHI_HID_MOUSE_CHANGE(dev,b_plug) -#define UHI_HID_MOUSE_EVENT_BTN_LEFT(b_state) -#define UHI_HID_MOUSE_EVENT_BTN_RIGHT(b_state) -#define UHI_HID_MOUSE_EVENT_BTN_MIDDLE(b_state) -#define UHI_HID_MOUSE_EVENT_MOUVE(x,y,scroll) - -/**@}*/ - -/**@}*/ - -/** - * \page asfdoc_uhi_hid_mouse_exqsg Quick Start Guide for USB Host Mouse Module (UHI Mouse) - * - * This is the quick start guide for the \ref asfdoc_uhi_hid_mouse_group - * "USB Host Mouse Module (UHI Mouse)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases highlights several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section uhi_hid_mouse_basic_use_case Basic Use Case - * In this basic use case, the "USB Host HID Mouse (Single Class support)" module is used. - * The "USB Host HID Mouse (Multiple Classes support)" module usage is described - * in \ref uhi_hid_mouse_use_cases "Advanced Use Cases". - * - * \subsection uhi_hid_mouse_basic_use_case_setup Setup Steps - * As a USB host, it follows common USB host setup steps. Refer to - * \ref asfdoc_uhc_basic_use_case_setup "USB Host Basic Setup". - - * - * \subsection uhi_hid_mouse_basic_use_case_usage Usage Steps - * - * \subsubsection uhi_hid_mouse_basic_use_case_usage_code Example Code - * Content of conf_usb_host.h: - - * \code - #define USB_HOST_UHI UHI_HID_MOUSE - #define UHI_HID_MOUSE_CHANGE(dev, b_plug) my_callback_mouse_change(dev, b_plug) - extern bool my_callback_mouse_change(uhc_device_t* dev, bool b_plug); - #define UHI_HID_MOUSE_EVENT_BTN_LEFT(b_state) my_callback_event_btn_left(b_state) - extern void my_callback_event_btn_left(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_RIGHT(b_state) my_callback_event_btn_right(b_state) - extern void my_callback_event_btn_right(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_MIDDLE(b_state) my_callback_event_btn_middle(b_state) - extern void my_callback_event_btn_middle(bool b_state); - #define UHI_HID_MOUSE_EVENT_MOUVE(x, y, scroll) my_callback_event_mouse(x, y, scroll) - extern void my_callback_event_mouse(int8_t x, int8_t y, int8_t scroll); - #include "uhi_hid_mouse.h" // At the end of conf_usb_host.h file - \endcode - - * - * Add to application C-file: - * \code - bool my_callback_mouse_change(uhc_device_t* dev, bool b_plug) - { - if (b_plug) { - my_display_on_mouse_icon(); - } else { - my_display_off_mouse_icon(); - } - } - - void my_callback_event_btn_left(bool b_state) - { - if (b_state) { - // Here mouse button left pressed - } else { - // Here mouse button left released - } - } - - void my_callback_event_mouse(int8_t x, int8_t y, int8_t scroll) - { - if (!x) { - // Here mouse are moved on axe X - cursor_x += x; - } - if (!y) { - // Here mouse are moved on axe Y - cursor_y += y; - } - if (!scroll) { - // Here mouse are moved the wheel - wheel += scroll; - } - } - \endcode - * - * - * \subsubsection uhi_hid_mouse_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb_host.h is available and contains the following configuration - * which is the USB host mouse configuration: - * - * \code - #define USB_HOST_UHI UHI_HID_MOUSE - \endcode - * \note It defines the list of UHI supported by USB host. - * - * \code - #define UHI_HID_MOUSE_CHANGE(dev, b_plug) my_callback_mouse_change(dev, b_plug) - extern bool my_callback_mouse_change(uhc_device_t* dev, bool b_plug); - \endcode - * \note This callback is called when a USB device mouse is plugged or unplugged. - * - * \code - #define UHI_HID_MOUSE_EVENT_BTN_LEFT(b_state) my_callback_event_btn_left(b_state) - extern void my_callback_event_btn_left(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_RIGHT(b_state) my_callback_event_btn_right(b_state) - extern void my_callback_event_btn_right(bool b_state); - #define UHI_HID_MOUSE_EVENT_BTN_MIDDLE(b_state) my_callback_event_btn_middle(b_state) - extern void my_callback_event_btn_middle(bool b_state); - #define UHI_HID_MOUSE_EVENT_MOUVE(x, y, scroll) my_callback_event_mouse(x, y, scroll) - extern void my_callback_event_mouse(int8_t x, int8_t y, int8_t scroll) - \endcode - * \note These callbacks are called when a USB device mouse event is received. - * - * \section uhi_hid_mouse_use_cases Advanced Use Cases - * \ifnot ASF_MANUAL - * For more advanced use of the UHI HID mouse module, see the following use cases: - * - \subpage uhc_use_case_1 - * - \subpage uhc_use_case_2 - * - \subpage uhc_use_case_3 - * \else - * For more advanced use of the UHI HID mouse module, see the following: - * - \ref asfdoc_uhc_use_cases - * \endif - */ - - -/** - * \page asfdoc_uhi_hid_mouse_config_examples Configuration File Examples - * - * \section asfdoc_uhi_hid_mouse_config_examples_1 conf_usb_host.h - * \subsection asfdoc_uhi_hid_mouse_config_examples_1_1 UHI HID MOUSE Single - * \include module_config/conf_usb_host.h - * \subsection asfdoc_uhi_hid_mouse_config_examples_1_2 UHI HID MOUSE Multiple (Composite) - * \include composite/host/module_config/conf_usb_host.h - * - * \section asfdoc_uhi_hid_mouse_config_examples_2 conf_clock.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_2_1 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_clock.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_2_2 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_clock.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_2_3 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_clock.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_2_4 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_clock.h - * - * \section asfdoc_uhi_hid_mouse_config_examples_3 conf_clocks.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_3_1 SAM D21 Devices (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_clocks.h - * - * \section asfdoc_uhi_hid_mouse_config_examples_4 conf_board.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_4_1 AT32UC3A0, AT32UC3A1, AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_board.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_4_2 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_board.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_4_3 AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_board.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_4_4 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_board.h - * - * \subsection asfdoc_uhi_hid_mouse_config_examples_4_5 SAM D21 Devices (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_board.h - */ - -/** - * \page asfdoc_uhi_hid_mouse_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42342B12/2015Fixed typos
42342A12/2014Initial release
- */ - diff --git a/atmel-samd/asf/common/services/usb/class/hid/usb_protocol_hid.h b/atmel-samd/asf/common/services/usb/class/hid/usb_protocol_hid.h deleted file mode 100644 index bea54b01f89e6..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/hid/usb_protocol_hid.h +++ /dev/null @@ -1,320 +0,0 @@ -/** - * \file - * - * \brief USB Human Interface Device (HID) protocol definitions. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_PROTOCOL_HID_H_ -#define _USB_PROTOCOL_HID_H_ - - -/** - * \ingroup usb_protocol_group - * \defgroup usb_hid_protocol USB Human Interface Device (HID) - * protocol definitions - * \brief USB Human Interface Device (HID) protocol definitions - * - * @{ - */ - -//! \name Possible Class value -//@{ -#define HID_CLASS 0x03 -//@} - -//! \name Possible SubClass value -//@{ -//! Interface subclass NO support BOOT protocol -#define HID_SUB_CLASS_NOBOOT 0x00 -//! Interface subclass support BOOT protocol -#define HID_SUB_CLASS_BOOT 0x01 -//@} - -//! \name Possible protocol value -//@{ -//! Protocol generic standard -#define HID_PROTOCOL_GENERIC 0x00 -//! Protocol keyboard standard -#define HID_PROTOCOL_KEYBOARD 0x01 -//! Protocol mouse standard -#define HID_PROTOCOL_MOUSE 0x02 -//@} - - -//! \brief Hid USB requests (bRequest) -enum usb_reqid_hid { - USB_REQ_HID_GET_REPORT = 0x01, - USB_REQ_HID_GET_IDLE = 0x02, - USB_REQ_HID_GET_PROTOCOL = 0x03, - USB_REQ_HID_SET_REPORT = 0x09, - USB_REQ_HID_SET_IDLE = 0x0A, - USB_REQ_HID_SET_PROTOCOL = 0x0B, -}; - -//! \brief HID USB descriptor types -enum usb_descriptor_type_hid { - USB_DT_HID = 0x21, - USB_DT_HID_REPORT = 0x22, - USB_DT_HID_PHYSICAL = 0x23, -}; - -//! \brief HID Type for report descriptor -enum usb_hid_item_report_type { - USB_HID_ITEM_REPORT_TYPE_MAIN = 0, - USB_HID_ITEM_REPORT_TYPE_GLOBAL = 1, - USB_HID_ITEM_REPORT_TYPE_LOCAL = 2, - USB_HID_ITEM_REPORT_TYPE_LONG = 3, -}; - -//! \brief HID report type -enum usb_hid_report_type { - USB_HID_REPORT_TYPE_INPUT = 1, - USB_HID_REPORT_TYPE_OUTPUT = 2, - USB_HID_REPORT_TYPE_FEATURE = 3, -}; - - -//! \brief HID protocol -enum usb_hid_protocol { - USB_HID_PROCOTOL_BOOT = 0, - USB_HID_PROCOTOL_REPORT = 1, -}; - -COMPILER_PACK_SET(1) - -//! \brief HID Descriptor -typedef struct { - uint8_t bLength; //!< Size of this descriptor in bytes - uint8_t bDescriptorType; //!< HID descriptor type - le16_t bcdHID; //!< Binary Coded Decimal Spec. release - uint8_t bCountryCode; //!< Hardware target country - uint8_t bNumDescriptors; //!< Number of HID class descriptors to follow - uint8_t bRDescriptorType; //!< Report descriptor type - le16_t wDescriptorLength; //!< Total length of Report descriptor -} usb_hid_descriptor_t; - -COMPILER_PACK_RESET() - - //! \name HID Report type - //! Used by SETUP_HID_GET_REPORT & SETUP_HID_SET_REPORT - //! @{ -#define REPORT_TYPE_INPUT 0x01 -#define REPORT_TYPE_OUTPUT 0x02 -#define REPORT_TYPE_FEATURE 0x03 - //! @} - - //! \name Constants of field DESCRIPTOR_HID - //! @{ -//! Numeric expression identifying the HID Class -//! Specification release (here V1.11) -#define USB_HID_BDC_V1_11 0x0111 -//! Numeric expression specifying the number of class descriptors -//! Note: Always at least one i.e. Report descriptor. -#define USB_HID_NUM_DESC 0x01 - - //! \name Country code - //! @{ -#define USB_HID_NO_COUNTRY_CODE 0 // Not Supported -#define USB_HID_COUNTRY_ARABIC 1 // Arabic -#define USB_HID_COUNTRY_BELGIAN 2 // Belgian -#define USB_HID_COUNTRY_CANADIAN_BILINGUAL 3 // Canadian-Bilingual -#define USB_HID_COUNTRY_CANADIAN_FRENCH 4 // Canadian-French -#define USB_HID_COUNTRY_CZECH_REPUBLIC 5 // Czech Republic -#define USB_HID_COUNTRY_DANISH 6 // Danish -#define USB_HID_COUNTRY_FINNISH 7 // Finnish -#define USB_HID_COUNTRY_FRENCH 8 // French -#define USB_HID_COUNTRY_GERMAN 9 // German -#define USB_HID_COUNTRY_GREEK 10 // Greek -#define USB_HID_COUNTRY_HEBREW 11 // Hebrew -#define USB_HID_COUNTRY_HUNGARY 12 // Hungary -#define USB_HID_COUNTRY_INTERNATIONAL_ISO 13 // International (ISO) -#define USB_HID_COUNTRY_ITALIAN 14 // Italian -#define USB_HID_COUNTRY_JAPAN_KATAKANA 15 // Japan (Katakana) -#define USB_HID_COUNTRY_KOREAN 16 // Korean -#define USB_HID_COUNTRY_LATIN_AMERICAN 17 // Latin American -#define USB_HID_COUNTRY_NETHERLANDS_DUTCH 18 // Netherlands/Dutch -#define USB_HID_COUNTRY_NORWEGIAN 19 // Norwegian -#define USB_HID_COUNTRY_PERSIAN_FARSI 20 // Persian (Farsi) -#define USB_HID_COUNTRY_POLAND 21 // Poland -#define USB_HID_COUNTRY_PORTUGUESE 22 // Portuguese -#define USB_HID_COUNTRY_RUSSIA 23 // Russia -#define USB_HID_COUNTRY_SLOVAKIA 24 // Slovakia -#define USB_HID_COUNTRY_SPANISH 25 // Spanish -#define USB_HID_COUNTRY_SWEDISH 26 // Swedish -#define USB_HID_COUNTRY_SWISS_FRENCH 27 // Swiss/French -#define USB_HID_COUNTRY_SWISS_GERMAN 28 // Swiss/German -#define USB_HID_COUNTRY_SWITZERLAND 29 // Switzerland -#define USB_HID_COUNTRY_TAIWAN 30 // Taiwan -#define USB_HID_COUNTRY_TURKISH_Q 31 // Turkish-Q -#define USB_HID_COUNTRY_UK 32 // UK -#define USB_HID_COUNTRY_US 33 // US -#define USB_HID_COUNTRY_YUGOSLAVIA 34 // Yugoslavia -#define USB_HID_COUNTRY_TURKISH_F 35 // Turkish-F - //! @} - //! @} -//! @} - - -//! \name HID KEYS values -//! @{ -#define HID_A 0x04 -#define HID_B 0x05 -#define HID_C 0x06 -#define HID_D 0x07 -#define HID_E 0x08 -#define HID_F 0x09 -#define HID_G 0x0A -#define HID_H 0x0B -#define HID_I 0x0C -#define HID_J 0x0D -#define HID_K 0x0E -#define HID_L 0x0F -#define HID_M 0x10 -#define HID_N 0x11 -#define HID_O 0x12 -#define HID_P 0x13 -#define HID_Q 0x14 -#define HID_R 0x15 -#define HID_S 0x16 -#define HID_T 0x17 -#define HID_U 0x18 -#define HID_V 0x19 -#define HID_W 0x1A -#define HID_X 0x1B -#define HID_Y 0x1C -#define HID_Z 0x1D -#define HID_1 30 -#define HID_2 31 -#define HID_3 32 -#define HID_4 33 -#define HID_5 34 -#define HID_6 35 -#define HID_7 36 -#define HID_8 37 -#define HID_9 38 -#define HID_0 39 -#define HID_ENTER 40 -#define HID_ESCAPE 41 -#define HID_BACKSPACE 42 -#define HID_TAB 43 -#define HID_SPACEBAR 44 -#define HID_UNDERSCORE 45 -#define HID_PLUS 46 -#define HID_OPEN_BRACKET 47 // { -#define HID_CLOSE_BRACKET 48 // } -#define HID_BACKSLASH 49 -#define HID_ASH 50 // # ~ -#define HID_COLON 51 // ; : -#define HID_QUOTE 52 // ' " -#define HID_TILDE 53 -#define HID_COMMA 54 -#define HID_DOT 55 -#define HID_SLASH 56 -#define HID_CAPS_LOCK 57 -#define HID_F1 58 -#define HID_F2 59 -#define HID_F3 60 -#define HID_F4 61 -#define HID_F5 62 -#define HID_F6 63 -#define HID_F7 64 -#define HID_F8 65 -#define HID_F9 66 -#define HID_F10 67 -#define HID_F11 68 -#define HID_F12 69 -#define HID_PRINTSCREEN 70 -#define HID_SCROLL_LOCK 71 -#define HID_PAUSE 72 -#define HID_INSERT 73 -#define HID_HOME 74 -#define HID_PAGEUP 75 -#define HID_DELETE 76 -#define HID_END 77 -#define HID_PAGEDOWN 78 -#define HID_RIGHT 79 -#define HID_LEFT 80 -#define HID_DOWN 81 -#define HID_UP 82 -#define HID_KEYPAD_NUM_LOCK 83 -#define HID_KEYPAD_DIVIDE 84 -#define HID_KEYPAD_AT 85 -#define HID_KEYPAD_MULTIPLY 85 -#define HID_KEYPAD_MINUS 86 -#define HID_KEYPAD_PLUS 87 -#define HID_KEYPAD_ENTER 88 -#define HID_KEYPAD_1 89 -#define HID_KEYPAD_2 90 -#define HID_KEYPAD_3 91 -#define HID_KEYPAD_4 92 -#define HID_KEYPAD_5 93 -#define HID_KEYPAD_6 94 -#define HID_KEYPAD_7 95 -#define HID_KEYPAD_8 96 -#define HID_KEYPAD_9 97 -#define HID_KEYPAD_0 98 - - //! \name HID modifier values - //! @{ -#define HID_MODIFIER_NONE 0x00 -#define HID_MODIFIER_LEFT_CTRL 0x01 -#define HID_MODIFIER_LEFT_SHIFT 0x02 -#define HID_MODIFIER_LEFT_ALT 0x04 -#define HID_MODIFIER_LEFT_UI 0x08 -#define HID_MODIFIER_RIGHT_CTRL 0x10 -#define HID_MODIFIER_RIGHT_SHIFT 0x20 -#define HID_MODIFIER_RIGHT_ALT 0x40 -#define HID_MODIFIER_RIGHT_UI 0x80 - //! @} -//! @} - -//! \name HID KEYS values -//! @{ -#define HID_LED_NUM_LOCK (1<<0) -#define HID_LED_CAPS_LOCK (1<<1) -#define HID_LED_SCROLL_LOCK (1<<2) -#define HID_LED_COMPOSE (1<<3) -#define HID_LED_KANA (1<<4) -//! @} - -#endif // _USB_PROTOCOL_HID_H_ diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_disable/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_disable/doxyfile.doxygen deleted file mode 100644 index d00fe7536c6c5..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_disable/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_disable/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_disable/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_disable/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_enable/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_enable/doxyfile.doxygen deleted file mode 100644 index 144eb930c483d..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_enable/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device MSC (Composite Device)" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../udi_msc.c ../../udi_msc.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 ACCESS_USB_ENABLED - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_enable/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_enable/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.composite_enable/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.single/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.single/doxyfile.doxygen deleted file mode 100644 index 8ac809353af7b..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.single/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device MSC (Single Interface Device)" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../udi_msc.c ../../udi_msc_desc.c ../../udi_msc.h ../../udi_msc_conf.h ../../module_config/conf_usb.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 ACCESS_USB_ENABLED - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. 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This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.single/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.single/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/doxygen/common.services.usb.class.msc.device.single/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
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- * - * \section main_licence License - *
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  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/module_config/conf_usb.h b/atmel-samd/asf/common/services/usb/class/msc/device/module_config/conf_usb.h deleted file mode 100644 index 6dc1f1d1b1da2..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/module_config/conf_usb.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - * \file - * - * \brief USB configuration file - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_USB_H_ -#define _CONF_USB_H_ - -#include "compiler.h" - -#warning You must refill the following definitions with a correct values - -/** - * USB Device Configuration - * @{ - */ - -//! Device definition (mandatory) -#define USB_DEVICE_VENDOR_ID USB_VID_ATMEL -#define USB_DEVICE_PRODUCT_ID USB_PID_ATMEL_ASF_MSC -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on VBUS line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -// #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" -// #define USB_DEVICE_PRODUCT_NAME "Product name" -#define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC - -/** - * Device speeds support - * Low speed not supported by MSC - * @{ - */ -//! To authorize the High speed -#if (UC3A3||UC3A4) -//#define USB_DEVICE_HS_SUPPORT -#endif -//@} - - -/** - * USB Device Callbacks definitions (Optional) - * @{ - */ -// #define UDC_VBUS_EVENT(b_vbus_high) user_callback_vbus_action(b_vbus_high) -// extern void user_callback_vbus_action(bool b_vbus_high); -// #define UDC_SOF_EVENT() user_callback_sof_action() -// extern void user_callback_sof_action(void); -// #define UDC_SUSPEND_EVENT() user_callback_suspend_action() -// extern void user_callback_suspend_action(void); -// #define UDC_RESUME_EVENT() user_callback_resume_action() -// extern void user_callback_resume_action(void); -//! Mandatory when USB_DEVICE_ATTR authorizes remote wakeup feature -// #define UDC_REMOTEWAKEUP_ENABLE() user_callback_remotewakeup_enable() -// extern void user_callback_remotewakeup_enable(void); -// #define UDC_REMOTEWAKEUP_DISABLE() user_callback_remotewakeup_disable() -// extern void user_callback_remotewakeup_disable(void); -//! When a extra string descriptor must be supported -//! other than manufacturer, product and serial string -// #define UDC_GET_EXTRA_STRING() -//@} - -//@} - - -/** - * USB Interface Configuration - * @{ - */ - -/** - * Configuration of MSC interface - * @{ - */ - -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() true -#define UDI_MSC_DISABLE_EXT() -#define UDI_MSC_NOTIFY_TRANS_EXT() -/* - * #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable() - * extern bool my_callback_msc_enable(void); - * #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable() - * extern void my_callback_msc_disable(void); - * #define UDI_MSC_NOTIFY_TRANS_EXT() msc_notify_trans() - * extern void msc_notify_trans(void) { - */ -//@} - -//@} - - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_msc_conf.h" - -#endif // _CONF_USB_H_ diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc.c b/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc.c deleted file mode 100644 index 49269afa1c74e..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc.c +++ /dev/null @@ -1,1124 +0,0 @@ -/** - * \file - * - * \brief USB Device Mass Storage Class (MSC) interface. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_msc.h" -#include "spc_protocol.h" -#include "sbc_protocol.h" -#include "udd.h" -#include "udc.h" -#include "udi_msc.h" -#include "ctrl_access.h" -#include - -#ifndef UDI_MSC_NOTIFY_TRANS_EXT -# define UDI_MSC_NOTIFY_TRANS_EXT() -#endif - -/** - * \ingroup udi_msc_group - * \defgroup udi_msc_group_udc Interface with USB Device Core (UDC) - * - * Structures and functions required by UDC. - * - * @{ - */ -bool udi_msc_enable(void); -void udi_msc_disable(void); -bool udi_msc_setup(void); -uint8_t udi_msc_getsetting(void); - -//! Global structure which contains standard UDI API for UDC -UDC_DESC_STORAGE udi_api_t udi_api_msc = { - .enable = udi_msc_enable, - .disable = udi_msc_disable, - .setup = udi_msc_setup, - .getsetting = udi_msc_getsetting, - .sof_notify = NULL, -}; -//@} - - -/** - * \ingroup udi_msc_group - * \defgroup udi_msc_group_internal Implementation of UDI MSC - * - * Class internal implementation - * @{ - */ - -//! Static block size for all memories -#define UDI_MSC_BLOCK_SIZE 512L - -/** - * \name Variables to manage SCSI requests - */ -//@{ - -//! Structure to receive a CBW packet -UDC_BSS(4) static struct usb_msc_cbw udi_msc_cbw; -//! Structure to send a CSW packet -UDC_DATA(4) static struct usb_msc_csw udi_msc_csw = - {.dCSWSignature = CPU_TO_BE32(USB_CSW_SIGNATURE) }; -//! Number of lun -UDC_DATA(4) static uint8_t udi_msc_nb_lun = 0; -//! Structure with current SCSI sense data -UDC_BSS(4) static struct scsi_request_sense_data udi_msc_sense; - -/** - * \name Variables to manage the background read/write SCSI commands - */ -//@{ -//! True if an invalid CBW command has been detected -static bool udi_msc_b_cbw_invalid = false; -//! True if a transfer command must be processed -static bool udi_msc_b_trans_req = false; -//! True if it is a read command, else write command -static bool udi_msc_b_read; -//! Memory address to execute the command -static uint32_t udi_msc_addr; -//! Number of block to transfer -static uint16_t udi_msc_nb_block; -//! Signal end of transfer, if true -volatile bool udi_msc_b_ack_trans = true; -//! Status of transfer, aborted if true -volatile bool udi_msc_b_abort_trans; -//! Signal (re)init of transfer, if true (by reset/reconnect) -volatile bool udi_msc_b_reset_trans = true; -//@} - -//@} - - -/** - * \name Internal routines - */ -//@{ - -/** - * \name Routines to process CBW packet - */ -//@{ - -/** - * \brief Stall CBW request - */ -static void udi_msc_cbw_invalid(void); - -/** - * \brief Stall CSW request - */ -static void udi_msc_csw_invalid(void); - -/** - * \brief Links a callback and buffer on endpoint OUT reception - * - * Called by: - * - enable interface - * - at the end of previous command after sending the CSW - */ -static void udi_msc_cbw_wait(void); - -/** - * \brief Callback called after CBW reception - * Called by UDD when a transfer is finished or aborted - * - * \param status UDD_EP_TRANSFER_OK, if transfer is finished - * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted - * \param nb_received number of data transfered - */ -static void udi_msc_cbw_received(udd_ep_status_t status, - iram_size_t nb_received, udd_ep_id_t ep); - -/** - * \brief Function to check the CBW length and direction - * Call it after SCSI command decode to check integrity of command - * - * \param alloc_len number of bytes that device want transfer - * \param dir_flag Direction of transfer (USB_CBW_DIRECTION_IN/OUT) - * - * \retval true if the command can be processed - */ -static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag); -//@} - - -/** - * \name Routines to process small data packet - */ -//@{ - -/** - * \brief Sends data on MSC IN endpoint - * Called by SCSI command which must send a data to host followed by a CSW - * - * \param buffer Internal RAM buffer to send - * \param buf_size Size of buffer to send - */ -static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size); - -/** - * \brief Callback called after data sent - * It start CSW packet process - * - * \param status UDD_EP_TRANSFER_OK, if transfer finish - * \param status UDD_EP_TRANSFER_ABORT, if transfer aborted - * \param nb_sent number of data transfered - */ -static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent, - udd_ep_id_t ep); -//@} - - -/** - * \name Routines to process CSW packet - */ -//@{ - -/** - * \brief Build CSW packet and send it - * - * Called at the end of SCSI command - */ -static void udi_msc_csw_process(void); - -/** - * \brief Sends CSW - * - * Called by #udi_msc_csw_process() - * or UDD callback when endpoint halt is cleared - */ -void udi_msc_csw_send(void); - -/** - * \brief Callback called after CSW sent - * It restart CBW reception. - * - * \param status UDD_EP_TRANSFER_OK, if transfer is finished - * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted - * \param nb_sent number of data transfered - */ -static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent, - udd_ep_id_t ep); -//@} - - -/** - * \name Routines manage sense data - */ -//@{ - -/** - * \brief Reinitialize sense data. - */ -static void udi_msc_clear_sense(void); - -/** - * \brief Update sense data with new value to signal a fail - * - * \param sense_key Sense key - * \param add_sense Additional Sense Code - * \param lba LBA corresponding at error - */ -static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense, - uint32_t lba); - -/** - * \brief Update sense data with new value to signal success - */ -static void udi_msc_sense_pass(void); - -/** - * \brief Update sense data to signal that memory is not present - */ -static void udi_msc_sense_fail_not_present(void); - -/** - * \brief Update sense data to signal that memory is busy - */ -static void udi_msc_sense_fail_busy_or_change(void); - -/** - * \brief Update sense data to signal a hardware error on memory - */ -static void udi_msc_sense_fail_hardware(void); - -/** - * \brief Update sense data to signal that memory is protected - */ -static void udi_msc_sense_fail_protected(void); - -/** - * \brief Update sense data to signal that CDB fields are not valid - */ -static void udi_msc_sense_fail_cdb_invalid(void); - -/** - * \brief Update sense data to signal that command is not supported - */ -static void udi_msc_sense_command_invalid(void); -//@} - - -/** - * \name Routines manage SCSI Commands - */ -//@{ - -/** - * \brief Process SPC Request Sense command - * Returns error information about last command - */ -static void udi_msc_spc_requestsense(void); - -/** - * \brief Process SPC Inquiry command - * Returns information (name,version) about disk - */ -static void udi_msc_spc_inquiry(void); - -/** - * \brief Checks state of disk - * - * \retval true if disk is ready, otherwise false and updates sense data - */ -static bool udi_msc_spc_testunitready_global(void); - -/** - * \brief Process test unit ready command - * Returns state of logical unit - */ -static void udi_msc_spc_testunitready(void); - -/** - * \brief Process prevent allow medium removal command - */ -static void udi_msc_spc_prevent_allow_medium_removal(void); - -/** - * \brief Process mode sense command - * - * \param b_sense10 Sense10 SCSI command, if true - * \param b_sense10 Sense6 SCSI command, if false - */ -static void udi_msc_spc_mode_sense(bool b_sense10); - -/** - * \brief Process start stop command - */ -static void udi_msc_sbc_start_stop(void); - -/** - * \brief Process read capacity command - */ -static void udi_msc_sbc_read_capacity(void); - -/** - * \brief Process read10 or write10 command - * - * \param b_read Read transfer, if true, - * \param b_read Write transfer, if false - */ -static void udi_msc_sbc_trans(bool b_read); -//@} - -//@} - - -bool udi_msc_enable(void) -{ - uint8_t lun; - udi_msc_b_trans_req = false; - udi_msc_b_cbw_invalid = false; - udi_msc_b_ack_trans = true; - udi_msc_b_reset_trans = true; - udi_msc_nb_lun = get_nb_lun(); - if (0 == udi_msc_nb_lun) - return false; // No lun available, then not authorize to enable interface - udi_msc_nb_lun--; - // Call application callback - // to initialize memories or signal that interface is enabled - if (!UDI_MSC_ENABLE_EXT()) - return false; - // Load the medium on each LUN - for (lun = 0; lun <= udi_msc_nb_lun; lun ++) { - mem_unload(lun, false); - } - // Start MSC process by CBW reception - udi_msc_cbw_wait(); - return true; -} - - -void udi_msc_disable(void) -{ - udi_msc_b_trans_req = false; - udi_msc_b_ack_trans = true; - udi_msc_b_reset_trans = true; - UDI_MSC_DISABLE_EXT(); -} - - -bool udi_msc_setup(void) -{ - if (Udd_setup_is_in()) { - // Requests Interface GET - if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { - // Requests Class Interface Get - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_MSC_GET_MAX_LUN: - // Give the number of memories available - if (1 != udd_g_ctrlreq.req.wLength) - return false; // Error for USB host - if (0 != udd_g_ctrlreq.req.wValue) - return false; - udd_g_ctrlreq.payload = &udi_msc_nb_lun; - udd_g_ctrlreq.payload_size = 1; - return true; - } - } - } - if (Udd_setup_is_out()) { - // Requests Interface SET - if (Udd_setup_type() == USB_REQ_TYPE_CLASS) { - // Requests Class Interface Set - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_MSC_BULK_RESET: - // Reset MSC interface - if (0 != udd_g_ctrlreq.req.wLength) - return false; - if (0 != udd_g_ctrlreq.req.wValue) - return false; - udi_msc_b_cbw_invalid = false; - udi_msc_b_trans_req = false; - // Abort all tasks (transfer or clear stall wait) on endpoints - udd_ep_abort(UDI_MSC_EP_OUT); - udd_ep_abort(UDI_MSC_EP_IN); - // Restart by CBW wait - udi_msc_cbw_wait(); - return true; - } - } - } - return false; // Not supported request -} - -uint8_t udi_msc_getsetting(void) -{ - return 0; // MSC don't have multiple alternate setting -} - - -//--------------------------------------------- -//------- Routines to process CBW packet - -static void udi_msc_cbw_invalid(void) -{ - if (!udi_msc_b_cbw_invalid) - return; // Don't re-stall endpoint if error reseted by setup - udd_ep_set_halt(UDI_MSC_EP_OUT); - // If stall cleared then re-stall it. Only Setup MSC Reset can clear it - udd_ep_wait_stall_clear(UDI_MSC_EP_OUT, udi_msc_cbw_invalid); -} - -static void udi_msc_csw_invalid(void) -{ - if (!udi_msc_b_cbw_invalid) - return; // Don't re-stall endpoint if error reseted by setup - udd_ep_set_halt(UDI_MSC_EP_IN); - // If stall cleared then re-stall it. Only Setup MSC Reset can clear it - udd_ep_wait_stall_clear(UDI_MSC_EP_IN, udi_msc_csw_invalid); -} - -static void udi_msc_cbw_wait(void) -{ - // Register buffer and callback on OUT endpoint - if (!udd_ep_run(UDI_MSC_EP_OUT, true, - (uint8_t *) & udi_msc_cbw, - sizeof(udi_msc_cbw), - udi_msc_cbw_received)) { - // OUT endpoint not available (halted), then wait a clear of halt. - udd_ep_wait_stall_clear(UDI_MSC_EP_OUT, udi_msc_cbw_wait); - } -} - - -static void udi_msc_cbw_received(udd_ep_status_t status, - iram_size_t nb_received, udd_ep_id_t ep) -{ - UNUSED(ep); - // Check status of transfer - if (UDD_EP_TRANSFER_OK != status) { - // Transfer aborted - // Now wait MSC setup reset to relaunch CBW reception - return; - } - // Check CBW integrity: - // transfer status/CBW length/CBW signature - if ((sizeof(udi_msc_cbw) != nb_received) - || (udi_msc_cbw.dCBWSignature != - CPU_TO_BE32(USB_CBW_SIGNATURE))) { - // (5.2.1) Devices receiving a CBW with an invalid signature should stall - // further traffic on the Bulk In pipe, and either stall further traffic - // or accept and discard further traffic on the Bulk Out pipe, until - // reset recovery. - udi_msc_b_cbw_invalid = true; - udi_msc_cbw_invalid(); - udi_msc_csw_invalid(); - return; - } - // Check LUN asked - udi_msc_cbw.bCBWLUN &= USB_CBW_LUN_MASK; - if (udi_msc_cbw.bCBWLUN > udi_msc_nb_lun) { - // Bad LUN, then stop command process - udi_msc_sense_fail_cdb_invalid(); - udi_msc_csw_process(); - return; - } - // Prepare CSW residue field with the size requested - udi_msc_csw.dCSWDataResidue = - le32_to_cpu(udi_msc_cbw.dCBWDataTransferLength); - - // Decode opcode - switch (udi_msc_cbw.CDB[0]) { - case SPC_REQUEST_SENSE: - udi_msc_spc_requestsense(); - break; - - case SPC_INQUIRY: - udi_msc_spc_inquiry(); - break; - - case SPC_MODE_SENSE6: - udi_msc_spc_mode_sense(false); - break; - case SPC_MODE_SENSE10: - udi_msc_spc_mode_sense(true); - break; - - case SPC_TEST_UNIT_READY: - udi_msc_spc_testunitready(); - break; - - case SBC_READ_CAPACITY10: - udi_msc_sbc_read_capacity(); - break; - - case SBC_START_STOP_UNIT: - udi_msc_sbc_start_stop(); - break; - - // Accepts request to support plug/plug in case of card reader - case SPC_PREVENT_ALLOW_MEDIUM_REMOVAL: - udi_msc_spc_prevent_allow_medium_removal(); - break; - - // Accepts request to support full format from Windows - case SBC_VERIFY10: - udi_msc_sense_pass(); - udi_msc_csw_process(); - break; - - case SBC_READ10: - udi_msc_sbc_trans(true); - break; - - case SBC_WRITE10: - udi_msc_sbc_trans(false); - break; - - default: - udi_msc_sense_command_invalid(); - udi_msc_csw_process(); - break; - } -} - - -static bool udi_msc_cbw_validate(uint32_t alloc_len, uint8_t dir_flag) -{ - /* - * The following cases should result in a phase error: - * - Case 2: Hn < Di - * - Case 3: Hn < Do - * - Case 7: Hi < Di - * - Case 8: Hi <> Do - * - Case 10: Ho <> Di - * - Case 13: Ho < Do - */ - if (((udi_msc_cbw.bmCBWFlags ^ dir_flag) & USB_CBW_DIRECTION_IN) - || (udi_msc_csw.dCSWDataResidue < alloc_len)) { - udi_msc_sense_fail_cdb_invalid(); - udi_msc_csw_process(); - return false; - } - - /* - * The following cases should result in a stall and nonzero - * residue: - * - Case 4: Hi > Dn - * - Case 5: Hi > Di - * - Case 9: Ho > Dn - * - Case 11: Ho > Do - */ - return true; -} - - -//--------------------------------------------- -//------- Routines to process small data packet - -static void udi_msc_data_send(uint8_t * buffer, uint8_t buf_size) -{ - // Sends data on IN endpoint - if (!udd_ep_run(UDI_MSC_EP_IN, true, - buffer, buf_size, udi_msc_data_sent)) { - // If endpoint not available, then exit process command - udi_msc_sense_fail_hardware(); - udi_msc_csw_process(); - } -} - - -static void udi_msc_data_sent(udd_ep_status_t status, iram_size_t nb_sent, - udd_ep_id_t ep) -{ - UNUSED(ep); - if (UDD_EP_TRANSFER_OK != status) { - // Error protocol - // Now wait MSC setup reset to relaunch CBW reception - return; - } - // Update sense data - udi_msc_sense_pass(); - // Update CSW - udi_msc_csw.dCSWDataResidue -= nb_sent; - udi_msc_csw_process(); -} - - -//--------------------------------------------- -//------- Routines to process CSW packet - -static void udi_msc_csw_process(void) -{ - if (0 != udi_msc_csw.dCSWDataResidue) { - // Residue not NULL - // then STALL next request from USB host on corresponding endpoint - if (udi_msc_cbw.bmCBWFlags & USB_CBW_DIRECTION_IN) - udd_ep_set_halt(UDI_MSC_EP_IN); - else - udd_ep_set_halt(UDI_MSC_EP_OUT); - } - // Prepare and send CSW - udi_msc_csw.dCSWTag = udi_msc_cbw.dCBWTag; - udi_msc_csw.dCSWDataResidue = cpu_to_le32(udi_msc_csw.dCSWDataResidue); - udi_msc_csw_send(); -} - - -void udi_msc_csw_send(void) -{ - // Sends CSW on IN endpoint - if (!udd_ep_run(UDI_MSC_EP_IN, false, - (uint8_t *) & udi_msc_csw, - sizeof(udi_msc_csw), - udi_msc_csw_sent)) { - // Endpoint not available - // then restart CSW sent when endpoint IN STALL will be cleared - udd_ep_wait_stall_clear(UDI_MSC_EP_IN, udi_msc_csw_send); - } -} - - -static void udi_msc_csw_sent(udd_ep_status_t status, iram_size_t nb_sent, - udd_ep_id_t ep) -{ - UNUSED(ep); - UNUSED(status); - UNUSED(nb_sent); - // CSW is sent or not - // In all case, restart process and wait CBW - udi_msc_cbw_wait(); -} - - -//--------------------------------------------- -//------- Routines manage sense data - -static void udi_msc_clear_sense(void) -{ - memset((uint8_t*)&udi_msc_sense, 0, sizeof(struct scsi_request_sense_data)); - udi_msc_sense.valid_reponse_code = SCSI_SENSE_VALID | SCSI_SENSE_CURRENT; - udi_msc_sense.AddSenseLen = SCSI_SENSE_ADDL_LEN(sizeof(udi_msc_sense)); -} - -static void udi_msc_sense_fail(uint8_t sense_key, uint16_t add_sense, - uint32_t lba) -{ - udi_msc_clear_sense(); - udi_msc_csw.bCSWStatus = USB_CSW_STATUS_FAIL; - udi_msc_sense.sense_flag_key = sense_key; - udi_msc_sense.information[0] = lba >> 24; - udi_msc_sense.information[1] = lba >> 16; - udi_msc_sense.information[2] = lba >> 8; - udi_msc_sense.information[3] = lba; - udi_msc_sense.AddSenseCode = add_sense >> 8; - udi_msc_sense.AddSnsCodeQlfr = add_sense; -} - -static void udi_msc_sense_pass(void) -{ - udi_msc_clear_sense(); - udi_msc_csw.bCSWStatus = USB_CSW_STATUS_PASS; -} - - -static void udi_msc_sense_fail_not_present(void) -{ - udi_msc_sense_fail(SCSI_SK_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT, 0); -} - -static void udi_msc_sense_fail_busy_or_change(void) -{ - udi_msc_sense_fail(SCSI_SK_UNIT_ATTENTION, - SCSI_ASC_NOT_READY_TO_READY_CHANGE, 0); -} - -static void udi_msc_sense_fail_hardware(void) -{ - udi_msc_sense_fail(SCSI_SK_HARDWARE_ERROR, - SCSI_ASC_NO_ADDITIONAL_SENSE_INFO, 0); -} - -static void udi_msc_sense_fail_protected(void) -{ - udi_msc_sense_fail(SCSI_SK_DATA_PROTECT, SCSI_ASC_WRITE_PROTECTED, 0); -} - -static void udi_msc_sense_fail_cdb_invalid(void) -{ - udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, - SCSI_ASC_INVALID_FIELD_IN_CDB, 0); -} - -static void udi_msc_sense_command_invalid(void) -{ - udi_msc_sense_fail(SCSI_SK_ILLEGAL_REQUEST, - SCSI_ASC_INVALID_COMMAND_OPERATION_CODE, 0); -} - - -//--------------------------------------------- -//------- Routines manage SCSI Commands - -static void udi_msc_spc_requestsense(void) -{ - uint8_t length = udi_msc_cbw.CDB[4]; - - // Can't send more than sense data length - if (length > sizeof(udi_msc_sense)) - length = sizeof(udi_msc_sense); - - if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN)) - return; - // Send sense data - udi_msc_data_send((uint8_t*)&udi_msc_sense, length); -} - - -static void udi_msc_spc_inquiry(void) -{ - uint8_t length, i; - UDC_DATA(4) - // Constant inquiry data for all LUNs - static struct scsi_inquiry_data udi_msc_inquiry_data = { - .pq_pdt = SCSI_INQ_PQ_CONNECTED | SCSI_INQ_DT_DIR_ACCESS, - .version = SCSI_INQ_VER_SPC, - .flags3 = SCSI_INQ_RSP_SPC2, - .addl_len = SCSI_INQ_ADDL_LEN(sizeof(struct scsi_inquiry_data)), - .vendor_id = {UDI_MSC_GLOBAL_VENDOR_ID}, - .product_rev = {UDI_MSC_GLOBAL_PRODUCT_VERSION}, - }; - - length = udi_msc_cbw.CDB[4]; - - // Can't send more than inquiry data length - if (length > sizeof(udi_msc_inquiry_data)) - length = sizeof(udi_msc_inquiry_data); - - if (!udi_msc_cbw_validate(length, USB_CBW_DIRECTION_IN)) - return; - if ((0 != (udi_msc_cbw.CDB[1] & (SCSI_INQ_REQ_EVPD | SCSI_INQ_REQ_CMDT))) - || (0 != udi_msc_cbw.CDB[2])) { - // CMDT and EPVD bits are not at 0 - // PAGE or OPERATION CODE fields are not empty - // = No standard inquiry asked - udi_msc_sense_fail_cdb_invalid(); // Command is unsupported - udi_msc_csw_process(); - return; - } - - udi_msc_inquiry_data.flags1 = mem_removal(udi_msc_cbw.bCBWLUN) ? - SCSI_INQ_RMB : 0; - - //* Fill product ID field - // Copy name in product id field - memcpy(udi_msc_inquiry_data.product_id, - mem_name(udi_msc_cbw.bCBWLUN)+1, // To remove first '"' - sizeof(udi_msc_inquiry_data.product_id)); - - // Search end of name '/0' or '"' - i = 0; - while (sizeof(udi_msc_inquiry_data.product_id) != i) { - if ((0 == udi_msc_inquiry_data.product_id[i]) - || ('"' == udi_msc_inquiry_data.product_id[i])) { - break; - } - i++; - } - // Padding with space char - while (sizeof(udi_msc_inquiry_data.product_id) != i) { - udi_msc_inquiry_data.product_id[i] = ' '; - i++; - } - - // Send inquiry data - udi_msc_data_send((uint8_t *) & udi_msc_inquiry_data, length); -} - - -static bool udi_msc_spc_testunitready_global(void) -{ - switch (mem_test_unit_ready(udi_msc_cbw.bCBWLUN)) { - case CTRL_GOOD: - return true; // Don't change sense data - case CTRL_BUSY: - udi_msc_sense_fail_busy_or_change(); - break; - case CTRL_NO_PRESENT: - udi_msc_sense_fail_not_present(); - break; - case CTRL_FAIL: - default: - udi_msc_sense_fail_hardware(); - break; - } - return false; -} - - -static void udi_msc_spc_testunitready(void) -{ - if (udi_msc_spc_testunitready_global()) { - // LUN ready, then update sense data with status pass - udi_msc_sense_pass(); - } - // Send status in CSW packet - udi_msc_csw_process(); -} - - -static void udi_msc_spc_mode_sense(bool b_sense10) -{ - // Union of all mode sense structures - union sense_6_10 { - struct { - struct scsi_mode_param_header6 header; - struct spc_control_page_info_execpt sense_data; - } s6; - struct { - struct scsi_mode_param_header10 header; - struct spc_control_page_info_execpt sense_data; - } s10; - }; - - uint8_t data_sense_lgt; - uint8_t mode; - uint8_t request_lgt; - uint8_t wp; - struct spc_control_page_info_execpt *ptr_mode; - UDC_BSS(4) static union sense_6_10 sense; - - // Clear all fields - memset(&sense, 0, sizeof(sense)); - - // Initialize process - if (b_sense10) { - request_lgt = udi_msc_cbw.CDB[8]; - ptr_mode = &sense.s10.sense_data; - data_sense_lgt = sizeof(struct scsi_mode_param_header10); - } else { - request_lgt = udi_msc_cbw.CDB[4]; - ptr_mode = &sense.s6.sense_data; - data_sense_lgt = sizeof(struct scsi_mode_param_header6); - } - - // No Block descriptor - - // Fill page(s) - mode = udi_msc_cbw.CDB[2] & SCSI_MS_MODE_ALL; - if ((SCSI_MS_MODE_INFEXP == mode) - || (SCSI_MS_MODE_ALL == mode)) { - // Informational exceptions control page (from SPC) - ptr_mode->page_code = - SCSI_MS_MODE_INFEXP; - ptr_mode->page_length = - SPC_MP_INFEXP_PAGE_LENGTH; - ptr_mode->mrie = - SPC_MP_INFEXP_MRIE_NO_SENSE; - data_sense_lgt += sizeof(struct spc_control_page_info_execpt); - } - // Can't send more than mode sense data length - if (request_lgt > data_sense_lgt) - request_lgt = data_sense_lgt; - if (!udi_msc_cbw_validate(request_lgt, USB_CBW_DIRECTION_IN)) - return; - - // Fill mode parameter header length - wp = (mem_wr_protect(udi_msc_cbw.bCBWLUN)) ? SCSI_MS_SBC_WP : 0; - - if (b_sense10) { - sense.s10.header.mode_data_length = - cpu_to_be16((data_sense_lgt - 2)); - //sense.s10.header.medium_type = 0; - sense.s10.header.device_specific_parameter = wp; - //sense.s10.header.block_descriptor_length = 0; - } else { - sense.s6.header.mode_data_length = data_sense_lgt - 1; - //sense.s6.header.medium_type = 0; - sense.s6.header.device_specific_parameter = wp; - //sense.s6.header.block_descriptor_length = 0; - } - - // Send mode sense data - udi_msc_data_send((uint8_t *) & sense, request_lgt); -} - - -static void udi_msc_spc_prevent_allow_medium_removal(void) -{ - uint8_t prevent = udi_msc_cbw.CDB[4]; - if (0 == prevent) { - udi_msc_sense_pass(); - } else { - udi_msc_sense_fail_cdb_invalid(); // Command is unsupported - } - udi_msc_csw_process(); -} - - -static void udi_msc_sbc_start_stop(void) -{ - bool start = 0x1 & udi_msc_cbw.CDB[4]; - bool loej = 0x2 & udi_msc_cbw.CDB[4]; - if (loej) { - mem_unload(udi_msc_cbw.bCBWLUN, !start); - } - udi_msc_sense_pass(); - udi_msc_csw_process(); -} - - -static void udi_msc_sbc_read_capacity(void) -{ - UDC_BSS(4) static struct sbc_read_capacity10_data udi_msc_capacity; - - if (!udi_msc_cbw_validate(sizeof(udi_msc_capacity), - USB_CBW_DIRECTION_IN)) - return; - - // Get capacity of LUN - switch (mem_read_capacity(udi_msc_cbw.bCBWLUN, - &udi_msc_capacity.max_lba)) { - case CTRL_GOOD: - break; - case CTRL_BUSY: - udi_msc_sense_fail_busy_or_change(); - udi_msc_csw_process(); - return; - case CTRL_NO_PRESENT: - udi_msc_sense_fail_not_present(); - udi_msc_csw_process(); - return; - default: - udi_msc_sense_fail_hardware(); - udi_msc_csw_process(); - return; - } - - // Format capacity data - udi_msc_capacity.block_len = CPU_TO_BE32(UDI_MSC_BLOCK_SIZE); - udi_msc_capacity.max_lba = cpu_to_be32(udi_msc_capacity.max_lba); - // Send the corresponding sense data - udi_msc_data_send((uint8_t *) & udi_msc_capacity, - sizeof(udi_msc_capacity)); -} - - -static void udi_msc_sbc_trans(bool b_read) -{ - uint32_t trans_size; - - if (!b_read) { - // Write operation then check Write Protect - if (mem_wr_protect(udi_msc_cbw.bCBWLUN)) { - // Write not authorized - udi_msc_sense_fail_protected(); - udi_msc_csw_process(); - return; - } - } - // Read/Write command fields (address and number of block) - MSB0(udi_msc_addr) = udi_msc_cbw.CDB[2]; - MSB1(udi_msc_addr) = udi_msc_cbw.CDB[3]; - MSB2(udi_msc_addr) = udi_msc_cbw.CDB[4]; - MSB3(udi_msc_addr) = udi_msc_cbw.CDB[5]; - MSB(udi_msc_nb_block) = udi_msc_cbw.CDB[7]; - LSB(udi_msc_nb_block) = udi_msc_cbw.CDB[8]; - - // Compute number of byte to transfer and valid it - trans_size = (uint32_t) udi_msc_nb_block *UDI_MSC_BLOCK_SIZE; - if (!udi_msc_cbw_validate(trans_size, - (b_read) ? USB_CBW_DIRECTION_IN : - USB_CBW_DIRECTION_OUT)) - return; - - // Record transfer request to do it in a task and not under interrupt - udi_msc_b_read = b_read; - udi_msc_b_trans_req = true; - UDI_MSC_NOTIFY_TRANS_EXT(); -} - - -bool udi_msc_process_trans(void) -{ - Ctrl_status status; - - if (!udi_msc_b_trans_req) - return false; // No Transfer request to do - udi_msc_b_trans_req = false; - udi_msc_b_reset_trans = false; - - // Start transfer - if (udi_msc_b_read) { - status = memory_2_usb(udi_msc_cbw.bCBWLUN, udi_msc_addr, - udi_msc_nb_block); - } else { - status = usb_2_memory(udi_msc_cbw.bCBWLUN, udi_msc_addr, - udi_msc_nb_block); - } - - // Check if transfer is aborted by reset - if (udi_msc_b_reset_trans) { - udi_msc_b_reset_trans = false; - return true; - } - - // Check status of transfer - switch (status) { - case CTRL_GOOD: - udi_msc_sense_pass(); - break; - case CTRL_BUSY: - udi_msc_sense_fail_busy_or_change(); - break; - case CTRL_NO_PRESENT: - udi_msc_sense_fail_not_present(); - break; - default: - case CTRL_FAIL: - udi_msc_sense_fail_hardware(); - break; - } - // Send status of transfer in CSW packet - udi_msc_csw_process(); - return true; -} - - -static void udi_msc_trans_ack(udd_ep_status_t status, iram_size_t n, - udd_ep_id_t ep) -{ - UNUSED(ep); - UNUSED(n); - // Update variable to signal the end of transfer - udi_msc_b_abort_trans = (UDD_EP_TRANSFER_OK != status) ? true : false; - udi_msc_b_ack_trans = true; -} - - -bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size, - void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)) -{ - if (!udi_msc_b_ack_trans) - return false; // No possible, transfer on going - - // Start transfer Internal RAM<->USB line - udi_msc_b_ack_trans = false; - if (!udd_ep_run((b_read) ? UDI_MSC_EP_IN : UDI_MSC_EP_OUT, - false, - block, - block_size, - (NULL == callback) ? udi_msc_trans_ack : - callback)) { - udi_msc_b_ack_trans = true; - return false; - } - if (NULL == callback) { - while (!udi_msc_b_ack_trans); - if (udi_msc_b_abort_trans) { - return false; - } - udi_msc_csw.dCSWDataResidue -= block_size; - return (!udi_msc_b_abort_trans); - } - udi_msc_csw.dCSWDataResidue -= block_size; - return true; -} - -//@} diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc.h b/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc.h deleted file mode 100644 index 7a76ad84fc992..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc.h +++ /dev/null @@ -1,376 +0,0 @@ -/** - * \file - * - * \brief USB Device Mass Storage Class (MSC) interface definitions. - * - * Copyright (c) 2009-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_MSC_H_ -#define _UDI_MSC_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "usb_protocol_msc.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup udi_msc_group_udc - * @{ - */ -//! Global structure which contains standard UDI interface for UDC -extern UDC_DESC_STORAGE udi_api_t udi_api_msc; -//@} - -/** - * \ingroup udi_msc_group - * \defgroup udi_msc_group USB interface descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - */ -//@{ - -//! Interface descriptor structure for MSC -typedef struct { - usb_iface_desc_t iface; - usb_ep_desc_t ep_in; - usb_ep_desc_t ep_out; -} udi_msc_desc_t; - -//! By default no string associated to this interface -#ifndef UDI_MSC_STRING_ID -#define UDI_MSC_STRING_ID 0 -#endif - -//! MSC endpoints size for full speed -#define UDI_MSC_EPS_SIZE_FS 64 -//! MSC endpoints size for high speed -#define UDI_MSC_EPS_SIZE_HS 512 - -//! Content of MSC interface descriptor for all speeds -#define UDI_MSC_DESC \ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_MSC_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 2,\ - .iface.bInterfaceClass = MSC_CLASS,\ - .iface.bInterfaceSubClass = MSC_SUBCLASS_TRANSPARENT,\ - .iface.bInterfaceProtocol = MSC_PROTOCOL_BULK,\ - .iface.iInterface = UDI_MSC_STRING_ID,\ - .ep_in.bLength = sizeof(usb_ep_desc_t),\ - .ep_in.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_in.bEndpointAddress = UDI_MSC_EP_IN,\ - .ep_in.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_in.bInterval = 0,\ - .ep_out.bLength = sizeof(usb_ep_desc_t),\ - .ep_out.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_out.bEndpointAddress = UDI_MSC_EP_OUT,\ - .ep_out.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_out.bInterval = 0, - -//! Content of MSC interface descriptor for full speed only -#define UDI_MSC_DESC_FS {\ - UDI_MSC_DESC \ - .ep_in.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_FS),\ - .ep_out.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_FS),\ - } - -//! Content of MSC interface descriptor for high speed only -#define UDI_MSC_DESC_HS {\ - UDI_MSC_DESC \ - .ep_in.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_HS),\ - .ep_out.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_HS),\ - } -//@} - - -/** - * \ingroup udi_group - * \defgroup udi_msc_group USB Device Interface (UDI) for Mass Storage Class (MSC) - * - * Common APIs used by high level application to use this USB class. - * - * These routines are used by memory to transfer its data - * to/from USB MSC endpoints. - * - * See \ref udi_msc_quickstart. - * @{ - */ - -/** - * \brief Process the background read/write commands - * - * Routine called by the main loop - */ -bool udi_msc_process_trans(void); - -/** - * \brief Transfers data to/from USB MSC endpoints - * - * - * \param b_read Memory to USB, if true - * \param block Buffer on Internal RAM to send or fill - * \param block_size Buffer size to send or fill - * \param callback Function to call at the end of transfer. - * If NULL then the routine exit when transfer is finish. - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size, - void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)); -//@} - -#ifdef __cplusplus -} -#endif - - -/** - * \page udi_msc_quickstart Quick start guide for USB device Mass Storage module (UDI MSC) - * - * This is the quick start guide for the \ref udi_msc_group - * "USB device interface MSC module (UDI MSC)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section udi_msc_basic_use_case Basic use case - * In this basic use case, the "USB MSC (Single Interface Device)" module is used. - * The "USB MSC (Composite Device)" module usage is described in \ref udi_msc_use_cases - * "Advanced use cases". - * - * \section udi_msc_basic_use_case_setup Setup steps - * \subsection udi_msc_basic_use_case_setup_prereq Prerequisites - * \copydetails udc_basic_use_case_setup_prereq - * \subsection udi_msc_basic_use_case_setup_code Example code - * \copydetails udc_basic_use_case_setup_code - * \subsection udi_msc_basic_use_case_setup_flow Workflow - * \copydetails udc_basic_use_case_setup_flow - * - * \section udi_msc_basic_use_case_usage Usage steps - * - * \subsection udi_msc_basic_use_case_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC - #define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' - #define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable() - extern bool my_callback_msc_enable(void); - #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable() - extern void my_callback_msc_disable(void); - #include "udi_msc_conf.h" // At the end of conf_usb.h file -\endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_msc_transfert = false; - bool my_callback_msc_enable(void) - { - my_flag_autorize_msc_transfert = true; - return true; - } - void my_callback_msc_disable(void) - { - my_flag_autorize_msc_transfert = false; - } - - void task(void) - { - udi_msc_process_trans(); - } -\endcode - * - * \subsection udi_msc_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration, - * which is the USB device MSC configuration: - * - \code #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC \endcode - * \note The USB serial number is mandatory when a MSC interface is used. - * - \code //! Vendor name and Product version of MSC interface - #define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' - #define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' \endcode - * \note The USB MSC interface requires a vendor ID (8 ASCII characters) - * and a product version (4 ASCII characters). - * - \code #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable() - extern bool my_callback_msc_enable(void); \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB MSC interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_MSC_ENABLE_EXT() callback function is called and return true. - * Thus, when this event is received, the tasks which call - * udi_msc_process_trans() must be enabled. - * - \code #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable() - extern void my_callback_msc_disable(void); \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_MSC_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable the task which is called udi_msc_process_trans(). - * -# The MSC is automatically linked with memory control access component - * which provides the memories interfaces. However, the memory data transfers - * must be done outside USB interrupt routine. This is done in the MSC process - * ("udi_msc_process_trans()") called by main loop: - * - \code * void task(void) { - udi_msc_process_trans(); - } \endcode - * -# The MSC speed depends on task periodicity. To get the best speed - * the notification callback "UDI_MSC_NOTIFY_TRANS_EXT" can be used to wakeup - * this task (Example, through a mutex): - * - \code #define UDI_MSC_NOTIFY_TRANS_EXT() msc_notify_trans() - void msc_notify_trans(void) { - wakeup_my_task(); - } \endcode - * - * \section udi_msc_use_cases Advanced use cases - * For more advanced use of the UDI MSC module, see the following use cases: - * - \subpage udi_msc_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - */ - -/** - * \page udi_msc_use_case_composite MSC in a composite device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB MSC (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB HID Mouse (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_msc_use_case_composite_setup Setup steps - * For the setup code of this use case to work, the - * \ref udi_msc_basic_use_case "basic use case" must be followed. - * - * \section udi_msc_use_case_composite_usage Usage steps - * - * \subsection udi_msc_use_case_composite_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+2) - - #define UDI_MSC_EP_IN (X | USB_EP_DIR_IN) - #define UDI_MSC_EP_OUT (Y | USB_EP_DIR_OUT) - #define UDI_MSC_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_msc_desc_t udi_msc; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_msc = UDI_MSC_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_msc = UDI_MSC_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_msc, \ - ... -\endcode - * - * \subsection udi_msc_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * - \code // Endpoint control size, This must be: - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for MSC. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 2 for MSC. - #define USB_DEVICE_MAX_EP (X+2) \endcode - * -# Ensure that conf_usb.h contains the description of - * composite device: - * - \code // The endpoint numbers chosen by you for the MSC. - // The endpoint numbers starting from 1. - #define UDI_MSC_EP_IN (X | USB_EP_DIR_IN) - #define UDI_MSC_EP_OUT (Y | USB_EP_DIR_OUT) - // The interface index of an interface starting from 0 - #define UDI_MSC_IFACE_NUMBER X \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * - \code // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_msc_desc_t udi_msc; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_msc = UDI_MSC_DESC_FS, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_msc = UDI_MSC_DESC_HS, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_msc, \ - ... \endcode - * - \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -#endif // _UDI_MSC_H_ diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_conf.h b/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_conf.h deleted file mode 100644 index faad843002e70..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_conf.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * \file - * - * \brief Default MSC configuration for a USB Device - * with a single interface MSC - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_MSC_CONF_H_ -#define _UDI_MSC_CONF_H_ - -/** - * \addtogroup udi_msc_group_single_desc - * @{ - */ - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Endpoint numbers used by MSC interface -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number is 0 because it is the unique interface -#define UDI_MSC_IFACE_NUMBER 0 - -/** - * \name UDD Configuration - */ -//@{ -//! 2 endpoints used by MSC interface -#undef USB_DEVICE_MAX_EP // undefine this definition in header file -#define USB_DEVICE_MAX_EP 2 -//@} - -//@} - -#include "udi_msc.h" - -#endif // _UDI_MSC_CONF_H_ diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_desc.c b/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_desc.c deleted file mode 100644 index ca0fa71ce5ac5..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_desc.c +++ /dev/null @@ -1,189 +0,0 @@ -/** - * \file - * - * \brief Default descriptors for a USB Device with a single interface MSC - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi_msc.h" - - -/** - * \defgroup udi_msc_group_single_desc USB device descriptors for a single interface - * - * The following structures provide the USB device descriptors required - * for USB Device with a single interface MSC. - * - * It is ready to use and do not require more definition. - * @{ - */ - -//! Only one interface for this device -#define USB_DEVICE_NB_INTERFACE 1 - -//! USB Device Descriptor -UDC_DATA(4) -UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc = { - .bLength = sizeof(usb_dev_desc_t), - .bDescriptorType = USB_DT_DEVICE, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .idVendor = LE16(USB_DEVICE_VENDOR_ID), - .idProduct = LE16(USB_DEVICE_PRODUCT_ID), - .bcdDevice = LE16((USB_DEVICE_MAJOR_VERSION << 8) - | USB_DEVICE_MINOR_VERSION), -#ifdef USB_DEVICE_MANUFACTURE_NAME - .iManufacturer = 1, -#else - .iManufacturer = 0, // No manufacture string -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - .iProduct = 2, -#else - .iProduct = 0, // No product string -#endif -#ifdef USB_DEVICE_SERIAL_NAME - .iSerialNumber = 3, -#else - .iSerialNumber = 0, // No serial string -#endif - .bNumConfigurations = 1 -}; - - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Qualifier Descriptor for HS -UDC_DATA(4) -UDC_DESC_STORAGE usb_dev_qual_desc_t udc_device_qual = { - .bLength = sizeof(usb_dev_qual_desc_t), - .bDescriptorType = USB_DT_DEVICE_QUALIFIER, - .bcdUSB = LE16(USB_V2_0), - .bDeviceClass = 0, - .bDeviceSubClass = 0, - .bDeviceProtocol = 0, - .bMaxPacketSize0 = USB_DEVICE_EP_CTRL_SIZE, - .bNumConfigurations = 1 -}; -#endif - -//! Structure for USB Device Configuration Descriptor -COMPILER_PACK_SET(1) -typedef struct { - usb_conf_desc_t conf; - udi_msc_desc_t udi_msc; -} udc_desc_t; -COMPILER_PACK_RESET() - -//! USB Device Configuration Descriptor filled for FS -UDC_DATA(4) -UDC_DESC_STORAGE udc_desc_t udc_desc_fs = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), - .udi_msc = UDI_MSC_DESC_FS, -}; - -#ifdef USB_DEVICE_HS_SUPPORT -//! USB Device Configuration Descriptor filled for HS -UDC_DATA(4) -UDC_DESC_STORAGE udc_desc_t udc_desc_hs = { - .conf.bLength = sizeof(usb_conf_desc_t), - .conf.bDescriptorType = USB_DT_CONFIGURATION, - .conf.wTotalLength = LE16(sizeof(udc_desc_t)), - .conf.bNumInterfaces = USB_DEVICE_NB_INTERFACE, - .conf.bConfigurationValue = 1, - .conf.iConfiguration = 0, - .conf.bmAttributes = USB_CONFIG_ATTR_MUST_SET | USB_DEVICE_ATTR, - .conf.bMaxPower = USB_CONFIG_MAX_POWER(USB_DEVICE_POWER), - .udi_msc = UDI_MSC_DESC_HS, -}; -#endif - - -/** - * \name UDC structures which contains all USB Device definitions - */ -//@{ - -//! Associate an UDI for each USB interface -UDC_DESC_STORAGE udi_api_t *udi_apis[USB_DEVICE_NB_INTERFACE] = { - &udi_api_msc, -}; - -//! Add UDI with USB Descriptors FS -UDC_DESC_STORAGE udc_config_speed_t udc_config_lsfs[1] = {{ - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_fs, - .udi_apis = udi_apis, -}}; - -#ifdef USB_DEVICE_HS_SUPPORT -//! Add UDI with USB Descriptors HS -UDC_DESC_STORAGE udc_config_speed_t udc_config_hs[1] = {{ - .desc = (usb_conf_desc_t UDC_DESC_STORAGE*)&udc_desc_hs, - .udi_apis = udi_apis, -}}; -#endif - -//! Add all information about USB Device in global structure for UDC -UDC_DESC_STORAGE udc_config_t udc_config = { - .confdev_lsfs = &udc_device_desc, - .conf_lsfs = udc_config_lsfs, -#ifdef USB_DEVICE_HS_SUPPORT - .confdev_hs = &udc_device_desc, - .qualifier = &udc_device_qual, - .conf_hs = udc_config_hs, -#endif -}; - -//@} -//@} diff --git a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_doc.h b/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_doc.h deleted file mode 100644 index d1c011a92abed..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/device/udi_msc_doc.h +++ /dev/null @@ -1,568 +0,0 @@ -/** - * \file - * - * \brief USB Device Mass Storage Class (MSC) interface definitions. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \defgroup asfdoc_udi_msc_group USB Device Interface (UDI) for Mass Storage Class (MSC) - * - * USB Device Interface (UDI) for Mass Storage Class (MSC) provides an - * interface for the configuration and management of USB MSC storage device. - * - * The outline of this documentation is as follows: - * - \ref asfdoc_udi_msc_api_overview - * - \ref asfdoc_udi_msc_exqsg - * - \ref asfdoc_udi_msc_config_examples - * - * For more details for Atmel® Software Framework (ASF) USB Device Stack, - * refer to following application notes: - * - - * AVR4900: ASF - USB Device Stack - * - - * AVR4920: ASF - USB Device Stack - Compliance and Performance Figures - * - - * AVR4921: ASF - USB Device Stack Differences between ASF V1 and V2 - * - * \section asfdoc_udi_msc_api_overview API Overview - * @{ - */ - -/** - * \name UDI MSC Interface for UDC - * @{ - */ -/** Global structure which contains standard UDI interface for UDC. */ -extern UDC_DESC_STORAGE udi_api_t udi_api_msc; -//@} - -/** - * \name USB Interface Descriptors - * - * The following structures provide predefined USB interface descriptors. - * It must be used to define the final USB descriptors. - */ -//@{ - -/** Interface descriptor structure for MSC. */ -typedef struct { - /** Standard USB interface descriptor structure */ - usb_iface_desc_t iface; - /** Data IN endpoint descriptors */ - usb_ep_desc_t ep_in; - /** Data OUT endpoint descriptors */ - usb_ep_desc_t ep_out; -} udi_msc_desc_t; - -/** By default no string is associated to this interface. */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UDI_MSC_STRING_ID -#define UDI_MSC_STRING_ID 0 -#endif - -/** MSC endpoints size for full speed. */ -#define UDI_MSC_EPS_SIZE_FS 64 -/** MSC endpoints size for high speed. */ -#define UDI_MSC_EPS_SIZE_HS 512 - -/** Content of MSC interface descriptor for all speeds. */ -#define UDI_MSC_DESC \ - .iface.bLength = sizeof(usb_iface_desc_t),\ - .iface.bDescriptorType = USB_DT_INTERFACE,\ - .iface.bInterfaceNumber = UDI_MSC_IFACE_NUMBER,\ - .iface.bAlternateSetting = 0,\ - .iface.bNumEndpoints = 2,\ - .iface.bInterfaceClass = MSC_CLASS,\ - .iface.bInterfaceSubClass = MSC_SUBCLASS_TRANSPARENT,\ - .iface.bInterfaceProtocol = MSC_PROTOCOL_BULK,\ - .iface.iInterface = UDI_MSC_STRING_ID,\ - .ep_in.bLength = sizeof(usb_ep_desc_t),\ - .ep_in.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_in.bEndpointAddress = UDI_MSC_EP_IN,\ - .ep_in.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_in.bInterval = 0,\ - .ep_out.bLength = sizeof(usb_ep_desc_t),\ - .ep_out.bDescriptorType = USB_DT_ENDPOINT,\ - .ep_out.bEndpointAddress = UDI_MSC_EP_OUT,\ - .ep_out.bmAttributes = USB_EP_TYPE_BULK,\ - .ep_out.bInterval = 0, - -/** Content of MSC interface descriptor for full speed only. */ -#define UDI_MSC_DESC_FS {\ - UDI_MSC_DESC \ - .ep_in.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_FS),\ - .ep_out.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_FS),\ - } - -/** Content of MSC interface descriptor for high speed only. */ -#define UDI_MSC_DESC_HS {\ - UDI_MSC_DESC \ - .ep_in.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_HS),\ - .ep_out.wMaxPacketSize = LE16(UDI_MSC_EPS_SIZE_HS),\ - } -//@} - -/** - * \brief Process the background read/write commands - * - * Routine called by the main loop. - */ -bool udi_msc_process_trans(void); - -/** - * \brief Transfers data to/from USB MSC endpoints - * - * - * \param[in] b_read Memory to USB, if true - * \param[inout] block Buffer on Internal RAM to send or fill - * \param[in] block_size Buffer size to send or fill - * \param[in] callback Function to call at the end of transfer. - * If NULL then the routine exit when transfer is finish. - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udi_msc_trans_block(bool b_read, uint8_t * block, iram_size_t block_size, - void (*callback) (udd_ep_status_t status, iram_size_t n, udd_ep_id_t ep)); - -//@} - -/** - * \page asfdoc_udi_msc_exqsg Quick Start Guide for USB Device Mass Storage Module (UDI MSC) - * - * This is the quick start guide for the \ref asfdoc_udi_msc_group - * "USB Device Interface MSC Module (UDI MSC)" with step-by-step instructions on - * how to configure and use the modules in a selection of use cases. - * - * The use cases contain several code fragments. The code fragments in the - * steps for setup can be copied into a custom initialization function, while - * the steps for usage can be copied into, e.g., the main application function. - * - * \section udi_msc_basic_use_case Basic Use Case - * In this basic use case, the "USB MSC (Single Interface Device)" module is used. - * The "USB MSC (Composite Device)" module usage is described in \ref udi_msc_use_cases - * "Advanced Use Cases". - * - * \section udi_msc_basic_use_case_setup Setup Steps - * As a USB device, it follows common USB device setup steps. Refer to - * \ref asfdoc_udc_basic_use_case_setup "USB Device Basic Setup". - * - * The USB MSC interface accesses Memory through Common Abstraction Layer - * (ctrl_access) in ASF. See \ref udi_msc_basic_use_case_setup_ctrl_access. - * - * \subsection udi_msc_basic_use_case_setup_ctrl_access Common Abstraction Layer for Memory Interfaces - * Common abstraction layer (ctrl_access) can provide interfaces between Memory - * and USB. In USB MSC UDI the read/write invokes following ctrl_access - * functions: - * \code - extern Ctrl_status memory_2_usb(U8 lun, U32 addr, U16 nb_sector); - extern Ctrl_status usb_2_memory(U8 lun, U32 addr, U16 nb_sector); - \endcode - * - * Then the ctrl_access dispatch the read/write operation to different Logic Unit Numbers (LUNs). - * - * The memory access in ctrl_access is configured through conf_access.h. - * E.g., to use LUN0 to access virtual memory disk, the configuration should - * include: - * - * \code - #define LUN_0 ENABLE // Enable LUN0 access - //... - - #define VIRTUAL_MEM LUN_0 - #define LUN_ID_VIRTUAL_MEM LUN_ID_0 - #define LUN_0_INCLUDE "virtual_mem.h" // APIs (complied to ctrl_access) - #define Lun_0_test_unit_ready virtual_test_unit_ready // check disk ready - #define Lun_0_read_capacity virtual_read_capacity // get disk size - #define Lun_0_wr_protect virtual_wr_protect // check protection - #define Lun_0_removal virtual_removal // check if disk is removable - #define Lun_0_usb_read_10 virtual_usb_read_10 // Disk to USB transfer - #define Lun_0_usb_write_10 virtual_usb_write_10 // USB to Disk transfer - #define LUN_0_NAME "\"On-Chip Virtual Memory\"" - //... - - #define ACCESS_USB true // USB interface. - //... - - #define GLOBAL_WR_PROTECT false - \endcode - * - * - * Since LUN_0 is defined as a "Virtual Memory", the module to encapsulate the - * internal or on-board memory to access as a disk is included. - * The configuration of such a virtual memory disk is in conf_virtual_mem.h. - * E.g., to use internal RAM to build such a memory disk, the configuration - * should include: - * - * \code - //! Size of Virtual Memory on internal RAM (unit 512B) - #define VMEM_NB_SECTOR 48 //Internal RAM 24KB (should > 20KB or PC can not format it) - \endcode - * - * For more examples of the control access or disk configuration, refer - * to \ref asfdoc_udi_msc_config_examples_5 "conf_access.h" and - * \ref asfdoc_udi_msc_config_examples_6 "conf_virtual_mem.h". - * - * For more Information about Memory Control Access, refer to the online - * document: - * - - * Atmel Software Framework - Memory Control Access - * - * \section udi_msc_basic_use_case_usage Usage Steps - * - * \subsection udi_msc_basic_use_case_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC - #define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' - #define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable() - extern bool my_callback_msc_enable(void); - #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable() - extern void my_callback_msc_disable(void); - #include "udi_msc_conf.h" // At the end of conf_usb.h file - \endcode - * - * Add to application C-file: - * \code - static bool my_flag_autorize_msc_transfert = false; - bool my_callback_msc_enable(void) - { - my_flag_autorize_msc_transfert = true; - return true; - } - void my_callback_msc_disable(void) - { - my_flag_autorize_msc_transfert = false; - } - - void task(void) - { - udi_msc_process_trans(); - } - \endcode - - * - * \subsection udi_msc_basic_use_case_setup_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following configuration, - * which is the USB device MSC configuration: - * \code - #define USB_DEVICE_SERIAL_NAME "12...EF" // Disk SN for MSC - \endcode - * \note The USB serial number is mandatory when a MSC interface is used. - * - * \code - //! Vendor name and Product version of MSC interface - #define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' - #define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - \endcode - * \note The USB MSC interface requires a vendor ID (eight ASCII characters) - * and a product version (four ASCII characters). - * - * \code - #define UDI_MSC_ENABLE_EXT() my_callback_msc_enable() - extern bool my_callback_msc_enable(void); - \endcode - * \note After the device enumeration (detecting and identifying USB devices), - * the USB host starts the device configuration. When the USB MSC interface - * from the device is accepted by the host, the USB host enables this interface and the - * UDI_MSC_ENABLE_EXT() callback function is called and return true. - * Thus, when this event is received, the tasks which call - * udi_msc_process_trans() must be enabled. - * - * \code - #define UDI_MSC_DISABLE_EXT() my_callback_msc_disable() - extern void my_callback_msc_disable(void); - \endcode - * \note When the USB device is unplugged or is reset by the USB host, the USB - * interface is disabled and the UDI_MSC_DISABLE_EXT() callback function - * is called. Thus, it is recommended to disable the task which is called udi_msc_process_trans(). - * - * -# The MSC is automatically linked with memory control access component - * which provides the memories interfaces. However, the memory data transfers - * must be done outside USB interrupt routine. This is done in the MSC process - * ("udi_msc_process_trans()") called by main loop: - * \code - void task(void) { - udi_msc_process_trans(); - } - \endcode - * - * -# The MSC speed depends on task periodicity. To get the best speed - * the notification callback "UDI_MSC_NOTIFY_TRANS_EXT" can be used to wakeup - * this task (Example, through a mutex): - * \code - #define UDI_MSC_NOTIFY_TRANS_EXT() msc_notify_trans() - void msc_notify_trans(void) { - wakeup_my_task(); - } - \endcode - * - * \section udi_msc_use_cases Advanced Use Cases - * \ifnot ASF_MANUAL - * For more advanced use of the UDI MSC module, see the following use cases: - * - \subpage udi_msc_use_case_composite - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - * - \subpage asfdoc_udc_device_cfg - * - \subpage asfdoc_udc_vbus_monitoring - * \else - * For multiple interface use of UDI MSC module, see the following: - * - \subpage udi_msc_use_case_composite - * - * For more advanced use of the UDI CDC module, see the following: - * - \ref asfdoc_udc_use_cases. - * \endif - */ - -/** - * \page udi_msc_use_case_composite MSC in a Composite Device - * - * A USB Composite Device is a USB Device which uses more than one USB class. - * In this use case, the "USB MSC (Composite Device)" module is used to - * create a USB composite device. Thus, this USB module can be associated with - * another "Composite Device" module, like "USB HID Mouse (Composite Device)". - * - * Also, you can refer to application note - * - * AVR4902 ASF - USB Composite Device. - * - * \section udi_msc_use_case_composite_setup Setup Steps - * For the setup code of this use case to work, the - * \ref udi_msc_basic_use_case "Basic Use Case" must be followed. - * - * \section udi_msc_use_case_composite_usage Usage Steps - * - * \subsection udi_msc_use_case_composite_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_EP_CTRL_SIZE 64 - #define USB_DEVICE_NB_INTERFACE (X+1) - #define USB_DEVICE_MAX_EP (X+2) - - #define UDI_MSC_EP_IN (X | USB_EP_DIR_IN) - #define UDI_MSC_EP_OUT (Y | USB_EP_DIR_OUT) - #define UDI_MSC_IFACE_NUMBER X - - #define UDI_COMPOSITE_DESC_T \ - udi_msc_desc_t udi_msc; \ - ... - #define UDI_COMPOSITE_DESC_FS \ - .udi_msc = UDI_MSC_DESC, \ - ... - #define UDI_COMPOSITE_DESC_HS \ - .udi_msc = UDI_MSC_DESC, \ - ... - #define UDI_COMPOSITE_API \ - &udi_api_msc, \ - ... - \endcode - * - * \subsection udi_msc_use_case_composite_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB composite device configuration: - * \code - // Endpoint control size, This must be: - // - 8, 16, 32 or 64 for full speed device (8 is recommended to save RAM) - // - 64 for a high speed device - #define USB_DEVICE_EP_CTRL_SIZE 64 - // Total Number of interfaces on this USB device. - // Add 1 for MSC. - #define USB_DEVICE_NB_INTERFACE (X+1) - // Total number of endpoints on this USB device. - // This must include each endpoint for each interface. - // Add 2 for MSC. - #define USB_DEVICE_MAX_EP (X+2) - \endcode - * - * -# Ensure that conf_usb.h contains the description of - * composite device: - * \code - // The endpoint numbers chosen by you for the MSC. - // The endpoint numbers starting from 1. - #define UDI_MSC_EP_IN (X | USB_EP_DIR_IN) - #define UDI_MSC_EP_OUT (Y | USB_EP_DIR_OUT) - // The interface index of an interface starting from 0 - #define UDI_MSC_IFACE_NUMBER X - \endcode - * - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB composite device configuration: - * \code - // USB Interfaces descriptor structure - #define UDI_COMPOSITE_DESC_T \ - ... - udi_msc_desc_t udi_msc; \ - ... - // USB Interfaces descriptor value for Full Speed - #define UDI_COMPOSITE_DESC_FS \ - ... - .udi_msc = UDI_MSC_DESC_FS, \ - ... - // USB Interfaces descriptor value for High Speed - #define UDI_COMPOSITE_DESC_HS \ - ... - .udi_msc = UDI_MSC_DESC_HS, \ - ... - // USB Interface APIs - #define UDI_COMPOSITE_API \ - ... - &udi_api_msc, \ - ... - \endcode - * \note The descriptors order given in the four lists above must be the - * same as the order defined by all interface indexes. The interface index - * orders are defined through UDI_X_IFACE_NUMBER defines. - */ - -/** - * \page asfdoc_udi_msc_config_examples Configuration File Examples - * - * \section asfdoc_udi_msc_config_examples_1 conf_usb.h - * \subsection asfdoc_udi_msc_config_examples_1_1 UDI MSC Single - * \include module_config/conf_usb.h - * \subsection asfdoc_udi_msc_config_examples_1_2 UDI MSC Multiple (Composite) - * \include composite/device/module_config/conf_usb.h - * - * \section asfdoc_udi_msc_config_examples_2 conf_clock.h - * - * \subsection asfdoc_udi_msc_config_examples_2_1 XMEGA (USB) - * \include example/atxmega128b1_xmega_b1_xplained/conf_clock.h - * - * \subsection asfdoc_udi_msc_config_examples_2_2 AT32UC3A0, AT32UC3A1, and AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_clock.h - * - * \subsection asfdoc_udi_msc_config_examples_2_3 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_clock.h - * - * \subsection asfdoc_udi_msc_config_examples_2_4 AT32UC3C, ATUCXXD, ATUCXXL3U, and ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_clock.h - * - * \subsection asfdoc_udi_msc_config_examples_2_5 SAM3S, SAM3SD, and SAM4S Devices (UPD: USB Peripheral Device) - * \include example/sam3s4c_sam3s_ek/conf_clock.h - * - * \subsection asfdoc_udi_msc_config_examples_2_6 SAM3U Device (UPDHS: USB Peripheral Device High Speed) - * \include example/sam3u4e_sam3u_ek/conf_clock.h - * - * \subsection asfdoc_udi_msc_config_examples_2_7 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_clock.h - * - * \section asfdoc_udi_msc_config_examples_3 conf_clocks.h - * - * \subsection asfdoc_udi_msc_config_examples_3_1 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_clocks.h - * - * \section asfdoc_udi_msc_config_examples_4 conf_board.h - * - * \subsection asfdoc_udi_msc_config_examples_4_1 AT32UC3A0, AT32UC3A1, and AT32UC3B Devices (USBB) - * \include example/at32uc3a0512_evk1100/conf_board.h - * - * \subsection asfdoc_udi_msc_config_examples_4_2 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * \include example/at32uc3a3256_evk1104/conf_board.h - * - * \subsection asfdoc_udi_msc_config_examples_4_3 AT32UC3C, ATUCXXD, ATUCXXL3U, and ATUCXXL4U Devices (USBC) - * \include example/at32uc3c0512c_uc3c_ek/conf_board.h - * - * \subsection asfdoc_udi_msc_config_examples_4_4 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * \include example/sam3x8h_sam3x_ek/conf_board.h - * - * \subsection asfdoc_udi_msc_config_examples_4_5 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_board.h - * - * \section asfdoc_udi_msc_config_examples_5 conf_access.h - * - * \subsection asfdoc_udi_msc_config_examples_5_1 AT32UC3A0, AT32UC3A1, and AT32UC3B Devices (USBB) - * On EVK1100, the AT45DBx and one SD/MMC are for MSC. - * \include example/at32uc3a0512_evk1100/conf_access.h - * - * \subsection asfdoc_udi_msc_config_examples_5_2 AT32UC3A3 and AT32UC3A4 Devices (USBB with High Speed Support) - * On EVK1104, the AT45DBx and two SD/MMC slots are for MSC. - * \include example/at32uc3a3256_evk1104/conf_access.h - * - * \subsection asfdoc_udi_msc_config_examples_5_3 AT32UC3C, ATUCXXD, ATUCXXL3U, and ATUCXXL4U Devices (USBC) - * On EVK1100, the AT45DBx and one SD/MMC are for MSC. - * \include example/at32uc3c0512c_uc3c_ek/conf_access.h - * - * \subsection asfdoc_udi_msc_config_examples_5_4 SAM3X and SAM3A Devices (UOTGHS: USB OTG High Speed) - * On SAM3X-EK, the SD/MMC and on-board nand are for MSC. - * \include example/sam3x8h_sam3x_ek/conf_access.h - * - * \subsection asfdoc_udi_msc_config_examples_5_5 SAM D21 Device (USB) - * \include example/samd21j18a_samd21_xplained_pro/conf_access.h - * - * \section asfdoc_udi_msc_config_examples_6 conf_virtual_mem.h - * - * \subsection asfdoc_udi_msc_config_examples_6_1 On-chip Virtual Memory Disk - * \include example/samd21j18a_samd21_xplained_pro/conf_virtual_mem.h - * - * \subsection asfdoc_udi_msc_config_examples_6_2 On-board Virtual Memory Disk - * \include example/sam3u4e_sam3u_ek/conf_virtual_mem.h - */ - -/** - * \page asfdoc_udi_msc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42343B12/2015Fixed typos
42343A12/2014Initial release
- */ - diff --git a/atmel-samd/asf/common/services/usb/class/msc/doxygen/common.services.usb.class.msc.protocol/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/class/msc/doxygen/common.services.usb.class.msc.protocol/doxyfile.doxygen deleted file mode 100644 index 4758627251be3..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/doxygen/common.services.usb.class.msc.protocol/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../sbc_protocol.h ../../spc_protocol.h ../../usb_protocol_msc.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. 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This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/class/msc/doxygen/common.services.usb.class.msc.protocol/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/class/msc/doxygen/common.services.usb.class.msc.protocol/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/doxygen/common.services.usb.class.msc.protocol/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
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- * - * \section main_licence License - *
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- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/class/msc/sbc_protocol.h b/atmel-samd/asf/common/services/usb/class/msc/sbc_protocol.h deleted file mode 100644 index 082b735fa6197..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/sbc_protocol.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - * \file - * - * \brief SCSI Block Commands - * - * This file contains definitions of some of the commands found in the - * SCSI SBC-2 standard. - * - * Note that the SBC specification depends on several commands defined - * by the SCSI Primary Commands (SPC) standard. Each version of the SBC - * standard is meant to be used in conjunction with a specific version - * of the SPC standard, as follows: - * - SBC depends on SPC - * - SBC-2 depends on SPC-3 - * - SBC-3 depends on SPC-4 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _SBC_PROTOCOL_H_ -#define _SBC_PROTOCOL_H_ - - -/** - * \ingroup usb_msc_protocol - * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions - * - * @{ - */ - -//! \name SCSI commands defined by SBC-2 -//@{ -#define SBC_FORMAT_UNIT 0x04 -#define SBC_READ6 0x08 -#define SBC_WRITE6 0x0A -#define SBC_START_STOP_UNIT 0x1B -#define SBC_READ_CAPACITY10 0x25 -#define SBC_READ10 0x28 -#define SBC_WRITE10 0x2A -#define SBC_VERIFY10 0x2F -//@} - -//! \name SBC-2 Mode page definitions -//@{ - -enum scsi_sbc_mode { - SCSI_MS_MODE_RW_ERR_RECOV = 0x01, //!< Read-Write Error Recovery mode page - SCSI_MS_MODE_FORMAT_DEVICE = 0x03, //!< Format Device mode page - SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, //!< Flexible Disk mode page - SCSI_MS_MODE_CACHING = 0x08, //!< Caching mode page -}; - - -//! \name SBC-2 Device-Specific Parameter -//@{ -#define SCSI_MS_SBC_WP 0x80 //!< Write Protected -#define SCSI_MS_SBC_DPOFUA 0x10 //!< DPO and FUA supported -//@} - -/** - * \brief SBC-2 Short LBA mode parameter block descriptor - */ -struct sbc_slba_block_desc { - be32_t nr_blocks; //!< Number of Blocks - be32_t block_len; //!< Block Length -#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU //!< Mask reserved bits -}; - -/** - * \brief SBC-2 Caching mode page - */ -struct sbc_caching_mode_page { - uint8_t page_code; - uint8_t page_length; - uint8_t flags2; -#define SBC_MP_CACHE_IC (1 << 7) //!< Initiator Control -#define SBC_MP_CACHE_ABPF (1 << 6) //!< Abort Pre-Fetch -#define SBC_MP_CACHE_CAP (1 << 5) //!< Catching Analysis Permitted -#define SBC_MP_CACHE_DISC (1 << 4) //!< Discontinuity -#define SBC_MP_CACHE_SIZE (1 << 3) //!< Size enable -#define SBC_MP_CACHE_WCE (1 << 2) //!< Write back Cache Enable -#define SBC_MP_CACHE_MF (1 << 1) //!< Multiplication Factor -#define SBC_MP_CACHE_RCD (1 << 0) //!< Read Cache Disable - uint8_t retention; - be16_t dis_pf_transfer_len; - be16_t min_prefetch; - be16_t max_prefetch; - be16_t max_prefetch_ceil; - uint8_t flags12; -#define SBC_MP_CACHE_FSW (1 << 7) //!< Force Sequential Write -#define SBC_MP_CACHE_LBCSS (1 << 6) //!< Logical Blk Cache Seg Sz -#define SBC_MP_CACHE_DRA (1 << 5) //!< Disable Read-Ahead -#define SBC_MP_CACHE_NV_DIS (1 << 0) //!< Non-Volatile Cache Disable - uint8_t nr_cache_segments; - be16_t cache_segment_size; - uint8_t reserved[4]; -}; - -/** - * \brief SBC-2 Read-Write Error Recovery mode page - */ -struct sbc_rdwr_error_recovery_mode_page { - uint8_t page_code; - uint8_t page_length; -#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A - uint8_t flags1; -#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7) -#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6) -#define SBC_MP_RW_ERR_RECOV_TB (1 << 5) -#define SBC_MP_RW_ERR_RECOV_RC (1 << 4) -#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3) -#define SBC_MP_RW_ERR_RECOV_PER (1 << 2) -#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1) -#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0) - uint8_t read_retry_count; - uint8_t correction_span; - uint8_t head_offset_count; - uint8_t data_strobe_offset_count; - uint8_t flags2; - uint8_t write_retry_count; - uint8_t flags3; - be16_t recovery_time_limit; -}; -//@} - -/** - * \brief SBC-2 READ CAPACITY (10) parameter data - */ -struct sbc_read_capacity10_data { - be32_t max_lba; //!< LBA of last logical block - be32_t block_len; //!< Number of bytes in the last logical block -}; - -//@} - -#endif // _SBC_PROTOCOL_H_ diff --git a/atmel-samd/asf/common/services/usb/class/msc/spc_protocol.h b/atmel-samd/asf/common/services/usb/class/msc/spc_protocol.h deleted file mode 100644 index 84c4dd50a9018..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/spc_protocol.h +++ /dev/null @@ -1,337 +0,0 @@ -/** - * \file - * - * \brief SCSI Primary Commands - * - * This file contains definitions of some of the commands found in the - * SPC-2 standard. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _SPC_PROTOCOL_H_ -#define _SPC_PROTOCOL_H_ - - -/** - * \ingroup usb_msc_protocol - * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions - * - * @{ - */ - -//! \name SCSI commands defined by SPC-2 -//@{ -#define SPC_TEST_UNIT_READY 0x00 -#define SPC_REQUEST_SENSE 0x03 -#define SPC_INQUIRY 0x12 -#define SPC_MODE_SELECT6 0x15 -#define SPC_MODE_SENSE6 0x1A -#define SPC_SEND_DIAGNOSTIC 0x1D -#define SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -#define SPC_MODE_SENSE10 0x5A -#define SPC_REPORT_LUNS 0xA0 -//@} - -//! \brief May be set in byte 0 of the INQUIRY CDB -//@{ -//! Enable Vital Product Data -#define SCSI_INQ_REQ_EVPD 0x01 -//! Command Support Data specified by the PAGE OR OPERATION CODE field -#define SCSI_INQ_REQ_CMDT 0x02 -//@} - -COMPILER_PACK_SET(1) - -/** - * \brief SCSI Standard Inquiry data structure - */ -struct scsi_inquiry_data { - uint8_t pq_pdt; //!< Peripheral Qual / Peripheral Dev Type -#define SCSI_INQ_PQ_CONNECTED 0x00 //!< Peripheral connected -#define SCSI_INQ_PQ_NOT_CONN 0x20 //!< Peripheral not connected -#define SCSI_INQ_PQ_NOT_SUPP 0x60 //!< Peripheral not supported -#define SCSI_INQ_DT_DIR_ACCESS 0x00 //!< Direct Access (SBC) -#define SCSI_INQ_DT_SEQ_ACCESS 0x01 //!< Sequential Access -#define SCSI_INQ_DT_PRINTER 0x02 //!< Printer -#define SCSI_INQ_DT_PROCESSOR 0x03 //!< Processor device -#define SCSI_INQ_DT_WRITE_ONCE 0x04 //!< Write-once device -#define SCSI_INQ_DT_CD_DVD 0x05 //!< CD/DVD device -#define SCSI_INQ_DT_OPTICAL 0x07 //!< Optical Memory -#define SCSI_INQ_DT_MC 0x08 //!< Medium Changer -#define SCSI_INQ_DT_ARRAY 0x0c //!< Storage Array Controller -#define SCSI_INQ_DT_ENCLOSURE 0x0d //!< Enclosure Services -#define SCSI_INQ_DT_RBC 0x0e //!< Simplified Direct Access -#define SCSI_INQ_DT_OCRW 0x0f //!< Optical card reader/writer -#define SCSI_INQ_DT_BCC 0x10 //!< Bridge Controller Commands -#define SCSI_INQ_DT_OSD 0x11 //!< Object-based Storage -#define SCSI_INQ_DT_NONE 0x1f //!< No Peripheral - uint8_t flags1; //!< Flags (byte 1) -#define SCSI_INQ_RMB 0x80 //!< Removable Medium - uint8_t version; //!< Version -#define SCSI_INQ_VER_NONE 0x00 //!< No standards conformance -#define SCSI_INQ_VER_SPC 0x03 //!< SCSI Primary Commands (link to SBC) -#define SCSI_INQ_VER_SPC2 0x04 //!< SCSI Primary Commands - 2 (link to SBC-2) -#define SCSI_INQ_VER_SPC3 0x05 //!< SCSI Primary Commands - 3 (link to SBC-2) -#define SCSI_INQ_VER_SPC4 0x06 //!< SCSI Primary Commands - 4 (link to SBC-3) - uint8_t flags3; //!< Flags (byte 3) -#define SCSI_INQ_NORMACA 0x20 //!< Normal ACA Supported -#define SCSI_INQ_HISUP 0x10 //!< Hierarchal LUN addressing -#define SCSI_INQ_RSP_SPC2 0x02 //!< SPC-2 / SPC-3 response format - uint8_t addl_len; //!< Additional Length (n-4) -#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) //!< Total length is \a tot - uint8_t flags5; //!< Flags (byte 5) -#define SCSI_INQ_SCCS 0x80 - uint8_t flags6; //!< Flags (byte 6) -#define SCSI_INQ_BQUE 0x80 -#define SCSI_INQ_ENCSERV 0x40 -#define SCSI_INQ_MULTIP 0x10 -#define SCSI_INQ_MCHGR 0x08 -#define SCSI_INQ_ADDR16 0x01 - uint8_t flags7; //!< Flags (byte 7) -#define SCSI_INQ_WBUS16 0x20 -#define SCSI_INQ_SYNC 0x10 -#define SCSI_INQ_LINKED 0x08 -#define SCSI_INQ_CMDQUE 0x02 - uint8_t vendor_id[8]; //!< T10 Vendor Identification - uint8_t product_id[16]; //!< Product Identification - uint8_t product_rev[4]; //!< Product Revision Level -}; - -/** - * \brief SCSI Standard Request sense data structure - */ -struct scsi_request_sense_data { - /* 1st byte: REQUEST SENSE response flags*/ - uint8_t valid_reponse_code; -#define SCSI_SENSE_VALID 0x80 //!< Indicates the INFORMATION field contains valid information -#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F -#define SCSI_SENSE_CURRENT 0x70 //!< Response code 70h (current errors) -#define SCSI_SENSE_DEFERRED 0x71 - - /* 2nd byte */ - uint8_t obsolete; - - /* 3rd byte */ - uint8_t sense_flag_key; -#define SCSI_SENSE_FILEMARK 0x80 //!< Indicates that the current command has read a filemark or setmark. -#define SCSI_SENSE_EOM 0x40 //!< Indicates that an end-of-medium condition exists. -#define SCSI_SENSE_ILI 0x20 //!< Indicates that the requested logical block length did not match the logical block length of the data on the medium. -#define SCSI_SENSE_RESERVED 0x10 //!< Reserved -#define SCSI_SENSE_KEY(x) (x&0x0F) //!< Sense Key - - /* 4th to 7th bytes - INFORMATION field */ - uint8_t information[4]; - - /* 8th byte - ADDITIONAL SENSE LENGTH field */ - uint8_t AddSenseLen; -#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len) - 8) - - /* 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */ - uint8_t CmdSpecINFO[4]; - - /* 13th byte - ADDITIONAL SENSE CODE field */ - uint8_t AddSenseCode; - - /* 14th byte - ADDITIONAL SENSE CODE QUALIFIER field */ - uint8_t AddSnsCodeQlfr; - - /* 15th byte - FIELD REPLACEABLE UNIT CODE field */ - uint8_t FldReplUnitCode; - - /* 16th byte */ - uint8_t SenseKeySpec[3]; -#define SCSI_SENSE_SKSV 0x80 //!< Indicates the SENSE-KEY SPECIFIC field contains valid information -}; - -COMPILER_PACK_RESET() - -/* Vital Product Data page codes */ -enum scsi_vpd_page_code { - SCSI_VPD_SUPPORTED_PAGES = 0x00, - SCSI_VPD_UNIT_SERIAL_NUMBER = 0x80, - SCSI_VPD_DEVICE_IDENTIFICATION = 0x83, -}; -#define SCSI_VPD_HEADER_SIZE 4 - -/* Constants associated with the Device Identification VPD page */ -#define SCSI_VPD_ID_HEADER_SIZE 4 - -#define SCSI_VPD_CODE_SET_BINARY 1 -#define SCSI_VPD_CODE_SET_ASCII 2 -#define SCSI_VPD_CODE_SET_UTF8 3 - -#define SCSI_VPD_ID_TYPE_T10 1 - - -/* Sense keys */ -enum scsi_sense_key { - SCSI_SK_NO_SENSE = 0x0, - SCSI_SK_RECOVERED_ERROR = 0x1, - SCSI_SK_NOT_READY = 0x2, - SCSI_SK_MEDIUM_ERROR = 0x3, - SCSI_SK_HARDWARE_ERROR = 0x4, - SCSI_SK_ILLEGAL_REQUEST = 0x5, - SCSI_SK_UNIT_ATTENTION = 0x6, - SCSI_SK_DATA_PROTECT = 0x7, - SCSI_SK_BLANK_CHECK = 0x8, - SCSI_SK_VENDOR_SPECIFIC = 0x9, - SCSI_SK_COPY_ABORTED = 0xa, - SCSI_SK_ABORTED_COMMAND = 0xb, - SCSI_SK_VOLUME_OVERFLOW = 0xd, - SCSI_SK_MISCOMPARE = 0xe, -}; - -/* Additional Sense Code / Additional Sense Code Qualifier pairs */ -enum scsi_asc_ascq { - SCSI_ASC_NO_ADDITIONAL_SENSE_INFO = 0x0000, - SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405, - SCSI_ASC_WRITE_ERROR = 0x0c00, - SCSI_ASC_UNRECOVERED_READ_ERROR = 0x1100, - SCSI_ASC_INVALID_COMMAND_OPERATION_CODE = 0x2000, - SCSI_ASC_INVALID_FIELD_IN_CDB = 0x2400, - SCSI_ASC_WRITE_PROTECTED = 0x2700, - SCSI_ASC_NOT_READY_TO_READY_CHANGE = 0x2800, - SCSI_ASC_MEDIUM_NOT_PRESENT = 0x3A00, - SCSI_ASC_INTERNAL_TARGET_FAILURE = 0x4400, -}; - -/** - * \brief SPC-2 Mode parameter - * This subclause describes the block descriptors and the pages - * used with MODE SELECT and MODE SENSE commands - * that are applicable to all SCSI devices. - */ -enum scsi_spc_mode { - SCSI_MS_MODE_VENDOR_SPEC = 0x00, - SCSI_MS_MODE_INFEXP = 0x1C, // Informational exceptions control page - SCSI_MS_MODE_ALL = 0x3f, -}; - -/** - * \brief SPC-2 Informational exceptions control page - * See chapter 8.3.8 - */ -struct spc_control_page_info_execpt { - uint8_t page_code; - uint8_t page_length; -#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A - uint8_t flags1; -#define SPC_MP_INFEXP_PERF (1<<7) //!< Initiator Control -#define SPC_MP_INFEXP_EBF (1<<5) //!< Caching Analysis Permitted -#define SPC_MP_INFEXP_EWASC (1<<4) //!< Discontinuity -#define SPC_MP_INFEXP_DEXCPT (1<<3) //!< Size enable -#define SPC_MP_INFEXP_TEST (1<<2) //!< Writeback Cache Enable -#define SPC_MP_INFEXP_LOGERR (1<<0) //!< Log errors bit - uint8_t mrie; -#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00 -#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01 -#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02 -#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03 -#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04 -#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05 -#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06 - be32_t interval_timer; - be32_t report_count; -}; - - -enum scsi_spc_mode_sense_pc { - SCSI_MS_SENSE_PC_CURRENT = 0, - SCSI_MS_SENSE_PC_CHANGEABLE = 1, - SCSI_MS_SENSE_PC_DEFAULT = 2, - SCSI_MS_SENSE_PC_SAVED = 3, -}; - - - -static inline bool scsi_mode_sense_dbd_is_set(const uint8_t * cdb) -{ - return (cdb[1] >> 3) & 1; -} - -static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t * cdb) -{ - return cdb[2] & 0x3f; -} - -static inline uint8_t scsi_mode_sense_get_pc(const uint8_t * cdb) -{ - return cdb[2] >> 6; -} - -/** - * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE - * SENSE(6) - */ -struct scsi_mode_param_header6 { - uint8_t mode_data_length; //!< Number of bytes after this - uint8_t medium_type; //!< Medium Type - uint8_t device_specific_parameter; //!< Defined by command set - uint8_t block_descriptor_length; //!< Length of block descriptors -}; - -/** - * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE - * SENSE(10) - */ -struct scsi_mode_param_header10 { - be16_t mode_data_length; //!< Number of bytes after this - uint8_t medium_type; //!< Medium Type - uint8_t device_specific_parameter; //!< Defined by command set - uint8_t flags4; //!< LONGLBA in bit 0 - uint8_t reserved; - be16_t block_descriptor_length; //!< Length of block descriptors -}; - -/** - * \brief SCSI Page_0 Mode Page header (SPF not set) - */ -struct scsi_mode_page_0_header { - uint8_t page_code; -#define SCSI_PAGE_CODE_PS (1 << 7) //!< Parameters Saveable -#define SCSI_PAGE_CODE_SPF (1 << 6) //!< SubPage Format - uint8_t page_length; //!< Number of bytes after this -#define SCSI_MS_PAGE_LEN(total) ((total) - 2) -}; - -//@} - -#endif // SPC_PROTOCOL_H_ diff --git a/atmel-samd/asf/common/services/usb/class/msc/usb_protocol_msc.h b/atmel-samd/asf/common/services/usb/class/msc/usb_protocol_msc.h deleted file mode 100644 index d5312328f2617..0000000000000 --- a/atmel-samd/asf/common/services/usb/class/msc/usb_protocol_msc.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief USB Mass Storage Class (MSC) protocol definitions. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_PROTOCOL_MSC_H_ -#define _USB_PROTOCOL_MSC_H_ - - -/** - * \ingroup usb_protocol_group - * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions - * - * @{ - */ - -/** - * \name Possible Class value - */ -//@{ -#define MSC_CLASS 0x08 -//@} - -/** - * \name Possible SubClass value - * \note In practise, most devices should use - * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in - * the standard INQUIRY data block, even if the MSC spec indicates - * otherwise. In particular, RBC is not supported by certain major - * operating systems like Windows XP. - */ -//@{ -#define MSC_SUBCLASS_RBC 0x01 //!< Reduced Block Commands -#define MSC_SUBCLASS_ATAPI 0x02 //!< CD/DVD devices -#define MSC_SUBCLASS_QIC_157 0x03 //!< Tape devices -#define MSC_SUBCLASS_UFI 0x04 //!< Floppy disk drives -#define MSC_SUBCLASS_SFF_8070I 0x05 //!< Floppy disk drives -#define MSC_SUBCLASS_TRANSPARENT 0x06 //!< Determined by INQUIRY -//@} - -/** - * \name Possible protocol value - * \note Only the BULK protocol should be used in new designs. - */ -//@{ -#define MSC_PROTOCOL_CBI 0x00 //!< Command/Bulk/Interrupt -#define MSC_PROTOCOL_CBI_ALT 0x01 //!< W/o command completion -#define MSC_PROTOCOL_BULK 0x50 //!< Bulk-only -//@} - - -/** - * \brief MSC USB requests (bRequest) - */ -enum usb_reqid_msc { - USB_REQ_MSC_BULK_RESET = 0xFF, //!< Mass Storage Reset - USB_REQ_MSC_GET_MAX_LUN = 0xFE, //!< Get Max LUN -}; - - -COMPILER_PACK_SET(1) - -/** - * \name A Command Block Wrapper (CBW). - */ -//@{ -struct usb_msc_cbw { - le32_t dCBWSignature; //!< Must contain 'USBC' - le32_t dCBWTag; //!< Unique command ID - le32_t dCBWDataTransferLength; //!< Number of bytes to transfer - uint8_t bmCBWFlags; //!< Direction in bit 7 - uint8_t bCBWLUN; //!< Logical Unit Number - uint8_t bCBWCBLength; //!< Number of valid CDB bytes - uint8_t CDB[16]; //!< SCSI Command Descriptor Block -}; - -#define USB_CBW_SIGNATURE 0x55534243 //!< dCBWSignature value -#define USB_CBW_DIRECTION_IN (1<<7) //!< Data from device to host -#define USB_CBW_DIRECTION_OUT (0<<7) //!< Data from host to device -#define USB_CBW_LUN_MASK 0x0F //!< Valid bits in bCBWLUN -#define USB_CBW_LEN_MASK 0x1F //!< Valid bits in bCBWCBLength -//@} - - -/** - * \name A Command Status Wrapper (CSW). - */ -//@{ -struct usb_msc_csw { - le32_t dCSWSignature; //!< Must contain 'USBS' - le32_t dCSWTag; //!< Same as dCBWTag - le32_t dCSWDataResidue; //!< Number of bytes not transfered - uint8_t bCSWStatus; //!< Status code -}; - -#define USB_CSW_SIGNATURE 0x55534253 //!< dCSWSignature value -#define USB_CSW_STATUS_PASS 0x00 //!< Command Passed -#define USB_CSW_STATUS_FAIL 0x01 //!< Command Failed -#define USB_CSW_STATUS_PE 0x02 //!< Phase Error -//@} - -COMPILER_PACK_RESET() - -//@} - -#endif // _USB_PROTOCOL_MSC_H_ diff --git a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device.dfu_optimization/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device.dfu_optimization/doxyfile.doxygen deleted file mode 100644 index 5386f2c0be4ba..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device.dfu_optimization/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../udc_dfu_small.c ../../udc.h ../../udc_desc.h ../../udd.h ../../udi.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device.dfu_optimization/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device.dfu_optimization/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device.dfu_optimization/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device/doxyfile.doxygen b/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device/doxyfile.doxygen deleted file mode 100644 index 5daee4490ece6..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device Stack Core (Common API)" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../udc.c ../../udc.h ../../udc_desc.h ../../udd.h ../../udi.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. 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When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. 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This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device/doxygen_module_mainpage.h b/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/doxygen/common.services.usb.device/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
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  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/services/usb/udc/udc.c b/atmel-samd/asf/common/services/usb/udc/udc.c deleted file mode 100644 index a48b86bd3a7f6..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/udc.c +++ /dev/null @@ -1,1145 +0,0 @@ -/** - * \file - * - * \brief USB Device Controller (UDC) - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi.h" -#include "udc.h" - -/** - * \ingroup udc_group - * \defgroup udc_group_interne Implementation of UDC - * - * Internal implementation - * @{ - */ - -//! \name Internal variables to manage the USB device -//! @{ - -//! Device status state (see enum usb_device_status in usb_protocol.h) -static le16_t udc_device_status; - -COMPILER_WORD_ALIGNED -//! Device interface setting value -static uint8_t udc_iface_setting = 0; - -//! Device Configuration number selected by the USB host -COMPILER_WORD_ALIGNED -static uint8_t udc_num_configuration = 0; - -//! Pointer on the selected speed device configuration -static udc_config_speed_t UDC_DESC_STORAGE *udc_ptr_conf; - -//! Pointer on interface descriptor used by SETUP request. -static usb_iface_desc_t UDC_DESC_STORAGE *udc_ptr_iface; - -//! @} - - -//! \name Internal structure to store the USB device main strings -//! @{ - -/** - * \brief Language ID of USB device (US ID by default) - */ -COMPILER_WORD_ALIGNED -static UDC_DESC_STORAGE usb_str_lgid_desc_t udc_string_desc_languageid = { - .desc.bLength = sizeof(usb_str_lgid_desc_t), - .desc.bDescriptorType = USB_DT_STRING, - .string = {LE16(USB_LANGID_EN_US)} -}; - -/** - * \brief USB device manufacture name storage - * String is allocated only if USB_DEVICE_MANUFACTURE_NAME is declared - * by usb application configuration - */ -#ifdef USB_DEVICE_MANUFACTURE_NAME -static uint8_t udc_string_manufacturer_name[] = USB_DEVICE_MANUFACTURE_NAME; -# define USB_DEVICE_MANUFACTURE_NAME_SIZE \ - (sizeof(udc_string_manufacturer_name)-1) -#else -# define USB_DEVICE_MANUFACTURE_NAME_SIZE 0 -#endif - -/** - * \brief USB device product name storage - * String is allocated only if USB_DEVICE_PRODUCT_NAME is declared - * by usb application configuration - */ -#ifdef USB_DEVICE_PRODUCT_NAME -static uint8_t udc_string_product_name[] = USB_DEVICE_PRODUCT_NAME; -# define USB_DEVICE_PRODUCT_NAME_SIZE (sizeof(udc_string_product_name)-1) -#else -# define USB_DEVICE_PRODUCT_NAME_SIZE 0 -#endif - -/** - * \brief Get USB device serial number - * - * Use the define USB_DEVICE_SERIAL_NAME to set static serial number. - * - * For dynamic serial number set the define USB_DEVICE_GET_SERIAL_NAME_POINTER - * to a suitable pointer. This will also require the serial number length - * define USB_DEVICE_GET_SERIAL_NAME_LENGTH. - */ -#if defined USB_DEVICE_GET_SERIAL_NAME_POINTER - static const uint8_t *udc_get_string_serial_name(void) - { - return (const uint8_t *)USB_DEVICE_GET_SERIAL_NAME_POINTER; - } -# define USB_DEVICE_SERIAL_NAME_SIZE \ - USB_DEVICE_GET_SERIAL_NAME_LENGTH -#elif defined USB_DEVICE_SERIAL_NAME - static const uint8_t *udc_get_string_serial_name(void) - { - return (const uint8_t *)USB_DEVICE_SERIAL_NAME; - } -# define USB_DEVICE_SERIAL_NAME_SIZE \ - (sizeof(USB_DEVICE_SERIAL_NAME)-1) -#else -# define USB_DEVICE_SERIAL_NAME_SIZE 0 -#endif - -/** - * \brief USB device string descriptor - * Structure used to transfer ASCII strings to USB String descriptor structure. - */ -struct udc_string_desc_t { - usb_str_desc_t header; - le16_t string[Max(Max(USB_DEVICE_MANUFACTURE_NAME_SIZE, \ - USB_DEVICE_PRODUCT_NAME_SIZE), USB_DEVICE_SERIAL_NAME_SIZE)]; -}; -COMPILER_WORD_ALIGNED -static UDC_DESC_STORAGE struct udc_string_desc_t udc_string_desc = { - .header.bDescriptorType = USB_DT_STRING -}; -//! @} - -usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void) -{ - return udc_ptr_iface; -} - -/** - * \brief Returns a value to check the end of USB Configuration descriptor - * - * \return address after the last byte of USB Configuration descriptor - */ -static usb_conf_desc_t UDC_DESC_STORAGE *udc_get_eof_conf(void) -{ - return (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) - udc_ptr_conf->desc + - le16_to_cpu(udc_ptr_conf->desc->wTotalLength)); -} - -#if (0!=USB_DEVICE_MAX_EP) -/** - * \brief Search specific descriptor in global interface descriptor - * - * \param desc Address of interface descriptor - * or previous specific descriptor found - * \param desc_id Descriptor ID to search - * - * \return address of specific descriptor found - * \return NULL if it is the end of global interface descriptor - */ -static usb_conf_desc_t UDC_DESC_STORAGE *udc_next_desc_in_iface(usb_conf_desc_t - UDC_DESC_STORAGE * desc, uint8_t desc_id) -{ - usb_conf_desc_t UDC_DESC_STORAGE *ptr_eof_desc; - - ptr_eof_desc = udc_get_eof_conf(); - // Go to next descriptor - desc = (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) desc + - desc->bLength); - // Check the end of configuration descriptor - while (ptr_eof_desc > desc) { - // If new interface descriptor is found, - // then it is the end of the current global interface descriptor - if (USB_DT_INTERFACE == desc->bDescriptorType) { - break; // End of global interface descriptor - } - if (desc_id == desc->bDescriptorType) { - return desc; // Specific descriptor found - } - // Go to next descriptor - desc = (UDC_DESC_STORAGE usb_conf_desc_t *) ((uint8_t *) desc + - desc->bLength); - } - return NULL; // No specific descriptor found -} -#endif - -/** - * \brief Search an interface descriptor - * This routine updates the internal pointer udc_ptr_iface. - * - * \param iface_num Interface number to find in Configuration Descriptor - * \param setting_num Setting number of interface to find - * - * \return 1 if found or 0 if not found - */ -static bool udc_update_iface_desc(uint8_t iface_num, uint8_t setting_num) -{ - usb_conf_desc_t UDC_DESC_STORAGE *ptr_end_desc; - - if (0 == udc_num_configuration) { - return false; - } - - if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) { - return false; - } - - // Start at the beginning of configuration descriptor - udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *) - udc_ptr_conf->desc; - - // Check the end of configuration descriptor - ptr_end_desc = udc_get_eof_conf(); - while (ptr_end_desc > - (UDC_DESC_STORAGE usb_conf_desc_t *) udc_ptr_iface) { - if (USB_DT_INTERFACE == udc_ptr_iface->bDescriptorType) { - // A interface descriptor is found - // Check interface and alternate setting number - if ((iface_num == udc_ptr_iface->bInterfaceNumber) && - (setting_num == - udc_ptr_iface->bAlternateSetting)) { - return true; // Interface found - } - } - // Go to next descriptor - udc_ptr_iface = (UDC_DESC_STORAGE usb_iface_desc_t *) ( - (uint8_t *) udc_ptr_iface + - udc_ptr_iface->bLength); - } - return false; // Interface not found -} - -/** - * \brief Disables an usb device interface (UDI) - * This routine call the UDI corresponding to interface number - * - * \param iface_num Interface number to disable - * - * \return 1 if it is done or 0 if interface is not found - */ -static bool udc_iface_disable(uint8_t iface_num) -{ - udi_api_t UDC_DESC_STORAGE *udi_api; - - // Select first alternate setting of the interface - // to update udc_ptr_iface before call iface->getsetting() - if (!udc_update_iface_desc(iface_num, 0)) { - return false; - } - - // Select the interface with the current alternate setting - udi_api = udc_ptr_conf->udi_apis[iface_num]; - -#if (0!=USB_DEVICE_MAX_EP) - if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) { - return false; - } - - // Start at the beginning of interface descriptor - { - usb_ep_desc_t UDC_DESC_STORAGE *ep_desc; - ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) udc_ptr_iface; - while (1) { - // Search Endpoint descriptor included in global interface descriptor - ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) - udc_next_desc_in_iface((UDC_DESC_STORAGE - usb_conf_desc_t *) - ep_desc, USB_DT_ENDPOINT); - if (NULL == ep_desc) { - break; - } - // Free the endpoint used by the interface - udd_ep_free(ep_desc->bEndpointAddress); - } - } -#endif - - // Disable interface - udi_api->disable(); - return true; -} - -/** - * \brief Enables an usb device interface (UDI) - * This routine calls the UDI corresponding - * to the interface and setting number. - * - * \param iface_num Interface number to enable - * \param setting_num Setting number to enable - * - * \return 1 if it is done or 0 if interface is not found - */ -static bool udc_iface_enable(uint8_t iface_num, uint8_t setting_num) -{ - // Select the interface descriptor - if (!udc_update_iface_desc(iface_num, setting_num)) { - return false; - } - -#if (0!=USB_DEVICE_MAX_EP) - usb_ep_desc_t UDC_DESC_STORAGE *ep_desc; - - // Start at the beginning of the global interface descriptor - ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) udc_ptr_iface; - while (1) { - // Search Endpoint descriptor included in the global interface descriptor - ep_desc = (UDC_DESC_STORAGE usb_ep_desc_t *) - udc_next_desc_in_iface((UDC_DESC_STORAGE - usb_conf_desc_t *) ep_desc, - USB_DT_ENDPOINT); - if (NULL == ep_desc) - break; - // Alloc the endpoint used by the interface - if (!udd_ep_alloc(ep_desc->bEndpointAddress, - ep_desc->bmAttributes, - le16_to_cpu - (ep_desc->wMaxPacketSize))) { - return false; - } - } -#endif - // Enable the interface - return udc_ptr_conf->udi_apis[iface_num]->enable(); -} - -/*! \brief Start the USB Device stack - */ -void udc_start(void) -{ - udd_enable(); -} - -/*! \brief Stop the USB Device stack - */ -void udc_stop(void) -{ - udd_disable(); - udc_reset(); -} - -/** - * \brief Reset the current configuration of the USB device, - * This routines can be called by UDD when a RESET on the USB line occurs. - */ -void udc_reset(void) -{ - uint8_t iface_num; - - if (udc_num_configuration) { - for (iface_num = 0; - iface_num < udc_ptr_conf->desc->bNumInterfaces; - iface_num++) { - udc_iface_disable(iface_num); - } - } - udc_num_configuration = 0; -#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \ - == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP)) - if (CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP) & udc_device_status) { - // Remote wakeup is enabled then disable it - UDC_REMOTEWAKEUP_DISABLE(); - } -#endif - udc_device_status = -#if (USB_DEVICE_ATTR & USB_CONFIG_ATTR_SELF_POWERED) - CPU_TO_LE16(USB_DEV_STATUS_SELF_POWERED); -#else - CPU_TO_LE16(USB_DEV_STATUS_BUS_POWERED); -#endif -} - -void udc_sof_notify(void) -{ - uint8_t iface_num; - - if (udc_num_configuration) { - for (iface_num = 0; - iface_num < udc_ptr_conf->desc->bNumInterfaces; - iface_num++) { - if (udc_ptr_conf->udi_apis[iface_num]->sof_notify != NULL) { - udc_ptr_conf->udi_apis[iface_num]->sof_notify(); - } - } - } -} - -/** - * \brief Standard device request to get device status - * - * \return true if success - */ -static bool udc_req_std_dev_get_status(void) -{ - if (udd_g_ctrlreq.req.wLength != sizeof(udc_device_status)) { - return false; - } - - udd_set_setup_payload( (uint8_t *) & udc_device_status, - sizeof(udc_device_status)); - return true; -} - -#if (0!=USB_DEVICE_MAX_EP) -/** - * \brief Standard endpoint request to get endpoint status - * - * \return true if success - */ -static bool udc_req_std_ep_get_status(void) -{ - static le16_t udc_ep_status; - - if (udd_g_ctrlreq.req.wLength != sizeof(udc_ep_status)) { - return false; - } - - udc_ep_status = udd_ep_is_halted(udd_g_ctrlreq.req. - wIndex & 0xFF) ? CPU_TO_LE16(USB_EP_STATUS_HALTED) : 0; - - udd_set_setup_payload( (uint8_t *) & udc_ep_status, - sizeof(udc_ep_status)); - return true; -} -#endif - -/** - * \brief Standard device request to change device status - * - * \return true if success - */ -static bool udc_req_std_dev_clear_feature(void) -{ - if (udd_g_ctrlreq.req.wLength) { - return false; - } - - if (udd_g_ctrlreq.req.wValue == USB_DEV_FEATURE_REMOTE_WAKEUP) { - udc_device_status &= CPU_TO_LE16(~(uint32_t)USB_DEV_STATUS_REMOTEWAKEUP); -#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \ - == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP)) - UDC_REMOTEWAKEUP_DISABLE(); -#endif - return true; - } - return false; -} - -#if (0!=USB_DEVICE_MAX_EP) -/** - * \brief Standard endpoint request to clear endpoint feature - * - * \return true if success - */ -static bool udc_req_std_ep_clear_feature(void) -{ - if (udd_g_ctrlreq.req.wLength) { - return false; - } - - if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) { - return udd_ep_clear_halt(udd_g_ctrlreq.req.wIndex & 0xFF); - } - return false; -} -#endif - -/** - * \brief Standard device request to set a feature - * - * \return true if success - */ -static bool udc_req_std_dev_set_feature(void) -{ - if (udd_g_ctrlreq.req.wLength) { - return false; - } - - switch (udd_g_ctrlreq.req.wValue) { - - case USB_DEV_FEATURE_REMOTE_WAKEUP: -#if (USB_CONFIG_ATTR_REMOTE_WAKEUP \ - == (USB_DEVICE_ATTR & USB_CONFIG_ATTR_REMOTE_WAKEUP)) - udc_device_status |= CPU_TO_LE16(USB_DEV_STATUS_REMOTEWAKEUP); - UDC_REMOTEWAKEUP_ENABLE(); - return true; -#else - return false; -#endif - -#ifdef USB_DEVICE_HS_SUPPORT - case USB_DEV_FEATURE_TEST_MODE: - if (!udd_is_high_speed()) { - break; - } - if (udd_g_ctrlreq.req.wIndex & 0xff) { - break; - } - // Unconfigure the device, terminating all ongoing requests - udc_reset(); - switch ((udd_g_ctrlreq.req.wIndex >> 8) & 0xFF) { - case USB_DEV_TEST_MODE_J: - udd_g_ctrlreq.callback = udd_test_mode_j; - return true; - - case USB_DEV_TEST_MODE_K: - udd_g_ctrlreq.callback = udd_test_mode_k; - return true; - - case USB_DEV_TEST_MODE_SE0_NAK: - udd_g_ctrlreq.callback = udd_test_mode_se0_nak; - return true; - - case USB_DEV_TEST_MODE_PACKET: - udd_g_ctrlreq.callback = udd_test_mode_packet; - return true; - - case USB_DEV_TEST_MODE_FORCE_ENABLE: // Only for downstream facing hub ports - default: - break; - } - break; -#endif - default: - break; - } - return false; -} - -/** - * \brief Standard endpoint request to halt an endpoint - * - * \return true if success - */ -#if (0!=USB_DEVICE_MAX_EP) -static bool udc_req_std_ep_set_feature(void) -{ - if (udd_g_ctrlreq.req.wLength) { - return false; - } - if (udd_g_ctrlreq.req.wValue == USB_EP_FEATURE_HALT) { - udd_ep_abort(udd_g_ctrlreq.req.wIndex & 0xFF); - return udd_ep_set_halt(udd_g_ctrlreq.req.wIndex & 0xFF); - } - return false; -} -#endif - -/** - * \brief Change the address of device - * Callback called at the end of request set address - */ -static void udc_valid_address(void) -{ - udd_set_address(udd_g_ctrlreq.req.wValue & 0x7F); -} - -/** - * \brief Standard device request to set device address - * - * \return true if success - */ -static bool udc_req_std_dev_set_address(void) -{ - if (udd_g_ctrlreq.req.wLength) { - return false; - } - - // The address must be changed at the end of setup request after the handshake - // then we use a callback to change address - udd_g_ctrlreq.callback = udc_valid_address; - return true; -} - -/** - * \brief Standard device request to get device string descriptor - * - * \return true if success - */ -static bool udc_req_std_dev_get_str_desc(void) -{ - uint8_t i; - const uint8_t *str; - uint8_t str_length = 0; - - // Link payload pointer to the string corresponding at request - switch (udd_g_ctrlreq.req.wValue & 0xff) { - case 0: - udd_set_setup_payload((uint8_t *) &udc_string_desc_languageid, - sizeof(udc_string_desc_languageid)); - break; - -#ifdef USB_DEVICE_MANUFACTURE_NAME - case 1: - str_length = USB_DEVICE_MANUFACTURE_NAME_SIZE; - str = udc_string_manufacturer_name; - break; -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - case 2: - str_length = USB_DEVICE_PRODUCT_NAME_SIZE; - str = udc_string_product_name; - break; -#endif -#if defined USB_DEVICE_SERIAL_NAME || defined USB_DEVICE_GET_SERIAL_NAME_POINTER - case 3: - str_length = USB_DEVICE_SERIAL_NAME_SIZE; - str = udc_get_string_serial_name(); - break; -#endif - default: -#ifdef UDC_GET_EXTRA_STRING - if (UDC_GET_EXTRA_STRING()) { - break; - } -#endif - return false; - } - - if (str_length) { - for(i = 0; i < str_length; i++) { - udc_string_desc.string[i] = cpu_to_le16((le16_t)str[i]); - } - - udc_string_desc.header.bLength = 2 + (str_length) * 2; - udd_set_setup_payload( - (uint8_t *) &udc_string_desc, - udc_string_desc.header.bLength); - } - - return true; -} - -/** - * \brief Standard device request to get descriptors about USB device - * - * \return true if success - */ -static bool udc_req_std_dev_get_descriptor(void) -{ - uint8_t conf_num; - - conf_num = udd_g_ctrlreq.req.wValue & 0xff; - - // Check descriptor ID - switch ((uint8_t) (udd_g_ctrlreq.req.wValue >> 8)) { - case USB_DT_DEVICE: - // Device descriptor requested -#ifdef USB_DEVICE_HS_SUPPORT - if (!udd_is_high_speed()) { - udd_set_setup_payload( - (uint8_t *) udc_config.confdev_hs, - udc_config.confdev_hs->bLength); - } else -#endif - { - udd_set_setup_payload( - (uint8_t *) udc_config.confdev_lsfs, - udc_config.confdev_lsfs->bLength); - } - break; - - case USB_DT_CONFIGURATION: - // Configuration descriptor requested -#ifdef USB_DEVICE_HS_SUPPORT - if (udd_is_high_speed()) { - // HS descriptor - if (conf_num >= udc_config.confdev_hs-> - bNumConfigurations) { - return false; - } - udd_set_setup_payload( - (uint8_t *)udc_config.conf_hs[conf_num].desc, - le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength)); - } else -#endif - { - // FS descriptor - if (conf_num >= udc_config.confdev_lsfs-> - bNumConfigurations) { - return false; - } - udd_set_setup_payload( - (uint8_t *)udc_config.conf_lsfs[conf_num].desc, - le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength)); - } - ((usb_conf_desc_t *) udd_g_ctrlreq.payload)->bDescriptorType = - USB_DT_CONFIGURATION; - break; - -#ifdef USB_DEVICE_HS_SUPPORT - case USB_DT_DEVICE_QUALIFIER: - // Device qualifier descriptor requested - udd_set_setup_payload( (uint8_t *) udc_config.qualifier, - udc_config.qualifier->bLength); - break; - - case USB_DT_OTHER_SPEED_CONFIGURATION: - // Other configuration descriptor requested - if (!udd_is_high_speed()) { - // HS descriptor - if (conf_num >= udc_config.confdev_hs-> - bNumConfigurations) { - return false; - } - udd_set_setup_payload( - (uint8_t *)udc_config.conf_hs[conf_num].desc, - le16_to_cpu(udc_config.conf_hs[conf_num].desc->wTotalLength)); - } else { - // FS descriptor - if (conf_num >= udc_config.confdev_lsfs-> - bNumConfigurations) { - return false; - } - udd_set_setup_payload( - (uint8_t *)udc_config.conf_lsfs[conf_num].desc, - le16_to_cpu(udc_config.conf_lsfs[conf_num].desc->wTotalLength)); - } - ((usb_conf_desc_t *) udd_g_ctrlreq.payload)->bDescriptorType = - USB_DT_OTHER_SPEED_CONFIGURATION; - break; -#endif - - case USB_DT_BOS: - // Device BOS descriptor requested - if (udc_config.conf_bos == NULL) { - return false; - } - udd_set_setup_payload( (uint8_t *) udc_config.conf_bos, - udc_config.conf_bos->wTotalLength); - break; - - case USB_DT_STRING: - // String descriptor requested - if (!udc_req_std_dev_get_str_desc()) { - return false; - } - break; - - default: - // Unknown descriptor requested - return false; - } - // if the descriptor is larger than length requested, then reduce it - if (udd_g_ctrlreq.req.wLength < udd_g_ctrlreq.payload_size) { - udd_g_ctrlreq.payload_size = udd_g_ctrlreq.req.wLength; - } - return true; -} - -/** - * \brief Standard device request to get configuration number - * - * \return true if success - */ -static bool udc_req_std_dev_get_configuration(void) -{ - if (udd_g_ctrlreq.req.wLength != 1) { - return false; - } - - udd_set_setup_payload(&udc_num_configuration,1); - return true; -} - -/** - * \brief Standard device request to enable a configuration - * - * \return true if success - */ -static bool udc_req_std_dev_set_configuration(void) -{ - uint8_t iface_num; - - // Check request length - if (udd_g_ctrlreq.req.wLength) { - return false; - } - // Authorize configuration only if the address is valid - if (!udd_getaddress()) { - return false; - } - // Check the configuration number requested -#ifdef USB_DEVICE_HS_SUPPORT - if (udd_is_high_speed()) { - // HS descriptor - if ((udd_g_ctrlreq.req.wValue & 0xFF) > - udc_config.confdev_hs->bNumConfigurations) { - return false; - } - } else -#endif - { - // FS descriptor - if ((udd_g_ctrlreq.req.wValue & 0xFF) > - udc_config.confdev_lsfs->bNumConfigurations) { - return false; - } - } - - // Reset current configuration - udc_reset(); - - // Enable new configuration - udc_num_configuration = udd_g_ctrlreq.req.wValue & 0xFF; - if (udc_num_configuration == 0) { - return true; // Default empty configuration requested - } - // Update pointer of the configuration descriptor -#ifdef USB_DEVICE_HS_SUPPORT - if (udd_is_high_speed()) { - // HS descriptor - udc_ptr_conf = &udc_config.conf_hs[udc_num_configuration - 1]; - } else -#endif - { - // FS descriptor - udc_ptr_conf = &udc_config.conf_lsfs[udc_num_configuration - 1]; - } - // Enable all interfaces of the selected configuration - for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; - iface_num++) { - if (!udc_iface_enable(iface_num, 0)) { - return false; - } - } - return true; -} - -/** - * \brief Standard interface request - * to get the alternate setting number of an interface - * - * \return true if success - */ -static bool udc_req_std_iface_get_setting(void) -{ - uint8_t iface_num; - udi_api_t UDC_DESC_STORAGE *udi_api; - - if (udd_g_ctrlreq.req.wLength != 1) { - return false; // Error in request - } - if (!udc_num_configuration) { - return false; // The device is not is configured state yet - } - - // Check the interface number included in the request - iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; - if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) { - return false; - } - - // Select first alternate setting of the interface to update udc_ptr_iface - // before call iface->getsetting() - if (!udc_update_iface_desc(iface_num, 0)) { - return false; - } - // Get alternate setting from UDI - udi_api = udc_ptr_conf->udi_apis[iface_num]; - udc_iface_setting = udi_api->getsetting(); - - // Link value to payload pointer of request - udd_set_setup_payload(&udc_iface_setting,1); - return true; -} - -/** - * \brief Standard interface request - * to set an alternate setting of an interface - * - * \return true if success - */ -static bool udc_req_std_iface_set_setting(void) -{ - uint8_t iface_num, setting_num; - - if (udd_g_ctrlreq.req.wLength) { - return false; // Error in request - } - if (!udc_num_configuration) { - return false; // The device is not is configured state yet - } - - iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; - setting_num = udd_g_ctrlreq.req.wValue & 0xFF; - - // Disable current setting - if (!udc_iface_disable(iface_num)) { - return false; - } - - // Enable new setting - return udc_iface_enable(iface_num, setting_num); -} - -/** - * \brief Main routine to manage the standard USB SETUP request - * - * \return true if the request is supported - */ -static bool udc_reqstd(void) -{ - if (Udd_setup_is_in()) { - // GET Standard Requests - if (udd_g_ctrlreq.req.wLength == 0) { - return false; // Error for USB host - } - - if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) { - // Standard Get Device request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_GET_STATUS: - return udc_req_std_dev_get_status(); - case USB_REQ_GET_DESCRIPTOR: - return udc_req_std_dev_get_descriptor(); - case USB_REQ_GET_CONFIGURATION: - return udc_req_std_dev_get_configuration(); - default: - break; - } - } - - if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) { - // Standard Get Interface request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_GET_INTERFACE: - return udc_req_std_iface_get_setting(); - default: - break; - } - } -#if (0!=USB_DEVICE_MAX_EP) - if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) { - // Standard Get Endpoint request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_GET_STATUS: - return udc_req_std_ep_get_status(); - default: - break; - } - } -#endif - } else { - // SET Standard Requests - if (USB_REQ_RECIP_DEVICE == Udd_setup_recipient()) { - // Standard Set Device request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_SET_ADDRESS: - return udc_req_std_dev_set_address(); - case USB_REQ_CLEAR_FEATURE: - return udc_req_std_dev_clear_feature(); - case USB_REQ_SET_FEATURE: - return udc_req_std_dev_set_feature(); - case USB_REQ_SET_CONFIGURATION: - return udc_req_std_dev_set_configuration(); - case USB_REQ_SET_DESCRIPTOR: - /* Not supported (defined as optional by the USB 2.0 spec) */ - break; - default: - break; - } - } - - if (USB_REQ_RECIP_INTERFACE == Udd_setup_recipient()) { - // Standard Set Interface request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_SET_INTERFACE: - return udc_req_std_iface_set_setting(); - default: - break; - } - } -#if (0!=USB_DEVICE_MAX_EP) - if (USB_REQ_RECIP_ENDPOINT == Udd_setup_recipient()) { - // Standard Set Endpoint request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_CLEAR_FEATURE: - return udc_req_std_ep_clear_feature(); - case USB_REQ_SET_FEATURE: - return udc_req_std_ep_set_feature(); - default: - break; - } - } -#endif - } - return false; -} - -/** - * \brief Send the SETUP interface request to UDI - * - * \return true if the request is supported - */ -static bool udc_req_iface(void) -{ - uint8_t iface_num; - udi_api_t UDC_DESC_STORAGE *udi_api; - - if (0 == udc_num_configuration) { - return false; // The device is not is configured state yet - } - // Check interface number - iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; - if (iface_num >= udc_ptr_conf->desc->bNumInterfaces) { - return false; - } - - //* To update udc_ptr_iface with the selected interface in request - // Select first alternate setting of interface to update udc_ptr_iface - // before calling udi_api->getsetting() - if (!udc_update_iface_desc(iface_num, 0)) { - return false; - } - // Select the interface with the current alternate setting - udi_api = udc_ptr_conf->udi_apis[iface_num]; - if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) { - return false; - } - - // Send the SETUP request to the UDI corresponding to the interface number - return udi_api->setup(); -} - -/** - * \brief Send the SETUP interface request to UDI - * - * \return true if the request is supported - */ -static bool udc_req_ep(void) -{ - uint8_t iface_num; - udi_api_t UDC_DESC_STORAGE *udi_api; - - if (0 == udc_num_configuration) { - return false; // The device is not is configured state yet - } - // Send this request on all enabled interfaces - iface_num = udd_g_ctrlreq.req.wIndex & 0xFF; - for (iface_num = 0; iface_num < udc_ptr_conf->desc->bNumInterfaces; - iface_num++) { - // Select the interface with the current alternate setting - udi_api = udc_ptr_conf->udi_apis[iface_num]; - if (!udc_update_iface_desc(iface_num, udi_api->getsetting())) { - return false; - } - - // Send the SETUP request to the UDI - if (udi_api->setup()) { - return true; - } - } - return false; -} - -/** - * \brief Main routine to manage the USB SETUP request. - * - * This function parses a USB SETUP request and submits an appropriate - * response back to the host or, in the case of SETUP OUT requests - * with data, sets up a buffer for receiving the data payload. - * - * The main standard requests defined by the USB 2.0 standard are handled - * internally. The interface requests are sent to UDI, and the specific request - * sent to a specific application callback. - * - * \return true if the request is supported, else the request is stalled by UDD - */ -bool udc_process_setup(void) -{ - // By default no data (receive/send) and no callbacks registered - udd_g_ctrlreq.payload_size = 0; - udd_g_ctrlreq.callback = NULL; - udd_g_ctrlreq.over_under_run = NULL; - - if (Udd_setup_is_in()) { - if (udd_g_ctrlreq.req.wLength == 0) { - return false; // Error from USB host - } - } - - // If standard request then try to decode it in UDC - if (Udd_setup_type() == USB_REQ_TYPE_STANDARD) { - if (udc_reqstd()) { - return true; - } - } - - // If interface request then try to decode it in UDI - if (Udd_setup_recipient() == USB_REQ_RECIP_INTERFACE) { - if (udc_req_iface()) { - return true; - } - } - - // If endpoint request then try to decode it in UDI - if (Udd_setup_recipient() == USB_REQ_RECIP_ENDPOINT) { - if (udc_req_ep()) { - return true; - } - } - - // Here SETUP request unknown by UDC and UDIs -#ifdef USB_DEVICE_SPECIFIC_REQUEST - // Try to decode it in specific callback - return USB_DEVICE_SPECIFIC_REQUEST(); // Ex: Vendor request,... -#else - return false; -#endif -} - -//! @} diff --git a/atmel-samd/asf/common/services/usb/udc/udc.h b/atmel-samd/asf/common/services/usb/udc/udc.h deleted file mode 100644 index edfe70788b075..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/udc.h +++ /dev/null @@ -1,697 +0,0 @@ -/** - * \file - * - * \brief Interface of the USB Device Controller (UDC) - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDC_H_ -#define _UDC_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udc_desc.h" -#include "udd.h" - -#if USB_DEVICE_VENDOR_ID == 0 -# error USB_DEVICE_VENDOR_ID cannot be equal to 0 -#endif - -#if USB_DEVICE_PRODUCT_ID == 0 -# error USB_DEVICE_PRODUCT_ID cannot be equal to 0 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup usb_device_group - * \defgroup udc_group USB Device Controller (UDC) - * - * The UDC provides a high-level abstraction of the usb device. - * You can use these functions to control the main device state - * (start/attach/wakeup). - * - * \section USB_DEVICE_CONF USB Device Custom configuration - * The following USB Device configuration must be included in the conf_usb.h - * file of the application. - * - * USB_DEVICE_VENDOR_ID (Word)
- * Vendor ID provided by USB org (ATMEL 0x03EB). - * - * USB_DEVICE_PRODUCT_ID (Word)
- * Product ID (Referenced in usb_atmel.h). - * - * USB_DEVICE_MAJOR_VERSION (Byte)
- * Major version of the device - * - * USB_DEVICE_MINOR_VERSION (Byte)
- * Minor version of the device - * - * USB_DEVICE_MANUFACTURE_NAME (string)
- * ASCII name for the manufacture - * - * USB_DEVICE_PRODUCT_NAME (string)
- * ASCII name for the product - * - * USB_DEVICE_SERIAL_NAME (string)
- * ASCII name to enable and set a serial number - * - * USB_DEVICE_POWER (Numeric)
- * (unit mA) Maximum device power - * - * USB_DEVICE_ATTR (Byte)
- * USB attributes available: - * - USB_CONFIG_ATTR_SELF_POWERED - * - USB_CONFIG_ATTR_REMOTE_WAKEUP - * Note: if remote wake enabled then defines remotewakeup callbacks, - * see Table 5-2. External API from UDC - Callback - * - * USB_DEVICE_LOW_SPEED (Only defined)
- * Force the USB Device to run in low speed - * - * USB_DEVICE_HS_SUPPORT (Only defined)
- * Authorize the USB Device to run in high speed - * - * USB_DEVICE_MAX_EP (Byte)
- * Define the maximum endpoint number used by the USB Device.
- * This one is already defined in UDI default configuration. - * Ex: - * - When endpoint control 0x00, endpoint 0x01 and - * endpoint 0x82 is used then USB_DEVICE_MAX_EP=2 - * - When only endpoint control 0x00 is used then USB_DEVICE_MAX_EP=0 - * - When endpoint 0x01 and endpoint 0x81 is used then USB_DEVICE_MAX_EP=1
- * (configuration not possible on USBB interface) - * @{ - */ - -/** - * \brief Authorizes the VBUS event - * - * \return true, if the VBUS monitoring is possible. - * - * \section udc_vbus_monitoring VBus monitoring used cases - * - * The VBus monitoring is used only for USB SELF Power application. - * - * - By default the USB device is automatically attached when Vbus is high - * or when USB is start for devices without internal Vbus monitoring. - * conf_usb.h file does not contains define USB_DEVICE_ATTACH_AUTO_DISABLE. - * \code //#define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode - * - * - Add custom VBUS monitoring. conf_usb.h file contains define - * USB_DEVICE_ATTACH_AUTO_DISABLE: - * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode - * User C file contains: - * \code - // Authorize VBUS monitoring - if (!udc_include_vbus_monitoring()) { - // Implement custom VBUS monitoring via GPIO or other - } - Event_VBUS_present() // VBUS interrupt or GPIO interrupt or other - { - // Attach USB Device - udc_attach(); - } -\endcode - * - * - Case of battery charging. conf_usb.h file contains define - * USB_DEVICE_ATTACH_AUTO_DISABLE: - * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode - * User C file contains: - * \code - Event VBUS present() // VBUS interrupt or GPIO interrupt or .. - { - // Authorize battery charging, but wait key press to start USB. - } - Event Key press() - { - // Stop batteries charging - // Start USB - udc_attach(); - } -\endcode - */ -static inline bool udc_include_vbus_monitoring(void) -{ - return udd_include_vbus_monitoring(); -} - -/*! \brief Start the USB Device stack - */ -void udc_start(void); - -/*! \brief Stop the USB Device stack - */ -void udc_stop(void); - -/** - * \brief Attach device to the bus when possible - * - * \warning If a VBus control is included in driver, - * then it will attach device when an acceptable Vbus - * level from the host is detected. - */ -static inline void udc_attach(void) -{ - udd_attach(); -} - - -/** - * \brief Detaches the device from the bus - * - * The driver must remove pull-up on USB line D- or D+. - */ -static inline void udc_detach(void) -{ - udd_detach(); -} - - -/*! \brief The USB driver sends a resume signal called \e "Upstream Resume" - * This is authorized only when the remote wakeup feature is enabled by host. - */ -static inline void udc_remotewakeup(void) -{ - udd_send_remotewakeup(); -} - - -/** - * \brief Returns a pointer on the current interface descriptor - * - * \return pointer on the current interface descriptor. - */ -usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void); - -//@} - -/** - * \ingroup usb_group - * \defgroup usb_device_group USB Stack Device - * - * This module includes USB Stack Device implementation. - * The stack is divided in three parts: - * - USB Device Controller (UDC) provides USB chapter 9 compliance - * - USB Device Interface (UDI) provides USB Class compliance - * - USB Device Driver (UDD) provides USB Driver for each Atmel MCU - - * Many USB Device applications can be implemented on Atmel MCU. - * Atmel provides many application notes for different applications: - * - AVR4900, provides general information about Device Stack - * - AVR4901, explains how to create a new class - * - AVR4902, explains how to create a composite device - * - AVR49xx, all device classes provided in ASF have an application note - * - * A basic USB knowledge is required to understand the USB Device - * Class application notes (HID,MS,CDC,PHDC,...). - * Then, to create an USB device with - * only one class provided by ASF, refer directly to the application note - * corresponding to this USB class. The USB Device application note for - * New Class and Composite is dedicated to advanced USB users. - * - * @{ - */ - -//! @} - -#ifdef __cplusplus -} -#endif - -/** - * \ingroup udc_group - * \defgroup udc_basic_use_case_setup_prereq USB Device Controller (UDC) - Prerequisites - * Common prerequisites for all USB devices. - * - * This module is based on USB device stack full interrupt driven, and supporting - * \ref sleepmgr_group sleepmgr. For AVR and SAM3/4 devices the \ref clk_group clock services - * is supported. For SAMD devices the \ref asfdoc_sam0_system_clock_group clock driver is supported. - * - * The following procedure must be executed to setup the project correctly: - * - Specify the clock configuration: - * - XMEGA USB devices need 48MHz clock input.\n - * XMEGA USB devices need CPU frequency higher than 12MHz.\n - * You can use either an internal RC48MHz auto calibrated by Start of Frames - * or an external OSC. - * - UC3 and SAM3/4 devices without USB high speed support need 48MHz clock input.\n - * You must use a PLL and an external OSC. - * - UC3 and SAM3/4 devices with USB high speed support need 12MHz clock input.\n - * You must use an external OSC. - * - UC3 devices with USBC hardware need CPU frequency higher than 25MHz. - * - SAMD devices without USB high speed support need 48MHz clock input.\n - * You should use DFLL with USBCRM. - * - In conf_board.h, the define CONF_BOARD_USB_PORT must be added to enable USB lines. - * (Not mandatory for all boards) - * - Enable interrupts - * - Initialize the clock service - * - * The usage of \ref sleepmgr_group sleepmgr service is optional, but recommended to reduce power - * consumption: - * - Initialize the sleep manager service - * - Activate sleep mode when the application is in IDLE state - * - * \subpage udc_conf_clock. - * - * for AVR and SAM3/4 devices, add to the initialization code: - * \code - sysclk_init(); - irq_initialize_vectors(); - cpu_irq_enable(); - board_init(); - sleepmgr_init(); // Optional -\endcode - * - * For SAMD devices, add to the initialization code: - * \code - system_init(); - irq_initialize_vectors(); - cpu_irq_enable(); - sleepmgr_init(); // Optional -\endcode - * Add to the main IDLE loop: - * \code - sleepmgr_enter_sleep(); // Optional -\endcode - * - */ - -/** - * \ingroup udc_group - * \defgroup udc_basic_use_case_setup_code USB Device Controller (UDC) - Example code - * Common example code for all USB devices. - * - * Content of conf_usb.h: - * \code - #define USB_DEVICE_VENDOR_ID 0x03EB - #define USB_DEVICE_PRODUCT_ID 0xXXXX - #define USB_DEVICE_MAJOR_VERSION 1 - #define USB_DEVICE_MINOR_VERSION 0 - #define USB_DEVICE_POWER 100 - #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED -\endcode - * - * Add to application C-file: - * \code - void usb_init(void) - { - udc_start(); - } -\endcode - */ - -/** - * \ingroup udc_group - * \defgroup udc_basic_use_case_setup_flow USB Device Controller (UDC) - Workflow - * Common workflow for all USB devices. - * - * -# Ensure that conf_usb.h is available and contains the following configuration - * which is the main USB device configuration: - * - \code // Vendor ID provided by USB org (ATMEL 0x03EB) - #define USB_DEVICE_VENDOR_ID 0x03EB // Type Word - // Product ID (Atmel PID referenced in usb_atmel.h) - #define USB_DEVICE_PRODUCT_ID 0xXXXX // Type Word - // Major version of the device - #define USB_DEVICE_MAJOR_VERSION 1 // Type Byte - // Minor version of the device - #define USB_DEVICE_MINOR_VERSION 0 // Type Byte - // Maximum device power (mA) - #define USB_DEVICE_POWER 100 // Type 9-bits - // USB attributes to enable features - #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED // Flags \endcode - * -# Call the USB device stack start function to enable stack and start USB: - * - \code udc_start(); \endcode - * \note In case of USB dual roles (Device and Host) managed through USB OTG connector - * (USB ID pin), the call of udc_start() must be removed and replaced by uhc_start(). - * SeRefer to "AVR4950 section 6.1 Dual roles" for further information about dual roles. - */ - -/** - * \page udc_conf_clock conf_clock.h examples with USB support - * - * Content of XMEGA conf_clock.h: - * \code - // Configuration based on internal RC: - // USB clock need of 48Mhz - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_RCOSC - #define CONFIG_OSC_RC32_CAL 48000000UL - #define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC OSC_ID_USBSOF - // CPU clock need of clock > 12MHz to run with USB (Here 24MHz) - #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC32MHZ - #define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_2 - #define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1 -\endcode - * - * Content of conf_clock.h for AT32UC3A0, AT32UC3A1, AT32UC3B devices (USBB): - * \code - // Configuration based on 12MHz external OSC: - #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0 - #define CONFIG_PLL1_MUL 8 - #define CONFIG_PLL1_DIV 2 - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 - #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) -\endcode - * - * Content of conf_clock.h for AT32UC3A3, AT32UC3A4 devices (USBB with high speed support): - * \code - // Configuration based on 12MHz external OSC: - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0 - #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) -\endcode - * - * Content of conf_clock.h for AT32UC3C, ATUCXXD, ATUCXXL3U, ATUCXXL4U devices (USBC): - * \code - // Configuration based on 12MHz external OSC: - #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0 - #define CONFIG_PLL1_MUL 8 - #define CONFIG_PLL1_DIV 2 - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 - #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) - // CPU clock need of clock > 25MHz to run with USBC - #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL1 -\endcode - * - * Content of conf_clock.h for SAM3S, SAM3SD, SAM4S devices (UPD: USB Peripheral Device): - * \code - // PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div) - #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL - #define CONFIG_PLL1_MUL 16 - #define CONFIG_PLL1_DIV 2 - // USB Clock Source Options (Fusb = FpllX / USB_div) - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 - #define CONFIG_USBCLK_DIV 2 -\endcode - * - * Content of conf_clock.h for SAM3U device (UPDHS: USB Peripheral Device High Speed): - * \code - // USB Clock Source fixed at UPLL. -\endcode - * - * Content of conf_clock.h for SAM3X, SAM3A devices (UOTGHS: USB OTG High Speed): - * \code - // USB Clock Source fixed at UPLL. - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL - #define CONFIG_USBCLK_DIV 1 -\endcode - * - * Content of conf_clocks.h for SAMD devices (USB): - * \code - // System clock bus configuration - # define CONF_CLOCK_FLASH_WAIT_STATES 2 - - // USB Clock Source fixed at DFLL. - // SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop - # define CONF_CLOCK_DFLL_ENABLE true - # define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY - # define CONF_CLOCK_DFLL_ON_DEMAND true - - // Set this to true to configure the GCLK when running clocks_init. - // If set to false, none of the GCLK generators will be configured in clocks_init(). - # define CONF_CLOCK_CONFIGURE_GCLK true - - // Configure GCLK generator 0 (Main Clock) - # define CONF_CLOCK_GCLK_0_ENABLE true - # define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true - # define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL - # define CONF_CLOCK_GCLK_0_PRESCALER 1 - # define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false -\endcode - */ - -/** - * \page udc_use_case_1 Change USB speed - * - * In this use case, the USB device is used with different USB speeds. - * - * \section udc_use_case_1_setup Setup steps - * - * Prior to implement this use case, be sure to have already - * apply the UDI module "basic use case". - * - * \section udc_use_case_1_usage Usage steps - * - * \subsection udc_use_case_1_usage_code Example code - * Content of conf_usb.h: - * \code - #if // Low speed - #define USB_DEVICE_LOW_SPEED - // #define USB_DEVICE_HS_SUPPORT - - #elif // Full speed - // #define USB_DEVICE_LOW_SPEED - // #define USB_DEVICE_HS_SUPPORT - - #elif // High speed - // #define USB_DEVICE_LOW_SPEED - #define USB_DEVICE_HS_SUPPORT - - #endif -\endcode - * - * \subsection udc_use_case_1_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB device low speed (1.5Mbit/s): - * - \code #define USB_DEVICE_LOW_SPEED - //#define USB_DEVICE_HS_SUPPORT \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB device full speed (12Mbit/s): - * - \code //#define USB_DEVICE_LOW_SPEED - //#define USB_DEVICE_HS_SUPPORT \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB device high speed (480Mbit/s): - * - \code //#define USB_DEVICE_LOW_SPEED - #define USB_DEVICE_HS_SUPPORT \endcode - */ - -/** - * \page udc_use_case_2 Use USB strings - * - * In this use case, the usual USB strings is added in the USB device. - * - * \section udc_use_case_2_setup Setup steps - * Prior to implement this use case, be sure to have already - * apply the UDI module "basic use case". - * - * \section udc_use_case_2_usage Usage steps - * - * \subsection udc_use_case_2_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" - #define USB_DEVICE_PRODUCT_NAME "Product name" - #define USB_DEVICE_SERIAL_NAME "12...EF" -\endcode - * - * \subsection udc_use_case_2_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required to enable different USB strings: - * - \code // Static ASCII name for the manufacture - #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" \endcode - * - \code // Static ASCII name for the product - #define USB_DEVICE_PRODUCT_NAME "Product name" \endcode - * - \code // Static ASCII name to enable and set a serial number - #define USB_DEVICE_SERIAL_NAME "12...EF" \endcode - */ - -/** - * \page udc_use_case_3 Use USB remote wakeup feature - * - * In this use case, the USB remote wakeup feature is enabled. - * - * \section udc_use_case_3_setup Setup steps - * Prior to implement this use case, be sure to have already - * apply the UDI module "basic use case". - * - * \section udc_use_case_3_usage Usage steps - * - * \subsection udc_use_case_3_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) - #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable() - extern void my_callback_remotewakeup_enable(void); - #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable() - extern void my_callback_remotewakeup_disable(void); -\endcode - * - * Add to application C-file: - * \code - void my_callback_remotewakeup_enable(void) - { - // Enable application wakeup events (e.g. enable GPIO interrupt) - } - void my_callback_remotewakeup_disable(void) - { - // Disable application wakeup events (e.g. disable GPIO interrupt) - } - - void my_interrupt_event(void) - { - udc_remotewakeup(); - } -\endcode - * - * \subsection udc_use_case_3_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required to enable remote wakeup feature: - * - \code // Authorizes the remote wakeup feature - #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) \endcode - * - \code // Define callback called when the host enables the remotewakeup feature - #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable() - extern void my_callback_remotewakeup_enable(void); \endcode - * - \code // Define callback called when the host disables the remotewakeup feature - #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable() - extern void my_callback_remotewakeup_disable(void); \endcode - * -# Send a remote wakeup (USB upstream): - * - \code udc_remotewakeup(); \endcode - */ - -/** - * \page udc_use_case_5 Bus power application recommendations - * - * In this use case, the USB device BUS power feature is enabled. - * This feature requires a correct power consumption management. - * - * \section udc_use_case_5_setup Setup steps - * Prior to implement this use case, be sure to have already - * apply the UDI module "basic use case". - * - * \section udc_use_case_5_usage Usage steps - * - * \subsection udc_use_case_5_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) - #define UDC_SUSPEND_EVENT() user_callback_suspend_action() - extern void user_callback_suspend_action(void) - #define UDC_RESUME_EVENT() user_callback_resume_action() - extern void user_callback_resume_action(void) -\endcode - * - * Add to application C-file: - * \code - void user_callback_suspend_action(void) - { - // Disable hardware component to reduce power consumption - } - void user_callback_resume_action(void) - { - // Re-enable hardware component - } -\endcode - * - * \subsection udc_use_case_5_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters: - * - \code // Authorizes the BUS power feature - #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) \endcode - * - \code // Define callback called when the host suspend the USB line - #define UDC_SUSPEND_EVENT() user_callback_suspend_action() - extern void user_callback_suspend_action(void); \endcode - * - \code // Define callback called when the host or device resume the USB line - #define UDC_RESUME_EVENT() user_callback_resume_action() - extern void user_callback_resume_action(void); \endcode - * -# Reduce power consumption in suspend mode (max. 2.5mA on Vbus): - * - \code void user_callback_suspend_action(void) - { - turn_off_components(); - } \endcode - */ - -/** - * \page udc_use_case_6 USB dynamic serial number - * - * In this use case, the USB serial strings is dynamic. - * For a static serial string refer to \ref udc_use_case_2. - * - * \section udc_use_case_6_setup Setup steps - * Prior to implement this use case, be sure to have already - * apply the UDI module "basic use case". - * - * \section udc_use_case_6_usage Usage steps - * - * \subsection udc_use_case_6_usage_code Example code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_SERIAL_NAME - #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number - #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 - extern uint8_t serial_number[]; -\endcode - * - * Add to application C-file: - * \code - uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - - void init_build_usb_serial_number(void) - { - serial_number[0] = 'A'; - serial_number[1] = 'B'; - ... - serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C'; - } \endcode - * - * \subsection udc_use_case_6_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required to enable a USB serial number strings dynamically: - * - \code #define USB_DEVICE_SERIAL_NAME // Define this empty - #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number // Give serial array pointer - #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 // Give size of serial array - extern uint8_t serial_number[]; // Declare external serial array \endcode - * -# Before start USB stack, initialize the serial array - * - \code - uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - - void init_build_usb_serial_number(void) - { - serial_number[0] = 'A'; - serial_number[1] = 'B'; - ... - serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C'; - } \endcode - */ - - - -#endif // _UDC_H_ diff --git a/atmel-samd/asf/common/services/usb/udc/udc_desc.h b/atmel-samd/asf/common/services/usb/udc/udc_desc.h deleted file mode 100644 index 88ed08a96118b..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/udc_desc.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * \file - * - * \brief Common API for USB Device Interface - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDC_DESC_H_ -#define _UDC_DESC_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udi.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup udc_group - * \defgroup udc_desc_group USB Device Descriptor - * - * @{ - */ - -/** - * \brief Defines the memory's location of USB descriptors - * - * By default the Descriptor is stored in RAM - * (UDC_DESC_STORAGE is defined empty). - * - * If you have need to free RAM space, - * it is possible to put descriptor in flash in following case: - * - USB driver authorize flash transfer (USBB on UC3 and USB on Mega) - * - USB Device is not high speed (UDC no need to change USB descriptors) - * - * For UC3 application used "const". - * - * For Mega application used "code". - */ -#define UDC_DESC_STORAGE - // Descriptor storage in internal RAM -#if (defined UDC_DATA_USE_HRAM_SUPPORT) -# if defined(__GNUC__) -# define UDC_DATA(x) COMPILER_WORD_ALIGNED __attribute__((__section__(".data_hram0"))) -# define UDC_BSS(x) COMPILER_ALIGNED(x) __attribute__((__section__(".bss_hram0"))) -# elif defined(__ICCAVR32__) -# define UDC_DATA(x) COMPILER_ALIGNED(x) __data32 -# define UDC_BSS(x) COMPILER_ALIGNED(x) __data32 -# endif -#else -# define UDC_DATA(x) COMPILER_ALIGNED(x) -# define UDC_BSS(x) COMPILER_ALIGNED(x) -#endif - - - -/** - * \brief Configuration descriptor and UDI link for one USB speed - */ -typedef struct { - //! USB configuration descriptor - usb_conf_desc_t UDC_DESC_STORAGE *desc; - //! Array of UDI API pointer - udi_api_t UDC_DESC_STORAGE *UDC_DESC_STORAGE * udi_apis; -} udc_config_speed_t; - - -/** - * \brief All information about the USB Device - */ -typedef struct { - //! USB device descriptor for low or full speed - usb_dev_desc_t UDC_DESC_STORAGE *confdev_lsfs; - //! USB configuration descriptor and UDI API pointers for low or full speed - udc_config_speed_t UDC_DESC_STORAGE *conf_lsfs; -#ifdef USB_DEVICE_HS_SUPPORT - //! USB device descriptor for high speed - usb_dev_desc_t UDC_DESC_STORAGE *confdev_hs; - //! USB device qualifier, only use in high speed mode - usb_dev_qual_desc_t UDC_DESC_STORAGE *qualifier; - //! USB configuration descriptor and UDI API pointers for high speed - udc_config_speed_t UDC_DESC_STORAGE *conf_hs; -#endif - usb_dev_bos_desc_t UDC_DESC_STORAGE *conf_bos; -} udc_config_t; - -//! Global variables of USB Device Descriptor and UDI links -extern UDC_DESC_STORAGE udc_config_t udc_config; - -//@} - -#ifdef __cplusplus -} -#endif -#endif // _UDC_DESC_H_ diff --git a/atmel-samd/asf/common/services/usb/udc/udc_dfu_small.c b/atmel-samd/asf/common/services/usb/udc/udc_dfu_small.c deleted file mode 100644 index 79897308e08fb..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/udc_dfu_small.c +++ /dev/null @@ -1,493 +0,0 @@ -/** - * \file - * - * \brief USB Device Controller (UDC) optimized for DFU FLIP Device - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "conf_usb.h" -#include "usb_protocol.h" -#include "udd.h" -#include "udc_desc.h" -#include "udi.h" -#include "udc.h" -#include "udi_dfu_atmel.h" - -extern bool udi_dfu_atmel_enable(void); -extern void udi_dfu_atmel_disable(void); -extern bool udi_dfu_atmel_setup(void); - -/** - * \addtogroup udc_group - * @{ - */ - -//! \name Internal variables to manage the USB device -//! @{ - -//! Device status state (see enum usb_device_status in usb_protocol.h) -static le16_t udc_device_status; -//! Device Configuration number selected by the USB host -static uint8_t udc_num_configuration = 0; -//! Pointer on the selected speed device configuration -//static udc_config_speed_t UDC_DESC_STORAGE *udc_ptr_conf; -//! Pointer on interface descriptor used by SETUP request. -//static usb_iface_desc_t UDC_DESC_STORAGE *udc_ptr_iface; -extern UDC_DESC_STORAGE usb_dev_desc_t udc_device_desc; -//! Structure for USB Device Configuration Descriptor -COMPILER_PACK_SET(1) -typedef struct { - usb_conf_desc_t conf; - udi_dfu_atmel_desc_t udi_dfu_atmel; -} udc_desc_t; -COMPILER_PACK_RESET() -extern UDC_DESC_STORAGE udc_desc_t udc_desc_fs; - -//! @} - - -//! \name Internal structure to store the USB device main strings -//! @{ - -/** - * \brief USB device manufacture name storage - * String is allocated only if USB_DEVICE_MANUFACTURE_NAME is declared - * by usb application configuration - */ -#ifdef USB_DEVICE_MANUFACTURE_NAME -static uint8_t udc_string_manufacturer_name[] = USB_DEVICE_MANUFACTURE_NAME; -#define USB_DEVICE_MANUFACTURE_NAME_SIZE (sizeof(udc_string_manufacturer_name)-1) -#else -#define USB_DEVICE_MANUFACTURE_NAME_SIZE 0 -#endif - - -/** - * \brief USB device product name storage - * String is allocated only if USB_DEVICE_PRODUCT_NAME is declared - * by usb application configuration - */ -#ifdef USB_DEVICE_PRODUCT_NAME -static uint8_t udc_string_product_name[] = USB_DEVICE_PRODUCT_NAME; -#define USB_DEVICE_PRODUCT_NAME_SIZE (sizeof(udc_string_product_name)-1) -#else -#define USB_DEVICE_PRODUCT_NAME_SIZE 0 -#endif - -/** - * \brief USB device serial number storage - * String is allocated only if USB_DEVICE_SERIAL_NAME is declared - * by usb application configuration - */ -#ifdef USB_DEVICE_SERIAL_NAME -static uint8_t udc_string_serial_name[] = USB_DEVICE_SERIAL_NAME; -#define USB_DEVICE_SERIAL_NAME_SIZE (sizeof(udc_string_serial_name)-1) -#else -#define USB_DEVICE_SERIAL_NAME_SIZE 0 -#endif - -/** - * \brief USB device string descriptor - * Structure used to transfer ASCII strings to USB String descriptor structure. - */ -struct udc_string_desc_t { - usb_str_desc_t header; - le16_t string[Max(Max(USB_DEVICE_MANUFACTURE_NAME_SIZE, \ - USB_DEVICE_PRODUCT_NAME_SIZE), USB_DEVICE_SERIAL_NAME_SIZE)]; -}; -COMPILER_WORD_ALIGNED -static UDC_DESC_STORAGE struct udc_string_desc_t udc_string_desc = { - .header.bDescriptorType = USB_DT_STRING -}; - -/** - * \brief Language ID of USB device (US ID by default) - */ -COMPILER_WORD_ALIGNED -static UDC_DESC_STORAGE usb_str_lgid_desc_t udc_string_desc_languageid = { - .desc.bLength = sizeof(usb_str_lgid_desc_t), - .desc.bDescriptorType = USB_DT_STRING, - .string = {LE16(USB_LANGID_EN_US)} -}; - -//! @} - - - - -/** - * \brief Disables an usb device interface (UDI) - * This routine call the UDI corresponding to interface number - * - * \param iface_num Interface number to disable - * - * \return 1 if it is done or 0 if interface is not found - */ -static bool udc_iface_disable(void) -{ - // Disable interface - udi_dfu_atmel_disable(); - return true; -} - - -/** - * \brief Enables an usb device interface (UDI) - * This routine calls the UDI corresponding - * to the interface and setting number. - * - * \param iface_num Interface number to enable - * \param setting_num Setting number to enable - * - * \return 1 if it is done or 0 if interface is not found - */ -static bool udc_iface_enable(void) -{ - // Enable the interface - return udi_dfu_atmel_enable(); -} - -/*! \brief Start the USB Device stack - */ -void udc_start(void) -{ - udd_enable(); -} - -/*! \brief Stop the USB Device stack - */ -void udc_stop(void) -{ - udd_disable(); -} - -/** - * \brief Reset the current configuration of the USB device, - * This routines can be called by UDD when a RESET on the USB line occurs. - */ -void udc_reset(void) -{ - if (udc_num_configuration) { - udc_iface_disable(); - } - udc_num_configuration = 0; - udc_device_status = -#if (USB_DEVICE_ATTR & USB_CONFIG_ATTR_SELF_POWERED) - CPU_TO_LE16(USB_DEV_STATUS_SELF_POWERED); -#else - CPU_TO_LE16(USB_DEV_STATUS_BUS_POWERED); -#endif -} - -void udc_sof_notify(void) -{ -} - -/** - * \brief Standard device request to get device status - * - * \return true if success - */ -static bool udc_req_std_dev_get_status(void) -{ - udd_set_setup_payload( - (uint8_t *) &udc_device_status, - sizeof(udc_device_status)); - return true; -} - - -/** - * \brief Change the address of device - * Callback called at the end of request set address - */ -static void udc_valid_address(void) -{ - udd_set_address(udd_g_ctrlreq.req.wValue & 0x7F); -} - - -/** - * \brief Standard device request to set device address - * - * \return true if success - */ -static bool udc_req_std_dev_set_address(void) -{ - // The address must be changed at the end of setup request after the handshake - // then we use a callback to change address - udd_g_ctrlreq.callback = udc_valid_address; - return true; -} - - -/** - * \brief Standard device request to get device string descriptor - * - * \return true if success - */ -static bool udc_req_std_dev_get_str_desc(void) -{ - uint8_t i; - uint8_t *str; - uint8_t str_lgt=0; - - // Link payload pointer to the string corresponding at request - switch (udd_g_ctrlreq.req.wValue & 0xff) { - case 0: - udd_set_setup_payload( - (uint8_t *) & udc_string_desc_languageid, - sizeof(udc_string_desc_languageid)); - break; - -#ifdef USB_DEVICE_MANUFACTURE_NAME - case 1: - str_lgt = USB_DEVICE_MANUFACTURE_NAME_SIZE; - str = udc_string_manufacturer_name; - break; -#endif -#ifdef USB_DEVICE_PRODUCT_NAME - case 2: - str_lgt = USB_DEVICE_PRODUCT_NAME_SIZE; - str = udc_string_product_name; - break; -#endif -#ifdef USB_DEVICE_SERIAL_NAME - case 3: - str_lgt = USB_DEVICE_SERIAL_NAME_SIZE; - str = udc_string_serial_name; - break; -#endif - default: - return false; - } - - if (str_lgt != 0) { - for(i = 0; i < str_lgt; i++) { - udc_string_desc.string[i] = cpu_to_le16((le16_t)str[i]); - } - - udc_string_desc.header.bLength = 2 + (str_lgt) * 2; - udd_set_setup_payload( - (uint8_t *) &udc_string_desc, - udc_string_desc.header.bLength); - } - return true; -} - - -/** - * \brief Standard device request to get descriptors about USB device - * - * \return true if success - */ -static bool udc_req_std_dev_get_descriptor(void) -{ - // Check descriptor ID - switch ((uint8_t) (udd_g_ctrlreq.req.wValue >> 8)) { - case USB_DT_DEVICE: - // Device descriptor requested - udd_set_setup_payload( - (uint8_t*)&udc_device_desc, - udc_device_desc.bLength); - break; - - case USB_DT_CONFIGURATION: - // Configuration descriptor requested - // FS descriptor - udd_set_setup_payload( - (uint8_t*)&udc_desc_fs, - le16_to_cpu(udc_desc_fs.conf.wTotalLength)); - break; - - case USB_DT_STRING: - // String descriptor requested - if (!udc_req_std_dev_get_str_desc()) { - return false; - } - break; - - default: - // Unknown descriptor requested - return false; - } - // if the descriptor is larger than length requested, then reduce it - if (udd_g_ctrlreq.req.wLength < udd_g_ctrlreq.payload_size) { - udd_g_ctrlreq.payload_size = udd_g_ctrlreq.req.wLength; - } - return true; -} - - -/** - * \brief Standard device request to get configuration number - * - * \return true if success - */ -static bool udc_req_std_dev_get_configuration(void) -{ - udd_set_setup_payload( - &udc_num_configuration, 1); - return true; -} - - -/** - * \brief Standard device request to enable a configuration - * - * \return true if success - */ -static bool udc_req_std_dev_set_configuration(void) -{ - // Reset current configuration - udc_reset(); - - // Enable new configuration - udc_num_configuration = udd_g_ctrlreq.req.wValue & 0xFF; - if (udc_num_configuration == 0) { - return true; // Default empty configuration requested - } - // Pointer of the configuration descriptor always good - // Enable all interfaces of the selected configuration - if (!udc_iface_enable()) { - return false; - } - return true; -} - - -/** - * \brief Main routine to manage the standard USB SETUP request - * - * \return true if the request is supported - */ -static bool udc_reqstd(void) -{ - if (USB_REQ_RECIP_DEVICE != Udd_setup_recipient()) { - return false; - } - - if (Udd_setup_is_in()) { - // Standard Get Device request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_GET_STATUS: - return udc_req_std_dev_get_status(); - case USB_REQ_GET_DESCRIPTOR: - return udc_req_std_dev_get_descriptor(); - case USB_REQ_GET_CONFIGURATION: - return udc_req_std_dev_get_configuration(); - } - } else { - // Standard Set Device request - switch (udd_g_ctrlreq.req.bRequest) { - case USB_REQ_SET_ADDRESS: - return udc_req_std_dev_set_address(); - case USB_REQ_SET_CONFIGURATION: - return udc_req_std_dev_set_configuration(); - } - } - return false; -} - - -/** - * \brief Send the SETUP interface request to UDI - * - * \return true if the request is supported - */ -static bool udc_req_iface(void) -{ - // Send the SETUP request to the UDI corresponding to the interface number - return udi_dfu_atmel_setup(); -} - - -/** - * \brief Main routine to manage the USB SETUP request. - * - * This function parses a USB SETUP request and submits an appropriate - * response back to the host or, in the case of SETUP OUT requests - * with data, sets up a buffer for receiving the data payload. - * - * The main standard requests defined by the USB 2.0 standard are handled - * internally. The interface requests are sent to UDI, and the specific request - * sent to a specific application callback. - * - * \return true if the request is supported, else the request is stalled by UDD - */ -bool udc_process_setup(void) -{ - // By default no data (receive/send) and no callbacks registered - udd_g_ctrlreq.payload_size = 0; - udd_g_ctrlreq.callback = NULL; - udd_g_ctrlreq.over_under_run = NULL; - - if (Udd_setup_is_in()) { - if (udd_g_ctrlreq.req.wLength == 0) { - return false; // Error from USB host - } - } - - // If standard request then try to decode it in UDC - if (Udd_setup_type() == USB_REQ_TYPE_STANDARD) { - if (udc_reqstd()) { - return true; - } - } - - // If interface request then try to decode it in UDI - if (Udd_setup_recipient() == USB_REQ_RECIP_INTERFACE) { - if (udc_req_iface()) { - return true; - } - } - - // Here SETUP request unknown by UDC and UDIs -#ifdef USB_DEVICE_SPECIFIC_REQUEST - // Try to decode it in specific callback - return USB_DEVICE_SPECIFIC_REQUEST(); // Ex: Vendor request,... -#else - return false; -#endif -} - -//! @} diff --git a/atmel-samd/asf/common/services/usb/udc/udc_doc.h b/atmel-samd/asf/common/services/usb/udc/udc_doc.h deleted file mode 100644 index 56441bd24ba05..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/udc_doc.h +++ /dev/null @@ -1,722 +0,0 @@ -/** - * \file - * - * \brief USB Device Controller (UDC) - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \if ASF_MANUAL - * \defgroup asfdoc_udc_group USB Device Controller (UDC) - * - * The UDC provides a high-level abstraction of the USB device. - * You can use these functions to control the main device state - * (start/attach/wakeup). - * - * All USB Device Interface (UDI) in USB Device Stack is based on UDC to support - * USB enumeration. - * - * This documentation describes common USB Device usage based on UDC, as follow: - * - \ref asfdoc_udc_api_overview - * - \ref asfdoc_udc_basic_use_case_setup - * - \ref asfdoc_udc_use_cases - * - * \section asfdoc_udc_api_overview API Overview - * @{ - * - */ - -/** - * \brief Authorizes the VBUS event - * - * \return True, if the VBUS monitoring is possible. - * - * See \ref asfdoc_udc_vbus_monitoring for more details. - * - */ -static inline bool udc_include_vbus_monitoring(void) -{ - return udd_include_vbus_monitoring(); -} - -/** - * \brief Start the USB Device stack - */ -void udc_start(void); - -/** - * \brief Stop the USB Device stack - */ -void udc_stop(void); - -/** - * \brief Attach device to the bus when possible - * - * \warning If a VBUS control is included in driver, - * then it will attach device when an acceptable VBUS - * level from the host is detected. - */ -static inline void udc_attach(void) -{ - udd_attach(); -} - -/** - * \brief Detaches the device from the bus - * - * The driver must remove pull-up on USB line D- or D+. - */ -static inline void udc_detach(void) -{ - udd_detach(); -} - -/** - * \brief The USB driver sends a resume signal called \e "Upstream Resume" - * - * This is authorized only when the remote wakeup feature is enabled by host. - */ -static inline void udc_remotewakeup(void) -{ - udd_send_remotewakeup(); -} - - -/** - * \brief Returns a pointer on the current interface descriptor - * - * \return Pointer on the current interface descriptor. - */ -usb_iface_desc_t UDC_DESC_STORAGE *udc_get_interface_desc(void); - -/** - * @} - * \endif - */ -/* - * Support and FAQ: visit Atmel Support - */ - -/** - * \page asfdoc_udc_basic_use_case_setup USB Device Basic Setup - * - * \section asfdoc_udc_device_cfg Custom Configuration - * - * The following USB Device configuration must be included in the conf_usb.h - * file of the application: - * - * \b 1. USB_DEVICE_VENDOR_ID (Word). - * - * Vendor ID provided by USB org (Atmel 0x03EB). - * - * \b 2. USB_DEVICE_PRODUCT_ID (Word). - * - * Product ID (Referenced in usb_atmel.h). - * - * \b 3. USB_DEVICE_MAJOR_VERSION (Byte). - * - * Major version of the device. - * - * \b 4. USB_DEVICE_MINOR_VERSION (Byte). - * - * Minor version of the device. - * - * \b 5. USB_DEVICE_MANUFACTURE_NAME (string). - * - * ASCII name for the manufacture. - * - * \b 6. USB_DEVICE_PRODUCT_NAME (string). - * - * ASCII name for the product. - * - * \b 7. USB_DEVICE_SERIAL_NAME (string). - * - * ASCII name to enable and set a serial number. - * - * \b 8. USB_DEVICE_POWER (Numeric). - * - * (unit mA) Maximum device power. - * - * \b 9. USB_DEVICE_ATTR (Byte). - * - * USB attributes available: - * - USB_CONFIG_ATTR_SELF_POWERED - * - USB_CONFIG_ATTR_REMOTE_WAKEUP - * - * \note If remote wake is enabled, this defines remotewakeup callbacks. - * - * \b 10. USB_DEVICE_LOW_SPEED (Only defined). - * - * Force the USB Device to run in low speed. - * - * \b 11. USB_DEVICE_HS_SUPPORT (Only defined). - * - * Authorize the USB Device to run in high speed. - * - * \b 12. USB_DEVICE_MAX_EP (Byte). - * - * Define the maximum endpoint number used by the USB Device. - * - * This one is already defined in the UDI default configuration. - * E.g.: - * - When endpoint control 0x00, endpoint 0x01, and - * endpoint 0x82 is used, then USB_DEVICE_MAX_EP=2 - * - When only endpoint control 0x00 is used, then USB_DEVICE_MAX_EP=0 - * - When endpoint 0x01 and endpoint 0x81 is used, then USB_DEVICE_MAX_EP=1 - * (configuration not possible on USBB interface) - * - * \section asfdoc_udc_vbus_monitoring VBUS Monitoring - * - * The VBUS monitoring is used only for USB SELF Power application. - * - * - By default the USB device is automatically attached when VBUS is high - * or when USB starts for devices without internal VBUS monitoring. - * conf_usb.h file does not contain definition USB_DEVICE_ATTACH_AUTO_DISABLE. - * \code - //#define USB_DEVICE_ATTACH_AUTO_DISABLE - \endcode - * - * - Add custom VBUS monitoring. conf_usb.h file contains define - * USB_DEVICE_ATTACH_AUTO_DISABLE: - * \code -#define USB_DEVICE_ATTACH_AUTO_DISABLE - \endcode - * User C-file contains: - * \code -// Authorize VBUS monitoring -if (!udc_include_vbus_monitoring()) { - // Implement custom VBUS monitoring via GPIO or other -} -Event_VBUS_present() // VBUS interrupt or GPIO interrupt or other -{ - // Attach USB Device - udc_attach(); -} - \endcode - * - * - Case of battery charging. conf_usb.h file contains define - * USB_DEVICE_ATTACH_AUTO_DISABLE: - * \code #define USB_DEVICE_ATTACH_AUTO_DISABLE \endcode - * User C-file contains: - * \code - Event VBUS present() // VBUS interrupt or GPIO interrupt or .. - { - // Authorize battery charging, but wait key press to start USB. - } - Event Key press() - { - // Stop batteries charging - // Start USB - udc_attach(); - } - \endcode - * - * \section asfdoc_udc_basic_use_case_setup USB Device Setup Steps - * - * \subsection asfdoc_udc_basic_use_case_setup_prereq USB Device Controller (UDC) - Prerequisites - * - * Common prerequisites for all USB devices. - * - * This module is based on USB device stack full interrupt driven, and supporting - * \ref sleepmgr_group "sleepmgr". - * For AVR® and Atmel® | SMART ARM®-based SAM3/4 devices the - * \ref clk_group "clock services" is supported. - * For SAM D21 devices the \ref asfdoc_sam0_system_clock_group "clock driver" is supported. - * - * The following procedure must be executed to set up the project correctly: - * - Specify the clock configuration: - * - XMEGA® USB devices need 48MHz clock input. - * XMEGA USB devices need CPU frequency higher than 12MHz. - * You can use either an internal RC 48MHz auto calibrated by Start of Frames - * or an external OSC. - * - UC3 and SAM3/4 devices without USB high speed support need 48MHz clock input. - * You must use a PLL and an external OSC. - * - UC3 and SAM3/4 devices with USB high speed support need 12MHz clock input. - * You must use an external OSC. - * - UC3 devices with USBC hardware need CPU frequency higher than 25MHz - * - SAM D21 devices without USB high speed support need 48MHz clock input. - * You should use DFLL with USBCRM. - * - In conf_board.h, the define CONF_BOARD_USB_PORT must be added to enable USB lines. - * (Not mandatory for all boards). - * - Enable interrupts - * - Initialize the clock service - * - * The usage of \ref sleepmgr_group "sleep manager" service is optional, but recommended to reduce power - * consumption: - * - Initialize the sleep manager service - * - Activate sleep mode when the application is in IDLE state - * - * For AVR and SAM3/4 devices, add to the initialization code: - * \code - sysclk_init(); - irq_initialize_vectors(); - cpu_irq_enable(); - board_init(); - sleepmgr_init(); // Optional - \endcode - * - * For SAM D21 devices, add to the initialization code: - * \code - system_init(); - irq_initialize_vectors(); - cpu_irq_enable(); - sleepmgr_init(); // Optional - \endcode - * - * Add to the main IDLE loop: - * \code - sleepmgr_enter_sleep(); // Optional - \endcode - * - * \subsection asfdoc_udc_basic_use_case_setup_code USB Device Controller (UDC) - Example Code - * Common example code for all USB devices. - * - * Content of conf_usb.h: - * \code - #define USB_DEVICE_VENDOR_ID 0x03EB - #define USB_DEVICE_PRODUCT_ID 0xXXXX - #define USB_DEVICE_MAJOR_VERSION 1 - #define USB_DEVICE_MINOR_VERSION 0 - #define USB_DEVICE_POWER 100 - #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED - \endcode - * - * Add to application C-file: - * \code - void usb_init(void) - { - udc_start(); - } - \endcode - * - * \subsection asfdoc_udc_basic_use_case_setup_flow USB Device Controller (UDC) - Workflow - * Common workflow for all USB devices. - * - * -# Ensure that conf_usb.h is available and contains the following configuration, - * which is the main USB device configuration: - * \code - // Vendor ID provided by USB org (Atmel 0x03EB) - #define USB_DEVICE_VENDOR_ID 0x03EB // Type Word - // Product ID (Atmel PID referenced in usb_atmel.h) - #define USB_DEVICE_PRODUCT_ID 0xXXXX // Type Word - // Major version of the device - #define USB_DEVICE_MAJOR_VERSION 1 // Type Byte - // Minor version of the device - #define USB_DEVICE_MINOR_VERSION 0 // Type Byte - // Maximum device power (mA) - #define USB_DEVICE_POWER 100 // Type 9-bits - // USB attributes to enable features - #define USB_DEVICE_ATTR USB_CONFIG_ATTR_BUS_POWERED // Flags - \endcode - * - * -# Call the USB device stack start function to enable stack and start USB: - * \code - udc_start(); - \endcode - * - * \note In case of USB dual roles (Device and Host) managed through USB OTG connector - * (USB ID pin), the call of udc_start() must be removed and replaced by uhc_start(). - * Refer to section "Dual roles" for further information in the application note: - * - * Atmel AVR4950: ASF - USB Host Stack - * - * \section udc_conf_clock conf_clock.h Examples - * - * Content of XMEGA conf_clock.h: - * \code - // Configuration based on internal RC: - // USB clock need of 48MHz - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_RCOSC - #define CONFIG_OSC_RC32_CAL 48000000UL - #define CONFIG_OSC_AUTOCAL_RC32MHZ_REF_OSC OSC_ID_USBSOF - // CPU clock need of clock > 12MHz to run with USB (Here 24MHz) - #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_RC32MHZ - #define CONFIG_SYSCLK_PSADIV SYSCLK_PSADIV_2 - #define CONFIG_SYSCLK_PSBCDIV SYSCLK_PSBCDIV_1_1 - \endcode - * - * Content of conf_clock.h for AT32UC3A0, AT32UC3A1, and AT32UC3B devices (USBB): - * \code - // Configuration based on 12MHz external OSC: - #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0 - #define CONFIG_PLL1_MUL 8 - #define CONFIG_PLL1_DIV 2 - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 - #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) - \endcode - * - * Content of conf_clock.h for AT32UC3A3 and AT32UC3A4 devices (USBB with high speed support): - * \code - // Configuration based on 12MHz external OSC: - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_OSC0 - #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) - \endcode - * - * Content of conf_clock.h for AT32UC3C, ATUCXXD, ATUCXXL3U, and ATUCXXL4U devices (USBC): - * \code - // Configuration based on 12MHz external OSC: - #define CONFIG_PLL1_SOURCE PLL_SRC_OSC0 - #define CONFIG_PLL1_MUL 8 - #define CONFIG_PLL1_DIV 2 - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 - #define CONFIG_USBCLK_DIV 1 // Fusb = Fsys/(2 ^ USB_div) - // CPU clock need of clock > 25MHz to run with USBC - #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLL1 - \endcode - * - * Content of conf_clock.h for SAM3S, SAM3SD, and SAM4S devices (UPD: USB Peripheral Device): - * \code - // PLL1 (B) Options (Fpll = (Fclk * PLL_mul) / PLL_div) - #define CONFIG_PLL1_SOURCE PLL_SRC_MAINCK_XTAL - #define CONFIG_PLL1_MUL 16 - #define CONFIG_PLL1_DIV 2 - // USB Clock Source Options (Fusb = FpllX / USB_div) - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL1 - #define CONFIG_USBCLK_DIV 2 - \endcode - * - * Content of conf_clock.h for SAM3U device (UPDHS: USB Peripheral Device High Speed): - * \code - // USB Clock Source fixed at UPLL. - \endcode - * - * Content of conf_clock.h for SAM3X and SAM3A devices (UOTGHS: USB OTG High Speed): - * \code - // USB Clock Source fixed at UPLL. - #define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL - #define CONFIG_USBCLK_DIV 1 - \endcode - * - * Content of conf_clocks.h for SAM D21 devices (USB): - * \code - // System clock bus configuration - # define CONF_CLOCK_FLASH_WAIT_STATES 2 - - // USB Clock Source fixed at DFLL. - // SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop - # define CONF_CLOCK_DFLL_ENABLE true - # define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY - # define CONF_CLOCK_DFLL_ON_DEMAND true - - // Set this to true to configure the GCLK when running clocks_init. - // If set to false, none of the GCLK generators will be configured in clocks_init(). - # define CONF_CLOCK_CONFIGURE_GCLK true - - // Configure GCLK generator 0 (Main Clock) - # define CONF_CLOCK_GCLK_0_ENABLE true - # define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true - # define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL - # define CONF_CLOCK_GCLK_0_PRESCALER 1 - # define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false - \endcode - * - */ - -/** - * \if ASF_MANUAL - * \page asfdoc_udc_use_cases USB Device Advanced Use Cases - * - \subpage udc_use_case_1 - * - \subpage udc_use_case_2 - * - \subpage udc_use_case_3 - * - \subpage udc_use_case_5 - * - \subpage udc_use_case_6 - * \endif - */ - -/** - * \page udc_use_case_1 Change USB Speed - * - * In this use case, the USB device is used with different USB speeds. - * - * \section udc_use_case_1_setup Setup Steps - * - * Prior to implement this use case, be sure to have already - * applied the UDI module "basic use case". - * - * \section udc_use_case_1_usage Usage Steps - * - * \subsection udc_use_case_1_usage_code Example Code - * Content of conf_usb.h: - * \code - #if // Low speed - #define USB_DEVICE_LOW_SPEED - // #define USB_DEVICE_HS_SUPPORT - - #elif // Full speed - // #define USB_DEVICE_LOW_SPEED - // #define USB_DEVICE_HS_SUPPORT - #elif // High speed - // #define USB_DEVICE_LOW_SPEED - #define USB_DEVICE_HS_SUPPORT - - #endif - \endcode - * - * \subsection udc_use_case_1_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required for a USB device low speed (1.5Mbit/s): - * \code - #define USB_DEVICE_LOW_SPEED - //#define USB_DEVICE_HS_SUPPORT - \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB device full speed (12Mbit/s): - * \code - //#define USB_DEVICE_LOW_SPEED - //#define USB_DEVICE_HS_SUPPORT - \endcode - * -# Ensure that conf_usb.h contains the following parameters - * required for a USB device high speed (480Mbit/s): - * \code - //#define USB_DEVICE_LOW_SPEED - #define USB_DEVICE_HS_SUPPORT - \endcode - */ - -/** - * \page udc_use_case_2 Use USB Strings - * - * In this use case, the usual USB strings are added in the USB device. - * - * \section udc_use_case_2_setup Setup Steps - * Prior to implement this use case, be sure to have already - * applied the UDI module "basic use case". - * - * \section udc_use_case_2_usage Usage Steps - * - * \subsection udc_use_case_2_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" - #define USB_DEVICE_PRODUCT_NAME "Product name" - #define USB_DEVICE_SERIAL_NAME "12...EF" - \endcode - * - * \subsection udc_use_case_2_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required to enable different USB strings: - * \code - // Static ASCII name for the manufacture - #define USB_DEVICE_MANUFACTURE_NAME "Manufacture name" - \endcode - * \code - // Static ASCII name for the product - #define USB_DEVICE_PRODUCT_NAME "Product name" - \endcode - * \code - // Static ASCII name to enable and set a serial number - #define USB_DEVICE_SERIAL_NAME "12...EF" \endcode - */ - -/** - * \page udc_use_case_3 Use USB Remote Wakeup Feature - * - * In this use case, the USB remote wakeup feature is enabled. - * - * \section udc_use_case_3_setup Setup Steps - * Prior to implement this use case, be sure to have already - * applied the UDI module "basic use case". - * - * \section udc_use_case_3_usage Usage Steps - * - * \subsection udc_use_case_3_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) - #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable() - extern void my_callback_remotewakeup_enable(void); - #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable() - extern void my_callback_remotewakeup_disable(void); - \endcode - * - * Add to application C-file: - * \code - void my_callback_remotewakeup_enable(void) - { - // Enable application wakeup events (e.g. enable GPIO interrupt) - } - void my_callback_remotewakeup_disable(void) - { - // Disable application wakeup events (e.g. disable GPIO interrupt) - } - - void my_interrupt_event(void) - { - udc_remotewakeup(); - } - \endcode - - * - * \subsection udc_use_case_3_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required to enable the remote wakeup feature: - * \code - // Authorizes the remote wakeup feature - #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_REMOTE_WAKEUP | USB_CONFIG_ATTR_..._POWERED) - \endcode - * \code - // Define callback called when the host enables the remotewakeup feature - #define UDC_REMOTEWAKEUP_ENABLE() my_callback_remotewakeup_enable() - extern void my_callback_remotewakeup_enable(void); - \endcode - * \code - // Define callback called when the host disables the remotewakeup feature - #define UDC_REMOTEWAKEUP_DISABLE() my_callback_remotewakeup_disable() - extern void my_callback_remotewakeup_disable(void); - \endcode - * -# Send a remote wakeup (USB upstream): - * \code - udc_remotewakeup(); - \endcode - */ - -/** - * \page udc_use_case_5 Bus Power Application Recommendations - * - * In this use case, the USB device bus power feature is enabled. - * This feature requires a correct power consumption management. - * - * \section udc_use_case_5_setup Setup Steps - * Prior to implement this use case, be sure to have already - * applied the UDI module "basic use case". - * - * \section udc_use_case_5_usage Usage Steps - * - * \subsection udc_use_case_5_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) - #define UDC_SUSPEND_EVENT() user_callback_suspend_action() - extern void user_callback_suspend_action(void) - #define UDC_RESUME_EVENT() user_callback_resume_action() - extern void user_callback_resume_action(void) - \endcode - * - * Add to application C-file: - * \code - void user_callback_suspend_action(void) - { - // Disable hardware component to reduce power consumption - } - void user_callback_resume_action(void) - { - // Re-enable hardware component - } - \endcode - * - * \subsection udc_use_case_5_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters: - * \code - // Authorizes the BUS power feature - #define USB_DEVICE_ATTR (USB_CONFIG_ATTR_BUS_POWERED) - \endcode - * \code - // Define callback called when the host suspend the USB line - #define UDC_SUSPEND_EVENT() user_callback_suspend_action() - extern void user_callback_suspend_action(void); - \endcode - * \code - // Define callback called when the host or device resume the USB line - #define UDC_RESUME_EVENT() user_callback_resume_action() - extern void user_callback_resume_action(void); - \endcode - * -# Reduce power consumption in suspend mode (max. 2.5mA on VBUS): - * \code - void user_callback_suspend_action(void) - { - turn_off_components(); - } - \endcode - */ - -/** - * \page udc_use_case_6 USB Dynamic Serial Number - * - * In this use case, the USB serial strings are dynamic. - * For a static serial string refer to \ref udc_use_case_2. - * - * \section udc_use_case_6_setup Setup Steps - * Prior to implement this use case, be sure to have already - * applied the UDI module "basic use case". - * - * \section udc_use_case_6_usage Usage Steps - * - * \subsection udc_use_case_6_usage_code Example Code - * Content of conf_usb.h: - * \code - #define USB_DEVICE_SERIAL_NAME - #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number - #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 - extern uint8_t serial_number[]; - \endcode - * - * Add to application C-file: - * \code - uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - void init_build_usb_serial_number(void) - { - serial_number[0] = 'A'; - serial_number[1] = 'B'; - ... - serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C'; - } - \endcode - * - * \subsection udc_use_case_6_usage_flow Workflow - * -# Ensure that conf_usb.h is available and contains the following parameters - * required to enable a USB serial number string dynamically: - * \code - #define USB_DEVICE_SERIAL_NAME // Define this empty - #define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number // Give serial array pointer - #define USB_DEVICE_GET_SERIAL_NAME_LENGTH 12 // Give size of serial array - extern uint8_t serial_number[]; // Declare external serial array - \endcode - * -# Before starting USB stack, initialize the serial array: - * \code - uint8_t serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - void init_build_usb_serial_number(void) - { - serial_number[0] = 'A'; - serial_number[1] = 'B'; - ... - serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH-1] = 'C'; - } - \endcode - */ diff --git a/atmel-samd/asf/common/services/usb/udc/udd.h b/atmel-samd/asf/common/services/usb/udc/udd.h deleted file mode 100644 index 10807f43d79e2..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/udd.h +++ /dev/null @@ -1,396 +0,0 @@ -/** - * \file - * - * \brief Common API for USB Device Drivers (UDD) - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDD_H_ -#define _UDD_H_ - -#include "usb_protocol.h" -#include "udc_desc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup usb_device_group - * \defgroup udd_group USB Device Driver (UDD) - * - * The UDD driver provides a low-level abstraction of the device - * controller hardware. Most events coming from the hardware such as - * interrupts, which may cause the UDD to call into the UDC and UDI. - * - * @{ - */ - -//! \brief Endpoint identifier -typedef uint8_t udd_ep_id_t; - -//! \brief Endpoint transfer status -//! Returned in parameters of callback register via udd_ep_run routine. -typedef enum { - UDD_EP_TRANSFER_OK = 0, - UDD_EP_TRANSFER_ABORT = 1, -} udd_ep_status_t; - -/** - * \brief Global variable to give and record information of the setup request management - * - * This global variable allows to decode and response a setup request. - * It can be updated by udc_process_setup() from UDC or *setup() from UDIs. - */ -typedef struct { - //! Data received in USB SETUP packet - //! Note: The swap of "req.wValues" from uin16_t to le16_t is done by UDD. - usb_setup_req_t req; - - //! Point to buffer to send or fill with data following SETUP packet - //! This buffer must be word align for DATA IN phase (use prefix COMPILER_WORD_ALIGNED for buffer) - uint8_t *payload; - - //! Size of buffer to send or fill, and content the number of byte transfered - uint16_t payload_size; - - //! Callback called after reception of ZLP from setup request - void (*callback) (void); - - //! Callback called when the buffer given (.payload) is full or empty. - //! This one return false to abort data transfer, or true with a new buffer in .payload. - bool(*over_under_run) (void); -} udd_ctrl_request_t; -extern udd_ctrl_request_t udd_g_ctrlreq; - -//! Return true if the setup request \a udd_g_ctrlreq indicates IN data transfer -#define Udd_setup_is_in() \ - (USB_REQ_DIR_IN == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK)) - -//! Return true if the setup request \a udd_g_ctrlreq indicates OUT data transfer -#define Udd_setup_is_out() \ - (USB_REQ_DIR_OUT == (udd_g_ctrlreq.req.bmRequestType & USB_REQ_DIR_MASK)) - -//! Return the type of the SETUP request \a udd_g_ctrlreq. \see usb_reqtype. -#define Udd_setup_type() \ - (udd_g_ctrlreq.req.bmRequestType & USB_REQ_TYPE_MASK) - -//! Return the recipient of the SETUP request \a udd_g_ctrlreq. \see usb_recipient -#define Udd_setup_recipient() \ - (udd_g_ctrlreq.req.bmRequestType & USB_REQ_RECIP_MASK) - -/** - * \brief End of halt callback function type. - * Registered by routine udd_ep_wait_stall_clear() - * Callback called when endpoint stall is cleared. - */ -typedef void (*udd_callback_halt_cleared_t) (void); - -/** - * \brief End of transfer callback function type. - * Registered by routine udd_ep_run() - * Callback called by USB interrupt after data transfer or abort (reset,...). - * - * \param status UDD_EP_TRANSFER_OK, if transfer is complete - * \param status UDD_EP_TRANSFER_ABORT, if transfer is aborted - * \param n number of data transfered - */ -typedef void (*udd_callback_trans_t) (udd_ep_status_t status, - iram_size_t nb_transfered, udd_ep_id_t ep); - -/** - * \brief Authorizes the VBUS event - * - * \return true, if the VBUS monitoring is possible. - */ -bool udd_include_vbus_monitoring(void); - -/** - * \brief Enables the USB Device mode - */ -void udd_enable(void); - -/** - * \brief Disables the USB Device mode - */ -void udd_disable(void); - -/** - * \brief Attach device to the bus when possible - * - * \warning If a VBus control is included in driver, - * then it will attach device when an acceptable Vbus - * level from the host is detected. - */ -void udd_attach(void); - -/** - * \brief Detaches the device from the bus - * - * The driver must remove pull-up on USB line D- or D+. - */ -void udd_detach(void); - -/** - * \brief Test whether the USB Device Controller is running at high - * speed or not. - * - * \return \c true if the Device is running at high speed mode, otherwise \c false. - */ -bool udd_is_high_speed(void); - -/** - * \brief Changes the USB address of device - * - * \param address New USB address - */ -void udd_set_address(uint8_t address); - -/** - * \brief Returns the USB address of device - * - * \return USB address - */ -uint8_t udd_getaddress(void); - -/** - * \brief Returns the current start of frame number - * - * \return current start of frame number. - */ -uint16_t udd_get_frame_number(void); - -/** - * \brief Returns the current micro start of frame number - * - * \return current micro start of frame number required in high speed mode. - */ -uint16_t udd_get_micro_frame_number(void); - -/*! \brief The USB driver sends a resume signal called Upstream Resume - */ -void udd_send_remotewakeup(void); - -/** - * \brief Load setup payload - * - * \param payload Pointer on payload - * \param payload_size Size of payload - */ -void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size ); - - -/** - * \name Endpoint Management - * - * The following functions allow drivers to create and remove - * endpoints, as well as set, clear and query their "halted" and - * "wedged" states. - */ -//@{ - -#if (USB_DEVICE_MAX_EP != 0) - -/** - * \brief Configures and enables an endpoint - * - * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT). - * \param bmAttributes Attributes of endpoint declared in the descriptor. - * \param MaxEndpointSize Endpoint maximum size - * - * \return \c 1 if the endpoint is enabled, otherwise \c 0. - */ -bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, - uint16_t MaxEndpointSize); - -/** - * \brief Disables an endpoint - * - * \param ep Endpoint number including direction (USB_EP_DIR_IN/USB_EP_DIR_OUT). - */ -void udd_ep_free(udd_ep_id_t ep); - -/** - * \brief Check if the endpoint \a ep is halted. - * - * \param ep The ID of the endpoint to check. - * - * \return \c 1 if \a ep is halted, otherwise \c 0. - */ -bool udd_ep_is_halted(udd_ep_id_t ep); - -/** - * \brief Set the halted state of the endpoint \a ep - * - * After calling this function, any transaction on \a ep will result - * in a STALL handshake being sent. Any pending transactions will be - * performed first, however. - * - * \param ep The ID of the endpoint to be halted - * - * \return \c 1 if \a ep is halted, otherwise \c 0. - */ -bool udd_ep_set_halt(udd_ep_id_t ep); - -/** - * \brief Clear the halted state of the endpoint \a ep - * - * After calling this function, any transaction on \a ep will - * be handled normally, i.e. a STALL handshake will not be sent, and - * the data toggle sequence will start at DATA0. - * - * \param ep The ID of the endpoint to be un-halted - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udd_ep_clear_halt(udd_ep_id_t ep); - -/** - * \brief Registers a callback to call when endpoint halt is cleared - * - * \param ep The ID of the endpoint to use - * \param callback NULL or function to call when endpoint halt is cleared - * - * \warning if the endpoint is not halted then the \a callback is called immediately. - * - * \return \c 1 if the register is accepted, otherwise \c 0. - */ -bool udd_ep_wait_stall_clear(udd_ep_id_t ep, - udd_callback_halt_cleared_t callback); - -/** - * \brief Allows to receive or send data on an endpoint - * - * The driver uses a specific DMA USB to transfer data - * from internal RAM to endpoint, if this one is available. - * When the transfer is finished or aborted (stall, reset, ...), the \a callback is called. - * The \a callback returns the transfer status and eventually the number of byte transfered. - * Note: The control endpoint is not authorized. - * - * \param ep The ID of the endpoint to use - * \param b_shortpacket Enabled automatic short packet - * \param buf Buffer on Internal RAM to send or fill. - * It must be align, then use COMPILER_WORD_ALIGNED. - * \param buf_size Buffer size to send or fill - * \param callback NULL or function to call at the end of transfer - * - * \warning About \a b_shortpacket, for IN endpoint it means that a short packet - * (or a Zero Length Packet) will be sent to the USB line to properly close the usb - * transfer at the end of the data transfer. - * For Bulk and Interrupt OUT endpoint, it will automatically stop the transfer - * at the end of the data transfer (received short packet). - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, - uint8_t * buf, iram_size_t buf_size, - udd_callback_trans_t callback); -/** - * \brief Aborts transfer on going on endpoint - * - * If a transfer is on going, then it is stopped and - * the callback registered is called to signal the end of transfer. - * Note: The control endpoint is not authorized. - * - * \param ep Endpoint to abort - */ -void udd_ep_abort(udd_ep_id_t ep); - -#endif - -//@} - - -/** - * \name High speed test mode management - * - * The following functions allow the device to jump to a specific test mode required in high speed mode. - */ -//@{ -void udd_test_mode_j(void); -void udd_test_mode_k(void); -void udd_test_mode_se0_nak(void); -void udd_test_mode_packet(void); -//@} - - -/** - * \name UDC callbacks to provide for UDD - * - * The following callbacks are used by UDD. - */ -//@{ - -/** - * \brief Decodes and manages a setup request - * - * The driver call it when a SETUP packet is received. - * The \c udd_g_ctrlreq contains the data of SETUP packet. - * If this callback accepts the setup request then it must - * return \c 1 and eventually update \c udd_g_ctrlreq to send or receive data. - * - * \return \c 1 if the request is accepted, otherwise \c 0. - */ -extern bool udc_process_setup(void); - -/** - * \brief Reset the UDC - * - * The UDC must reset all configuration. - */ -extern void udc_reset(void); - -/** - * \brief To signal that a SOF is occurred - * - * The UDC must send the signal to all UDIs enabled - */ -extern void udc_sof_notify(void); - -//@} - -//@} - -#ifdef __cplusplus -} -#endif -#endif // _UDD_H_ diff --git a/atmel-samd/asf/common/services/usb/udc/udi.h b/atmel-samd/asf/common/services/usb/udc/udi.h deleted file mode 100644 index 1fc7ae5d01a43..0000000000000 --- a/atmel-samd/asf/common/services/usb/udc/udi.h +++ /dev/null @@ -1,133 +0,0 @@ -/** - * \file - * - * \brief Common API for USB Device Interface - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _UDI_H_ -#define _UDI_H_ - -#include "conf_usb.h" -#include "usb_protocol.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup usb_device_group - * \defgroup udi_group USB Device Interface (UDI) - * The UDI provides a common API for all classes, - * and this is used by UDC for the main control of USB Device interface. - * @{ - */ - -/** - * \brief UDI API. - * - * The callbacks within this structure are called only by - * USB Device Controller (UDC) - * - * The udc_get_interface_desc() can be use by UDI to know the interface descriptor - * selected by UDC. - */ -typedef struct { - /** - * \brief Enable the interface. - * - * This function is called when the host selects a configuration - * to which this interface belongs through a Set Configuration - * request, and when the host selects an alternate setting of - * this interface through a Set Interface request. - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ - bool(*enable) (void); - - /** - * \brief Disable the interface. - * - * This function is called when this interface is currently - * active, and - * - the host selects any configuration through a Set - * Configuration request, or - * - the host issues a USB reset, or - * - the device is detached from the host (i.e. Vbus is no - * longer present) - */ - void (*disable) (void); - - /** - * \brief Handle a control request directed at an interface. - * - * This function is called when this interface is currently - * active and the host sends a SETUP request - * with this interface as the recipient. - * - * Use udd_g_ctrlreq to decode and response to SETUP request. - * - * \return \c 1 if this interface supports the SETUP request, otherwise \c 0. - */ - bool(*setup) (void); - - /** - * \brief Returns the current setting of the selected interface. - * - * This function is called when UDC when know alternate setting of selected interface. - * - * \return alternate setting of selected interface - */ - uint8_t(*getsetting) (void); - - /** - * \brief To signal that a SOF is occurred - */ - void(*sof_notify) (void); -} udi_api_t; - -//@} - -#ifdef __cplusplus -} -#endif -#endif // _UDI_H_ diff --git a/atmel-samd/asf/common/services/usb/usb_atmel.h b/atmel-samd/asf/common/services/usb/usb_atmel.h deleted file mode 100644 index 2fe72192a8d83..0000000000000 --- a/atmel-samd/asf/common/services/usb/usb_atmel.h +++ /dev/null @@ -1,191 +0,0 @@ -/** - * \file - * - * \brief All USB VIDs and PIDs from Atmel USB applications - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_ATMEL_H_ -#define _USB_ATMEL_H_ - -/** - * \defgroup usb_group USB Stack - * - * This stack includes the USB Device Stack, USB Host Stack and common - * definitions. - * @{ - */ - -//! @} - -/** - * \ingroup usb_group - * \defgroup usb_atmel_ids_group Atmel USB Identifiers - * - * This module defines Atmel PID and VIDs constants. - * - * @{ - */ - -//! \name Vendor Identifier assigned by USB org to ATMEL -#define USB_VID_ATMEL 0x03EB - - -//! \name Product Identifier assigned by ATMEL to AVR applications -//! @{ - -//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others. -//! @{ -#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013 -#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017 -#define USB_PID_ATMEL_MEGA_CDC 0x2018 -#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019 -#define USB_PID_ATMEL_MEGA_MS 0x201A -#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B -#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C -#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D -#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E -#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022 -#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023 -#define USB_PID_ATMEL_MEGA_MS_2 0x2029 -#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A -#define USB_PID_ATMEL_MEGA_MS_3 0x2032 -#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050 -//! @} - -//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools. -//! @{ -#define USB_PID_ATMEL_XPLAINED 0x2122 -#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A -#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B -//! @} - -//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=> -//! @{ -#define USB_PID_ATMEL_UC3_ENUM 0x2300 -#define USB_PID_ATMEL_UC3_MS 0x2301 -#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302 -#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303 -#define USB_PID_ATMEL_UC3_HID 0x2304 -#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305 -#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306 -#define USB_PID_ATMEL_UC3_CDC 0x2307 -#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308 -#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx -#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311 -#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312 -//! @} - -//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications -//! @{ -#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400 -#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401 -#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402 -#define USB_PID_ATMEL_ASF_MSC 0x2403 -#define USB_PID_ATMEL_ASF_CDC 0x2404 -#define USB_PID_ATMEL_ASF_PHDC 0x2405 -#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406 -#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420 -#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421 -#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422 -#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423 -#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424 -#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425 -#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432 -#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433 -#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434 -//! @} - -//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders -//! Note, !!!! don't use this range for demos or examples !!!! -//! @{ -#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6 -#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7 -#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8 -#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9 -#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA -#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB -#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC -#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD -#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE - -#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF -#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0 -#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1 -#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2 -#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3 -#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4 -#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5 -#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6 -#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7 -#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8 -#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9 -#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA -#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB -#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC -#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED -#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE -#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF -#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0 -#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1 -#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2 -#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3 -#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4 -#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5 -#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6 -#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7 -#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8 -#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9 -#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA -#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB -// 2FFCh to 2FFFh used by C51 family products -//! @} - -//! @} - -//! @} - - -#endif // _USB_ATMEL_H_ diff --git a/atmel-samd/asf/common/services/usb/usb_protocol.h b/atmel-samd/asf/common/services/usb/usb_protocol.h deleted file mode 100644 index 32fafa565b257..0000000000000 --- a/atmel-samd/asf/common/services/usb/usb_protocol.h +++ /dev/null @@ -1,499 +0,0 @@ -/** - * \file - * - * \brief USB protocol definitions. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_PROTOCOL_H_ -#define _USB_PROTOCOL_H_ - -#include "compiler.h" -#include "usb_atmel.h" - -/** - * \ingroup usb_group - * \defgroup usb_protocol_group USB Protocol Definitions - * - * This module defines constants and data structures provided by the USB - * 2.0 specification. - * - * @{ - */ - -//! Value for field bcdUSB -#define USB_V2_0 0x0200 //!< USB Specification version 2.00 -#define USB_V2_1 0x0201 //!< USB Specification version 2.01 - -/*! \name Generic definitions (Class, subclass and protocol) - */ -//! @{ -#define NO_CLASS 0x00 -#define CLASS_VENDOR_SPECIFIC 0xFF -#define NO_SUBCLASS 0x00 -#define NO_PROTOCOL 0x00 -//! @} - -//! \name IAD (Interface Association Descriptor) constants -//! @{ -#define CLASS_IAD 0xEF -#define SUB_CLASS_IAD 0x02 -#define PROTOCOL_IAD 0x01 -//! @} - -/** - * \brief USB request data transfer direction (bmRequestType) - */ -#define USB_REQ_DIR_OUT (0<<7) //!< Host to device -#define USB_REQ_DIR_IN (1<<7) //!< Device to host -#define USB_REQ_DIR_MASK (1<<7) //!< Mask - -/** - * \brief USB request types (bmRequestType) - */ -#define USB_REQ_TYPE_STANDARD (0<<5) //!< Standard request -#define USB_REQ_TYPE_CLASS (1<<5) //!< Class-specific request -#define USB_REQ_TYPE_VENDOR (2<<5) //!< Vendor-specific request -#define USB_REQ_TYPE_MASK (3<<5) //!< Mask - -/** - * \brief USB recipient codes (bmRequestType) - */ -#define USB_REQ_RECIP_DEVICE (0<<0) //!< Recipient device -#define USB_REQ_RECIP_INTERFACE (1<<0) //!< Recipient interface -#define USB_REQ_RECIP_ENDPOINT (2<<0) //!< Recipient endpoint -#define USB_REQ_RECIP_OTHER (3<<0) //!< Recipient other -#define USB_REQ_RECIP_MASK (0x1F) //!< Mask - -/** - * \brief Standard USB requests (bRequest) - */ -enum usb_reqid { - USB_REQ_GET_STATUS = 0, - USB_REQ_CLEAR_FEATURE = 1, - USB_REQ_SET_FEATURE = 3, - USB_REQ_SET_ADDRESS = 5, - USB_REQ_GET_DESCRIPTOR = 6, - USB_REQ_SET_DESCRIPTOR = 7, - USB_REQ_GET_CONFIGURATION = 8, - USB_REQ_SET_CONFIGURATION = 9, - USB_REQ_GET_INTERFACE = 10, - USB_REQ_SET_INTERFACE = 11, - USB_REQ_SYNCH_FRAME = 12, -}; - -/** - * \brief Standard USB device status flags - * - */ -enum usb_device_status { - USB_DEV_STATUS_BUS_POWERED = 0, - USB_DEV_STATUS_SELF_POWERED = 1, - USB_DEV_STATUS_REMOTEWAKEUP = 2 -}; - -/** - * \brief Standard USB Interface status flags - * - */ -enum usb_interface_status { - USB_IFACE_STATUS_RESERVED = 0 -}; - -/** - * \brief Standard USB endpoint status flags - * - */ -enum usb_endpoint_status { - USB_EP_STATUS_HALTED = 1, -}; - -/** - * \brief Standard USB device feature flags - * - * \note valid for SetFeature request. - */ -enum usb_device_feature { - USB_DEV_FEATURE_REMOTE_WAKEUP = 1, //!< Remote wakeup enabled - USB_DEV_FEATURE_TEST_MODE = 2, //!< USB test mode - USB_DEV_FEATURE_OTG_B_HNP_ENABLE = 3, - USB_DEV_FEATURE_OTG_A_HNP_SUPPORT = 4, - USB_DEV_FEATURE_OTG_A_ALT_HNP_SUPPORT = 5 -}; - -/** - * \brief Test Mode possible on HS USB device - * - * \note valid for USB_DEV_FEATURE_TEST_MODE request. - */ -enum usb_device_hs_test_mode { - USB_DEV_TEST_MODE_J = 1, - USB_DEV_TEST_MODE_K = 2, - USB_DEV_TEST_MODE_SE0_NAK = 3, - USB_DEV_TEST_MODE_PACKET = 4, - USB_DEV_TEST_MODE_FORCE_ENABLE = 5, -}; - -/** - * \brief Standard USB endpoint feature/status flags - */ -enum usb_endpoint_feature { - USB_EP_FEATURE_HALT = 0, -}; - -/** - * \brief Standard USB Test Mode Selectors - */ -enum usb_test_mode_selector { - USB_TEST_J = 0x01, - USB_TEST_K = 0x02, - USB_TEST_SE0_NAK = 0x03, - USB_TEST_PACKET = 0x04, - USB_TEST_FORCE_ENABLE = 0x05, -}; - -/** - * \brief Standard USB descriptor types - */ -enum usb_descriptor_type { - USB_DT_DEVICE = 1, - USB_DT_CONFIGURATION = 2, - USB_DT_STRING = 3, - USB_DT_INTERFACE = 4, - USB_DT_ENDPOINT = 5, - USB_DT_DEVICE_QUALIFIER = 6, - USB_DT_OTHER_SPEED_CONFIGURATION = 7, - USB_DT_INTERFACE_POWER = 8, - USB_DT_OTG = 9, - USB_DT_IAD = 0x0B, - USB_DT_BOS = 0x0F, - USB_DT_DEVICE_CAPABILITY = 0x10, -}; - -/** - * \brief USB Device Capability types - */ -enum usb_capability_type { - USB_DC_USB20_EXTENSION = 0x02, -}; - -/** - * \brief USB Device Capability - USB 2.0 Extension - * To fill bmAttributes field of usb_capa_ext_desc_t structure. - */ -enum usb_capability_extension_attr { - USB_DC_EXT_LPM = 0x00000002, -}; - -#define HIRD_50_US 0 -#define HIRD_125_US 1 -#define HIRD_200_US 2 -#define HIRD_275_US 3 -#define HIRD_350_US 4 -#define HIRD_425_US 5 -#define HIRD_500_US 6 -#define HIRD_575_US 7 -#define HIRD_650_US 8 -#define HIRD_725_US 9 -#define HIRD_800_US 10 -#define HIRD_875_US 11 -#define HIRD_950_US 12 -#define HIRD_1025_US 13 -#define HIRD_1100_US 14 -#define HIRD_1175_US 15 - -/** Fields definition from a LPM TOKEN */ -#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0) -#define USB_LPM_ATTRIBUT_FIRD_MASK (0xF << 4) -#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8) -#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0) -#define USB_LPM_ATTRIBUT_FIRD(value) ((value & 0xF) << 4) -#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8) -#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1) - -/** - * \brief Standard USB endpoint transfer types - */ -enum usb_ep_type { - USB_EP_TYPE_CONTROL = 0x00, - USB_EP_TYPE_ISOCHRONOUS = 0x01, - USB_EP_TYPE_BULK = 0x02, - USB_EP_TYPE_INTERRUPT = 0x03, - USB_EP_TYPE_MASK = 0x03, -}; - -/** - * \brief Standard USB language IDs for string descriptors - */ -enum usb_langid { - USB_LANGID_EN_US = 0x0409, //!< English (United States) -}; - -/** - * \brief Mask selecting the index part of an endpoint address - */ -#define USB_EP_ADDR_MASK 0x0f - -//! \brief USB address identifier -typedef uint8_t usb_add_t; - -/** - * \brief Endpoint transfer direction is IN - */ -#define USB_EP_DIR_IN 0x80 - -/** - * \brief Endpoint transfer direction is OUT - */ -#define USB_EP_DIR_OUT 0x00 - -//! \brief Endpoint identifier -typedef uint8_t usb_ep_t; - -/** - * \brief Maximum length in bytes of a USB descriptor - * - * The maximum length of a USB descriptor is limited by the 8-bit - * bLength field. - */ -#define USB_MAX_DESC_LEN 255 - -/* - * 2-byte alignment requested for all USB structures. - */ -COMPILER_PACK_SET(1) - -/** - * \brief A USB Device SETUP request - * - * The data payload of SETUP packets always follows this structure. - */ -typedef struct { - uint8_t bmRequestType; - uint8_t bRequest; - le16_t wValue; - le16_t wIndex; - le16_t wLength; -} usb_setup_req_t; - -/** - * \brief Standard USB device descriptor structure - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - le16_t idVendor; - le16_t idProduct; - le16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} usb_dev_desc_t; - -/** - * \brief Standard USB device qualifier descriptor structure - * - * This descriptor contains information about the device when running at - * the "other" speed (i.e. if the device is currently operating at high - * speed, this descriptor can be used to determine what would change if - * the device was operating at full speed.) - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; -} usb_dev_qual_desc_t; - -/** - * \brief USB Device BOS descriptor structure - * - * The BOS descriptor (Binary device Object Store) defines a root - * descriptor that is similar to the configuration descriptor, and is - * the base descriptor for accessing a family of related descriptors. - * A host can read a BOS descriptor and learn from the wTotalLength field - * the entire size of the device-level descriptor set, or it can read in - * the entire BOS descriptor set of device capabilities. - * The host accesses this descriptor using the GetDescriptor() request. - * The descriptor type in the GetDescriptor() request is set to BOS. - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t wTotalLength; - uint8_t bNumDeviceCaps; -} usb_dev_bos_desc_t; - - -/** - * \brief USB Device Capabilities - USB 2.0 Extension Descriptor structure - * - * Defines the set of USB 1.1-specific device level capabilities. - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - le32_t bmAttributes; -} usb_dev_capa_ext_desc_t; - -/** - * \brief USB Device LPM Descriptor structure - * - * The BOS descriptor and capabilities descriptors for LPM. - */ -typedef struct { - usb_dev_bos_desc_t bos; - usb_dev_capa_ext_desc_t capa_ext; -} usb_dev_lpm_desc_t; - -/** - * \brief Standard USB Interface Association Descriptor structure - */ -typedef struct { - uint8_t bLength; //!< size of this descriptor in bytes - uint8_t bDescriptorType; //!< INTERFACE descriptor type - uint8_t bFirstInterface; //!< Number of interface - uint8_t bInterfaceCount; //!< value to select alternate setting - uint8_t bFunctionClass; //!< Class code assigned by the USB - uint8_t bFunctionSubClass;//!< Sub-class code assigned by the USB - uint8_t bFunctionProtocol;//!< Protocol code assigned by the USB - uint8_t iFunction; //!< Index of string descriptor -} usb_association_desc_t; - - -/** - * \brief Standard USB configuration descriptor structure - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; -} usb_conf_desc_t; - - -#define USB_CONFIG_ATTR_MUST_SET (1 << 7) //!< Must always be set -#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) //!< Bus-powered -#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) //!< Self-powered -#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) //!< remote wakeup supported - -#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) //!< Max power in mA - -/** - * \brief Standard USB association descriptor structure - */ -typedef struct { - uint8_t bLength; //!< Size of this descriptor in bytes - uint8_t bDescriptorType; //!< Interface descriptor type - uint8_t bFirstInterface; //!< Number of interface - uint8_t bInterfaceCount; //!< value to select alternate setting - uint8_t bFunctionClass; //!< Class code assigned by the USB - uint8_t bFunctionSubClass; //!< Sub-class code assigned by the USB - uint8_t bFunctionProtocol; //!< Protocol code assigned by the USB - uint8_t iFunction; //!< Index of string descriptor -} usb_iad_desc_t; - -/** - * \brief Standard USB interface descriptor structure - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} usb_iface_desc_t; - -/** - * \brief Standard USB endpoint descriptor structure - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - le16_t wMaxPacketSize; - uint8_t bInterval; -} usb_ep_desc_t; - - -/** - * \brief A standard USB string descriptor structure - */ -typedef struct { - uint8_t bLength; - uint8_t bDescriptorType; -} usb_str_desc_t; - -typedef struct { - usb_str_desc_t desc; - le16_t string[1]; -} usb_str_lgid_desc_t; - -COMPILER_PACK_RESET() - -//! @} - -#endif /* _USB_PROTOCOL_H_ */ diff --git a/atmel-samd/asf/common/utils/interrupt.h b/atmel-samd/asf/common/utils/interrupt.h deleted file mode 100644 index a88c6f0c5990c..0000000000000 --- a/atmel-samd/asf/common/utils/interrupt.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for 8- and 32-bit AVR - * - * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UTILS_INTERRUPT_H -#define UTILS_INTERRUPT_H - -#include - -#if XMEGA || MEGA -# include "interrupt/interrupt_avr8.h" -#elif UC3 -# include "interrupt/interrupt_avr32.h" -#elif SAM || SAMB -# include "interrupt/interrupt_sam_nvic.h" -#else -# error Unsupported device. -#endif - -/** - * \defgroup interrupt_group Global interrupt management - * - * This is a driver for global enabling and disabling of interrupts. - * - * @{ - */ - -#if defined(__DOXYGEN__) -/** - * \def CONFIG_INTERRUPT_FORCE_INTC - * \brief Force usage of the ASF INTC driver - * - * Predefine this symbol when preprocessing to force the use of the ASF INTC driver. - * This is useful to ensure compatibility across compilers and shall be used only when required - * by the application needs. - */ -# define CONFIG_INTERRUPT_FORCE_INTC -#endif - -//! \name Global interrupt flags -//@{ -/** - * \typedef irqflags_t - * \brief Type used for holding state of interrupt flag - */ - -/** - * \def cpu_irq_enable - * \brief Enable interrupts globally - */ - -/** - * \def cpu_irq_disable - * \brief Disable interrupts globally - */ - -/** - * \fn irqflags_t cpu_irq_save(void) - * \brief Get and clear the global interrupt flags - * - * Use in conjunction with \ref cpu_irq_restore. - * - * \return Current state of interrupt flags. - * - * \note This function leaves interrupts disabled. - */ - -/** - * \fn void cpu_irq_restore(irqflags_t flags) - * \brief Restore global interrupt flags - * - * Use in conjunction with \ref cpu_irq_save. - * - * \param flags State to set interrupt flag to. - */ - -/** - * \fn bool cpu_irq_is_enabled_flags(irqflags_t flags) - * \brief Check if interrupts are globally enabled in supplied flags - * - * \param flags Currents state of interrupt flags. - * - * \return True if interrupts are enabled. - */ - -/** - * \def cpu_irq_is_enabled - * \brief Check if interrupts are globally enabled - * - * \return True if interrupts are enabled. - */ -//@} - -//! @} - -/** - * \ingroup interrupt_group - * \defgroup interrupt_deprecated_group Deprecated interrupt definitions - */ - -#endif /* UTILS_INTERRUPT_H */ diff --git a/atmel-samd/asf/common/utils/interrupt/interrupt_avr32.h b/atmel-samd/asf/common/utils/interrupt/interrupt_avr32.h deleted file mode 100644 index 66f2fa2c2fed5..0000000000000 --- a/atmel-samd/asf/common/utils/interrupt/interrupt_avr32.h +++ /dev/null @@ -1,351 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for 32-bit AVR - * - * Copyright (c) 2010-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UTILS_INTERRUPT_INTERRUPT_H -#define UTILS_INTERRUPT_INTERRUPT_H - -#include -#include - -/** - * \weakgroup interrupt_group - * - * @{ - */ - -//! Pointer to interrupt handler. -#if (defined __GNUC__) -typedef void (*__int_handler)(void); -#elif (defined __ICCAVR32__) -typedef void (__interrupt *__int_handler)(void); -#endif - -/** - * \name Interrupt Service Routine definition and registration - * - * @{ - */ -#if defined(__GNUC__) || defined(__DOXYGEN__) - -/** - * \brief Macro to declare an interrupt service routine - * - * With GCC, this macro only causes the function to be defined as an interrupt - * service routine, i.e., it does not add any initialization code. A valid - * function name is required for use with \ref irq_register_handler. - * - * With IAR, this macro defines the function as an interrupt service routine and - * causes the compiler to add initialization code for the interrupt controller - * (INTC). The interrupt group and level, as well as a valid function name are - * therefore required.\n - * \note If \ref CONFIG_INTERRUPT_FORCE_INTC is defined, only a valid function - * name is required for use with \ref irq_register_handler. The initialization - * code will be handled by the interrupt controller itself. - * - * Usage: - * \code - ISR(foo_irq_handler, AVR32_xxx_IRQ_GROUP, n) - { - // Function definition - ... - } -\endcode - * - * \param func Name for the function, needed by \ref irq_register_handler. - * \param int_grp Interrupt group to define service routine for. - * \param int_lvl Priority level to set for the interrupt group, in the range - * \c 0 to \c 3. - * - * \note The interrupt groups can be found in the device header files for the - * IAR toolchain (avr32/io\.h). - * - * \todo Update to use IRQ numbers when these are made available in the - * device header files of both IAR and GCC. - */ -# define ISR(func, int_grp, int_lvl) \ - __attribute__((__interrupt__)) static void func (void) - -#elif defined(__ICCAVR32__) && defined(CONFIG_INTERRUPT_FORCE_INTC) -# define ISR(func, int_grp, int_lvl) \ - __interrupt static void func (void) - -#elif defined(__ICCAVR32__) -# define ISR0(...) _Pragma(#__VA_ARGS__) -# define ISR(func, int_grp, int_lvl) \ - ISR0(handler=int_grp, int_lvl) \ - __interrupt static void func (void) -#endif - -#if defined(__GNUC__) || defined(__DOXYGEN__) || defined(CONFIG_INTERRUPT_FORCE_INTC) -# include - -/** - * \brief Initialize interrupt vectors - * - * With GCC, this macro adds code for initialization of the interrupt vectors - * with the driver for the interrupt controller (INTC). - * - * With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro - * adds no code, since initialization of the INTC is handled by the compiler. - * \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the - * INTC driver, replacing the compiler built-in interrupt handler. - * - * This must be called prior to \ref irq_register_handler. - */ -# define irq_initialize_vectors() INTC_init_interrupts() - -/** - * \brief Register handler for interrupt - * - * With GCC, this macro adds code for registering an interrupt handler with the - * driver for the interrupt controller (INTC). - * - * With IAR and unless \ref CONFIG_INTERRUPT_FORCE_INTC is defined this macro - * adds no code, since initialization of the INTC is handled by the compiler. - * \note Defining \ref CONFIG_INTERRUPT_FORCE_INTC will force the use of the - * INTC driver, replacing the compiler built-in interrupt handler. - * - * \param func Name of handler function to register for interrupt. - * \param int_num Number of the interrupt line to register function for. - * \param int_lvl Priority level to set for the interrupt's group, in the range - * \c 0 to \c 3. - * - * Usage: - * \code - irq_initialize_vectors(); - irq_register_handler(foo_irq_handler, AVR32_xxx_IRQ, n); -\endcode - * - * \note The function \a func must be defined with the \ref ISR macro. - * \note The interrupt line number can be found in the device header files for - * the GCC toolchain (avr32/\.h). - */ -# define irq_register_handler(func, int_num, int_lvl) \ - INTC_register_interrupt(func, int_num, \ - TPASTE2(AVR32_INTC_INT, int_lvl)) - -#elif defined(__ICCAVR32__) -# define irq_initialize_vectors() do{ } while(0) -# define irq_register_handler(func, int_num, int_lvl) do{ } while(0) -#endif - -//@} - -#if (defined __GNUC__) -# define cpu_irq_enable() \ - do { \ - barrier(); \ - __builtin_csrf(AVR32_SR_GM_OFFSET); \ - } while (0) -# define cpu_irq_disable() \ - do { \ - __builtin_ssrf(AVR32_SR_GM_OFFSET); \ - barrier(); \ - } while (0) -#elif (defined __ICCAVR32__) -# if (defined CONFIG_INTERRUPT_FORCE_INTC) -# define cpu_irq_enable() \ - do { \ - barrier(); \ - __clear_status_flag(AVR32_SR_GM_OFFSET); \ - } while(0) -# define cpu_irq_disable() \ - do { \ - __set_status_flag(AVR32_SR_GM_OFFSET); \ - barrier(); \ - } while (0) -# else -# define cpu_irq_enable() __enable_interrupt() -# define cpu_irq_disable() __disable_interrupt() -# endif -#endif - -typedef uint32_t irqflags_t; - -static inline irqflags_t cpu_irq_save(void) -{ - volatile irqflags_t flags; - - flags = sysreg_read(AVR32_SR); - cpu_irq_disable(); - - return flags; -} - -static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) -{ - return !(flags & AVR32_SR_GM_MASK); -} - -static inline void cpu_irq_restore(irqflags_t flags) -{ - barrier(); - - /* Restore the global IRQ mask status flag if it was previously set */ - if ( cpu_irq_is_enabled_flags(flags) ) { - cpu_irq_enable(); - } - - barrier(); -} - -#define cpu_irq_is_enabled() cpu_irq_is_enabled_flags(sysreg_read(AVR32_SR)) - -//! \name Global interrupt levels -//@{ - -/** - * \brief Check if interrupt level is enabled in supplied flags - * - * \param flags State of interrupt flags. - * \param level Bit position for interrupt level. - * - * \return True if interrupt level is enabled. - */ -static inline bool cpu_irq_level_is_enabled_flags(irqflags_t flags, - uint32_t level) -{ - return !(flags & (1 << level)); -} - -/** - * \brief Check if interrupt level is enabled - * - * \param level Interrupt level (0 to 3). - * - * \return True if interrupt level \a level is enabled. - * - * \note The interrupt level must be known at compile time. - */ -#define cpu_irq_level_is_enabled(level) \ - cpu_irq_level_is_enabled_flags(sysreg_read(AVR32_SR), \ - TPASTE3(AVR32_SR_I, level, M_OFFSET)) - -#if defined(__GNUC__) || defined(__DOXYGEN__) -/** - * \brief Enable interrupt level - * - * \param level Interrupt level to enable (0 to 3). - * - * \note The interrupt level must be known at compile time. - */ -# define cpu_irq_enable_level(level) \ - do { \ - barrier(); \ - __builtin_csrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ - } while (0) - -/** - * \brief Disable interrupt level - * - * \param level Interrupt level to disable (0 to 3). - * - * \note The interrupt level must be known at compile time. - */ -# define cpu_irq_disable_level(level) \ - do { \ - __builtin_ssrf(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ - barrier(); \ - } while (0) - -#elif (defined __ICCAVR32__) -# define cpu_irq_enable_level(level) \ - do { \ - barrier(); \ - __clear_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ - } while(0) -# define cpu_irq_disable_level(level) \ - do { \ - __set_status_flag(TPASTE3(AVR32_SR_I, level, M_OFFSET)); \ - barrier(); \ - } while (0) -#endif - -//@} - -//@} - -/** - * \weakgroup interrupt_deprecated_group - * @{ - */ - -#define Enable_global_interrupt() cpu_irq_enable() -#define Disable_global_interrupt() cpu_irq_disable() -#define Is_global_interrupt_enabled() cpu_irq_is_enabled() - -#define Enable_interrupt_level(level) cpu_irq_enable_level(level) -#define Disable_interrupt_level(level) cpu_irq_disable_level(level) -#define Is_interrupt_level_enabled(level) cpu_irq_level_is_enabled(level) - -/** - * \name Interrupt protection of code sections - * \note Use \ref cpu_irq_save and \ref cpu_irq_restore instead of these macros. - * @{ - */ - -/** - * \brief Start section with code protected against interrupts - */ -#define AVR32_ENTER_CRITICAL_REGION() \ - { \ - bool global_interrupt_enabled = Is_global_interrupt_enabled(); \ - Disable_global_interrupt(); - -/** - * \brief End section with code protected against interrupts - * - * \note This macro must always be used in conjunction with - * \ref AVR32_ENTER_CRITICAL_REGION so that interrupts are enabled again. - */ -#define AVR32_LEAVE_CRITICAL_REGION() \ - if (global_interrupt_enabled) Enable_global_interrupt(); \ - } - -//@} - -//@} - -#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/atmel-samd/asf/common/utils/interrupt/interrupt_avr8.h b/atmel-samd/asf/common/utils/interrupt/interrupt_avr8.h deleted file mode 100644 index 1e6928c285c82..0000000000000 --- a/atmel-samd/asf/common/utils/interrupt/interrupt_avr8.h +++ /dev/null @@ -1,148 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for 8-bit AVR - * - * Copyright (C) 2010-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef UTILS_INTERRUPT_INTERRUPT_H -#define UTILS_INTERRUPT_INTERRUPT_H - -#include -#include - -/** - * \weakgroup interrupt_group - * - * @{ - */ - -#ifdef ISR_CUSTOM_H -# include ISR_CUSTOM_H -#else - -/** - * \def ISR - * \brief Define service routine for specified interrupt vector - * - * Usage: - * \code - ISR(FOO_vect) - { - ... - } -\endcode - * - * \param vect Interrupt vector name as found in the device header files. - */ -#if defined(__DOXYGEN__) -# define ISR(vect) -#elif defined(__GNUC__) -# include -#elif defined(__ICCAVR__) -# define __ISR(x) _Pragma(#x) -# define ISR(vect) __ISR(vector=vect) __interrupt void handler_##vect(void) -#endif -#endif // ISR_CUSTOM_H - -#if XMEGA -/** - * \brief Initialize interrupt vectors - * Enables all interrupt levels, with vectors located in the application section - * and fixed priority scheduling. - */ -#define irq_initialize_vectors() \ - PMIC.CTRL = PMIC_LOLVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_HILVLEN_bm; -#elif MEGA_RF -#define irq_initialize_vectors() -#endif - -#ifdef __GNUC__ -# define cpu_irq_enable() sei() -# define cpu_irq_disable() cli() -#else -# define cpu_irq_enable() __enable_interrupt() -# define cpu_irq_disable() __disable_interrupt() -#endif - -typedef uint8_t irqflags_t; - -static inline irqflags_t cpu_irq_save(void) -{ - volatile irqflags_t flags = SREG; - cpu_irq_disable(); - return flags; -} - -static inline void cpu_irq_restore(irqflags_t flags) -{ - barrier(); - SREG = flags; -} - -static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) -{ -#if XMEGA -# ifdef __GNUC__ - return flags & CPU_I_bm; -# else - return flags & I_bm; -# endif -#elif MEGA || TINY - return flags & (1 << SREG_I); -#endif -} - -#define cpu_irq_is_enabled() cpu_irq_is_enabled_flags(SREG) - -//! @} - -/** - * \weakgroup interrupt_deprecated_group - * @{ - */ -// Deprecated definitions. -#define Enable_global_interrupt() cpu_irq_enable() -#define Disable_global_interrupt() cpu_irq_disable() -#define Is_global_interrupt_enabled() cpu_irq_is_enabled() -//! @} - -#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/atmel-samd/asf/common/utils/interrupt/interrupt_sam_nvic.c b/atmel-samd/asf/common/utils/interrupt/interrupt_sam_nvic.c deleted file mode 100644 index 26dcc91ef4dc1..0000000000000 --- a/atmel-samd/asf/common/utils/interrupt/interrupt_sam_nvic.c +++ /dev/null @@ -1,86 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "interrupt_sam_nvic.h" - -#if !defined(__DOXYGEN__) -/* Deprecated - global flag to determine the global interrupt state. Required by - * QTouch library, however new applications should use cpu_irq_is_enabled() - * which probes the true global interrupt state from the CPU special registers. - */ -volatile bool g_interrupt_enabled = true; -#endif - -void cpu_irq_enter_critical(void) -{ - if (cpu_irq_critical_section_counter == 0) { - if (cpu_irq_is_enabled()) { - cpu_irq_disable(); - cpu_irq_prev_interrupt_state = true; - } else { - /* Make sure the to save the prev state as false */ - cpu_irq_prev_interrupt_state = false; - } - - } - - cpu_irq_critical_section_counter++; -} - -void cpu_irq_leave_critical(void) -{ - /* Check if the user is trying to leave a critical section when not in a critical section */ - Assert(cpu_irq_critical_section_counter > 0); - - cpu_irq_critical_section_counter--; - - /* Only enable global interrupts when the counter reaches 0 and the state of the global interrupt flag - was enabled when entering critical state */ - if ((cpu_irq_critical_section_counter == 0) && (cpu_irq_prev_interrupt_state)) { - cpu_irq_enable(); - } -} - diff --git a/atmel-samd/asf/common/utils/interrupt/interrupt_sam_nvic.h b/atmel-samd/asf/common/utils/interrupt/interrupt_sam_nvic.h deleted file mode 100644 index 419ad2046e8d1..0000000000000 --- a/atmel-samd/asf/common/utils/interrupt/interrupt_sam_nvic.h +++ /dev/null @@ -1,189 +0,0 @@ -/** - * \file - * - * \brief Global interrupt management for SAM D20, SAM3 and SAM4 (NVIC based) - * - * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef UTILS_INTERRUPT_INTERRUPT_H -#define UTILS_INTERRUPT_INTERRUPT_H - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \weakgroup interrupt_group - * - * @{ - */ - -/** - * \name Interrupt Service Routine definition - * - * @{ - */ - -/** - * \brief Define service routine - * - * \note For NVIC devices the interrupt service routines are predefined to - * add to vector table in binary generation, so there is no service - * register at run time. The routine collections are in exceptions.h. - * - * Usage: - * \code - ISR(foo_irq_handler) - { - // Function definition - ... - } -\endcode - * - * \param func Name for the function. - */ -# define ISR(func) \ - void func (void) - -/** - * \brief Initialize interrupt vectors - * - * For NVIC the interrupt vectors are put in vector table. So nothing - * to do to initialize them, except defined the vector function with - * right name. - * - * This must be called prior to \ref irq_register_handler. - */ -# define irq_initialize_vectors() \ - do { \ - } while(0) - -/** - * \brief Register handler for interrupt - * - * For NVIC the interrupt vectors are put in vector table. So nothing - * to do to register them, except defined the vector function with - * right name. - * - * Usage: - * \code - irq_initialize_vectors(); - irq_register_handler(foo_irq_handler); -\endcode - * - * \note The function \a func must be defined with the \ref ISR macro. - * \note The functions prototypes can be found in the device exception header - * files (exceptions.h). - */ -# define irq_register_handler(int_num, int_prio) \ - NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ - NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ - NVIC_EnableIRQ( (IRQn_Type)int_num); \ - -//@} - -# define cpu_irq_enable() \ - do { \ - g_interrupt_enabled = true; \ - __DMB(); \ - __enable_irq(); \ - } while (0) -# define cpu_irq_disable() \ - do { \ - __disable_irq(); \ - __DMB(); \ - g_interrupt_enabled = false; \ - } while (0) - -typedef uint32_t irqflags_t; - -#if !defined(__DOXYGEN__) -extern volatile bool g_interrupt_enabled; -#endif - -#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) - -static volatile uint32_t cpu_irq_critical_section_counter; -static volatile bool cpu_irq_prev_interrupt_state; - -static inline irqflags_t cpu_irq_save(void) -{ - volatile irqflags_t flags = cpu_irq_is_enabled(); - cpu_irq_disable(); - return flags; -} - -static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) -{ - return (flags); -} - -static inline void cpu_irq_restore(irqflags_t flags) -{ - if (cpu_irq_is_enabled_flags(flags)) - cpu_irq_enable(); -} - -void cpu_irq_enter_critical(void); -void cpu_irq_leave_critical(void); - -/** - * \weakgroup interrupt_deprecated_group - * @{ - */ - -#define Enable_global_interrupt() cpu_irq_enable() -#define Disable_global_interrupt() cpu_irq_disable() -#define Is_global_interrupt_enabled() cpu_irq_is_enabled() - -//@} - -//@} - -#ifdef __cplusplus -} -#endif - -#endif /* UTILS_INTERRUPT_INTERRUPT_H */ diff --git a/atmel-samd/asf/common/utils/make/Makefile.avr.in b/atmel-samd/asf/common/utils/make/Makefile.avr.in deleted file mode 100644 index 5d9a83754735b..0000000000000 --- a/atmel-samd/asf/common/utils/make/Makefile.avr.in +++ /dev/null @@ -1,483 +0,0 @@ -# List of available make goals: -# -# all Default target, builds the project -# clean Clean up the project -# rebuild Rebuild the project -# -# doc Build the documentation -# cleandoc Clean up the documentation -# rebuilddoc Rebuild the documentation -# -# -# Copyright (c) 2009 - 2013 Atmel Corporation. All rights reserved. -# -# \asf_license_start -# -# \page License -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# 3. The name of Atmel may not be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# 4. This software may only be redistributed and used in connection with an -# Atmel microcontroller product. -# -# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -# \asf_license_stop -# - -# Include the config.mk file from the current working path, e.g., where the -# user called make. -include config.mk - -# Tool to use to generate documentation from the source code -DOCGEN ?= doxygen - -# Look for source files relative to the top-level source directory -VPATH := $(PRJ_PATH) - -# Output target file -target := $(TARGET) - -# Output project name (target name minus suffix) -project := $(basename $(target)) - -# Output target file (typically ELF or static library) -ifeq ($(suffix $(target)),.a) -target_type := lib -else -ifeq ($(suffix $(target)),.elf) -target_type := elf -else -$(error "Target type $(target_type) is not supported") -endif -endif - -# Allow override of operating system detection. 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Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../membag.c ../../membag.h ../../module_config/conf_membag.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/membag/doxygen/common.utils.membag/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/membag/doxygen/common.utils.membag/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/membag/doxygen/common.utils.membag/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/membag/membag.c b/atmel-samd/asf/common/utils/membag/membag.c deleted file mode 100644 index c6a50c059f15d..0000000000000 --- a/atmel-samd/asf/common/utils/membag/membag.c +++ /dev/null @@ -1,325 +0,0 @@ -/** - * \file - * - * \brief Memory bag allocator - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include "conf_membag.h" - -/** \internal - * - * Retrieves the number of elements in a statically declared array. - */ -#define ARRAY_LEN(a) (sizeof(a) / sizeof((a)[0])) - -/** - * Static address space which is split up into usable chunks by membag. - * For configuration details, see \ref membag_list. - */ -static uint8_t membag_pool[CONF_MEMBAG_POOL_SIZE]; - -/** - * Internal structure used by membag to keep track of memory, - * with maximum 32 blocks per membag. - */ -struct membag { - /*! Number of bytes per block in this bag. */ - size_t block_size; - /*! Total number of blocks. */ - size_t num_blocks; - /*! Pointer to start of this bag. */ - uintptr_t start; - /*! Pointer to end of this bag. */ - uintptr_t end; - /*! 32-bit integer used to keep track of allocations. */ - uint32_t allocated; - /*! Counter for number of free blocks. */ - uint8_t blocks_free; -}; - -/** - * Array of available membags, provided by the user in the applications - * conf_membag.h header file. Example: - * - * \code - #define CONF_MEMBAG_ARRAY \ - MEMBAG(32, 4), \ - MEMBAG(16, 2), - - #define CONF_MEMBAG_POOL_SIZE \ - MEMBAG_SIZE(32, 4) + \ - MEMBAG_SIZE(16, 2) -\endcode - * - */ -static struct membag membag_list[] = { - CONF_MEMBAG_ARRAY -}; - -/** - * \brief Initialize the membag system. - * - * This function sets up the membags, allocates memory from the memory pool, and - * initializes them. Any existing allocations are destroyed and all memory pools - * reset to their initial states. - */ -void membag_init(void) -{ - uint8_t i; - uintptr_t poolptr; - - poolptr = (uintptr_t)membag_pool; - - for (i = 0; i < ARRAY_LEN(membag_list); i++) { - Assert(membag_list[i].block_size > 0); - Assert(membag_list[i].num_blocks > 0); - Assert(membag_list[i].num_blocks <= 32); - - membag_list[i].start = poolptr; - poolptr += (membag_list[i].block_size * - membag_list[i].num_blocks); - membag_list[i].end = poolptr; - membag_list[i].blocks_free = membag_list[i].num_blocks; - - /* Mark all blocks as free. */ - membag_list[i].allocated = 0; - } -} - -/** - * \brief Determine the total remaining free memory from all membags. - * - * \return Sum of all free memory, in bytes. - */ -size_t membag_get_total_free(void) -{ - uint8_t i; - size_t total_free = 0; - - for (i = 0; i < ARRAY_LEN(membag_list); i++) { - total_free += membag_list[i].blocks_free * - membag_list[i].block_size; - } - - return total_free; -} - -/** - * \brief Determine the total memory from all membags. - * - * \return Sum of all blocks in all bags, in bytes. - */ -size_t membag_get_total(void) -{ - uint8_t i; - size_t total = 0; - - for (i = 0; i < ARRAY_LEN(membag_list); i++) { - total += membag_list[i].num_blocks * membag_list[i].block_size; - } - - return total; -} - -/** - * \brief Determine the smallest available block size. - * - * Calculates the smallest block which can be allocated by the Membag allocator - * if requested. Allocations larger than this amount are not guaranteed to - * complete successfully. - * - * \return Size of the smallest available block, in bytes. - */ -size_t membag_get_smallest_free_block_size(void) -{ - uint8_t i; - struct membag *smallest_bag = NULL; - - for (i = 0; i < ARRAY_LEN(membag_list); i++) { - if (membag_list[i].blocks_free == 0) { - continue; - } - - if (!smallest_bag || - (smallest_bag->block_size > membag_list[i].block_size)) { - smallest_bag = &membag_list[i]; - } - } - - if (smallest_bag) { - return smallest_bag->block_size; - } - - return 0; -} - -/** - * \brief Determine the largest available block size. - * - * Calculates the largest block which can be allocated by the Membag allocator - * if requested. Allocations larger than this amount are guaranteed to fail. - * - * \return Size of the largest available block, in bytes. - */ -size_t membag_get_largest_free_block_size(void) -{ - uint8_t i; - struct membag *largest_bag = NULL; - - for (i = 0; i < ARRAY_LEN(membag_list); i++) { - if (membag_list[i].blocks_free == 0) { - continue; - } - - if (!largest_bag || - (largest_bag->block_size < membag_list[i].block_size)) { - largest_bag = &membag_list[i]; - } - } - - if (largest_bag) { - return largest_bag->block_size; - } - - return 0; -} - -/** - * \brief Allocate a memory block via a block from the Membag pool - * - * Allocates memory to the user from one of the available Membag pools. Each - * Membag pool is examined in sequence, and the first free block of sufficient - * size (if any) is chosen for the allocation. Allocated blocks persist until - * either the Membag module is re-initialized, or an allocation block is freed - * via \ref membag_free(). - * - * \note The execution cycle time for this function is not deterministic; each - * allocation request may take a variable amount of cycles to complete. - * - * \param size Size of memory block requested, in bytes - * - * \return Pointer to the start of an allocated block if one was found in the - * Membag pool, NULL if no suitable block was found. - */ -void *membag_alloc(const size_t size) -{ - uint8_t i; - struct membag *smallest_bag = NULL; - uintptr_t p; - - /* Find the smallest available block size big enough for the requested - * memory chunk size. */ - for (i = 0; i < ARRAY_LEN(membag_list); i++) { - if (membag_list[i].blocks_free == 0) { - continue; - } - - if (membag_list[i].block_size >= size) { - if (!smallest_bag || - (smallest_bag->block_size > membag_list[i].block_size)) { - smallest_bag = &membag_list[i]; - } - } - } - - /* We return the first available block in the bag that has one, and if - * there is none, we return NULL. - */ - if (smallest_bag) { - /* We know that there is a free block within the membag's - * memory, and we simply return the first one available. - */ - p = smallest_bag->start; - - for (i = 0; i < smallest_bag->num_blocks; i++) { - /* Check the allocation byte to see whether the block is - * in use. */ - if (!(smallest_bag->allocated & ((uint32_t)1 << i))) { - /* It is free, set it to used. */ - smallest_bag->allocated |= ((uint32_t)1 << i); - smallest_bag->blocks_free--; - - return (void *)(p); - } - - p += smallest_bag->block_size; - } - } - - /* There is no available memory. Return NULL. */ - return NULL; -} - -/** - * \brief Free a previously allocated memory block from the Membag pool - * - * This function frees memory which has been allocated previously via a - * successful call to \ref membag_alloc(). Once deallocated, the given pointer - * is no longer valid and should not be used in the user application unless - * re-allocated. - * - * \note The execution cycle time for this function is not deterministic; each - * allocation request may take a variable amount of cycles to complete. - * - * \param ptr Pointer to an allocated memory block to free - */ -void membag_free(const void *ptr) -{ - uint8_t i; - uintptr_t p = (uintptr_t)ptr; - uint8_t block_index; - - for (i = 0; i < ARRAY_LEN(membag_list); i++) { - if (p >= membag_list[i].start && p < membag_list[i].end) { - block_index = (p - membag_list[i].start) / membag_list[i].block_size; - - /* Mark the memory as free. */ - membag_list[i].allocated &= ~((uint32_t)1 << block_index); - membag_list[i].blocks_free++; - - return; - } - } -} diff --git a/atmel-samd/asf/common/utils/membag/membag.h b/atmel-samd/asf/common/utils/membag/membag.h deleted file mode 100644 index 88495a53d337c..0000000000000 --- a/atmel-samd/asf/common/utils/membag/membag.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief Memory Bag allocator for 8-bit AVR, 32-bit AVR, SAM - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef UTILS_MEMBAG_H -#define UTILS_MEMBAG_H - -#include - -/** - * \defgroup membag_group Memory Bag Allocator - * - * The Membag allocator is a optimized, fragmentationless general purpose - * memory allocator utility module designed to replace the standard C library - * \c malloc() and \c free() functions in resource constrained environments. - * - * - * Internally, the Membag allocator uses several user defined "bags" of one or - * more fixed-size blocks to form a memory pool for use in a user application. - * When an allocation is requested, the Membag module will search all available - * bags and find the smallest unallocated block of sufficient size, and return - * this block to the calling function. The size of each bag and number of blocks - * in each bag is user configurable, via the \ref conf_membag.h header file - * added to the user project. - * - * The allocator also has basic statistics functionality to obtain the size of - * the entire memory pool, amount of free memory, and the size of the smallest - * and largest free memory block. - * - * The memory bag allocator always allocates memory as a block from a fixed size - * bag/pool. This helps reduce memory fragmentation compared to an generic - * allocator that gives exactly the bytes requested. While this gives a - * trade-off of the maximum number of concurrent allocations and the size of - * allocations that are allowable, the allocator prevents memory fragmentation - * from occuring in an embedded application. - * - * The allocation and deallocation of memory with the Membag module is - * non-deterministic, however the module functions all have a maximum run time - * that is dependent on the number of bags that have been configured. - * - * @{ - */ - -/** - * Macro used to create memory bags in conf_membag.h - * - * \note Multiple bags of the same size are allowed, if more than 32 bags of a - * given size are required in an application. - * - * \param objsize Size of each block in the bag - * \param nr_objs Number of blocks in the bag, a value less than 32 - */ -#define MEMBAG(objsize, nr_objs)\ - { .block_size = objsize, .num_blocks = nr_objs } - -/** - * Macro used to store the size of the membags in conf_membag.h - * - * \note Multiple bags of the same size are allowed, if more than 32 bags of a - * given size are required in an application. - * - * \param objsize Size of each block in the bag - * \param nr_objs Number of blocks in the bag, a value less than 32 - */ -#define MEMBAG_SIZE(objsize, nr_objs)\ - (objsize * nr_objs) - -void membag_init(void); - -size_t membag_get_total(void); -size_t membag_get_total_free(void); - -size_t membag_get_smallest_free_block_size(void); -size_t membag_get_largest_free_block_size(void); - -void *membag_alloc(const size_t size); -void membag_free(const void *ptr); - -/** @} */ - -#endif /* UTILS_MEMBAG_H */ diff --git a/atmel-samd/asf/common/utils/membag/module_config/conf_membag.h b/atmel-samd/asf/common/utils/membag/module_config/conf_membag.h deleted file mode 100644 index 3112435145fa2..0000000000000 --- a/atmel-samd/asf/common/utils/membag/module_config/conf_membag.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief Membag configuration header - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_MEMBAG_H -#define CONF_MEMBAG_H - -#include - -#define CONF_MEMBAG_ARRAY\ - MEMBAG(16, 5),\ - MEMBAG(64, 2),\ - MEMBAG(128, 10), - -#define CONF_MEMBAG_POOL_SIZE\ - MEMBAG_SIZE(16, 5) +\ - MEMBAG_SIZE(64, 2) +\ - MEMBAG_SIZE(128, 10) - -#endif /* CONF_MEMBAG_H */ diff --git a/atmel-samd/asf/common/utils/osprintf/doxygen/common.utils.osprintf_sam/doxyfile.doxygen b/atmel-samd/asf/common/utils/osprintf/doxygen/common.utils.osprintf_sam/doxyfile.doxygen deleted file mode 100644 index 2f51fed575f8c..0000000000000 --- a/atmel-samd/asf/common/utils/osprintf/doxygen/common.utils.osprintf_sam/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard I/O (stdio) Interface with RTOS Support - SAM implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../osprintf.c ../../osprintf.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/osprintf/doxygen/common.utils.osprintf_sam/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/osprintf/doxygen/common.utils.osprintf_sam/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/osprintf/doxygen/common.utils.osprintf_sam/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/osprintf/osprintf.c b/atmel-samd/asf/common/utils/osprintf/osprintf.c deleted file mode 100644 index e50748b4c06fa..0000000000000 --- a/atmel-samd/asf/common/utils/osprintf/osprintf.c +++ /dev/null @@ -1,103 +0,0 @@ -/** - * - * \file - * - * \brief - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include "asf.h" -#include -#include -#include "FreeRTOS.h" -#include "osprintf.h" - -xSemaphoreHandle trace_lock; - -void osprintf_init(void *usart, const void *opt) -{ - trace_lock = xSemaphoreCreateMutex(); - stdio_serial_init(usart, opt); -} - -void osprintf(const char *fmt, ...) -{ - va_list args; - va_start(args, fmt); - xSemaphoreTake(trace_lock, portMAX_DELAY); - vprintf(fmt, args); - xSemaphoreGive(trace_lock); - va_end(args); -} - -void osprint(const char *s) -{ - xSemaphoreTake(trace_lock, portMAX_DELAY); - puts(s); - xSemaphoreGive(trace_lock); -} - -void osprint_hex_array(uint8_t *p, int sz) -{ - xSemaphoreTake(trace_lock, portMAX_DELAY); - while (sz) { - if (sz < 8) { - while (sz--) { - printf("%02x ", *p); - p++; - } - break; - } - printf("%02x %02x %02x %02x %02x %02x %02x %02x\n", - p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]); - p += 8; - sz -= 8; - } - printf("\n"); - xSemaphoreGive(trace_lock); -} - -void osprint_sem_take(void) -{ - xSemaphoreTake(trace_lock, portMAX_DELAY); -} - -void osprint_sem_give(void) -{ - xSemaphoreGive(trace_lock); -} diff --git a/atmel-samd/asf/common/utils/osprintf/osprintf.h b/atmel-samd/asf/common/utils/osprintf/osprintf.h deleted file mode 100644 index 5c3593316c5bf..0000000000000 --- a/atmel-samd/asf/common/utils/osprintf/osprintf.h +++ /dev/null @@ -1,59 +0,0 @@ -/** - * - * \file - * - * \brief - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef OSPRINTF_H_INCLUDED -#define OSPRINTF_H_INCLUDED - -#include "compiler.h" - -void osprintf_init(void *usart, const void *opt); -void osprintf(const char *fmt, ...) __attribute__ ((format (gnu_printf, 1, 0))); - -void osprint(const char *s); -void osprint_hex_array(uint8_t *p, int sz); - -void osprint_sem_take(void); -void osprint_sem_give(void); - -#endif /* OSPRINTF_H_INCLUDED */ diff --git a/atmel-samd/asf/common/utils/parts.h b/atmel-samd/asf/common/utils/parts.h deleted file mode 100644 index e3df5533f2e10..0000000000000 --- a/atmel-samd/asf/common/utils/parts.h +++ /dev/null @@ -1,1593 +0,0 @@ -/** - * \file - * - * \brief Atmel part identification macros - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -/** - * \defgroup part_macros_group Atmel part identification macros - * - * This collection of macros identify which series and families that the various - * Atmel parts belong to. These can be used to select part-dependent sections of - * code at compile time. - * - * @{ - */ - -/** - * \name Convenience macros for part checking - * @{ - */ -/* ! Check GCC and IAR part definition for 8-bit AVR */ -#define AVR8_PART_IS_DEFINED(part) \ - (defined(__ ## part ## __) || defined(__AVR_ ## part ## __)) - -/* ! Check GCC and IAR part definition for 32-bit AVR */ -#define AVR32_PART_IS_DEFINED(part) \ - (defined(__AT32 ## part ## __) || defined(__AVR32_ ## part ## __)) - -/* ! Check GCC and IAR part definition for SAM */ -#define SAM_PART_IS_DEFINED(part) (defined(__ ## part ## __)) -/** @} */ - -/** - * \defgroup uc3_part_macros_group AVR UC3 parts - * @{ - */ - -/** - * \name AVR UC3 A series - * @{ - */ -#define UC3A0 ( \ - AVR32_PART_IS_DEFINED(UC3A0128) || \ - AVR32_PART_IS_DEFINED(UC3A0256) || \ - AVR32_PART_IS_DEFINED(UC3A0512) \ - ) - -#define UC3A1 ( \ - AVR32_PART_IS_DEFINED(UC3A1128) || \ - AVR32_PART_IS_DEFINED(UC3A1256) || \ - AVR32_PART_IS_DEFINED(UC3A1512) \ - ) - -#define UC3A3 ( \ - AVR32_PART_IS_DEFINED(UC3A364) || \ - AVR32_PART_IS_DEFINED(UC3A364S) || \ - AVR32_PART_IS_DEFINED(UC3A3128) || \ - AVR32_PART_IS_DEFINED(UC3A3128S) || \ - AVR32_PART_IS_DEFINED(UC3A3256) || \ - AVR32_PART_IS_DEFINED(UC3A3256S) \ - ) - -#define UC3A4 ( \ - AVR32_PART_IS_DEFINED(UC3A464) || \ - AVR32_PART_IS_DEFINED(UC3A464S) || \ - AVR32_PART_IS_DEFINED(UC3A4128) || \ - AVR32_PART_IS_DEFINED(UC3A4128S) || \ - AVR32_PART_IS_DEFINED(UC3A4256) || \ - AVR32_PART_IS_DEFINED(UC3A4256S) \ - ) -/** @} */ - -/** - * \name AVR UC3 B series - * @{ - */ -#define UC3B0 ( \ - AVR32_PART_IS_DEFINED(UC3B064) || \ - AVR32_PART_IS_DEFINED(UC3B0128) || \ - AVR32_PART_IS_DEFINED(UC3B0256) || \ - AVR32_PART_IS_DEFINED(UC3B0512) \ - ) - -#define UC3B1 ( \ - AVR32_PART_IS_DEFINED(UC3B164) || \ - AVR32_PART_IS_DEFINED(UC3B1128) || \ - AVR32_PART_IS_DEFINED(UC3B1256) || \ - AVR32_PART_IS_DEFINED(UC3B1512) \ - ) -/** @} */ - -/** - * \name AVR UC3 C series - * @{ - */ -#define UC3C0 ( \ - AVR32_PART_IS_DEFINED(UC3C064C) || \ - AVR32_PART_IS_DEFINED(UC3C0128C) || \ - AVR32_PART_IS_DEFINED(UC3C0256C) || \ - AVR32_PART_IS_DEFINED(UC3C0512C) \ - ) - -#define UC3C1 ( \ - AVR32_PART_IS_DEFINED(UC3C164C) || \ - AVR32_PART_IS_DEFINED(UC3C1128C) || \ - AVR32_PART_IS_DEFINED(UC3C1256C) || \ - AVR32_PART_IS_DEFINED(UC3C1512C) \ - ) - -#define UC3C2 ( \ - AVR32_PART_IS_DEFINED(UC3C264C) || \ - AVR32_PART_IS_DEFINED(UC3C2128C) || \ - AVR32_PART_IS_DEFINED(UC3C2256C) || \ - AVR32_PART_IS_DEFINED(UC3C2512C) \ - ) -/** @} */ - -/** - * \name AVR UC3 D series - * @{ - */ -#define UC3D3 ( \ - AVR32_PART_IS_DEFINED(UC64D3) || \ - AVR32_PART_IS_DEFINED(UC128D3) \ - ) - -#define UC3D4 ( \ - AVR32_PART_IS_DEFINED(UC64D4) || \ - AVR32_PART_IS_DEFINED(UC128D4) \ - ) -/** @} */ - -/** - * \name AVR UC3 L series - * @{ - */ -#define UC3L0 ( \ - AVR32_PART_IS_DEFINED(UC3L016) || \ - AVR32_PART_IS_DEFINED(UC3L032) || \ - AVR32_PART_IS_DEFINED(UC3L064) \ - ) - -#define UC3L0128 ( \ - AVR32_PART_IS_DEFINED(UC3L0128) \ - ) - -#define UC3L0256 ( \ - AVR32_PART_IS_DEFINED(UC3L0256) \ - ) - -#define UC3L3 ( \ - AVR32_PART_IS_DEFINED(UC64L3U) || \ - AVR32_PART_IS_DEFINED(UC128L3U) || \ - AVR32_PART_IS_DEFINED(UC256L3U) \ - ) - -#define UC3L4 ( \ - AVR32_PART_IS_DEFINED(UC64L4U) || \ - AVR32_PART_IS_DEFINED(UC128L4U) || \ - AVR32_PART_IS_DEFINED(UC256L4U) \ - ) - -#define UC3L3_L4 (UC3L3 || UC3L4) -/** @} */ - -/** - * \name AVR UC3 families - * @{ - */ -/** AVR UC3 A family */ -#define UC3A (UC3A0 || UC3A1 || UC3A3 || UC3A4) - -/** AVR UC3 B family */ -#define UC3B (UC3B0 || UC3B1) - -/** AVR UC3 C family */ -#define UC3C (UC3C0 || UC3C1 || UC3C2) - -/** AVR UC3 D family */ -#define UC3D (UC3D3 || UC3D4) - -/** AVR UC3 L family */ -#define UC3L (UC3L0 || UC3L0128 || UC3L0256 || UC3L3_L4) -/** @} */ - -/** AVR UC3 product line */ -#define UC3 (UC3A || UC3B || UC3C || UC3D || UC3L) - -/** @} */ - -/** - * \defgroup xmega_part_macros_group AVR XMEGA parts - * @{ - */ - -/** - * \name AVR XMEGA A series - * @{ - */ -#define XMEGA_A1 ( \ - AVR8_PART_IS_DEFINED(ATxmega64A1) || \ - AVR8_PART_IS_DEFINED(ATxmega128A1) \ - ) - -#define XMEGA_A3 ( \ - AVR8_PART_IS_DEFINED(ATxmega64A3) || \ - AVR8_PART_IS_DEFINED(ATxmega128A3) || \ - AVR8_PART_IS_DEFINED(ATxmega192A3) || \ - AVR8_PART_IS_DEFINED(ATxmega256A3) \ - ) - -#define XMEGA_A3B ( \ - AVR8_PART_IS_DEFINED(ATxmega256A3B) \ - ) - -#define XMEGA_A4 ( \ - AVR8_PART_IS_DEFINED(ATxmega16A4) || \ - AVR8_PART_IS_DEFINED(ATxmega32A4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA AU series - * @{ - */ -#define XMEGA_A1U ( \ - AVR8_PART_IS_DEFINED(ATxmega64A1U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A1U) \ - ) - -#define XMEGA_A3U ( \ - AVR8_PART_IS_DEFINED(ATxmega64A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega192A3U) || \ - AVR8_PART_IS_DEFINED(ATxmega256A3U) \ - ) - -#define XMEGA_A3BU ( \ - AVR8_PART_IS_DEFINED(ATxmega256A3BU) \ - ) - -#define XMEGA_A4U ( \ - AVR8_PART_IS_DEFINED(ATxmega16A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega32A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega64A4U) || \ - AVR8_PART_IS_DEFINED(ATxmega128A4U) \ - ) -/** @} */ - -/** - * \name AVR XMEGA B series - * @{ - */ -#define XMEGA_B1 ( \ - AVR8_PART_IS_DEFINED(ATxmega64B1) || \ - AVR8_PART_IS_DEFINED(ATxmega128B1) \ - ) - -#define XMEGA_B3 ( \ - AVR8_PART_IS_DEFINED(ATxmega64B3) || \ - AVR8_PART_IS_DEFINED(ATxmega128B3) \ - ) -/** @} */ - -/** - * \name AVR XMEGA C series - * @{ - */ -#define XMEGA_C3 ( \ - AVR8_PART_IS_DEFINED(ATxmega384C3) || \ - AVR8_PART_IS_DEFINED(ATxmega256C3) || \ - AVR8_PART_IS_DEFINED(ATxmega192C3) || \ - AVR8_PART_IS_DEFINED(ATxmega128C3) || \ - AVR8_PART_IS_DEFINED(ATxmega64C3) || \ - AVR8_PART_IS_DEFINED(ATxmega32C3) \ - ) - -#define XMEGA_C4 ( \ - AVR8_PART_IS_DEFINED(ATxmega32C4) || \ - AVR8_PART_IS_DEFINED(ATxmega16C4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA D series - * @{ - */ -#define XMEGA_D3 ( \ - AVR8_PART_IS_DEFINED(ATxmega32D3) || \ - AVR8_PART_IS_DEFINED(ATxmega64D3) || \ - AVR8_PART_IS_DEFINED(ATxmega128D3) || \ - AVR8_PART_IS_DEFINED(ATxmega192D3) || \ - AVR8_PART_IS_DEFINED(ATxmega256D3) || \ - AVR8_PART_IS_DEFINED(ATxmega384D3) \ - ) - -#define XMEGA_D4 ( \ - AVR8_PART_IS_DEFINED(ATxmega16D4) || \ - AVR8_PART_IS_DEFINED(ATxmega32D4) || \ - AVR8_PART_IS_DEFINED(ATxmega64D4) || \ - AVR8_PART_IS_DEFINED(ATxmega128D4) \ - ) -/** @} */ - -/** - * \name AVR XMEGA E series - * @{ - */ -#define XMEGA_E5 ( \ - AVR8_PART_IS_DEFINED(ATxmega8E5) || \ - AVR8_PART_IS_DEFINED(ATxmega16E5) || \ - AVR8_PART_IS_DEFINED(ATxmega32E5) \ - ) -/** @} */ - - -/** - * \name AVR XMEGA families - * @{ - */ -/** AVR XMEGA A family */ -#define XMEGA_A (XMEGA_A1 || XMEGA_A3 || XMEGA_A3B || XMEGA_A4) - -/** AVR XMEGA AU family */ -#define XMEGA_AU (XMEGA_A1U || XMEGA_A3U || XMEGA_A3BU || XMEGA_A4U) - -/** AVR XMEGA B family */ -#define XMEGA_B (XMEGA_B1 || XMEGA_B3) - -/** AVR XMEGA C family */ -#define XMEGA_C (XMEGA_C3 || XMEGA_C4) - -/** AVR XMEGA D family */ -#define XMEGA_D (XMEGA_D3 || XMEGA_D4) - -/** AVR XMEGA E family */ -#define XMEGA_E (XMEGA_E5) -/** @} */ - - -/** AVR XMEGA product line */ -#define XMEGA (XMEGA_A || XMEGA_AU || XMEGA_B || XMEGA_C || XMEGA_D || XMEGA_E) - -/** @} */ - -/** - * \defgroup mega_part_macros_group megaAVR parts - * - * \note These megaAVR groupings are based on the groups in AVR Libc for the - * part header files. They are not names of official megaAVR device series or - * families. - * - * @{ - */ - -/** - * \name ATmegaxx0/xx1 subgroups - * @{ - */ -#define MEGA_XX0 ( \ - AVR8_PART_IS_DEFINED(ATmega640) || \ - AVR8_PART_IS_DEFINED(ATmega1280) || \ - AVR8_PART_IS_DEFINED(ATmega2560) \ - ) - -#define MEGA_XX1 ( \ - AVR8_PART_IS_DEFINED(ATmega1281) || \ - AVR8_PART_IS_DEFINED(ATmega2561) \ - ) -/** @} */ - -/** - * \name megaAVR groups - * @{ - */ -/** ATmegaxx0/xx1 group */ -#define MEGA_XX0_1 (MEGA_XX0 || MEGA_XX1) - -/** ATmegaxx4 group */ -#define MEGA_XX4 ( \ - AVR8_PART_IS_DEFINED(ATmega164A) || \ - AVR8_PART_IS_DEFINED(ATmega164PA) || \ - AVR8_PART_IS_DEFINED(ATmega324A) || \ - AVR8_PART_IS_DEFINED(ATmega324PA) || \ - AVR8_PART_IS_DEFINED(ATmega324PB) || \ - AVR8_PART_IS_DEFINED(ATmega644) || \ - AVR8_PART_IS_DEFINED(ATmega644A) || \ - AVR8_PART_IS_DEFINED(ATmega644PA) || \ - AVR8_PART_IS_DEFINED(ATmega1284P) || \ - AVR8_PART_IS_DEFINED(ATmega128RFA1) \ - ) - -/** ATmegaxx4 group */ -#define MEGA_XX4_A ( \ - AVR8_PART_IS_DEFINED(ATmega164A) || \ - AVR8_PART_IS_DEFINED(ATmega164PA) || \ - AVR8_PART_IS_DEFINED(ATmega324A) || \ - AVR8_PART_IS_DEFINED(ATmega324PA) || \ - AVR8_PART_IS_DEFINED(ATmega644A) || \ - AVR8_PART_IS_DEFINED(ATmega644PA) || \ - AVR8_PART_IS_DEFINED(ATmega1284P) \ - ) - -/** ATmegaxx8 group */ -#define MEGA_XX8 ( \ - AVR8_PART_IS_DEFINED(ATmega48) || \ - AVR8_PART_IS_DEFINED(ATmega48A) || \ - AVR8_PART_IS_DEFINED(ATmega48PA) || \ - AVR8_PART_IS_DEFINED(ATmega48PB) || \ - AVR8_PART_IS_DEFINED(ATmega88) || \ - AVR8_PART_IS_DEFINED(ATmega88A) || \ - AVR8_PART_IS_DEFINED(ATmega88PA) || \ - AVR8_PART_IS_DEFINED(ATmega88PB) || \ - AVR8_PART_IS_DEFINED(ATmega168) || \ - AVR8_PART_IS_DEFINED(ATmega168A) || \ - AVR8_PART_IS_DEFINED(ATmega168PA) || \ - AVR8_PART_IS_DEFINED(ATmega168PB) || \ - AVR8_PART_IS_DEFINED(ATmega328) || \ - AVR8_PART_IS_DEFINED(ATmega328P) || \ - AVR8_PART_IS_DEFINED(ATmega328PB) \ - ) - -/** ATmegaxx8A/P/PA group */ -#define MEGA_XX8_A ( \ - AVR8_PART_IS_DEFINED(ATmega48A) || \ - AVR8_PART_IS_DEFINED(ATmega48PA) || \ - AVR8_PART_IS_DEFINED(ATmega88A) || \ - AVR8_PART_IS_DEFINED(ATmega88PA) || \ - AVR8_PART_IS_DEFINED(ATmega168A) || \ - AVR8_PART_IS_DEFINED(ATmega168PA) || \ - AVR8_PART_IS_DEFINED(ATmega328P) \ - ) - -/** ATmegaxx group */ -#define MEGA_XX ( \ - AVR8_PART_IS_DEFINED(ATmega16) || \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32) || \ - AVR8_PART_IS_DEFINED(ATmega32A) || \ - AVR8_PART_IS_DEFINED(ATmega64) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) - -/** ATmegaxxA/P/PA group */ -#define MEGA_XX_A ( \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32A) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) -/** ATmegaxxRFA1 group */ -#define MEGA_RFA1 ( \ - AVR8_PART_IS_DEFINED(ATmega128RFA1) \ - ) - -/** ATmegaxxRFR2 group */ -#define MEGA_RFR2 ( \ - AVR8_PART_IS_DEFINED(ATmega64RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega128RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega256RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega644RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega1284RFR2) || \ - AVR8_PART_IS_DEFINED(ATmega2564RFR2) \ - ) - - -/** ATmegaxxRFxx group */ -#define MEGA_RF (MEGA_RFA1 || MEGA_RFR2) - -/** - * \name ATmegaxx_un0/un1/un2 subgroups - * @{ - */ -#define MEGA_XX_UN0 ( \ - AVR8_PART_IS_DEFINED(ATmega16) || \ - AVR8_PART_IS_DEFINED(ATmega16A) || \ - AVR8_PART_IS_DEFINED(ATmega32) || \ - AVR8_PART_IS_DEFINED(ATmega32A) \ - ) - -/** ATmegaxx group without power reduction and - * And interrupt sense register. - */ -#define MEGA_XX_UN1 ( \ - AVR8_PART_IS_DEFINED(ATmega64) || \ - AVR8_PART_IS_DEFINED(ATmega64A) || \ - AVR8_PART_IS_DEFINED(ATmega128) || \ - AVR8_PART_IS_DEFINED(ATmega128A) \ - ) - -/** ATmegaxx group without power reduction and - * And interrupt sense register. - */ -#define MEGA_XX_UN2 ( \ - AVR8_PART_IS_DEFINED(ATmega169P) || \ - AVR8_PART_IS_DEFINED(ATmega169PA) || \ - AVR8_PART_IS_DEFINED(ATmega329P) || \ - AVR8_PART_IS_DEFINED(ATmega329PA) \ - ) - -/** Devices added to complete megaAVR offering. - * Please do not use this group symbol as it is not intended - * to be permanent: the devices should be regrouped. - */ -#define MEGA_UNCATEGORIZED ( \ - AVR8_PART_IS_DEFINED(AT90CAN128) || \ - AVR8_PART_IS_DEFINED(AT90CAN32) || \ - AVR8_PART_IS_DEFINED(AT90CAN64) || \ - AVR8_PART_IS_DEFINED(AT90PWM1) || \ - AVR8_PART_IS_DEFINED(AT90PWM216) || \ - AVR8_PART_IS_DEFINED(AT90PWM2B) || \ - AVR8_PART_IS_DEFINED(AT90PWM316) || \ - AVR8_PART_IS_DEFINED(AT90PWM3B) || \ - AVR8_PART_IS_DEFINED(AT90PWM81) || \ - AVR8_PART_IS_DEFINED(AT90USB1286) || \ - AVR8_PART_IS_DEFINED(AT90USB1287) || \ - AVR8_PART_IS_DEFINED(AT90USB162) || \ - AVR8_PART_IS_DEFINED(AT90USB646) || \ - AVR8_PART_IS_DEFINED(AT90USB647) || \ - AVR8_PART_IS_DEFINED(AT90USB82) || \ - AVR8_PART_IS_DEFINED(ATmega1284) || \ - AVR8_PART_IS_DEFINED(ATmega162) || \ - AVR8_PART_IS_DEFINED(ATmega164P) || \ - AVR8_PART_IS_DEFINED(ATmega165A) || \ - AVR8_PART_IS_DEFINED(ATmega165P) || \ - AVR8_PART_IS_DEFINED(ATmega165PA) || \ - AVR8_PART_IS_DEFINED(ATmega168P) || \ - AVR8_PART_IS_DEFINED(ATmega169A) || \ - AVR8_PART_IS_DEFINED(ATmega16M1) || \ - AVR8_PART_IS_DEFINED(ATmega16U2) || \ - AVR8_PART_IS_DEFINED(ATmega16U4) || \ - AVR8_PART_IS_DEFINED(ATmega256RFA2) || \ - AVR8_PART_IS_DEFINED(ATmega324P) || \ - AVR8_PART_IS_DEFINED(ATmega325) || \ - AVR8_PART_IS_DEFINED(ATmega3250) || \ - AVR8_PART_IS_DEFINED(ATmega3250A) || \ - AVR8_PART_IS_DEFINED(ATmega3250P) || \ - AVR8_PART_IS_DEFINED(ATmega3250PA) || \ - AVR8_PART_IS_DEFINED(ATmega325A) || \ - AVR8_PART_IS_DEFINED(ATmega325P) || \ - AVR8_PART_IS_DEFINED(ATmega325PA) || \ - AVR8_PART_IS_DEFINED(ATmega329) || \ - AVR8_PART_IS_DEFINED(ATmega3290) || \ - AVR8_PART_IS_DEFINED(ATmega3290A) || \ - AVR8_PART_IS_DEFINED(ATmega3290P) || \ - AVR8_PART_IS_DEFINED(ATmega3290PA) || \ - AVR8_PART_IS_DEFINED(ATmega329A) || \ - AVR8_PART_IS_DEFINED(ATmega32M1) || \ - AVR8_PART_IS_DEFINED(ATmega32U2) || \ - AVR8_PART_IS_DEFINED(ATmega32U4) || \ - AVR8_PART_IS_DEFINED(ATmega48P) || \ - AVR8_PART_IS_DEFINED(ATmega644P) || \ - AVR8_PART_IS_DEFINED(ATmega645) || \ - AVR8_PART_IS_DEFINED(ATmega6450) || \ - AVR8_PART_IS_DEFINED(ATmega6450A) || \ - AVR8_PART_IS_DEFINED(ATmega6450P) || \ - AVR8_PART_IS_DEFINED(ATmega645A) || \ - AVR8_PART_IS_DEFINED(ATmega645P) || \ - AVR8_PART_IS_DEFINED(ATmega649) || \ - AVR8_PART_IS_DEFINED(ATmega6490) || \ - AVR8_PART_IS_DEFINED(ATmega6490A) || \ - AVR8_PART_IS_DEFINED(ATmega6490P) || \ - AVR8_PART_IS_DEFINED(ATmega649A) || \ - AVR8_PART_IS_DEFINED(ATmega649P) || \ - AVR8_PART_IS_DEFINED(ATmega64M1) || \ - AVR8_PART_IS_DEFINED(ATmega64RFA2) || \ - AVR8_PART_IS_DEFINED(ATmega8) || \ - AVR8_PART_IS_DEFINED(ATmega8515) || \ - AVR8_PART_IS_DEFINED(ATmega8535) || \ - AVR8_PART_IS_DEFINED(ATmega88P) || \ - AVR8_PART_IS_DEFINED(ATmega8A) || \ - AVR8_PART_IS_DEFINED(ATmega8U2) \ - ) - -/** Unspecified group */ -#define MEGA_UNSPECIFIED (MEGA_XX_UN0 || MEGA_XX_UN1 || MEGA_XX_UN2 || \ - MEGA_UNCATEGORIZED) - -/** @} */ - -/** megaAVR product line */ -#define MEGA (MEGA_XX0_1 || MEGA_XX4 || MEGA_XX8 || MEGA_XX || MEGA_RF || \ - MEGA_UNSPECIFIED) - -/** @} */ - -/** - * \defgroup sam_part_macros_group SAM parts - * @{ - */ - -/** - * \name SAM3S series - * @{ - */ -#define SAM3S1 ( \ - SAM_PART_IS_DEFINED(SAM3S1A) || \ - SAM_PART_IS_DEFINED(SAM3S1B) || \ - SAM_PART_IS_DEFINED(SAM3S1C) \ - ) - -#define SAM3S2 ( \ - SAM_PART_IS_DEFINED(SAM3S2A) || \ - SAM_PART_IS_DEFINED(SAM3S2B) || \ - SAM_PART_IS_DEFINED(SAM3S2C) \ - ) - -#define SAM3S4 ( \ - SAM_PART_IS_DEFINED(SAM3S4A) || \ - SAM_PART_IS_DEFINED(SAM3S4B) || \ - SAM_PART_IS_DEFINED(SAM3S4C) \ - ) - -#define SAM3S8 ( \ - SAM_PART_IS_DEFINED(SAM3S8B) || \ - SAM_PART_IS_DEFINED(SAM3S8C) \ - ) - -#define SAM3SD8 ( \ - SAM_PART_IS_DEFINED(SAM3SD8B) || \ - SAM_PART_IS_DEFINED(SAM3SD8C) \ - ) -/** @} */ - -/** - * \name SAM3U series - * @{ - */ -#define SAM3U1 ( \ - SAM_PART_IS_DEFINED(SAM3U1C) || \ - SAM_PART_IS_DEFINED(SAM3U1E) \ - ) - -#define SAM3U2 ( \ - SAM_PART_IS_DEFINED(SAM3U2C) || \ - SAM_PART_IS_DEFINED(SAM3U2E) \ - ) - -#define SAM3U4 ( \ - SAM_PART_IS_DEFINED(SAM3U4C) || \ - SAM_PART_IS_DEFINED(SAM3U4E) \ - ) -/** @} */ - -/** - * \name SAM3N series - * @{ - */ -#define SAM3N00 ( \ - SAM_PART_IS_DEFINED(SAM3N00A) || \ - SAM_PART_IS_DEFINED(SAM3N00B) \ - ) - -#define SAM3N0 ( \ - SAM_PART_IS_DEFINED(SAM3N0A) || \ - SAM_PART_IS_DEFINED(SAM3N0B) || \ - SAM_PART_IS_DEFINED(SAM3N0C) \ - ) - -#define SAM3N1 ( \ - SAM_PART_IS_DEFINED(SAM3N1A) || \ - SAM_PART_IS_DEFINED(SAM3N1B) || \ - SAM_PART_IS_DEFINED(SAM3N1C) \ - ) - -#define SAM3N2 ( \ - SAM_PART_IS_DEFINED(SAM3N2A) || \ - SAM_PART_IS_DEFINED(SAM3N2B) || \ - SAM_PART_IS_DEFINED(SAM3N2C) \ - ) - -#define SAM3N4 ( \ - SAM_PART_IS_DEFINED(SAM3N4A) || \ - SAM_PART_IS_DEFINED(SAM3N4B) || \ - SAM_PART_IS_DEFINED(SAM3N4C) \ - ) -/** @} */ - -/** - * \name SAM3X series - * @{ - */ -#define SAM3X4 ( \ - SAM_PART_IS_DEFINED(SAM3X4C) || \ - SAM_PART_IS_DEFINED(SAM3X4E) \ - ) - -#define SAM3X8 ( \ - SAM_PART_IS_DEFINED(SAM3X8C) || \ - SAM_PART_IS_DEFINED(SAM3X8E) || \ - SAM_PART_IS_DEFINED(SAM3X8H) \ - ) -/** @} */ - -/** - * \name SAM3A series - * @{ - */ -#define SAM3A4 ( \ - SAM_PART_IS_DEFINED(SAM3A4C) \ - ) - -#define SAM3A8 ( \ - SAM_PART_IS_DEFINED(SAM3A8C) \ - ) -/** @} */ - -/** - * \name SAM4S series - * @{ - */ -#define SAM4S2 ( \ - SAM_PART_IS_DEFINED(SAM4S2A) || \ - SAM_PART_IS_DEFINED(SAM4S2B) || \ - SAM_PART_IS_DEFINED(SAM4S2C) \ - ) - -#define SAM4S4 ( \ - SAM_PART_IS_DEFINED(SAM4S4A) || \ - SAM_PART_IS_DEFINED(SAM4S4B) || \ - SAM_PART_IS_DEFINED(SAM4S4C) \ - ) - -#define SAM4S8 ( \ - SAM_PART_IS_DEFINED(SAM4S8B) || \ - SAM_PART_IS_DEFINED(SAM4S8C) \ - ) - -#define SAM4S16 ( \ - SAM_PART_IS_DEFINED(SAM4S16B) || \ - SAM_PART_IS_DEFINED(SAM4S16C) \ - ) - -#define SAM4SA16 ( \ - SAM_PART_IS_DEFINED(SAM4SA16B) || \ - SAM_PART_IS_DEFINED(SAM4SA16C) \ - ) - -#define SAM4SD16 ( \ - SAM_PART_IS_DEFINED(SAM4SD16B) || \ - SAM_PART_IS_DEFINED(SAM4SD16C) \ - ) - -#define SAM4SD32 ( \ - SAM_PART_IS_DEFINED(SAM4SD32B) || \ - SAM_PART_IS_DEFINED(SAM4SD32C) \ - ) -/** @} */ - -/** - * \name SAM4L series - * @{ - */ -#define SAM4LS ( \ - SAM_PART_IS_DEFINED(SAM4LS2A) || \ - SAM_PART_IS_DEFINED(SAM4LS2B) || \ - SAM_PART_IS_DEFINED(SAM4LS2C) || \ - SAM_PART_IS_DEFINED(SAM4LS4A) || \ - SAM_PART_IS_DEFINED(SAM4LS4B) || \ - SAM_PART_IS_DEFINED(SAM4LS4C) || \ - SAM_PART_IS_DEFINED(SAM4LS8A) || \ - SAM_PART_IS_DEFINED(SAM4LS8B) || \ - SAM_PART_IS_DEFINED(SAM4LS8C) \ - ) - -#define SAM4LC ( \ - SAM_PART_IS_DEFINED(SAM4LC2A) || \ - SAM_PART_IS_DEFINED(SAM4LC2B) || \ - SAM_PART_IS_DEFINED(SAM4LC2C) || \ - SAM_PART_IS_DEFINED(SAM4LC4A) || \ - SAM_PART_IS_DEFINED(SAM4LC4B) || \ - SAM_PART_IS_DEFINED(SAM4LC4C) || \ - SAM_PART_IS_DEFINED(SAM4LC8A) || \ - SAM_PART_IS_DEFINED(SAM4LC8B) || \ - SAM_PART_IS_DEFINED(SAM4LC8C) \ - ) -/** @} */ - -/** - * \name SAMD20 series - * @{ - */ -#define SAMD20J ( \ - SAM_PART_IS_DEFINED(SAMD20J14) || \ - SAM_PART_IS_DEFINED(SAMD20J15) || \ - SAM_PART_IS_DEFINED(SAMD20J16) || \ - SAM_PART_IS_DEFINED(SAMD20J17) || \ - SAM_PART_IS_DEFINED(SAMD20J18) \ - ) - -#define SAMD20G ( \ - SAM_PART_IS_DEFINED(SAMD20G14) || \ - SAM_PART_IS_DEFINED(SAMD20G15) || \ - SAM_PART_IS_DEFINED(SAMD20G16) || \ - SAM_PART_IS_DEFINED(SAMD20G17) || \ - SAM_PART_IS_DEFINED(SAMD20G17U) || \ - SAM_PART_IS_DEFINED(SAMD20G18) || \ - SAM_PART_IS_DEFINED(SAMD20G18U) \ - ) - -#define SAMD20E ( \ - SAM_PART_IS_DEFINED(SAMD20E14) || \ - SAM_PART_IS_DEFINED(SAMD20E15) || \ - SAM_PART_IS_DEFINED(SAMD20E16) || \ - SAM_PART_IS_DEFINED(SAMD20E17) || \ - SAM_PART_IS_DEFINED(SAMD20E18) \ - ) -/** @} */ - -/** - * \name SAMD21 series - * @{ - */ -#define SAMD21J ( \ - SAM_PART_IS_DEFINED(SAMD21J15A) || \ - SAM_PART_IS_DEFINED(SAMD21J16A) || \ - SAM_PART_IS_DEFINED(SAMD21J17A) || \ - SAM_PART_IS_DEFINED(SAMD21J18A) || \ - SAM_PART_IS_DEFINED(SAMD21J15B) || \ - SAM_PART_IS_DEFINED(SAMD21J16B) \ - ) - -#define SAMD21G ( \ - SAM_PART_IS_DEFINED(SAMD21G15A) || \ - SAM_PART_IS_DEFINED(SAMD21G16A) || \ - SAM_PART_IS_DEFINED(SAMD21G17A) || \ - SAM_PART_IS_DEFINED(SAMD21G17AU) || \ - SAM_PART_IS_DEFINED(SAMD21G18A) || \ - SAM_PART_IS_DEFINED(SAMD21G18AU) || \ - SAM_PART_IS_DEFINED(SAMD21G15B) || \ - SAM_PART_IS_DEFINED(SAMD21G16B) || \ - SAM_PART_IS_DEFINED(SAMD21G15L) || \ - SAM_PART_IS_DEFINED(SAMD21G16L) \ - ) - -#define SAMD21GXXL ( \ - SAM_PART_IS_DEFINED(SAMD21G15L) || \ - SAM_PART_IS_DEFINED(SAMD21G16L) \ - ) - -#define SAMD21E ( \ - SAM_PART_IS_DEFINED(SAMD21E15A) || \ - SAM_PART_IS_DEFINED(SAMD21E16A) || \ - SAM_PART_IS_DEFINED(SAMD21E17A) || \ - SAM_PART_IS_DEFINED(SAMD21E18A) || \ - SAM_PART_IS_DEFINED(SAMD21E15B) || \ - SAM_PART_IS_DEFINED(SAMD21E15BU) || \ - SAM_PART_IS_DEFINED(SAMD21E16B) || \ - SAM_PART_IS_DEFINED(SAMD21E16BU) || \ - SAM_PART_IS_DEFINED(SAMD21E15L) || \ - SAM_PART_IS_DEFINED(SAMD21E16L) \ - ) - -#define SAMD21EXXL ( \ - SAM_PART_IS_DEFINED(SAMD21E15L) || \ - SAM_PART_IS_DEFINED(SAMD21E16L) \ - ) - -/** @} */ - -/** - * \name SAMR21 series - * @{ - */ -#define SAMR21G ( \ - SAM_PART_IS_DEFINED(SAMR21G16A) || \ - SAM_PART_IS_DEFINED(SAMR21G17A) || \ - SAM_PART_IS_DEFINED(SAMR21G18A) \ - ) - -#define SAMR21E ( \ - SAM_PART_IS_DEFINED(SAMR21E16A) || \ - SAM_PART_IS_DEFINED(SAMR21E17A) || \ - SAM_PART_IS_DEFINED(SAMR21E18A) || \ - SAM_PART_IS_DEFINED(SAMR21E19A) \ - ) -/** @} */ - -/** - * \name SAMR30 series - * @{ - */ -#define SAMR30G ( \ - SAM_PART_IS_DEFINED(SAMR30G18A) \ - ) - -#define SAMR30E ( \ - SAM_PART_IS_DEFINED(SAMR30E18A) \ - ) -/** @} */ - -/** - * \name SAMB11 series - * @{ - */ -#define SAMB11G ( \ - SAM_PART_IS_DEFINED(SAMB11G18A) || \ - SAM_PART_IS_DEFINED(SAMB11ZR) \ - ) -#define BTLC1000 ( \ - SAM_PART_IS_DEFINED(BTLC1000WLCSP) \ - ) - -/** @} */ - -/** - * \name SAMD09 series - * @{ - */ -#define SAMD09C ( \ - SAM_PART_IS_DEFINED(SAMD09C13A) \ - ) - -#define SAMD09D ( \ - SAM_PART_IS_DEFINED(SAMD09D14A) \ - ) -/** @} */ - -/** - * \name SAMD10 series - * @{ - */ -#define SAMD10C ( \ - SAM_PART_IS_DEFINED(SAMD10C12A) || \ - SAM_PART_IS_DEFINED(SAMD10C13A) || \ - SAM_PART_IS_DEFINED(SAMD10C14A) \ - ) - -#define SAMD10DS ( \ - SAM_PART_IS_DEFINED(SAMD10D12AS) || \ - SAM_PART_IS_DEFINED(SAMD10D13AS) || \ - SAM_PART_IS_DEFINED(SAMD10D14AS) \ - ) - -#define SAMD10DM ( \ - SAM_PART_IS_DEFINED(SAMD10D12AM) || \ - SAM_PART_IS_DEFINED(SAMD10D13AM) || \ - SAM_PART_IS_DEFINED(SAMD10D14AM) \ - ) - -#define SAMD10DU ( \ - SAM_PART_IS_DEFINED(SAMD10D14AU) \ - ) -/** @} */ - -/** - * \name SAMD11 series - * @{ - */ -#define SAMD11C ( \ - SAM_PART_IS_DEFINED(SAMD11C14A) \ - ) - -#define SAMD11DS ( \ - SAM_PART_IS_DEFINED(SAMD11D14AS) \ - ) - -#define SAMD11DM ( \ - SAM_PART_IS_DEFINED(SAMD11D14AM) \ - ) - -#define SAMD11DU ( \ - SAM_PART_IS_DEFINED(SAMD11D14AU) \ - ) -/** @} */ - -/** - * \name SAML21 series - * @{ - */ -#define SAML21E ( \ - SAM_PART_IS_DEFINED(SAML21E18A) || \ - SAM_PART_IS_DEFINED(SAML21E15B) || \ - SAM_PART_IS_DEFINED(SAML21E16B) || \ - SAM_PART_IS_DEFINED(SAML21E17B) || \ - SAM_PART_IS_DEFINED(SAML21E18B) \ - ) - -#define SAML21G ( \ - SAM_PART_IS_DEFINED(SAML21G18A) || \ - SAM_PART_IS_DEFINED(SAML21G16B) || \ - SAM_PART_IS_DEFINED(SAML21G17B) || \ - SAM_PART_IS_DEFINED(SAML21G18B) \ - ) - -#define SAML21J ( \ - SAM_PART_IS_DEFINED(SAML21J18A) || \ - SAM_PART_IS_DEFINED(SAML21J16B) || \ - SAM_PART_IS_DEFINED(SAML21J17B) || \ - SAM_PART_IS_DEFINED(SAML21J18B) \ - ) - -/* Group for SAML21 A variant: SAML21[E/G/J][18]A */ -#define SAML21XXXA ( \ - SAM_PART_IS_DEFINED(SAML21E18A) || \ - SAM_PART_IS_DEFINED(SAML21G18A) || \ - SAM_PART_IS_DEFINED(SAML21J18A) \ - ) - -/* Group for SAML21 B variant: SAML21[E/G/J][15/16/1718]B */ -#define SAML21XXXB ( \ - SAM_PART_IS_DEFINED(SAML21E15B) || \ - SAM_PART_IS_DEFINED(SAML21E16B) || \ - SAM_PART_IS_DEFINED(SAML21E17B) || \ - SAM_PART_IS_DEFINED(SAML21E18B) || \ - SAM_PART_IS_DEFINED(SAML21G16B) || \ - SAM_PART_IS_DEFINED(SAML21G17B) || \ - SAM_PART_IS_DEFINED(SAML21G18B) || \ - SAM_PART_IS_DEFINED(SAML21J16B) || \ - SAM_PART_IS_DEFINED(SAML21J17B) || \ - SAM_PART_IS_DEFINED(SAML21J18B) \ - ) - -/** @} */ - -/** - * \name SAML22 series - * @{ - */ -#define SAML22N ( \ - SAM_PART_IS_DEFINED(SAML22N16A) || \ - SAM_PART_IS_DEFINED(SAML22N17A) || \ - SAM_PART_IS_DEFINED(SAML22N18A) \ - ) - -#define SAML22G ( \ - SAM_PART_IS_DEFINED(SAML22G16A) || \ - SAM_PART_IS_DEFINED(SAML22G17A) || \ - SAM_PART_IS_DEFINED(SAML22G18A) \ - ) - -#define SAML22J ( \ - SAM_PART_IS_DEFINED(SAML22J16A) || \ - SAM_PART_IS_DEFINED(SAML22J17A) || \ - SAM_PART_IS_DEFINED(SAML22J18A) \ - ) -/** @} */ - -/** - * \name SAMDA0 series - * @{ - */ -#define SAMDA0J ( \ - SAM_PART_IS_DEFINED(SAMDA0J14A) || \ - SAM_PART_IS_DEFINED(SAMDA0J15A) || \ - SAM_PART_IS_DEFINED(SAMDA0J16A) \ - ) - -#define SAMDA0G ( \ - SAM_PART_IS_DEFINED(SAMDA0G14A) || \ - SAM_PART_IS_DEFINED(SAMDA0G15A) || \ - SAM_PART_IS_DEFINED(SAMDA0G16A) \ - ) - -#define SAMDA0E ( \ - SAM_PART_IS_DEFINED(SAMDA0E14A) || \ - SAM_PART_IS_DEFINED(SAMDA0E15A) || \ - SAM_PART_IS_DEFINED(SAMDA0E16A) \ - ) -/** @} */ - -/** - * \name SAMDA1 series - * @{ - */ -#define SAMDA1J ( \ - SAM_PART_IS_DEFINED(SAMDA1J14A) || \ - SAM_PART_IS_DEFINED(SAMDA1J15A) || \ - SAM_PART_IS_DEFINED(SAMDA1J16A) \ - ) - -#define SAMDA1G ( \ - SAM_PART_IS_DEFINED(SAMDA1G14A) || \ - SAM_PART_IS_DEFINED(SAMDA1G15A) || \ - SAM_PART_IS_DEFINED(SAMDA1G16A) \ - ) - -#define SAMDA1E ( \ - SAM_PART_IS_DEFINED(SAMDA1E14A) || \ - SAM_PART_IS_DEFINED(SAMDA1E15A) || \ - SAM_PART_IS_DEFINED(SAMDA1E16A) \ - ) -/** @} */ - -/** - * \name SAMC20 series - * @{ - */ -#define SAMC20E ( \ - SAM_PART_IS_DEFINED(SAMC20E15A) || \ - SAM_PART_IS_DEFINED(SAMC20E16A) || \ - SAM_PART_IS_DEFINED(SAMC20E17A) || \ - SAM_PART_IS_DEFINED(SAMC20E18A) \ - ) - -#define SAMC20G ( \ - SAM_PART_IS_DEFINED(SAMC20G15A) || \ - SAM_PART_IS_DEFINED(SAMC20G16A) || \ - SAM_PART_IS_DEFINED(SAMC20G17A) || \ - SAM_PART_IS_DEFINED(SAMC20G18A) \ - ) - -#define SAMC20J ( \ - SAM_PART_IS_DEFINED(SAMC20J15A) || \ - SAM_PART_IS_DEFINED(SAMC20J16A) || \ - SAM_PART_IS_DEFINED(SAMC20J17A) || \ - SAM_PART_IS_DEFINED(SAMC20J18A) \ - ) -/** @} */ - -/** - * \name SAMC21 series - * @{ - */ -#define SAMC21E ( \ - SAM_PART_IS_DEFINED(SAMC21E15A) || \ - SAM_PART_IS_DEFINED(SAMC21E16A) || \ - SAM_PART_IS_DEFINED(SAMC21E17A) || \ - SAM_PART_IS_DEFINED(SAMC21E18A) \ - ) - -#define SAMC21G ( \ - SAM_PART_IS_DEFINED(SAMC21G15A) || \ - SAM_PART_IS_DEFINED(SAMC21G16A) || \ - SAM_PART_IS_DEFINED(SAMC21G17A) || \ - SAM_PART_IS_DEFINED(SAMC21G18A) \ - ) - -#define SAMC21J ( \ - SAM_PART_IS_DEFINED(SAMC21J15A) || \ - SAM_PART_IS_DEFINED(SAMC21J16A) || \ - SAM_PART_IS_DEFINED(SAMC21J17A) || \ - SAM_PART_IS_DEFINED(SAMC21J18A) \ - ) -/** @} */ - -/** - * \name SAM4E series - * @{ - */ -#define SAM4E8 ( \ - SAM_PART_IS_DEFINED(SAM4E8C) || \ - SAM_PART_IS_DEFINED(SAM4E8CB) || \ - SAM_PART_IS_DEFINED(SAM4E8E) \ - ) - -#define SAM4E16 ( \ - SAM_PART_IS_DEFINED(SAM4E16C) || \ - SAM_PART_IS_DEFINED(SAM4E16CB) || \ - SAM_PART_IS_DEFINED(SAM4E16E) \ - ) -/** @} */ - -/** - * \name SAM4N series - * @{ - */ -#define SAM4N8 ( \ - SAM_PART_IS_DEFINED(SAM4N8A) || \ - SAM_PART_IS_DEFINED(SAM4N8B) || \ - SAM_PART_IS_DEFINED(SAM4N8C) \ - ) - -#define SAM4N16 ( \ - SAM_PART_IS_DEFINED(SAM4N16B) || \ - SAM_PART_IS_DEFINED(SAM4N16C) \ - ) -/** @} */ - -/** - * \name SAM4C series - * @{ - */ -#define SAM4C4_0 ( \ - SAM_PART_IS_DEFINED(SAM4C4C_0) \ - ) - -#define SAM4C4_1 ( \ - SAM_PART_IS_DEFINED(SAM4C4C_1) \ - ) - -#define SAM4C4 (SAM4C4_0 || SAM4C4_1) - -#define SAM4C8_0 ( \ - SAM_PART_IS_DEFINED(SAM4C8C_0) \ - ) - -#define SAM4C8_1 ( \ - SAM_PART_IS_DEFINED(SAM4C8C_1) \ - ) - -#define SAM4C8 (SAM4C8_0 || SAM4C8_1) - -#define SAM4C16_0 ( \ - SAM_PART_IS_DEFINED(SAM4C16C_0) \ - ) - -#define SAM4C16_1 ( \ - SAM_PART_IS_DEFINED(SAM4C16C_1) \ - ) - -#define SAM4C16 (SAM4C16_0 || SAM4C16_1) - -#define SAM4C32_0 ( \ - SAM_PART_IS_DEFINED(SAM4C32C_0) ||\ - SAM_PART_IS_DEFINED(SAM4C32E_0) \ - ) - -#define SAM4C32_1 ( \ - SAM_PART_IS_DEFINED(SAM4C32C_1) ||\ - SAM_PART_IS_DEFINED(SAM4C32E_1) \ - ) - - -#define SAM4C32 (SAM4C32_0 || SAM4C32_1) - -/** @} */ - -/** - * \name SAM4CM series - * @{ - */ -#define SAM4CMP8_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMP8C_0) \ - ) - -#define SAM4CMP8_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMP8C_1) \ - ) - -#define SAM4CMP8 (SAM4CMP8_0 || SAM4CMP8_1) - -#define SAM4CMP16_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMP16C_0) \ - ) - -#define SAM4CMP16_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMP16C_1) \ - ) - -#define SAM4CMP16 (SAM4CMP16_0 || SAM4CMP16_1) - -#define SAM4CMP32_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMP32C_0) \ - ) - -#define SAM4CMP32_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMP32C_1) \ - ) - -#define SAM4CMP32 (SAM4CMP32_0 || SAM4CMP32_1) - -#define SAM4CMS4_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMS4C_0) \ - ) - -#define SAM4CMS4_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMS4C_1) \ - ) - -#define SAM4CMS4 (SAM4CMS4_0 || SAM4CMS4_1) - -#define SAM4CMS8_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMS8C_0) \ - ) - -#define SAM4CMS8_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMS8C_1) \ - ) - -#define SAM4CMS8 (SAM4CMS8_0 || SAM4CMS8_1) - -#define SAM4CMS16_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMS16C_0) \ - ) - -#define SAM4CMS16_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMS16C_1) \ - ) - -#define SAM4CMS16 (SAM4CMS16_0 || SAM4CMS16_1) - -#define SAM4CMS32_0 ( \ - SAM_PART_IS_DEFINED(SAM4CMS32C_0) \ - ) - -#define SAM4CMS32_1 ( \ - SAM_PART_IS_DEFINED(SAM4CMS32C_1) \ - ) - -#define SAM4CMS32 (SAM4CMS32_0 || SAM4CMS32_1) - -/** @} */ - -/** - * \name SAM4CP series - * @{ - */ -#define SAM4CP16_0 ( \ - SAM_PART_IS_DEFINED(SAM4CP16B_0) \ - ) - -#define SAM4CP16_1 ( \ - SAM_PART_IS_DEFINED(SAM4CP16B_1) \ - ) - -#define SAM4CP16 (SAM4CP16_0 || SAM4CP16_1) -/** @} */ - -/** - * \name SAMG series - * @{ - */ -#define SAMG51 ( \ - SAM_PART_IS_DEFINED(SAMG51G18) \ - ) - -#define SAMG53 ( \ - SAM_PART_IS_DEFINED(SAMG53G19) ||\ - SAM_PART_IS_DEFINED(SAMG53N19) \ - ) - -#define SAMG54 ( \ - SAM_PART_IS_DEFINED(SAMG54G19) ||\ - SAM_PART_IS_DEFINED(SAMG54J19) ||\ - SAM_PART_IS_DEFINED(SAMG54N19) \ - ) - -#define SAMG55 ( \ - SAM_PART_IS_DEFINED(SAMG55G18) ||\ - SAM_PART_IS_DEFINED(SAMG55G19) ||\ - SAM_PART_IS_DEFINED(SAMG55J18) ||\ - SAM_PART_IS_DEFINED(SAMG55J19) ||\ - SAM_PART_IS_DEFINED(SAMG55N19) \ - ) -/** @} */ - -/** - * \name SAMV71 series - * @{ - */ -#define SAMV71J ( \ - SAM_PART_IS_DEFINED(SAMV71J19) || \ - SAM_PART_IS_DEFINED(SAMV71J20) || \ - SAM_PART_IS_DEFINED(SAMV71J21) \ - ) - -#define SAMV71N ( \ - SAM_PART_IS_DEFINED(SAMV71N19) || \ - SAM_PART_IS_DEFINED(SAMV71N20) || \ - SAM_PART_IS_DEFINED(SAMV71N21) \ - ) - -#define SAMV71Q ( \ - SAM_PART_IS_DEFINED(SAMV71Q19) || \ - SAM_PART_IS_DEFINED(SAMV71Q20) || \ - SAM_PART_IS_DEFINED(SAMV71Q21) \ - ) -/** @} */ - -/** - * \name SAMV70 series - * @{ - */ -#define SAMV70J ( \ - SAM_PART_IS_DEFINED(SAMV70J19) || \ - SAM_PART_IS_DEFINED(SAMV70J20) \ - ) - -#define SAMV70N ( \ - SAM_PART_IS_DEFINED(SAMV70N19) || \ - SAM_PART_IS_DEFINED(SAMV70N20) \ - ) - -#define SAMV70Q ( \ - SAM_PART_IS_DEFINED(SAMV70Q19) || \ - SAM_PART_IS_DEFINED(SAMV70Q20) \ - ) -/** @} */ - -/** - * \name SAMS70 series - * @{ - */ -#define SAMS70J ( \ - SAM_PART_IS_DEFINED(SAMS70J19) || \ - SAM_PART_IS_DEFINED(SAMS70J20) || \ - SAM_PART_IS_DEFINED(SAMS70J21) \ - ) - -#define SAMS70N ( \ - SAM_PART_IS_DEFINED(SAMS70N19) || \ - SAM_PART_IS_DEFINED(SAMS70N20) || \ - SAM_PART_IS_DEFINED(SAMS70N21) \ - ) - -#define SAMS70Q ( \ - SAM_PART_IS_DEFINED(SAMS70Q19) || \ - SAM_PART_IS_DEFINED(SAMS70Q20) || \ - SAM_PART_IS_DEFINED(SAMS70Q21) \ - ) -/** @} */ - -/** - * \name SAME70 series - * @{ - */ -#define SAME70J ( \ - SAM_PART_IS_DEFINED(SAME70J19) || \ - SAM_PART_IS_DEFINED(SAME70J20) || \ - SAM_PART_IS_DEFINED(SAME70J21) \ - ) - -#define SAME70N ( \ - SAM_PART_IS_DEFINED(SAME70N19) || \ - SAM_PART_IS_DEFINED(SAME70N20) || \ - SAM_PART_IS_DEFINED(SAME70N21) \ - ) - -#define SAME70Q ( \ - SAM_PART_IS_DEFINED(SAME70Q19) || \ - SAM_PART_IS_DEFINED(SAME70Q20) || \ - SAM_PART_IS_DEFINED(SAME70Q21) \ - ) -/** @} */ - -/** - * \name SAM families - * @{ - */ -/** SAM3S Family */ -#define SAM3S (SAM3S1 || SAM3S2 || SAM3S4 || SAM3S8 || SAM3SD8) - -/** SAM3U Family */ -#define SAM3U (SAM3U1 || SAM3U2 || SAM3U4) - -/** SAM3N Family */ -#define SAM3N (SAM3N00 || SAM3N0 || SAM3N1 || SAM3N2 || SAM3N4) - -/** SAM3XA Family */ -#define SAM3XA (SAM3X4 || SAM3X8 || SAM3A4 || SAM3A8) - -/** SAM4S Family */ -#define SAM4S (SAM4S2 || SAM4S4 || SAM4S8 || SAM4S16 || SAM4SA16 || SAM4SD16 || SAM4SD32) - -/** SAM4L Family */ -#define SAM4L (SAM4LS || SAM4LC) - -/** SAMD20 Family */ -#define SAMD20 (SAMD20J || SAMD20G || SAMD20E) - -/** SAMD21 Family */ -#define SAMD21 (SAMD21J || SAMD21G || SAMD21E) - -/** SAMD09 Family */ -#define SAMD09 (SAMD09C || SAMD09D) - -/** SAMD10 Family */ -#define SAMD10 (SAMD10C || SAMD10DS || SAMD10DM || SAMD10DU) - -/** SAMD11 Family */ -#define SAMD11 (SAMD11C || SAMD11DS || SAMD11DM || SAMD11DU) - -/** SAMDA1 Family */ -#define SAMDA1 (SAMDA1J || SAMDA1G || SAMDA1E) - -/** SAMD Family */ -#define SAMD (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAMDA1) - -/** SAMR21 Family */ -#define SAMR21 (SAMR21G || SAMR21E) - -/** SAMR30 Family */ -#define SAMR30 (SAMR30G || SAMR30E) - -/** SAMB11 Family */ -#define SAMB11 (SAMB11G || BTLC1000) - -/** SAML21 Family */ -#define SAML21 (SAML21J || SAML21G || SAML21E) - -/** SAML22 Family */ -#define SAML22 (SAML22J || SAML22G || SAML22N) -/** SAMC20 Family */ -#define SAMC20 (SAMC20J || SAMC20G || SAMC20E) - -/** SAMC21 Family */ -#define SAMC21 (SAMC21J || SAMC21G || SAMC21E) - -/** SAM4E Family */ -#define SAM4E (SAM4E8 || SAM4E16) - -/** SAM4N Family */ -#define SAM4N (SAM4N8 || SAM4N16) - -/** SAM4C Family */ -#define SAM4C_0 (SAM4C4_0 || SAM4C8_0 || SAM4C16_0 || SAM4C32_0) -#define SAM4C_1 (SAM4C4_1 || SAM4C8_1 || SAM4C16_1 || SAM4C32_1) -#define SAM4C (SAM4C4 || SAM4C8 || SAM4C16 || SAM4C32) - -/** SAM4CM Family */ -#define SAM4CM_0 (SAM4CMP8_0 || SAM4CMP16_0 || SAM4CMP32_0 || \ - SAM4CMS4_0 || SAM4CMS8_0 || SAM4CMS16_0 || SAM4CMS32_0) -#define SAM4CM_1 (SAM4CMP8_1 || SAM4CMP16_1 || SAM4CMP32_1 || \ - SAM4CMS4_1 || SAM4CMS8_1 || SAM4CMS16_1 || SAM4CMS32_1) -#define SAM4CM (SAM4CMP8 || SAM4CMP16 || SAM4CMP32 || \ - SAM4CMS4 || SAM4CMS8 || SAM4CMS16 || SAM4CMS32) - -/** SAM4CP Family */ -#define SAM4CP_0 (SAM4CP16_0) -#define SAM4CP_1 (SAM4CP16_1) -#define SAM4CP (SAM4CP16) - -/** SAMG Family */ -#define SAMG (SAMG51 || SAMG53 || SAMG54 || SAMG55) - -/** SAMB Family */ -#define SAMB (SAMB11) - -/** SAMV71 Family */ -#define SAMV71 (SAMV71J || SAMV71N || SAMV71Q) - -/** SAMV70 Family */ -#define SAMV70 (SAMV70J || SAMV70N || SAMV70Q) - -/** SAME70 Family */ -#define SAME70 (SAME70J || SAME70N || SAME70Q) - -/** SAMS70 Family */ -#define SAMS70 (SAMS70J || SAMS70N || SAMS70Q) - -/** SAM0 product line (cortex-m0+) */ -#define SAM0 (SAMD20 || SAMD21 || SAMR21 || SAMD10 || SAMD11 || SAML21 ||\ - SAMDA1 || SAMC20 || SAMC21 || SAML22 || SAMD09 || SAMR30) - -/** @} */ - -/** SAM product line */ -#define SAM (SAM3S || SAM3U || SAM3N || SAM3XA || SAM4S || SAM4L || SAM4E || \ - SAM0 || SAM4N || SAM4C || SAM4CM || SAM4CP || SAMG || SAMV71 || SAMV70 || SAME70 || SAMS70) - -/** @} */ - -/** @} */ - -/** @} */ - -#endif /* ATMEL_PARTS_H */ diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_mega/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_mega/doxyfile.doxygen deleted file mode 100644 index 3cd4ea7452edc..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_mega/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard I/O (stdio) Interface - mega implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../read.c ../../write.c - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_mega/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_mega/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_mega/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_sam/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_sam/doxyfile.doxygen deleted file mode 100644 index e4865072ab1ba..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_sam/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard I/O (stdio) Interface - SAM implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../read.c ../../write.c - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_sam/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_sam/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_sam/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_uc3/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_uc3/doxyfile.doxygen deleted file mode 100644 index 487a3ff8f4e01..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_uc3/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard I/O (stdio) Interface - UC3 implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../read.c ../../write.c - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_uc3/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_uc3/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_uc3/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_xmega/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_xmega/doxyfile.doxygen deleted file mode 100644 index 8cf8e3567509b..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_xmega/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard I/O (stdio) Interface - XMEGA implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../read.c ../../write.c - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_xmega/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_xmega/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/doxygen/common.utils.stdio_xmega/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/read.c b/atmel-samd/asf/common/utils/stdio/read.c deleted file mode 100644 index 1326308be5589..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/read.c +++ /dev/null @@ -1,167 +0,0 @@ -/** - * \file - * - * \brief System-specific implementation of the \ref _read function used by - * the standard library. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "compiler.h" - -/** - * \defgroup group_common_utils_stdio Standard I/O (stdio) - * - * Common standard I/O driver that implements the stdio - * read and write functions on AVR and SAM devices. - * - * \{ - */ - -extern volatile void *volatile stdio_base; -void (*ptr_get)(void volatile*, char*); - - -// IAR common implementation -#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__) ) - -#include - -_STD_BEGIN - -#pragma module_name = "?__read" - -/*! \brief Reads a number of bytes, at most \a size, into the memory area - * pointed to by \a buffer. - * - * \param handle File handle to read from. - * \param buffer Pointer to buffer to write read bytes to. - * \param size Number of bytes to read. - * - * \return The number of bytes read, \c 0 at the end of the file, or - * \c _LLIO_ERROR on failure. - */ -size_t __read(int handle, unsigned char *buffer, size_t size) -{ - int nChars = 0; - // This implementation only reads from stdin. - // For all other file handles, it returns failure. - if (handle != _LLIO_STDIN) { - return _LLIO_ERROR; - } - for (; size > 0; --size) { - ptr_get(stdio_base, (char*)buffer); - buffer++; - nChars++; - } - return nChars; -} - -/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 - * the implementation is empty to be compatible with old IAR version. - */ -int __close(int handle) -{ - UNUSED(handle); - return 0; -} - -/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 - * the implementation is empty to be compatible with old IAR version. - */ -int remove(const char* val) -{ - UNUSED(val); - return 0; -} - -/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 - * the implementation is empty to be compatible with old IAR version. - */ -long __lseek(int handle, long val, int val2) -{ - UNUSED(handle); - UNUSED(val2); - return val; -} - -_STD_END - -// GCC AVR32 and SAM implementation -#elif (defined(__GNUC__) && !XMEGA && !MEGA) - -int __attribute__((weak)) -_read (int file, char * ptr, int len); // Remove GCC compiler warning - -int __attribute__((weak)) -_read (int file, char * ptr, int len) -{ - int nChars = 0; - - if (file != 0) { - return -1; - } - - for (; len > 0; --len) { - ptr_get(stdio_base, ptr); - ptr++; - nChars++; - } - return nChars; -} - -// GCC AVR implementation -#elif (defined(__GNUC__) && (XMEGA || MEGA) ) - -int _read (int *f); // Remove GCC compiler warning - -int _read (int *f) -{ - char c; - ptr_get(stdio_base,&c); - return c; -} -#endif - -/** - * \} - */ - diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_megarf/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_megarf/doxyfile.doxygen deleted file mode 100644 index 37f5fe91d2e41..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_megarf/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard serial I/O (stdio) - MEGARF implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. 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If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. 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The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_serial.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 __AVR_ATmega128RFA1__ - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_megarf/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_megarf/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_megarf/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_sam/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_sam/doxyfile.doxygen deleted file mode 100644 index ed56467d6082c..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_sam/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard serial I/O (stdio) - SAM implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_serial.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_sam/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_sam/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_sam/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_uc3/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_uc3/doxyfile.doxygen deleted file mode 100644 index 6e510805b1c42..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_uc3/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard serial I/O (stdio) - UC3 implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_serial.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_uc3/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_uc3/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_uc3/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_xmega/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_xmega/doxyfile.doxygen deleted file mode 100644 index b030532735b7e..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_xmega/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard serial I/O (stdio) - XMEGA implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_serial.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_xmega/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_xmega/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/doxygen/common.utils.stdio.stdio_serial_xmega/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_serial/stdio_serial.h b/atmel-samd/asf/common/utils/stdio/stdio_serial/stdio_serial.h deleted file mode 100644 index 4315d3fcdc1e8..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_serial/stdio_serial.h +++ /dev/null @@ -1,129 +0,0 @@ -/** - * - * \file - * - * \brief Common Standard I/O Serial Management. - * - * This file defines a useful set of functions for the Stdio Serial interface on AVR - * and SAM devices. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - ******************************************************************************/ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef _STDIO_SERIAL_H_ -#define _STDIO_SERIAL_H_ - -/** - * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio) - * \ingroup group_common_utils_stdio - * - * Common standard serial I/O management driver that - * implements a stdio serial interface on AVR and SAM devices. - * - * \{ - */ - -#include -#include "compiler.h" -#ifndef SAMD20 -# include "sysclk.h" -#endif -#include "serial.h" - -#if (XMEGA || MEGA_RF) && defined(__GNUC__) - extern int _write (char c, int *f); - extern int _read (int *f); -#endif - - -//! Pointer to the base of the USART module instance to use for stdio. -extern volatile void *volatile stdio_base; -//! Pointer to the external low level write function. -extern int (*ptr_put)(void volatile*, char); - -//! Pointer to the external low level read function. -extern void (*ptr_get)(void volatile*, char*); - -/*! \brief Initializes the stdio in Serial Mode. - * - * \param usart Base address of the USART instance. - * \param opt Options needed to set up RS232 communication (see \ref usart_options_t). - * - */ -static inline void stdio_serial_init(volatile void *usart, const usart_serial_options_t *opt) -{ - stdio_base = (void *)usart; - ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar; - ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar; -# if (XMEGA || MEGA_RF) - usart_serial_init((USART_t *)usart,opt); -# elif UC3 - usart_serial_init(usart,(usart_serial_options_t *)opt); -# elif SAM - usart_serial_init((Usart *)usart,(usart_serial_options_t *)opt); -# else -# error Unsupported chip type -# endif - -# if defined(__GNUC__) -# if (XMEGA || MEGA_RF) - // For AVR GCC libc print redirection uses fdevopen. - fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read)); -# endif -# if UC3 || SAM - // For AVR32 and SAM GCC - // Specify that stdout and stdin should not be buffered. - setbuf(stdout, NULL); - setbuf(stdin, NULL); - // Note: Already the case in IAR's Normal DLIB default configuration - // and AVR GCC library: - // - printf() emits one character at a time. - // - getchar() requests only 1 byte to exit. -# endif -# endif -} - -/** - * \} - */ - -#endif // _STDIO_SERIAL_H_ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_avr/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_avr/doxyfile.doxygen deleted file mode 100644 index c811550f1c5fb..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_avr/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC Standard I/O (stdio) - AVR implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. 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This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. 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This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_usb.c ../../stdio_usb.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_avr/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_avr/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_avr/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam/doxyfile.doxygen deleted file mode 100644 index 7c16e2e69d434..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC Standard I/O (stdio) - SAM implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_usb.c ../../stdio_usb.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam0/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam0/doxyfile.doxygen deleted file mode 100644 index 74ddc92701dbd..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam0/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC Standard I/O (stdio) - SAM0 implementation" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_usb.c ../../stdio_usb.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam0/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam0/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.common_sam0/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_disable/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_disable/doxyfile.doxygen deleted file mode 100644 index 3011569de01cd..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_disable/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC Standard I/O (stdio) disabled" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_disable/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_disable/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_disable/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_enable/doxyfile.doxygen b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_enable/doxyfile.doxygen deleted file mode 100644 index 0877f060a47d0..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_enable/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "USB Device CDC Standard I/O (stdio) (Composite Device)" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_enable/doxygen_module_mainpage.h b/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_enable/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/doxygen/common.utils.stdio.stdio_usb.composite_enable/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/stdio_usb.c b/atmel-samd/asf/common/utils/stdio/stdio_usb/stdio_usb.c deleted file mode 100644 index 7eaa962f07fd6..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/stdio_usb.c +++ /dev/null @@ -1,121 +0,0 @@ -/** - * \file - * - * \brief USB CDC Standard I/O Serial Management. - * - * This module defines support routines for a stdio serial interface to the - * Atmel Software Framework (ASF) common USB CDC service. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - - -#include "stdio_usb.h" - -static bool stdio_usb_interface_enable = false; - -int stdio_usb_putchar (volatile void * unused, char data) -{ - /* A negative return value should be used to indicate that data - * was not written, but this doesn't seem to work with GCC libc. - */ - if (!stdio_usb_interface_enable) { - return 0; // -1 - } - - return udi_cdc_putc(data) ? 0 : -1; -} - -void stdio_usb_getchar (void volatile * unused, char *data) -{ - /* A negative return value should be used to indicate that data - * was not read, but this doesn't seem to work with GCC libc. - */ - if (!stdio_usb_interface_enable) { - *data = 0; // -1 - return; - } - - *data = (char)udi_cdc_getc(); -} - -bool stdio_usb_enable(void) -{ - stdio_usb_interface_enable = true; - return true; -} - -void stdio_usb_disable(void) -{ - stdio_usb_interface_enable = false; -} - -void stdio_usb_init(void) -{ - stdio_base = NULL; - ptr_put = stdio_usb_putchar; - ptr_get = stdio_usb_getchar; - - /* - * Start and attach USB CDC device interface for devices with - * integrated USB interfaces. Assume the VBUS is present if - * VBUS monitoring is not available. - */ - udc_start (); - -#if defined(__GNUC__) -# if XMEGA - // For AVR GCC libc print redirection uses fdevopen. - fdevopen((int (*)(char, FILE*))(_write),(int (*)(FILE*))(_read)); -# endif -# if UC3 || SAM - // For AVR32 and SAM GCC - // Specify that stdout and stdin should not be buffered. - setbuf(stdout, NULL); - setbuf(stdin, NULL); - // Note: Already the case in IAR's Normal DLIB default configuration - // and AVR GCC library: - // - printf() emits one character at a time. - // - getchar() requests only 1 byte to exit. -# endif -#endif -} - diff --git a/atmel-samd/asf/common/utils/stdio/stdio_usb/stdio_usb.h b/atmel-samd/asf/common/utils/stdio/stdio_usb/stdio_usb.h deleted file mode 100644 index 4d0084f167823..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/stdio_usb/stdio_usb.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief USB Standard I/O Serial Management. - * - * This file defines a useful set of functions for the Stdio Serial - * interface on AVR devices. - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _stdio_usb_h_ -#define _stdio_usb_h_ - -/** - * \defgroup group_common_utils_stdio_stdio_usb USB/CDC Standard I/O (stdio) - * \ingroup group_common_utils_stdio - * - * Standard I/O (stdio) management component that implements a stdio - * USB CDC interface on AVR devices. - * - * \{ - */ - -#include - -#include - -#include -#include - -extern int _write (char c, int *f); -extern int _read (int *f); - - -//! Pointer to the base of the USART module instance to use for stdio. -extern volatile void *volatile stdio_base; -//! Pointer to the external low level write function. -extern int (*ptr_put)(void volatile*, char); -//! Pointer to the external low level read function. -extern void (*ptr_get)(void volatile*, char*); - -/*! \brief Sends a character with the USART. - * - * \param usart Base address of the USART instance. - * \param data Character to write. - * - * \return Status. - * \retval 0 The character was written. - * \retval -1 The function timed out before the transmitter became ready. - */ -int stdio_usb_putchar (volatile void * usart, char data); - -/*! \brief Waits until a character is received, and returns it. - * - * \param usart Base address of the USART instance. - * \param data Data to read - * - * \return Nothing. - */ -void stdio_usb_getchar (void volatile * usart, char * data); - -/*! \brief Enables the stdio in USB Serial Mode. - * - * \return \c 1 if function was successfully done, otherwise \c 0. - */ -bool stdio_usb_enable(void); - -/*! \brief Disables the stdio in USB Serial Mode. - * - * \return Nothing. - */ -void stdio_usb_disable(void); - -/*! \brief Initializes the stdio in USB Serial Mode. - * - * \return Nothing. - */ -void stdio_usb_init(void); - -/** - * \} - */ - -#endif // _stdio_usb_h_ diff --git a/atmel-samd/asf/common/utils/stdio/write.c b/atmel-samd/asf/common/utils/stdio/write.c deleted file mode 100644 index 1e8f45943774d..0000000000000 --- a/atmel-samd/asf/common/utils/stdio/write.c +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief System-specific implementation of the \ref _write function used by - * the standard library. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "compiler.h" - -/** - * \addtogroup group_common_utils_stdio - * - * \{ - */ - -volatile void *volatile stdio_base; -int (*ptr_put)(void volatile*, char); - - -#if ( defined(__ICCAVR32__) || defined(__ICCAVR__) || defined(__ICCARM__)) - -#include - -_STD_BEGIN - -#pragma module_name = "?__write" - -/*! \brief Writes a number of bytes, at most \a size, from the memory area - * pointed to by \a buffer. - * - * If \a buffer is zero then \ref __write performs flushing of internal buffers, - * if any. In this case, \a handle can be \c -1 to indicate that all handles - * should be flushed. - * - * \param handle File handle to write to. - * \param buffer Pointer to buffer to read bytes to write from. - * \param size Number of bytes to write. - * - * \return The number of bytes written, or \c _LLIO_ERROR on failure. - */ -size_t __write(int handle, const unsigned char *buffer, size_t size) -{ - size_t nChars = 0; - - if (buffer == 0) { - // This means that we should flush internal buffers. - return 0; - } - - // This implementation only writes to stdout and stderr. - // For all other file handles, it returns failure. - if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { - return _LLIO_ERROR; - } - - for (; size != 0; --size) { - if (ptr_put(stdio_base, *buffer++) < 0) { - return _LLIO_ERROR; - } - ++nChars; - } - return nChars; -} - -_STD_END - - -#elif (defined(__GNUC__) && !XMEGA && !MEGA) - -int __attribute__((weak)) -_write (int file, const char *ptr, int len); - -int __attribute__((weak)) -_write (int file, const char *ptr, int len) -{ - int nChars = 0; - - if ((file != 1) && (file != 2) && (file!=3)) { - return -1; - } - - for (; len != 0; --len) { - if (ptr_put(stdio_base, *ptr++) < 0) { - return -1; - } - ++nChars; - } - return nChars; -} - -#elif (defined(__GNUC__) && (XMEGA || MEGA)) - -int _write (char c, int *f); - -int _write (char c, int *f) -{ - if (ptr_put(stdio_base, c) < 0) { - return -1; - } - return 1; -} -#endif - -/** - * \} - */ - diff --git a/atmel-samd/asf/common/utils/unit_test/suite.c b/atmel-samd/asf/common/utils/unit_test/suite.c deleted file mode 100644 index 12fe542ce2d88..0000000000000 --- a/atmel-samd/asf/common/utils/unit_test/suite.c +++ /dev/null @@ -1,263 +0,0 @@ -/** - * \file - * - * \brief Test suite core functionality - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include -#include -#include "suite.h" - -/** - * \weakgroup test_suite_group - * @{ - */ - -/** - * \internal - * \brief Data pointer for test cases - * - * \see test_set_data(), test_get_data() - */ -void *test_priv_data; - -/** - * \internal - * \brief Context saved before executing a test or fixture function. - * - * This is used for doing non-local jumps from the test cases on failure. - */ -static jmp_buf test_failure_jmpbuf; - -/** - * \internal - * \brief Pointer to current test case - * - * \see test_set_case(), test_get_case() - */ -struct test_case *test_case_ptr = NULL; - -/** - * \internal - * \brief Report a failing test stage - * - * \param test Current test case. - * \param stage Name of test stage that failed. - * \param result Result value of test stage. - */ -static void test_report_failure(const struct test_case *test, const char *stage, - int result) -{ - dbg_error("Test '%s' failed during '%s': %d\r\n", test->name, stage, - result); -} - -/** - * \internal - * \brief Call a test or fixture function - * - * This function will initialize \ref test_failure_jmpbuf and call \a func - * with \a test as the parameter. - * - * \param func Pointer to function to call. - * \param test_case Pointer to the function's originating test case. - * - * \return #TEST_PASS if \a func was executed successfully, or the - * result value passed to test_fail() on failure. - */ -static int test_call(void (*func)(const struct test_case *), - const struct test_case *test) -{ - int ret = 0; - - if (!func) { - return TEST_PASS; - } - - /* - * The first call to setjmp() always return 0. However, if the - * call to func() below goes wrong, we'll return here again with - * a nonzero value. - */ - ret = setjmp(test_failure_jmpbuf); - if (ret) { - return ret; - } - - func(test); - - return TEST_PASS; -} - -/** - * \internal - * \brief Run a test case - * - * This function will call the \e setup, \e run and \e cleanup functions of the - * specified test case, outputting debug information as it goes, then returning - * the result value of the test case. - * - * If the setup stage does not pass, the rest of the test case if skipped. - * If the test stage itself does not pass, the cleanup is still executed. - * - * The result from the first non-passing function in the test case is returned, - * meaning a failing cleanup will override a successful test. - * - * \param test_case Test case to run. - * - * \return \ref TEST_PASS if all functions execute successfully. Otherwise, the - * first non-zero value which is returned from the test case. - */ -static int test_case_run(const struct test_case *test) -{ - int result; - -// Store test pointer for access by test_get_data() -#if defined(_ASSERT_ENABLE_) && defined(TEST_SUITE_DEFINE_ASSERT_MACRO) - test_set_case(test); -#endif - - dbg_info("Running test: %s\r\n", test->name); - if (test->setup) { - int ret; - dbg("Setting up fixture\r\n"); - ret = test_call(test->setup, test); - if (ret) { - test_report_failure(test, "setup", ret); - return ret; - } - } - - result = test_call(test->run, test); - if (result) { - test_report_failure(test, "test", result); - } - - if (test->cleanup) { - int ret; - dbg("Cleaning up fixture\r\n"); - ret = test_call(test->cleanup, test); - if (ret && !result) { - test_report_failure(test, "cleanup", ret); - result = ret; - } - } - -// Test is done, clear the stored test pointer -#if defined(_ASSERT_ENABLE_) && defined(TEST_SUITE_DEFINE_ASSERT_MACRO) - test_set_case(NULL); -#endif - - return result; -} - -/** - * \internal - * \brief Report a failure and jump out of current test case function - * - * \param test Current test case. - * \param result Result value of failure. \note Should not be \ref TEST_PASS. - * \param file Name of file in which function resides. - * \param line Line number at which failure occurred. - * \param fmt Failure message, as printf-formatted string. - * \param ... Values to insert into failure message. - */ -void test_case_fail(const struct test_case *test, int result, - const char *file, unsigned int line, - const char *fmt, ...) -{ - va_list ap; - - dbg_error("Test '%s' failed at %s:%u:\r\n\t", test->name, file, line); - - va_start(ap, fmt); - dbg_vprintf_pgm(fmt, ap); - va_end(ap); - dbg_putchar('\r'); - dbg_putchar('\n'); - - /* - * This will cause the setjmp() call in test_call() to return - * TEST_FAIL. - */ - longjmp(test_failure_jmpbuf, result); -} - -/** - * \brief Run a test suite - * - * Run all tests in \a suite, in the order in which they are found in - * the array. - * - * \return The number of tests that didn't pass. - */ -int test_suite_run(const struct test_suite *suite) -{ - unsigned int nr_failures = 0; - unsigned int nr_errors = 0; - unsigned int i; - int ret; - - dbg_info("Running test suite '%s'...\r\n", suite->name); - - for (i = 0; i < suite->nr_tests; i++) { - const struct test_case *test; - - test = suite->tests[i]; - ret = test_case_run(test); - if (ret < TEST_PASS) { - nr_errors++; - } else if (ret > TEST_PASS) { - nr_failures++; - } - } - - dbg_info("Test suite '%s' complete: %u tests, %u failures, %u errors\r\n\r\n", - suite->name, suite->nr_tests, nr_failures, nr_errors); - - return nr_errors + nr_failures; -} - -//! @} diff --git a/atmel-samd/asf/common/utils/unit_test/suite.h b/atmel-samd/asf/common/utils/unit_test/suite.h deleted file mode 100644 index a4664fbcf5d57..0000000000000 --- a/atmel-samd/asf/common/utils/unit_test/suite.h +++ /dev/null @@ -1,456 +0,0 @@ -/** - * \file - * - * \brief Test suite core declarations - * - * Copyright (c) 2011-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef TEST_SUITE_H_INCLUDED -#define TEST_SUITE_H_INCLUDED - -#include -#include -#include - -#if XMEGA -# include -#endif - -/** - * \defgroup test_suite_group Test Suite Framework - * - * This module is the test suite framework, which provides a set of standard - * functions and macros for defining and running test suites. - * - * A test \e suite consists of test \e cases. Each test case consists of a set - * of functions that are called in a specific order by the framework when the - * test suite is run. The runtime environment of a test is referred to as the - * test \e fixture. A setup function can be defined for the purpose of - * fulfilling preconditions that are needed for the test to run. To free up or - * reset resources which were used in the test case, a cleanup function can be - * defined. - * - * The following three functions can be defined for each test case: - * - fixture \e setup - * - test \e run - * - fixture \e cleanup - * - * The setup and/or cleanup functions may be skipped if they are not needed. - * - * A function may report an error or failure by use of the macros \ref test_fail - * , \ref test_assert_true and \ref test_assert_false. Note that only the first - * macro allows for the result value to be specified, while the two latter will - * automatically return TEST_FAIL if the specified condition is false. - * - * If any of the functions return a failure/error result, execution of that - * specific function is ended. However, depending on which function did not - * pass, execution of the test case may continue: - * - if the setup does not pass, the rest of the test case is skipped - * - if the test itself does not pass, cleanup will still be executed - * - * The result of the first function in the test case which does not pass - * determines the end result. - * - * Example code for definition of a test suite: - * \code - void setup_1(const struct test_case *test); - void run_1(const struct test_case *test); - void cleanup_1(const struct test_case *test); - - void run_2(const struct test_case *test); - - ... - DEFINE_TEST_CASE(test_1, - setup_1, - run_1, - cleanup_1, - "First test"); - DEFINE_TEST_CASE(test_2, - NULL, - run_2, - NULL, - "Second test"); - - DEFINE_TEST_ARRAY(my_tests) = { - &test_1, - &test_2, - }; - - DEFINE_TEST_SUITE(my_suite, my_tests, "Two-test suite"); - - test_suite_run(&my_suite); - ... -\endcode - * - * Example code for definition of a test case: - * \code - void setup_1(const struct test_case *test) - { - void *resource = allocate_test_resource(); - - if (resource == NULL) { - test_fail(test, TEST_ERROR, - "Could not allocate test resource"); - } - test_set_data(resource); - } - - void run_1(const struct test_case *test) - { - void *resource = test_get_data(); - int8_t test_result; - - ... - // TEST CODE - ... - test_assert_true(test, test_result > 0, - "Test result is not larger than 0: %i", test_result); - test_assert_false(test, test_result > 2, - "Test result is larger than 2: %i", test_result); - } - - void cleanup_1(const struct test_case *test) - { - void *resource = test_get_data(); - - free_test_resource(resource); - } -\endcode - * - * @{ - */ - -/** - * \brief A test case - * - * This structure represents a test case which tests one specific - * feature or behavior. - */ -struct test_case { - /** - * \brief Set up the environment in which \a test is to be run - * - * This may involve allocating memory, initializing hardware, - * etc. If something goes wrong, this function may call - * test_fail(), normally with a negative status code. - */ - void (*setup)(const struct test_case *test); - //! Run the test - void (*run)(const struct test_case *test); - /** - * \brief Clean up the environment after \a test has been run - * - * This may free up any memory allocated by setup(), gracefully - * shutting down hardware, etc. If something goes wrong, this - * function may call test_fail(), normally with a negative - * status code. - */ - void (*cleanup)(const struct test_case *test); - //! The name of the test case - const char *name; -}; - -/** - * \brief A test suite - * - * A test suite may contain one or more test cases which are to be run - * in sequence. - */ -struct test_suite { - //! The number of tests in this suite - unsigned int nr_tests; - //! Array of pointers to the test cases - const struct test_case *const *tests; - //! The name of the test suite - const char *name; -}; - -/** - * \name Wrappers for printing debug information - * - * \note The test suite framework feeds its output to printf. It is left up to - * the test application to set up the stream. - */ -//@{ -#if XMEGA && !defined(__ICCAVR__) -# define dbg(__fmt_) \ - printf_P(PROGMEM_STRING(__fmt_)) -# define dbg_info(__fmt_, ...) \ - printf_P(PROGMEM_STRING(__fmt_), __VA_ARGS__) -# define dbg_error(_x, ...) \ - printf_P(PROGMEM_STRING(_x), __VA_ARGS__) -# define dbg_putchar(c) \ - putc(c, stdout) -# define dbg_vprintf_pgm(...) \ - vfprintf_P(stdout, __VA_ARGS__) -#else -# define dbg(__fmt_) \ - printf(__fmt_) -# define dbg_info(__fmt_, ...) \ - printf(__fmt_, __VA_ARGS__) -# define dbg_error(_x, ...) \ - printf(_x, __VA_ARGS__) -# define dbg_putchar(c) \ - putc(c, stdout) -# define dbg_vprintf_pgm(...) \ - vfprintf(stdout, __VA_ARGS__) -#endif -//@} - -//! \name Test suite definition macros -//@{ -/** - * \brief Create a test case struct. - * - * \param _sym Variable name of the resulting struct - * \param _setup Function which sets up a test case environment. Can be NULL. - * \param _run Test function - * \param _cleanup Function which cleans up what was set up. Can be NULL. - * \param _name String describing the test case. - */ -#define DEFINE_TEST_CASE(_sym, _setup, _run, _cleanup, _name) \ - static const char _test_str_##_sym[] = _name; \ - static const struct test_case _sym = { \ - .setup = _setup, \ - .run = _run, \ - .cleanup = _cleanup, \ - .name = _test_str_##_sym, \ - } - -/** - * \brief Create an array of test case pointers. - * - * \param _sym Variable name of the resulting array - */ -#define DEFINE_TEST_ARRAY(_sym) \ - const struct test_case *const _sym[] - -/** - * \brief Create a test suite. - * - * \param _sym Variable name of the resulting struct - * \param _test_array Array of test cases, created with DEFINE_TEST_ARRAY() - * \param _name String describing the test suite. - */ -#define DEFINE_TEST_SUITE(_sym, _test_array, _name) \ - static const char _test_str_##_sym[] = _name; \ - const struct test_suite _sym = { \ - .nr_tests = ARRAY_LEN(_test_array), \ - .tests = _test_array, \ - .name = _test_str_##_sym, \ - } -//@} - -#ifndef ARRAY_LEN -/** - * \internal - * \brief Convenience macro for counting elements in arrays - */ -# define ARRAY_LEN(a) (sizeof(a) / sizeof((a)[0])) -#endif - -//! \name Test data access -//@{ -extern void *test_priv_data; - -/** - * \brief Set private data pointer for the current test. - * - * \param data Pointer to arbitrary run-time data for the test currently - * being run. - */ -static inline void test_set_data(void *data) -{ - test_priv_data = data; -} - -/** - * \brief Get the private data pointer for the current test. - * - * \return Pointer to arbitrary run-time data for the test currently - * being run, previously registered using test_set_data(). - */ -static inline void *test_get_data(void) -{ - return test_priv_data; -} -//@} - -//! \name Test case pointer access -//@{ - -/** - * \brief Pointer to current test case - */ -extern struct test_case *test_case_ptr; - -/** - * \internal - * \brief Set pointer to current test. - */ -static inline void test_set_case(const struct test_case *test) -{ - test_case_ptr = (struct test_case *)test; -} - -/** - * \internal - * \brief Get pointer to current test. - */ -static inline struct test_case *test_get_case(void) -{ - return test_case_ptr; -} -//@} - -//@{ -//! \name Test result reporting -//@{ -/** - * \brief Status codes returned by test cases and fixtures - * - * Note that test cases and especially fixtures may return any of the - * status codes defined by \ref status_code as well. - */ -enum test_status { - TEST_ERROR = -1, //!< Test error - TEST_PASS = 0, //!< Test success - TEST_FAIL = 1, //!< Test failure -}; - -/** - * \def test_fail(test, result, ...) - * \brief Fail the test - * - * Calling this function will cause the test to terminate with a - * failure. It will return directly to the test suite core, not to the - * caller. - * - * \param test Test case which failed - * \param result The result of the test (may not be 0) - * \param ... printf()-style format string and arguments - */ -#if XMEGA && !defined(__ICCAVR__) -# define test_priv_fail_ps(test, result, format, ...) \ - do { \ - static PROGMEM_DECLARE(char, _fmtstr[]) = format "%s"; \ - test_case_fail(test, result, __FILE__, __LINE__, _fmtstr, \ - __VA_ARGS__); \ - } while (0) - -# define test_fail(test, result, ...) \ - test_priv_fail_ps(test, result, __VA_ARGS__, "") -#else -# define test_fail(test, result, ...) \ - test_case_fail(test, result, __FILE__, __LINE__, __VA_ARGS__) -#endif - -/** - * \brief Verify that \a condition is true - * - * If \a condition is false, fail the test with an error message - * indicating the condition which failed. - * - * \param test The test case currently being run - * \param condition Expression to be validated - * \param ... Format string and arguments - */ -#define test_assert_true(test, condition, ...) \ - do { \ - if (!(condition)) { \ - test_fail(test, TEST_FAIL, __VA_ARGS__); \ - } \ - } while (0) - -/** - * \brief Verify that \a condition is false - * - * If \a condition is true, fail the test with an error message - * indicating the condition which failed. - * - * \param test The test case currently being run - * \param condition Expression to be validated - * \param ... Format string and arguments - */ -#define test_assert_false(test, condition, ...) \ - test_assert_true(test, !(condition), __VA_ARGS__) -//@} - -//! \name Test suite interaction -//@{ -extern int test_suite_run(const struct test_suite *suite); -//@} - -#if defined(__GNUC__) -/* GCC should perform additional printf() argument sanity checks on the - * function call site to try to ensure arguments are printf() compatible */ -__attribute__((format(__printf__, 5, 6))) -#endif -extern void test_case_fail(const struct test_case *test, int result, - const char *file, unsigned int line, - const char *fmt, ...); - -//! @} - -/** - * \brief Assert() macro definition for unit testing - * - * The Assert() macro is set up to use test_assert_true(), - * as this will only halt execution of the current test, allowing - * the remaining tests a chance to complete. - */ -#if defined(_ASSERT_ENABLE_) && defined(TEST_SUITE_DEFINE_ASSERT_MACRO) -# define Assert(expr) \ - { \ - if (test_get_case() != NULL) { \ - test_assert_true(test_get_case(), expr, \ - "Assertion failed: %s", #expr); \ - } else { \ - if (!(expr)) { \ - dbg_error("Assertion '%s' failed at %s:%d\r\n", \ - #expr, __FILE__, __LINE__); \ - while (true); \ - } \ - } \ - } -#endif - -#endif /* TEST_SUITE_H_INCLUDED */ diff --git a/atmel-samd/asf/common2/services/delay/delay.h b/atmel-samd/asf/common2/services/delay/delay.h deleted file mode 100644 index 9326e2b3a14bc..0000000000000 --- a/atmel-samd/asf/common2/services/delay/delay.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - * \file - * - * \brief Common Delay Service - * - * Copyright (c) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DELAY_H_INCLUDED -#define DELAY_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup group_common_services_delay Busy-Wait Delay Routines - * - * This module provides simple loop-based delay routines for those - * applications requiring a brief wait during execution. Common for - * API ver. 2. - * - * @{ - */ - -#ifdef SYSTICK_MODE -#include "sam0/systick_counter.h" -#endif -#ifdef CYCLE_MODE -#include "sam0/cycle_counter.h" -#endif - -void delay_init(void); - -/** - * \def delay_s - * \brief Delay in at least specified number of seconds. - * \param delay Delay in seconds - */ -#define delay_s(delay) ((delay) ? cpu_delay_s(delay) : cpu_delay_us(1)) - -/** - * \def delay_ms - * \brief Delay in at least specified number of milliseconds. - * \param delay Delay in milliseconds - */ -#define delay_ms(delay) ((delay) ? cpu_delay_ms(delay) : cpu_delay_us(1)) - -/** - * \def delay_us - * \brief Delay in at least specified number of microseconds. - * \param delay Delay in microseconds - */ -#define delay_us(delay) ((delay) ? cpu_delay_us(delay) : cpu_delay_us(1)) - -#ifdef __cplusplus -} -#endif - -/** - * @} - */ - -#endif /* DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_cycle/doxyfile.doxygen b/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_cycle/doxyfile.doxygen deleted file mode 100644 index b5a096e2730db..0000000000000 --- a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_cycle/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Delay routines" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. 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The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../sam0/cycle_counter.c ../../delay.h ../../sam0/cycle_counter.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. ../../sam0 - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 CYCLE_MODE - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_cycle/doxygen_module_mainpage.h b/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_cycle/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_cycle/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_systick/doxyfile.doxygen b/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_systick/doxyfile.doxygen deleted file mode 100644 index 030f03f29fcef..0000000000000 --- a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_systick/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Delay routines" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../sam0/systick_counter.c ../../delay.h ../../sam0/systick_counter.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. ../../sam0 - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 SYSTICK_MODE - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_systick/doxygen_module_mainpage.h b/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_systick/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/common2/services/delay/doxygen/common2.services.delay_systick/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
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- * - * \section main_licence License - *
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  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/common2/services/delay/sam0/cycle_counter.c b/atmel-samd/asf/common2/services/delay/sam0/cycle_counter.c deleted file mode 100644 index bff6107962d5a..0000000000000 --- a/atmel-samd/asf/common2/services/delay/sam0/cycle_counter.c +++ /dev/null @@ -1,76 +0,0 @@ -/** - * \file - * - * \brief ARM functions for busy-wait delay loops - * - * Copyright (c) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "cycle_counter.h" -#include "delay.h" - -/** - * \brief Initialize the delay driver. - * - * Not used in cycle mode. - */ -void delay_init(void) -{ -} - -// Delay loop is put to SRAM so that FWS will not affect delay time -OPTIMIZE_HIGH -RAMFUNC -void portable_delay_cycles(unsigned long n) -{ - UNUSED(n); - - __asm ( - "loop: DMB \n" -#ifdef __ICCARM__ - "SUBS r0, r0, #1 \n" -#else - "SUB r0, r0, #1 \n" -#endif - "CMP r0, #0 \n" - "BNE loop " - ); -} diff --git a/atmel-samd/asf/common2/services/delay/sam0/cycle_counter.h b/atmel-samd/asf/common2/services/delay/sam0/cycle_counter.h deleted file mode 100644 index 3a52bc574eaaf..0000000000000 --- a/atmel-samd/asf/common2/services/delay/sam0/cycle_counter.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief ARM functions for busy-wait delay loops - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CYCLE_COUNTER_H_INCLUDED -#define CYCLE_COUNTER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @def F_CPU - * @brief MCU Clock Frequency (Hertz) - */ -#ifndef F_CPU -# define F_CPU system_gclk_gen_get_hz(0) -#endif - -/** - * @name Convenience functions for busy-wait delay loops - * - * @def delay_cycles - * @brief Delay program execution for a specified number of CPU cycles. - * @param n number of CPU cycles to wait - * - * @def cpu_delay_ms - * @brief Delay program execution for a specified number of milliseconds. - * @param delay number of milliseconds to wait - * @param f_cpu CPU frequency in Hertz - * - * @def cpu_delay_us - * @brief Delay program execution for a specified number of microseconds. - * @param delay number of microseconds to wait - * @param f_cpu CPU frequency in Hertz - * - * @def cpu_ms_2_cy - * @brief Convert milli-seconds into CPU cycles. - * @param ms number of milliseconds - * @param f_cpu CPU frequency in Hertz - * @return the converted number of CPU cycles - * - * @def cpu_us_2_cy - * @brief Convert micro-seconds into CPU cycles. - * @param ms number of microseconds - * @param f_cpu CPU frequency in Hertz - * @return the converted number of CPU cycles - * - * @{ - */ - -/** - * \brief Delay loop to delay n number of cycles - * - * \note The function runs in internal RAM so that flash wait states - * will not affect the delay time. - * - * \param n Number of cycles - */ -void portable_delay_cycles(unsigned long n); - -#define cpu_ms_2_cy(ms, f_cpu) \ - (((uint64_t)(ms) * (f_cpu) + (uint64_t)(7e3-1ul)) / (uint64_t)7e3) -#define cpu_us_2_cy(us, f_cpu) \ - (((uint64_t)(us) * (f_cpu) + (uint64_t)(7e6-1ul)) / (uint64_t)7e6) - -#define delay_cycles portable_delay_cycles - -#define cpu_delay_s(delay) delay_cycles(cpu_ms_2_cy(1000 * delay, F_CPU)) -#define cpu_delay_ms(delay) delay_cycles(cpu_ms_2_cy(delay, F_CPU)) -#define cpu_delay_us(delay) delay_cycles(cpu_us_2_cy(delay, F_CPU)) -//! @} - - -#ifdef __cplusplus -} -#endif - -#endif /* CYCLE_COUNTER_H_INCLUDED */ diff --git a/atmel-samd/asf/common2/services/delay/sam0/systick_counter.c b/atmel-samd/asf/common2/services/delay/sam0/systick_counter.c deleted file mode 100644 index fcd05c670f953..0000000000000 --- a/atmel-samd/asf/common2/services/delay/sam0/systick_counter.c +++ /dev/null @@ -1,96 +0,0 @@ -/** - * \file - * - * \brief ARM functions for busy-wait delay loops - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "delay.h" - -/** - * Value used to calculate ms delay. Default to be used with a 8MHz clock; - */ -static uint32_t cycles_per_ms = 8000000UL / 1000; -static uint32_t cycles_per_us = 8000000UL / 1000000; - -/** - * \brief Initialize the delay driver. - * - * This must be called during start up to initialize the delay routine with - * the current used main clock. It must run any time the main CPU clock is changed. - */ -void delay_init(void) -{ - cycles_per_ms = system_gclk_gen_get_hz(0); - cycles_per_ms /= 1000; - cycles_per_us = cycles_per_ms / 1000; - - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; -} - -/** - * \brief Delay loop to delay at least n number of microseconds - * - * \param n Number of microseconds to wait - */ -void delay_cycles_us( - uint32_t n) -{ - while (n--) { - /* Divide up to blocks of 10u */ - delay_cycles(cycles_per_us); - } -} - -/** - * \brief Delay loop to delay at least n number of milliseconds - * - * \param n Number of milliseconds to wait - */ -void delay_cycles_ms( - uint32_t n) -{ - while (n--) { - /* Divide up to blocks of 1ms */ - delay_cycles(cycles_per_ms); - } -} diff --git a/atmel-samd/asf/common2/services/delay/sam0/systick_counter.h b/atmel-samd/asf/common2/services/delay/sam0/systick_counter.h deleted file mode 100644 index 06885e63c693d..0000000000000 --- a/atmel-samd/asf/common2/services/delay/sam0/systick_counter.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * \file - * - * \brief ARM functions for busy-wait delay loops - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CYCLE_COUNTER_H_INCLUDED -#define CYCLE_COUNTER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Convenience functions for busy-wait delay loops - * - * @{ - */ - -/** - * \brief Delay loop to delay n number of cycles - * Delay program execution for at least the specified number of CPU cycles. - * - * \param n Number of cycles to delay - */ -static inline void delay_cycles( - const uint32_t n) -{ - if (n > 0) { - SysTick->LOAD = n; - SysTick->VAL = 0; - - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) { - }; - } -} - -void delay_cycles_us(uint32_t n); - -void delay_cycles_ms(uint32_t n); - -/** - * \brief Delay program execution for at least the specified number of microseconds. - * - * \param delay number of microseconds to wait - */ -#define cpu_delay_us(delay) delay_cycles_us(delay) - -/** - * \brief Delay program execution for at least the specified number of milliseconds. - * - * \param delay number of milliseconds to wait - */ -#define cpu_delay_ms(delay) delay_cycles_ms(delay) - -/** - * \brief Delay program execution for at least the specified number of seconds. - * - * \param delay number of seconds to wait - */ -#define cpu_delay_s(delay) delay_cycles_ms(1000 * delay) - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* CYCLE_COUNTER_H_INCLUDED */ diff --git a/atmel-samd/asf/readme.txt b/atmel-samd/asf/readme.txt deleted file mode 100644 index 24a71b0a841a9..0000000000000 --- a/atmel-samd/asf/readme.txt +++ /dev/null @@ -1,125 +0,0 @@ -1 - Introduction ----------------- - -The Atmel® Software Framework (ASF) is a collection of embedded software for Atmel flash MCU (www.atmel.com/asf). -» It simplifies the usage of microcontrollers, providing an abstraction to the hardware and high-value middlewares -» ASF is designed to be used for evaluation, prototyping, design and production phases -» ASF is integrated in the Atmel Studio IDE with a graphical user interface or available as standalone for GCC, IAR compilers -» ASF can be downloaded for free - -ASF online documentation can be found here: http://asf.atmel.com - -Supported devices: -» AVR UC3(Trade Mark) (http://www.atmel.com/products/microcontrollers/avr/32-bitavruc3.aspx) -» AVR XMEGA(Trade Mark) (http://www.atmel.com/products/microcontrollers/avr/avr_xmega.aspx) -» megaAVR(Trade Mark) (http://www.atmel.com/products/microcontrollers/avr/megaavr.aspx) -» SAM (http://www.atmel.com/products/microcontrollers/arm/default.aspx) - -Each software module is provided with full source code, example of usage and -ready-to-use projects for the IAR EW and GNU GCC compilers. - -This package is dedicated for IAR and GCC makefile users. AVR Studio 5 or Atmel Studio 6 users do not -need this package as the ASF is integrated in Atmel Studio. - -The top folder organization is as follow: -- the avr32/ folder contains software modules(source code and projects) dedicated to AVR UC3 devices, -- the mega/ folder contains software modules(source code and projects) dedicated to megaAVR devices, -- the xmega/ folder contains software modules(source code and projects) dedicated to AVR XMEGA devices, -- the sam/ folder contains software modules(source code and projects) dedicated to SAM devices, -- the common/ folder contains software modules(source code and projects) shared by all AVR and SAM devices, -- the thirdparty/ folder contains software modules(source code and projects) from thirdparty providers for all Atmel devices. - -The thirdparty/ folder is organized by thirdparty software module (i.e. one folder per thirdparty software module). - -The avr32/, xmega/, mega/, sam/ and common/ folders are organized as follow: -- the drivers/ folder contains low-level software drivers for MCU on-chip resources (eg cpu, usart, adc drivers). -- the boards/ folder contains board-specific source code files. -- the utils/ folder contains files that are used by all other modules: it holds -several linker script files, IAR & GCC pre-compiled libraries of some ASF modules, -and C/C++ utility files with general usage defines, macros and functions. -- the services/ folder contains application-oriented pieces of software that are -not specific to boards nor chips (eg. FAT, TCP/IP stack, os, JPEG decoder). -For the common/ top folder, the services/ folder also contains chip-specific code. -- the components/ folder offers, for each supported hardware component, a software -interface to interact with the component (eg memories like SDRAM, SD card, or display) -- the applications/ contains hefty examples of applications using services and drivers. - - -2 - Documentation --------------------------- - -ASF release notes, reference manual and getting started documents can be found on http://www.atmel.com/asf. - -The ASF documentation can be found online on http://asf.atmel.com. - - -3 - Toolchain Header Files Update ---------------------------------- - -For 8-bit AVR users it is recommended to update the toolchain header files, a -description about how to do that is located in the readme.txt file under the -xmega/utils/header_files/ directory. - -For AVR UC3 users using IAR, it is recommended to update the IAR header files. -To do that, unzip the avr32-headers.zip file (located under -the avr32/utils/header_files/ directory) to the IAR EWAVR32 installation folder -under "IAR installation folder"/Embedded Workbench x.y/avr32/inc/. - - -4 - IAR EW Users ----------------- - -Using an example of usage of the AVR UC3 GPIO driver module as an example, the -IAR projects are located under: -- avr32/drivers/gpio/peripheral_bus_example/at32uc3a0512_evk1000/iar/ for an EVK1100 board, -- avr32/drivers/gpio/peripheral_bus_example/at32uc3a0512_evk1105/iar/ for an EVK1105 board, -- avr32/drivers/gpio/peripheral_bus_example/at32uc3b0256_evk1101/iar/ for an EVK1101 board, -- avr32/drivers/gpio/peripheral_bus_example/at32uc3a3256_evk1104/iar/ for an EVK1104 board, -- avr32/drivers/gpio/peripheral_bus_example/at32uc3l064_stk600-rcuc3l0/iar/ for an STK600-RCUC3L0 setup, -- avr32/drivers/gpio/peripheral_bus_example/at32uc3c0512c_uc3c_ek/iar/ for an AT32UC3C-EK board, -- avr32/drivers/gpio/peripheral_bus_example/at32uc3l064_uc3l_ek/iar/ for an AT32UC3L-EK board. - -Each iar folder contains a full IAR project with: -- an IAR EWAVR32 workspace file(avr32_drivers_gpio_peripheral_bus_example_uc3l_ek.eww: double-click on this file to open the whole project), -- an IAR EWAVR32 project file(avr32_drivers_gpio_peripheral_bus_example_uc3l_ek.ewp), -- an IAR EWAVR32 debug configuration file(avr32_drivers_gpio_peripheral_bus_example_uc3l_ek.ewd). - - -5 - AVR32 Studio Users ----------------------- - -It is possible to work with an unzipped ASF package from within AVR32 Studio: this -is described in the application note "AVR32769: How to Compile the standalone AVR -UC3 Software Framework in AVR32 Studio V2": http://www.atmel.com/dyn/resources/prod_documents/doc32115.pdf - - -6 - Offline documentation - Generating The HTML Documentation -------------------------------------- - -All modules are fully documented using doxygen tags. Each project within the ASF -contains a doxyfile.doxygen (used to configure doxygen for a proper documentation -generation): to generate the html documentation, doxygen must be installed (see -http://www.doxygen.org/download.html) and the doxyfile.doxygen must be used as -the input configuration file for doxygen. - -Using an example of usage of the AVR UC3 GPIO driver module as an example, for -an AT32UC3C-EK board, the associated doxyfile.doxygen file is under the -avr32/drivers/gpio/peripheral_bus_example/at32uc3c0512c_uc3c_ek/doxygen/ folder. -Run doxygen and use this doxyfile.doxygen as configuration file for doxygen. -Using the command line, this is done with the following command: doxygen doxyfile.doxygen - - -7 - Contact Information ------------------------ - -For more info about Atmel MCU visit http://www.atmel.com/products/microcontrollers/default.aspx or contact support through the http://support.atmel.no/ site. -The support site also have a Frequently Asked Questions page with the most common questions. - -ASF bugs or enhancement requests can be reported in the ASF Bug Tracker (http://asf.atmel.com/bugzilla/). - - -8 - Community Information -------------------------- - -Users can find an ASF forum (http://www.avrfreaks.net/index.php?name=PNphpBB2&file=viewforum&f=21) on AVRfreaks for AVR users or on http://www.at91.com/ for SAM users. -This forum can be used to have an open discussion about usage, development, bugs, fixes, improvements, etc. \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/adc/adc.h b/atmel-samd/asf/sam0/drivers/adc/adc.h deleted file mode 100644 index a31bff7221f0e..0000000000000 --- a/atmel-samd/asf/sam0/drivers/adc/adc.h +++ /dev/null @@ -1,1155 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef ADC_H_INCLUDED -#define ADC_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_adc_group SAM Analog-to-Digital Converter (ADC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's Analog-to-Digital Converter functionality, for - * the conversion of analog voltages into a corresponding digital form. - * The following driver Application Programming Interface (API) modes are covered by this manual: - * - Polled APIs - * \if ADC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - ADC (Analog-to-Digital Converter) - * - * The following devices can use this module: - * \if DEVICE_SAML21_SUPPORT - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM C20/C21 - * \else - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM DA1 - * \endif - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_adc_prerequisites - * - \ref asfdoc_sam0_adc_module_overview - * - \ref asfdoc_sam0_adc_special_considerations - * - \ref asfdoc_sam0_adc_extra_info - * - \ref asfdoc_sam0_adc_examples - * - \ref asfdoc_sam0_adc_api_overview - * - * - * \section asfdoc_sam0_adc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_adc_module_overview Module Overview - * - * This driver provides an interface for the Analog-to-Digital conversion - * functions on the device, to convert analog voltages to a corresponding - * digital value. The ADC has up to 12-bit resolution, and is capable of - * \if DEVICE_SAML21_SUPPORT - * converting up to 1,000,000 samples per second (MSPS). - * \else - * converting up to 500K samples per second (KSPS). - * \endif - * - * The ADC has a compare function for accurate monitoring of user defined - * thresholds with minimum software intervention required. - * The ADC may be configured for 8-, 10-, or 12-bit result, reducing the - * conversion time. ADC conversion results are provided left or right adjusted - * which eases calculation when the result is represented as a signed integer. - * - * The input selection is flexible, and both single-ended and differential - * measurements can be made. For differential measurements, an optional gain - * stage is available to increase the dynamic range. In addition, several - * internal signal inputs are available. The ADC can provide both signed and - * unsigned results. - * - * The ADC measurements can either be started by application software or an - * incoming event from another peripheral in the device, and both internal and - * external reference voltages can be selected. - * - * \note Internal references will be enabled by the driver, but not disabled. - * Any reference not used by the application should be disabled by the application. - * - * A simplified block diagram of the ADC can be seen in - * \ref asfdoc_sam0_adc_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_adc_module_block_diagram - * \dot - * digraph overview { - * splines = false; - * rankdir=LR; - * - * mux1 [label="Positive input", shape=box]; - * mux2 [label="Negative input", shape=box]; - * - * - * mux3 [label="Reference", shape=box]; - * - * adc [label="ADC", shape=polygon, sides=5, orientation=90, distortion=-0.6, style=filled, fillcolor=darkolivegreen1, height=1, width=1]; - * prescaler [label="PRESCALER", shape=box, style=filled, fillcolor=lightblue]; - * - * mux1 -> adc; - * mux2 -> adc; - * mux3 -> adc:sw; - * prescaler -> adc; - * - * postproc [label="Post processing", shape=box]; - * result [label="RESULT", shape=box, style=filled, fillcolor=lightblue]; - * - * adc:e -> postproc:w; - * postproc:e -> result:w; - * - * {rank=same; mux1 mux2} - * {rank=same; prescaler adc} - * - * } - * \enddot - * - * - * \subsection asfdoc_sam0_adc_module_overview_prescaler Sample Clock Prescaler - * The ADC features a prescaler, which enables conversion at lower clock rates - * than the input Generic Clock to the ADC module. This feature can be used to - * lower the synchronization time of the digital interface to the ADC module - * via a high speed Generic Clock frequency, while still allowing the ADC - * sampling rate to be reduced. - * - * \subsection asfdoc_sam0_adc_module_overview_resolution ADC Resolution - * The ADC supports full 8-, 10-, or 12-bit resolution. Hardware - * oversampling and decimation can be used to increase the - * effective resolution at the expense of throughput. Using oversampling and - * decimation mode the ADC resolution is increased from 12-bit to an effective - * 13-, 14-, 15-, or 16-bit. In these modes the conversion rate is reduced, as - * a greater number of samples is used to achieve the increased resolution. The - * available resolutions and effective conversion rate is listed in - * \ref asfdoc_sam0_adc_module_conversion_rate "the table below". - * - * \anchor asfdoc_sam0_adc_module_conversion_rate - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Effective ADC Conversion Speed Using Oversampling
ResolutionEffective conversion rate
13-bitConversion rate divided by 4
14-bitConversion rate divided by 16
15-bitConversion rate divided by 64
16-bitConversion rate divided by 256
- * - * \subsection asfdoc_sam0_adc_module_overview_conversion Conversion Modes - * ADC conversions can be software triggered on demand by the user application, - * if continuous sampling is not required. It is also possible to configure the - * ADC in free running mode, where new conversions are started as soon as the - * previous conversion is completed, or configure the ADC to scan across a - * number of input pins (see \ref asfdoc_sam0_adc_module_overview_pin_scan). - * - * \subsection asfdoc_sam0_adc_module_overview_diff_mode Differential and Single-ended Conversion - * The ADC has two conversion modes; differential and single-ended. When - * measuring signals where the positive input pin is always at a higher voltage - * than the negative input pin, the single-ended conversion mode should be used - * in order to achieve a full 12-bit output resolution. - * - * If however the positive input pin voltage may drop below the negative input - * pin the signed differential mode should be used. - * - * \subsection asfdoc_sam0_adc_module_overview_sample_time Sample Time - * The sample time for each ADC conversion is configurable as a number of half - * prescaled ADC clock cycles (depending on the prescaler value), allowing the - * user application to achieve faster or slower sampling depending on the - * source impedance of the ADC input channels. For applications with high - * impedance inputs the sample time can be increased to give the ADC an adequate - * time to sample and convert the input channel. - * - * The resulting sampling time is given by the following equation: - * \f[ - * t_{SAMPLE} = (sample\_length+1) \times \frac{ADC_{CLK}} {2} - * \f] - * - * \subsection asfdoc_sam0_adc_module_overview_averaging Averaging - * The ADC can be configured to trade conversion speed for accuracy by averaging - * multiple samples in hardware. This feature is suitable when operating in - * noisy conditions. - * - * You can specify any number of samples to accumulate (up to 1024) and the - * divide ratio to use (up to divide by 128). To modify these settings the - * ADC_RESOLUTION_CUSTOM needs to be set as the resolution. When this is set - * the number of samples to accumulate and the division ratio can be set by - * the configuration struct members \ref adc_config.accumulate_samples and - * \ref adc_config.divide_result. When using this mode the ADC result register - * will be set to be 16-bit wide to accommodate the larger result sizes - * produced by the accumulator. - * - * The effective ADC conversion rate will be reduced by a factor of the number - * of accumulated samples; - * however, the effective resolution will be increased according to - * \ref asfdoc_sam0_adc_module_hw_av_resolution "the table below". - * - * \anchor asfdoc_sam0_adc_module_hw_av_resolution - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Effective ADC Resolution From Various Hardware Averaging Modes
Number of samples
Final result
112-bit
213-bit
414-bit
815-bit
1616-bit
3216-bit
6416-bit
12816-bit
25616-bit
51216-bit
102416-bit
- * - * - * \subsection asfdoc_sam0_adc_module_overview_offset_corr Offset and Gain Correction - * Inherent gain and offset errors affect the absolute accuracy of the ADC. - * - * The offset error is defined as the deviation of the ADC's actual transfer - * function from ideal straight line at zero input voltage. - * - * The gain error is defined as the deviation of the last output step's - * midpoint from the ideal straight line, after compensating for offset error. - * - * The offset correction value is subtracted from the converted data before the - * result is ready. The gain correction value is multiplied with the offset - * corrected value. - * - * The equation for both offset and gain error compensation is shown below: - * \f[ - * ADC_{RESULT} = (VALUE_{CONV} + CORR_{OFFSET}) \times CORR_{GAIN} - * \f] - * - * When enabled, a given set of offset and gain correction values can be applied - * to the sampled data in hardware, giving a corrected stream of sample data to - * the user application at the cost of an increased sample latency. - * - * In single conversion, a latency of 13 ADC Generic Clock cycles is added for - * the final sample result availability. As the correction time is always less - * than the propagation delay, in free running mode this latency appears only - * during the first conversion. After the first conversion is complete, future - * conversion results are available at the defined sampling rate. - * - * \subsection asfdoc_sam0_adc_module_overview_pin_scan Pin Scan - * In pin scan mode, the first ADC conversion will begin from the configured - * positive channel, plus the requested starting offset. When the first - * conversion is completed, the next conversion will start at the next positive - * input channel and so on, until all requested pins to scan have been sampled - * and converted. - * SAM L21/L22 has automatic sequences feature instead of pin scan mode. In automatic - * sequence mode, all of 32 positives inputs can be included in a sequence. The - * sequence starts from the lowest input, and go to the next enabled input - * automatically. - * - * Pin scanning gives a simple mechanism to sample a large number of physical - * input channel samples, using a single physical ADC channel. - * - * \subsection asfdoc_sam0_adc_module_overview_window_monitor Window Monitor - * The ADC module window monitor function can be used to automatically compare - * the conversion result against a preconfigured pair of upper and lower - * threshold values. - * - * The threshold values are evaluated differently, depending on whether - * differential or single-ended mode is selected. In differential mode, the - * upper and lower thresholds are evaluated as signed values for the comparison, - * while in single-ended mode the comparisons are made as a set of unsigned - * values. - * - * The significant bits of the lower window monitor threshold and upper window - * monitor threshold values are user-configurable, and follow the overall ADC - * sampling bit precision set when the ADC is configured by the user application. - * For example, only the eight lower bits of the window threshold values will be - * compared to the sampled data whilst the ADC is configured in 8-bit mode. - * In addition, if using differential mode, the 8th bit will be considered as - * the sign bit even if bit 9 is zero. - * - * \subsection asfdoc_sam0_adc_module_overview_events Events - * Event generation and event actions are configurable in the ADC. - * - * The ADC has two actions that can be triggered upon event reception: - * \li Start conversion - * \li Flush pipeline and start conversion - * - * The ADC can generate two events: - * \li Window monitor - * \li Result ready - * - * If the event actions are enabled in the configuration, any incoming event - * will trigger the action. - * - * If the window monitor event is enabled, an event will be generated - * when the configured window condition is detected. - * - * If the result ready event is enabled, an event will be generated when a - * conversion is completed. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * - * \section asfdoc_sam0_adc_special_considerations Special Considerations - * - * An integrated analog temperature sensor is available for use with the ADC. - * The bandgap voltage, as well as the scaled I/O and core voltages can also be - * measured by the ADC. For internal ADC inputs, the internal source(s) may need - * to be manually enabled by the user application before they can be measured. - * - * - * \section asfdoc_sam0_adc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_adc_extra. This includes: - * - \ref asfdoc_sam0_adc_extra_acronyms - * - \ref asfdoc_sam0_adc_extra_dependencies - * - \ref asfdoc_sam0_adc_extra_errata - * - \ref asfdoc_sam0_adc_extra_history - * - * - * \section asfdoc_sam0_adc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_adc_exqsg. - * - * - * \section asfdoc_sam0_adc_api_overview API Overview - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \name Module Status Flags - * - * ADC status flags, returned by \ref adc_get_status() and cleared by - * \ref adc_clear_status(). - * - * @{ - */ - -/** ADC result ready. */ -#define ADC_STATUS_RESULT_READY (1UL << 0) -/** Window monitor match. */ -#define ADC_STATUS_WINDOW (1UL << 1) -/** ADC result overwritten before read. */ -#define ADC_STATUS_OVERRUN (1UL << 2) - -/** @} */ - -#if ADC_CALLBACK_MODE == true -# if (ADC_INST_NUM > 1) -# define _ADC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_ADC##n, -/** - * \internal Get the interrupt vector for the given device instance - * - * \param[in] The ADC module instance number - * - * \return Interrupt vector for of the given ADC module instance. - */ -static enum system_interrupt_vector _adc_interrupt_get_interrupt_vector( - uint32_t inst_num) -{ - static uint8_t adc_interrupt_vectors[ADC_INST_NUM] = { - MREPEAT(ADC_INST_NUM, _ADC_INTERRUPT_VECT_NUM, 0) - }; - - return (enum system_interrupt_vector)adc_interrupt_vectors[inst_num]; -} -# endif -#endif - -#if !defined(__DOXYGEN__) -uint8_t _adc_get_inst_index( - Adc *const hw); -#endif - -/** - * \name Driver Initialization and Configuration - * @{ - */ -enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config); - -void adc_get_config_defaults( - struct adc_config *const config); - -#if (SAMD) || (SAMR21) -void adc_regular_ain_channel( - uint32_t *pin_array, uint8_t size); -#endif - -/** @} */ - -/** - * \name Status Management - * @{ - */ - -/** - * \brief Retrieves the current module status. - * - * Retrieves the status of the module, giving overall state information. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * - * \return Bitmask of \c ADC_STATUS_* flags. - * - * \retval ADC_STATUS_RESULT_READY ADC result is ready to be read - * \retval ADC_STATUS_WINDOW ADC has detected a value inside the set - * window range - * \retval ADC_STATUS_OVERRUN ADC result has overrun - */ -static inline uint32_t adc_get_status( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - uint32_t int_flags = adc_module->INTFLAG.reg; - - uint32_t status_flags = 0; - - /* Check for ADC Result Ready */ - if (int_flags & ADC_INTFLAG_RESRDY) { - status_flags |= ADC_STATUS_RESULT_READY; - } - - /* Check for ADC Window Match */ - if (int_flags & ADC_INTFLAG_WINMON) { - status_flags |= ADC_STATUS_WINDOW; - } - - /* Check for ADC Overrun */ - if (int_flags & ADC_INTFLAG_OVERRUN) { - status_flags |= ADC_STATUS_OVERRUN; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag. - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] status_flags Bitmask of \c ADC_STATUS_* flags to clear - */ -static inline void adc_clear_status( - struct adc_module *const module_inst, - const uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - uint32_t int_flags = 0; - - /* Check for ADC Result Ready */ - if (status_flags & ADC_STATUS_RESULT_READY) { - int_flags |= ADC_INTFLAG_RESRDY; - } - - /* Check for ADC Window Match */ - if (status_flags & ADC_STATUS_WINDOW) { - int_flags |= ADC_INTFLAG_WINMON; - } - - /* Check for ADC Overrun */ - if (status_flags & ADC_STATUS_OVERRUN) { - int_flags |= ADC_INTFLAG_OVERRUN; - } - - /* Clear interrupt flag */ - adc_module->INTFLAG.reg = int_flags; -} -/** @} */ - -/** - * \name Enable, Disable, and Reset ADC Module, Start Conversion and Read Result - * @{ - */ - -/** - * \brief Enables the ADC module. - * - * Enables an ADC module that has previously been configured. If any internal reference - * is selected it will be enabled. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline enum status_code adc_enable( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - -#if ADC_CALLBACK_MODE == true -# if (ADC_INST_NUM > 1) - system_interrupt_enable(_adc_interrupt_get_interrupt_vector( - _adc_get_inst_index(adc_module))); -# elif (SAMC20) - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC0); -# else - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_ADC); -# endif -#endif - - /* Disbale interrupt */ - adc_module->INTENCLR.reg = ADC_INTENCLR_MASK; - /* Clear interrupt flag */ - adc_module->INTFLAG.reg = ADC_INTFLAG_MASK; - - adc_module->CTRLA.reg |= ADC_CTRLA_ENABLE; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; -} - -/** - * \brief Disables the ADC module. - * - * Disables an ADC module that was previously enabled. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline enum status_code adc_disable( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - -#if ADC_CALLBACK_MODE == true -# if (ADC_INST_NUM > 1) - system_interrupt_disable(_adc_interrupt_get_interrupt_vector( - _adc_get_inst_index(adc_module))); -# elif (SAMC20) - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC0); -# else - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_ADC); -# endif -#endif - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Disbale interrupt */ - adc_module->INTENCLR.reg = ADC_INTENCLR_MASK; - /* Clear interrupt flag */ - adc_module->INTFLAG.reg = ADC_INTFLAG_MASK; - - adc_module->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; -} - -/** - * \brief Resets the ADC module. - * - * Resets an ADC module, clearing all module state, and registers to their - * default values. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline enum status_code adc_reset( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - /* Disable to make sure the pipeline is flushed before reset */ - adc_disable(module_inst); - - /* Software reset the module */ - adc_module->CTRLA.reg |= ADC_CTRLA_SWRST; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - return STATUS_OK; -} - - -/** - * \brief Enables an ADC event input or output. - * - * Enables one or more input or output events to or from the ADC module. See - * \ref adc_events "Struct adc_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the ADC peripheral - * \param[in] events Struct containing flags of events to enable - */ -static inline void adc_enable_events( - struct adc_module *const module_inst, - struct adc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Adc *const adc_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Window Monitor event */ - if (events->generate_event_on_window_monitor) { - event_mask |= ADC_EVCTRL_WINMONEO; - } - - /* Configure Result Ready event */ - if (events->generate_event_on_conversion_done) { - event_mask |= ADC_EVCTRL_RESRDYEO; - } - - adc_module->EVCTRL.reg |= event_mask; -} - -/** - * \brief Disables an ADC event input or output. - * - * Disables one or more input or output events to or from the ADC module. See - * \ref adc_events "Struct adc_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the ADC peripheral - * \param[in] events Struct containing flags of events to disable - */ -static inline void adc_disable_events( - struct adc_module *const module_inst, - struct adc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Adc *const adc_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Window Monitor event */ - if (events->generate_event_on_window_monitor) { - event_mask |= ADC_EVCTRL_WINMONEO; - } - - /* Configure Result Ready event */ - if (events->generate_event_on_conversion_done) { - event_mask |= ADC_EVCTRL_RESRDYEO; - } - - adc_module->EVCTRL.reg &= ~event_mask; -} - -/** - * \brief Starts an ADC conversion. - * - * Starts a new ADC conversion. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_start_conversion( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - adc_module->SWTRIG.reg |= ADC_SWTRIG_START; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} - -/** - * \brief Reads the ADC result. - * - * Reads the result from an ADC conversion that was previously started. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[out] result Pointer to store the result value in - * - * \return Status of the ADC read request. - * \retval STATUS_OK The result was retrieved successfully - * \retval STATUS_BUSY A conversion result was not ready - * \retval STATUS_ERR_OVERFLOW The result register has been overwritten by the - * ADC module before the result was read by the software - */ -static inline enum status_code adc_read( - struct adc_module *const module_inst, - uint16_t *result) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(result); - - if (!(adc_get_status(module_inst) & ADC_STATUS_RESULT_READY)) { - /* Result not ready */ - return STATUS_BUSY; - } - - Adc *const adc_module = module_inst->hw; - -#if (SAMD) || (SAMR21) - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -#endif - - /* Get ADC result */ - *result = adc_module->RESULT.reg; - - /* Reset ready flag */ - adc_clear_status(module_inst, ADC_STATUS_RESULT_READY); - - if (adc_get_status(module_inst) & ADC_STATUS_OVERRUN) { - adc_clear_status(module_inst, ADC_STATUS_OVERRUN); - return STATUS_ERR_OVERFLOW; - } - - return STATUS_OK; -} - -/** @} */ - -/** - * \name Runtime Changes of ADC Module - * @{ - */ - -/** - * \brief Flushes the ADC pipeline. - * - * Flushes the pipeline and restarts the ADC clock on the next peripheral clock - * edge. All conversions in progress will be lost. When flush is complete, the - * module will resume where it left off. - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_flush( - struct adc_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - adc_module->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} -void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value); - -/** - * \brief Sets positive ADC input pin. - * - * Sets the positive ADC input pin selection. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] positive_input Positive input pin - */ -static inline void adc_set_positive_input( - struct adc_module *const module_inst, - const enum adc_positive_input positive_input) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set positive input pin */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXPOS_Msk) | - (positive_input); - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} - - -/** - * \brief Sets negative ADC input pin for differential mode. - * - * Sets the negative ADC input pin, when the ADC is configured in differential - * mode. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] negative_input Negative input pin - */ -static inline void adc_set_negative_input( - struct adc_module *const module_inst, - const enum adc_negative_input negative_input) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set negative input pin */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_MUXNEG_Msk) | - (negative_input); - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } -} - -/** @} */ - -#if ADC_CALLBACK_MODE == true -/** - * \name Enable and Disable Interrupts - * @{ - */ - -/** - * \brief Enable interrupt. - * - * Enable the given interrupt request from the ADC module. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] interrupt Interrupt to enable - */ -static inline void adc_enable_interrupt(struct adc_module *const module_inst, - enum adc_interrupt_flag interrupt) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - /* Enable interrupt */ - adc_module->INTENSET.reg = interrupt; -} - -/** - * \brief Disable interrupt. - * - * Disable the given interrupt request from the ADC module. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] interrupt Interrupt to disable - */ -static inline void adc_disable_interrupt(struct adc_module *const module_inst, - enum adc_interrupt_flag interrupt) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - /* Enable interrupt */ - adc_module->INTENCLR.reg = interrupt; -} - -/** @} */ -#endif /* ADC_CALLBACK_MODE == true */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - - -/** - * \page asfdoc_sam0_adc_extra Extra Information for ADC Driver - * - * \section asfdoc_sam0_adc_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ADCAnalog-to-Digital Converter
DACDigital-to-Analog Converter
LSBLeast Significant Bit
MSBMost Significant Bit
DMADirect Memory Access
- * - * - * \section asfdoc_sam0_adc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_adc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_adc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * \if DEVICE_SAML21_SUPPORT - * - * - * - * \else - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
Changelog
Initial Release
Added support for SAM R21
Added support for SAM D21 and new DMA quick start guide
Added ADC calibration constant loading from the device signature - * row when the module is initialized
Initial Release
- */ - -/** - * \page asfdoc_sam0_adc_exqsg Examples for ADC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_adc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_adc_basic_use_case - * \if ADC_CALLBACK_MODE - * - \subpage asfdoc_sam0_adc_basic_use_case_callback - * \endif - * - \subpage asfdoc_sam0_adc_dma_use_case - * - * \page asfdoc_sam0_adc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * \if DEVICE_SAML21_SUPPORT - * - * - * - * - * - * - * - * - * - * - * \else - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
Doc. Rev.DateComments
42451B12/2015Added support for SAM L22
42451A07/2015Initial document release
42109E12/2015Added support for SAM DA1 and SAM D09
42109D12/2014Added support for SAM R21 and SAM D10/D11
42109C01/2014Added support for SAM D21
42109B06/2013Added additional documentation on the event system. Corrected - * documentation typos.
42109A06/2013Initial release
- */ - -#endif /* ADC_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/adc/adc_callback.h b/atmel-samd/asf/sam0/drivers/adc/adc_callback.h deleted file mode 100644 index f6b30e86ed517..0000000000000 --- a/atmel-samd/asf/sam0/drivers/adc/adc_callback.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef ADC_CALLBACK_H_INCLUDED -#define ADC_CALLBACK_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_adc_group - * - * @{ - */ - -#include - -/** - * Enum for the possible types of ADC asynchronous jobs that may be issued to - * the driver. - */ -enum adc_job_type { - /** Asynchronous ADC read into a user provided buffer */ - ADC_JOB_READ_BUFFER, -}; - -/** - * \name Callback Management - * @{ - */ -void adc_register_callback( - struct adc_module *const module, - adc_callback_t callback_func, - enum adc_callback callback_type); - -void adc_unregister_callback( - struct adc_module *module, - enum adc_callback callback_type); - -/** - * \brief Enables callback. - * - * Enables the callback function registered by \ref - * adc_register_callback. The callback function will be called from the - * interrupt handler when the conditions for the callback type are met. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_ERR_INVALID If operation was not completed, - * due to invalid callback_type - * - */ -static inline void adc_enable_callback( - struct adc_module *const module, - enum adc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Enable callback */ - module->enabled_callback_mask |= (1 << callback_type); - - /* Enable window interrupt if this is a window callback */ - if (callback_type == ADC_CALLBACK_WINDOW) { - adc_enable_interrupt(module, ADC_INTERRUPT_WINDOW); - } - /* Enable overrun interrupt if error callback is registered */ - if (callback_type == ADC_CALLBACK_ERROR) { - adc_enable_interrupt(module, ADC_INTERRUPT_OVERRUN); - } -} - -/** - * \brief Disables callback. - * - * Disables the callback function registered by the \ref - * adc_register_callback. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_ERR_INVALID If operation was not completed, - * due to invalid callback_type - * - */ -static inline void adc_disable_callback( - struct adc_module *const module, - enum adc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Disable callback */ - module->enabled_callback_mask &= ~(1 << callback_type); - - /* Disable window interrupt if this is a window callback */ - if (callback_type == ADC_CALLBACK_WINDOW) { - adc_disable_interrupt(module, ADC_INTERRUPT_WINDOW); - } - /* Disable overrun interrupt if this is the error callback */ - if (callback_type == ADC_CALLBACK_ERROR) { - adc_disable_interrupt(module, ADC_INTERRUPT_OVERRUN); - } -} - -/** @} */ - - -/** - * \name Job Management - * @{ - */ -enum status_code adc_read_buffer_job( - struct adc_module *const module_inst, - uint16_t *buffer, - uint16_t samples); - -enum status_code adc_get_job_status( - struct adc_module *module_inst, - enum adc_job_type type); - -void adc_abort_job( - struct adc_module *module_inst, - enum adc_job_type type); -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* ADC_CALLBACK_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/adc/adc_sam_b.h b/atmel-samd/asf/sam0/drivers/adc/adc_sam_b.h deleted file mode 100644 index 5323ad92a11ff..0000000000000 --- a/atmel-samd/asf/sam0/drivers/adc/adc_sam_b.h +++ /dev/null @@ -1,426 +0,0 @@ -/** - * \file - * - * \brief SAMB Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef ADC_SAM_B_H_INCLUDED -#define ADC_SAM_B_H_INCLUDED - -/** - * \defgroup asfdoc_samb_adc_group SAM Analog-to-Digital Converter (ADC) Driver - * - * This driver for Atmel® | SMART SAM devices provides an interface for the - * configuration and management of the device's Analog-to-Digital Converter - * functionality, for the conversion of analog voltages into a corresponding - * digital form. - * - * The following peripheral is used by this module: - * - ADC (Analog-to-Digital Converter) - * - * The following devices can use this module: - * - Atmel | SMART SAM B11 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_samb_adc_prerequisites - * - \ref asfdoc_samb_adc_module_overview - * - \ref asfdoc_samb_adc_special_considerations - * - \ref asfdoc_samb_adc_extra_info - * - \ref asfdoc_samb_adc_examples - * - \ref asfdoc_samb_adc_api_overview - * - * - * \section asfdoc_samb_adc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_samb_adc_module_overview Module Overview - * - * This driver provides an interface for the Analog-to-Digital conversion - * functions on the device, to convert analog voltages to a corresponding - * digital value. The ADC has up to 12-bit resolution. - * - * \subsection asfdoc_samb_adc_module_overview_prescaler Sample Clock Prescaler - * \f[ - * F_{clk} = N + 2 \times {(throughput\_frequency)} - * \f] - * \f[ - * (N = ADC resolution) - * \f] - * - * Example: For throughput of 100KS/s use sampling clock (Fclk=1.3MHz) - * - * \subsection asfdoc_samb_adc_module_overview_resolution ADC Resolution - * There are two ADC resolution of operation: - * - \b High Resolution (11-bit) - * - * Set the reference voltage to half the supply voltage or below. In this - * mode the input signal dynamic range equals twice the reference voltage. - * - * Example: If supply voltage =3V and reference voltage= 1.4V, input signal - * dynamic range can be from ground to 2*reference voltage (0~2.8V). - * - \b Medium Resolution (10-bit) - * - * Set the reference voltage to any value below supply voltage (up to - * supply voltage - 300mV) and in this condition the input dynamic range is - * from zero to reference voltage. - * - * Example: If supply voltage =3V and reference voltage= 2.7V, input signal - * dynamic range can be from ground to reference voltage (0~2.7V). - * - * \subsection asfdoc_samb_adc_module_overview_conversion Channel Modes - * There are two modes for input channel selection: - * - Either to assign a specific input channel - * - Time domain multiplexing between 4 input channels - * - Channel1 to channel4 - * - channel5 to channel8 - * - * \section asfdoc_samb_adc_special_considerations Special Considerations - * An integrated analog temperature sensor is available for use with the ADC. - * The internal specific voltage can also be measured by the ADC. For internal - * ADC inputs, the internal source(s) may need to be manually enabled by the - * user application before they can be measured. - * - * - * \section asfdoc_samb_adc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_samb_adc_extra. This includes: - * - \ref asfdoc_samb_adc_extra_acronyms - * - \ref asfdoc_samb_adc_extra_dependencies - * - \ref asfdoc_samb_adc_extra_errata - * - \ref asfdoc_samb_adc_extra_history - * - * - * \section asfdoc_samb_adc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_samb_adc_exqsg. - * - * - * \section asfdoc_samb_adc_api_overview API Overview - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * \brief ADC internal reference voltage level enum - * - * Enum for the possible internal reference voltage level for the ADC. - * - */ -enum adc_internal_buf { - /** Internal buffer voltage level: 0.5V */ - ADC_INTERNAL_BUF_0_5 = 0, - /** Internal buffer voltage level: 0.6V */ - ADC_INTERNAL_BUF_0_6, - /** Internal buffer voltage level: 0.7V */ - ADC_INTERNAL_BUF_0_7, - /** Internal buffer voltage level: 0.8V */ - ADC_INTERNAL_BUF_0_8, - /** Internal buffer voltage level: 0.9V */ - ADC_INTERNAL_BUF_0_9, - /** Internal buffer voltage level: 1.0V */ - ADC_INTERNAL_BUF_1_0, - /** Internal buffer voltage level: 1.1V */ - ADC_INTERNAL_BUF_1_1, - /** Internal buffer voltage level: 1.2V */ - ADC_INTERNAL_BUF_1_2, - /** Internal buffer voltage level: 1.3V */ - ADC_INTERNAL_BUF_1_3, - /** Internal buffer voltage level: 1.4V */ - ADC_INTERNAL_BUF_1_4, - /** Internal buffer voltage level: 1.5V */ - ADC_INTERNAL_BUF_1_5, - /** Internal buffer voltage level: 1.6V */ - ADC_INTERNAL_BUF_1_6, - /** Internal buffer voltage level: 1.7V */ - ADC_INTERNAL_BUF_1_7, - /** Internal buffer voltage level: 1.8V */ - ADC_INTERNAL_BUF_1_8, - /** Internal buffer voltage level: 1.9V */ - ADC_INTERNAL_BUF_1_9, - /** Internal buffer voltage level: 2.0V */ - ADC_INTERNAL_BUF_2_0, -}; - -/** - * \brief ADC reference voltage enum - * - * Enum for the possible reference voltages for the ADC. - * - */ -enum adc_reference { - /** Internal form buffer reference */ - ADC_REFERENCE_INTERNAL_BUF = 0, - /** Internal from IxR reference */ - ADC_REFERENCE_INTERNAL_IR, - /** VBATT/2 reference */ - ADC_REFERENCE_VBATT_2, - /** GPIO_MS1 reference */ - ADC_REFERENCE_GPIO_MS1, - /** GPIO_MS2 reference */ - ADC_REFERENCE_GPIO_MS2, - /** GPIO_MS3 reference */ - ADC_REFERENCE_GPIO_MS3, - /** GPIO_MS4 reference */ - ADC_REFERENCE_GPIO_MS4, - /** VBATTERY reference */ - ADC_REFERENCE_VBATT, -}; - -/** - * \brief ADC input channel selection enum - * - * Enum for the possible input channel selections for the ADC. - * - */ -enum adc_input_channel { - /** GPIO_MS1 input */ - ADC_INPUT_CH_GPIO_MS1 = 0, - /** GPIO_MS2 input */ - ADC_INPUT_CH_GPIO_MS2, - /** GPIO_MS3 input */ - ADC_INPUT_CH_GPIO_MS3, - /** GPIO_MS4 input */ - ADC_INPUT_CH_GPIO_MS4, - /** On chip temperature measurement input */ - ADC_INPUT_CH_TEMPERATURE, - /** VBATT divided by 4 voltage level */ - ADC_INPUT_CH_VBATT_4, - /** LP_LDO_OUT_1P2 low power domain voltage */ - ADC_INPUT_CH_LPD0_LDO, - /** ADC reference voltage level */ - ADC_INPUT_CH_VREF, -}; - -/** - * \brief ADC input channel time multiplexing selection mode enum - * - * Enum for the possible channel time multiplexing mode for the ADC. - * - */ -enum adc_channel_mode { - /** - * Input channels time multiplexing is between channel 0 to channel 3. - * In this mode, ADC input channel selection is invalid. - */ - ADC_CH_MODE_CH0_TO_CH3, - /** - * Input channels time multiplexing is between channel 4 to channel 7. - * In this mode, ADC input channel selection is invalid. - */ - ADC_CH_MODE_CH4_TO_CH7, - /** Assign a specific input channel using \ref adc_input_channel */ - ADC_CH_MODE_ASSIGN, -}; - -/** - * \brief ADC input dynamic range selection enum - * - * Enum for the possible input dynamic range for the ADC. - * - */ -enum adc_input_dynamic_range{ - /** Input dynamic range from 0V to VBATT voltage level */ - ADC_INPUT_DYNAMIC_RANGE_0 = 0, - /** Input dynamic range from 0.08*VBATT to 0.92*VBATT voltage level */ - ADC_INPUT_DYNAMIC_RANGE_1, - /** Input dynamic range from 0.17*VBATT to 0.83*VBATT voltage level */ - ADC_INPUT_DYNAMIC_RANGE_2, - /** Input dynamic range from 0.25*VBATT to 0.75*VBATT voltage level */ - ADC_INPUT_DYNAMIC_RANGE_3, -}; - -/** - * \brief ADC comparator biasing current enum - * - * Enum for the possible comparator biasing current for the ADC different - * sampling rates. - * - */ -enum adc_bias_current { - /** Comparator bias current is 4uA for throughput 100KS/s */ - ADC_BIAS_CURRENT_0 = 0, - /** Comparator bias current is 8uA */ - ADC_BIAS_CURRENT_1, - /** Comparator bias current is 20uA */ - ADC_BIAS_CURRENT_2, - /** Comparator bias current is 24uA for throughput 1MS/s */ - ADC_BIAS_CURRENT_3, -}; - -/** - * \brief ADC configuration structure - * - * Configuration structure for an ADC instance. This structure should be - * initialized by the \ref adc_get_config_defaults() - * function before being modified by the user application. - */ -struct adc_config { - /** Voltage reference */ - enum adc_reference reference; - /** Internal reference voltage level */ - enum adc_internal_buf internal_vref; - /** Input channel */ - enum adc_input_channel input_channel; - /** Input channel selection */ - enum adc_channel_mode channel_mode; - /** Input channel time multiplexing selection mode */ - enum adc_input_dynamic_range input_dynamic_range; - /** Comparator biasing current selection */ - enum adc_bias_current bias_current; - /** Invert ADC Clock */ - bool invert_clock; - /** Fractional part for the clock divider */ - uint8_t frac_part; - /** Integer part for the clock divider */ - uint16_t int_part; -}; - -/** \name Configuration, initialization and get status - * @{ - */ -void adc_get_config_defaults(struct adc_config *const config); -void adc_init(struct adc_config *config); -uint32_t adc_get_status(void); -/** @}*/ - -/** \name Enable/Disable and Reset - * @{ - */ -void adc_enable(void); -void adc_disable(void); -void adc_reset(void); -/** @}*/ - -/** \name Read Result - * @{ - */ -enum status_code adc_read(enum adc_input_channel input_channel, uint16_t *result); -/** @}*/ - -/** @}*/ - -#ifdef __cplusplus -} -#endif - - -/** - * \page asfdoc_samb_adc_extra Extra Information for ADC Driver - * - * \section asfdoc_samb_adc_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ADCAnalog-to-Digital Converter
- * - * - * \section asfdoc_samb_adc_extra_dependencies Dependencies - * There are no dependencies related to this driver. - * - * - * \section asfdoc_samb_adc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_samb_adc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - -/** - * \page asfdoc_samb_adc_exqsg Examples for ADC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_samb_adc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_samb_adc_basic_use_case - * - * \page asfdoc_samb_adc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
A09/2015Initial document release
- */ - -#endif /* ADC_SAM_B_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc.c b/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc.c deleted file mode 100644 index 1565c8625d5c9..0000000000000 --- a/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc.c +++ /dev/null @@ -1,715 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "asf/sam0/drivers/adc/adc.h" - -#if SAMD20 -/* The Die revision D number */ -#define REVISON_D_NUM 3 -#endif - -/** - * \brief Initializes an ADC configuration structure to defaults - * - * Initializes a given ADC configuration struct to a set of known default - * values. This function should be called on any new instance of the - * configuration struct before being modified by the user application. - * - * The default configuration is as follows: - * \li GCLK generator 0 (GCLK main) clock source - * \li 1V from internal bandgap reference - * \li Div 4 clock prescaler - * \li 12-bit resolution - * \li Window monitor disabled - * \li No gain - * \li Positive input on ADC PIN 0 - * \li Negative input on ADC PIN 1 - * \li Averaging disabled - * \li Oversampling disabled - * \li Right adjust data - * \li Single-ended mode - * \li Free running disabled - * \li All events (input and generation) disabled - * \li Sleep operation disabled - * \li No reference compensation - * \li No gain/offset correction - * \li No added sampling time - * \li Pin scan mode disabled - * - * \param[out] config Pointer to configuration struct to initialize to - * default values - */ -void adc_get_config_defaults(struct adc_config *const config) -{ - Assert(config); - config->clock_source = GCLK_GENERATOR_0; - config->reference = ADC_REFERENCE_INT1V; - config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4; - config->resolution = ADC_RESOLUTION_12BIT; - config->window.window_mode = ADC_WINDOW_MODE_DISABLE; - config->window.window_upper_value = 0; - config->window.window_lower_value = 0; - config->gain_factor = ADC_GAIN_FACTOR_1X; -#if SAMR21 - config->positive_input = ADC_POSITIVE_INPUT_PIN6 ; -#else - config->positive_input = ADC_POSITIVE_INPUT_PIN0 ; -#endif - config->negative_input = ADC_NEGATIVE_INPUT_GND ; - config->accumulate_samples = ADC_ACCUMULATE_DISABLE; - config->divide_result = ADC_DIVIDE_RESULT_DISABLE; - config->left_adjust = false; - config->differential_mode = false; - config->freerunning = false; - config->event_action = ADC_EVENT_ACTION_DISABLED; - config->run_in_standby = false; - config->reference_compensation_enable = false; - config->correction.correction_enable = false; - config->correction.gain_correction = ADC_GAINCORR_RESETVALUE; - config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE; - config->sample_length = 0; - config->pin_scan.offset_start_scan = 0; - config->pin_scan.inputs_to_scan = 0; -} - -/** - * \brief Sets the ADC window mode - * - * Sets the ADC window mode to a given mode and value range. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] window_mode Window monitor mode to set - * \param[in] window_lower_value Lower window monitor threshold value - * \param[in] window_upper_value Upper window monitor threshold value - */ -void adc_set_window_mode( - struct adc_module *const module_inst, - const enum adc_window_mode window_mode, - const int16_t window_lower_value, - const int16_t window_upper_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set window mode */ - adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set lower window monitor threshold value */ - adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set upper window monitor threshold value */ - adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos; -} - -/** -* \internal Configure MUX settings for the analog pins -* -* This function will set the given ADC input pins -* to the analog function in the pinmux, giving -* the ADC access to the analog signal -* -* \param [in] pin AINxx pin to configure -*/ -static inline void _adc_configure_ain_pin(uint32_t pin) -{ -#define PIN_INVALID_ADC_AIN 0xFFFFUL - - /* Pinmapping table for AINxx -> GPIO pin number */ - const uint32_t pinmapping[] = { -#if (SAMD20E) || (SAMD21E)|| (SAMDA1E) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13, - PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19, -#elif SAMR21E - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif SAMR21G - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5, - PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD09C) || (SAMD10C) || (SAMD11C) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD09D) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DS) || (SAMD10DU) || (SAMD11DS) || (SAMD11DU) - PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#elif (SAMD10DM) || (SAMD11DM) - PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1, - PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3, - PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5, - PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7, - PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, - PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN, -#else -# error ADC pin mappings are not defined for this device. -#endif - }; - - uint32_t pin_map_result = PIN_INVALID_ADC_AIN; - - if (pin <= ADC_EXTCHANNEL_MSB) { - pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos]; - - Assert(pin_map_result != PIN_INVALID_ADC_AIN); - - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); - - /* Analog functions are all on MUX setting B */ - config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - config.mux_position = 1; - - system_pinmux_pin_set_config(pin_map_result, &config); - } -} - -/** - * \internal Writes an ADC configuration to the hardware module - * - * Writes out a given ADC module configuration to the hardware module. - * - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] config Pointer to configuration struct - * - * \return Status of the configuration procedure - * \retval STATUS_OK The configuration was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - */ -static enum status_code _adc_set_config( - struct adc_module *const module_inst, - struct adc_config *const config) -{ - uint8_t adjres = 0; - uint32_t resolution = ADC_RESOLUTION_16BIT; - enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE; -#if SAMD20 - uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos); -#endif - - /* Get the hardware module pointer */ - Adc *const adc_module = module_inst->hw; - - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(ADC_GCLK_ID); - - /* Setup pinmuxing for analog inputs */ - if (config->pin_scan.inputs_to_scan != 0) { - uint8_t offset = config->pin_scan.offset_start_scan; - uint8_t start_pin = - offset +(uint8_t)config->positive_input; - uint8_t end_pin = - start_pin + config->pin_scan.inputs_to_scan; - - while (start_pin < end_pin) { - _adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input); - start_pin++; - offset++; - } - _adc_configure_ain_pin(config->negative_input); - } else { - _adc_configure_ain_pin(config->positive_input); - _adc_configure_ain_pin(config->negative_input); - } - - /* Configure run in standby */ - adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos); - - /* Configure reference */ - adc_module->REFCTRL.reg = - (config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) | - (config->reference); - - /* Set adjusting result and number of samples */ - switch (config->resolution) { - - case ADC_RESOLUTION_CUSTOM: - adjres = config->divide_result; - accumulate = config->accumulate_samples; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_13BIT: - /* Increase resolution by 1 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_4; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_14BIT: - /* Increase resolution by 2 bit */ - adjres = ADC_DIVIDE_RESULT_4; - accumulate = ADC_ACCUMULATE_SAMPLES_16; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#if SAMD20 - /* See $35.1.8 for ADC errata of SAM D20. - The revisions before D have this issue.*/ - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - if(revision_num < REVISON_D_NUM) { - adjres = ADC_DIVIDE_RESULT_8; - } else { - adjres = ADC_DIVIDE_RESULT_2; - } - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_16BIT: - if(revision_num < REVISON_D_NUM) { - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_16; - } else { - adjres = ADC_DIVIDE_RESULT_DISABLE; - } - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#else - case ADC_RESOLUTION_15BIT: - /* Increase resolution by 3 bit */ - adjres = ADC_DIVIDE_RESULT_2; - accumulate = ADC_ACCUMULATE_SAMPLES_64; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; - - case ADC_RESOLUTION_16BIT: - /* Increase resolution by 4 bit */ - adjres = ADC_DIVIDE_RESULT_DISABLE; - accumulate = ADC_ACCUMULATE_SAMPLES_256; - /* 16-bit result register */ - resolution = ADC_RESOLUTION_16BIT; - break; -#endif - case ADC_RESOLUTION_8BIT: - /* 8-bit result register */ - resolution = ADC_RESOLUTION_8BIT; - break; - case ADC_RESOLUTION_10BIT: - /* 10-bit result register */ - resolution = ADC_RESOLUTION_10BIT; - break; - case ADC_RESOLUTION_12BIT: - /* 12-bit result register */ - resolution = ADC_RESOLUTION_12BIT; - break; - - default: - /* Unknown. Abort. */ - return STATUS_ERR_INVALID_ARG; - } - - adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate; - - /* Check validity of sample length value */ - if (config->sample_length > 63) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Configure sample length */ - adc_module->SAMPCTRL.reg = - (config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos); - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure CTRLB */ - adc_module->CTRLB.reg = - config->clock_prescaler | - resolution | - (config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) | - (config->freerunning << ADC_CTRLB_FREERUN_Pos) | - (config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) | - (config->differential_mode << ADC_CTRLB_DIFFMODE_Pos); - - /* Check validity of window thresholds */ - if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) { - switch (resolution) { - case ADC_RESOLUTION_8BIT: - if (config->differential_mode && - (config->window.window_lower_value > 127 || - config->window.window_lower_value < -128 || - config->window.window_upper_value > 127 || - config->window.window_upper_value < -128)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 255 || - config->window.window_upper_value > 255){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_10BIT: - if (config->differential_mode && - (config->window.window_lower_value > 511 || - config->window.window_lower_value < -512 || - config->window.window_upper_value > 511 || - config->window.window_upper_value < -512)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 1023 || - config->window.window_upper_value > 1023){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_12BIT: - if (config->differential_mode && - (config->window.window_lower_value > 2047 || - config->window.window_lower_value < -2048 || - config->window.window_upper_value > 2047 || - config->window.window_upper_value < -2048)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 4095 || - config->window.window_upper_value > 4095){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - case ADC_RESOLUTION_16BIT: - if (config->differential_mode && - (config->window.window_lower_value > 32767 || - config->window.window_lower_value < -32768 || - config->window.window_upper_value > 32767 || - config->window.window_upper_value < -32768)) { - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } else if (config->window.window_lower_value > 65535 || - config->window.window_upper_value > 65535){ - /* Invalid value */ - return STATUS_ERR_INVALID_ARG; - } - break; - } - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure window mode */ - adc_module->WINCTRL.reg = config->window.window_mode; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINLT.reg = - config->window.window_lower_value << ADC_WINLT_WINLT_Pos; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure lower threshold */ - adc_module->WINUT.reg = config->window.window_upper_value << - ADC_WINUT_WINUT_Pos; - - uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan; - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } - - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins or input offset */ - return STATUS_ERR_INVALID_ARG; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Configure pin scan mode and positive and negative input pins */ - adc_module->INPUTCTRL.reg = - config->gain_factor | - (config->pin_scan.offset_start_scan << - ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) | - config->negative_input | - config->positive_input; - - /* Configure events */ - adc_module->EVCTRL.reg = config->event_action; - - /* Disable all interrupts */ - adc_module->INTENCLR.reg = - (1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) | - (1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos); - - if (config->correction.correction_enable){ - /* Make sure gain_correction value is valid */ - if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set gain correction value */ - adc_module->GAINCORR.reg = config->correction.gain_correction << - ADC_GAINCORR_GAINCORR_Pos; - } - - /* Make sure offset correction value is valid */ - if (config->correction.offset_correction > 2047 || - config->correction.offset_correction < -2048) { - return STATUS_ERR_INVALID_ARG; - } else { - /* Set offset correction value */ - adc_module->OFFSETCORR.reg = config->correction.offset_correction << - ADC_OFFSETCORR_OFFSETCORR_Pos; - } - } - - /* Load in the fixed device ADC calibration constants */ - adc_module->CALIB.reg = - ADC_CALIB_BIAS_CAL( - (*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos) - ) | - ADC_CALIB_LINEARITY_CAL( - (*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos) - ); - - return STATUS_OK; -} - -/** - * \brief Initializes the ADC channel sequence - * - * Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one - * automatically after a conversion done, causing the next conversion - * to be done with the positive input equal to MUXPOS + INPUTOFFSET, - * it is scanning continuously one by one even ADC channels are not continuous. - * - * Initializes the ADC channel sequence by the sequence of pin_array. - * - * \param[in] pin_array The array of the Mux selection for the positive ADC input - * \param[in] size The size of pin_array - */ -void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size) -{ - for (int i = 0; i < size; i++) { - _adc_configure_ain_pin(pin_array[i]); - } -} - -/** - * \brief Initializes the ADC - * - * Initializes the ADC device struct and the hardware module based on the - * given configuration struct values. - * - * \param[out] module_inst Pointer to the ADC software instance struct - * \param[in] hw Pointer to the ADC module instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of the initialization procedure. - * \retval STATUS_OK The initialization was successful - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided - * \retval STATUS_BUSY The module is busy with a reset operation - * \retval STATUS_ERR_DENIED The module is enabled - */ -enum status_code adc_init( - struct adc_module *const module_inst, - Adc *hw, - struct adc_config *config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(hw); - Assert(config); - - /* Associate the software module instance with the hardware module */ - module_inst->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC); - - if (hw->CTRLA.reg & ADC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - /* Store the selected reference for later use */ - module_inst->reference = config->reference; - - /* Make sure bandgap is enabled if requested by the config */ - if (module_inst->reference == ADC_REFERENCE_INT1V) { - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); - } - -#if ADC_CALLBACK_MODE == true - for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - }; - - module_inst->registered_callback_mask = 0; - module_inst->enabled_callback_mask = 0; - module_inst->remaining_conversions = 0; - module_inst->job_status = STATUS_OK; - - _adc_instances[0] = module_inst; - - if (config->event_action == ADC_EVENT_ACTION_DISABLED && - !config->freerunning) { - module_inst->software_trigger = true; - } else { - module_inst->software_trigger = false; - } -#endif - - /* Write configuration to module */ - return _adc_set_config(module_inst, config); -} diff --git a/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc_callback.c b/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc_callback.c deleted file mode 100644 index 6f673dd344a08..0000000000000 --- a/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc_callback.c +++ /dev/null @@ -1,255 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Analog-to-Digital Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "adc_callback.h" - -struct adc_module *_adc_instances[ADC_INST_NUM]; - -static void _adc_interrupt_handler(const uint8_t instance) -{ - struct adc_module *module = _adc_instances[instance]; - - /* get interrupt flags and mask out enabled callbacks */ - uint32_t flags = module->hw->INTFLAG.reg; - - if (flags & ADC_INTFLAG_RESRDY) { - if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER)) && - (module->registered_callback_mask & (1 << ADC_CALLBACK_READ_BUFFER))) { - /* clear interrupt flag */ - module->hw->INTFLAG.reg = ADC_INTFLAG_RESRDY; - - while (adc_is_syncing(module)) { - /* Wait for synchronization */ - } - - /* store ADC result in job buffer */ - *(module->job_buffer++) = module->hw->RESULT.reg; - - if (--module->remaining_conversions > 0) { - if (module->software_trigger == true) { - adc_start_conversion(module); - } - } else { - if (module->job_status == STATUS_BUSY) { - /* job is complete. update status,disable interrupt - *and call callback */ - module->job_status = STATUS_OK; - adc_disable_interrupt(module, ADC_INTERRUPT_RESULT_READY); - - (module->callback[ADC_CALLBACK_READ_BUFFER])(module); - } - } - } - } - - if (flags & ADC_INTFLAG_WINMON) { - module->hw->INTFLAG.reg = ADC_INTFLAG_WINMON; - if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_WINDOW)) && - (module->registered_callback_mask & (1 << ADC_CALLBACK_WINDOW))) { - (module->callback[ADC_CALLBACK_WINDOW])(module); - } - - } - - if (flags & ADC_INTFLAG_OVERRUN) { - module->hw->INTFLAG.reg = ADC_INTFLAG_OVERRUN; - if ((module->enabled_callback_mask & (1 << ADC_CALLBACK_ERROR)) && - (module->registered_callback_mask & (1 << ADC_CALLBACK_ERROR))) { - (module->callback[ADC_CALLBACK_ERROR])(module); - } - } -} - -/** Interrupt handler for the ADC module. */ -void ADC_Handler(void) -{ - _adc_interrupt_handler(0); -} - -/** - * \brief Registers a callback - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by for the interrupt handler to call it - * when the condition for the callback is met. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - * - */ -void adc_register_callback( - struct adc_module *const module, - adc_callback_t callback_func, - enum adc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); - - /* Register callback function */ - module->callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module->registered_callback_mask |= (1 << callback_type); -} - -/** - * \brief Unregisters a callback - * - * Unregisters a callback function which is implemented by the user. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] callback_type Callback type given by an enum - * - */ -void adc_unregister_callback( - struct adc_module *const module, - enum adc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Unregister callback function */ - module->callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module->registered_callback_mask &= ~(1 << callback_type); -} - -/** - * \brief Read multiple samples from ADC - * - * Read \c samples samples from the ADC into the buffer \c buffer. - * If there is no hardware trigger defined (event action) the - * driver will retrigger the ADC conversion whenever a conversion - * is complete until \c samples samples has been acquired. To avoid - * jitter in the sampling frequency using an event trigger is advised. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] samples Number of samples to acquire - * \param[out] buffer Buffer to store the ADC samples - * - * \return Status of the job start. - * \retval STATUS_OK The conversion job was started successfully and is - * in progress - * \retval STATUS_BUSY The ADC is already busy with another job - */ -enum status_code adc_read_buffer_job( - struct adc_module *const module_inst, - uint16_t *buffer, - uint16_t samples) -{ - Assert(module_inst); - Assert(samples); - Assert(buffer); - - if(module_inst->remaining_conversions != 0 || - module_inst->job_status == STATUS_BUSY){ - return STATUS_BUSY; - } - - module_inst->job_status = STATUS_BUSY; - module_inst->remaining_conversions = samples; - module_inst->job_buffer = buffer; - - adc_enable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY); - - if(module_inst->software_trigger == true) { - adc_start_conversion(module_inst); - } - - return STATUS_OK; -} - -/** - * \brief Gets the status of a job - * - * Gets the status of an ongoing or the last job. - * - * \param [in] module_inst Pointer to the ADC software instance struct - * \param [in] type Type of job to get status - * - * \return Status of the job. - */ -enum status_code adc_get_job_status( - struct adc_module *module_inst, - enum adc_job_type type) -{ - /* Sanity check arguments */ - Assert(module_inst); - - if (type == ADC_JOB_READ_BUFFER ) { - return module_inst->job_status; - } else { - return STATUS_ERR_INVALID_ARG; - } -} - -/** - * \brief Aborts an ongoing job - * - * Aborts an ongoing job. - * - * \param [in] module_inst Pointer to the ADC software instance struct - * \param [in] type Type of job to abort - */ -void adc_abort_job( - struct adc_module *module_inst, - enum adc_job_type type) -{ - /* Sanity check arguments */ - Assert(module_inst); - - if (type == ADC_JOB_READ_BUFFER) { - /* Disable interrupt */ - adc_disable_interrupt(module_inst, ADC_INTERRUPT_RESULT_READY); - /* Mark job as aborted */ - module_inst->job_status = STATUS_ABORTED; - module_inst->remaining_conversions = 0; - } -} - diff --git a/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc_feature.h b/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc_feature.h deleted file mode 100644 index 9635a190d7abb..0000000000000 --- a/atmel-samd/asf/sam0/drivers/adc/adc_sam_d_r/adc_feature.h +++ /dev/null @@ -1,728 +0,0 @@ -/** - * \file - * - * \brief SAM ADC functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef ADC_FEATURE_H_INCLUDED -#define ADC_FEATURE_H_INCLUDED - -/** - * \addtogroup asfdoc_sam0_adc_group - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#if ADC_CALLBACK_MODE == true -# include - -#if !defined(__DOXYGEN__) -extern struct adc_module *_adc_instances[ADC_INST_NUM]; -#endif - -/** Forward definition of the device instance. */ -struct adc_module; - -/** Type of the callback functions. */ -typedef void (*adc_callback_t)(struct adc_module *const module); - -/** - * \brief ADC Callback enum - * - * Callback types for ADC callback driver. - * - */ -enum adc_callback { - /** Callback for buffer received */ - ADC_CALLBACK_READ_BUFFER, - /** Callback when window is hit */ - ADC_CALLBACK_WINDOW, - /** Callback for error */ - ADC_CALLBACK_ERROR, -# if !defined(__DOXYGEN__) - /** Number of available callbacks */ - ADC_CALLBACK_N, -# endif -}; - -#endif - -/** - * \brief ADC reference voltage enum - * - * Enum for the possible reference voltages for the ADC. - * - */ -enum adc_reference { - /** 1.0V voltage reference */ - ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V, - /** 1/1.48VCC reference */ - ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0, - /** 1/2VCC (only for internal VCC > 2.1V) */ - ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1, - /** External reference A */ - ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA, - /** External reference B */ - ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB, -}; - -/** - * \brief ADC clock prescaler enum - * - * Enum for the possible clock prescaler values for the ADC. - * - */ -enum adc_clock_prescaler { - /** ADC clock division factor 4 */ - ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4, - /** ADC clock division factor 8 */ - ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8, - /** ADC clock division factor 16 */ - ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16, - /** ADC clock division factor 32 */ - ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32, - /** ADC clock division factor 64 */ - ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64, - /** ADC clock division factor 128 */ - ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128, - /** ADC clock division factor 256 */ - ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256, - /** ADC clock division factor 512 */ - ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512, -}; - -/** - * \brief ADC resolution enum - * - * Enum for the possible resolution values for the ADC. - * - */ -enum adc_resolution { - /** ADC 12-bit resolution */ - ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT, - /** ADC 16-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT, - /** ADC 10-bit resolution */ - ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT, - /** ADC 8-bit resolution */ - ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT, - /** ADC 13-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_13BIT, - /** ADC 14-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_14BIT, - /** ADC 15-bit resolution using oversampling and decimation */ - ADC_RESOLUTION_15BIT, - /** ADC 16-bit result register for use with averaging. When using this mode - * the ADC result register will be set to 16-bit wide, and the number of - * samples to accumulate and the division factor is configured by the - * \ref adc_config.accumulate_samples and \ref adc_config.divide_result - * members in the configuration struct. - */ - ADC_RESOLUTION_CUSTOM, -}; - -/** - * \brief ADC window monitor mode enum - * - * Enum for the possible window monitor modes for the ADC. - * - */ -enum adc_window_mode { - /** No window mode */ - ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE, - /** RESULT > WINLT */ - ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1, - /** RESULT < WINUT */ - ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2, - /** WINLT < RESULT < WINUT */ - ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3, - /** !(WINLT < RESULT < WINUT) */ - ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4, -}; - -/** - * \brief ADC gain factor selection enum - * - * Enum for the possible gain factor values for the ADC. - * - */ -enum adc_gain_factor { - /** 1x gain */ - ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X, - /** 2x gain */ - ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X, - /** 4x gain */ - ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X, - /** 8x gain */ - ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X, - /** 16x gain */ - ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X, - /** 1/2x gain */ - ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2, -}; - -/** - * \brief ADC event action enum - * - * Enum for the possible actions to take on an incoming event. - * - */ -enum adc_event_action { - /** Event action disabled */ - ADC_EVENT_ACTION_DISABLED = 0, - /** Flush ADC and start conversion */ - ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI, - /** Start conversion */ - ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI, -}; - -/** - * \brief ADC positive MUX input selection enum - * - * Enum for the possible positive MUX input selections for the ADC. - * - */ -enum adc_positive_input { - /** ADC0 pin */ - ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0, - /** ADC1 pin */ - ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1, - /** ADC2 pin */ - ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2, - /** ADC3 pin */ - ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3, - /** ADC4 pin */ - ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4, - /** ADC5 pin */ - ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5, - /** ADC6 pin */ - ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6, - /** ADC7 pin */ - ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7, - /** ADC8 pin */ - ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8, - /** ADC9 pin */ - ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9, - /** ADC10 pin */ - ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10, - /** ADC11 pin */ - ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11, - /** ADC12 pin */ - ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12, - /** ADC13 pin */ - ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13, - /** ADC14 pin */ - ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14, - /** ADC15 pin */ - ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15, - /** ADC16 pin */ - ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16, - /** ADC17 pin */ - ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17, - /** ADC18 pin */ - ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18, - /** ADC19 pin */ - ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19, - /** Temperature reference */ - ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP, - /** Bandgap voltage */ - ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP, - /** 1/4 scaled core supply */ - ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC, - /** 1/4 scaled I/O supply */ - ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC, - /** DAC input */ - ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC, -}; - -/** - * \brief ADC negative Multiplexer(MUX) input selection enum - * - * Enum for the possible negative Multiplexer(MUX) input selections for the ADC. - * - */ -enum adc_negative_input { - /** ADC0 pin */ - ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0, - /** ADC1 pin */ - ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1, - /** ADC2 pin */ - ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2, - /** ADC3 pin */ - ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3, - /** ADC4 pin */ - ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4, - /** ADC5 pin */ - ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5, - /** ADC6 pin */ - ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6, - /** ADC7 pin */ - ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7, - /** Internal ground */ - ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND, - /** I/O ground */ - ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND, -}; - -/** - * \brief ADC number of accumulated samples enum - * - * Enum for the possible numbers of ADC samples to accumulate. - * This setting is only used when the \ref ADC_RESOLUTION_CUSTOM - * resolution setting is used. - * - */ -enum adc_accumulate_samples { - /** No averaging */ - ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1, - /** Average 2 samples */ - ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2, - /** Average 4 samples */ - ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4, - /** Average 8 samples */ - ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8, - /** Average 16 samples */ - ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16, - /** Average 32 samples */ - ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32, - /** Average 64 samples */ - ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64, - /** Average 128 samples */ - ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128, - /** Average 256 samples */ - ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256, - /** Average 512 samples */ - ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512, - /** Average 1024 samples */ - ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024, -}; - -/** - * \brief ADC possible dividers for the result register - * - * Enum for the possible division factors to use when accumulating - * multiple samples. To keep the same resolution for the averaged - * result and the actual input value, the division factor must - * be equal to the number of samples accumulated. This setting is only - * used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used. - */ -enum adc_divide_result { - /** Don't divide result register after accumulation */ - ADC_DIVIDE_RESULT_DISABLE = 0, - /** Divide result register by 2 after accumulation */ - ADC_DIVIDE_RESULT_2 = 1, - /** Divide result register by 4 after accumulation */ - ADC_DIVIDE_RESULT_4 = 2, - /** Divide result register by 8 after accumulation */ - ADC_DIVIDE_RESULT_8 = 3, - /** Divide result register by 16 after accumulation */ - ADC_DIVIDE_RESULT_16 = 4, - /** Divide result register by 32 after accumulation */ - ADC_DIVIDE_RESULT_32 = 5, - /** Divide result register by 64 after accumulation */ - ADC_DIVIDE_RESULT_64 = 6, - /** Divide result register by 128 after accumulation */ - ADC_DIVIDE_RESULT_128 = 7, -}; - -#if ADC_CALLBACK_MODE == true -/** - * Enum for the possible ADC interrupt flags. - */ -enum adc_interrupt_flag { - /** ADC result ready */ - ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY, - /** Window monitor match */ - ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON, - /** ADC result overwritten before read */ - ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN, -}; -#endif - -/** - * \brief ADC oversampling and decimation enum - * - * Enum for the possible numbers of bits resolution can be increased by when - * using oversampling and decimation. - * - */ -enum adc_oversampling_and_decimation { - /** Don't use oversampling and decimation mode */ - ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0, - /** 1-bit resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_1BIT, - /** 2-bit resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_2BIT, - /** 3-bit resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_3BIT, - /** 4-bit resolution increase */ - ADC_OVERSAMPLING_AND_DECIMATION_4BIT -}; - -/** - * \brief Window monitor configuration structure - * - * Window monitor configuration structure. - */ -struct adc_window_config { - /** Selected window mode */ - enum adc_window_mode window_mode; - /** Lower window value */ - int32_t window_lower_value; - /** Upper window value */ - int32_t window_upper_value; -}; - -/** - * \brief ADC event enable/disable structure. - * - * Event flags for the ADC module. This is used to enable and - * disable events via \ref adc_enable_events() and \ref adc_disable_events(). - */ -struct adc_events { - /** Enable event generation on conversion done */ - bool generate_event_on_conversion_done; - /** Enable event generation on window monitor */ - bool generate_event_on_window_monitor; -}; - -/** - * \brief Gain and offset correction configuration structure - * - * Gain and offset correction configuration structure. - * Part of the \ref adc_config struct and will be initialized by - * \ref adc_get_config_defaults. - */ -struct adc_correction_config { - /** - * Enables correction for gain and offset based on values of gain_correction and - * offset_correction if set to true - */ - bool correction_enable; - /** - * This value defines how the ADC conversion result is compensated for gain - * error before written to the result register. This is a fractional value, - * 1-bit integer plus an 11-bit fraction, therefore - * 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from - * \c 0b010000000000 to \c 0b111111111111. - */ - uint16_t gain_correction; - /** - * This value defines how the ADC conversion result is compensated for - * offset error before written to the result register. This is a 12-bit - * value in two's complement format. - */ - int16_t offset_correction; -}; - -/** - * \brief Pin scan configuration structure - * - * Pin scan configuration structure. Part of the \ref adc_config struct and will - * be initialized by \ref adc_get_config_defaults. - */ -struct adc_pin_scan_config { - /** - * Offset (relative to selected positive input) of the first input pin to be - * used in pin scan mode - */ - uint8_t offset_start_scan; - /** - * Number of input pins to scan in pin scan mode. A value below two will - * disable pin scan mode. - */ - uint8_t inputs_to_scan; -}; - -/** - * \brief ADC configuration structure - * - * Configuration structure for an ADC instance. This structure should be - * initialized by the \ref adc_get_config_defaults() - * function before being modified by the user application. - */ -struct adc_config { - /** GCLK generator used to clock the peripheral */ - enum gclk_generator clock_source; - /** Voltage reference */ - enum adc_reference reference; - /** Clock prescaler */ - enum adc_clock_prescaler clock_prescaler; - /** Result resolution */ - enum adc_resolution resolution; - /** Gain factor */ - enum adc_gain_factor gain_factor; - /** Positive Multiplexer (MUX) input */ - enum adc_positive_input positive_input; - /** Negative MUX input. For singled-ended conversion mode, the negative - * input must be connected to ground. This ground could be the internal - * GND, IOGND or an external ground connected to a pin. */ - enum adc_negative_input negative_input; - /** Number of ADC samples to accumulate when using the - * \c ADC_RESOLUTION_CUSTOM mode. Note: if the result width increases, - * result resolution will be changed accordingly. - */ - enum adc_accumulate_samples accumulate_samples; - /** Division ration when using the ADC_RESOLUTION_CUSTOM mode */ - enum adc_divide_result divide_result; - /** Left adjusted result */ - bool left_adjust; - /** Enables differential mode if true. - * if false, ADC will run in singled-ended mode. */ - bool differential_mode; - /** Enables free running mode if true */ - bool freerunning; - /** Enables ADC in standby sleep mode if true */ - bool run_in_standby; - /** - * Enables reference buffer offset compensation if true. - * This will increase the accuracy of the gain stage, but decreases the input - * impedance; therefore the startup time of the reference must be increased. - */ - bool reference_compensation_enable; - /** - * This value (0-63) control the ADC sampling time in number of half ADC - * prescaled clock cycles (depends of \c ADC_PRESCALER value), thus - * controlling the ADC input impedance. Sampling time is set according to - * the formula: - * Sample time = (sample_length+1) * (ADCclk / 2). - */ - uint8_t sample_length; - /** Window monitor configuration structure */ - struct adc_window_config window; - /** Gain and offset correction configuration structure */ - struct adc_correction_config correction; - /** Event action to take on incoming event */ - enum adc_event_action event_action; - /** Pin scan configuration structure */ - struct adc_pin_scan_config pin_scan; -}; - -/** - * \brief ADC software device instance structure. - * - * ADC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct adc_module { -#if !defined(__DOXYGEN__) - /** Pointer to ADC hardware module */ - Adc *hw; - /** Keep reference configuration so we know when enable is called */ - enum adc_reference reference; -# if ADC_CALLBACK_MODE == true - /** Array to store callback functions */ - adc_callback_t callback[ADC_CALLBACK_N]; - /** Pointer to buffer used for ADC results */ - volatile uint16_t *job_buffer; - /** Remaining number of conversions in current job */ - volatile uint16_t remaining_conversions; - /** Bit mask for callbacks registered */ - uint8_t registered_callback_mask; - /** Bit mask for callbacks enabled */ - uint8_t enabled_callback_mask; - /** Holds the status of the ongoing or last conversion job */ - volatile enum status_code job_status; - /** If software triggering is needed */ - bool software_trigger; -# endif -#endif -}; - -#if !defined(__DOXYGEN__) - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true if the module synchronization is ongoing - * \retval false if the module has completed synchronization - */ -static inline bool adc_is_syncing( - struct adc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - - Adc *const adc_module = module_inst->hw; - - if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) { - return true; - } - - return false; -} -#endif - -/** - * \name ADC Gain and Pin Scan Mode - * @{ - */ - -/** - * \brief Sets ADC gain factor - * - * Sets the ADC gain factor to a specified gain setting. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] gain_factor Gain factor value to set - */ -static inline void adc_set_gain( - struct adc_module *const module_inst, - const enum adc_gain_factor gain_factor) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set new gain factor */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) | - (gain_factor); -} - -/** - * \brief Sets the ADC pin scan mode - * - * Configures the pin scan mode of the ADC module. In pin scan mode, the first - * conversion will start at the configured positive input + start_offset. When - * a conversion is done, a conversion will start on the next input, until - * \c inputs_to_scan number of conversions are made. - * - * \param[in] module_inst Pointer to the ADC software instance struct - * \param[in] inputs_to_scan Number of input pins to perform a conversion on - * (must be two or more) - * \param[in] start_offset Offset of first pin to scan (relative to - * configured positive input) - * - * \return Status of the pin scan configuration set request. - * - * \retval STATUS_OK Pin scan mode has been set successfully - * \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has - * an invalid value - */ -static inline enum status_code adc_set_pin_scan_mode( - struct adc_module *const module_inst, - uint8_t inputs_to_scan, - const uint8_t start_offset) - -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Adc *const adc_module = module_inst->hw; - - if (inputs_to_scan > 0) { - /* - * Number of input sources included is the value written to INPUTSCAN - * plus 1. - */ - inputs_to_scan--; - } - - if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) || - start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) { - /* Invalid number of input pins */ - return STATUS_ERR_INVALID_ARG; - } - - while (adc_is_syncing(module_inst)) { - /* Wait for synchronization */ - } - - /* Set pin scan mode */ - adc_module->INPUTCTRL.reg = - (adc_module->INPUTCTRL.reg & - ~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) | - (start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) | - (inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos); - - return STATUS_OK; -} - -/** - * \brief Disables pin scan mode - * - * Disables pin scan mode. The next conversion will be made on only one pin - * (the configured positive input pin). - * - * \param[in] module_inst Pointer to the ADC software instance struct - */ -static inline void adc_disable_pin_scan_mode( - struct adc_module *const module_inst) -{ - /* Disable pin scan mode */ - adc_set_pin_scan_mode(module_inst, 0, 0); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif /* ADC_FEATURE_H_INCLUDED */ - diff --git a/atmel-samd/asf/sam0/drivers/dac/dac.h b/atmel-samd/asf/sam0/drivers/dac/dac.h deleted file mode 100644 index f26e08e5a0798..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dac/dac.h +++ /dev/null @@ -1,207 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DAC_H_INCLUDED -#define DAC_H_INCLUDED - - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \addtogroup asfdoc_sam0_dac_group - * - * @{ - */ - -/** - * Define DAC features set according to different device families. - * @{ - */ -#if (SAMD21 || SAMD10 || SAMD11 || SAMDA1) -# define FEATURE_DAC_DATABUF_WRITE_PROTECTION -#endif -/**@}*/ - -#ifndef DAC_TIMEOUT -# define DAC_TIMEOUT 0xFFFF -#endif - -#if DAC_CALLBACK_MODE == true -# include - -/** Forward definition of the device instance. */ -struct dac_module; - -#if !defined(__DOXYGEN__) -extern struct dac_module *_dac_instances[DAC_INST_NUM]; -#endif - -/** Type definition for a DAC module callback function. */ -typedef void (*dac_callback_t)(uint8_t channel); - -/** Enum for the possible callback types for the DAC module. */ -enum dac_callback { - /** Callback type for when a DAC channel data empty condition occurs - * (requires event triggered mode) */ - DAC_CALLBACK_DATA_EMPTY, - - /** Callback type for when a DAC channel data underrun condition occurs - * (requires event triggered mode) */ - DAC_CALLBACK_DATA_UNDERRUN, - - /** Callback type for when a DAC channel write buffer job complete (requires - * event triggered mode) */ - DAC_CALLBACK_TRANSFER_COMPLETE, -#if !defined(__DOXYGEN__) - DAC_CALLBACK_N, -#endif -}; - -#endif - -#include - -/** - * \name Configuration and Initialization - * @{ - */ - -bool dac_is_syncing( - struct dac_module *const dev_inst); - -void dac_get_config_defaults( - struct dac_config *const config); - -enum status_code dac_init( - struct dac_module *const dev_inst, - Dac *const module, - struct dac_config *const config); - -void dac_reset( - struct dac_module *const dev_inst); - -void dac_enable( - struct dac_module *const dev_inst); - -void dac_disable( - struct dac_module *const dev_inst); - -void dac_enable_events( - struct dac_module *const module_inst, - struct dac_events *const events); - -void dac_disable_events( - struct dac_module *const module_inst, - struct dac_events *const events); - -/** @} */ - -/** - * \name Configuration and Initialization (Channel) - * @{ - */ - -void dac_chan_get_config_defaults( - struct dac_chan_config *const config); - -void dac_chan_set_config( - struct dac_module *const dev_inst, - const enum dac_channel channel, - struct dac_chan_config *const config); - -void dac_chan_enable( - struct dac_module *const dev_inst, - enum dac_channel channel); - -void dac_chan_disable( - struct dac_module *const dev_inst, - enum dac_channel channel); - -/** @} */ - -/** - * \name Channel Data Management - * @{ - */ - -enum status_code dac_chan_write( - struct dac_module *const dev_inst, - enum dac_channel channel, - const uint16_t data); - -enum status_code dac_chan_write_buffer_wait( - struct dac_module *const module_inst, - enum dac_channel channel, - uint16_t *buffer, - uint32_t length); - -/** @} */ - -/** - * \name Status Management - * @{ - */ -uint32_t dac_get_status( - struct dac_module *const module_inst); -void dac_clear_status( - struct dac_module *const module_inst, - uint32_t status_flags); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - - -#endif /* DAC_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/dac/dac_callback.h b/atmel-samd/asf/sam0/drivers/dac/dac_callback.h deleted file mode 100644 index 0de73056b0547..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dac/dac_callback.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * \file - * - * \brief SAM Digital-to-Analog Interrupt Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DAC_CALLBACK_H_INCLUDED -#define DAC_CALLBACK_H_INCLUDED - -#include -#include "dac.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_dac_group - * - * @{ - */ - -/** \name Callback Configuration and Initialization - * @{ - */ -enum status_code dac_chan_write_buffer_job( - struct dac_module *const module_inst, - const enum dac_channel channel, - uint16_t *buffer, - uint32_t buffer_size); - -enum status_code dac_chan_write_job( - struct dac_module *const module_inst, - const enum dac_channel channel, - uint16_t data); - -enum status_code dac_register_callback( - struct dac_module *const module, - const enum dac_channel channel, - const dac_callback_t callback, - const enum dac_callback type); - -enum status_code dac_unregister_callback( - struct dac_module *const module, - const enum dac_channel channel, - const enum dac_callback type); - -/** @} */ - -/** \name Callback Enabling and Disabling (Channel) - * @{ - */ - -enum status_code dac_chan_enable_callback( - struct dac_module *const module, - const enum dac_channel channel, - const enum dac_callback type); - -enum status_code dac_chan_disable_callback( - struct dac_module *const module, - const enum dac_channel channel, - const enum dac_callback type); - -enum status_code dac_chan_get_job_status( - struct dac_module *module_inst, - const enum dac_channel channel); - -void dac_chan_abort_job( - struct dac_module *module_inst, - const enum dac_channel channel); - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac.c b/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac.c deleted file mode 100644 index aa73badd3ab07..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac.c +++ /dev/null @@ -1,779 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "dac.h" -#include -#include - -/** - * \internal Writes a DAC configuration to the hardware module. - * - * Writes out a given configuration to the hardware module. - * - * \param[out] module_inst Pointer to the DAC software instance struct - * \param[in] config Pointer to the configuration struct - * - */ -static void _dac_set_config( - struct dac_module *const module_inst, - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(config); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Set selected DAC output to be enabled when enabling the module */ - module_inst->output = config->output; - module_inst->start_on_event = false; - - uint32_t new_ctrla = 0; - uint32_t new_ctrlb = 0; - - /* Enable DAC in standby sleep mode if configured */ - if (config->run_in_standby) { - new_ctrla |= DAC_CTRLA_RUNSTDBY; - } - - /* Set reference voltage */ - new_ctrlb |= config->reference; - - /* Left adjust data if configured */ - if (config->left_adjust) { - new_ctrlb |= DAC_CTRLB_LEFTADJ; - } - -#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION - /* Bypass DATABUF write protection if configured */ - if (config->databuf_protection_bypass) { - new_ctrlb |= DAC_CTRLB_BDWP; - } -#endif - - /* Voltage pump disable if configured */ - if (config->voltage_pump_disable) { - new_ctrlb |= DAC_CTRLB_VPD; - } - - /* Apply the new configuration to the hardware module */ - dac_module->CTRLA.reg = new_ctrla; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - dac_module->CTRLB.reg = new_ctrlb; -} - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] dev_inst Pointer to the DAC software instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -bool dac_is_syncing( - struct dac_module *const dev_inst) -{ - /* Sanity check arguments */ - Assert(dev_inst); - - Dac *const dac_module = dev_inst->hw; - -#if (SAMC21) - if (dac_module->SYNCBUSY.reg) { -#else - if (dac_module->STATUS.reg & DAC_STATUS_SYNCBUSY) { -#endif - return true; - } - - return false; -} - -/** - * \brief Initializes a DAC configuration structure to defaults. - * - * Initializes a given DAC configuration structure to a set of - * known default values. This function should be called on any new - * instance of the configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li 1V from internal bandgap reference - * \li Drive the DAC output to the VOUT pin - * \li Right adjust data - * \li GCLK generator 0 (GCLK main) clock source - * \li The output buffer is disabled when the chip enters STANDBY sleep - * mode - * - * \param[out] config Configuration structure to initialize to default values - */ -void dac_get_config_defaults( - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->reference = DAC_REFERENCE_INT1V; - config->output = DAC_OUTPUT_EXTERNAL; - config->left_adjust = false; -#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION - config->databuf_protection_bypass = false; -#endif - config->voltage_pump_disable = false; - config->clock_source = GCLK_GENERATOR_0; - config->run_in_standby = false; -#if (SAMC21) - config->dither_mode = false; -#endif -} - -/** - * \brief Initialize the DAC device struct. - * - * Use this function to initialize the Digital to Analog Converter. Resets the - * underlying hardware module and configures it. - * - * \note The DAC channel must be configured separately. - * - * \param[out] module_inst Pointer to the DAC software instance struct - * \param[in] module Pointer to the DAC module instance - * \param[in] config Pointer to the config struct, created by the user - * application - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - */ -enum status_code dac_init( - struct dac_module *const module_inst, - Dac *const module, - struct dac_config *const config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module); - Assert(config); - - /* Initialize device instance */ - module_inst->hw = module; - - /* Turn on the digital interface clock */ -#if (SAMC21) - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC); -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_DAC); -#endif - - /* Check if module is enabled. */ - if (module->CTRLA.reg & DAC_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (module->CTRLA.reg & DAC_CTRLA_SWRST) { - return STATUS_BUSY; - } - - /* Configure GCLK channel and enable clock */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->clock_source; - system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(DAC_GCLK_ID); - - /* MUX the DAC VOUT pin */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - /* Set up the DAC VOUT pin */ - pin_conf.mux_position = MUX_PA02B_DAC_VOUT; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT, &pin_conf); - - /* Write configuration to module */ - _dac_set_config(module_inst, config); - - /* Store reference selection for later use */ - module_inst->reference = config->reference; - -#if DAC_CALLBACK_MODE == true - for (uint8_t i = 0; i < DAC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - }; - - _dac_instances[0] = module_inst; -#endif - - return STATUS_OK; -} - -/** - * \brief Resets the DAC module. - * - * This function will reset the DAC module to its power on default values and - * disable it. - * - * \param[in] module_inst Pointer to the DAC software instance struct - */ -void dac_reset( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Software reset the module */ - dac_module->CTRLA.reg |= DAC_CTRLA_SWRST; -} - -/** - * \brief Enable the DAC module. - * - * Enables the DAC interface and the selected output. If any internal reference - * is selected it will be enabled. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * - */ -void dac_enable( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Enable selected output */ - dac_module->CTRLB.reg |= module_inst->output; - - while (dac_is_syncing(module_inst)) { - /* Wait until the synchronization is complete */ - } - - /* Enable the module */ - dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE; - - /* Enable internal bandgap reference if selected in the configuration */ - if (module_inst->reference == DAC_REFERENCE_INT1V) { -#if (SAMC21) - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT); - } - - if(dac_module->CTRLA.reg & DAC_CTRLA_ENABLE) { - while(! (dac_module->STATUS.reg & DAC_STATUS_READY)) { - }; - } -#else - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP); - } - -#endif -} - -/** - * \brief Disable the DAC module. - * - * Disables the DAC interface and the output buffer. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * - */ -void dac_disable( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - /* Wait until the synchronization is complete */ - while (dac_is_syncing(module_inst)) { - }; - - /* Disbale interrupt */ - dac_module->INTENCLR.reg = DAC_INTENCLR_MASK; - /* Clear interrupt flag */ - dac_module->INTFLAG.reg = DAC_INTFLAG_MASK; - - /* Disable DAC */ - dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE; -} - -/** - * \brief Enables a DAC event input or output. - * - * Enables one or more input or output events to or from the DAC module. See - * \ref dac_events "dac_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the DAC peripheral - * \param[in] events Struct containing flags of events to enable - */ -void dac_enable_events( - struct dac_module *const module_inst, - struct dac_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Dac *const dac_module = module_inst->hw; - - uint32_t event_mask = 0; - -#if(SAMC21) - /* Configure Enable Inversion of input event */ - if (events->generate_event_on_chan_falling_edge) { - event_mask |= DAC_EVCTRL_INVEI; - } -#endif - - /* Configure Buffer Empty event */ - if (events->generate_event_on_buffer_empty) { - event_mask |= DAC_EVCTRL_EMPTYEO; - } - - /* Configure Conversion Start event */ - if (events->on_event_start_conversion) { - event_mask |= DAC_EVCTRL_STARTEI; - module_inst->start_on_event = true; - } - - dac_module->EVCTRL.reg |= event_mask; -} - -/** - * \brief Disables a DAC event input or output. - * - * Disables one or more input or output events to or from the DAC module. See - * \ref dac_events "dac_events" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Software instance for the DAC peripheral - * \param[in] events Struct containing flags of events to disable - */ -void dac_disable_events( - struct dac_module *const module_inst, - struct dac_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Dac *const dac_module = module_inst->hw; - - uint32_t event_mask = 0; - - /* Configure Buffer Empty event */ - if (events->generate_event_on_buffer_empty) { - event_mask |= DAC_EVCTRL_EMPTYEO; - } - - /* Configure Conversion Start event */ - if (events->on_event_start_conversion) { - event_mask |= DAC_EVCTRL_STARTEI; - module_inst->start_on_event = false; - } - - dac_module->EVCTRL.reg &= ~event_mask; -} - -/** - * \brief Initializes a DAC channel configuration structure to defaults. - * - * Initializes a given DAC channel configuration structure to a set of - * known default values. This function should be called on any new - * instance of the configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Start Conversion Event Input enabled - * \li Start Data Buffer Empty Event Output disabled - * - * \param[out] config Configuration structure to initialize to default values - */ -void dac_chan_get_config_defaults( - struct dac_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); -} - -/** - * \brief Writes a DAC channel configuration to the hardware module. - * - * Writes a given channel configuration to the hardware module. - * - * \note The DAC device instance structure must be initialized before calling - * this function. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to configure - * \param[in] config Pointer to the configuration struct - * - */ -void dac_chan_set_config( - struct dac_module *const module_inst, - const enum dac_channel channel, - struct dac_chan_config *const config) -{ - /* No channel support yet */ - UNUSED(channel); -} - -/** - * \brief Enable a DAC channel. - * - * Enables the selected DAC channel. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to enable - * - */ -void dac_chan_enable( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* No channel support yet */ - UNUSED(channel); -} - -/** - * \brief Disable a DAC channel. - * - * Disables the selected DAC channel. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Channel to disable - * - */ -void dac_chan_disable( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* No channel support yet */ - UNUSED(channel); -} - -/** - * \brief Enable the output buffer. - * - * Enables the output buffer and drives the DAC output to the VOUT pin. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel DAC channel to alter - */ -void dac_chan_enable_output_buffer( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Enable output buffer */ - dac_module->CTRLB.reg |= DAC_OUTPUT_EXTERNAL; -} - -/** - * \brief Disable the output buffer. - * - * Disables the output buffer. - * - * \note The output buffer(s) should be disabled when a channel's output is not - * currently needed, as it will draw current even if the system is in - * sleep mode. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel DAC channel to alter - */ -void dac_chan_disable_output_buffer( - struct dac_module *const module_inst, - enum dac_channel channel) -{ - /* Sanity check arguments*/ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Disable output buffer */ - dac_module->CTRLB.reg &= ~DAC_OUTPUT_EXTERNAL; -} - -/** - * \brief Write to the DAC. - * - * This function writes to the DATA or DATABUF register. - * If the conversion is not event-triggered, the data will be written to - * the DATA register and the conversion will start. - * If the conversion is event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] data Conversion data - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written - */ -enum status_code dac_chan_write( - struct dac_module *const module_inst, - enum dac_channel channel, - const uint16_t data) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Wait until the synchronization is complete */ - while (dac_is_syncing(module_inst)) { - }; - - if (module_inst->start_on_event) { - /* Write the new value to the buffered DAC data register */ - dac_module->DATABUF.reg = data; - } else { - /* Write the new value to the DAC data register */ - dac_module->DATA.reg = data; - } - - return STATUS_OK; -} - -/** - * \brief Write to the DAC. - * - * This function converts a specific number of digital data. - * The conversion should be event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] buffer Pointer to the digital data write buffer to be converted - * \param[in] length Length of the write buffer - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written or no data conversion required - * \retval STATUS_ERR_UNSUPPORTED_DEV The DAC is not configured as using event trigger - * \retval STATUS_BUSY The DAC is busy to convert - */ -enum status_code dac_chan_write_buffer_wait( - struct dac_module *const module_inst, - enum dac_channel channel, - uint16_t *buffer, - uint32_t length) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* No channel support yet */ - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* Wait until the synchronization is complete */ - while (dac_is_syncing(module_inst)) { - }; - - /* Zero length request */ - if (length == 0) { - /* No data to be converted */ - return STATUS_OK; - } - -#if DAC_CALLBACK_MODE == true - /* Check if busy */ - if (module_inst->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } -#endif - - /* Only support event triggered conversion */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Blocks while buffer is being transferred */ - while (length--) { - /* Convert one data */ - dac_chan_write(module_inst, channel, buffer[length]); - - /* Wait until Transmit is complete or timeout */ - for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) { - if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY) { - break; - } else if (i == DAC_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - } - - return STATUS_OK; -} - -/** - * \brief Retrieves the current module status - * - * Checks the status of the module and returns it as a bitmask of status - * flags. - * - * \param[in] module_inst Pointer to the DAC software device struct - * - * \return Bitmask of status flags. - * - * \retval DAC_STATUS_CHANNEL_0_EMPTY Data has been transferred from DATABUF - * to DATA by a start conversion event - * and DATABUF is ready for new data - * \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred - * when DATABUF is empty - * - */ -uint32_t dac_get_status( - struct dac_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - uint8_t intflags = dac_module->INTFLAG.reg; - uint32_t status_flags = 0; - - if (intflags & DAC_INTFLAG_EMPTY) { - status_flags |= DAC_STATUS_CHANNEL_0_EMPTY; - } - - if (intflags & DAC_INTFLAG_UNDERRUN) { - status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] status_flags Bit mask of status flags to clear - * - */ -void dac_clear_status( - struct dac_module *const module_inst, - uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Dac *const dac_module = module_inst->hw; - - uint32_t intflags = 0; - - if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) { - intflags |= DAC_INTFLAG_EMPTY; - } - - if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) { - intflags |= DAC_INTFLAG_UNDERRUN; - } - - dac_module->INTFLAG.reg = intflags; -} diff --git a/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac_callback.c b/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac_callback.c deleted file mode 100644 index d49fc09cbf27b..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac_callback.c +++ /dev/null @@ -1,435 +0,0 @@ -/** - * \file - * - * \brief SAM Digital-to-Analog Interrupt Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "dac.h" -#include "dac_callback.h" - -struct dac_module *_dac_instances[DAC_INST_NUM]; - -/** - * \brief Convert a specific number digital data to analog through DAC. - * - * This function will perform a conversion of specific number of digital data. - * The conversion should be event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] buffer Pointer to the digital data write buffer to be converted - * \param[in] length Size of the write buffer - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written - * \retval STATUS_ERR_UNSUPPORTED_DEV If a callback that requires event driven - * mode was specified with a DAC instance - * configured in non-event mode - * \retval STATUS_BUSY The DAC is busy to accept new job - */ -enum status_code dac_chan_write_buffer_job( - struct dac_module *const module_inst, - const enum dac_channel channel, - uint16_t *buffer, - uint32_t length) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(buffer); - - UNUSED(channel); - - Dac *const dac_module = module_inst->hw; - - /* DAC interrupts require it to be driven by events to work, fail if in - * unbuffered (polled) mode */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - if(module_inst->remaining_conversions != 0 || - module_inst->job_status == STATUS_BUSY){ - return STATUS_BUSY; - } - - /* Wait until the synchronization is complete */ - while (dac_is_syncing(module_inst)) { - }; - - module_inst->job_status = STATUS_BUSY; - - module_inst->remaining_conversions = length; - module_inst->job_buffer = buffer; - module_inst->transferred_conversions = 0; - - /* Enable interrupt */ - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DAC); - dac_module->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY; - dac_module->INTENSET.reg = DAC_INTENSET_UNDERRUN | DAC_INTENSET_EMPTY; - - return STATUS_OK; -} - -/** - * \brief Convert one digital data job. - * - * This function will perform a conversion of specfic number of digital data. - * The conversion is event-triggered, the data will be written to DATABUF - * and transferred to the DATA register and converted when a Start Conversion - * Event is issued. - * Conversion data must be right or left adjusted according to configuration - * settings. - * \note To be event triggered, the enable_start_on_event must be - * enabled in the configuration. - * - * \param[in] module_inst Pointer to the DAC software device struct - * \param[in] channel DAC channel to write to - * \param[in] data Digital data to be converted - * - * \return Status of the operation. - * \retval STATUS_OK If the data was written - * \retval STATUS_ERR_UNSUPPORTED_DEV If a callback that requires event driven - * mode was specified with a DAC instance - * configured in non-event mode - * \retval STATUS_BUSY The DAC is busy to accept new job - */ -enum status_code dac_chan_write_job( - struct dac_module *const module_inst, - const enum dac_channel channel, - uint16_t data) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - UNUSED(channel); - - /* DAC interrupts require it to be driven by events to work, fail if in - * unbuffered (polled) mode */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - if(module_inst->remaining_conversions != 0 || - module_inst->job_status == STATUS_BUSY){ - return STATUS_BUSY; - } - - dac_chan_write_buffer_job(module_inst, channel, &data, 1); - - return STATUS_OK; -} - -/** - * \brief Registers an asynchronous callback function with the driver. - * - * Registers an asynchronous callback with the DAC driver, fired when a callback - * condition occurs. - * - * \param[in,out] module_inst Pointer to the DAC software instance struct - * \param[in] callback Pointer to the callback function to register - * \param[in] channel Logical channel to register callback function - * \param[in] type Type of callback function to register - * - * \return Status of the registration operation. - * \retval STATUS_OK The callback was registered successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - * \retval STATUS_ERR_UNSUPPORTED_DEV If a callback that requires event driven - * mode was specified with a DAC instance - * configured in non-event mode - */ -enum status_code dac_register_callback( - struct dac_module *const module_inst, - const enum dac_channel channel, - const dac_callback_t callback, - const enum dac_callback type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(callback); - - UNUSED(channel); - - /* DAC interrupts require it to be driven by events to work, fail if in - * unbuffered (polled) mode */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - if ((uint8_t)type < DAC_CALLBACK_N) { - module_inst->callback[(uint8_t)type] = callback; - return STATUS_OK; - } - - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Unregisters an asynchronous callback function with the driver. - * - * Unregisters an asynchronous callback with the DAC driver, removing it - * from the internal callback registration table. - * - * \param[in,out] module_inst Pointer to the DAC software instance struct - * \param[in] channel Logical channel to unregister callback function - * \param[in] type Type of callback function to unregister - * - * \return Status of the de-registration operation. - * \retval STATUS_OK The callback was unregistered successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - * \retval STATUS_ERR_UNSUPPORTED_DEV If a callback that requires event driven - * mode was specified with a DAC instance - * configured in non-event mode - */ -enum status_code dac_unregister_callback( - struct dac_module *const module_inst, - const enum dac_channel channel, - const enum dac_callback type) -{ - /* Sanity check arguments */ - Assert(module_inst); - - UNUSED(channel); - - /* DAC interrupts require it to be driven by events to work, fail if in - * unbuffered (polled) mode */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - if ((uint8_t)type < DAC_CALLBACK_N) { - module_inst->callback[(uint8_t)type] = NULL; - return STATUS_OK; - } - - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Enables asynchronous callback generation for a given channel and type. - * - * Enables asynchronous callbacks for a given logical DAC channel and type. This - * must be called before a DAC channel will generate callback events. - * - * \param[in,out] dac_module Pointer to the DAC software instance struct - * \param[in] channel Logical channel to enable callback function - * \param[in] type Type of callback function callbacks to enable - * - * \return Status of the callback enable operation. - * \retval STATUS_OK The callback was enabled successfully - * \retval STATUS_ERR_UNSUPPORTED_DEV If a callback that requires event driven - * mode was specified with a DAC instance - * configured in non-event mode - */ -enum status_code dac_chan_enable_callback( - struct dac_module *const module_inst, - const enum dac_channel channel, - const enum dac_callback type) -{ - /* Sanity check arguments */ - Assert(module_inst); - - UNUSED(channel); - - /* DAC interrupts require it to be driven by events to work, fail if in - * unbuffered (polled) mode */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - module_inst->callback_enable[type] = true; - - return STATUS_OK; -} - -/** - * \brief Disables asynchronous callback generation for a given channel and type. - * - * Disables asynchronous callbacks for a given logical DAC channel and type. - * - * \param[in,out] dac_module Pointer to the DAC software instance struct - * \param[in] channel Logical channel to disable callback function - * \param[in] type Type of callback function callbacks to disable - * - * \return Status of the callback disable operation. - * \retval STATUS_OK The callback was disabled successfully - * \retval STATUS_ERR_UNSUPPORTED_DEV If a callback that requires event driven - * mode was specified with a DAC instance - * configured in non-event mode - */ -enum status_code dac_chan_disable_callback( - struct dac_module *const module_inst, - const enum dac_channel channel, - const enum dac_callback type) -{ - /* Sanity check arguments */ - Assert(module_inst); - - UNUSED(channel); - - /* DAC interrupts require it to be driven by events to work, fail if in - * unbuffered (polled) mode */ - if (module_inst->start_on_event == false) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - module_inst->callback_enable[type] = false; - - return STATUS_OK; -} - -/** \internal - * Internal handler for DAC module interrupts. - * - * \param[in] instance DAC instance number - */ -static void _dac_interrupt_handler(const uint8_t instance) -{ - struct dac_module *module = _dac_instances[instance]; - Dac *const dac_hw = module->hw; - - if (dac_hw->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) { - dac_hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; - - if ((module->callback) && - (module->callback_enable[DAC_CALLBACK_DATA_UNDERRUN])){ - module->callback[DAC_CALLBACK_DATA_UNDERRUN](0); - } - } - - if (dac_hw->INTFLAG.reg & DAC_INTFLAG_EMPTY) { - dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY; - - /* If in a write buffer job */ - if (module->remaining_conversions) { - - /* Fill the data buffer with next data in write buffer */ - dac_hw->DATABUF.reg = - module->job_buffer[module->transferred_conversions++]; - - /* Write buffer size decrement */ - module->remaining_conversions --; - - /* If in a write buffer job and all the data are converted */ - if (module->remaining_conversions == 0) { - module->job_status = STATUS_OK; - - /* Disable interrupt */ - dac_hw->INTENCLR.reg = DAC_INTENCLR_EMPTY; - dac_hw->INTFLAG.reg = DAC_INTFLAG_EMPTY; - system_interrupt_disable(SYSTEM_INTERRUPT_MODULE_DAC); - - if ((module->callback) && - (module->callback_enable[DAC_CALLBACK_TRANSFER_COMPLETE])) { - module->callback[DAC_CALLBACK_TRANSFER_COMPLETE](0); - } - } - } - - if ((module->callback) && - (module->callback_enable[DAC_CALLBACK_DATA_EMPTY])) { - module->callback[DAC_CALLBACK_DATA_EMPTY](0); - } - } -} - -/** Handler for the DAC hardware module interrupt. */ -void DAC_Handler(void) -{ - _dac_interrupt_handler(0); -} - -/** - * \brief Gets the status of a job - * - * Gets the status of an ongoing or the last job. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Logical channel to enable callback function - * - * \return Status of the job. - */ -enum status_code dac_chan_get_job_status( - struct dac_module *module_inst, - const enum dac_channel channel) -{ - /* Sanity check arguments */ - Assert(module_inst); - - UNUSED(channel); - - return module_inst->job_status; -} - -/** - * \brief Aborts an ongoing job - * - * Aborts an ongoing job. - * - * \param[in] module_inst Pointer to the DAC software instance struct - * \param[in] channel Logical channel to enable callback function - */ -void dac_chan_abort_job( - struct dac_module *module_inst, - const enum dac_channel channel) -{ - /* Sanity check arguments */ - Assert(module_inst); - - UNUSED(channel); - - /* Disable interrupt */ - module_inst->hw->INTFLAG.reg = DAC_INTFLAG_UNDERRUN | DAC_INTFLAG_EMPTY; - module_inst->hw->INTENCLR.reg = DAC_INTENCLR_UNDERRUN | DAC_INTENCLR_EMPTY; - - /* Mark job as aborted */ - module_inst->job_status = STATUS_ABORTED; - module_inst->remaining_conversions = 0; - -} diff --git a/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac_feature.h b/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac_feature.h deleted file mode 100644 index ae7ce8d657cae..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dac/dac_sam_d_c/dac_feature.h +++ /dev/null @@ -1,634 +0,0 @@ -/** - * \file - * - * \brief SAM Peripheral Digital-to-Analog Converter Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DAC_FEATURE_H_INCLUDED -#define DAC_FEATURE_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog (DAC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the conversion of - * digital values to analog voltage. The following driver API modes are covered - * by this manual: - * - * - Polled APIs - * \if DAC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - DAC (Digital-to-Analog Converter) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_dac_prerequisites - * - \ref asfdoc_sam0_dac_module_overview - * - \ref asfdoc_sam0_dac_special_considerations - * - \ref asfdoc_sam0_dac_extra_info - * - \ref asfdoc_sam0_dac_examples - * - \ref asfdoc_sam0_dac_api_overview - * - * - * \section asfdoc_sam0_dac_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_dac_module_overview Module Overview - * - * The Digital-to-Analog converter converts a digital value to analog voltage. - * The SAM DAC module has one channel with 10-bit resolution, - * and is capable of converting up to 350k samples per second (ksps). - * - * A common use of DAC is to generate audio signals by connecting the DAC - * output to a speaker, or to generate a reference voltage; either for an - * external circuit or an internal peripheral such as the Analog Comparator. - * - * After being set up, the DAC will convert new digital values written to the - * conversion data register (DATA) to an analog value either on the VOUT pin of - * the device, or internally for use as an input to the AC, ADC, and other analog - * modules. - * - * Writing the DATA register will start a new conversion. It is also possible - * to trigger the conversion from the event system. - * - * A simplified block diagram of the DAC can be seen in - * \ref asfdoc_sam0_dac_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_dac_module_block_diagram - * \image html dac_block_diagram.svg "DAC Block Diagram" - * - * \subsection asfdoc_sam0_dac_conversion_range Conversion Range - * The conversion range is between GND and the selected voltage reference. - * Available voltage references are: - * \li AVCC voltage reference - * \li Internal 1V reference (INT1V) - * \li External voltage reference (AREF) - * - * \note Internal references will be enabled by the driver, but not disabled. - * Any reference not used by the application should be disabled by the application. - * - * The output voltage from a DAC channel is given as: - * \f[ - * V_{OUT} = \frac{DATA}{0x3FF} \times VREF - * \f] - * - * \subsection asfdoc_sam0_dac_conversion Conversion - * The digital value written to the conversion data register (DATA) will be - * converted to an analog value. - * Writing the DATA register will start a new conversion. - * It is also possible to write the conversion data to the DATABUF register, - * the writing of the DATA register can then be triggered from the event - * system, which will load the value from DATABUF to DATA. - * - * \subsection asfdoc_sam0_dac_analog_output Analog Output - * The analog output value can be output to either the VOUT pin or internally, - * but not both at the same time. - * - * \subsubsection asfdoc_sam0_dac_analog_output_external External Output - * The output buffer must be enabled in order to drive the DAC output to the - * VOUT pin. Due to the output buffer, the DAC has high drive strength, and is - * capable of driving both resistive and capacitive loads, as well as loads - * which combine both. - * - * \subsubsection asfdoc_sam0_dac_analog_output_internal Internal Output - * The analog value can be internally available for use as input to the - * AC or ADC modules. - * - * \subsection asfdoc_sam0_dac_events Events - * Events generation and event actions are configurable in the DAC. - * The DAC has one event line input and one event output: Start Conversion - * and Data Buffer Empty. - * - * If the Start Conversion input event is enabled in the module configuration, - * an incoming event will load data from the data buffer to the data register - * and start a new conversion. This method synchronizes conversions with - * external events (such as those from a timer module) and ensures regular and - * fixed conversion intervals. - * - * If the Data Buffer Empty output event is enabled in the module configuration, - * events will be generated when the DAC data buffer register becomes empty and - * new data can be loaded to the buffer. - * - * \note The connection of events between modules requires the use of the event - * driver to route output event of one module to the input event of another. - * For more information on event routing, refer to the documentation - * \ref asfdoc_sam0_events_group "SAM Event System (EVENTS) Driver". - * - * \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values - * The 10-bit input value to the DAC is contained in a 16-bit register. This - * can be configured to be either left or right adjusted. In - * \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are - * shown, and the position of the most (MSB) and the least (LSB) significant bits - * are indicated. The unused bits should always be written to zero. - * - * \anchor asfdoc_sam0_dac_module_adj_modes - * \dot - * digraph { - * subgraph cluster_right { - * msbl [label="MSB", shape=none, group="msbl"]; - * lsbl [label="LSB", shape=none]; - * node [shape=none]; - * color="white"; - * reg_left [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
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DATA[9:0]
- * >]; - * msbl -> reg_left:msb:n; - * lsbl -> reg_left:lsb; - * label ="Left adjusted.\n"; - * } - * subgraph cluster_left { - * rankdir=TB; - * msb [label="MSB", shape=none]; - * lsb [label="LSB", shape=none]; - * color="white"; - * node [shape=none]; - * reg_right [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
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DATA[9:0]
- * >]; - * msb -> reg_right:msb; - * lsb -> reg_right:lsb:n; - * label = "Right adjusted.\n"; - * graph [shape=none]; - * } - * } - * \enddot - * - * \subsection asfdoc_sam0_dac_clk_sources Clock Sources - * The clock for the DAC interface (CLK_DAC) is generated by the Power Manager. - * This clock is turned on by default, and can be enabled and disabled in the - * Power Manager. - * - * Additionally, an asynchronous clock source (GCLK_DAC) is required. - * These clocks are normally disabled by default. The selected clock source - * must be enabled in the Power Manager before it can be used by the DAC. - * The DAC core operates asynchronously from the user interface and - * peripheral bus. As a consequence, the DAC needs two clock cycles of both - * CLK_DAC and GCLK_DAC to synchronize the values written to some of the - * control and data registers. - * The oscillator source for the GCLK_DAC clock is selected in the System - * Control Interface (SCIF). - * - * \section asfdoc_sam0_dac_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_dac_special_considerations_output_buffer Output Driver - * The DAC can only do conversions in Active or Idle modes. However, if the - * output buffer is enabled it will draw current even if the system is in - * sleep mode. Therefore, always make sure that the output buffer is not - * enabled when it is not needed, to ensure minimum power consumption. - * - * \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time - * DAC conversion time is approximately 2.85µs. The user must ensure that new - * data is not written to the DAC before the last conversion is complete. - * Conversions should be triggered by a periodic event from a Timer/Counter or - * another peripheral. - * - * - * \section asfdoc_sam0_dac_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_dac_extra. This includes: - * - \ref asfdoc_sam0_dac_extra_acronyms - * - \ref asfdoc_sam0_dac_extra_dependencies - * - \ref asfdoc_sam0_dac_extra_errata - * - \ref asfdoc_sam0_dac_extra_history - * - * - * \section asfdoc_sam0_dac_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_dac_exqsg. - * - * - * \section asfdoc_sam0_dac_api_overview API Overview - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - - -/** - * \name DAC Status Flags - * - * DAC status flags, returned by \ref dac_get_status() and cleared by - * \ref dac_clear_status(). - * @{ - */ - -/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF - * to DATA by a start conversion event and DATABUF is ready for new data. - */ -#define DAC_STATUS_CHANNEL_0_EMPTY (1UL << 0) - -/** Under-run Channel 0 - Set when a start conversion event occurs when - * DATABUF is empty. - */ -#define DAC_STATUS_CHANNEL_0_UNDERRUN (1UL << 1) - -/** @} */ - -/** - * \brief DAC reference voltage enum. - * - * Enum for the possible reference voltages for the DAC. - */ -enum dac_reference { - /** 1V from the internal band-gap reference*/ - DAC_REFERENCE_INT1V = DAC_CTRLB_REFSEL(0), - /** Analog VCC as reference */ - DAC_REFERENCE_AVCC = DAC_CTRLB_REFSEL(1), - /** External reference on AREF */ - DAC_REFERENCE_AREF = DAC_CTRLB_REFSEL(2), -}; - -/** - * \brief DAC output selection enum. - * - * Enum for the DAC output selection. - */ -enum dac_output { - /** DAC output to VOUT pin */ - DAC_OUTPUT_EXTERNAL = DAC_CTRLB_EOEN, - /** DAC output as internal reference */ - DAC_OUTPUT_INTERNAL = DAC_CTRLB_IOEN, - /** No output */ - DAC_OUTPUT_NONE = 0, -}; - -/** - * \brief DAC channel selection enum. - * - * Enum for the DAC channel selection. - */ -enum dac_channel { - /** DAC output channel 0 */ - DAC_CHANNEL_0, -}; - -/** - * \brief DAC software device instance structure. - * - * DAC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct dac_module { -#if !defined(__DOXYGEN__) - /** DAC hardware module */ - Dac *hw; - /** DAC output selection */ - enum dac_output output; - /** Reference selection */ - enum dac_reference reference; - /** DAC event selection */ - bool start_on_event; -# if DAC_CALLBACK_MODE == true - /** Pointer to buffer used for ADC results */ - volatile uint16_t *job_buffer; - /** Remaining number of conversions in current job */ - volatile uint16_t remaining_conversions; - /** Transferred number of conversions in current job */ - volatile uint16_t transferred_conversions; - /** DAC callback enable */ - bool callback_enable[DAC_CALLBACK_N]; - /** DAC registered callback functions */ - dac_callback_t callback[DAC_CALLBACK_N]; - /** Holds the status of the ongoing or last conversion job */ - volatile enum status_code job_status; -# endif -#endif -}; - -/** - * \brief DAC configuration structure. - * - * Configuration structure for a DAC instance. This structure should be - * initialized by the \ref dac_get_config_defaults() - * function before being modified by the user application. - */ -struct dac_config { - /** Reference voltage */ - enum dac_reference reference; - /** Select DAC output */ - enum dac_output output; - /** Left adjusted data */ - bool left_adjust; - /** GCLK generator used to clock the peripheral */ - enum gclk_generator clock_source; -#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION - /** Bypass DATABUF write protection */ - bool databuf_protection_bypass; -#endif - /** Voltage pump disable */ - bool voltage_pump_disable; - /** - * The DAC behaves as in normal mode when the chip enters STANDBY sleep - * mode - */ - bool run_in_standby; -#if (SAMC21) - /** Dither mode enable data */ - bool dither_mode; -#endif -}; - -/** - * \brief DAC event enable/disable structure. - * - * Event flags for the DAC module. This is used to enable and - * disable events via \ref dac_enable_events() and \ref dac_disable_events(). - */ -struct dac_events { - /** Start a new DAC conversion */ - bool on_event_start_conversion; - /** Enable event generation on data buffer empty */ - bool generate_event_on_buffer_empty; -#if (SAMC21) - /** Enable the falling edge of the input event for DAC1 */ - bool generate_event_on_chan_falling_edge; -#endif -}; - -/** - * \brief DAC channel configuration structure - * - * Configuration for a DAC channel. This structure should be initialized by the - * \ref dac_chan_get_config_defaults() function before being modified by the - * user application. - */ -struct dac_chan_config { -#if !defined(__DOXYGEN__) - /** Dummy value to ensure the struct has at least one member */ - uint8_t _dummy; -#endif -}; - -/** - * \name Configuration and Initialization (Channel) - * @{ - */ - -void dac_chan_enable_output_buffer( - struct dac_module *const dev_inst, - const enum dac_channel channel); - -void dac_chan_disable_output_buffer( - struct dac_module *const dev_inst, - const enum dac_channel channel); - -/** @} */ - -/** @} */ - -/** - * \page asfdoc_sam0_dac_extra Extra Information for DAC Driver - * - * \section asfdoc_sam0_dac_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ADCAnalog-to-Digital Converter
ACAnalog Comparator
DACDigital-to-Analog Converter
LSBLeast Significant Bit
MSBMost Significant Bit
DMADirect Memory Access
- * - * - * \section asfdoc_sam0_dac_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_dac_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_dac_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Add configuration for using 14-bit hardware dithering (SAMC21 support)
Added new configuration parameters \c databuf_protection_bypass, - * \c voltage_pump_disable. Added new callback functions - * \c dac_chan_write_buffer_wait, - * \c dac_chan_write_buffer_job, \c dac_chan_write_job, - * \c dac_get_job_status, \c dac_abort_job and new callback type - * \c DAC_CALLBACK_TRANSFER_COMPLETE for DAC conversion job
Initial Release
- */ - -/** - * \page asfdoc_sam0_dac_exqsg Examples for DAC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_dac_basic_use_case - * \if DAC_CALLBACK_MODE - * - \subpage asfdoc_sam0_dac_basic_use_case_callback - * \endif - * \if DAC_DMA_USE_MODE_SELECTION - * - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma - * \endif - * - * \if DAC_DMA_USE_MODE_SELECTION - * \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC - * For this examples, see - * \ref asfdoc_sam0_adc_dma_use_case - * \endif - * - * \page asfdoc_sam0_dac_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42110E09/2015Add SAM C21 and SAM DA1 support
42110D12/2014Add SAM D10/D11 support
42110C01/2014Add SAM D21 support
42110B06/2013Added additional documentation on the event system. Corrected - * documentation typos.
42110A06/2013Initial document release
- */ - -#ifdef __cplusplus -} -#endif - - -#endif /* DAC_FEATURE_H_INCLUDED */ - diff --git a/atmel-samd/asf/sam0/drivers/dac/docimg/dac_block_diagram.svg b/atmel-samd/asf/sam0/drivers/dac/docimg/dac_block_diagram.svg deleted file mode 100644 index 0b064257aee6e..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dac/docimg/dac_block_diagram.svg +++ /dev/null @@ -1,218 +0,0 @@ - - - - - - - - image/svg+xml - - - - - - - - - diff --git a/atmel-samd/asf/sam0/drivers/dac/docimg/dac_block_diagram_saml.svg b/atmel-samd/asf/sam0/drivers/dac/docimg/dac_block_diagram_saml.svg deleted file mode 100644 index 0ed3f88e790cb..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dac/docimg/dac_block_diagram_saml.svg +++ /dev/null @@ -1,1303 +0,0 @@ - - - - - - - - image/svg+xml - - - - - - - - - diff --git a/atmel-samd/asf/sam0/drivers/dma/dma.c b/atmel-samd/asf/sam0/drivers/dma/dma.c deleted file mode 100644 index 23592cda314b9..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dma/dma.c +++ /dev/null @@ -1,654 +0,0 @@ -/* - * \file - * - * \brief SAM Direct Memory Access Controller Driver - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include "dma.h" -#include "clock.h" -#include "system_interrupt.h" - -struct _dma_module { - volatile bool _dma_init; - volatile uint32_t allocated_channels; - uint8_t free_channels; -}; - -struct _dma_module _dma_inst = { - ._dma_init = false, - .allocated_channels = 0, - .free_channels = CONF_MAX_USED_CHANNEL_NUM, -}; - -/** Maximum retry counter for resuming a job transfer. */ -#define MAX_JOB_RESUME_COUNT 10000 - -/** DMA channel mask. */ -#define DMA_CHANNEL_MASK (0x1f) - -COMPILER_ALIGNED(16) -DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR; - -/** Initial write back memory section. */ -COMPILER_ALIGNED(16) -static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR; - -/** Internal DMA resource pool. */ -static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM]; - -/* DMA channel interrup flag. */ -uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]={0}; - -/** - * \brief Find a free channel for a DMA resource. - * - * Find a channel for the requested DMA resource. - * - * \return Status of channel allocation. - * \retval DMA_INVALID_CHANNEL No channel available - * \retval count Allocated channel for the DMA resource - */ -static uint8_t _dma_find_first_free_channel_and_allocate(void) -{ - uint8_t count; - uint32_t tmp; - bool allocated = false; - - system_interrupt_enter_critical_section(); - - tmp = _dma_inst.allocated_channels; - - for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) { - if (!(tmp & 0x00000001)) { - /* If free channel found, set as allocated and return - *number */ - - _dma_inst.allocated_channels |= 1 << count; - _dma_inst.free_channels--; - allocated = true; - - break; - } - - tmp = tmp >> 1; - } - - system_interrupt_leave_critical_section(); - - if (!allocated) { - return DMA_INVALID_CHANNEL; - } else { - return count; - } -} - -/** - * \brief Release an allocated DMA channel. - * - * \param[in] channel Channel id to be released - * - */ -static void _dma_release_channel(uint8_t channel) -{ - _dma_inst.allocated_channels &= ~(1 << channel); - _dma_inst.free_channels++; -} - -/** - * \brief Configure the DMA resource. - * - * \param[in] dma_resource Pointer to a DMA resource instance - * \param[out] resource_config Configurations of the DMA resource - * - */ -static void _dma_set_config(struct dma_resource *resource, - struct dma_resource_config *resource_config) -{ - Assert(resource); - Assert(resource_config); - uint32_t temp_CHCTRLB_reg; - system_interrupt_enter_critical_section(); - - /** Select the DMA channel and clear software trigger */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id)); - - temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \ - DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \ - DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action); - - - if(resource_config->event_config.input_action){ - temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT( - resource_config->event_config.input_action); - } - - /** Enable event output, the event output selection is configured in - * each transfer descriptor */ - if (resource_config->event_config.event_output_enable) { - temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE; - } - - /* Write config to CTRLB register */ - DMAC->CHCTRLB.reg = temp_CHCTRLB_reg; - - - - system_interrupt_leave_critical_section(); -} - -/** - * \brief DMA interrupt service routine. - * - */ -void DMAC_Handler( void ) -{ - uint8_t active_channel; - struct dma_resource *resource; - uint8_t isr; - uint32_t write_size; - uint32_t total_size; - - system_interrupt_enter_critical_section(); - - /* Get Pending channel */ - active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk; - - Assert(_dma_active_resource[active_channel]); - - /* Get active DMA resource based on channel */ - resource = _dma_active_resource[active_channel]; - - /* Select the active channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - isr = DMAC->CHINTFLAG.reg; - - /* Calculate block transfer size of the DMA transfer */ - total_size = descriptor_section[resource->channel_id].BTCNT.reg; - write_size = _write_back_section[resource->channel_id].BTCNT.reg; - resource->transfered_size = total_size - write_size; - - /* DMA channel interrupt handler */ - if (isr & DMAC_CHINTENCLR_TERR) { - /* Clear transfer error flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR; - - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - - /* Execute the callback function */ - if ((resource->callback_enable & (1<callback[DMA_CALLBACK_TRANSFER_ERROR])) { - resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource); - } - } else if (isr & DMAC_CHINTENCLR_TCMPL) { - /* Clear the transfer complete flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL; - - /* Set job status */ - resource->job_status = STATUS_OK; - - /* Execute the callback function */ - if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) && - (resource->callback[DMA_CALLBACK_TRANSFER_DONE])) { - resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource); - } - } else if (isr & DMAC_CHINTENCLR_SUSP) { - /* Clear channel suspend flag */ - DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP; - - /* Set job status */ - resource->job_status = STATUS_SUSPEND; - - /* Execute the callback function */ - if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) && - (resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])){ - resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource); - } - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Initializes config with predefined default values. - * - * This function will initialize a given DMA configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structure before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Software trigger is used as the transfer trigger - * \li Priority level 0 - * \li Only software/event trigger - * \li Requires a trigger for each transaction - * \li No event input /output - * \li DMA channel is disabled during sleep mode (if has the feature) - * \param[out] config Pointer to the configuration - * - */ -void dma_get_config_defaults(struct dma_resource_config *config) -{ - Assert(config); - /* Set as priority 0 */ - config->priority = DMA_PRIORITY_LEVEL_0; - /* Only software/event trigger */ - config->peripheral_trigger = 0; - /* Transaction trigger */ - config->trigger_action = DMA_TRIGGER_ACTION_TRANSACTION; - - /* Event configurations, no event input/output */ - config->event_config.input_action = DMA_EVENT_INPUT_NOACT; - config->event_config.event_output_enable = false; -#ifdef FEATURE_DMA_CHANNEL_STANDBY - config->run_in_standby = false; -#endif -} - -/** - * \brief Allocate a DMA with configurations. - * - * This function will allocate a proper channel for a DMA transfer request. - * - * \param[in,out] dma_resource Pointer to a DMA resource instance - * \param[in] transfer_config Configurations of the DMA transfer - * - * \return Status of the allocation procedure. - * - * \retval STATUS_OK The DMA resource was allocated successfully - * \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed - */ -enum status_code dma_allocate(struct dma_resource *resource, - struct dma_resource_config *config) -{ - uint8_t new_channel; - - Assert(resource); - - system_interrupt_enter_critical_section(); - - if (!_dma_inst._dma_init) { - /* Initialize clocks for DMA */ -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC); -#else - system_ahb_clock_set_mask(PM_AHBMASK_DMAC); - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, - PM_APBBMASK_DMAC); -#endif - - /* Perform a software reset before enable DMA controller */ - DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC->CTRL.reg = DMAC_CTRL_SWRST; - - /* Setup descriptor base address and write back section base - * address */ - DMAC->BASEADDR.reg = (uint32_t)descriptor_section; - DMAC->WRBADDR.reg = (uint32_t)_write_back_section; - - /* Enable all priority level at the same time */ - DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf); - - _dma_inst._dma_init = true; - } - - /* Find the proper channel */ - new_channel = _dma_find_first_free_channel_and_allocate(); - - /* If no channel available, return not found */ - if (new_channel == DMA_INVALID_CHANNEL) { - system_interrupt_leave_critical_section(); - - return STATUS_ERR_NOT_FOUND; - } - - /* Set the channel */ - resource->channel_id = new_channel; - - /** Perform a reset for the allocated channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST; - -#ifdef FEATURE_DMA_CHANNEL_STANDBY - if(config->run_in_standby){ - DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - } -#endif - - /** Configure the DMA control,channel registers and descriptors here */ - _dma_set_config(resource, config); - - resource->descriptor = NULL; - - /* Log the DMA resource into the internal DMA resource pool */ - _dma_active_resource[resource->channel_id] = resource; - - system_interrupt_leave_critical_section(); - - return STATUS_OK; -} - -/** - * \brief Free an allocated DMA resource. - * - * This function will free an allocated DMA resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - * \return Status of the free procedure. - * - * \retval STATUS_OK The DMA resource was freed successfully - * \retval STATUS_BUSY The DMA resource was busy and can't be freed - * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized - */ -enum status_code dma_free(struct dma_resource *resource) -{ - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - /* Check if channel is busy */ - if (dma_is_busy(resource)) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Check if DMA resource was not allocated */ - if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) { - system_interrupt_leave_critical_section(); - return STATUS_ERR_NOT_INITIALIZED; - } - - /* Release the DMA resource */ - _dma_release_channel(resource->channel_id); - - /* Reset the item in the DMA resource pool */ - _dma_active_resource[resource->channel_id] = NULL; - - system_interrupt_leave_critical_section(); - - return STATUS_OK; -} - -/** - * \brief Start a DMA transfer. - * - * This function will start a DMA transfer through an allocated DMA resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - * \return Status of the transfer start procedure. - * - * \retval STATUS_OK The transfer was started successfully - * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started - * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started - */ -enum status_code dma_start_transfer_job(struct dma_resource *resource) -{ - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - /* Check if resource was busy */ - if (resource->job_status == STATUS_BUSY) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Check if transfer size is valid */ - if (resource->descriptor->BTCNT.reg == 0) { - system_interrupt_leave_critical_section(); - return STATUS_ERR_INVALID_ARG; - } - - /* Enable DMA interrupt */ - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA); - - /* Set the interrupt flag */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]); - /* Set job status */ - resource->job_status = STATUS_BUSY; - - /* Set channel x descriptor 0 to the descriptor base address */ - memcpy(&descriptor_section[resource->channel_id], resource->descriptor, - sizeof(DmacDescriptor)); - - /* Enable the transfer channel */ - DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - - system_interrupt_leave_critical_section(); - - return STATUS_OK; -} - -/** - * \brief Abort a DMA transfer. - * - * This function will abort a DMA transfer. The DMA channel used for the DMA - * resource will be disabled. - * The block transfer count will also be calculated and written to the DMA - * resource structure. - * - * \note The DMA resource will not be freed after calling this function. - * The function \ref dma_free() can be used to free an allocated resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - */ -void dma_abort_job(struct dma_resource *resource) -{ - uint32_t write_size; - uint32_t total_size; - - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLA.reg = 0; - - system_interrupt_leave_critical_section(); - - /* Get transferred size */ - total_size = descriptor_section[resource->channel_id].BTCNT.reg; - write_size = _write_back_section[resource->channel_id].BTCNT.reg; - resource->transfered_size = total_size - write_size; - - resource->job_status = STATUS_ABORTED; -} - -/** - * \brief Suspend a DMA transfer. - * - * This function will request to suspend the transfer of the DMA resource. - * The channel is kept enabled, can receive transfer triggers (the transfer - * pending bit will be set), but will be removed from the arbitration scheme. - * The channel operation can be resumed by calling \ref dma_resume_job(). - * - * \note This function sets the command to suspend the DMA channel - * associated with a DMA resource. The channel suspend interrupt flag - * indicates whether the transfer is truly suspended. - * - * \param[in] resource Pointer to the DMA resource - * - */ -void dma_suspend_job(struct dma_resource *resource) -{ - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - system_interrupt_enter_critical_section(); - - /* Select the channel */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - - /* Send the suspend request */ - DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Resume a suspended DMA transfer. - * - * This function try to resume a suspended transfer of a DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * - */ -void dma_resume_job(struct dma_resource *resource) -{ - uint32_t bitmap_channel; - uint32_t count = 0; - - Assert(resource); - Assert(resource->channel_id != DMA_INVALID_CHANNEL); - - /* Get bitmap of the allocated DMA channel */ - bitmap_channel = (1 << resource->channel_id); - - /* Check if channel was suspended */ - if (resource->job_status != STATUS_SUSPEND) { - return; - } - - system_interrupt_enter_critical_section(); - - /* Send resume request */ - DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id); - DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME; - - system_interrupt_leave_critical_section(); - - /* Check if transfer job resumed */ - for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) { - if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) { - break; - } - } - - if (count < MAX_JOB_RESUME_COUNT) { - /* Job resumed */ - resource->job_status = STATUS_BUSY; - } else { - /* Job resume timeout */ - resource->job_status = STATUS_ERR_TIMEOUT; - } -} - -/** - * \brief Create a DMA transfer descriptor with configurations. - * - * This function will set the transfer configurations to the DMA transfer - * descriptor. - * - * \param[in] descriptor Pointer to the DMA transfer descriptor - * \param[in] config Pointer to the descriptor configuration structure - * - */ -void dma_descriptor_create(DmacDescriptor* descriptor, - struct dma_descriptor_config *config) -{ - /* Set block transfer control */ - descriptor->BTCTRL.bit.VALID = config->descriptor_valid; - descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection; - descriptor->BTCTRL.bit.BLOCKACT = config->block_action; - descriptor->BTCTRL.bit.BEATSIZE = config->beat_size; - descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable; - descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable; - descriptor->BTCTRL.bit.STEPSEL = config->step_selection; - descriptor->BTCTRL.bit.STEPSIZE = config->step_size; - - /* Set transfer size, source address and destination address */ - descriptor->BTCNT.reg = config->block_transfer_count; - descriptor->SRCADDR.reg = config->source_address; - descriptor->DSTADDR.reg = config->destination_address; - - /* Set next transfer descriptor address */ - descriptor->DESCADDR.reg = config->next_descriptor_address; -} - -/** - * \brief Add a DMA transfer descriptor to a DMA resource. - * - * This function will add a DMA transfer descriptor to a DMA resource. - * If there was a transfer descriptor already allocated to the DMA resource, - * the descriptor will be linked to the next descriptor address. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] descriptor Pointer to the transfer descriptor - * - * \retval STATUS_OK The descriptor is added to the DMA resource - * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added - */ -enum status_code dma_add_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor) -{ - DmacDescriptor* desc = resource->descriptor; - - if (resource->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } - - /* Look up for an empty space for the descriptor */ - if (desc == NULL) { - resource->descriptor = descriptor; - } else { - /* Looking for end of descriptor link */ - while(desc->DESCADDR.reg != 0) { - desc = (DmacDescriptor*)(desc->DESCADDR.reg); - } - - /* Set to the end of descriptor list */ - desc->DESCADDR.reg = (uint32_t)descriptor; - } - - return STATUS_OK; -} diff --git a/atmel-samd/asf/sam0/drivers/dma/dma.h b/atmel-samd/asf/sam0/drivers/dma/dma.h deleted file mode 100644 index 1cf3498d955c2..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dma/dma.h +++ /dev/null @@ -1,882 +0,0 @@ -/** - * \file - * - * \brief SAM Direct Memory Access Controller Driver - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DMA_H_INCLUDED -#define DMA_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_dma_group SAM Direct Memory Access Controller (DMAC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the Direct Memory Access Controller(DMAC) module within - * the device. The DMAC can transfer data between memories and peripherals, and - * thus off-load these tasks from the CPU. The module supports peripheral to - * peripheral, peripheral to memory, memory to peripheral, and memory to memory - * transfers. - * - * The following peripheral is used by the DMAC Driver: - * - DMAC (Direct Memory Access Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - Atmel | SMART SAM R30 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_dma_prerequisites - * - \ref asfdoc_sam0_dma_module_overview - * - \ref asfdoc_sam0_dma_special_considerations - * - \ref asfdoc_sam0_dma_extra_info - * - \ref asfdoc_sam0_dma_examples - * - \ref asfdoc_sam0_dma_api_overview - * - * - * \section asfdoc_sam0_dma_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_dma_module_overview Module Overview - * - * SAM devices with DMAC enables high data transfer rates with minimum - * CPU intervention and frees up CPU time. With access to all peripherals, - * the DMAC can handle automatic transfer of data to/from modules. - * It supports static and incremental addressing for both source and - * destination. - * - * The DMAC when used with Event System or peripheral triggers, provides a - * considerable advantage by reducing the power consumption and performing - * data transfer in the background. - * For example, if the ADC is configured to generate an event, it can trigger - * the DMAC to transfer the data into another peripheral or SRAM. - * The CPU can remain in sleep during this time to reduce the power consumption. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
DeviceDma channel number
SAM D21/R21/C20/C2112
SAM D09/D10/D116
SAM L21,SAMR3016
- * The DMA channel operation can be suspended at any time by software, by events - * from event system, or after selectable descriptor execution. The operation - * can be resumed by software or by events from the event system. - * The DMAC driver for SAM supports four types of transfers such as - * peripheral to peripheral, peripheral to memory, memory to peripheral, and - * memory to memory. - * - * The basic transfer unit is a beat, which is defined as a single bus access. - * There can be multiple beats in a single block transfer and multiple block - * transfers in a DMA transaction. - * DMA transfer is based on descriptors, which holds transfer properties - * such as the source and destination addresses, transfer counter, and other - * additional transfer control information. - * The descriptors can be static or linked. When static, a single block transfer - * is performed. When linked, a number of transfer descriptors can be used to - * enable multiple block transfers within a single DMA transaction. - * - * The implementation of the DMA driver is based on the idea that the DMA channel - * is a finite resource of entities with the same abilities. A DMA channel resource - * is able to move a defined set of data from a source address to destination - * address triggered by a transfer trigger. On the SAM devices there are 12 - * DMA resources available for allocation. Each of these DMA resources can trigger - * interrupt callback routines and peripheral events. - * The other main features are: - * - * - Selectable transfer trigger source - * - Software - * - Event System - * - Peripheral - * - Event input and output is supported for the four lower channels - * - Four level channel priority - * - Optional interrupt generation on transfer complete, channel error, or channel suspend - * - Supports multi-buffer or circular buffer mode by linking multiple descriptors - * - Beat size configurable as 8-bit, 16-bit, or 32-bit - * - * A simplified block diagram of the DMA Resource can be seen in - * \ref asfdoc_sam0_dma_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_dma_module_block_diagram - * \dot - * digraph overview { - * splines = false; - * rankdir=LR; - * - * mux1 [label="Transfer Trigger", shape=box]; - * - * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1]; - * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue]; - * - * mux1 -> dma; - * descriptor -> dma; - * - * interrupt [label="Interrupt", shape=box]; - * events [label="Events", shape=box]; - * - * dma:e -> interrupt:w; - * dma:e -> events:w; - * - * {rank=same; descriptor dma} - * - * } - * \enddot - * - * \subsection asfdoc_sam0_dma_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_DMA_CHANNEL_STANDBYSAM L21/L22/C20/C21/R30
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_dma_module_overview_dma_transf_term Terminology Used in DMAC Transfers - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Name Description
Beat It is a single bus access by the DMAC. - * Configurable as 8-bit, 16-bit, or 32-bit. - *
Burst It is a transfer of n-beats (n=1,4,8,16). - * For the DMAC module in SAM, the burst size is one beat. - * Arbitration takes place each time a burst transfer is completed. - *
Block transfer A single block transfer is a configurable number of (1 to 64k) - * beat transfers - *
- * - * \subsection asfdoc_sam0_dma_module_overview_dma_channels DMA Channels - * The DMAC in each device consists of several DMA channels, which - * along with the transfer descriptors defines the data transfer properties. - * - The transfer control descriptor defines the source and destination - * addresses, source and destination address increment settings, the - * block transfer count, and event output condition selection - * - Dedicated channel registers control the peripheral trigger source, - * trigger mode settings, event input actions, and channel priority level - * settings - * - * With a successful DMA resource allocation, a dedicated - * DMA channel will be assigned. The channel will be occupied until the - * DMA resource is freed. A DMA resource handle is used to identify the specific - * DMA resource. - * When there are multiple channels with active requests, the arbiter prioritizes - * the channels requesting access to the bus. - * - * \subsection asfdoc_sam0_dma_module_overview_dma_trigger DMA Triggers - * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A - * transfer request can be triggered from software, peripheral, or an event. There - * are dedicated source trigger selections for each DMA channel usage. - - * - * \subsection asfdoc_sam0_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor - * The transfer descriptor resides in the SRAM and - * defines these channel properties. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Field name Field width
Descriptor Next Address 32 bits
Destination Address 32 bits
Source Address 32 bits
Block Transfer Counter 16 bits
Block Transfer Control 16 bits
- * - * Before starting a transfer, at least one descriptor should be configured. - * After a successful allocation of a DMA channel, the transfer descriptor can - * be added with a call to \ref dma_add_descriptor(). If there is a transfer - * descriptor already allocated to the DMA resource, the descriptor will - * be linked to the next descriptor address. - * - * \subsection asfdoc_sam0_dma_module_overview_dma_output DMA Interrupts/Events - * Both an interrupt callback and an peripheral event can be triggered by the - * DMA transfer. Three types of callbacks are supported by the DMA driver: - * transfer complete, channel suspend, and transfer error. Each of these callback - * types can be registered and enabled for each channel independently through - * the DMA driver API. - * - * The DMAC module can also generate events on transfer complete. Event - * generation is enabled through the DMA channel, event channel configuration, - * and event user multiplexing is done through the events driver. - * - * The DMAC can generate events in the below cases: - * - * - When a block transfer is complete - * - * - When each beat transfer within a block transfer is complete - * - * \section asfdoc_sam0_dma_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_sam0_dma_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_dma_extra. This includes: - * - \ref asfdoc_sam0_dma_extra_acronyms - * - \ref asfdoc_sam0_dma_extra_dependencies - * - \ref asfdoc_sam0_dma_extra_errata - * - \ref asfdoc_sam0_dma_extra_history - * - * - * \section asfdoc_sam0_dma_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_dma_exqsg. - * - * - * \section asfdoc_sam0_dma_api_overview API Overview - * @{ - */ - -#include -#include "conf_dma.h" - -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__) -#define FEATURE_DMA_CHANNEL_STANDBY -#endif - -/** DMA invalid channel number. */ -#define DMA_INVALID_CHANNEL 0xff - -/** ExInitial description section. */ -extern DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM]; - -/* DMA channel interrup flag. */ -extern uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]; - -/** DMA priority level. */ -enum dma_priority_level { - /** Priority level 0. */ - DMA_PRIORITY_LEVEL_0, - /** Priority level 1. */ - DMA_PRIORITY_LEVEL_1, - /** Priority level 2. */ - DMA_PRIORITY_LEVEL_2, - /** Priority level 3. */ - DMA_PRIORITY_LEVEL_3, -}; - -/** DMA input actions. */ -enum dma_event_input_action { - /** No action. */ - DMA_EVENT_INPUT_NOACT, - /** Normal transfer and periodic transfer trigger. */ - DMA_EVENT_INPUT_TRIG, - /** Conditional transfer trigger. */ - DMA_EVENT_INPUT_CTRIG, - /** Conditional block transfer. */ - DMA_EVENT_INPUT_CBLOCK, - /** Channel suspend operation. */ - DMA_EVENT_INPUT_SUSPEND, - /** Channel resume operation. */ - DMA_EVENT_INPUT_RESUME, - /** Skip next block suspend action. */ - DMA_EVENT_INPUT_SSKIP, -}; - -/** - * Address increment step size. These bits select the address increment step - * size. The setting apply to source or destination address, depending on - * STEPSEL setting. - */ -enum dma_address_increment_stepsize { - /** The address is incremented by (beat size * 1). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_1 = 0, - /** The address is incremented by (beat size * 2). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_2, - /** The address is incremented by (beat size * 4). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_4, - /** The address is incremented by (beat size * 8). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_8, - /** The address is incremented by (beat size * 16). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_16, - /** The address is incremented by (beat size * 32). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_32, - /** The address is incremented by (beat size * 64). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_64, - /** The address is incremented by (beat size * 128). */ - DMA_ADDRESS_INCREMENT_STEP_SIZE_128, -}; - -/** - * DMA step selection. This bit determines whether the step size setting - * is applied to source or destination address. - */ -enum dma_step_selection { - /** Step size settings apply to the destination address. */ - DMA_STEPSEL_DST = 0, - /** Step size settings apply to the source address. */ - DMA_STEPSEL_SRC, -}; - -/** The basic transfer unit in DMAC is a beat, which is defined as a - * single bus access. Its size is configurable and applies to both read - * and write. */ -enum dma_beat_size { - /** 8-bit access. */ - DMA_BEAT_SIZE_BYTE = 0, - /** 16-bit access. */ - DMA_BEAT_SIZE_HWORD, - /** 32-bit access. */ - DMA_BEAT_SIZE_WORD, -}; - -/** - * Block action definitions. - */ -enum dma_block_action { - /** No action. */ - DMA_BLOCK_ACTION_NOACT = 0, - /** Channel in normal operation and sets transfer complete interrupt flag - * after block transfer. */ - DMA_BLOCK_ACTION_INT, - /** Trigger channel suspend after block transfer and sets channel - * suspend interrupt flag once the channel is suspended. */ - DMA_BLOCK_ACTION_SUSPEND, - /** Sets transfer complete interrupt flag after a block transfer and - * trigger channel suspend. The channel suspend interrupt flag will be set - * once the channel is suspended. */ - DMA_BLOCK_ACTION_BOTH, -}; - -/** Event output selection. */ -enum dma_event_output_selection { - /** Event generation disable. */ - DMA_EVENT_OUTPUT_DISABLE = 0, - /** Event strobe when block transfer complete. */ - DMA_EVENT_OUTPUT_BLOCK, - /** Event output reserved. */ - DMA_EVENT_OUTPUT_RESERVED, - /** Event strobe when beat transfer complete. */ - DMA_EVENT_OUTPUT_BEAT, -}; - -/** DMA trigger action type. */ -enum dma_transfer_trigger_action{ - /** Perform a block transfer when triggered. */ - DMA_TRIGGER_ACTION_BLOCK = DMAC_CHCTRLB_TRIGACT_BLOCK_Val, - /** Perform a beat transfer when triggered. */ - DMA_TRIGGER_ACTION_BEAT = DMAC_CHCTRLB_TRIGACT_BEAT_Val, - /** Perform a transaction when triggered. */ - DMA_TRIGGER_ACTION_TRANSACTION = DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val, -}; - -/** - * Callback types for DMA callback driver. - */ -enum dma_callback_type { - /** Callback for any of transfer errors. A transfer error is flagged - * if a bus error is detected during an AHB access or when the DMAC - * fetches an invalid descriptor. */ - DMA_CALLBACK_TRANSFER_ERROR, - /** Callback for transfer complete. */ - DMA_CALLBACK_TRANSFER_DONE, - /** Callback for channel suspend. */ - DMA_CALLBACK_CHANNEL_SUSPEND, - /** Number of available callbacks. */ - DMA_CALLBACK_N, -}; - -/** - * DMA transfer descriptor configuration. When the source or destination address - * increment is enabled, the addresses stored into the configuration structure - * must correspond to the end of the transfer. - * - */ -struct dma_descriptor_config { - /** Descriptor valid flag used to identify whether a descriptor is - valid or not */ - bool descriptor_valid; - /** This is used to generate an event on specific transfer action in - a channel. Supported only in four lower channels. */ - enum dma_event_output_selection event_output_selection; - /** Action taken when a block transfer is completed */ - enum dma_block_action block_action; - /** Beat size is configurable as 8-bit, 16-bit, or 32-bit */ - enum dma_beat_size beat_size; - /** Used for enabling the source address increment */ - bool src_increment_enable; - /** Used for enabling the destination address increment */ - bool dst_increment_enable; - /** This bit selects whether the source or destination address is - using the step size settings */ - enum dma_step_selection step_selection; - /** The step size for source/destination address increment. - The next address is calculated - as next_addr = addr + (2^step_size * beat size). */ - enum dma_address_increment_stepsize step_size; - /** It is the number of beats in a block. This count value is - * decremented by one after each beat data transfer. */ - uint16_t block_transfer_count; - /** Transfer source address */ - uint32_t source_address; - /** Transfer destination address */ - uint32_t destination_address; - /** Set to zero for static descriptors. This must have a valid memory - address for linked descriptors. */ - uint32_t next_descriptor_address; -}; - -/** Configurations for DMA events. */ -struct dma_events_config { - /** Event input actions */ - enum dma_event_input_action input_action; - /** Enable DMA event output */ - bool event_output_enable; -}; - -/** DMA configurations for transfer. */ -struct dma_resource_config { - /** DMA transfer priority */ - enum dma_priority_level priority; - /**DMA peripheral trigger index */ - uint8_t peripheral_trigger; - /** DMA trigger action */ - enum dma_transfer_trigger_action trigger_action; -#ifdef FEATURE_DMA_CHANNEL_STANDBY - /** Keep DMA channel enabled in standby sleep mode if true */ - bool run_in_standby; -#endif - /** DMA events configurations */ - struct dma_events_config event_config; -}; - -/** Forward definition of the DMA resource. */ -struct dma_resource; -/** Type definition for a DMA resource callback function. */ -typedef void (*dma_callback_t)(struct dma_resource *const resource); - -/** Structure for DMA transfer resource. */ -struct dma_resource { - /** Allocated DMA channel ID */ - uint8_t channel_id; - /** Array of callback functions for DMA transfer job */ - dma_callback_t callback[DMA_CALLBACK_N]; - /** Bit mask for enabled callbacks */ - uint8_t callback_enable; - /** Status of the last job */ - volatile enum status_code job_status; - /** Transferred data size */ - uint32_t transfered_size; - /** DMA transfer descriptor */ - DmacDescriptor* descriptor; -}; - -/** - * \brief Get DMA resource status. - * - * \param[in] resource Pointer to the DMA resource - * - * \return Status of the DMA resource. - */ -static inline enum status_code dma_get_job_status(struct dma_resource *resource) -{ - Assert(resource); - - return resource->job_status; -} - -/** - * \brief Check if the given DMA resource is busy. - * - * \param[in] resource Pointer to the DMA resource - * - * \return Status which indicates whether the DMA resource is busy. - * - * \retval true The DMA resource has an on-going transfer - * \retval false The DMA resource is not busy - */ -static inline bool dma_is_busy(struct dma_resource *resource) -{ - Assert(resource); - - return (resource->job_status == STATUS_BUSY); -} - -/** - * \brief Enable a callback function for a dedicated DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_enable_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - Assert(resource); - - resource->callback_enable |= 1 << type; - g_chan_interrupt_flag[resource->channel_id] |= (1UL << type); -} - -/** - * \brief Disable a callback function for a dedicated DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_disable_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - Assert(resource); - - resource->callback_enable &= ~(1 << type); - g_chan_interrupt_flag[resource->channel_id] &= (~(1UL << type) & DMAC_CHINTENSET_MASK); - DMAC->CHINTENCLR.reg = (1UL << type); -} - -/** - * \brief Register a callback function for a dedicated DMA resource. - * - * There are three types of callback functions, which can be registered: - * - Callback for transfer complete - * - Callback for transfer error - * - Callback for channel suspend - * - * \param[in] resource Pointer to the DMA resource - * \param[in] callback Pointer to the callback function - * \param[in] type Callback function type - * - */ -static inline void dma_register_callback(struct dma_resource *resource, - dma_callback_t callback, enum dma_callback_type type) -{ - Assert(resource); - - resource->callback[type] = callback; -} - -/** - * \brief Unregister a callback function for a dedicated DMA resource. - * - * There are three types of callback functions: - * - Callback for transfer complete - * - Callback for transfer error - * - Callback for channel suspend - * - * The application can unregister any of the callback functions which - * are already registered and are no longer needed. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_unregister_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - Assert(resource); - - resource->callback[type] = NULL; -} - -/** - * \brief Will set a software trigger for resource. - * - * This function is used to set a software trigger on the DMA channel - * associated with resource. If a trigger is already pending no new trigger - * will be generated for the channel. - * - * \param[in] resource Pointer to the DMA resource - */ -static inline void dma_trigger_transfer(struct dma_resource *resource) { - Assert(resource); - - DMAC->SWTRIGCTRL.reg |= (1 << resource->channel_id); -} - -/** - * \brief Initializes DMA transfer configuration with predefined default values. - * - * This function will initialize a given DMA descriptor configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structure before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Set the descriptor as valid - * \li Disable event output - * \li No block action - * \li Set beat size as byte - * \li Enable source increment - * \li Enable destination increment - * \li Step size is applied to the destination address - * \li Address increment is beat size multiplied by 1 - * \li Default transfer size is set to 0 - * \li Default source address is set to NULL - * \li Default destination address is set to NULL - * \li Default next descriptor not available - * \param[out] config Pointer to the configuration - * - */ -static inline void dma_descriptor_get_config_defaults(struct dma_descriptor_config *config) -{ - Assert(config); - - /* Set descriptor as valid */ - config->descriptor_valid = true; - /* Disable event output */ - config->event_output_selection = DMA_EVENT_OUTPUT_DISABLE; - /* No block action */ - config->block_action = DMA_BLOCK_ACTION_NOACT; - /* Set beat size to one byte */ - config->beat_size = DMA_BEAT_SIZE_BYTE; - /* Enable source increment */ - config->src_increment_enable = true; - /* Enable destination increment */ - config->dst_increment_enable = true; - /* Step size is applied to the destination address */ - config->step_selection = DMA_STEPSEL_DST; - /* Address increment is beat size multiplied by 1*/ - config->step_size = DMA_ADDRESS_INCREMENT_STEP_SIZE_1; - /* Default transfer size is set to 0 */ - config->block_transfer_count = 0; - /* Default source address is set to NULL */ - config->source_address = (uint32_t)NULL; - /* Default destination address is set to NULL */ - config->destination_address = (uint32_t)NULL; - /** Next descriptor address set to 0 */ - config->next_descriptor_address = 0; -} - -/** - * \brief Update DMA descriptor. - * - * This function can update the descriptor of an allocated DMA resource. - * - */ -static inline void dma_update_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor) -{ - Assert(resource); - - resource->descriptor = descriptor; -} - -/** - * \brief Reset DMA descriptor. - * - * This function will clear the DESCADDR register of an allocated DMA resource. - * - */ -static inline void dma_reset_descriptor(struct dma_resource *resource) -{ - Assert(resource); - - resource->descriptor = NULL; -} - -void dma_get_config_defaults(struct dma_resource_config *config); -enum status_code dma_allocate(struct dma_resource *resource, - struct dma_resource_config *config); -enum status_code dma_free(struct dma_resource *resource); -enum status_code dma_start_transfer_job(struct dma_resource *resource); -void dma_abort_job(struct dma_resource *resource); -void dma_suspend_job(struct dma_resource *resource); -void dma_resume_job(struct dma_resource *resource); -void dma_descriptor_create(DmacDescriptor* descriptor, - struct dma_descriptor_config *config); -enum status_code dma_add_descriptor(struct dma_resource *resource, - DmacDescriptor* descriptor); - -/** @} */ - -/** - * \page asfdoc_sam0_dma_extra Extra Information for DMAC Driver - * - * \section asfdoc_sam0_dma_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DMADirect Memory Access
DMACDirect Memory Access Controller
CPUCentral Processing Unit
- * - * - * \section asfdoc_sam0_dma_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_clock_group "System Clock Driver" - * - * - * \section asfdoc_sam0_dma_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_dma_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Add SAM C21 support
Add SAM L21 support
Add SAM R30 support
Initial Release
- */ - - /** - * \page asfdoc_sam0_dma_exqsg Examples for DMAC Driver - * - * This is a list of the available Quick Start Guides (QSGs) and example - * applications for \ref asfdoc_sam0_dma_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_dma_basic_use_case - * - * \note More DMA usage examples are available in peripheral QSGs. - * A quick start guide for TC/TCC - * shows the usage of DMA event trigger; SERCOM SPI/USART/I2C has example for - * DMA transfer from peripheral to memory or from memory to peripheral; - * ADC/DAC shows peripheral to peripheral transfer. - * - * \page asfdoc_sam0_dma_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42257C12/2015Added suppport for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1
42257B12/2014Added support for SAM R21 and SAM D10/D11
42257A02/2014Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* DMA_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/dma/dma_crc.h b/atmel-samd/asf/sam0/drivers/dma/dma_crc.h deleted file mode 100644 index 3d8c27c197d57..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dma/dma_crc.h +++ /dev/null @@ -1,230 +0,0 @@ -/** - * \file - * - * \brief SAM DMA cyclic redundancy check (CRC) Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DMA_CRC_H_INCLUDED -#define DMA_CRC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** DMA channel n offset. */ -#define DMA_CRC_CHANNEL_N_OFFSET 0x20 - -/** CRC Polynomial Type. */ -enum crc_polynomial_type { - /** CRC16 (CRC-CCITT). */ - CRC_TYPE_16, - /** CRC32 (IEEE 802.3). */ - CRC_TYPE_32, -}; - -/** CRC Beat Type. */ -enum crc_beat_size { - /** Byte bus access. */ - CRC_BEAT_SIZE_BYTE, - /** Half-word bus access. */ - CRC_BEAT_SIZE_HWORD, - /** Word bus access. */ - CRC_BEAT_SIZE_WORD, -}; - -/** Configurations for CRC calculation. */ -struct dma_crc_config { - /** CRC polynomial type. */ - enum crc_polynomial_type type; - /** CRC beat size. */ - enum crc_beat_size size; -}; - -/** - * \brief Get DMA CRC default configurations. - * - * The default configuration is as follows: - * \li Polynomial type is set to CRC-16(CRC-CCITT) - * \li CRC Beat size: BYTE - * - * \param[in] config default configurations - */ -static inline void dma_crc_get_config_defaults(struct dma_crc_config *config) -{ - Assert(config); - - config->type = CRC_TYPE_16; - config->size = CRC_BEAT_SIZE_BYTE; -} - -/** - * \brief Enable DMA CRC module with an DMA channel. - * - * This function enables a CRC calculation with an allocated DMA channel. This channel ID - * can be gotten from a successful \ref dma_allocate. - * - * \param[in] channel_id DMA channel expected with CRC calculation - * \param[in] config CRC calculation configurations - * - * \return Status of the DMC CRC. - * \retval STATUS_OK Get the DMA CRC module - * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet - */ -static inline enum status_code dma_crc_channel_enable(uint32_t channel_id, - struct dma_crc_config *config) -{ - if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { - return STATUS_BUSY; - } - - DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | - DMAC_CRCCTRL_CRCPOLY(config->type) | - DMAC_CRCCTRL_CRCSRC(channel_id+DMA_CRC_CHANNEL_N_OFFSET); - - DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; - - return STATUS_OK; -} - -/** - * \brief Disable DMA CRC module. - * - */ -static inline void dma_crc_disable(void) -{ - DMAC->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; - DMAC->CRCCTRL.reg = 0; -} - -/** - * \brief Get DMA CRC checksum value. - * - * \return Calculated CRC checksum. - */ -static inline uint32_t dma_crc_get_checksum(void) -{ - if (DMAC->CRCCTRL.bit.CRCSRC == DMAC_CRCCTRL_CRCSRC_IO_Val) { - DMAC->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - } - - return DMAC->CRCCHKSUM.reg; -} - -/** - * \brief Enable DMA CRC module with I/O. - * - * This function enables a CRC calculation with I/O mode. - * - * \param[in] config CRC calculation configurations. - * - * \return Status of the DMC CRC. - * \retval STATUS_OK Get the DMA CRC module - * \retval STATUS_BUSY DMA CRC module is already taken and not ready yet - */ -static inline enum status_code dma_crc_io_enable( - struct dma_crc_config *config) -{ - if (DMAC->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) { - return STATUS_BUSY; - } - - if (DMAC->CTRL.reg & DMAC_CTRL_CRCENABLE) { - return STATUS_BUSY; - } - - DMAC->CRCCTRL.reg = DMAC_CRCCTRL_CRCBEATSIZE(config->size) | - DMAC_CRCCTRL_CRCPOLY(config->type) | - DMAC_CRCCTRL_CRCSRC_IO; - - if (config->type == CRC_TYPE_32) { - DMAC->CRCCHKSUM.reg = 0xFFFFFFFF; - } - - DMAC->CTRL.reg |= DMAC_CTRL_CRCENABLE; - - return STATUS_OK; -} - -/** - * \brief Calculate CRC with I/O. - * - * This function calculate the CRC of the input data buffer. - * - * \param[in] buffer CRC Pointer to calculation buffer - * \param[in] total_beat_size Total beat size to be calculated - * - * \return Calculated CRC checksum value. - */ -static inline void dma_crc_io_calculation(void *buffer, - uint32_t total_beat_size) -{ - uint32_t counter = total_beat_size; - uint8_t *buffer_8; - uint16_t *buffer_16; - uint32_t *buffer_32; - - for (counter=0; counterCRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_BYTE) { - buffer_8 = buffer; - DMAC->CRCDATAIN.reg = buffer_8[counter]; - } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_HWORD) { - buffer_16 = buffer; - DMAC->CRCDATAIN.reg = buffer_16[counter]; - } else if (DMAC->CRCCTRL.bit.CRCBEATSIZE == CRC_BEAT_SIZE_WORD) { - buffer_32 = buffer; - DMAC->CRCDATAIN.reg = buffer_32[counter]; - } - /* Wait several cycle to make sure CRC complete */ - nop(); - nop(); - nop(); - nop(); - } -} - -#ifdef __cplusplus -} -#endif - -#endif /* DMA_CRC_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/dma/dma_sam_b.c b/atmel-samd/asf/sam0/drivers/dma/dma_sam_b.c deleted file mode 100644 index d14f0e5ee2aae..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dma/dma_sam_b.c +++ /dev/null @@ -1,557 +0,0 @@ -/* - * \file - * - * \brief Direct Memory Access Controller Driver for SAMB - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include "dma_sam_b.h" - -struct _dma_module { - volatile bool _dma_init; - volatile uint32_t allocated_channels; - uint8_t free_channels; -}; - -struct _dma_module _dma_inst = { - ._dma_init = false, - .allocated_channels = 0, - .free_channels = CONF_MAX_USED_CHANNEL_NUM, -}; - -/** Internal DMA resource pool. */ -static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM]; - -/** - * \brief Get the assigned channel DMA value. - * - * \param[in] channel DMA channel index - * \param[in] DMA register address - * - * \return The value of DMA register. - */ -static uint32_t get_channel_reg_val(uint8_t channel, uint32_t reg) -{ - return *(uint32_t*)(reg + 0x100*channel); -} - -/** - * \brief Set the assigned channel DMA value. - * - * \param[in] channel DMA channel index - * \param[in] DMA register address - * \param[in] The value to be set - * - */ -static void set_channel_reg_val(uint8_t channel, uint32_t reg, uint32_t val) -{ - *(uint32_t*)(reg + 0x100*channel) = val; -} - -/** - * \brief Get the DMA status. - * - * \param[in] channel DMA channel index - * - * \return The status of DMA - */ -uint8_t dma_get_status(uint8_t channel) -{ - return (uint8_t)get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_RAWSTAT_REG.reg); -} - -/** - * \brief Get the DMA interrupt status. - * - * \param[in] channel DMA channel index - * - * \return The interrupt of status DMA - */ -uint8_t dma_get_interrupt_status(uint8_t channel) -{ - return get_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg); -} - -/** - * \brief Get the DMA interrupt status. - * - * \param[in] channel DMA channel index - * \param[in] flag The interrupt flag want to clear - * - */ -void dma_clear_interrupt_status(uint8_t channel, uint8_t flag) -{ - set_channel_reg_val(channel, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1 << flag); -} - -/** - * \brief Find a free channel for a DMA resource. - * - * Find a channel for the requested DMA resource. - * - * \return Status of channel allocation. - * \retval DMA_INVALID_CHANNEL No channel available - * \retval count Allocated channel for the DMA resource - */ -static uint8_t _dma_find_first_free_channel_and_allocate(void) -{ - uint8_t count; - uint32_t tmp; - bool allocated = false; - - tmp = _dma_inst.allocated_channels; - - for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) { - if (!(tmp & 0x00000001)) { - /* If free channel found, set as allocated and return - *number */ - - _dma_inst.allocated_channels |= 1 << count; - _dma_inst.free_channels--; - allocated = true; - - break; - } - - tmp = tmp >> 1; - } - - if (!allocated) { - return DMA_INVALID_CHANNEL; - } else { - return count; - } -} - -/** - * \brief Release an allocated DMA channel. - * - * \param[in] channel Channel id to be released - * - */ -static void _dma_release_channel(uint8_t channel) -{ - _dma_inst.allocated_channels &= ~(1 << channel); - _dma_inst.free_channels++; -} - -/** - * \brief Initializes config with predefined default values. - * - * This function will initialize a given DMA configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structure before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Set source max burst number as 1 - * \li Set source tokens as 1 - * \li Set source peripheral as memory - * \li Set source peripheral delay as 0 - * \li Disable source top priority - * \li Set source top priority channel as 0 - * \li Disable source high priority - * \li Set source high priority channel as 0 - * \li Set destination max burst number as 1 - * \li Set destination tokens as 1 - * \li Set destination peripheral as memory - * \li Set destination peripheral delay as 0 - * \li Disable destination top priority - * \li Set destination top priority channel as 0 - * \li Disable destination high priority - * \li Set destination high priority channel as 0 - * \li Disable the joint mode - * \li Disable the endian swap - * \param[out] config Pointer to the configuration - * - */ -void dma_get_config_defaults(struct dma_resource_config *config) -{ - /* DMA source configuration */ - config->src.max_burst = 1; - config->src.tokens = 1; - config->src.enable_inc_addr = true; - config->src.periph = MEMORY_DMA_PERIPHERAL; - config->src.periph_delay = 0; - config->src.enable_proi_top = false; - config->src.proi_top_index = 0; - config->src.enable_proi_high = false; - config->src.proi_high_index = 0; - /* DMA destination configuration */ - config->des.max_burst = 1; - config->des.tokens = 1; - config->des.enable_inc_addr = true; - config->des.periph = MEMORY_DMA_PERIPHERAL; - config->des.periph_delay = 0; - config->des.enable_proi_top = false; - config->des.proi_top_index = 0; - config->des.enable_proi_high = false; - config->des.proi_high_index = 0; - /* DMA channel configuration */ - config->enable_joint_mode = false; - config->swap = DMA_ENDIAN_NO_SWAP; -} - -/** - * \brief Configure the DMA resource. - * - * \param[in] dma_resource Pointer to a DMA resource instance - * \param[out] config Configurations of the DMA resource - * - */ -static void _dma_set_config(struct dma_resource *resource, - struct dma_resource_config *config) -{ - uint32_t regval = 0; - - /* Static register configuration */ - regval = PROV_DMA_CTRL_CH0_STATIC_REG0_RD_BURST_MAX_SIZE(config->src.max_burst)| - PROV_DMA_CTRL_CH0_STATIC_REG0_RD_TOKENS(config->src.tokens) | - (config->src.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG0.reg, regval); - /* Static register1 configuration */ - regval = PROV_DMA_CTRL_CH0_STATIC_REG1_WR_BURST_MAX_SIZE(config->des.max_burst) | - PROV_DMA_CTRL_CH0_STATIC_REG1_WR_TOKENS(config->des.tokens) | - (config->des.enable_inc_addr << PROV_DMA_CTRL_CH0_STATIC_REG0_RD_INCR_Pos); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG1.reg, regval); - /* Static register2 configuration */ - regval = (config->enable_joint_mode << PROV_DMA_CTRL_CH0_STATIC_REG2_JOINT_Pos) | - PROV_DMA_CTRL_CH0_STATIC_REG2_END_SWAP(config->swap); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG2.reg, regval); - /* Static register4 configuration */ - regval = PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_NUM(config->src.periph) | - PROV_DMA_CTRL_CH0_STATIC_REG4_RD_PERIPH_DELAY(config->src.periph_delay) | - PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_NUM(config->des.periph) | - PROV_DMA_CTRL_CH0_STATIC_REG4_WR_PERIPH_DELAY(config->des.periph_delay); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_STATIC_REG4.reg, regval); - /* Priority channels configuration */ - regval = PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP_NUM(config->src.proi_top_index) | - (PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_TOP << config->src.enable_proi_top) | - PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH_NUM(config->src.proi_high_index) | - (PROV_DMA_CTRL_CORE_PRIORITY_RD_PRIO_HIGH << config->src.enable_proi_high) | - PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP_NUM(config->des.proi_top_index) | - (PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_TOP << config->des.enable_proi_top) | - PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH_NUM(config->des.proi_high_index) | - (PROV_DMA_CTRL_CORE_PRIORITY_WR_PRIO_HIGH << config->des.enable_proi_high); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CORE_PRIORITY.reg, regval); - /* Initial the global variety */ - for (int i = 0; i < DMA_CALLBACK_N; i++) { - resource->callback[i] = NULL; - } - resource->callback_enable = 0; -} - -/** - * \brief Free an allocated DMA resource. - * - * This function will free an allocated DMA resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - * \return Status of the free procedure. - * - * \retval STATUS_OK The DMA resource was freed successfully - * \retval STATUS_BUSY The DMA resource was busy and can't be freed - * \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized - */ -enum status_code dma_free(struct dma_resource *resource) -{ - /* Check if channel is busy */ - if (dma_get_job_status(resource) == STATUS_BUSY) { - return STATUS_BUSY; - } - - /* Check if DMA resource was not allocated */ - if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) { - return STATUS_ERR_NOT_INITIALIZED; - } - - /* Release the DMA resource */ - _dma_release_channel(resource->channel_id); - - /* Reset the item in the DMA resource pool */ - _dma_active_resource[resource->channel_id] = NULL; - - return STATUS_OK; -} - -/** - * \brief Add a DMA transfer descriptor to a DMA resource. - * - * This function will add a DMA transfer descriptor to a DMA resource. - * If there was a transfer descriptor already allocated to the DMA resource, - * the descriptor will be linked to the next descriptor address. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] descriptor Pointer to the transfer descriptor - * - * \retval STATUS_OK The descriptor is added to the DMA resource - * \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added - */ -enum status_code dma_add_descriptor(struct dma_resource *resource, - struct dma_descriptor *descriptor) -{ - struct dma_descriptor *desc = resource->descriptor; - - /* Check if channel is busy */ - if (dma_get_job_status(resource) == STATUS_BUSY) { - return STATUS_BUSY; - } - - /* Look up for an empty space for the descriptor */ - if (desc == NULL) { - resource->descriptor = descriptor; - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG0.reg, descriptor->read_start_addr); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG1.reg, descriptor->write_start_addr); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG2.reg, descriptor->buffer_size); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, 3); - } else { - /* Looking for end of descriptor link */ - while(((uint32_t)desc->cmd.next_addr) != 0) { - desc = (struct dma_descriptor*)((uint32_t)desc->next); - } - if (resource->descriptor->cmd.next_addr == 0x0) { - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CMD_REG3.reg, ((uint32_t)descriptor & (~0x3))); - } - /* Set to the end of descriptor list */ - desc->next = (uint32_t)descriptor; - /* The end of list should point to 0 */ - if (descriptor->cmd.next_addr != 0) { - /* Enable transferred interrupt, and channel stops when buffer done */ - descriptor->next = 0x3; - } - } - - return STATUS_OK; -} - -/** - * \brief Start a DMA transfer. - * - * This function will start a DMA transfer through an allocated DMA resource. - * - * \param[in,out] resource Pointer to the DMA resource - * - * \return Status of the transfer start procedure. - * - * \retval STATUS_OK The transfer was started successfully - * \retval STATUS_BUSY The DMA resource was busy and the transfer was not started - * \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started - */ -enum status_code dma_start_transfer_job(struct dma_resource *resource) -{ - volatile uint32_t regval; - - /* Check if resource was busy */ - if (resource->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } - - /* Check if transfer size is valid */ - if (resource->descriptor->buffer_size == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Clear the interrupt flag */ - regval = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg); - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, regval); - /* Set the interrupt flag */ - regval = PROV_DMA_CTRL_CH0_INT_ENABLE_REG_MASK & resource->callback_enable; - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_ENABLE_REG.reg, regval); - /* Set job status */ - resource->job_status = STATUS_BUSY; - - /* Enable the transfer channel */ - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_ENABLE_REG.reg, 1); - /* Start the transfer channel */ - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_CH_START_REG.reg, 1); - - return STATUS_OK; -} -/** - * \brief Get the channel index - * - * \param[in] channel Channel active - * - */ -static uint8_t get_channel_index(uint8_t channel) -{ - uint8_t index = 0; - - channel = channel & 0x0f; - do { - channel = channel >> 1; - index++; - } while (channel); - - return (index - 1); -} - -/** - * \brief DMA interrupt service routine. - * - */ -static void dma_isr_handler( void ) -{ - uint8_t active_channel; - static uint8_t channel_index; // - struct dma_resource *resource; - uint8_t isr; - uint8_t isr_flag = 0; - - /* Get active channel */ - active_channel = PROV_DMA_CTRL0->CORE_INT_STATUS.reg & - PROV_DMA_CTRL_CORE_INT_STATUS_CHANNEL__Msk; - - do { - channel_index = get_channel_index(active_channel); - /* Get active DMA resource based on channel */ - resource = _dma_active_resource[channel_index]; - isr = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_STATUS_REG.reg); - /* Calculate block transfer size of the DMA transfer */ - resource->transfered_size = get_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_COUNT_REG.reg); - - /* DMA channel interrupt handler */ - if (isr & (1 << DMA_CALLBACK_TRANSFER_DONE)) { - /* Transfer complete flag */ - isr_flag = DMA_CALLBACK_TRANSFER_DONE; - /* Set job status */ - resource->job_status = STATUS_OK; - } else if (isr & (1 << DMA_CALLBACK_READ_ERR)) { - /* Read error flag */ - isr_flag = DMA_CALLBACK_READ_ERR; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - } else if (isr & (1 << DMA_CALLBACK_WRITE_ERR)) { - /* Write error flag */ - isr_flag = DMA_CALLBACK_WRITE_ERR; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - } else if (isr & (1 << DMA_CALLBACK_FIFO_OVERFLOW)) { - /* Overflow flag */ - isr_flag = DMA_CALLBACK_FIFO_OVERFLOW; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - } else if (isr & (1 << DMA_CALLBACK_FIFO_UNDERFLOW)) { - /* Underflow flag */ - isr_flag = DMA_CALLBACK_FIFO_UNDERFLOW; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - } else if (isr & (1 << DMA_CALLBACK_READ_TIMEOUT)) { - /* Read timeout flag */ - isr_flag = DMA_CALLBACK_READ_TIMEOUT; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - } else if (isr & (1 << DMA_CALLBACK_WRITE_TIMEOUT)) { - /* Write timeout flag */ - isr_flag = DMA_CALLBACK_WRITE_TIMEOUT; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - } else if (isr & (1 << DMA_CALLBACK_WDT_TRIGGER)) { - /* Watchdog error flag */ - isr_flag = DMA_CALLBACK_WDT_TRIGGER; - /* Set I/O ERROR status */ - resource->job_status = STATUS_ERR_IO; - } - - if (isr) { - /* Clear the watch dog error flag */ - set_channel_reg_val(resource->channel_id, (uint32_t)&PROV_DMA_CTRL0->CH0_INT_CLEAR_REG.reg, 1<callback_enable & (1<callback[isr_flag])) { - resource->callback[isr_flag](resource); - } - } - isr &= ~(1<IRQ_MUX_IO_SEL_3.bit.MUX_15 = LPMCU_MISC_REGS_IRQ_MUX_IO_SEL_3_MUX_15_16_Val; - system_register_isr(31, (uint32_t)dma_isr_handler); - - _dma_inst._dma_init = true; - } - - new_channel = _dma_find_first_free_channel_and_allocate(); - /* If no channel available, return not found */ - if (new_channel == DMA_INVALID_CHANNEL) { - return STATUS_ERR_NOT_FOUND; - } - - /* Set the channel */ - resource->channel_id = new_channel; - /* Configure the DMA control,channel registers and descriptors here */ - _dma_set_config(resource, config); - - resource->descriptor = NULL; - - /* Log the DMA resource into the internal DMA resource pool */ - _dma_active_resource[resource->channel_id] = resource; - - return STATUS_OK; -} \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/dma/dma_sam_b.h b/atmel-samd/asf/sam0/drivers/dma/dma_sam_b.h deleted file mode 100644 index ae3ecede8550d..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dma/dma_sam_b.h +++ /dev/null @@ -1,650 +0,0 @@ -/** - * \file - * - * \brief Direct Memory Access Controller Driver for SAMB - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef DMA_H_INCLUDED -#define DMA_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_samb_dma_group SAM Direct Memory Access Controller Driver (DMAC) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and management of the Direct Memory Access Controller(DMAC) module within - * the device. The DMAC can transfer data between memories and peripherals, and - * thus off-load these tasks from the CPU. The module supports peripheral to - * peripheral, peripheral to memory, memory to peripheral, and memory to memory - * transfers. - * - * The following peripherals are used by the DMAC Driver: - * - DMAC (Direct Memory Access Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM B11 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_samb_dma_prerequisites - * - \ref asfdoc_samb_dma_module_overview - * - \ref asfdoc_samb_dma_special_considerations - * - \ref asfdoc_samb_dma_extra_info - * - \ref asfdoc_samb_dma_examples - * - \ref asfdoc_samb_dma_api_overview - * - * - * \section asfdoc_samb_dma_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_samb_dma_module_overview Module Overview - * - * SAM devices with DMAC enables high data transfer rates with minimum - * CPU intervention and frees up CPU time. With access to all peripherals, - * the DMAC can handle automatic transfer of data to/from modules. - * It supports static and incremental addressing for both source and - * destination. - * - * The DMAC when used with peripheral triggers, provides a - * considerable advantage by reducing the power consumption and performing - * data transfer in the background. - * The CPU can remain in sleep during this time to reduce power consumption. - * - * - * - * - * - * - * - * - * - * - *
DeviceDma channel number
SAMB114
- * The DMA channel operation can be suspended at any time by software, - * or after selectable descriptor execution. The DMAC driver for SAM - * supports four types of transfers such as peripheral to peripheral, - * peripheral to memory, memory to peripheral, and memory to memory. - * - * The basic transfer unit is a beat which is defined as a single bus access. - * There can be multiple beats in a single block transfer and multiple block - * transfers in a DMA transaction. - * DMA transfer is based on descriptors, which holds transfer properties - * such as the source and destination addresses, transfer counter, and other - * additional transfer control information. - * The descriptors can be static or linked. When static, a single block transfer - * is performed. When linked, a number of transfer descriptors can be used to - * enable multiple block transfers within a single DMA transaction. - * - * The implementation of the DMA driver is based on the idea that DMA channel - * is a finite resource of entities with the same abilities. A DMA channel resource - * is able to move a defined set of data from a source address to destination - * address triggered by a transfer trigger. On the SAM devices there are 12 - * DMA resources available for allocation. Each of these DMA resources can trigger - * interrupt callback routines. - * The other main features are: - * - * - Selectable transfer trigger source - * - Software - * - Peripheral - * - Tree level channel priority - * - Normal level - * - High level - * - Top level - * - Optional interrupt generation on transfer complete, channel error - * - Supports multi-buffer or circular buffer mode by linking multiple descriptors - * - Beat size configurable as 8-bit, 16-bit, or 32-bit - * - * A simplified block diagram of the DMA Resource can be seen in - * \ref asfdoc_samb_dma_module_block_diagram "the figure below". - * - * \anchor asfdoc_samb_dma_module_block_diagram - * \dot - * digraph overview { - * splines = false; - * rankdir=LR; - * - * mux1 [label="Transfer Trigger", shape=box]; - * - * dma [label="DMA Channel", shape=polygon, sides=6, orientation=60, style=filled, fillcolor=darkolivegreen1, height=1, width=1]; - * descriptor [label="Transfer Descriptor", shape=box, style=filled, fillcolor=lightblue]; - * - * mux1 -> dma; - * descriptor -> dma; - * - * interrupt [label="Interrupt", shape=box]; - * events [label="Events", shape=box]; - * - * dma:e -> interrupt:w; - * dma:e -> events:w; - * - * {rank=same; descriptor dma} - * - * } - * \enddot - * - * \subsection asfdoc_samb_dma_module_overview_dma_channels DMA Channels - * The DMAC in each device consists of several DMA channels, which - * along with the transfer descriptors defines the data transfer properties. - * - The transfer control descriptor defines the source and destination - * addresses, source and destination address increment settings, the - * block transfer count - * - Dedicated channel registers control the peripheral trigger source, - * trigger mode settings, and channel priority level settings - * - * With a successful DMA resource allocation, a dedicated - * DMA channel will be assigned. The channel will be occupied until the - * DMA resource is freed. A DMA resource handle is used to identify the specific - * DMA resource. - * When there are multiple channels with active requests, the arbiter prioritizes - * the channels requesting access to the bus. - * - * \subsection asfdoc_samb_dma_module_overview_dma_trigger DMA Triggers - * DMA transfer can be started only when a DMA transfer request is acknowledged/granted by the arbiter. A - * transfer request can be triggered from software, peripheral. There - * are dedicated source trigger selections for each DMA channel usage. - * - * \subsection asfdoc_samb_dma_module_overview_dma_transfer_descriptor DMA Transfer Descriptor - * The transfer descriptor resides in the SRAM and - * defines these channel properties. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Field nameField width
Source Address32 bits
Destination Address32 bits
Block Transfer Counter32 bits
Descriptor Next Address30 bits
Block Transfer Interrupt1 bit
Block Transfer Stop Control1 bit
- * - * Before starting a transfer, at least one descriptor should be configured. - * After a successful allocation of a DMA channel, the transfer descriptor can - * be added with a call to \ref dma_add_descriptor(). If there is a transfer - * descriptor already allocated to the DMA resource, the descriptor will - * be linked to the next descriptor address. - * - * \subsection asfdoc_samb_dma_module_overview_dma_output DMA Interrupts - * Both an interrupt callback and an peripheral can be triggered by the - * DMA transfer. Three types of callbacks are supported by the DMA driver: - * transfer complete, channel suspend, and transfer error. Each of these callback - * types can be registered and enabled for each channel independently through - * the DMA driver API. - * - * - * \section asfdoc_samb_dma_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_samb_dma_extra_info Extra Information - * - * For extra information, see \ref asfdoc_samb_dma_extra. This includes: - * - \ref asfdoc_samb_dma_extra_acronyms - * - \ref asfdoc_samb_dma_extra_dependencies - * - \ref asfdoc_samb_dma_extra_errata - * - \ref asfdoc_samb_dma_extra_history - * - * - * \section asfdoc_samb_dma_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_samb_dma_exqsg. - * - * - * \section asfdoc_samb_dma_api_overview API Overview - * @{ - */ - -#include -#include -#include "conf_dma.h" - -/** DMA IRQn number. */ -#define PROV_DMA_CTRL0_IRQn 15 - -/** DMA invalid channel number. */ -#define DMA_INVALID_CHANNEL 0xff - -/** DMA peripheral index */ -enum dma_peripheral_index { - MEMORY_DMA_PERIPHERAL = 0, - UART0RX_DMA_PERIPHERAL, - UART0TX_DMA_PERIPHERAL, - UART1RX_DMA_PERIPHERAL, - UART1TX_DMA_PERIPHERAL, - SPI0RX_DMA_PERIPHERAL, - SPI0TX_DMA_PERIPHERAL, - SPI1RX_DMA_PERIPHERAL, - SPI1TX_DMA_PERIPHERAL, - I2C0RX_DMA_PERIPHERAL, - I2C0TX_DMA_PERIPHERAL, - I2C1RX_DMA_PERIPHERAL, - I2C1TX_DMA_PERIPHERAL, - DUALTIMER0_DMA_PERIPHERAL = 15, - TIMER0_DMA_PERIPHERAL, -}; - -/** DMA channel index */ -enum dma_ch_index { - /** DMA channel 0 */ - DMA_CHANNEL_0 = 0, - /** DMA channel 1 */ - DMA_CHANNEL_1, - /** DMA channel 2 */ - DMA_CHANNEL_2, - /** DMA channel 3 */ - DMA_CHANNEL_3, -}; - -enum dma_endian_swap { - /** DMA endian no swap */ - DMA_ENDIAN_NO_SWAP, - /** DMA endian 16-bit */ - DMA_ENDIAN_SIZE_16, - /** DMA endian 32-bit */ - DMA_ENDIAN_SIZE_32, - /** DMA endian 64-bit */ - DMA_ENDIAN_SIZE_64, -}; - -/** - * Callback types for DMA callback driver. - */ -enum dma_callback_type { - /** Callback for transfer complete */ - DMA_CALLBACK_TRANSFER_DONE, - /** AHB read slave error */ - DMA_CALLBACK_READ_ERR, - /** AHB write slave error */ - DMA_CALLBACK_WRITE_ERR, - /** FIFO has been overflown */ - DMA_CALLBACK_FIFO_OVERFLOW, - /** FIFO has been underflows */ - DMA_CALLBACK_FIFO_UNDERFLOW, - /** Read timeout on AHB bus (timeout value fixed at 1024 cycles) */ - DMA_CALLBACK_READ_TIMEOUT, - /** Write timeout on AHB bus (timeout value fixed at 1024 cycles) */ - DMA_CALLBACK_WRITE_TIMEOUT, - /** Channel active but did not start a burst for 2048 cycles */ - DMA_CALLBACK_WDT_TRIGGER, - /** Number of available callbacks */ - DMA_CALLBACK_N, -}; - -/** - * DMA transfer descriptor configuration. When the source or destination address - * increment is enabled, the addresses stored into the configuration structure - * must correspond to the end of the transfer. - */ -struct dma_descriptor { - /** Start address of read buffer */ - uint32_t read_start_addr; - /** Start address of write buffer */ - uint32_t write_start_addr; - /** Size (in bytes) of buffer to transfer */ - uint32_t buffer_size; - union { - struct { - /** Active high interrupt enable once buffer has been transferred */ - uint32_t set_interrupt:1; - /** If set, channel stops when buffer done, otherwise load from cmd_next_addr */ - uint32_t last:1; - /** Address of next command if cmd_last is not set */ - uint32_t next_addr:30; - } cmd; - uint32_t next; - }; -}; -/** Structure for DMA source/description */ -struct dma_config { - /** Maximum number of bytes of an AHB read/write burst */ - uint8_t max_burst; - /** Number of AHB read/write commands to issue before channel is released */ - uint8_t tokens; - /** If true, the controller will increment the next burst address */ - bool enable_inc_addr; - /** Index of peripheral to read/write from (0 if memory or no peripheral flow control) */ - enum dma_peripheral_index periph; - /** - * Number of cycles to wait for read/write request signal to update - * after issuing the read/write clear signal - */ - uint8_t periph_delay; - /** Top priority enable */ - bool enable_proi_top; - /** Top priority channel index */ - uint8_t proi_top_index; - /** High priority enable */ - bool enable_proi_high; - /** High priority channel index */ - uint8_t proi_high_index; -}; - -/** Structure for DMA transfer resource */ -struct dma_resource_config { - struct dma_config src; - struct dma_config des; - /** If true, channel will work in joint mode */ - bool enable_joint_mode; - /** Endian Byte Swapping */ - enum dma_endian_swap swap; -}; - -/** Forward definition of the DMA resource */ -struct dma_resource; -/** Type definition for a DMA resource callback function */ -typedef void (*dma_callback_t)(struct dma_resource *const resource); - -/** Structure for DMA transfer resource */ -struct dma_resource { - /** Allocated DMA channel ID */ - uint8_t channel_id; - /** Array of callback functions for DMA transfer job */ - dma_callback_t callback[DMA_CALLBACK_N]; - /** Bit mask for enabled callbacks */ - uint8_t callback_enable; - /** Status of the last job */ - volatile enum status_code job_status; - /** Transferred data size */ - uint32_t transfered_size; - /** DMA transfer descriptor */ - struct dma_descriptor* descriptor; -}; - -/** - * \brief Get DMA resource status. - * - * \param[in] resource Pointer to the DMA resource - * - * \return Status of the DMA resource. - */ -static inline enum status_code dma_get_job_status(struct dma_resource *resource) -{ - return resource->job_status; -} - -/** - * \brief Enable a callback function for a dedicated DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_enable_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - resource->callback_enable |= 1 << type; -} - -/** - * \brief Disable a callback function for a dedicated DMA resource. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_disable_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - resource->callback_enable &= ~(1 << type); -} - -/** - * \brief Register a callback function for a dedicated DMA resource. - * - * There are three types of callback functions, which can be registered: - * - Callback for transfer complete - * - Callback for transfer error - * - Callback for channel suspend - * - * \param[in] resource Pointer to the DMA resource - * \param[in] callback Pointer to the callback function - * \param[in] type Callback function type - * - */ -static inline void dma_register_callback(struct dma_resource *resource, - dma_callback_t callback, enum dma_callback_type type) -{ - resource->callback[type] = callback; -} - -/** - * \brief Unregister a callback function for a dedicated DMA resource. - * - * There are three types of callback functions: - * - Callback for transfer complete - * - Callback for transfer error - * - Callback for channel suspend - * - * The application can unregister any of the callback functions which - * are already registered and are no longer needed. - * - * \param[in] resource Pointer to the DMA resource - * \param[in] type Callback function type - * - */ -static inline void dma_unregister_callback(struct dma_resource *resource, - enum dma_callback_type type) -{ - resource->callback[type] = NULL; -} - -/** - * \brief Initializes DMA transfer configuration with predefined default values. - * - * This function will initialize a given DMA descriptor configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structure before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Set the read start address as 0 - * \li Set the write start address as 0 - * \li Set buffer size as 1 - * \li Set beat size as byte - * \li Enable the interrupt - * \li Enable the channel stops when buffer done - * \li Set next command address to 0 - * \param[out] config Pointer to the configuration - * - */ -static inline void dma_descriptor_get_config_defaults(struct dma_descriptor *config) -{ - /* Default read buffer size is set to 0 */ - config->read_start_addr = 0; - /* Default write buffer size is set to 0 */ - config->write_start_addr = 0; - /* Set beat size to one byte */ - config->buffer_size = 1; - /* Enable transferred interrupt */ - config->cmd.set_interrupt = 1; - /* Channel stops when buffer done */ - config->cmd.last = 1; - /* Set next command to 0 */ - config->cmd.next_addr = 0; -} - -/** - * \brief Update DMA descriptor. - * - * This function can update the descriptor of an allocated DMA resource. - * - */ -static inline void dma_update_descriptor(struct dma_resource *resource, - struct dma_descriptor* descriptor) -{ - resource->descriptor = descriptor; -} - -/** - * \brief Reset DMA descriptor. - * - * This function will clear the DESCADDR register of an allocated DMA resource. - * - */ -static inline void dma_reset_descriptor(struct dma_resource *resource) -{ - resource->descriptor = NULL; -} - -void dma_get_config_defaults(struct dma_resource_config *config); -enum status_code dma_allocate(struct dma_resource *resource, - struct dma_resource_config *config); -enum status_code dma_add_descriptor(struct dma_resource *resource, - struct dma_descriptor* descriptor); -enum status_code dma_start_transfer_job(struct dma_resource *resource); -enum status_code dma_free(struct dma_resource *resource); -uint8_t dma_get_status(uint8_t channel); -uint8_t dma_get_interrupt_status(uint8_t channel); -void dma_clear_interrupt_status(uint8_t channel, uint8_t flag); -/** @} */ - -/** - * \page asfdoc_samb_dma_extra Extra Information for DMAC Driver - * - * \section asfdoc_samb_dma_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DMADirect Memory Access
DMACDirect Memory Access Controller
CPUCentral Processing Unit
- * - * - * \section asfdoc_samb_dma_extra_dependencies Dependencies - * There are no dependencies related to this driver. - * - * - * \section asfdoc_samb_dma_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_samb_dma_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - - /** - * \page asfdoc_samb_dma_exqsg Examples for DMAC Driver - * - * This is a list of the available Quick Start Guides (QSGs) and example - * applications for \ref asfdoc_samb_dma_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_samb_dma_basic_use_case - * - * \note More DMA usage examples are available in peripheral QSGs. - * - * \page asfdoc_samb_dma_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
A09/2015Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* DMA_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/dma/module_config/conf_dma.h b/atmel-samd/asf/sam0/drivers/dma/module_config/conf_dma.h deleted file mode 100644 index fff0a2c8164a5..0000000000000 --- a/atmel-samd/asf/sam0/drivers/dma/module_config/conf_dma.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief SAM Direct Memory Access Driver Configuration Header - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_DMA_H_INCLUDED -#define CONF_DMA_H_INCLUDED - -# define CONF_MAX_USED_CHANNEL_NUM 5 - -#endif diff --git a/atmel-samd/asf/sam0/drivers/events/events.h b/atmel-samd/asf/sam0/drivers/events/events.h deleted file mode 100644 index 318b89a4c51e7..0000000000000 --- a/atmel-samd/asf/sam0/drivers/events/events.h +++ /dev/null @@ -1,729 +0,0 @@ -/** - * \file - * - * \brief SAM Event System Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef EVENTS_H_INCLUDED -#define EVENTS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_events_group SAM Event System (EVENTS) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the device's peripheral - * event resources and users within the device, including enabling and disabling - * of peripheral source selection and synchronization of clock domains between - * various modules. The following API modes is covered by this manual: - * - Polled API - * \if EVENTS_INTERRUPT_HOOK_MODE - * - Interrupt hook API - * \endif - * - * The following peripheral is used by this module: - * - EVSYS (Event System Management) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - Atmel | SMART SAM R30 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_events_prerequisites - * - \ref asfdoc_sam0_events_module_overview - * - \ref asfdoc_sam0_events_special_considerations - * - \ref asfdoc_sam0_events_extra_info - * - \ref asfdoc_sam0_events_examples - * - \ref asfdoc_sam0_events_api_overview - * - * - * \section asfdoc_sam0_events_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_events_module_overview Module Overview - * - * Peripherals within the SAM devices are capable of generating two types of - * actions in response to given stimulus; set a register flag for later - * intervention by the CPU (using interrupt or polling methods), or generate - * event signals, which can be internally routed directly to other - * peripherals within the device. The use of events allows for direct actions - * to be performed in one peripheral in response to a stimulus in another - * without CPU intervention. This can lower the overall power consumption of the - * system if the CPU is able to remain in sleep modes for longer periods - * (SleepWalking), and lowers the latency of the system response. - * - * The event system is comprised of a number of freely configurable Event - * resources, plus a number of fixed Event Users. Each Event resource can be - * configured to select the input peripheral that will generate the events - * signal, as well as the synchronization path and edge detection mode. - * The fixed-function Event Users, connected to peripherals within the device, - * can then subscribe to an Event resource in a one-to-many relationship in order - * to receive events as they are generated. An overview of the event system - * chain is shown in - * \ref asfdoc_sam0_events_module_overview_fig "the figure below". - * - * \anchor asfdoc_sam0_events_module_overview_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Source\nPeripheral\n(Generator)" shape=ellipse style=filled fillcolor=lightgray] src_peripheral; - * node [label="Event\nResource A" shape=square style=""] event_gen0; - * node [label="Event\nUser X" shape=square style=""] event_user0; - * node [label="Event\nUser Y" shape=square style=""] event_user1; - * node [label="Destination\nPeripheral\n(User)" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral0; - * node [label="Destination\nPeripheral\n(User)" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral1; - * - * src_peripheral -> event_gen0; - * event_gen0 -> event_user0; - * event_gen0 -> event_user1; - * event_user0 -> dst_peripheral0; - * event_user1 -> dst_peripheral1; - * } - * \enddot - * - * There are many different events that can be routed in the device, which can - * then trigger many different actions. For example, an Analog Comparator module - * could be configured to generate an event when the input signal rises above - * the compare threshold, which then triggers a Timer Counter module to capture - * the current count value for later use. - * - * \subsection asfdoc_sam0_events_module_overview_event_channels Event Channels - * The Event module in each device consists of several channels, which can be - * freely linked to an event generator (i.e. a peripheral within the device - * that is capable of generating events). Each channel can be individually - * configured to select the generator peripheral, signal path, and edge detection - * applied to the input event signal, before being passed to any event user(s). - * - * Event channels can support multiple users within the device in a standardized - * manner. When an Event User is linked to an Event Channel, the channel will - * automatically handshake with all attached users to ensure that all modules - * correctly receive and acknowledge the event. - * - * \subsection asfdoc_sam0_events_module_overview_event_users Event Users - * Event Users are able to subscribe to an Event Channel, once it has been - * configured. Each Event User consists of a fixed connection to one of the - * peripherals within the device (for example, an ADC module, or Timer module) - * and is capable of being connected to a single Event Channel. - * - * \subsection asfdoc_sam0_events_module_overview_edge_detection Edge Detection - * For asynchronous events, edge detection on the event input is not possible, - * and the event signal must be passed directly between the event generator and - * event user. For synchronous and re-synchronous events, the input signal from - * the event generator must pass through an edge detection unit, so that only - * the rising, falling, or both edges of the event signal triggers an action in - * the event user. - * - * \subsection asfdoc_sam0_events_module_overview_path_selection Path Selection - * The event system in the SAM devices supports three signal path types from - * the event generator to Event Users: asynchronous, synchronous, and - * re-synchronous events. - * - * \subsubsection asfdoc_sam0_events_module_overview_path_selection_async Asynchronous Paths - * Asynchronous event paths allow for an asynchronous connection between the - * event generator and Event Users, when the source and destination - * peripherals share the same \ref asfdoc_sam0_system_clock_group "Generic Clock" - * channel. In this mode the event is propagated between the source and - * destination directly to reduce the event latency, thus no edge detection is - * possible. The asynchronous event chain is shown in - * \ref asfdoc_sam0_events_module_async_path_fig "the figure below". - * - * \anchor asfdoc_sam0_events_module_async_path_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Source\nPeripheral" shape=ellipse style=filled fillcolor=lightgray] src_peripheral; - * node [label=" EVSYS | Event\nChannel/User" fillcolor=white style="dashed" shape=record] events_chan; - * node [label="Destination\nPeripheral" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral; - * - * src_peripheral -> events_chan; - * events_chan -> dst_peripheral; - * - * } - * \enddot - * \note Identically shaped borders in the diagram indicate a shared generic clock channel. - * - * \subsubsection asfdoc_sam0_events_module_overview_path_selection_sync Synchronous Paths - * The Synchronous event path should be used when edge detection or interrupts - * from the event channel are required, and the source event generator and the - * event channel shares the same Generic Clock channel. The synchronous event - * chain is shown in - * \ref asfdoc_sam0_events_module_sync_path_fig "the figure below". - * - * Not all peripherals support Synchronous event paths; refer to the device datasheet. - * - * \anchor asfdoc_sam0_events_module_sync_path_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Source\nPeripheral" shape=ellipse style="filled, dashed" fillcolor=lightgray] src_peripheral; - * node [label=" EVSYS | Event\nChannel/User" fillcolor=white shape=record style="dashed"] events_chan; - * node [label="Destination\nPeripheral" shape=ellipse style="filled, solid" fillcolor=lightgray] dst_peripheral; - * - * src_peripheral -> events_chan; - * events_chan -> dst_peripheral; - * - * } - * \enddot - * \note Identically shaped borders in the diagram indicate a shared generic clock channel. - * - * \subsubsection asfdoc_sam0_events_module_overview_path_selection_resync Re-synchronous Paths - * Re-synchronous event paths are a special form of synchronous events, where - * when edge detection or interrupts from the event channel are required, but - * the event generator and the event channel use different Generic Clock - * channels. The re-synchronous path allows the Event System to synchronize the - * incoming event signal from the Event Generator to the clock of the Event - * System module to avoid missed events, at the cost of a higher latency due to - * the re-synchronization process. The re-synchronous event chain is shown in - * \ref asfdoc_sam0_events_module_resync_path_fig "the figure below". - * - * Not all peripherals support re-synchronous event paths; refer to the device datasheet. - * \anchor asfdoc_sam0_events_module_resync_path_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Source\nPeripheral" shape=ellipse style="filled, dotted" fillcolor=lightgray] src_peripheral; - * node [label=" EVSYS | Event\nChannel/User" fillcolor=white shape=record style="dashed"] events_chan; - * node [label="Destination\nPeripheral" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral; - * - * src_peripheral -> events_chan; - * events_chan -> dst_peripheral; - * - * } - * \enddot - * \note Identically shaped borders in the diagram indicate a shared generic clock channel. - * - * \subsection asfdoc_sam0_events_module_overview_physical Physical Connection - * - * \ref asfdoc_sam0_events_module_int_connections_fig "The diagram below" - * shows how this module is interconnected within the device. - * - * \anchor asfdoc_sam0_events_module_int_connections_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Source\nPeripherals" shape=ellipse style=filled fillcolor=lightgray] src_peripheral; - * - * subgraph driver { - * node [label=" EVSYS | Event Channels" fillcolor=white shape=record] events_chan; - * node [label=" EVSYS | Event Users" fillcolor=white shape=record] events_user; - * } - * - * node [label="Destination\nPeripherals" shape=ellipse style=filled fillcolor=lightgray] dst_peripheral; - * - * src_peripheral -> events_chan:f1 [label="Source\nMUXs"]; - * events_chan:f1 -> events_user:f1 [label="Channel\nMUXs"]; - * events_user:f1 -> dst_peripheral; - * } - * \enddot - * - * \subsection asfdoc_sam0_events_module_overview_config Configuring Events - * For SAM devices, several steps are required to properly configure an - * event chain, so that hardware peripherals can respond to events generated by - * each other, as listed below. - * - * \subsubsection asfdoc_sam0_events_module_overview_config_src Source Peripheral - * -# The source peripheral (that will generate events) must be configured and - * enabled. - * -# The source peripheral (that will generate events) must have an output - * event enabled. - - * \subsubsection asfdoc_sam0_events_module_overview_config_evsys Event System - * -# An event system channel must be allocated and configured with the - * correct source peripheral selected as the channel's event generator. - * -# The event system user must be configured and enabled, and attached to - # event channel previously allocated. - - * \subsubsection asfdoc_sam0_events_module_overview_config_dst Destination Peripheral - * -# The destination peripheral (that will receive events) must be configured - * and enabled. - * -# The destination peripheral (that will receive events) must have an input - * event enabled. - * - * - * \section asfdoc_sam0_events_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_sam0_events_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_events_extra. This includes: - * - \ref asfdoc_sam0_events_extra_acronyms - * - \ref asfdoc_sam0_events_extra_dependencies - * - \ref asfdoc_sam0_events_extra_errata - * - \ref asfdoc_sam0_events_extra_history - * - * - * \section asfdoc_sam0_events_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_events_exqsg. - * - * - * \section asfdoc_sam0_events_api_overview API Overview - * @{ - */ - -#include -#include "events_common.h" - -/** - * \brief Edge detect enum. - * - * Event channel edge detect setting. - * - */ -enum events_edge_detect { - /** No event output */ - EVENTS_EDGE_DETECT_NONE, - /** Event on rising edge */ - EVENTS_EDGE_DETECT_RISING, - /** Event on falling edge */ - EVENTS_EDGE_DETECT_FALLING, - /** Event on both edges */ - EVENTS_EDGE_DETECT_BOTH, -}; - -/** - * \brief Path selection enum. - * - * Event channel path selection. - * - */ -enum events_path_selection { - /** Select the synchronous path for this event channel */ - EVENTS_PATH_SYNCHRONOUS, - /** Select the resynchronizer path for this event channel */ - EVENTS_PATH_RESYNCHRONIZED, - /** Select the asynchronous path for this event channel */ - EVENTS_PATH_ASYNCHRONOUS, -}; - -/** - * \brief Events configuration struct. - * - * This event configuration struct is used to configure each of the channels. - * - */ -struct events_config { - /** Select edge detection mode */ - enum events_edge_detect edge_detect; - /** Select events channel path */ - enum events_path_selection path; - /** Set event generator for the channel */ - uint8_t generator; - /** Clock source for the event channel */ - uint8_t clock_source; -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - /** Run in standby mode for the channel */ - bool run_in_standby; - /** Run On Demand */ - bool on_demand; -#endif -}; - -/** - * \brief No event generator definition. - * - * Use this to disable any peripheral event input to a channel. This can be useful - * if you only want to use a channel for software generated events. - * - */ - -///@cond INTERNAL -/** - * \internal - * Status bit offsets in the status register/interrupt register. - * - * @{ - */ -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) -# define _EVENTS_START_OFFSET_BUSY_BITS 16 -# define _EVENTS_START_OFFSET_USER_READY_BIT 0 -# define _EVENTS_START_OFFSET_DETECTION_BIT 16 -# define _EVENTS_START_OFFSET_OVERRUN_BIT 0 -#else /* SAM D/R */ -# define _EVENTS_START_OFFSET_BUSY_BITS 8 -# define _EVENTS_START_OFFSET_USER_READY_BIT 0 -# define _EVENTS_START_OFFSET_DETECTION_BIT 8 -# define _EVENTS_START_OFFSET_OVERRUN_BIT 0 -#endif -/** @} */ -///@endcond - -/** -* Definition for no generator selection. -*/ -#define EVSYS_ID_GEN_NONE 0 - -/** - * \brief Event channel resource. - * - * Event resource structure. - * - * \note The fields in this structure should not be altered by the user application; - * they are reserved for driver internals only. - */ -struct events_resource { -#if !defined(__DOXYGEN__) - /** Channel allocated for the event resource */ - uint8_t channel; - /** Channel setting in CHANNEL register */ - uint32_t channel_reg; -#endif -}; - -#if EVENTS_INTERRUPT_HOOKS_MODE == true -typedef void (*events_interrupt_hook)(struct events_resource *resource); - -/** - * \brief Event hook. - * - * Event hook structure. - * - */ -struct events_hook { - /** Event resource */ - struct events_resource *resource; - /** Event hook function */ - events_interrupt_hook hook_func; - /** Next event hook */ - struct events_hook *next; -}; -#endif - -/** - * \brief Initializes an event configurations struct to defaults. - * - * Initailizes an event configuration struct to predefined safe default settings. - * - * \param[in] config Pointer to an instance of \ref struct events_config - * - */ -void events_get_config_defaults(struct events_config *config); - -/** - * \brief Allocate an event channel and set configuration. - * - * Allocates an event channel from the event channel pool and sets - * the channel configuration. - * - * \param[out] resource Pointer to a \ref events_resource struct instance - * \param[in] config Pointer to a \ref events_config struct - * - * \return Status of the configuration procedure. - * \retval STATUS_OK Allocation and configuration went successful - * \retval STATUS_ERR_NOT_FOUND No free event channel found - * - */ -enum status_code events_allocate(struct events_resource *resource, struct events_config *config); - -/** - * \brief Attach user to the event channel. - * - * Attach a user peripheral to the event channel to receive events. - * - * \param[in] resource Pointer to an \ref events_resource struct instance - * \param[in] user_id A number identifying the user peripheral found in the device header file - * - * \return Status of the user attach procedure. - * \retval STATUS_OK No errors detected when attaching the event user - */ -enum status_code events_attach_user(struct events_resource *resource, uint8_t user_id); - -/** - * \brief Detach a user peripheral from the event channel. - * - * Deattach a user peripheral from the event channels so it does not receive any more events. - * - * \param[in] resource Pointer to an \ref event_resource struct instance - * \param[in] user_id A number identifying the user peripheral found in the device header file - * - * \return Status of the user detach procedure. - * \retval STATUS_OK No errors detected when detaching the event user - */ -enum status_code events_detach_user(struct events_resource *resource, uint8_t user_id); - -/** - * \brief Check if a channel is busy. - * - * Check if a channel is busy, a channel stays busy until all users connected to the channel - * has handled an event. - * - * \param[in] resource Pointer to a \ref events_resource struct instance - * - * \return Status of the channels busy state. - * \retval true One or more users connected to the channel has not handled the last event - * \retval false All users are ready to handle new events - */ -bool events_is_busy(struct events_resource *resource); - -/** - * \brief Trigger software event. - * - * Trigger an event by software. - * - * \note Software event works on either a synchronous path or resynchronized path, and - * edge detection must be configured to rising-edge detection. - * - * \param[in] resource Pointer to an \ref events_resource struct - * - * \return Status of the event software procedure. - * \retval STATUS_OK No error was detected when the software tigger signal was issued - * \retval STATUS_ERR_UNSUPPORTED_DEV If the channel path is asynchronous and/or the - * edge detection is not set to RISING - */ -enum status_code events_trigger(struct events_resource *resource); - -/** - * \brief Check if all users connected to the channel are ready. - * - * Check if all users connected to the channel are ready to handle incoming events. - * - * \param[in] resource Pointer to an \ref events_resource struct - * - * \return The ready status of users connected to an event channel. - * \retval true All the users connected to the event channel are ready to handle incoming events - * \retval false One or more users connected to the event channel are not ready to handle incoming events - */ -bool events_is_users_ready(struct events_resource *resource); - -/** - * \brief Check if an event is detected on the event channel. - * - * Check if an event has been detected on the channel. - * - * \note This function will clear the event detected interrupt flag. - * - * \param[in] resource Pointer to an \ref events_resource struct - * - * \return Status of the event detection interrupt flag. - * \retval true Event has been detected - * \retval false Event has not been detected - */ -bool events_is_detected(struct events_resource *resource); - -/** - * \brief Check if there has been an overrun situation on this channel. - * - * \note This function will clear the event overrun detected interrupt flag. - * - * \param[in] resource Pointer to an \ref events_resource struct - * - * \return Status of the event overrun interrupt flag. - * \retval true Event overrun has been detected - * \retval false Event overrun has not been detected - */ -bool events_is_overrun(struct events_resource *resource); - -/** - * \brief Release allocated channel back the the resource pool. - * - * Release an allocated channel back to the resource pool to make it available for other purposes. - * - * \param[in] resource Pointer to an \ref events_resource struct - * - * \return Status of the channel release procedure. - * \retval STATUS_OK No error was detected when the channel was released - * \retval STATUS_BUSY One or more event users have not processed the last event - * \retval STATUS_ERR_NOT_INITIALIZED Channel not allocated, and can therefore not be released - */ -enum status_code events_release(struct events_resource *resource); - -/** - * \brief Get the number of free channels. - * - * Get the number of allocatable channels in the events system resource pool. - * - * \return The number of free channels in the event system. - * - */ -uint8_t events_get_free_channels(void); - - -///@cond INTERNAL -/** - * \internal - * Function to find bit position in the CHSTATUS and INTFLAG register, - * and return bit mask of this position. - * - * @{ - */ -uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset); -/** @} */ -///@endcond - - -/** @} */ - -/** - * \page asfdoc_sam0_events_extra Extra Information for EVENTS Driver - * - * \section asfdoc_sam0_events_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
CPUCentral Processing Unit
MUXMultiplexer
- * - * - * \section asfdoc_sam0_events_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_clock_group "System Clock Driver" - * - * - * \section asfdoc_sam0_events_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_events_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Fix a bug in internal function _events_find_bit_position()
Rewrite of events driver
Initial Release
- */ - - /** - * \page asfdoc_sam0_events_exqsg Examples for EVENTS Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_events_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_events_basic_use_case - * \if EVENTS_INTERRUPT_HOOK_MODE - * - \subpage asfdoc_sam0_events_interrupt_hook_use_case - * \endif - * - * \page asfdoc_sam0_events_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42108G12/2015Added support for SAM D09 and SAM L22
42108F08/2015Added support for SAM L21, SAM DA1, SAMR30 and SAM C20/C21
42108E12/2014Added support for interrupt hook mode. - * Added support for SAM R21 and SAM D10/D11.
42108D01/2014Update to support SAM D21 and corrected documentation typos
42108C11/2013Fixed incorrect documentation for the event signal paths. Added - * configuration steps overview to the documentation.
42108B06/2013Corrected documentation typos
42108A06/2013Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* EVENTS_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/events/events_common.h b/atmel-samd/asf/sam0/drivers/events/events_common.h deleted file mode 100644 index b40db7cec8816..0000000000000 --- a/atmel-samd/asf/sam0/drivers/events/events_common.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * \file - * - * \brief SAM Event System Controller Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _EVENTS_COMMON_H_INCLUDED_ -#define _EVENTS_COMMON_H_INCLUDED_ - -/** - * \internal Internal module structure to manage necessary globals - * - * - */ -struct _events_module { - /* Allocated channels bitmask where 1 means allocated */ - volatile uint32_t allocated_channels; - /* Free channels */ - uint8_t free_channels; - -#if EVENTS_INTERRUPT_HOOKS_MODE == true - /* Buffer to store a copy of the current interrupt flags */ - volatile uint32_t interrupt_flag_buffer; - /* Buffer to store acknowledged interrupt sources */ - volatile uint32_t interrupt_flag_ack_buffer; - - /* Interrup hook linked list start pointer */ - struct events_hook *hook_list; -#endif -}; - -#endif diff --git a/atmel-samd/asf/sam0/drivers/events/events_hooks.c b/atmel-samd/asf/sam0/drivers/events/events_hooks.c deleted file mode 100644 index ee912b060e0a9..0000000000000 --- a/atmel-samd/asf/sam0/drivers/events/events_hooks.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * \file - * - * \brief SAM Event System Controller Driver - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "events.h" -#include "events_hooks.h" -#include "system_interrupt.h" - -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) -# define _EVENTS_INTFLAGS_DETECT 0x0fff0000 -# define _EVENTS_INTFLAGS_OVERRUN 0x00000fff -#else -# define _EVENTS_INTFLAGS_DETECT 0x0f00ff00 -# define _EVENTS_INTFLAGS_OVERRUN 0x000f00ff -#endif -#define _EVENTS_INTFLAGS_MASK (_EVENTS_INTFLAGS_DETECT | _EVENTS_INTFLAGS_OVERRUN) - -extern struct _events_module _events_inst; - -enum status_code events_create_hook(struct events_hook *hook, events_interrupt_hook func) -{ - /* Initialize the hook struct members */ - hook->next = NULL; - hook->resource = NULL; - hook->hook_func = func; - - return STATUS_OK; -} - -enum status_code events_add_hook(struct events_resource *resource, struct events_hook *hook) -{ - struct events_hook *tmp_hook = NULL; - - /* Associate the hook with the resource */ - hook->resource = resource; - - /* Check if this is the first hook in the list */ - if (_events_inst.hook_list == NULL) { - _events_inst.hook_list = hook; - } else { - tmp_hook = _events_inst.hook_list; - - /* Find the first free place in the list */ - while (tmp_hook->next != NULL) { - tmp_hook = tmp_hook->next; - } - - /* Put the hook into the next free place in the list */ - tmp_hook->next = hook; - } - - /* Check if interrupts from the EVSYS module is enabled in the interrupt controller */ - if (!system_interrupt_is_enabled(SYSTEM_INTERRUPT_MODULE_EVSYS)) { - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EVSYS); - } - - return STATUS_OK; -} - -enum status_code events_del_hook(struct events_resource *resource, struct events_hook *hook) -{ - struct events_hook *tmp_hook = _events_inst.hook_list; - struct events_hook *last_hook = NULL; - - if (tmp_hook != NULL) { - /* Check if the first hook in the list is the one we are looking for */ - if (tmp_hook != hook) { - /* Don't double check the first hook */ - tmp_hook = tmp_hook->next; - - /* Check if the current hook is the one we are looking for */ - while (tmp_hook != hook) { - - /* If the current hook pointer is NULL the hook is not found in the list */ - if(tmp_hook == NULL) { - return STATUS_ERR_NOT_FOUND; - } - - last_hook = tmp_hook; - tmp_hook = tmp_hook->next; - - } - /* Remove the current hook from the list */ - last_hook->next = tmp_hook->next; - } else { - _events_inst.hook_list = tmp_hook->next; - } - } else { - /* No hooks where found in the list */ - return STATUS_ERR_NO_MEMORY; - } - - return STATUS_OK; -} - -enum status_code events_enable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source) -{ - Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN)); - - if (source == EVENTS_INTERRUPT_DETECT) { - EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_DETECTION_BIT); - } else if (source == EVENTS_INTERRUPT_OVERRUN) { - EVSYS->INTENSET.reg = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_OVERRUN_BIT); - } else { - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -enum status_code events_disable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source) -{ - Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN)); - - if (source == EVENTS_INTERRUPT_DETECT) { - EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_DETECTION_BIT); - } else if (source == EVENTS_INTERRUPT_OVERRUN) { - EVSYS->INTENCLR.reg = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_OVERRUN_BIT); - } else { - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - - -bool events_is_interrupt_set(struct events_resource *resource, enum events_interrupt_source source) -{ - Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN)); - - uint32_t bitpos; - - if (source == EVENTS_INTERRUPT_DETECT) { - bitpos = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_DETECTION_BIT); - } else if (source == EVENTS_INTERRUPT_OVERRUN) { - bitpos = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_OVERRUN_BIT); - } else { - return false; - } - - return (bool)(_events_inst.interrupt_flag_buffer & bitpos); -} - -enum status_code events_ack_interrupt(struct events_resource *resource, enum events_interrupt_source source) -{ - Assert((source == EVENTS_INTERRUPT_DETECT) || (source == EVENTS_INTERRUPT_OVERRUN)); - - uint32_t bitpos; - - if (source == EVENTS_INTERRUPT_DETECT) { - bitpos = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_DETECTION_BIT); - } else if (source == EVENTS_INTERRUPT_OVERRUN) { - bitpos = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_OVERRUN_BIT); - } else { - return STATUS_ERR_INVALID_ARG; - } - - _events_inst.interrupt_flag_ack_buffer |= bitpos; - - return STATUS_OK; -} - -void EVSYS_Handler(void) -{ - struct events_hook *current_hook = _events_inst.hook_list; - uint32_t flag; - - /* Synch the interrupt flag buffer with the hardware register */ - flag = EVSYS->INTFLAG.reg; - _events_inst.interrupt_flag_buffer |= flag; - /* Clear all hardware interrupt flags */ - EVSYS->INTFLAG.reg = _EVENTS_INTFLAGS_MASK; - - /* Traverse the linked list */ - while (current_hook != NULL) { - current_hook->hook_func(current_hook->resource); - current_hook = current_hook->next; - } - - /* Clear acknowledged interrupt sources from the interrupt flag buffer */ - flag = _events_inst.interrupt_flag_ack_buffer; - _events_inst.interrupt_flag_buffer &= ~flag; -} - - - diff --git a/atmel-samd/asf/sam0/drivers/events/events_hooks.h b/atmel-samd/asf/sam0/drivers/events/events_hooks.h deleted file mode 100644 index f16e5e33630c9..0000000000000 --- a/atmel-samd/asf/sam0/drivers/events/events_hooks.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - * \file - * - * \brief SAM Event System Driver - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "events.h" - -#ifndef _EVENTS_HOOKS_H_INCLUDED_ -#define _EVENTS_HOOKS_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_events_group - * @{ - * - */ - -/** - * \brief Interrupt source enumerator. - * - * Interrupt source selector definitions. - * - */ -enum events_interrupt_source { - /** Overrun in event channel detected interrupt */ - EVENTS_INTERRUPT_OVERRUN, - /** Event signal propagation in event channel detected interrupt */ - EVENTS_INTERRUPT_DETECT, -}; - -/** - * \brief Initializes an interrupt hook for insertion in the event interrupt hook queue. - * - * Initializes a hook structure so it is ready for insertion in the interrupt hook queue. - * - * \param[out] hook Pointer to an \ref events_hook struct instance - * \param[in] hook_func Pointer to a function containing the interrupt hook code - * - * \return Status of the hook creation procedure. - * \retval STATUS_OK Creation and initialization of interrupt hook went successful - * - */ -enum status_code events_create_hook(struct events_hook *hook, events_interrupt_hook hook_func); - -/** - * \brief Insert hook into the event drivers interrupt hook queue. - * - * Inserts a hook into the event drivers interrupt hook queue. - * - * \param[in] resource Pointer to an \ref events_resource struct instance - * \param[in] hook Pointer to an \ref events_hook struct instance - * - * \return Status of the insertion procedure. - * \retval STATUS_OK Insertion of hook went successful - * - */ -enum status_code events_add_hook(struct events_resource *resource, struct events_hook *hook); - -/** - * \brief Remove hook from the event drivers interrupt hook queue. - * - * Removes a hook from the event drivers interrupt hook queue. - * - * \param[in] resource Pointer to an \ref events_resource struct instance - * \param[in] hook Pointer to an \ref events_hook struct instance - * - * \return Status of the removal procedure. - * \retval STATUS_OK Removal of hook went successful - * \retval STATUS_ERR_NO_MEMORY There are no hooks instances in the event driver interrupt hook list - * \retval STATUS_ERR_NOT_FOUND Interrupt hook not found in the event drivers interrupt hook list - * - */ -enum status_code events_del_hook(struct events_resource *resource, struct events_hook *hook); - -/** - * \brief Enable interrupt source. - * - * Enable an interrupt source so can trigger execution of an interrupt hook. - * - * \param[in] resource Pointer to an \ref events_resource struct instance - * \param[in] source One of the members in the \ref events_interrupt_source enumerator - * - * \return Status of the interrupt source enable procedure. - * \retval STATUS_OK Enabling of the interrupt source was successful - * \retval STATUS_ERR_INVALID_ARG Interrupt source does not exist - * - */ -enum status_code events_enable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source); - -/** - * \brief Disable interrupt source. - * - * Disable an interrupt source so can trigger execution of an interrupt hook. - * - * \param[in] resource Pointer to an \ref events_resource struct instance - * \param[in] source One of the members in the \ref events_interrupt_source enumerator - * - * \return Status of the interrupt source enable procedure. - * \retval STATUS_OK Enabling of the interrupt source went successful - * \retval STATUS_ERR_INVALID_ARG Interrupt source does not exist - * - */ -enum status_code events_disable_interrupt_source(struct events_resource *resource, enum events_interrupt_source source); - -/** - * \brief Check if interrupt source is set. - * - * Check if an interrupt source is set and should be processed. - * - * \param[in] resource Pointer to an \ref events_resource struct instance - * \param[in] source One of the members in the \ref events_interrupt_source enumerator - * - * \return Status of the interrupt source. - * \retval true Interrupt source is set - * \retval false Interrupt source is not set - * - */ -bool events_is_interrupt_set(struct events_resource *resource, enum events_interrupt_source source); - -/** - * \brief Acknowledge an interrupt source. - * - * Acknowledge an interrupt source so the interrupt state is cleared in hardware. - * - * \param[in] resource Pointer to an \ref events_resource struct instance - * \param[in] source One of the members in the \ref events_interrupt_source enumerator - * - * \return Status of the interrupt source. - * \retval STATUS_OK Interrupt source was acknowledged successfully - * - */ -enum status_code events_ack_interrupt(struct events_resource *resource, enum events_interrupt_source source); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf/sam0/drivers/events/events_sam_d_r/events.c b/atmel-samd/asf/sam0/drivers/events/events_sam_d_r/events.c deleted file mode 100644 index b2180b999dd99..0000000000000 --- a/atmel-samd/asf/sam0/drivers/events/events_sam_d_r/events.c +++ /dev/null @@ -1,328 +0,0 @@ -/* - * \file - * - * \brief SAM Event System Controller Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include -#include - -#define EVENTS_INVALID_CHANNEL 0xff - -struct _events_module _events_inst = { - .allocated_channels = 0, - .free_channels = EVSYS_CHANNELS, - -#if EVENTS_INTERRUPT_HOOKS_MODE == true - .interrupt_flag_buffer = 0, - .interrupt_flag_ack_buffer = 0, - - .hook_list = NULL, -#endif -}; - -/** - * \internal - * - */ -uint32_t _events_find_bit_position(uint8_t channel, uint8_t start_offset) -{ - uint32_t pos; - - if (channel < _EVENTS_START_OFFSET_BUSY_BITS) { - pos = 0x01UL << (start_offset + channel); - } else { - pos = 0x01UL << (start_offset + channel + _EVENTS_START_OFFSET_BUSY_BITS); - } - - return pos; -} - -static uint8_t _events_find_first_free_channel_and_allocate(void) -{ - uint8_t count; - uint32_t tmp; - bool allocated = false; - - system_interrupt_enter_critical_section(); - - tmp = _events_inst.allocated_channels; - - for(count = 0; count < EVSYS_CHANNELS; ++count) { - - if(!(tmp & 0x00000001)) { - /* If free channel found, set as allocated and return number */ - - _events_inst.allocated_channels |= 1 << count; - _events_inst.free_channels--; - allocated = true; - - break; - - } - - tmp = tmp >> 1; - } - - system_interrupt_leave_critical_section(); - - if(!allocated) { - return EVENTS_INVALID_CHANNEL; - } else { - return count; - } -} - -static void _events_release_channel(uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - _events_inst.allocated_channels &= ~(1 << channel); - _events_inst.free_channels++; - - system_interrupt_leave_critical_section(); -} - - -/* This function is called by the system_init function, but should not be a public API call */ -#if defined(__GNUC__) -# pragma GCC diagnostic push -# pragma GCC diagnostic ignored "-Wmissing-prototypes" -#endif -void _system_events_init(void) -{ - /* Enable EVSYS register interface */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_EVSYS); - - /* Make sure the EVSYS module is properly reset */ - EVSYS->CTRL.reg = EVSYS_CTRL_SWRST; - - while (EVSYS->CTRL.reg & EVSYS_CTRL_SWRST) { - } -} -#if defined(__GNUC__) -# pragma GCC diagnostic pop -#endif - -void events_get_config_defaults(struct events_config *config) -{ - /* Check that config is something other than NULL */ - Assert(config); - - config->edge_detect = EVENTS_EDGE_DETECT_RISING; - config->path = EVENTS_PATH_SYNCHRONOUS; - config->generator = EVSYS_ID_GEN_NONE; - config->clock_source = GCLK_GENERATOR_0; -} - -enum status_code events_allocate( - struct events_resource *resource, - struct events_config *config) -{ - uint8_t new_channel; - - Assert(resource); - - new_channel = _events_find_first_free_channel_and_allocate(); - - if(new_channel == EVENTS_INVALID_CHANNEL) { - return STATUS_ERR_NOT_FOUND; - } - - resource->channel = new_channel; - - if (config->path != EVENTS_PATH_ASYNCHRONOUS) { - /* Set up a GLCK channel to use with the specific channel */ - struct system_gclk_chan_config gclk_chan_conf; - - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = - (enum gclk_generator)config->clock_source; - system_gclk_chan_set_config(EVSYS_GCLK_ID_0 + new_channel, &gclk_chan_conf); - system_gclk_chan_enable(EVSYS_GCLK_ID_0 + new_channel); - } - - /* Save channel setting and configure it after user multiplexer */ - resource->channel_reg = EVSYS_CHANNEL_CHANNEL(new_channel) | - EVSYS_CHANNEL_EVGEN(config->generator) | - EVSYS_CHANNEL_PATH(config->path) | - EVSYS_CHANNEL_EDGSEL(config->edge_detect); - - - return STATUS_OK; -} - - -enum status_code events_release(struct events_resource *resource) -{ - enum status_code err = STATUS_OK; - - Assert(resource); - - /* Check if channel is busy */ - if(events_is_busy(resource)) { - return STATUS_BUSY; - } - - if (!(_events_inst.allocated_channels & (1<channel))) { - err = STATUS_ERR_NOT_INITIALIZED; - } else { - _events_release_channel(resource->channel); - } - - return err; -} - -enum status_code events_trigger(struct events_resource *resource) -{ - - Assert(resource); - - system_interrupt_enter_critical_section(); - - /* Because of indirect access the channel must be set first */ - ((uint8_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel); - - /* Assert if event path is asynchronous */ - if (EVSYS->CHANNEL.reg & EVSYS_CHANNEL_PATH(EVENTS_PATH_ASYNCHRONOUS)) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Assert if event edge detection is not set to RISING */ - if (!(EVSYS->CHANNEL.reg & EVSYS_CHANNEL_EDGSEL(EVENTS_EDGE_DETECT_RISING))) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - - /* The GCLKREQ bit has to be set while triggering the software event */ - EVSYS->CTRL.reg = EVSYS_CTRL_GCLKREQ; - - ((uint16_t*)&EVSYS->CHANNEL)[0] = EVSYS_CHANNEL_CHANNEL(resource->channel) | - EVSYS_CHANNEL_SWEVT; - - EVSYS->CTRL.reg &= ~EVSYS_CTRL_GCLKREQ; - - system_interrupt_leave_critical_section(); - - return STATUS_OK; -} - -bool events_is_busy(struct events_resource *resource) -{ - Assert(resource); - - return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_BUSY_BITS)); -} - -bool events_is_users_ready(struct events_resource *resource) -{ - Assert(resource); - - return EVSYS->CHSTATUS.reg & (_events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_USER_READY_BIT)); -} - -bool events_is_detected(struct events_resource *resource) -{ - Assert(resource); - - uint32_t flag = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_DETECTION_BIT); - - /* Clear flag when read */ - if (EVSYS->INTFLAG.reg & flag) { - EVSYS->INTFLAG.reg = flag; - return true; - } - - return false; -} - -bool events_is_overrun(struct events_resource *resource) -{ - Assert(resource); - - uint32_t flag = _events_find_bit_position(resource->channel, - _EVENTS_START_OFFSET_OVERRUN_BIT); - - /* Clear flag when read */ - if (EVSYS->INTFLAG.reg & flag) { - EVSYS->INTFLAG.reg = flag; - return true; - } - - return false; -} - -enum status_code events_attach_user(struct events_resource *resource, uint8_t user_id) -{ - Assert(resource); - - /* First configure user multiplexer: channel number is n + 1 */ - EVSYS->USER.reg = EVSYS_USER_CHANNEL(resource->channel + 1) | - EVSYS_USER_USER(user_id); - - /* Then configure the channel */ - EVSYS->CHANNEL.reg = resource->channel_reg; - - return STATUS_OK; -} - -enum status_code events_detach_user(struct events_resource *resource, uint8_t user_id) -{ - - Assert(resource); - - /* Write 0 to the channel bit field to select no input */ - EVSYS->USER.reg = EVSYS_USER_USER(user_id); - - return STATUS_OK; -} - -uint8_t events_get_free_channels() -{ - return _events_inst.free_channels; -} diff --git a/atmel-samd/asf/sam0/drivers/extint/extint.h b/atmel-samd/asf/sam0/drivers/extint/extint.h deleted file mode 100644 index a40fd512cf722..0000000000000 --- a/atmel-samd/asf/sam0/drivers/extint/extint.h +++ /dev/null @@ -1,707 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef EXTINT_H_INCLUDED -#define EXTINT_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_extint_group SAM External Interrupt (EXTINT) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of external interrupts - * generated by the physical device pins, including edge detection. - * The following driver API modes are covered by this - * manual: - * - * - Polled APIs - * \if EXTINT_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - EIC (External Interrupt Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_extint_prerequisites - * - \ref asfdoc_sam0_extint_module_overview - * - \ref asfdoc_sam0_extint_special_considerations - * - \ref asfdoc_sam0_extint_extra_info - * - \ref asfdoc_sam0_extint_examples - * - \ref asfdoc_sam0_extint_api_overview - * - * - * \section asfdoc_sam0_extint_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_extint_module_overview Module Overview - * - * The External Interrupt (EXTINT) module provides a method of asynchronously - * detecting rising edge, falling edge, or specific level detection on individual - * I/O pins of a device. This detection can then be used to trigger a software - * interrupt or event, or polled for later use if required. External interrupts - * can also optionally be used to automatically wake up the device from sleep - * mode, allowing the device to conserve power while still being able to react - * to an external stimulus in a timely manner. - * - * \subsection asfdoc_sam0_extint_logical_channels Logical Channels - * The External Interrupt module contains a number of logical channels, each of - * which is capable of being individually configured for a given pin routing, - * detection mode, and filtering/wake up characteristics. - * - * Each individual logical external interrupt channel may be routed to a single - * physical device I/O pin in order to detect a particular edge or level of the - * incoming signal. - * - * \subsection asfdoc_sam0_extint_module_overview_nmi_chanel NMI Channels - * - * One or more Non Maskable Interrupt (NMI) channels are provided within each - * physical External Interrupt Controller module, allowing a single physical pin - * of the device to fire a single NMI interrupt in response to a particular - * edge or level stimulus. An NMI cannot, as the name suggests, be disabled in - * firmware and will take precedence over any in-progress interrupt sources. - * - * NMIs can be used to implement critical device features such as forced - * software reset or other functionality where the action should be executed in - * preference to all other running code with a minimum amount of latency. - * - * \subsection asfdoc_sam0_extint_module_overview_filtering Input Filtering and Detection - * - * To reduce the possibility of noise or other transient signals causing - * unwanted device wake-ups, interrupts, and/or events via an external interrupt - * channel. A hardware signal filter can be enabled on individual channels. This - * filter provides a Majority-of-Three voter filter on the incoming signal, so - * that the input state is considered to be the majority vote of three - * subsequent samples of the pin input buffer. The possible sampled input and - * resulting filtered output when the filter is enabled is shown in - * \ref asfdoc_sam0_extint_filter_table "the table below". - * - * \anchor asfdoc_sam0_extint_filter_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Sampled Input and Resulting Filtered Output
Input Sample 1Input Sample 2Input Sample 3Filtered Output
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
- * - * \subsection asfdoc_sam0_extint_module_overview_events Events and Interrupts - * - * Channel detection states may be polled inside the application for synchronous - * detection, or events and interrupts may be used for asynchronous behavior. - * Each channel can be configured to give an asynchronous hardware event (which - * may in turn trigger actions in other hardware modules) or an asynchronous - * software interrupt. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * \subsection asfdoc_sam0_extint_module_overview_physical Physical Connection - * - * \ref asfdoc_sam0_extint_int_connections "The diagram below" shows how this - * module is interconnected within the device. - * - * \anchor asfdoc_sam0_extint_int_connections - * \dot - * digraph overview { - * node [label="Port Pad" shape=square] pad; - * - * subgraph driver { - * node [label="Peripheral MUX" shape=trapezium] pinmux; - * node [label="EIC Module" shape=ellipse] eic; - * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals; - * } - * - * pinmux -> eic; - * pad -> pinmux; - * pinmux -> peripherals; - * } - * \enddot - * - * \section asfdoc_sam0_extint_special_considerations Special Considerations - * - * Not all devices support disabling of the NMI channel(s) detection mode - see - * your device datasheet. - * - * - * \section asfdoc_sam0_extint_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_extint_extra. This includes: - * - \ref asfdoc_sam0_extint_extra_acronyms - * - \ref asfdoc_sam0_extint_extra_dependencies - * - \ref asfdoc_sam0_extint_extra_errata - * - \ref asfdoc_sam0_extint_extra_history - * - * - * \section asfdoc_sam0_extint_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_extint_exqsg. - * - * - * \section asfdoc_sam0_extint_api_overview API Overview - * @{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief External interrupt edge detection configuration enum. - * - * Enum for the possible signal edge detection modes of the External - * Interrupt Controller module. - */ -enum extint_detect { - /** No edge detection. Not allowed as a NMI detection mode on some - * devices. */ - EXTINT_DETECT_NONE = 0, - /** Detect rising signal edges */ - EXTINT_DETECT_RISING = 1, - /** Detect falling signal edges */ - EXTINT_DETECT_FALLING = 2, - /** Detect both signal edges */ - EXTINT_DETECT_BOTH = 3, - /** Detect high signal levels */ - EXTINT_DETECT_HIGH = 4, - /** Detect low signal levels */ - EXTINT_DETECT_LOW = 5, -}; - -/** - * \brief External interrupt internal pull configuration enum. - * - * Enum for the possible pin internal pull configurations. - * - * \note Disabling the internal pull resistor is not recommended if the driver - * is used in interrupt (callback) mode, due the possibility of floating - * inputs generating continuous interrupts. - */ -enum extint_pull { - /** Internal pull-up resistor is enabled on the pin */ - EXTINT_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, - /** Internal pull-down resistor is enabled on the pin */ - EXTINT_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, - /** Internal pull resistor is disconnected from the pin */ - EXTINT_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, -}; - -/** The EIC is clocked by GCLK_EIC. */ -#define EXTINT_CLK_GCLK 0 -/** The EIC is clocked by CLK_ULP32K. */ -#define EXTINT_CLK_ULP32K 1 - -/** - * \brief External Interrupt Controller channel configuration structure. - * - * Configuration structure for the edge detection mode of an external - * interrupt channel. - */ -struct extint_chan_conf { - /** GPIO pin the NMI should be connected to */ - uint32_t gpio_pin; - /** MUX position the GPIO pin should be configured to */ - uint32_t gpio_pin_mux; - /** Internal pull to enable on the input pin */ - enum extint_pull gpio_pin_pull; -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - /** Enable asynchronous edge detection. */ - bool enable_async_edge_detection; -#else - /** Wake up the device if the channel interrupt fires during sleep mode */ - bool wake_if_sleeping; -#endif - /** Filter the raw input signal to prevent noise from triggering an - * interrupt accidentally, using a three sample majority filter */ - bool filter_input_signal; - /** Edge detection mode to use */ - enum extint_detect detection_criteria; -}; - -/** - * \brief External Interrupt event enable/disable structure. - * - * Event flags for the \ref extint_enable_events() and - * \ref extint_disable_events(). - */ -struct extint_events { - /** If \c true, an event will be generated when an external interrupt - * channel detection state changes */ - bool generate_event_on_detect[32 * EIC_INST_NUM]; -}; - -/** - * \brief External Interrupt Controller NMI configuration structure. - * - * Configuration structure for the edge detection mode of an external - * interrupt NMI channel. - */ -struct extint_nmi_conf { - /** GPIO pin the NMI should be connected to */ - uint32_t gpio_pin; - /** MUX position the GPIO pin should be configured to */ - uint32_t gpio_pin_mux; - /** Internal pull to enable on the input pin */ - enum extint_pull gpio_pin_pull; - /** Filter the raw input signal to prevent noise from triggering an - * interrupt accidentally, using a three sample majority filter */ - bool filter_input_signal; - /** Edge detection mode to use. Not all devices support all possible - * detection modes for NMIs. - */ - enum extint_detect detection_criteria; -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - /** Enable asynchronous edge detection. */ - bool enable_async_edge_detection; -#endif -}; - -#if EXTINT_CALLBACK_MODE == true -/** Type definition for an EXTINT module callback function */ -typedef void (*extint_callback_t)(void); - -#ifndef EIC_NUMBER_OF_INTERRUPTS -# define EIC_NUMBER_OF_INTERRUPTS 16 -#endif -#endif - -#if !defined(__DOXYGEN__) -/** \internal - * Internal EXTINT module device instance structure definition. - */ -struct _extint_module -{ -# if EXTINT_CALLBACK_MODE == true - /** Asynchronous channel callback table, for user-registered handlers */ - extint_callback_t callbacks[EIC_NUMBER_OF_INTERRUPTS]; -# else - /** Dummy value to ensure the struct has at least one member */ - uint8_t _dummy; -# endif -}; - -/** - * \brief Retrieves the base EIC module address from a given channel number. - * - * Retrieves the base address of a EIC hardware module associated with the - * given external interrupt channel. - * - * \param[in] channel External interrupt channel index to convert - * - * \return Base address of the associated EIC module. - */ -static inline Eic * _extint_get_eic_from_channel( - const uint8_t channel) -{ - uint8_t eic_index = (channel / 32); - - if (eic_index < EIC_INST_NUM) { - /* Array of available EICs */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - return eics[eic_index]; - } else { - Assert(false); - return NULL; - } -} - -/** - * \brief Retrieves the base EIC module address from a given NMI channel number. - * - * Retrieves the base address of a EIC hardware module associated with the - * given non-maskable external interrupt channel. - * - * \param[in] nmi_channel Non-Maskable interrupt channel index to convert - * - * \return Base address of the associated EIC module. - */ -static inline Eic * _extint_get_eic_from_nmi( - const uint8_t nmi_channel) -{ - uint8_t eic_index = nmi_channel; - - if (eic_index < EIC_INST_NUM) { - /* Array of available EICs */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - return eics[eic_index]; - } else { - Assert(false); - return NULL; - } -} -#endif - -/** \name Event Management - * @{ - */ - -void extint_enable_events( - struct extint_events *const events); - -void extint_disable_events( - struct extint_events *const events); - -/** @} */ - -/** \name Configuration and Initialization (Channel) - * @{ - */ - -void extint_chan_get_config_defaults( - struct extint_chan_conf *const config); - -void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config); - -/** @} */ - -/** \name Configuration and Initialization (NMI) - * @{ - */ - -/** - * \brief Initializes an External Interrupt NMI channel configuration structure to defaults. - * - * Initializes a given External Interrupt NMI channel configuration structure - * to a set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Input filtering disabled - * \li Detect falling edges of a signal - * \li Asynchronous edge detection is disabled - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void extint_nmi_get_config_defaults( - struct extint_nmi_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - config->enable_async_edge_detection = false; -#endif - -} - -enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config); - -/** @} */ - -/** \name Detection testing and clearing (channel) - * @{ - */ - -/** - * \brief Retrieves the edge detection state of a configured channel. - * - * Reads the current state of a configured channel, and determines - * if the detection criteria of the channel has been met. - * - * \param[in] channel External Interrupt channel index to check - * - * \return Status of the requested channel's edge detection state. - * \retval true If the channel's edge/level detection criteria was met - * \retval false If the channel has not detected its configured criteria - */ -static inline bool extint_chan_is_detected( - const uint8_t channel) -{ - Eic *const eic_module = _extint_get_eic_from_channel(channel); - uint32_t eic_mask = (1UL << (channel % 32)); - - return (eic_module->INTFLAG.reg & eic_mask); -} - -/** - * \brief Clears the edge detection state of a configured channel. - * - * Clears the current state of a configured channel, readying it for - * the next level or edge detection. - * - * \param[in] channel External Interrupt channel index to check - */ -static inline void extint_chan_clear_detected( - const uint8_t channel) -{ - Eic *const eic_module = _extint_get_eic_from_channel(channel); - uint32_t eic_mask = (1UL << (channel % 32)); - - eic_module->INTFLAG.reg = eic_mask; -} - -/** @} */ - -/** \name Detection Testing and Clearing (NMI) - * @{ - */ - -/** - * \brief Retrieves the edge detection state of a configured NMI channel. - * - * Reads the current state of a configured NMI channel, and determines - * if the detection criteria of the NMI channel has been met. - * - * \param[in] nmi_channel External Interrupt NMI channel index to check - * - * \return Status of the requested NMI channel's edge detection state. - * \retval true If the NMI channel's edge/level detection criteria was met - * \retval false If the NMI channel has not detected its configured criteria - */ -static inline bool extint_nmi_is_detected( - const uint8_t nmi_channel) -{ - Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); - - return (eic_module->NMIFLAG.reg & EIC_NMIFLAG_NMI); -} - -/** - * \brief Clears the edge detection state of a configured NMI channel. - * - * Clears the current state of a configured NMI channel, readying it for - * the next level or edge detection. - * - * \param[in] nmi_channel External Interrupt NMI channel index to check - */ -static inline void extint_nmi_clear_detected( - const uint8_t nmi_channel) -{ - Eic *const eic_module = _extint_get_eic_from_nmi(nmi_channel); - - eic_module->NMIFLAG.reg = EIC_NMIFLAG_NMI; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#if EXTINT_CALLBACK_MODE == true -# include "extint_callback.h" -#endif - -/** - * \page asfdoc_sam0_extint_extra Extra Information for EXTINT Driver - * - * \section asfdoc_sam0_extint_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
EICExternal Interrupt Controller
MUXMultiplexer
NMINon-Maskable Interrupt
- * - * - * \section asfdoc_sam0_extint_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_extint_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_extint_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
- * \li Driver updated to follow driver type convention - * \li Removed \c %extint_reset(), \c %extint_disable() and - * \c extint_enable() functions. Added internal function - * \c %_system_extint_init(). - * \li Added configuration EXTINT_CLOCK_SOURCE in conf_extint.h - * \li Removed configuration EXTINT_CALLBACKS_MAX in conf_extint.h, and - * added channel parameter in the register functions - * \c %extint_register_callback() and \c %extint_unregister_callback() - *
Updated interrupt handler to clear interrupt flag before calling - * callback function
Updated initialization function to also enable the digital interface - * clock to the module if it is disabled
Initial Release
- */ - -/** - * \page asfdoc_sam0_extint_exqsg Examples for EXTINT Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_extint_group. - * QSGs are simple examples with step-by-step instructions to configure and - * use this driver in a selection of use cases. Note that a QSG can be compiled - * as a standalone application or be added to the user application. - * - * - \subpage asfdoc_sam0_extint_basic_use_case - * \if EXTINT_CALLBACK_MODE - * - \subpage asfdoc_sam0_extint_callback_use_case - * \endif - * - * \page asfdoc_sam0_extint_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42112E12/2015Added support for SAM L21/L22, SAM C21, SAM D09, and SAM DA1
42112D12/2014Added support for SAM R21 and SAM D10/D11
42112C01/2014Added support for SAM D21
42112B06/2013Added additional documentation on the event system. Corrected - * documentation typos.
42112A06/2013Initial release
- */ - -#endif diff --git a/atmel-samd/asf/sam0/drivers/extint/extint_callback.c b/atmel-samd/asf/sam0/drivers/extint/extint_callback.c deleted file mode 100644 index 52424d7863a78..0000000000000 --- a/atmel-samd/asf/sam0/drivers/extint/extint_callback.c +++ /dev/null @@ -1,232 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "extint.h" -#include "extint_callback.h" - -/** - * \internal - * Internal driver device instance struct, declared in the main module driver. - */ -extern struct _extint_module _extint_dev; - -/** - * \internal - * This is the number of the channel whose callback is currently running. - */ -uint8_t _current_channel; - -/** - * \brief Registers an asynchronous callback function with the driver. - * - * Registers an asynchronous callback with the EXTINT driver, fired when a - * channel detects the configured channel detection criteria - * (e.g. edge or level). Callbacks are fired once for each detected channel. - * - * \note NMI channel callbacks cannot be registered via this function; the - * device's NMI interrupt should be hooked directly in the user - * application and the NMI flags manually cleared via - * \ref extint_nmi_clear_detected(). - * - * \param[in] callback Pointer to the callback function to register - * \param[in] channel Logical channel to register callback for - * \param[in] type Type of callback function to register - * - * \return Status of the registration operation. - * \retval STATUS_OK The callback was registered successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - * \retval STATUS_ERR_ALREADY_INITIALIZED Callback function has been - * registered, need unregister first - */ -enum status_code extint_register_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type) -{ - /* Sanity check arguments */ - Assert(callback); - - if (type != EXTINT_CALLBACK_TYPE_DETECT) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - if (_extint_dev.callbacks[channel] == NULL) { - _extint_dev.callbacks[channel] = callback; - return STATUS_OK; - } else if (_extint_dev.callbacks[channel] == callback) { - return STATUS_OK; - } - - return STATUS_ERR_ALREADY_INITIALIZED; -} - -/** - * \brief Unregisters an asynchronous callback function with the driver. - * - * Unregisters an asynchronous callback with the EXTINT driver, removing it - * from the internal callback registration table. - * - * \param[in] callback Pointer to the callback function to unregister - * \param[in] channel Logical channel to unregister callback for - * \param[in] type Type of callback function to unregister - * - * \return Status of the de-registration operation. - * \retval STATUS_OK The callback was unregistered successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - * \retval STATUS_ERR_BAD_ADDRESS No matching entry was found in the - * registration table - */ -enum status_code extint_unregister_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type) -{ - /* Sanity check arguments */ - Assert(callback); - - if (type != EXTINT_CALLBACK_TYPE_DETECT) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - if (_extint_dev.callbacks[channel] == callback) { - _extint_dev.callbacks[channel] = NULL; - return STATUS_OK; - } - - return STATUS_ERR_BAD_ADDRESS; -} - -/** - * \brief Enables asynchronous callback generation for a given channel and type. - * - * Enables asynchronous callbacks for a given logical external interrupt channel - * and type. This must be called before an external interrupt channel will - * generate callback events. - * - * \param[in] channel Logical channel to enable callback generation for - * \param[in] type Type of callback function callbacks to enable - * - * \return Status of the callback enable operation. - * \retval STATUS_OK The callback was enabled successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - */ -enum status_code extint_chan_enable_callback( - const uint8_t channel, - const enum extint_callback_type type) -{ - if (type == EXTINT_CALLBACK_TYPE_DETECT) { - Eic *const eic = _extint_get_eic_from_channel(channel); - - eic->INTENSET.reg = (1UL << channel); - } - else { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Disables asynchronous callback generation for a given channel and type. - * - * Disables asynchronous callbacks for a given logical external interrupt - * channel and type. - * - * \param[in] channel Logical channel to disable callback generation for - * \param[in] type Type of callback function callbacks to disable - * - * \return Status of the callback disable operation. - * \retval STATUS_OK The callback was disabled successfully - * \retval STATUS_ERR_INVALID_ARG If an invalid callback type was supplied - */ -enum status_code extint_chan_disable_callback( - const uint8_t channel, - const enum extint_callback_type type) -{ - if (type == EXTINT_CALLBACK_TYPE_DETECT) { - Eic *const eic = _extint_get_eic_from_channel(channel); - - eic->INTENCLR.reg = (1UL << channel); - } - else { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Find what channel caused the callback. - * - * Can be used in an EXTINT callback function to find what channel caused - * the callback in case the same callback is used by multiple channels. - * - * \return Channel number. - */ -uint8_t extint_get_current_channel(void) -{ - return _current_channel; -} - -/** Handler for the EXTINT hardware module interrupt. */ -void EIC_Handler(void) -{ - /* Find any triggered channels, run associated callback handlers */ - for (_current_channel = 0; _current_channel < EIC_NUMBER_OF_INTERRUPTS ; _current_channel++) { - if (extint_chan_is_detected(_current_channel)) { - /* Clear flag */ - extint_chan_clear_detected(_current_channel); - /* Find any associated callback entries in the callback table */ - if (_extint_dev.callbacks[_current_channel] != NULL) { - /* Run the registered callback */ - _extint_dev.callbacks[_current_channel](); - } - } - } -} diff --git a/atmel-samd/asf/sam0/drivers/extint/extint_callback.h b/atmel-samd/asf/sam0/drivers/extint/extint_callback.h deleted file mode 100644 index 35cf23018554b..0000000000000 --- a/atmel-samd/asf/sam0/drivers/extint/extint_callback.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef EXTINT_CALLBACK_H_INCLUDED -#define EXTINT_CALLBACK_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_extint_group - * - * @{ - */ - -/** \name Callback Configuration and Initialization - * @{ - */ - -/** Enum for the possible callback types for the EXTINT module. */ -enum extint_callback_type -{ - /** Callback type for when an external interrupt detects the configured - * channel criteria (i.e. edge or level detection) - */ - EXTINT_CALLBACK_TYPE_DETECT, -}; - -enum status_code extint_register_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type); - -enum status_code extint_unregister_callback( - const extint_callback_t callback, - const uint8_t channel, - const enum extint_callback_type type); - -uint8_t extint_get_current_channel(void); - -/** @} */ - -/** \name Callback Enabling and Disabling (Channel) - * @{ - */ - -enum status_code extint_chan_enable_callback( - const uint8_t channel, - const enum extint_callback_type type); - -enum status_code extint_chan_disable_callback( - const uint8_t channel, - const enum extint_callback_type type); - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf/sam0/drivers/extint/extint_sam_d_r/extint.c b/atmel-samd/asf/sam0/drivers/extint/extint_sam_d_r/extint.c deleted file mode 100644 index a9697d0e6fe21..0000000000000 --- a/atmel-samd/asf/sam0/drivers/extint/extint_sam_d_r/extint.c +++ /dev/null @@ -1,425 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include -#include - -#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__) -# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0. - -/** Configuration option, setting the EIC clock source which can be used for - * EIC edge detection or filtering. This option may be overridden in the module - * configuration header file \c conf_extint.h. - */ -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 -#endif - -/** - * \internal - * Internal driver device instance struct. - */ -struct _extint_module _extint_dev; - -/** - * \brief Determin if the general clock is required - * - * \param[in] filter_input_signal Filter the raw input signal to prevent noise - * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect) - */ -#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \ - ((filter_input_signal) ? true : (\ - (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false)))) - -static void _extint_enable(void); -static void _extint_disable(void); - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -static inline bool extint_is_syncing(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - if (eics[i]->STATUS.reg & EIC_STATUS_SYNCBUSY) { - return true; - } - } - return false; -} -/** - * \internal - * \brief Initializes and enables the External Interrupt driver. - * - * Enable the clocks used by External Interrupt driver. - * - * Resets the External Interrupt driver, resetting all hardware - * module registers to their power-on defaults, then enable it for further use. - * - * Reset the callback list if callback mode is used. - * - * This function must be called before attempting to use any NMI or standard - * external interrupt channel functions. - * - * \note When SYSTEM module is used, this function will be invoked by - * \ref system_init() automatically if the module is included. - */ -void _system_extint_init(void); -void _system_extint_init(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_EIC); - - /* Configure the generic clock for the module and enable it */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; - system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); - - /* Enable the clock anyway, since when needed it will be requested - * by External Interrupt driver */ - system_gclk_chan_enable(EIC_GCLK_ID); - - /* Reset all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_SWRST; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } - - /* Reset the software module */ -#if EXTINT_CALLBACK_MODE == true - /* Clear callback registration table */ - for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { - _extint_dev.callbacks[j] = NULL; - } - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); -#endif - - /* Enables the driver for further use */ - _extint_enable(); -} - -/** - * \internal - * \brief Enables the External Interrupt driver. - * - * Enables EIC modules. - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_enable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Enable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg |= EIC_CTRL_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \internal - * \brief Disables the External Interrupt driver. - * - * Disables EIC modules that were previously started via a call to - * \ref _extint_enable(). - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_disable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Disable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRL.reg &= ~EIC_CTRL_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \brief Initializes an External Interrupt channel configuration structure to defaults. - * - * Initializes a given External Interrupt channel configuration structure to a - * set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Wake the device if an edge detection occurs whilst in sleep - * \li Input filtering disabled - * \li Internal pull-up enabled - * \li Detect falling edges of a signal - * - * \param[out] config Configuration structure to initialize to default values - */ -void extint_chan_get_config_defaults( - struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->wake_if_sleeping = true; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; -} - -/** - * \brief Writes an External Interrupt channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] channel External Interrupt channel to configure - * \param[in] config Configuration settings for the channel - - */ -void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(channel); - - uint32_t config_pos = (4 * (channel % 8)); - uint32_t new_config; - - /* Determine the channel's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_CONFIG_FILTEN0; - } - - /* Clear the existing and set the new channel configuration */ - EIC_module->CONFIG[channel / 8].reg - = (EIC_module->CONFIG[channel / 8].reg & - ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | - (new_config << config_pos); - - /* Set the channel's new wake up mode setting */ - if (config->wake_if_sleeping) { - EIC_module->WAKEUP.reg |= (1UL << channel); - } else { - EIC_module->WAKEUP.reg &= ~(1UL << channel); - } -} - -/** - * \brief Writes an External Interrupt NMI channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt NMI channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] nmi_channel External Interrupt NMI channel to configure - * \param[in] config Configuration settings for the channel - * - * \returns Status code indicating the success or failure of the request. - * \retval STATUS_OK Configuration succeeded - * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pinmux value was supplied - * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested - */ -enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); - - uint32_t new_config; - - /* Determine the NMI's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_NMICTRL_NMIFILTEN; - } - - /* Disable EIC and general clock to configure NMI */ - _extint_disable(); - system_gclk_chan_disable(EIC_GCLK_ID); - - EIC_module->NMICTRL.reg = new_config; - - /* Enable the general clock and EIC after configure NMI */ - system_gclk_chan_enable(EIC_GCLK_ID); - _extint_enable(); - - return STATUS_OK; -} - -/** - * \brief Enables an External Interrupt event output. - * - * Enables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to enable - */ -void extint_enable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create an enable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Enable the masked events */ - eics[i]->EVCTRL.reg |= event_mask; - } -} - -/** - * \brief Disables an External Interrupt event output. - * - * Disables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to disable - */ -void extint_disable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create a disable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Disable the masked events */ - eics[i]->EVCTRL.reg &= ~event_mask; - } -} diff --git a/atmel-samd/asf/sam0/drivers/extint/extint_sam_l_c/extint.c b/atmel-samd/asf/sam0/drivers/extint/extint_sam_l_c/extint.c deleted file mode 100644 index 1f5236222e058..0000000000000 --- a/atmel-samd/asf/sam0/drivers/extint/extint_sam_l_c/extint.c +++ /dev/null @@ -1,491 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include -#include - -#if !defined(EXTINT_CLOCK_SELECTION) || defined(__DOXYGEN__) -# warning EXTINT_CLOCK_SELECTION is not defined, assuming EXTINT_CLK_GCLK. - -/** Configuration option, setting the EIC clock source which can be used for - * EIC edge detection or filtering. This option may be overridden in the module - * configuration header file \c conf_extint.h. - */ -# define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK -#endif - -#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) -#if !defined(EXTINT_CLOCK_SOURCE) || defined(__DOXYGEN__) -# warning EXTINT_CLOCK_SOURCE is not defined, assuming GCLK_GENERATOR_0. - -/** Configuration option, setting the EIC clock source which can be used for - * EIC edge detection or filtering. This option may be overridden in the module - * configuration header file \c conf_extint.h. - */ -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 -#endif -#endif - -/** - * \internal - * Internal driver device instance struct. - */ -struct _extint_module _extint_dev; - -/** - * \brief Determin if the general clock is required. - * - * \param[in] filter_input_signal Filter the raw input signal to prevent noise - * \param[in] detection_criteria Edge detection mode to use (\ref extint_detect) - */ -#define _extint_is_gclk_required(filter_input_signal, detection_criteria) \ - ((filter_input_signal) ? true : (\ - (EXTINT_DETECT_RISING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_FALLING == (detection_criteria)) ? true : (\ - (EXTINT_DETECT_BOTH == (detection_criteria)) ? true : false)))) - -static void _extint_enable(void); -static void _extint_disable(void); - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval true If the module synchronization is ongoing - * \retval false If the module has completed synchronization - */ -static inline bool extint_is_syncing(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - if((eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) - || (eics[i]->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST)){ - return true; - } - } - return false; -} - -/** - * \internal - * \brief Initializes and enables the External Interrupt driver. - * - * Enable the clocks used by External Interrupt driver. - * - * Resets the External Interrupt driver, resetting all hardware - * module registers to their power-on defaults, then enable it for further use. - * - * Reset the callback list if callback mode is used. - * - * This function must be called before attempting to use any NMI or standard - * external interrupt channel functions. - * - * \note When SYSTEM module is used, this function will be invoked by - * \ref system_init() automatically if the module is included. - */ -void _system_extint_init(void); -void _system_extint_init(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, MCLK_APBAMASK_EIC); - -#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - /* Configure the generic clock for the module and enable it */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = EXTINT_CLOCK_SOURCE; - system_gclk_chan_set_config(EIC_GCLK_ID, &gclk_chan_conf); - - /* Enable the clock anyway, since when needed it will be requested - * by External Interrupt driver */ - system_gclk_chan_enable(EIC_GCLK_ID); -#endif - - /* Reset all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.reg |= EIC_CTRLA_SWRST; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } - -#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK; - } -#else - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K; - } -#endif - - /* Reset the software module */ -#if EXTINT_CALLBACK_MODE == true - /* Clear callback registration table */ - for (uint8_t j = 0; j < EIC_NUMBER_OF_INTERRUPTS; j++) { - _extint_dev.callbacks[j] = NULL; - } - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_EIC); -#endif - - /* Enables the driver for further use */ - _extint_enable(); -} - -/** - * \internal - * \brief Enables the External Interrupt driver. - * - * Enables EIC modules. - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_enable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Enable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.reg |= EIC_CTRLA_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \internal - * \brief Disables the External Interrupt driver. - * - * Disables EIC modules that were previously started via a call to - * \ref _extint_enable(). - * Registered callback list will not be affected if callback mode is used. - */ -void _extint_disable(void) -{ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - /* Disable all EIC hardware modules. */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - eics[i]->CTRLA.reg &= ~EIC_CTRLA_ENABLE; - } - - while (extint_is_syncing()) { - /* Wait for all hardware modules to complete synchronization */ - } -} - -/** - * \brief Initializes an External Interrupt channel configuration structure to defaults. - * - * Initializes a given External Interrupt channel configuration structure to a - * set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Input filtering disabled - * \li Internal pull-up enabled - * \li Detect falling edges of a signal - * \li Asynchronous edge detection is disabled - * - * \param[out] config Configuration structure to initialize to default values - */ -void extint_chan_get_config_defaults( - struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->gpio_pin = 0; - config->gpio_pin_mux = 0; - config->gpio_pin_pull = EXTINT_PULL_UP; - config->filter_input_signal = false; - config->detection_criteria = EXTINT_DETECT_FALLING; - config->enable_async_edge_detection = false; -} - -/** - * \brief Writes an External Interrupt channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] channel External Interrupt channel to configure - * \param[in] config Configuration settings for the channel - - */ -void extint_chan_set_config( - const uint8_t channel, - const struct extint_chan_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - _extint_disable(); -#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); -#endif - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(channel); - - uint32_t config_pos = (4 * (channel % 8)); - uint32_t new_config; - - /* Determine the channel's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_CONFIG_SENSE0_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_CONFIG_FILTEN0; - } - - /* Clear the existing and set the new channel configuration */ - EIC_module->CONFIG[channel / 8].reg - = (EIC_module->CONFIG[channel / 8].reg & - ~((EIC_CONFIG_SENSE0_Msk | EIC_CONFIG_FILTEN0) << config_pos)) | - (new_config << config_pos); -#if (SAML22) || (SAML21XXXB) || (SAMC20) || (SAMR30) - /* Config asynchronous edge detection */ - if (config->enable_async_edge_detection) { - EIC_module->ASYNCH.reg |= (1UL << channel); - } else { - EIC_module->ASYNCH.reg &= (EIC_ASYNCH_MASK & (~(1UL << channel))); - } -#endif -#if (SAMC21) - /* Config asynchronous edge detection */ - if (config->enable_async_edge_detection) { - EIC_module->EIC_ASYNCH.reg |= (1UL << channel); - } else { - EIC_module->EIC_ASYNCH.reg &= (EIC_EIC_ASYNCH_MASK & (~(1UL << channel))); - } -#endif - _extint_enable(); -} - -/** - * \brief Writes an External Interrupt NMI channel configuration to the hardware module. - * - * Writes out a given configuration of an External Interrupt NMI channel - * configuration to the hardware module. If the channel is already configured, - * the new configuration will replace the existing one. - * - * \param[in] nmi_channel External Interrupt NMI channel to configure - * \param[in] config Configuration settings for the channel - * - * \returns Status code indicating the success or failure of the request. - * \retval STATUS_OK Configuration succeeded - * \retval STATUS_ERR_PIN_MUX_INVALID An invalid pin mux value was supplied - * \retval STATUS_ERR_BAD_FORMAT An invalid detection mode was requested - */ -enum status_code extint_nmi_set_config( - const uint8_t nmi_channel, - const struct extint_nmi_conf *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Sanity check clock requirements */ - Assert(!(!system_gclk_gen_is_enabled(EXTINT_CLOCK_SOURCE) && - _extint_is_gclk_required(config->filter_input_signal, - config->detection_criteria))); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = config->gpio_pin_mux; - pinmux_config.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pinmux_config.input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->gpio_pin_pull; - system_pinmux_pin_set_config(config->gpio_pin, &pinmux_config); - - /* Get a pointer to the module hardware instance */ - Eic *const EIC_module = _extint_get_eic_from_channel(nmi_channel); - - uint32_t new_config; - - /* Determine the NMI's new edge detection configuration */ - new_config = (config->detection_criteria << EIC_NMICTRL_NMISENSE_Pos); - - /* Enable the hardware signal filter if requested in the config */ - if (config->filter_input_signal) { - new_config |= EIC_NMICTRL_NMIFILTEN; - } - -#if (SAML21XXXB) || (SAML22) || (SAMC21) || (SAMR30) - /* Enable asynchronous edge detection if requested in the config */ - if (config->enable_async_edge_detection) { - new_config |= EIC_NMICTRL_NMIASYNCH; - } -#endif - - /* Disable EIC and general clock to configure NMI */ - _extint_disable(); -#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - system_gclk_chan_disable(EIC_GCLK_ID); -#else - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - for (uint32_t i = 0; i < EIC_INST_NUM; i++){ - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_GCLK; - system_gclk_chan_disable(EIC_GCLK_ID); - } -#endif - - EIC_module->NMICTRL.reg = new_config; - - /* Enable the EIC clock and EIC after configure NMI */ -#if(EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) - system_gclk_chan_enable(EIC_GCLK_ID); -#else - for (uint32_t i = 0; i < EIC_INST_NUM; i++){ - eics[i]->CTRLA.bit.CKSEL = EXTINT_CLK_ULP32K; - } -#endif - _extint_enable(); - - return STATUS_OK; -} - -/** - * \brief Enables an External Interrupt event output. - * - * Enables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to enable - */ -void extint_enable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - _extint_disable(); - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create an enable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Enable the masked events */ - eics[i]->EVCTRL.reg |= event_mask; - } - _extint_enable(); -} - -/** - * \brief Disables an External Interrupt event output. - * - * Disables one or more output events from the External Interrupt module. See - * \ref extint_events "here" for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] events Struct containing flags of events to disable - */ -void extint_disable_events( - struct extint_events *const events) -{ - /* Sanity check arguments */ - Assert(events); - - /* Array of available EICs. */ - Eic *const eics[EIC_INST_NUM] = EIC_INSTS; - - _extint_disable(); - - /* Update the event control register for each physical EIC instance */ - for (uint32_t i = 0; i < EIC_INST_NUM; i++) { - uint32_t event_mask = 0; - - /* Create a disable mask for the current EIC module */ - for (uint32_t j = 0; j < 32; j++) { - if (events->generate_event_on_detect[(32 * i) + j]) { - event_mask |= (1UL << j); - } - } - - /* Disable the masked events */ - eics[i]->EVCTRL.reg &= ~event_mask; - } - _extint_enable(); -} diff --git a/atmel-samd/asf/sam0/drivers/extint/module_config/conf_extint.h b/atmel-samd/asf/sam0/drivers/extint/module_config/conf_extint.h deleted file mode 100644 index fd8611ec1a2e7..0000000000000 --- a/atmel-samd/asf/sam0/drivers/extint/module_config/conf_extint.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief SAM External Interrupt Driver Configuration Header - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_EXTINT_H_INCLUDED -#define CONF_EXTINT_H_INCLUDED - -/** - * Define which clock type is used to clock EIC peripheral: - * - EXTINT_CLK_GCLK - * - EXTINT_CLK_ULP32K - * - * EXTINT_CLK_ULP32K is available for SAM L21/C21. - */ -#define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK - -/** - * Define which GCLK source is used when selecting EXTINT_CLK_GCLK type. - */ -#if (EXTINT_CLOCK_SELECTION == EXTINT_CLK_GCLK) -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 -#endif - -#endif diff --git a/atmel-samd/asf/sam0/drivers/i2s/i2s.c b/atmel-samd/asf/sam0/drivers/i2s/i2s.c deleted file mode 100644 index bbf04620bbd23..0000000000000 --- a/atmel-samd/asf/sam0/drivers/i2s/i2s.c +++ /dev/null @@ -1,750 +0,0 @@ -/** - * \file - * - * \brief SAM I2S - Inter-IC Sound Controller - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2s.h" - -/** - * \brief Initializes a hardware I2S module instance - * - * Enables the clock and initialize the I2S module. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the TCC hardware module - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * initialization procedure was attempted - * \retval STATUS_ERR_DENIED Hardware module was already enabled - */ -enum status_code i2s_init( - struct i2s_module *const module_inst, - I2s *hw) -{ - Assert(module_inst); - Assert(hw); - - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_I2S); - - /* Status check */ - uint32_t ctrla; - ctrla = module_inst->hw->CTRLA.reg; - if (ctrla & I2S_CTRLA_ENABLE) { - if (ctrla & (I2S_CTRLA_SEREN1 | - I2S_CTRLA_SEREN0 | I2S_CTRLA_CKEN1 | I2S_CTRLA_CKEN0)) { - return STATUS_BUSY; - } else { - return STATUS_ERR_DENIED; - } - } - - /* Initialize module */ - module_inst->hw = hw; - - /* Initialize serializers */ -#if I2S_CALLBACK_MODE == true - int i, j; - for (i = 0; i < 2; i ++) { - for (j = 0; j < I2S_SERIALIZER_CALLBACK_N; j ++) { - module_inst->serializer[i].callback[j] = NULL; - } - module_inst->serializer[i].registered_callback_mask = 0; - module_inst->serializer[i].enabled_callback_mask = 0; - - module_inst->serializer[i].job_buffer = NULL; - module_inst->serializer[i].job_status = STATUS_OK; - module_inst->serializer[i].requested_words = 0; - module_inst->serializer[i].transferred_words = 0; - - module_inst->serializer[i].mode = I2S_SERIALIZER_RECEIVE; - module_inst->serializer[i].data_size = I2S_DATA_SIZE_32BIT; - } - - _i2s_instances[0] = module_inst; - - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_I2S); -#endif - - return STATUS_OK; -} - - -/** - * \brief Configure specified I2S clock unit - * - * Enables the clock and initialize the clock unit, based on the given - * configurations. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] clock_unit I2S clock unit to initialize and configure - * \param[in] config Pointer to the I2S clock unit configuration - * options struct - * - * \return Status of the configuration procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * configuration procedure was attempted - * \retval STATUS_ERR_DENIED Hardware module was already enabled - * \retval STATUS_ERR_INVALID_ARG Invalid divider value or - * MCK direction setting conflict - */ -enum status_code i2s_clock_unit_set_config( - struct i2s_module *const module_inst, - const enum i2s_clock_unit clock_unit, - const struct i2s_clock_unit_config *config) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(clock_unit < I2S_CLOCK_UNIT_N); - Assert(config); - - /* Status check */ - uint32_t ctrla, syncbusy; - syncbusy = module_inst->hw->SYNCBUSY.reg; - ctrla = module_inst->hw->CTRLA.reg; - - /* Busy ? */ - if (syncbusy & (I2S_SYNCBUSY_CKEN0 << clock_unit)) { - return STATUS_BUSY; - } - /* Already enabled ? */ - if (ctrla & (I2S_CTRLA_CKEN0 << clock_unit)) { - return STATUS_ERR_DENIED; - } - /* Parameter check */ - if (config->clock.mck_src && config->clock.mck_out_enable) { - return STATUS_ERR_INVALID_ARG; - } - - /* Initialize Clock Unit */ - uint32_t clkctrl = - (config->clock.mck_out_invert ? I2S_CLKCTRL_MCKOUTINV : 0) | - (config->clock.sck_out_invert ? I2S_CLKCTRL_SCKOUTINV : 0) | - (config->frame.frame_sync.invert_out ? I2S_CLKCTRL_FSOUTINV : 0) | - (config->clock.mck_out_enable ? I2S_CLKCTRL_MCKEN : 0) | - (config->clock.mck_src ? I2S_CLKCTRL_MCKSEL : 0) | - (config->clock.sck_src ? I2S_CLKCTRL_SCKSEL : 0) | - (config->frame.frame_sync.invert_use ? I2S_CLKCTRL_FSINV : 0) | - (config->frame.frame_sync.source ? I2S_CLKCTRL_FSSEL : 0) | - (config->frame.data_delay ? I2S_CLKCTRL_BITDELAY : 0); - - uint8_t div_val = config->clock.mck_out_div; - if ((div_val > 0x21) || (div_val == 0)) { - return STATUS_ERR_INVALID_ARG; - } else { - div_val --; - } - clkctrl |= I2S_CLKCTRL_MCKOUTDIV(div_val); - - div_val = config->clock.sck_div; - if ((div_val > 0x21) || (div_val == 0)) { - return STATUS_ERR_INVALID_ARG; - } else { - div_val --; - } - clkctrl |= I2S_CLKCTRL_MCKDIV(div_val); - - uint8_t number_slots = config->frame.number_slots; - if (number_slots > 8) { - return STATUS_ERR_INVALID_ARG; - } else if (number_slots > 0) { - number_slots --; - } - clkctrl |= - I2S_CLKCTRL_NBSLOTS(number_slots) | - I2S_CLKCTRL_FSWIDTH(config->frame.frame_sync.width) | - I2S_CLKCTRL_SLOTSIZE(config->frame.slot_size); - - /* Write clock unit configurations */ - module_inst->hw->CLKCTRL[clock_unit].reg = clkctrl; - - /* Select general clock source */ - const uint8_t i2s_gclk_ids[2] = {I2S_GCLK_ID_0, I2S_GCLK_ID_1}; - struct system_gclk_chan_config gclk_chan_config; - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->clock.gclk_src; - system_gclk_chan_set_config(i2s_gclk_ids[clock_unit], &gclk_chan_config); - system_gclk_chan_enable(i2s_gclk_ids[clock_unit]); - - /* Initialize pins */ - struct system_pinmux_config pin_config; - system_pinmux_get_config_defaults(&pin_config); - if (config->mck_pin.enable) { - pin_config.mux_position = config->mck_pin.mux; - system_pinmux_pin_set_config(config->mck_pin.gpio, &pin_config); - } - if (config->sck_pin.enable) { - pin_config.mux_position = config->sck_pin.mux; - system_pinmux_pin_set_config(config->sck_pin.gpio, &pin_config); - } - if (config->fs_pin.enable) { - pin_config.mux_position = config->fs_pin.mux; - system_pinmux_pin_set_config(config->fs_pin.gpio, &pin_config); - } - - return STATUS_OK; -} - - -/** - * \brief Configure specified I2S serializer - * - * Enables the clock and initialize the serializer, based on the given - * configurations. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] serializer I2S serializer to initialize and configure - * \param[in] config Pointer to the I2S serializer configuration - * options struct - * - * \return Status of the configuration procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * configuration procedure was attempted - * \retval STATUS_ERR_DENIED Hardware module was already enabled - */ -enum status_code i2s_serializer_set_config( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const struct i2s_serializer_config *config) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(serializer < I2S_SERIALIZER_N); - Assert(config); - - /* Status check */ - uint32_t ctrla, syncbusy; - syncbusy = module_inst->hw->SYNCBUSY.reg; - ctrla = module_inst->hw->CTRLA.reg; - - /* Busy ? */ - if (syncbusy & ((I2S_SYNCBUSY_SEREN0 | I2S_SYNCBUSY_DATA0) << serializer)) { - return STATUS_BUSY; - } - /* Already enabled ? */ - if (ctrla & (I2S_CTRLA_CKEN0 << serializer)) { - return STATUS_ERR_DENIED; - } - - /* Initialize Serializer */ - uint32_t serctrl = - (config->loop_back ? I2S_SERCTRL_RXLOOP : 0) | - (config->dma_usage ? I2S_SERCTRL_DMA : 0) | - (config->mono_mode ? I2S_SERCTRL_MONO : 0) | - (config->disable_data_slot[7] ? I2S_SERCTRL_SLOTDIS7 : 0) | - (config->disable_data_slot[6] ? I2S_SERCTRL_SLOTDIS6 : 0) | - (config->disable_data_slot[5] ? I2S_SERCTRL_SLOTDIS5 : 0) | - (config->disable_data_slot[4] ? I2S_SERCTRL_SLOTDIS4 : 0) | - (config->disable_data_slot[3] ? I2S_SERCTRL_SLOTDIS3 : 0) | - (config->disable_data_slot[2] ? I2S_SERCTRL_SLOTDIS2 : 0) | - (config->disable_data_slot[1] ? I2S_SERCTRL_SLOTDIS1 : 0) | - (config->disable_data_slot[0] ? I2S_SERCTRL_SLOTDIS0 : 0) | - (config->transfer_lsb_first ? I2S_SERCTRL_BITREV : 0) | - (config->data_adjust_left_in_word ? I2S_SERCTRL_WORDADJ : 0) | - (config->data_adjust_left_in_slot ? I2S_SERCTRL_SLOTADJ : 0) | - (config->data_padding ? I2S_SERCTRL_TXSAME : 0); - - if (config->clock_unit < I2S_CLOCK_UNIT_N) { - serctrl |= (config->clock_unit ? I2S_SERCTRL_CLKSEL : 0); - } else { - return STATUS_ERR_INVALID_ARG; - } - - serctrl |= - I2S_SERCTRL_SERMODE(config->mode) | - I2S_SERCTRL_TXDEFAULT(config->line_default_state) | - I2S_SERCTRL_DATASIZE(config->data_size) | - I2S_SERCTRL_EXTEND(config->bit_padding); - - /* Write Serializer configuration */ - module_inst->hw->SERCTRL[serializer].reg = serctrl; - - /* Initialize pins */ - struct system_pinmux_config pin_config; - system_pinmux_get_config_defaults(&pin_config); - if (config->data_pin.enable) { - pin_config.mux_position = config->data_pin.mux; - system_pinmux_pin_set_config(config->data_pin.gpio, &pin_config); - } - - /* Save configure */ - module_inst->serializer[serializer].mode = config->mode; - module_inst->serializer[serializer].data_size = config->data_size; - - return STATUS_OK; -} - - - -/** - * \brief Retrieves the current module status. - * - * Retrieves the status of the module, giving overall state information. - * - * \param[in] module_inst Pointer to the I2S software instance struct - * - * \return Bitmask of \c I2S_STATUS_* flags. - * - * \retval I2S_STATUS_SYNC_BUSY Module is busy synchronization - * \retval I2S_STATUS_TRANSMIT_UNDERRUN(x) Serializer x (0~1) is underrun - * \retval I2S_STATUS_TRANSMIT_READY(x) Serializer x (0~1) is ready to - * transmit new data word - * \retval I2S_STATUS_RECEIVE_OVERRUN(x) Serializer x (0~1) is overrun - * \retval I2S_STATUS_RECEIVE_READY(x) Serializer x (0~1) has data ready to - * read - */ -uint32_t i2s_get_status( - const struct i2s_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint32_t intflag = module_inst->hw->INTFLAG.reg; - uint32_t status; - if (module_inst->hw->SYNCBUSY.reg) { - status = I2S_STATUS_SYNC_BUSY; - } else { - status = 0; - } - if (intflag & I2S_INTFLAG_TXUR0) { - status |= I2S_STATUS_TRANSMIT_UNDERRUN(0); - } - if (intflag & I2S_INTFLAG_TXUR1) { - status |= I2S_STATUS_TRANSMIT_UNDERRUN(1); - } - if ((intflag & I2S_INTFLAG_TXRDY0) && - !module_inst->hw->SYNCBUSY.bit.DATA0) { - status |= I2S_STATUS_TRANSMIT_READY(0); - } - if ((intflag & I2S_INTFLAG_TXRDY1) && - !module_inst->hw->SYNCBUSY.bit.DATA1) { - status |= I2S_STATUS_TRANSMIT_READY(1); - } - if (intflag & I2S_INTFLAG_RXOR0) { - status |= I2S_STATUS_RECEIVE_OVERRUN(0); - } - if (intflag & I2S_INTFLAG_RXOR1) { - status |= I2S_STATUS_RECEIVE_OVERRUN(1); - } - if (intflag & I2S_INTFLAG_RXRDY0) { - status |= I2S_STATUS_RECEIVE_READY(0); - } - if (intflag & I2S_INTFLAG_RXRDY1) { - status |= I2S_STATUS_RECEIVE_READY(1); - } - return status; -} - -/** - * \brief Clears a module status flags. - * - * Clears the given status flags of the module. - * - * \param[in] module_inst Pointer to the I2S software instance struct - * \param[in] status Bitmask of \c I2S_STATUS_* flags to clear - */ -void i2s_clear_status( - const struct i2s_module *const module_inst, - uint32_t status) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint32_t intflag = 0; - - if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) { - intflag = I2S_INTFLAG_TXUR0; - } - if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) { - intflag = I2S_INTFLAG_TXUR1; - } - if (status & I2S_STATUS_TRANSMIT_READY(0)) { - intflag = I2S_INTFLAG_TXRDY0; - } - if (status & I2S_STATUS_TRANSMIT_READY(1)) { - intflag = I2S_INTFLAG_TXRDY1; - } - if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) { - intflag = I2S_INTFLAG_RXOR0; - } - if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) { - intflag = I2S_INTFLAG_RXOR1; - } - if (status & I2S_STATUS_RECEIVE_READY(0)) { - intflag = I2S_INTFLAG_RXRDY0; - } - if (status & I2S_STATUS_RECEIVE_READY(1)) { - intflag = I2S_INTFLAG_RXRDY1; - } - module_inst->hw->INTFLAG.reg = intflag; -} - -/** - * \brief Enable interrupts on status set - * - * Enable the given status interrupt request from the I2S module. - * - * \param[in] module_inst Pointer to the I2S software instance struct - * \param[in] status Status interrupts to enable - * - * \return Status of enable procedure. - * - * \retval STATUS_OK Interrupt is enabled successfully - * \retval STATUS_ERR_INVALID_ARG Status with no interrupt is passed - */ -enum status_code i2s_enable_status_interrupt( - struct i2s_module *const module_inst, - uint32_t status) -{ - /* Sanity check arguments */ - Assert(module_inst); - - /* No sync busy interrupt */ - if (status & I2S_STATUS_SYNC_BUSY) { - return STATUS_ERR_INVALID_ARG; - } - Assert(module_inst->hw); - - uint32_t intflag = 0; - if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) { - intflag = I2S_INTFLAG_TXUR0; - } - if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) { - intflag = I2S_INTFLAG_TXUR1; - } - if (status & I2S_STATUS_TRANSMIT_READY(0)) { - intflag = I2S_INTFLAG_TXRDY0; - } - if (status & I2S_STATUS_TRANSMIT_READY(1)) { - intflag = I2S_INTFLAG_TXRDY1; - } - if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) { - intflag = I2S_INTFLAG_RXOR0; - } - if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) { - intflag = I2S_INTFLAG_RXOR1; - } - if (status & I2S_STATUS_RECEIVE_READY(0)) { - intflag = I2S_INTFLAG_RXRDY0; - } - if (status & I2S_STATUS_RECEIVE_READY(1)) { - intflag = I2S_INTFLAG_RXRDY1; - } - module_inst->hw->INTENSET.reg = intflag; - return STATUS_OK; -} - -/** - * \brief Disable interrupts on status set - * - * Disable the given status interrupt request from the I2S module. - * - * \param[in] module_inst Pointer to the I2S software instance struct - * \param[in] status Status interrupts to disable - */ -void i2s_disable_status_interrupt( - struct i2s_module *const module_inst, - uint32_t status) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint32_t intflag = 0; - if (status & I2S_STATUS_TRANSMIT_UNDERRUN(0)) { - intflag = I2S_INTFLAG_TXUR0; - } - if (status & I2S_STATUS_TRANSMIT_UNDERRUN(1)) { - intflag = I2S_INTFLAG_TXUR1; - } - if (status & I2S_STATUS_TRANSMIT_READY(0)) { - intflag = I2S_INTFLAG_TXRDY0; - } - if (status & I2S_STATUS_TRANSMIT_READY(1)) { - intflag = I2S_INTFLAG_TXRDY1; - } - if (status & I2S_STATUS_RECEIVE_OVERRUN(0)) { - intflag = I2S_INTFLAG_RXOR0; - } - if (status & I2S_STATUS_RECEIVE_OVERRUN(1)) { - intflag = I2S_INTFLAG_RXOR1; - } - if (status & I2S_STATUS_RECEIVE_READY(0)) { - intflag = I2S_INTFLAG_RXRDY0; - } - if (status & I2S_STATUS_RECEIVE_READY(1)) { - intflag = I2S_INTFLAG_RXRDY1; - } - module_inst->hw->INTENCLR.reg = intflag; -} - - -/** - * \brief Write buffer to the specified Serializer of I2S module - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The serializer to write to - * \param[in] buffer The data buffer to write - * \param[in] size Number of data words to write - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The data was sent successfully - * \retval STATUS_ERR_DENIED The module or serializer is disabled - * \retval STATUS_ERR_INVALID_ARG An invalid buffer pointer was supplied - */ -enum status_code i2s_serializer_write_buffer_wait( - const struct i2s_module *const module_inst, - enum i2s_serializer serializer, - void *buffer, uint32_t size) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(serializer < I2S_SERIALIZER_N); - Assert(buffer); - - if (size == 0) { - return STATUS_OK; - } - - uint8_t data_size = 1; /* number of bytes */ - struct i2s_serializer_module *data_module = (struct i2s_serializer_module *) - &module_inst->serializer[serializer]; - - /* Check buffer */ - switch(data_module->data_size) { - case I2S_DATA_SIZE_32BIT: - case I2S_DATA_SIZE_24BIT: - case I2S_DATA_SIZE_20BIT: - case I2S_DATA_SIZE_18BIT: - if ((uint32_t)buffer & 0x3) { - return STATUS_ERR_INVALID_ARG; - } - data_size = 4; - break; - case I2S_DATA_SIZE_16BIT: - case I2S_DATA_SIZE_16BIT_COMPACT: - if ((uint32_t)buffer & 0x1) { - return STATUS_ERR_INVALID_ARG; - } - data_size = 2; - break; - default: - break; - } - - /* Check status */ - if (!(module_inst->hw->CTRLA.reg & - (I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) { - return STATUS_ERR_DENIED; - } - - /* Write */ - uint32_t i; - uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer; - uint32_t ready_bit = I2S_INTFLAG_TXRDY0 << serializer; - if (4 == data_size) { - uint32_t *p32 = (uint32_t*)buffer; - for (i = 0; i < size; i ++) { - while(!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait Tx ready */ - } - while(module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait Sync */ - } - module_inst->hw->DATA[serializer].reg = p32[i]; - module_inst->hw->INTFLAG.reg = ready_bit; - } - } else if (2 == data_size) { - uint16_t *p16 = (uint16_t*)buffer; - for (i = 0; i < size; i ++) { - while(!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait Tx ready */ - } - while(module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait Sync */ - } - module_inst->hw->DATA[serializer].reg = p16[i]; - module_inst->hw->INTFLAG.reg = ready_bit; - } - } else { - uint8_t *p8 = (uint8_t*)buffer; - for (i = 0; i < size; i ++) { - while(!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait Tx ready */ - } - while(module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait Sync */ - } - module_inst->hw->DATA[serializer].reg = p8[i]; - module_inst->hw->INTFLAG.reg = ready_bit; - } - } - - return STATUS_OK; -} - -/** - * \brief Read from the specified Serializer of I2S module to a buffer - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The serializer to write to - * \param[in] buffer The buffer to fill read data (NULL to discard) - * \param[in] size Number of data words to read - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The data was sent successfully - * \retval STATUS_ERR_DENIED The module or serializer is disabled - * \retval STATUS_ERR_INVALID_ARG An invalid buffer pointer was supplied - */ -enum status_code i2s_serializer_read_buffer_wait( - const struct i2s_module *const module_inst, - enum i2s_serializer serializer, - void *buffer, uint32_t size) -{ - Assert(module_inst); - Assert(module_inst->hw); - - if (size == 0) { - return STATUS_OK; - } - - uint8_t data_size = 1; /* number of bytes */ - struct i2s_serializer_module *data_module = (struct i2s_serializer_module *) - &module_inst->serializer[serializer]; - - /* Check buffer */ - switch(data_module->data_size) { - case I2S_DATA_SIZE_32BIT: - case I2S_DATA_SIZE_24BIT: - case I2S_DATA_SIZE_20BIT: - case I2S_DATA_SIZE_18BIT: - if ((uint32_t)buffer & 0x3) { - return STATUS_ERR_INVALID_ARG; - } - data_size = 4; - break; - case I2S_DATA_SIZE_16BIT: - case I2S_DATA_SIZE_16BIT_COMPACT: - if ((uint32_t)buffer & 0x1) { - return STATUS_ERR_INVALID_ARG; - } - data_size = 2; - break; - default: - break; - } - - /* Check status */ - if (!(module_inst->hw->CTRLA.reg & - (I2S_CTRLA_ENABLE | (I2S_CTRLA_SEREN0 << serializer)))) { - return STATUS_ERR_DENIED; - } - - /* Read */ - uint32_t i; - uint32_t sync_bit = I2S_SYNCBUSY_DATA0 << serializer; - uint32_t ready_bit = I2S_INTFLAG_RXRDY0 << serializer; - if (buffer == NULL) { - for (i = 0; i < size; i ++) { - while(!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait Rx ready */ - } - while(module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait Sync */ - } - module_inst->hw->DATA[serializer].reg; - module_inst->hw->INTFLAG.reg = ready_bit; - } - } - else if (4 == data_size) { - uint32_t *p32 = (uint32_t*)buffer; - for (i = 0; i < size; i ++) { - while(!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait Rx ready */ - } - while(module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait Sync */ - } - p32[i] = module_inst->hw->DATA[serializer].reg; - module_inst->hw->INTFLAG.reg = ready_bit; - } - } else if (2 == data_size) { - uint16_t *p16 = (uint16_t*)buffer; - for (i = 0; i < size; i ++) { - while(!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait Rx ready */ - } - while(module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait Sync */ - } - p16[i] = module_inst->hw->DATA[serializer].reg; - module_inst->hw->INTFLAG.reg = ready_bit; - } - } else { - uint8_t *p8 = (uint8_t*)buffer; - for (i = 0; i < size; i ++) { - while(!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait Tx ready */ - } - while(module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait Sync */ - } - p8[i] = module_inst->hw->DATA[serializer].reg; - module_inst->hw->INTFLAG.reg = ready_bit; - } - } - - return STATUS_OK; -} diff --git a/atmel-samd/asf/sam0/drivers/i2s/i2s.h b/atmel-samd/asf/sam0/drivers/i2s/i2s.h deleted file mode 100644 index 0e965d8d3a94f..0000000000000 --- a/atmel-samd/asf/sam0/drivers/i2s/i2s.h +++ /dev/null @@ -1,1386 +0,0 @@ -/** - * \file - * - * \brief SAM I2S - Inter-IC Sound Controller - * - * Copyright (c) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2S_H_INCLUDED -#define I2S_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_i2s_group SAM Inter-IC Sound Controller (I2S) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the device's Inter-IC - * Sound Controller functionality. - * - * The following driver API modes are covered by this manual: - * - Polled APIs - * \if I2S_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - I2S (Inter-IC Sound Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM D21 - * - Atmel | SMART SAM DA1 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_i2s_prerequisites - * - \ref asfdoc_sam0_i2s_module_overview - * - \ref asfdoc_sam0_i2s_special_considerations - * - \ref asfdoc_sam0_i2s_extra_info - * - \ref asfdoc_sam0_i2s_examples - * - \ref asfdoc_sam0_i2s_api_overview - * - * \section asfdoc_sam0_i2s_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * \section asfdoc_sam0_i2s_module_overview Module Overview - * - * The I2S provides bidirectional, synchronous, digital audio link with - * external audio devices through these signal pins: - * - Serial Data (SDm) - * - Frame Sync (FSn) - * - Serial Clock (SCKn) - * - Master Clock (MCKn) - * - * The I2S consists of two Clock Units and two Serializers, which can be - * separately configured and enabled, to provide varies functionalities as follow: - * - Communicate to Audio CODECs as Master or Slave, or provides clock and - * frame sync signals as Controller - * - Communicate to DAC or ADC through dedicated I2S serial interface - * - Communicate to multi-slot or multiple stereo DACs or ADCs, via - * Time Division Multiplexed (TDM) format - * - Reading mono or stereo MEMS microphones, using the Pulse Density - * Modulation (PDM) interface - * - * The I2S supports compact stereo data word, where left channel data bits are - * in lower half and right channel data bits are in upper half. It reduces the - * number of data words for stereo audio data and the DMA bandwidth. - * - * In master mode, the frame is configured by number of slots and slot size, and - * allows range covering 16fs to 1024fs MCK, to provide oversampling clock to an - * external audio CODEC or digital signal processor (DSP). - * - * A block diagram of the I2S can be seen in - * \ref asfdoc_sam0_i2s_module_block_diagram "the figure below". - * - * \anchor asfdoc_sam0_i2s_module_block_diagram - * \image html i2s_blocks.svg "I2S Block Diagram" - * - * This driver for I2S module provides an interface to: - * - Initialize and control I2S module - * - Configure and control the I2S Clock Unit and Serializer - * - Transmit/receive data through I2S Serializer - * - * \subsection asfdoc_sam0_i2s_module_overview_clocks Clocks - * - * To use I2S module, the I2S bus interface clock (clk_i2s) - * must be enabled via Power Manager. - * - * For each I2S Clock Unit, a generic clock (gclk_i2s_n) is connnected. - * When I2S works in master mode the generic clock is used. It should - * be prepared before clock unit is used. In master mode the input generic clock - * will be used as MCK for SCKn and FSn generation, in addition, the MCK could be - * devided and output to I2S MCKn pin, as oversampling clock to - * external audio device. - * - * The I2S Serializer uses clock and control signal from Clock Unit to handle - * transfer. Select different clock unit with different configurations allows - * the I2S to work as master or slave, to work on non-related clocks. - * - * When using the driver with ASF, enabling the register interface is normally - * done by the \c init function. - * The Generic Clock Controller (GCLK) source for the asynchronous domain is - * normally configured and set through the _configuration - * struct_ / _init_ function. - * If GCLK source != 0 is used, this source has to be configured and enabled - * through invoking the system_gclk driver function when needed, or modifying - * conf_clock.h to enable it at the beginning. - * - * \subsection asfdoc_sam0_i2s_module_overview_frame Audio Frame Generation - * - * Audio sample data for all channels are sent in frames, one frame can consist - * 1 - 8 slots where each slot can be configured to a size 8-bit, 16-bit, 24-bit, - * or 32-bit. The audio frame synch clock is generated by the I2S - * Clock unit in the master/controller mode. The frame rate (or frame sync - * frequency) is calculated as follows: - * - * FS = SCK / number_of_slots / number_of_bits_in_slot - * - * The serial clock (SCK) source is either an external source (slave mode) or - * generated by the I2S clock unit (controller or master mode) using - * the MCK as source. - * - * SCK = MCK / sck_div - * \note SCK generation division value is MCKDIV in register. - * - * MCK is either an external source or generated using the GCLK input from a - * generic clock generator. - * - * \subsection asfdoc_sam0_i2s_module_overview_mode Master, Controller, and Slave Modes - * - * The I2S module has three modes: master, controller, and slave. - * - * \subsubsection asfdoc_sam0_i2s_module_overview_mode_mst Master - * In master mode the module will control the data flow on the I2S bus and can - * be responsible for clock generation. The Serializers are enabled and will - * transmit/receive data. On a bus with only master and slave the SCK, and FS - * clock signal will be outputted on the SCK and FS pin on the master module. - * MCK can optionally be outputted on the MCK pin, if there is a controller - * module on the bus the SCK, FS, and optionally the MCK clock is sourced from - * the same pins. Serial data will be trancieved on the SD pin in both - * scenarios. - * - * \subsubsection asfdoc_sam0_i2s_module_overview_mode_ctl Controller - * In controller mode the module will generate the clock signals, but the - * Serializers are disabled and no data will be transmitted/received by the - * module in this mode. The clock signals is outputted on the SCK, FS and - * optionally the MCK pin. - * - * \subsubsection asfdoc_sam0_i2s_module_overview_mode_slv Slave - * In slave mode the module will use the SCK and FS clock source from the master - * or the controller which is received on the SCK and FS pin. The MCK can - * optionally be sourced externally on the MCK pin. The Serializers are enabled - * and will tranceive data on the SD pin. All data flow is controlled by the - * master. - * - * \subsubsection asfdoc_sam0_i2s_module_overview_mode_chg Switch Modes - * The mode switching between master, controller, and slave modes are actually - * done by modifying the source mode of I2S pins. - * The source mode of I2S pins are selected by writing corresponding - * bits in CLKCTRLn. - * Since source mode switching changes the direction of pin, the mode must be - * changed when the I2S Clock Unit is stopped. - * - * \subsection asfdoc_sam0_i2s_module_overview_data Data Stream Reception/Transmission - * - * The I2S module support several data stream formats: - * - I2S format - * - Time Division Multiplexed (TDM) format - * - Pulse Density Modulation (PDM) format (reception only) - * - * Basically the I2S module can send several words within each frame, - * it's more like TDM format. With adjust to the number of data words in a frame, - * the FS width, the FS to data bits delay, etc., the module is able to handle - * I2S compliant data stream. - * - * Also the Serializer can receive PDM format data stream, which allows the - * I2S module receive 1 PDM data on each SCK edge. - * - * \subsubsection asfdoc_sam0_i2s_module_overview_data_i2s I2S Stream Reception/Transmission - * - * For 2-channel I2S compliant data stream format the I2S - * module uses the FS line as word select (WS) signal and will send left channel - * data word on low WS level and right channel data word on high WS level as - * specified in the I2S standard. The supported word sizes are 8-, - * 16-, 18-, 20-, 24-, and 32- bit. - * - * Thus for I2S stream, the following settings should be applied to the module: - * - Data starting delay after FS transition : one SCK period - * - FS width : half of frame - * - Data bits adjust in word : left-adjusted - * - Bit transmitting order : MSB first - * - * Following is an example for I2S application connections and waveforms. See - * the figure below. - * - * \anchor asfdoc_sam0_i2s_module_i2s_example_diagram - * \image html i2s_example.svg "I2S Example Diagram" - * - * \subsubsection asfdoc_sam0_i2s_module_overview_data_tdm TDM Stream Reception/Transmission - * In TDM format, the module sends several data words in each frame. For this - * data stream format most of the configurations could be adjusted: - * - Main Frame related settings are as follow: - * - Frame Sync (FS) options: - * - The active edge of the FS (or if FS is inverted before use) - * - The width of the FS - * - The delay between FS to first data bit - * - Data alignment in slot - * - The number of slots and slot size can be adjusted, it has been mentioned - * in \ref asfdoc_sam0_i2s_module_overview_frame - * - The data word size is controlled by Serializer, it can be chosen among - * 8, 16, 18, 20, 24, and 32 bits. - * - * The general TDM waveform generation is as follows: - * - * \anchor asfdoc_sam0_i2s_module_tdm_wave_diagram - * \image html tdm_wave.svg "TDM Waveform Generation" - * - * Some other settings could also be found to set up clock, data formatting and - * pin multiplexer (MUX). - * Refer to \ref i2s_clock_unit_config "Clock Unit Configurations" - * and \ref i2s_serializer_config "Serializer Configurations" for more - * details. - * - * Following is examples for different application use cases. - * - * See \ref asfdoc_sam0_i2s_module_tdm_timeslot_example_diagram "here" for - * the Time Slot Application connection and waveform example. - * - * \anchor asfdoc_sam0_i2s_module_tdm_timeslot_example_diagram - * \image html tdm_timeslot_example.svg "Codec Example Diagram" - * - * See \ref asfdoc_sam0_i2s_module_tdm_codec_example_diagram "here" for the - * Codec Application connection and waveform example. - * - * \anchor asfdoc_sam0_i2s_module_tdm_codec_example_diagram - * \image html tdm_codec_example.svg "Time Slot Example Diagram" - * - * \subsubsection asfdoc_sam0_i2s_module_overview_data_pdm PDM Reception - * The I2S Serializer integrates PDM reception feature, to use this feature, - * simply select PDM2 mode in Serializer configuration. In PDM2 mode, it assumes - * two microphones are input for stereo stream. The left microphone bits will - * be stored in lower half and right microphone bits in upper half of the data - * word, like in compact stereo format. - * - * See \ref asfdoc_sam0_i2s_module_pdm_example_diagram "following figure" for an - * example of PDM Microphones Application with both left and right channel - * microphone connected. - * - * \anchor asfdoc_sam0_i2s_module_pdm_example_diagram - * \image html pdm_example.svg "Time PDM2 Example Diagram" - * - * \subsubsection asfdoc_sam0_i2s_module_overview_data_fmt MONO and Compact Data - * The I2S Serializer can accept some pre-defined data format and generates - * the data stream in specified way. - * - * When transmitting data, the Serializer can work in MONO mode: assum input - * is single channel mono data on left channel and copy it to right channel - * automatically. - * - * Also the I2S Serializer can support compact stereo data word. The data word - * size of the Serializer can be set to \ref I2S_DATA_SIZE_16BIT_COMPACT - * "16-bit compact" or \ref I2S_DATA_SIZE_8BIT_COMPACT "8-bit compact", with - * these option I2S Serializer will compact left channel data and right channel - * data together, the left channel data will take lower bytes and right channel - * data take higher bytes. - * - * \subsection asfdoc_sam0_i2s_module_overview_loop Loop-back Mode - * The I2S can be configured to loop back the Transmitter to Receiver. In this - * mode Serializer's input will be connected to another Serializer's output - * internally. - * - * \subsection asfdoc_sam0_i2s_module_overview_sleep Sleep Modes - * The I2S will continue to operate in any sleep mode, where the selected source - * clocks are running. - * - * \section asfdoc_sam0_i2s_special_considerations Special Considerations - * - * There is no special considerations for I2S module. - * - * \section asfdoc_sam0_i2s_extra_info Extra Information - * - * For extra information see \ref asfdoc_sam0_i2s_extra. This includes: - * - \ref asfdoc_sam0_i2s_extra_acronyms - * - \ref asfdoc_sam0_i2s_extra_dependencies - * - \ref asfdoc_sam0_i2s_extra_errata - * - \ref asfdoc_sam0_i2s_extra_history - * - * \section asfdoc_sam0_i2s_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_i2s_exqsg. - * - * - * \section asfdoc_sam0_i2s_api_overview API Overview - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if I2S_CALLBACK_MODE == true -# include - -#if !defined(__DOXYGEN__) -extern struct i2s_module *_i2s_instances[I2S_INST_NUM]; -#endif - -/** Forward definition of the device instance */ -struct i2s_module; - -/** Type of the callback functions. */ -typedef void (*i2s_serializer_callback_t) - (struct i2s_module *const module); - -/** - * \brief I2S Serializer Callback enum - */ -enum i2s_serializer_callback { - /** Callback for buffer read/write finished */ - I2S_SERIALIZER_CALLBACK_BUFFER_DONE, - /** Callback for Serializer overrun/underrun */ - I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN, -# if !defined(__DOXYGEN__) - I2S_SERIALIZER_CALLBACK_N -# endif -}; - -#endif /* #if I2S_CALLBACK_MODE == true */ - -/** - * \name Module Status Flags - * - * I2S status flags, returned by \ref i2s_get_status() and cleared by - * \ref i2s_clear_status(). - * - * @{ - */ - -/** Module Serializer x (0~1) Transmit Underrun. */ -#define I2S_STATUS_TRANSMIT_UNDERRUN(x) (1u << ((x)+0)) -/** Module Serializer x (0~1) is ready to accept new data to be transmitted. */ -#define I2S_STATUS_TRANSMIT_READY(x) (1u << ((x)+2)) -/** Module Serializer x (0~1) Receive Overrun. */ -#define I2S_STATUS_RECEIVE_OVERRUN(x) (1u << ((x)+4)) -/** Module Serializer x (0~1) has received a new data. */ -#define I2S_STATUS_RECEIVE_READY(x) (1u << ((x)+6)) -/** Module is busy on synchronization. */ -#define I2S_STATUS_SYNC_BUSY (1u << 8) - -/** @} */ - -/** - * Master Clock (MCK) source selection. - */ -enum i2s_master_clock_source { - /** Master Clock (MCK) is from general clock */ - I2S_MASTER_CLOCK_SOURCE_GCLK, - /** Master Clock (MCK) is from MCK input pin */ - I2S_MASTER_CLOCK_SOURCE_MCKPIN -}; - -/** - * Serial Clock (SCK) source selection. - */ -enum i2s_serial_clock_source { - /** Serial Clock (SCK) is divided from Master Clock */ - I2S_SERIAL_CLOCK_SOURCE_MCKDIV, - /** Serial Clock (SCK) is input from SCK input pin */ - I2S_SERIAL_CLOCK_SOURCE_SCKPIN -}; - -/** - * Data delay from Frame Sync (FS). - */ -enum i2s_data_delay { - /** Left Justified (no delay) */ - I2S_DATA_DELAY_0, - /** I2S data delay (1-bit delay) */ - I2S_DATA_DELAY_1, - /** Left Justified (no delay) */ - I2S_DATA_DELAY_LEFT_JUSTIFIED = I2S_DATA_DELAY_0, - /** I2S data delay (1-bit delay) */ - I2S_DATA_DELAY_I2S = I2S_DATA_DELAY_1 -}; - -/** - * Frame Sync (FS) source. - */ -enum i2s_frame_sync_source { - /** Frame Sync (FS) is divided from I2S Serial Clock */ - I2S_FRAME_SYNC_SOURCE_SCKDIV, - /** Frame Sync (FS) is input from FS input pin */ - I2S_FRAME_SYNC_SOURCE_FSPIN -}; - -/** - * Frame Sync (FS) output pulse width. - */ -enum i2s_frame_sync_width { - /** Frame Sync (FS) Pulse is one slot width */ - I2S_FRAME_SYNC_WIDTH_SLOT, - /** Frame Sync (FS) Pulse is half a frame width */ - I2S_FRAME_SYNC_WIDTH_HALF_FRAME, - /** Frame Sync (FS) Pulse is one bit width */ - I2S_FRAME_SYNC_WIDTH_BIT, - /** 1-bit wide Frame Sync (FS) per Data sample, only used when Data transfer - * is requested */ - I2S_FRAME_SYNC_WIDTH_BURST -}; - -/** - * Time Slot Size in number of I2S serial clocks (bits). - */ -enum i2s_slot_size { - /** 8-bit slot */ - I2S_SLOT_SIZE_8_BIT, - /** 16-bit slot */ - I2S_SLOT_SIZE_16_BIT, - /** 24-bit slot */ - I2S_SLOT_SIZE_24_BIT, - /** 32-bit slot */ - I2S_SLOT_SIZE_32_BIT -}; - -/** - * DMA channels usage for I2S. - */ -enum i2s_dma_usage { - /** Single DMA channel for all I2S channels */ - I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL, - /** One DMA channel per data channel */ - I2S_DMA_USE_ONE_CHANNEL_PER_DATA_CHANNEL -}; - -/** - * I2S data format, to extend mono data to two channels. - */ -enum i2s_data_format { - /** Normal mode, keep data to its right channel */ - I2S_DATA_FORMAT_STEREO, - /** Assume input is mono data for left channel, the data is duplicated to - * right channel */ - I2S_DATA_FORMAT_MONO -}; - -/** - * I2S data bit order. - */ -enum i2s_bit_order { - /** Transfer Data Most Significant Bit first - * (Default for I2S protocol) - */ - I2S_BIT_ORDER_MSB_FIRST, - /** Transfer Data Least Significant Bit first */ - I2S_BIT_ORDER_LSB_FIRST -}; - -/** - * I2S data bit padding. - */ -enum i2s_bit_padding { - /** Padding with 0 */ - I2S_BIT_PADDING_0, - /** Padding with 1 */ - I2S_BIT_PADDING_1, - /** Padding with MSBit */ - I2S_BIT_PADDING_MSB, - /** Padding with LSBit */ - I2S_BIT_PADDING_LSB, -}; - -/** - * I2S data word adjust. - */ -enum i2s_data_adjust { - /** Data is right adjusted in word */ - I2S_DATA_ADJUST_RIGHT, - /** Data is left adjusted in word */ - I2S_DATA_ADJUST_LEFT -}; - -/** - * I2S data word size. - */ -enum i2s_data_size { - /** 32-bit */ - I2S_DATA_SIZE_32BIT, - /** 24-bit */ - I2S_DATA_SIZE_24BIT, - /** 20-bit */ - I2S_DATA_SIZE_20BIT, - /** 18-bit */ - I2S_DATA_SIZE_18BIT, - /** 16-bit */ - I2S_DATA_SIZE_16BIT, - /** 16-bit compact stereo */ - I2S_DATA_SIZE_16BIT_COMPACT, - /** 8-bit */ - I2S_DATA_SIZE_8BIT, - /** 8-bit compact stereo */ - I2S_DATA_SIZE_8BIT_COMPACT -}; - -/** - * I2S data slot adjust. - */ -enum i2s_slot_adjust { - /** Data is right adjusted in slot */ - I2S_SLOT_ADJUST_RIGHT, - /** Data is left adjusted in slot */ - I2S_SLOT_ADJUST_LEFT -}; - -/** - * I2S data padding. - */ -enum i2s_data_padding { - /** Padding 0 in case of under-run */ - I2S_DATA_PADDING_0, - /** Padding last data in case of under-run */ - I2S_DATA_PADDING_SAME_AS_LAST, - /** Padding last data in case of under-run - * (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */ - I2S_DATA_PADDING_LAST = I2S_DATA_PADDING_SAME_AS_LAST, - /** Padding last data in case of under-run - * (abbr. \c I2S_DATA_PADDING_SAME_AS_LAST) */ - I2S_DATA_PADDING_SAME = I2S_DATA_PADDING_SAME_AS_LAST -}; - -/** - * I2S line default value when slot disabled. - */ -enum i2s_line_default_state { - /** Output default value is 0 */ - I2S_LINE_DEFAULT_0, - /** Output default value is 1 */ - I2S_LINE_DEFAULT_1, - /** Output default value is high impedance */ - I2S_LINE_DEFAULT_HIGH_IMPEDANCE = 3, - /** Output default value is high impedance - * (abbr. \c I2S_LINE_DEFAULT_HIGH_IMPEDANCE) */ - I2S_LINE_DEFAULT_HIZ = I2S_LINE_DEFAULT_HIGH_IMPEDANCE -}; - -/** - * I2S Serializer mode. - */ -enum i2s_serializer_mode { - /** Serializer is used to receive data */ - I2S_SERIALIZER_RECEIVE, - /** Serializer is used to transmit data */ - I2S_SERIALIZER_TRANSMIT, - /** Serializer is used to receive PDM data on each clock edge */ - I2S_SERIALIZER_PDM2 -}; - -/** - * I2S clock unit selection. - */ -enum i2s_clock_unit { - /** Clock Unit channel 0 */ - I2S_CLOCK_UNIT_0, - /** Clock Unit channel 1 */ - I2S_CLOCK_UNIT_1, - /** Number of Clock Unit channels */ - I2S_CLOCK_UNIT_N -}; - -/** - * I2S Serializer selection. - */ -enum i2s_serializer { - /** Serializer channel 0 */ - I2S_SERIALIZER_0, - /** Serializer channel 1 */ - I2S_SERIALIZER_1, - /** Number of Serializer channels */ - I2S_SERIALIZER_N -}; - - -/** - * Configure for I2S pin. - */ -struct i2s_pin_config { - /** GPIO index to access the pin */ - uint8_t gpio; - /** Pin function MUX */ - uint8_t mux; - /** Enable this pin for I2S module */ - bool enable; -}; - -/** - * Configure for I2S clock (SCK). - */ -struct i2s_clock_config { - /** Divide generic clock to master clock output (1~32, 0,1 means no div) */ - uint8_t mck_out_div; - /** Divide generic clock to serial clock (1~32, 0,1 means no div) */ - uint8_t sck_div; - /** Clock source selection */ - enum gclk_generator gclk_src; - /** Master clock source selection: generated or input from pin */ - enum i2s_master_clock_source mck_src; - /** Serial clock source selection: generated or input from pin */ - enum i2s_serial_clock_source sck_src; - /** Invert master clock output */ - bool mck_out_invert; - /** Invert serial clock output */ - bool sck_out_invert; - /** Generate MCK clock output */ - bool mck_out_enable; -}; - -/** - * Configure for I2S frame sync (FS). - */ -struct i2s_frame_sync_config { - /** Frame Sync (FS) generated or input from pin */ - enum i2s_frame_sync_source source; - /** Frame Sync (FS) width */ - enum i2s_frame_sync_width width; - /** Invert Frame Sync (FS) signal before use */ - bool invert_use; - /** Invert Frame Sync (FS) signal before output */ - bool invert_out; -}; - -/** - * Configure for I2S frame. - */ -struct i2s_frame_config { - /** Number of slots in a frame (1~8, 0,1 means minimum 1) */ - uint8_t number_slots; - /** Size of each slot in frame */ - enum i2s_slot_size slot_size; - /** Data delay from Frame Sync (FS) to first data bit */ - enum i2s_data_delay data_delay; - /** Frame sync (FS) */ - struct i2s_frame_sync_config frame_sync; -}; - -/** - * Configure for I2S clock unit. - */ -struct i2s_clock_unit_config { - /** Configure clock generation */ - struct i2s_clock_config clock; - /** Configure frame generation */ - struct i2s_frame_config frame; - - /** Configure master clock pin */ - struct i2s_pin_config mck_pin; - /** Configure serial clock pin */ - struct i2s_pin_config sck_pin; - /** Configure frame sync pin */ - struct i2s_pin_config fs_pin; -}; - -/** - * Configure for I2S Serializer. - */ -struct i2s_serializer_config { - /** Configure Serializer data pin */ - struct i2s_pin_config data_pin; - - /** Set to \c true to loop-back output to input pin for test */ - bool loop_back; - - /** Set to \c true to assumes mono input and duplicate it (left channel) to - * right channel */ - bool mono_mode; - - /** Disable data slot */ - bool disable_data_slot[8]; - - /** Set to \c true to transfer LSB first, \c false to transfer MSB first */ - bool transfer_lsb_first; - /** Data Word Formatting Adjust, - * set to \c true to adjust bits in word to left */ - bool data_adjust_left_in_word; - /** Data Slot Formatting Adjust, - * set to \c true to adjust words in slot to left */ - bool data_adjust_left_in_slot; - - /** Data Word Size */ - enum i2s_data_size data_size; - /** Data Formatting Bit Extension */ - enum i2s_bit_padding bit_padding; - /** Data padding when under-run */ - enum i2s_data_padding data_padding; - - /** DMA usage */ - enum i2s_dma_usage dma_usage; - - /** Clock unit selection */ - enum i2s_clock_unit clock_unit; - - /** Line default state where slot is disabled */ - enum i2s_line_default_state line_default_state; - - /** Serializer Mode */ - enum i2s_serializer_mode mode; -}; - -/** - * \brief I2S Serializer instance struct. - */ -struct i2s_serializer_module { - -#if I2S_CALLBACK_MODE == true - /** Callbacks list for Serializer */ - i2s_serializer_callback_t callback[I2S_SERIALIZER_CALLBACK_N]; - - /** Job buffer */ - void *job_buffer; - /** Requested data words to read/write */ - uint32_t requested_words; - /** Transferred data words for read/write */ - uint32_t transferred_words; - - /** Callback mask for registered callbacks */ - uint8_t registered_callback_mask; - /** Callback mask for enabled callbacks */ - uint8_t enabled_callback_mask; - - /** Status of the ongoing or last transfer job */ - enum status_code job_status; -#endif - - /** Serializer mode */ - enum i2s_serializer_mode mode; - /** Serializer data word size */ - enum i2s_data_size data_size; -}; - -/** - * \brief I2S Software Module instance struct. - */ -struct i2s_module { - /** Module HW register access base */ - I2s *hw; - - /** Module Serializer used */ - struct i2s_serializer_module serializer[2]; -}; - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval false If the module has completed synchronization - * \retval true If the module synchronization is ongoing - */ -static inline bool i2s_is_syncing( - const struct i2s_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return (module_inst->hw->SYNCBUSY.reg > 0); -} - -/** - * \name Driver Initialization - * @{ - */ - -enum status_code i2s_init( - struct i2s_module *const module_inst, - I2s *hw); - -/** @} */ - -/** - * \name Enable/Disable/Reset - * @{ - */ - -/** - * \brief Enable the I2S module. - * - * Enables a I2S module that has been previously initialized. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void i2s_enable(const struct i2s_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) { - /* Sync wait */ - } - module_inst->hw->CTRLA.reg |= I2S_SYNCBUSY_ENABLE; -} - -/** - * \brief Disables the I2S module. - * - * Disables a I2S module. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void i2s_disable(const struct i2s_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - while (module_inst->hw->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) { - /* Sync wait */ - } - - module_inst->hw->INTENCLR.reg = I2S_INTENCLR_MASK; - module_inst->hw->INTFLAG.reg = I2S_INTFLAG_MASK; - module_inst->hw->CTRLA.reg &= ~I2S_SYNCBUSY_ENABLE; -} - -/** - * \brief Resets the I2S module. - * - * Resets the I2S module, restoring all hardware module registers to their - * default values and disabling the module. The I2S module will not be - * accessible while the reset is being performed. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void i2s_reset(const struct i2s_module *const module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - /* Disable the module if it is running */ - if (module_inst->hw->CTRLA.reg & I2S_CTRLA_ENABLE) { - i2s_disable(module_inst); - while (i2s_is_syncing(module_inst)) { - /* Sync wait */ - } - } - /* Reset the HW module */ - module_inst->hw->CTRLA.reg = I2S_CTRLA_SWRST; -} - -/** @} */ - -/** - * \name Clock Unit Initialization and Configuration - * @{ - */ - -/** - * \brief Initializes config with predefined default values for I2S clock unit. - * - * This function will initialize a given I2S Clock Unit configuration structure - * to a set of known default values. This function should be called on any new - * instance of the configuration structures before being modified by the user - * application. - * - * The default configuration is as follows: - * - The clock unit does not generate output clocks (MCK, SCK, and FS) - * - The pins (MCK, SCK, and FS) and MUX configurations are not set - * - * \param[out] config Pointer to a I2S module clock unit configuration struct - * to set - */ -static inline void i2s_clock_unit_get_config_defaults( - struct i2s_clock_unit_config *const config) -{ - Assert(config); - - config->clock.mck_out_enable = false; - config->clock.gclk_src = GCLK_GENERATOR_0; - - config->clock.mck_src = I2S_MASTER_CLOCK_SOURCE_GCLK; - config->clock.mck_out_div = 1; - config->clock.mck_out_invert = false; - - config->clock.sck_src = I2S_SERIAL_CLOCK_SOURCE_MCKDIV; - config->clock.sck_div = 1; - config->clock.sck_out_invert = false; - - config->frame.number_slots = 1; - config->frame.slot_size = I2S_SLOT_SIZE_32_BIT; - config->frame.data_delay = I2S_DATA_DELAY_I2S; - - config->frame.frame_sync.source = I2S_FRAME_SYNC_SOURCE_SCKDIV; - config->frame.frame_sync.width = I2S_FRAME_SYNC_WIDTH_HALF_FRAME; - config->frame.frame_sync.invert_use = false; - config->frame.frame_sync.invert_out = false; - - config->mck_pin.enable = false; - config->mck_pin.mux = 0; - config->mck_pin.gpio = 0; - - config->sck_pin.enable = false; - config->sck_pin.mux = 0; - config->sck_pin.gpio = 0; - - config->fs_pin.enable = false; - config->fs_pin.mux = 0; - config->fs_pin.gpio = 0; -} - -enum status_code i2s_clock_unit_set_config( - struct i2s_module *const module_inst, - const enum i2s_clock_unit clock_unit, - const struct i2s_clock_unit_config *config); - -/** @} */ - - -/** - * \name Clock Unit Enable/Disable - * @{ - */ - -/** - * \brief Enable the Specified Clock Unit of I2S module. - * - * Enables a Clock Unit in I2S module that has been previously initialized. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] clock_unit I2S Clock Unit to enable - */ -static inline void i2s_clock_unit_enable( - const struct i2s_module *const module_inst, - const enum i2s_clock_unit clock_unit) -{ - uint32_t cken_bit; - - Assert(module_inst); - Assert(module_inst->hw); - - cken_bit = I2S_CTRLA_CKEN0 << clock_unit; - - while (module_inst->hw->SYNCBUSY.reg & cken_bit) { - /* Sync wait */ - } - module_inst->hw->CTRLA.reg |= cken_bit; -} - -/** - * \brief Disable the Specified Clock Unit of I2S module. - * - * Disables a Clock Unit in I2S module that has been previously initialized. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] clock_unit I2S Clock Unit to disable - */ -static inline void i2s_clock_unit_disable( - const struct i2s_module *const module_inst, - const enum i2s_clock_unit clock_unit) -{ - uint32_t cken_bit; - - Assert(module_inst); - Assert(module_inst->hw); - - cken_bit = I2S_CTRLA_CKEN0 << clock_unit; - - while (module_inst->hw->SYNCBUSY.reg & cken_bit) { - /* Sync wait */ - } - module_inst->hw->CTRLA.reg &= ~cken_bit; -} - -/** @} */ - - -/** - * \name Serializer Initialization and Configuration - * @{ - */ - -/** - * \brief Initializes config with predefined default values for I2S Serializer. - * - * This function will initialize a given I2S Clock Unit configuration structure - * to a set of known default values. This function should be called on any new - * instance of the configuration structures before being modified by the user - * application. - * - * The default configuration is as follows: - * - Output data does not internally loopback to input line - * - Does not extend mono data (left channel) to right channel - * - None of the data slot is disabled - * - MSB of I2S data is transferred first - * - In data word data is adjusted right - * - In slot data word is adjusted left - * - The data size is 16-bit width - * - I2S will padd 0 to not defined bits - * - I2S will padd 0 to not defined words - * - I2S will use single DMA channel for all data channels - * - I2S will use clock unit 0 to serve as clock - * - The default data line state is 0, when there is no data - * - I2S will transmit data to output line - * - The data pin and MUX configuration are not set - * - * \param[out] config Pointer to a I2S module Serializer configuration struct - * to set - */ -static inline void i2s_serializer_get_config_defaults( - struct i2s_serializer_config *const config) -{ - config->loop_back = false; - - config->mono_mode = false; - - config->disable_data_slot[0] = false; - config->disable_data_slot[1] = false; - config->disable_data_slot[2] = false; - config->disable_data_slot[3] = false; - config->disable_data_slot[4] = false; - config->disable_data_slot[5] = false; - config->disable_data_slot[6] = false; - config->disable_data_slot[7] = false; - - config->transfer_lsb_first = false; - config->data_adjust_left_in_word = false; - config->data_adjust_left_in_slot = true; - - config->data_size = I2S_DATA_SIZE_16BIT; - - config->bit_padding = I2S_BIT_PADDING_0; - config->data_padding = I2S_DATA_PADDING_0; - - config->dma_usage = I2S_DMA_USE_SINGLE_CHANNEL_FOR_ALL; - - config->clock_unit = I2S_CLOCK_UNIT_0; - - config->line_default_state = I2S_LINE_DEFAULT_0; - - config->mode = I2S_SERIALIZER_TRANSMIT; - - config->data_pin.enable = false; - config->data_pin.gpio = 0; - config->data_pin.mux = 0; -} - -enum status_code i2s_serializer_set_config( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const struct i2s_serializer_config *config); -/** @} */ - -/** - * \name Serializer Enable/Disable - * @{ - */ - -/** - * \brief Enable the Specified Serializer of I2S module. - * - * Enables a Serializer in I2S module that has been previously initialized. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer I2S Serializer to enable - */ -static inline void i2s_serializer_enable( - const struct i2s_module *const module_inst, - const enum i2s_serializer serializer) -{ - uint32_t seren_bit; - - Assert(module_inst); - Assert(module_inst->hw); - - seren_bit = I2S_CTRLA_SEREN0 << serializer; - - while (module_inst->hw->SYNCBUSY.reg & seren_bit) { - /* Sync wait */ - } - module_inst->hw->CTRLA.reg |= seren_bit; -} - -/** - * \brief Disable the Specified Serializer of I2S module. - * - * Disables a Serializer in I2S module that has been previously initialized. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer I2S Serializer to disable - */ -static inline void i2s_serializer_disable( - const struct i2s_module *const module_inst, - const enum i2s_serializer serializer) -{ - uint32_t seren_bit; - - Assert(module_inst); - Assert(module_inst->hw); - - seren_bit = I2S_CTRLA_SEREN0 << serializer; - - while (module_inst->hw->SYNCBUSY.reg & seren_bit) { - /* Sync wait */ - } - module_inst->hw->CTRLA.reg &= ~seren_bit; -} -/** @} */ - -/** - * \name Status Management - * @{ - */ - -uint32_t i2s_get_status( - const struct i2s_module *const module_inst); - -void i2s_clear_status( - const struct i2s_module *const module_inst, - uint32_t status); - - -enum status_code i2s_enable_status_interrupt( - struct i2s_module *const module_inst, - uint32_t status); - -void i2s_disable_status_interrupt( - struct i2s_module *const module_inst, - uint32_t status); - -/** @}*/ - -/** - * \name Data Read/Write - * @{ - */ - -/** - * \brief Write a data word to the specified Serializer of I2S module - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The Serializer to write to - * \param[in] data The data to write - * - */ -static inline void i2s_serializer_write_wait( - const struct i2s_module *const module_inst, - enum i2s_serializer serializer, - uint32_t data) -{ - uint32_t sync_bit, ready_bit; - - Assert(module_inst); - Assert(module_inst->hw); - - ready_bit = I2S_INTFLAG_TXRDY0 << serializer; - while (!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait until ready to transmit */ - } - sync_bit = I2S_SYNCBUSY_DATA0 << serializer; - while (module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait sync */ - } - /* Write data */ - module_inst->hw->DATA[serializer].reg = data; - module_inst->hw->INTFLAG.reg = ready_bit; -} - -/** - * \brief Read a data word from the specified Serializer of I2S module - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The Serializer to read - */ -static inline uint32_t i2s_serializer_read_wait( - const struct i2s_module *const module_inst, - enum i2s_serializer serializer) -{ - uint32_t sync_bit, ready_bit; - uint32_t data; - - Assert(module_inst); - Assert(module_inst->hw); - - ready_bit = I2S_INTFLAG_RXRDY0 << serializer; - while (!(module_inst->hw->INTFLAG.reg & ready_bit)) { - /* Wait until ready to transmit */ - } - sync_bit = I2S_SYNCBUSY_DATA0 << serializer; - while (module_inst->hw->SYNCBUSY.reg & sync_bit) { - /* Wait sync */ - } - /* Read data */ - data = module_inst->hw->DATA[serializer].reg; - module_inst->hw->INTFLAG.reg = ready_bit; - return data; -} - -enum status_code i2s_serializer_write_buffer_wait( - const struct i2s_module *const module_inst, - enum i2s_serializer serializer, - void *buffer, uint32_t size); - -enum status_code i2s_serializer_read_buffer_wait( - const struct i2s_module *const module_inst, - enum i2s_serializer serializer, - void *buffer, uint32_t size); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - - -/** - * \page asfdoc_sam0_i2s_extra Extra Information for I2S Driver - * - * \section asfdoc_sam0_i2s_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
I2S, IISInter-IC Sound Controller
MCKMaster Clock
SCKSerial Clock
FSFrame Sync
SDSerial Data
ADCAnalog-to-Digital Converter
DACDigital-to-Analog Converter
TDMTime Division Multiplexed
PDMPulse Density Modulation
LSBLeast Significant Bit
MSBMost Significant Bit
DSPDigital Signal Processor
- * - * - * \section asfdoc_sam0_i2s_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_i2s_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_i2s_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - -/** - * \page asfdoc_sam0_i2s_exqsg Examples for I2S Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_i2s_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_i2s_basic_use_case - * \if I2S_CALLBACK_MODE - * - \subpage asfdoc_sam0_i2s_callback_use_case - * \endif - * - \subpage asfdoc_sam0_i2s_dma_use_case - * - * \page asfdoc_sam0_i2s_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42255B12/2015Added support for SAM DA1
42255A01/2014Initial release
- */ - -#endif /* #ifndef I2S_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/i2s/i2s_callback.c b/atmel-samd/asf/sam0/drivers/i2s/i2s_callback.c deleted file mode 100644 index fae543c119810..0000000000000 --- a/atmel-samd/asf/sam0/drivers/i2s/i2s_callback.c +++ /dev/null @@ -1,392 +0,0 @@ -/** - * \file - * - * \brief SAM I2S - Inter-IC Sound Controller - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2s_callback.h" - -struct i2s_module *_i2s_instances[I2S_INST_NUM]; - -static void _i2s_interrupt_handler(const uint8_t instance) -{ - struct i2s_module *module = _i2s_instances[instance]; - struct i2s_serializer_module *data_module; - - /* Get interrupt flags */ - uint32_t intflag = module->hw->INTFLAG.reg; - uint32_t inten = intflag & module->hw->INTENSET.reg; - uint32_t run_flags = (I2S_INTFLAG_TXUR0 | I2S_INTFLAG_RXOR0); - uint32_t ready_flags = (I2S_INTFLAG_TXRDY0 | I2S_INTFLAG_RXRDY0); - uint32_t call_mask; - uint8_t serializer; - - for (serializer = 0; serializer < 2; serializer ++) { - data_module = &module->serializer[serializer]; - call_mask = data_module->registered_callback_mask & - data_module->enabled_callback_mask; - - if (intflag & (run_flags | ready_flags)) { - /* Serializer Tx ready */ - if ((I2S_INTFLAG_TXRDY0 << serializer) & inten) { - - if (data_module->transferred_words < - data_module->requested_words) { - - /* Write data word */ - while (module->hw->SYNCBUSY.reg & - (I2S_SYNCBUSY_DATA0 << serializer)) { - /* Wait sync */ - } - switch(data_module->data_size) { - case I2S_DATA_SIZE_32BIT: - case I2S_DATA_SIZE_24BIT: - case I2S_DATA_SIZE_20BIT: - case I2S_DATA_SIZE_18BIT: - module->hw->DATA[serializer].reg = - ((uint32_t*)data_module->job_buffer) \ - [data_module->transferred_words]; - break; - case I2S_DATA_SIZE_16BIT: - case I2S_DATA_SIZE_16BIT_COMPACT: - module->hw->DATA[serializer].reg = - ((uint16_t*)data_module->job_buffer) \ - [data_module->transferred_words]; - break; - default: - module->hw->DATA[serializer].reg = - ((uint8_t*)data_module->job_buffer) \ - [data_module->transferred_words]; - } - /* Clear interrupt status */ - module->hw->INTFLAG.reg = I2S_INTFLAG_TXRDY0 << serializer; - - /* Count data */ - data_module->transferred_words ++; - } - - /* Check if the buffer is done */ - if (data_module->transferred_words >= - data_module->requested_words) { - /* It's done */ - data_module->job_status = STATUS_OK; - /* Disable interrupt */ - module->hw->INTENCLR.reg = - I2S_INTFLAG_TXRDY0 << serializer; - /* Invoke callback */ - if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) & - call_mask) { - (data_module->callback \ - [I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module); - } - } - return; - } - /* Serializer Rx ready */ - if ((I2S_INTFLAG_RXRDY0 << serializer) & inten) { - /* Read data word */ - switch(data_module->data_size) { - case I2S_DATA_SIZE_32BIT: - case I2S_DATA_SIZE_24BIT: - case I2S_DATA_SIZE_20BIT: - case I2S_DATA_SIZE_18BIT: - ((uint32_t*)data_module->job_buffer) \ - [data_module->transferred_words] = - module->hw->DATA[serializer].reg; - break; - case I2S_DATA_SIZE_16BIT: - case I2S_DATA_SIZE_16BIT_COMPACT: - ((uint16_t*)data_module->job_buffer) \ - [data_module->transferred_words] = - (uint16_t)module->hw->DATA[serializer].reg; - break; - default: - ((uint8_t*)data_module->job_buffer) \ - [data_module->transferred_words] = - (uint8_t)module->hw->DATA[serializer].reg; - - } - /* Clear interrupt status */ - module->hw->INTFLAG.reg = I2S_INTFLAG_RXRDY0 << serializer; - - /* Count data */ - data_module->transferred_words ++; - - /* Check if the buffer is done */ - if (data_module->transferred_words >= - data_module->requested_words) { - if (data_module->job_status == STATUS_BUSY) { - data_module->job_status = STATUS_OK; - /* Disable interrupt */ - module->hw->INTENCLR.reg = - I2S_INTFLAG_RXRDY0 << serializer; - /* Invoke callback */ - if ((1 << I2S_SERIALIZER_CALLBACK_BUFFER_DONE) & - call_mask) { - (data_module->callback \ - [I2S_SERIALIZER_CALLBACK_BUFFER_DONE])(module); - } - } - } - return; - } - /* Serializer Tx undrerun or Rx overrun */ - if (run_flags & inten) { - module->hw->INTFLAG.reg = I2S_INTFLAG_TXUR0 << serializer; - if ((1 << I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN) & - call_mask) { - (data_module->callback \ - [I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN])(module); - } - return; - } - } - run_flags <<= 1; - ready_flags <<= 1; - } - -} - -/** Interrupt handler for the I2S module */ -void I2S_Handler(void) -{ - _i2s_interrupt_handler(0); -} - -/** - * \brief Write buffer to the specified Serializer of I2S module - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The serializer to write to - * \param[in] buffer The data buffer to write - * \param[in] size Number of data words to write - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The data was sent successfully - * \retval STATUS_ERR_DENIED The serializer is not in transmit mode - * \retval STATUS_ERR_INVALID_ARG An invalid buffer pointer was supplied - */ -enum status_code i2s_serializer_write_buffer_job( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const void *buffer, - const uint32_t size) -{ - struct i2s_serializer_module *data_module; - - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(serializer < I2S_SERIALIZER_N); - - data_module = &module_inst->serializer[serializer]; - - /* Serializer must in transmit mode */ - if (data_module->mode != I2S_SERIALIZER_TRANSMIT) { - return STATUS_ERR_DENIED; - } - - /* Buffer should be aligned */ - switch(data_module->data_size) { - case I2S_DATA_SIZE_32BIT: - case I2S_DATA_SIZE_24BIT: - case I2S_DATA_SIZE_20BIT: - case I2S_DATA_SIZE_18BIT: - if ((uint32_t)buffer & 0x3) { - return STATUS_ERR_INVALID_ARG; - } - break; - case I2S_DATA_SIZE_16BIT: - case I2S_DATA_SIZE_16BIT_COMPACT: - if ((uint32_t)buffer & 0x1) { - return STATUS_ERR_INVALID_ARG; - } - break; - default: - break; - } - - data_module = &module_inst->serializer[serializer]; - if (data_module->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } - - data_module->job_status = STATUS_BUSY; - data_module->requested_words = size; - data_module->transferred_words = 0; - data_module->job_buffer = (void*)buffer; - - module_inst->hw->INTENSET.reg = (I2S_INTENSET_TXRDY0 << serializer); - - return STATUS_OK; -} - -/** - * \brief Read from the specified Serializer of I2S module to a buffer - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The serializer to write to - * \param[out] buffer The buffer to fill read data - * \param[in] size Number of data words to read - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The data was sent successfully - * \retval STATUS_ERR_DENIED The serializer is not in receive mode - * \retval STATUS_ERR_INVALID_ARG An invalid buffer pointer was supplied - */ -enum status_code i2s_serializer_read_buffer_job( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - void *buffer, - const uint32_t size) -{ - struct i2s_serializer_module *data_module; - - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(serializer < I2S_SERIALIZER_N); - - data_module = &module_inst->serializer[serializer]; - - /* Serializer must in receive mode */ - if (data_module->mode == I2S_SERIALIZER_TRANSMIT) { - return STATUS_ERR_DENIED; - } - - /* Data buffer must be aligned */ - switch(data_module->data_size) { - case I2S_DATA_SIZE_32BIT: - case I2S_DATA_SIZE_24BIT: - case I2S_DATA_SIZE_20BIT: - case I2S_DATA_SIZE_18BIT: - if ((uint32_t)buffer & 0x3) { - return STATUS_ERR_INVALID_ARG; - } - break; - case I2S_DATA_SIZE_16BIT: - case I2S_DATA_SIZE_16BIT_COMPACT: - if ((uint32_t)buffer & 0x1) { - return STATUS_ERR_INVALID_ARG; - } - break; - default: - break; - } - - data_module = &module_inst->serializer[serializer]; - if (data_module->job_status == STATUS_BUSY) { - return STATUS_BUSY; - } - - data_module->job_status = STATUS_BUSY; - data_module->requested_words = size; - data_module->transferred_words = 0; - data_module->job_buffer = (void*)buffer; - - module_inst->hw->INTENCLR.reg = (I2S_INTENSET_RXRDY0 << serializer); - module_inst->hw->INTENSET.reg = (I2S_INTENSET_RXRDY0 << serializer); - - return STATUS_OK; -} - -/** - * \brief Aborts an ongoing job running on serializer - * - * Aborts an ongoing job. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The serializer which runs the job - * \param[in] job_type Type of job to abort - */ -void i2s_serializer_abort_job( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const enum i2s_job_type job_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(serializer < I2S_SERIALIZER_N); - - if (job_type == I2S_JOB_WRITE_BUFFER) { - /* Disable interrupt */ - module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_TXRDY0 << serializer); - /* Mark job as aborted */ - module_inst->serializer[serializer].job_status = STATUS_ABORTED; - } else if (job_type == I2S_JOB_READ_BUFFER) { - /* Disable interrupt */ - module_inst->hw->INTENCLR.reg = (I2S_INTENCLR_RXRDY0 << serializer); - /* Mark job as aborted */ - module_inst->serializer[serializer].job_status = STATUS_ABORTED; - } -} - -/** - * \brief Gets the status of a job running on serializer - * - * Gets the status of an ongoing or the last job. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] serializer The serializer which runs the job - * \param[in] job_type Type of job to abort - * - * \return Status of the job. - */ -enum status_code i2s_serializer_get_job_status( - const struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const enum i2s_job_type job_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(serializer < I2S_SERIALIZER_N); - - if (job_type == I2S_JOB_WRITE_BUFFER || job_type == I2S_JOB_READ_BUFFER) { - return module_inst->serializer[serializer].job_status; - } else { - return STATUS_ERR_INVALID_ARG; - } -} diff --git a/atmel-samd/asf/sam0/drivers/i2s/i2s_callback.h b/atmel-samd/asf/sam0/drivers/i2s/i2s_callback.h deleted file mode 100644 index 6fa98f3e177ba..0000000000000 --- a/atmel-samd/asf/sam0/drivers/i2s/i2s_callback.h +++ /dev/null @@ -1,234 +0,0 @@ -/** - * \file - * - * \brief SAM I2S - Inter-IC Sound Controller - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2S_CALLBACK_H_INCLUDED -#define I2S_CALLBACK_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_i2s_group - * - * @{ - */ - -#include - -/** - * Enum for the possible types of I2S asynchronous jobs that may be issued to - * the driver. - */ -enum i2s_job_type { - /** Asynchronous I2S write from a user provided buffer */ - I2S_JOB_WRITE_BUFFER, - /** Asynchronous I2S read into a user provided buffer */ - I2S_JOB_READ_BUFFER -}; - -/** - * \name Callback Management - * @{ - */ - -/** - * \brief Registers a callback for serializer - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by for the interrupt handler to call it - * when the condition for the callback is met. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] serializer The serializer that generates callback - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - * - */ -static inline void i2s_serializer_register_callback( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const i2s_serializer_callback_t callback_func, - const enum i2s_serializer_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(serializer < I2S_SERIALIZER_N); - - module_inst->serializer[serializer].callback[callback_type] = callback_func; - module_inst->serializer[serializer].registered_callback_mask |= - (1u << callback_type); -} - -/** - * \brief Unregisters a callback for serializer - * - * Unregisters a callback function which is implemented by the user. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] serializer The serializer that generates callback - * \param[in] callback_type Callback type given by an enum - * - */ -static inline void i2s_serializer_unregister_callback( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const enum i2s_serializer_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(serializer < I2S_SERIALIZER_N); - - module_inst->serializer[serializer].callback[callback_type] = NULL; - module_inst->serializer[serializer].registered_callback_mask &= - ~(1u << callback_type); -} - -/** - * \brief Enables callback for serializer - * - * Enables the callback function registered by \ref - * i2s_serializer_register_callback. The callback function will be called from - * the interrupt handler when the conditions for the callback type are met. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] serializer The serializer that generates callback - * \param[in] callback_type Callback type given by an enum - * - */ -static inline void i2s_serializer_enable_callback( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const enum i2s_serializer_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(serializer < I2S_SERIALIZER_N); - - module_inst->serializer[serializer].enabled_callback_mask |= - (1u << callback_type); - if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type) { - return; - } - module_inst->hw->INTENSET.reg = - (module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ? - (I2S_INTFLAG_TXUR0 << serializer) : - (I2S_INTFLAG_RXOR0 << serializer); -} - -/** - * \brief Disables callback for Serializer - * - * Disables the callback function registered by the \ref - * i2s_serializer_register_callback. - * - * \param[in] module Pointer to ADC software instance struct - * \param[in] serializer The serializer that generates callback - * \param[in] callback_type Callback type given by an enum - * - */ -static inline void i2s_serializer_disable_callback( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const enum i2s_serializer_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(serializer < I2S_SERIALIZER_N); - - module_inst->serializer[serializer].enabled_callback_mask &= - ~(1u << callback_type); - if (I2S_SERIALIZER_CALLBACK_OVER_UNDER_RUN != callback_type) { - return; - } - module_inst->hw->INTENCLR.reg = - (module_inst->serializer[serializer].mode == I2S_SERIALIZER_TRANSMIT) ? - (I2S_INTFLAG_TXUR0 << serializer) : - (I2S_INTFLAG_RXOR0 << serializer); -} - -/** @} */ - -/** - * \name Job Management - * - * @{ - */ - -enum status_code i2s_serializer_write_buffer_job( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const void *buffer, - const uint32_t size); - -enum status_code i2s_serializer_read_buffer_job( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - void *buffer, - const uint32_t size); - -void i2s_serializer_abort_job( - struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const enum i2s_job_type job_type); - -enum status_code i2s_serializer_get_job_status( - const struct i2s_module *const module_inst, - const enum i2s_serializer serializer, - const enum i2s_job_type job_type); - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* #ifndef I2S_CALLBACK_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/nvm/nvm.c b/atmel-samd/asf/sam0/drivers/nvm/nvm.c deleted file mode 100644 index 53a0d7beb391c..0000000000000 --- a/atmel-samd/asf/sam0/drivers/nvm/nvm.c +++ /dev/null @@ -1,1146 +0,0 @@ -/** - * \file - * - * \brief SAM Non Volatile Memory driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "nvm.h" -#include -#include -#include - -/** - * \internal Internal device instance struct - * - * This struct contains information about the NVM module which is - * often used by the different functions. The information is loaded - * into the struct in the nvm_init() function. - */ -struct _nvm_module { - /** Number of bytes contained per page. */ - uint16_t page_size; - /** Total number of pages in the NVM memory. */ - uint16_t number_of_pages; - /** If \c false, a page write command will be issued automatically when the - * page buffer is full. */ - bool manual_page_write; -}; - -/** - * \internal Instance of the internal device struct - */ -static struct _nvm_module _nvm_dev; - -/** - * \internal Pointer to the NVM MEMORY region start address - */ -#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR) - -/** - * \internal Pointer to the NVM USER MEMORY region start address - */ -#define NVM_USER_MEMORY ((volatile uint16_t *)NVMCTRL_USER) - - -/** - * \brief Sets the up the NVM hardware module based on the configuration. - * - * Writes a given configuration of an NVM controller configuration to the - * hardware module, and initializes the internal device struct. - * - * \param[in] config Configuration settings for the NVM controller - * - * \note The security bit must be cleared in order successfully use this - * function. This can only be done by a chip erase. - * - * \return Status of the configuration procedure. - * - * \retval STATUS_OK If the initialization was a success - * \retval STATUS_BUSY If the module was busy when the operation was attempted - * \retval STATUS_ERR_IO If the security bit has been set, preventing the - * EEPROM and/or auxiliary space configuration from being - * altered - */ -enum status_code nvm_set_config( - const struct nvm_config *const config) -{ - /* Sanity check argument */ - Assert(config); - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, MCLK_APBBMASK_NVMCTRL); -#else - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_NVMCTRL); -#endif - - /* Clear error flags */ - nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK; - - /* Check if the module is busy */ - if (!nvm_is_ready()) { - return STATUS_BUSY; - } - -#if (!SAMC20) && (!SAMC21) - /* Writing configuration to the CTRLB register */ - nvm_module->CTRLB.reg = - NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) | - ((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) | - NVMCTRL_CTRLB_RWS(config->wait_states) | - ((config->disable_cache & 0x01) << NVMCTRL_CTRLB_CACHEDIS_Pos) | - NVMCTRL_CTRLB_READMODE(config->cache_readmode); -#else - uint8_t cache_disable_value = 0; - if (config->disable_rww_cache == false) { - cache_disable_value = 0x02; - } else { - cache_disable_value = (config->disable_cache & 0x01); - } - /* Writing configuration to the CTRLB register */ - nvm_module->CTRLB.reg = - NVMCTRL_CTRLB_SLEEPPRM(config->sleep_power_mode) | - ((config->manual_page_write & 0x01) << NVMCTRL_CTRLB_MANW_Pos) | - NVMCTRL_CTRLB_RWS(config->wait_states) | - (cache_disable_value << NVMCTRL_CTRLB_CACHEDIS_Pos) | - NVMCTRL_CTRLB_READMODE(config->cache_readmode); -#endif - - /* Initialize the internal device struct */ - _nvm_dev.page_size = (8 << nvm_module->PARAM.bit.PSZ); - _nvm_dev.number_of_pages = nvm_module->PARAM.bit.NVMP; - _nvm_dev.manual_page_write = config->manual_page_write; - - /* If the security bit is set, the auxiliary space cannot be written */ - if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB) { - return STATUS_ERR_IO; - } - - return STATUS_OK; -} - -/** - * \brief Executes a command on the NVM controller. - * - * Executes an asynchronous command on the NVM controller, to perform a requested - * action such as an NVM page read or write operation. - * - * \note The function will return before the execution of the given command is - * completed. - * - * \param[in] command Command to issue to the NVM controller - * \param[in] address Address to pass to the NVM controller in NVM memory - * space - * \param[in] parameter Parameter to pass to the NVM controller, not used - * for this driver - * - * \return Status of the attempt to execute a command. - * - * \retval STATUS_OK If the command was accepted and execution - * is now in progress - * \retval STATUS_BUSY If the NVM controller was already busy - * executing a command when the new command - * was issued - * \retval STATUS_ERR_IO If the command was invalid due to memory or - * security locking - * \retval STATUS_ERR_INVALID_ARG If the given command was invalid or - * unsupported - * \retval STATUS_ERR_BAD_ADDRESS If the given address was invalid - */ -enum status_code nvm_execute_command( - const enum nvm_command command, - const uint32_t address, - const uint32_t parameter) -{ - uint32_t ctrlb_bak; - - /* Check that the address given is valid */ - if (address > ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages) - && !(address >= NVMCTRL_AUX0_ADDRESS && address <= NVMCTRL_AUX1_ADDRESS )){ -#ifdef FEATURE_NVM_RWWEE - if (address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR) - || address < NVMCTRL_RWW_EEPROM_ADDR){ - return STATUS_ERR_BAD_ADDRESS; - } -#else - return STATUS_ERR_BAD_ADDRESS; -#endif - } - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - /* Turn off cache before issuing flash commands */ - ctrlb_bak = nvm_module->CTRLB.reg; -#if (SAMC20) || (SAMC21) - nvm_module->CTRLB.reg = ((ctrlb_bak &(~(NVMCTRL_CTRLB_CACHEDIS(0x2)))) - | NVMCTRL_CTRLB_CACHEDIS(0x1)); -#else - nvm_module->CTRLB.reg = ctrlb_bak | NVMCTRL_CTRLB_CACHEDIS; -#endif - - /* Clear error flags */ - nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK; - - /* Check if the module is busy */ - if (!nvm_is_ready()) { - /* Restore the setting */ - nvm_module->CTRLB.reg = ctrlb_bak; - return STATUS_BUSY; - } - - switch (command) { - - /* Commands requiring address (protected) */ - case NVM_COMMAND_ERASE_AUX_ROW: - case NVM_COMMAND_WRITE_AUX_ROW: - - /* Auxiliary space cannot be accessed if the security bit is set */ - if (nvm_module->STATUS.reg & NVMCTRL_STATUS_SB) { - /* Restore the setting */ - nvm_module->CTRLB.reg = ctrlb_bak; - return STATUS_ERR_IO; - } - - /* Set address, command will be issued elsewhere */ - nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4]; - break; - - /* Commands requiring address (unprotected) */ - case NVM_COMMAND_ERASE_ROW: - case NVM_COMMAND_WRITE_PAGE: - case NVM_COMMAND_LOCK_REGION: - case NVM_COMMAND_UNLOCK_REGION: -#ifdef FEATURE_NVM_RWWEE - case NVM_COMMAND_RWWEE_ERASE_ROW: - case NVM_COMMAND_RWWEE_WRITE_PAGE: -#endif - - /* Set address, command will be issued elsewhere */ - nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[address / 4]; - break; - - /* Commands not requiring address */ - case NVM_COMMAND_PAGE_BUFFER_CLEAR: - case NVM_COMMAND_SET_SECURITY_BIT: - case NVM_COMMAND_ENTER_LOW_POWER_MODE: - case NVM_COMMAND_EXIT_LOW_POWER_MODE: - break; - - default: - /* Restore the setting */ - nvm_module->CTRLB.reg = ctrlb_bak; - return STATUS_ERR_INVALID_ARG; - } - - /* Set command */ - nvm_module->CTRLA.reg = command | NVMCTRL_CTRLA_CMDEX_KEY; - - /* Wait for the NVM controller to become ready */ - while (!nvm_is_ready()) { - } - - /* Restore the setting */ - nvm_module->CTRLB.reg = ctrlb_bak; - - return STATUS_OK; -} - -/** - * \brief Updates an arbitrary section of a page with new data. - * - * Writes from a buffer to a given page in the NVM memory, retaining any - * unmodified data already stored in the page. - * - * \note If manual write mode is enable, the write command must be executed after - * this function, otherwise the data will not write to NVM from page buffer. - * - * \warning This routine is unsafe if data integrity is critical; a system reset - * during the update process will result in up to one row of data being - * lost. If corruption must be avoided in all circumstances (including - * power loss or system reset) this function should not be used. - * - * \param[in] destination_address Destination page address to write to - * \param[in] buffer Pointer to buffer where the data to write is - * stored - * \param[in] offset Number of bytes to offset the data write in - * the page - * \param[in] length Number of bytes in the page to update - * - * \return Status of the attempt to update a page. - * - * \retval STATUS_OK Requested NVM memory page was successfully - * read - * \retval STATUS_BUSY NVM controller was busy when the operation - * was attempted - * \retval STATUS_ERR_BAD_ADDRESS The requested address was outside the - * acceptable range of the NVM memory region - * \retval STATUS_ERR_INVALID_ARG The supplied length and offset was invalid - */ -enum status_code nvm_update_buffer( - const uint32_t destination_address, - uint8_t *const buffer, - uint16_t offset, - uint16_t length) -{ - enum status_code error_code = STATUS_OK; - uint8_t row_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; - - /* Ensure the read does not overflow the page size */ - if ((offset + length) > _nvm_dev.page_size) { - return STATUS_ERR_INVALID_ARG; - } - - /* Calculate the starting row address of the page to update */ - uint32_t row_start_address = - destination_address & ~((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1); - - /* Read in the current row contents */ - for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++) { - do - { - error_code = nvm_read_buffer( - row_start_address + (i * _nvm_dev.page_size), - row_buffer[i], _nvm_dev.page_size); - } while (error_code == STATUS_BUSY); - - if (error_code != STATUS_OK) { - return error_code; - } - } - - /* Calculate the starting page in the row that is to be updated */ - uint8_t page_in_row = - (destination_address % (_nvm_dev.page_size * NVMCTRL_ROW_PAGES)) / - _nvm_dev.page_size; - - /* Update the specified bytes in the page buffer */ - for (uint32_t i = 0; i < length; i++) { - row_buffer[page_in_row][offset + i] = buffer[i]; - } - - system_interrupt_enter_critical_section(); - - /* Erase the row */ - do - { - error_code = nvm_erase_row(row_start_address); - } while (error_code == STATUS_BUSY); - - if (error_code != STATUS_OK) { - system_interrupt_leave_critical_section(); - return error_code; - } - - /* Write the updated row contents to the erased row */ - for (uint32_t i = 0; i < NVMCTRL_ROW_PAGES; i++) { - do - { - error_code = nvm_write_buffer( - row_start_address + (i * _nvm_dev.page_size), - row_buffer[i], _nvm_dev.page_size); - } while (error_code == STATUS_BUSY); - - if (error_code != STATUS_OK) { - system_interrupt_leave_critical_section(); - return error_code; - } - } - - system_interrupt_leave_critical_section(); - - return error_code; -} - -/** - * \brief Writes a number of bytes to a page in the NVM memory region. - * - * Writes from a buffer to a given page address in the NVM memory. - * - * \param[in] destination_address Destination page address to write to - * \param[in] buffer Pointer to buffer where the data to write is - * stored - * \param[in] length Number of bytes in the page to write - * - * \note If writing to a page that has previously been written to, the page's - * row should be erased (via \ref nvm_erase_row()) before attempting to - * write new data to the page. - * - * \note For SAM D21 RWW devices, see \c SAMD21_64K, command \c NVM_COMMAND_RWWEE_WRITE_PAGE - * must be executed before any other commands after writing a page, - * refer to errata 13588. - * - * \note If manual write mode is enabled, the write command must be executed after - * this function, otherwise the data will not write to NVM from page buffer. - * - * \return Status of the attempt to write a page. - * - * \retval STATUS_OK Requested NVM memory page was successfully - * read - * \retval STATUS_BUSY NVM controller was busy when the operation - * was attempted - * \retval STATUS_ERR_BAD_ADDRESS The requested address was outside the - * acceptable range of the NVM memory region or - * not aligned to the start of a page - * \retval STATUS_ERR_INVALID_ARG The supplied write length was invalid - */ -enum status_code nvm_write_buffer( - const uint32_t destination_address, - const uint8_t *buffer, - uint16_t length) -{ -#ifdef FEATURE_NVM_RWWEE - bool is_rww_eeprom = false; -#endif - - /* Check if the destination address is valid */ - if (destination_address > - ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) { -#ifdef FEATURE_NVM_RWWEE - if (destination_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR) - || destination_address < NVMCTRL_RWW_EEPROM_ADDR){ - return STATUS_ERR_BAD_ADDRESS; - } - is_rww_eeprom = true; -#else - return STATUS_ERR_BAD_ADDRESS; -#endif - } - - /* Check if the write address not aligned to the start of a page */ - if (destination_address & (_nvm_dev.page_size - 1)) { - return STATUS_ERR_BAD_ADDRESS; - } - - /* Check if the write length is longer than an NVM page */ - if (length > _nvm_dev.page_size) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - /* Check if the module is busy */ - if (!nvm_is_ready()) { - return STATUS_BUSY; - } - - /* Erase the page buffer before buffering new data */ - nvm_module->CTRLA.reg = NVM_COMMAND_PAGE_BUFFER_CLEAR | NVMCTRL_CTRLA_CMDEX_KEY; - - /* Check if the module is busy */ - while (!nvm_is_ready()) { - /* Force-wait for the buffer clear to complete */ - } - - /* Clear error flags */ - nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK; - - uint32_t nvm_address = destination_address / 2; - - /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy - * to ensure alignment */ - for (uint16_t i = 0; i < length; i += 2) { - uint16_t data; - - /* Copy first byte of the 16-bit chunk to the temporary buffer */ - data = buffer[i]; - - /* If we are not at the end of a write request with an odd byte count, - * store the next byte of data as well */ - if (i < (length - 1)) { - data |= (buffer[i + 1] << 8); - } - - /* Store next 16-bit chunk to the NVM memory space */ - NVM_MEMORY[nvm_address++] = data; - } - - /* If automatic page write mode is enable, then perform a manual NVM - * write when the length of data to be programmed is less than page size - */ - if ((_nvm_dev.manual_page_write == false) && (length < NVMCTRL_PAGE_SIZE)) { -#ifdef FEATURE_NVM_RWWEE - return ((is_rww_eeprom) ? - (nvm_execute_command(NVM_COMMAND_RWWEE_WRITE_PAGE,destination_address, 0)): - (nvm_execute_command(NVM_COMMAND_WRITE_PAGE,destination_address, 0))); -#else - return nvm_execute_command(NVM_COMMAND_WRITE_PAGE, - destination_address, 0); -#endif - } - - return STATUS_OK; -} - -/** - * \brief Reads a number of bytes from a page in the NVM memory region. - * - * Reads a given number of bytes from a given page address in the NVM memory - * space into a buffer. - * - * \param[in] source_address Source page address to read from - * \param[out] buffer Pointer to a buffer where the content of the read - * page will be stored - * \param[in] length Number of bytes in the page to read - * - * \return Status of the page read attempt. - * - * \retval STATUS_OK Requested NVM memory page was successfully - * read - * \retval STATUS_BUSY NVM controller was busy when the operation - * was attempted - * \retval STATUS_ERR_BAD_ADDRESS The requested address was outside the - * acceptable range of the NVM memory region or - * not aligned to the start of a page - * \retval STATUS_ERR_INVALID_ARG The supplied read length was invalid - */ -enum status_code nvm_read_buffer( - const uint32_t source_address, - uint8_t *const buffer, - uint16_t length) -{ - /* Check if the source address is valid */ - if (source_address > - ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) { -#ifdef FEATURE_NVM_RWWEE - if (source_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR) - || source_address < NVMCTRL_RWW_EEPROM_ADDR){ - return STATUS_ERR_BAD_ADDRESS; - } -#else - return STATUS_ERR_BAD_ADDRESS; -#endif - } - - /* Check if the read address is not aligned to the start of a page */ - if (source_address & (_nvm_dev.page_size - 1)) { - return STATUS_ERR_BAD_ADDRESS; - } - - /* Check if the write length is longer than an NVM page */ - if (length > _nvm_dev.page_size) { - return STATUS_ERR_INVALID_ARG; - } - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - /* Check if the module is busy */ - if (!nvm_is_ready()) { - return STATUS_BUSY; - } - - /* Clear error flags */ - nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK; - - uint32_t page_address = source_address / 2; - - /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy - * to ensure alignment */ - for (uint16_t i = 0; i < length; i += 2) { - /* Fetch next 16-bit chunk from the NVM memory space */ - uint16_t data = NVM_MEMORY[page_address++]; - - /* Copy first byte of the 16-bit chunk to the destination buffer */ - buffer[i] = (data & 0xFF); - - /* If we are not at the end of a read request with an odd byte count, - * store the next byte of data as well */ - if (i < (length - 1)) { - buffer[i + 1] = (data >> 8); - } - } - - return STATUS_OK; -} - -/** - * \brief Erases a row in the NVM memory space. - * - * Erases a given row in the NVM memory region. - * - * \param[in] row_address Address of the row to erase - * - * \return Status of the NVM row erase attempt. - * - * \retval STATUS_OK Requested NVM memory row was successfully - * erased - * \retval STATUS_BUSY NVM controller was busy when the operation - * was attempted - * \retval STATUS_ERR_BAD_ADDRESS The requested row address was outside the - * acceptable range of the NVM memory region or - * not aligned to the start of a row - * \retval STATUS_ABORTED NVM erased error - */ -enum status_code nvm_erase_row( - const uint32_t row_address) -{ -#ifdef FEATURE_NVM_RWWEE - bool is_rww_eeprom = false; -#endif - - /* Check if the row address is valid */ - if (row_address > - ((uint32_t)_nvm_dev.page_size * _nvm_dev.number_of_pages)) { -#ifdef FEATURE_NVM_RWWEE - if (row_address >= ((uint32_t)NVMCTRL_RWW_EEPROM_SIZE + NVMCTRL_RWW_EEPROM_ADDR) - || row_address < NVMCTRL_RWW_EEPROM_ADDR){ - return STATUS_ERR_BAD_ADDRESS;e4 - } - is_rww_eeprom = true; -#else - return STATUS_ERR_BAD_ADDRESS; -#endif - } - - /* Check if the address to erase is not aligned to the start of a row */ - if (row_address & ((_nvm_dev.page_size * NVMCTRL_ROW_PAGES) - 1)) { - return STATUS_ERR_BAD_ADDRESS; - } - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - /* Check if the module is busy */ - if (!nvm_is_ready()) { - return STATUS_BUSY; - } - - /* Clear error flags */ - nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK; - - /* Set address and command */ - nvm_module->ADDR.reg = (uintptr_t)&NVM_MEMORY[row_address / 4]; - -#ifdef SAMD21_64K - if (is_rww_eeprom) { - NVM_MEMORY[row_address / 2] = 0x0; - } -#endif - -#ifdef FEATURE_NVM_RWWEE - nvm_module->CTRLA.reg = ((is_rww_eeprom) ? - (NVM_COMMAND_RWWEE_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY): - (NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY)); -#else - nvm_module->CTRLA.reg = NVM_COMMAND_ERASE_ROW | NVMCTRL_CTRLA_CMDEX_KEY; -#endif - - while (!nvm_is_ready()) { - } - - /* There existed error in NVM erase operation */ - if ((enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK) != NVM_ERROR_NONE) { - return STATUS_ABORTED; - } - - return STATUS_OK; -} - -/** - * \brief Reads the parameters of the NVM controller. - * - * Retrieves the page size, number of pages, and other configuration settings - * of the NVM region. - * - * \param[out] parameters Parameter structure, which holds page size and - * number of pages in the NVM memory - */ -void nvm_get_parameters( - struct nvm_parameters *const parameters) -{ - /* Sanity check parameters */ - Assert(parameters); - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - /* Clear error flags */ - nvm_module->STATUS.reg = NVMCTRL_STATUS_MASK; - - /* Read out from the PARAM register */ - uint32_t param_reg = nvm_module->PARAM.reg; - - /* Mask out page size exponent and convert to a number of bytes */ - parameters->page_size = - 8 << ((param_reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos); - - /* Mask out number of pages count */ - parameters->nvm_number_of_pages = - (param_reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; - -#ifdef FEATURE_NVM_RWWEE - /* Mask out rwwee number of pages count */ - parameters->rww_eeprom_number_of_pages = - (param_reg & NVMCTRL_PARAM_RWWEEP_Msk) >> NVMCTRL_PARAM_RWWEEP_Pos; -#endif - - /* Read the current EEPROM fuse value from the USER row */ - uint16_t eeprom_fuse_value = - (NVM_USER_MEMORY[NVMCTRL_FUSES_EEPROM_SIZE_Pos / 16] & - NVMCTRL_FUSES_EEPROM_SIZE_Msk) >> NVMCTRL_FUSES_EEPROM_SIZE_Pos; - - /* Translate the EEPROM fuse byte value to a number of NVM pages */ - if (eeprom_fuse_value == 7) { - parameters->eeprom_number_of_pages = 0; - } - else { - parameters->eeprom_number_of_pages = - NVMCTRL_ROW_PAGES << (6 - eeprom_fuse_value); - } - - /* Read the current BOOTSZ fuse value from the USER row */ - uint16_t boot_fuse_value = - (NVM_USER_MEMORY[NVMCTRL_FUSES_BOOTPROT_Pos / 16] & - NVMCTRL_FUSES_BOOTPROT_Msk) >> NVMCTRL_FUSES_BOOTPROT_Pos; - - /* Translate the BOOTSZ fuse byte value to a number of NVM pages */ - if (boot_fuse_value == 7) { - parameters->bootloader_number_of_pages = 0; - } - else { - parameters->bootloader_number_of_pages = - NVMCTRL_ROW_PAGES << (7 - boot_fuse_value); - } -} - -/** - * \brief Checks whether the page region is locked. - * - * Extracts the region to which the given page belongs and checks whether - * that region is locked. - * - * \param[in] page_number Page number to be checked - * - * \return Page lock status. - * - * \retval true Page is locked - * \retval false Page is not locked - * - */ -bool nvm_is_page_locked(uint16_t page_number) -{ - uint16_t pages_in_region; - uint16_t region_number; - -#ifdef FEATURE_NVM_RWWEE - Assert(page_number < _nvm_dev.number_of_pages); -#endif - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - /* Get number of pages in a region */ - pages_in_region = _nvm_dev.number_of_pages / 16; - - /* Get region for given page */ - region_number = page_number / pages_in_region; - - return !(nvm_module->LOCK.reg & (1 << region_number)); -} - -///@cond INTERNAL - -/** - * \internal - * - * \brief Translate fusebit words into struct content. - * - */ -static void _nvm_translate_raw_fusebits_to_struct ( - uint32_t *raw_user_row, - struct nvm_fusebits *fusebits) -{ - - fusebits->bootloader_size = (enum nvm_bootloader_size) - ((raw_user_row[0] & NVMCTRL_FUSES_BOOTPROT_Msk) - >> NVMCTRL_FUSES_BOOTPROT_Pos); - - fusebits->eeprom_size = (enum nvm_eeprom_emulator_size) - ((raw_user_row[0] & NVMCTRL_FUSES_EEPROM_SIZE_Msk) - >> NVMCTRL_FUSES_EEPROM_SIZE_Pos); - -#if (SAML21) || (SAML22) || (SAMR30) - fusebits->bod33_level = (uint8_t) - ((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk) - >> FUSES_BOD33USERLEVEL_Pos); - - fusebits->bod33_enable = (bool) - (!((raw_user_row[0] & FUSES_BOD33_DIS_Msk) - >> FUSES_BOD33_DIS_Pos)); - - fusebits->bod33_action = (enum nvm_bod33_action) - ((raw_user_row[0] & FUSES_BOD33_ACTION_Msk) - >> FUSES_BOD33_ACTION_Pos); - - fusebits->bod33_hysteresis = (bool) - ((raw_user_row[1] & FUSES_BOD33_HYST_Msk) - >> FUSES_BOD33_HYST_Pos); - -#elif (SAMD20) || (SAMD21) || (SAMR21)|| (SAMDA1) || (SAMD09) || (SAMD10) - fusebits->bod33_level = (uint8_t) - ((raw_user_row[0] & FUSES_BOD33USERLEVEL_Msk) - >> FUSES_BOD33USERLEVEL_Pos); - - fusebits->bod33_enable = (bool) - ((raw_user_row[0] & FUSES_BOD33_EN_Msk) - >> FUSES_BOD33_EN_Pos); - - fusebits->bod33_action = (enum nvm_bod33_action) - ((raw_user_row[0] & FUSES_BOD33_ACTION_Msk) - >> FUSES_BOD33_ACTION_Pos); - fusebits->bod33_hysteresis = (bool) - ((raw_user_row[1] & FUSES_BOD33_HYST_Msk) - >> FUSES_BOD33_HYST_Pos); -#elif (SAMC20) || (SAMC21) - fusebits->bodvdd_level = (uint8_t) - ((raw_user_row[0] & FUSES_BODVDDUSERLEVEL_Msk) - >> FUSES_BODVDDUSERLEVEL_Pos); - - fusebits->bodvdd_enable = (bool) - (!((raw_user_row[0] & FUSES_BODVDD_DIS_Msk) - >> FUSES_BODVDD_DIS_Pos)); - - fusebits->bodvdd_action = (enum nvm_bod33_action) - ((raw_user_row[0] & FUSES_BODVDD_ACTION_Msk) - >> FUSES_BODVDD_ACTION_Pos); - - fusebits->bodvdd_hysteresis = (raw_user_row[1] & FUSES_BODVDD_HYST_Msk) - >> FUSES_BODVDD_HYST_Pos; -#else - fusebits->bod33_level = (uint8_t) - ((raw_user_row[0] & SYSCTRL_FUSES_BOD33USERLEVEL_Msk) - >> SYSCTRL_FUSES_BOD33USERLEVEL_Pos); - - fusebits->bod33_enable = (bool) - ((raw_user_row[0] & SYSCTRL_FUSES_BOD33_EN_Msk) - >> SYSCTRL_FUSES_BOD33_EN_Pos); - - fusebits->bod33_action = (enum nvm_bod33_action) - ((raw_user_row[0] & SYSCTRL_FUSES_BOD33_ACTION_Msk) - >> SYSCTRL_FUSES_BOD33_ACTION_Pos); - - fusebits->bod33_hysteresis = (bool) - ((raw_user_row[1] & SYSCTRL_FUSES_BOD33_HYST_Msk) - >> SYSCTRL_FUSES_BOD33_HYST_Pos); - -#endif - -#ifdef FEATURE_BOD12 - -#ifndef FUSES_BOD12USERLEVEL_Pos -#define FUSES_BOD12USERLEVEL_Pos 17 -#define FUSES_BOD12USERLEVEL_Msk (0x3Ful << FUSES_BOD12USERLEVEL_Pos) -#endif -#ifndef FUSES_BOD12_DIS_Pos -#define FUSES_BOD12_DIS_Pos 23 -#define FUSES_BOD12_DIS_Msk (0x1ul << FUSES_BOD12_DIS_Pos) -#endif -#ifndef FUSES_BOD12_ACTION_Pos -#define FUSES_BOD12_ACTION_Pos 24 -#define FUSES_BOD12_ACTION_Msk (0x3ul << FUSES_BOD12_ACTION_Pos) -#endif - - fusebits->bod12_level = (uint8_t) - ((raw_user_row[0] & FUSES_BOD12USERLEVEL_Msk) - >> FUSES_BOD12USERLEVEL_Pos); - - fusebits->bod12_enable = (bool) - (!((raw_user_row[0] & FUSES_BOD12_DIS_Msk) - >> FUSES_BOD12_DIS_Pos)); - - fusebits->bod12_action = (enum nvm_bod12_action) - ((raw_user_row[0] & FUSES_BOD12_ACTION_Msk) - >> FUSES_BOD33_ACTION_Pos); - - fusebits->bod12_hysteresis = (bool) - ((raw_user_row[1] & FUSES_BOD12_HYST_Msk) - >> FUSES_BOD12_HYST_Pos); -#endif - - fusebits->wdt_enable = (bool) - ((raw_user_row[0] & WDT_FUSES_ENABLE_Msk) >> WDT_FUSES_ENABLE_Pos); - - fusebits->wdt_always_on = (bool) - ((raw_user_row[0] & WDT_FUSES_ALWAYSON_Msk) >> WDT_FUSES_ALWAYSON_Pos); - - fusebits->wdt_timeout_period = (uint8_t) - ((raw_user_row[0] & WDT_FUSES_PER_Msk) >> WDT_FUSES_PER_Pos); - -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout) - ((raw_user_row[1] & WDT_FUSES_WINDOW_Msk) >> WDT_FUSES_WINDOW_Pos); -#else - /* WDT Windows timout lay between two 32-bit words in the user row. Because only one bit lays in word[0], - bits in word[1] must be left sifted by one to make the correct number */ - fusebits->wdt_window_timeout = (enum nvm_wdt_window_timeout) - (((raw_user_row[0] & WDT_FUSES_WINDOW_0_Msk) >> WDT_FUSES_WINDOW_0_Pos) | - ((raw_user_row[1] & WDT_FUSES_WINDOW_1_Msk) << 1)); -#endif - fusebits->wdt_early_warning_offset = (enum nvm_wdt_early_warning_offset) - ((raw_user_row[1] & WDT_FUSES_EWOFFSET_Msk) >> WDT_FUSES_EWOFFSET_Pos); - - fusebits->wdt_window_mode_enable_at_poweron = (bool) - ((raw_user_row[1] & WDT_FUSES_WEN_Msk) >> WDT_FUSES_WEN_Pos); - - fusebits->lockbits = (uint16_t) - ((raw_user_row[1] & NVMCTRL_FUSES_REGION_LOCKS_Msk) - >> NVMCTRL_FUSES_REGION_LOCKS_Pos); - -} - -///@endcond - -/** - * \brief Get fuses from user row. - * - * Read out the fuse settings from the user row. - * - * \param[in] fusebits Pointer to a 64-bit wide memory buffer of type struct nvm_fusebits - * - * \return Status of read fuses attempt. - * - * \retval STATUS_OK This function will always return STATUS_OK - */ -enum status_code nvm_get_fuses ( - struct nvm_fusebits *fusebits) -{ - enum status_code error_code = STATUS_OK; - uint32_t raw_fusebits[2]; - - /* Make sure the module is ready */ - while (!nvm_is_ready()) { - } - - /* Read the fuse settings in the user row, 64 bit */ - raw_fusebits[0] = ((uint32_t)(NVM_MEMORY[NVMCTRL_USER / 2] & 0xffff) << 16) + - (uint32_t)(NVM_MEMORY[(NVMCTRL_USER / 2) + 1] & 0xffff); - raw_fusebits[1] = ((uint32_t)(NVM_MEMORY[(NVMCTRL_USER / 2) + 2] & 0xffff) << 16) + - (uint32_t)(NVM_MEMORY[(NVMCTRL_USER / 2) + 3] & 0xffff); - - _nvm_translate_raw_fusebits_to_struct(raw_fusebits, fusebits); - - return error_code; -} - -/** - * \brief Set fuses from user row. - * - * Set fuse settings from the user row. - * - * \note When writing to the user row, the values do not get loaded by the - * other modules on the device until a device reset occurs. - * - * \param[in] fusebits Pointer to a 64-bit wide memory buffer of type struct nvm_fusebits - * - * \return Status of read fuses attempt. - * - * \retval STATUS_OK This function will always return STATUS_OK - * - * \retval STATUS_BUSY If the NVM controller was already busy - * executing a command when the new command - * was issued - * \retval STATUS_ERR_IO If the command was invalid due to memory or - * security locking - * \retval STATUS_ERR_INVALID_ARG If the given command was invalid or - * unsupported - * \retval STATUS_ERR_BAD_ADDRESS If the given address was invalid - */ - -enum status_code nvm_set_fuses(struct nvm_fusebits *fb) -{ - uint32_t fusebits[2]; - enum status_code error_code = STATUS_OK; - - if (fb == NULL) { - return STATUS_ERR_INVALID_ARG; - } - /* Read the fuse settings in the user row, 64 bit */ - fusebits[0] = *((uint32_t *)NVMCTRL_AUX0_ADDRESS); - fusebits[1] = *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1); - - /* Set user fuses bit */ - fusebits[0] &= (~NVMCTRL_FUSES_BOOTPROT_Msk); - fusebits[0] |= NVMCTRL_FUSES_BOOTPROT(fb->bootloader_size); - - fusebits[0] &= (~NVMCTRL_FUSES_EEPROM_SIZE_Msk); - fusebits[0] |= NVMCTRL_FUSES_EEPROM_SIZE(fb->eeprom_size); - -#if (SAML21) || (SAML22) || (SAMR30) - fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk); - fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level); - - fusebits[0] &= (~FUSES_BOD33_DIS_Msk); - fusebits[0] |= (!fb->bod33_enable) << FUSES_BOD33_DIS_Pos; - - fusebits[0] &= (~FUSES_BOD33_ACTION_Msk); - fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos; - - fusebits[1] &= (~FUSES_BOD33_HYST_Msk); - fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos; - -#elif (SAMD20) || (SAMD21) || (SAMR21) || (SAMDA1) || (SAMD09) || (SAMD10) - fusebits[0] &= (~FUSES_BOD33USERLEVEL_Msk); - fusebits[0] |= FUSES_BOD33USERLEVEL(fb->bod33_level); - - fusebits[0] &= (~FUSES_BOD33_EN_Msk); - fusebits[0] |= (fb->bod33_enable) << FUSES_BOD33_EN_Pos; - - fusebits[0] &= (~FUSES_BOD33_ACTION_Msk); - fusebits[0] |= fb->bod33_action << FUSES_BOD33_ACTION_Pos; - - fusebits[1] &= (~FUSES_BOD33_HYST_Msk); - fusebits[1] |= fb->bod33_hysteresis << FUSES_BOD33_HYST_Pos; - -#elif (SAMC20) || (SAMC21) - fusebits[0] &= (~FUSES_BODVDDUSERLEVEL_Msk); - fusebits[0] |= FUSES_BODVDDUSERLEVEL(fb->bodvdd_level); - - fusebits[0] &= (~FUSES_BODVDD_DIS_Msk); - fusebits[0] |= (!fb->bodvdd_enable) << FUSES_BODVDD_DIS_Pos; - - fusebits[0] &= (~FUSES_BODVDD_ACTION_Msk); - fusebits[0] |= fb->bodvdd_action << FUSES_BODVDD_ACTION_Pos; - - fusebits[1] &= (~FUSES_BODVDD_HYST_Msk); - fusebits[1] |= fb->bodvdd_hysteresis << FUSES_BODVDD_HYST_Pos; - -#else - fusebits[0] &= (~SYSCTRL_FUSES_BOD33USERLEVEL_Msk); - fusebits[0] |= SYSCTRL_FUSES_BOD33USERLEVEL(fb->bod33_level); - - fusebits[0] &= (~SYSCTRL_FUSES_BOD33_EN_Msk); - fusebits[0] |= (fb->bod33_enable) << SYSCTRL_FUSES_BOD33_EN_Pos; - - fusebits[0] &= (~SYSCTRL_FUSES_BOD33_ACTION_Msk); - fusebits[0] |= fb->bod33_action << SYSCTRL_FUSES_BOD33_ACTION_Pos; - - fusebits[1] &= (~SYSCTRL_FUSES_BOD33_HYST_Msk); - fusebits[1] |= fb->bod33_hysteresis << SYSCTRL_FUSES_BOD33_HYST_Pos; - -#endif - - fusebits[0] &= (~WDT_FUSES_ENABLE_Msk); - fusebits[0] |= fb->wdt_enable << WDT_FUSES_ENABLE_Pos; - - fusebits[0] &= (~WDT_FUSES_ALWAYSON_Msk); - fusebits[0] |= (fb->wdt_always_on) << WDT_FUSES_ALWAYSON_Pos; - - fusebits[0] &= (~WDT_FUSES_PER_Msk); - fusebits[0] |= fb->wdt_timeout_period << WDT_FUSES_PER_Pos; - -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - fusebits[1] &= (~WDT_FUSES_WINDOW_Msk); - fusebits[1] |= fb->wdt_window_timeout << WDT_FUSES_WINDOW_Pos; -#else - /* WDT Windows timout lay between two 32-bit words in the user row. the last one bit lays in word[0], - and the other bits in word[1] */ - fusebits[0] &= (~WDT_FUSES_WINDOW_0_Msk); - fusebits[0] |= (fb->wdt_window_timeout & 0x1) << WDT_FUSES_WINDOW_0_Pos; - - fusebits[1] &= (~WDT_FUSES_WINDOW_1_Msk); - fusebits[1] |= (fb->wdt_window_timeout >> 1) << WDT_FUSES_WINDOW_1_Pos; - -#endif - fusebits[1] &= (~WDT_FUSES_EWOFFSET_Msk); - fusebits[1] |= fb->wdt_early_warning_offset << WDT_FUSES_EWOFFSET_Pos; - - fusebits[1] &= (~WDT_FUSES_WEN_Msk); - fusebits[1] |= fb->wdt_window_mode_enable_at_poweron << WDT_FUSES_WEN_Pos; - - fusebits[1] &= (~NVMCTRL_FUSES_REGION_LOCKS_Msk); - fusebits[1] |= fb->lockbits << NVMCTRL_FUSES_REGION_LOCKS_Pos; - -#ifdef FEATURE_BOD12 - -#ifndef FUSES_BOD12USERLEVEL_Pos -#define FUSES_BOD12USERLEVEL_Pos 17 -#define FUSES_BOD12USERLEVEL_Msk (0x3Ful << FUSES_BOD12USERLEVEL_Pos) -#endif -#ifndef FUSES_BOD12_DIS_Pos -#define FUSES_BOD12_DIS_Pos 23 -#define FUSES_BOD12_DIS_Msk (0x1ul << FUSES_BOD12_DIS_Pos) -#endif -#ifndef FUSES_BOD12_ACTION_Pos -#define FUSES_BOD12_ACTION_Pos 24 -#define FUSES_BOD12_ACTION_Msk (0x3ul << FUSES_BOD12_ACTION_Pos) -#endif - - fusebits[0] &= (~FUSES_BOD12USERLEVEL_Msk); - fusebits[0] |= ((FUSES_BOD12USERLEVEL_Msk & ((fb->bod12_level) << - FUSES_BOD12USERLEVEL_Pos))); - - fusebits[0] &= (~FUSES_BOD12_DIS_Msk); - fusebits[0] |= (!fb->bod12_enable) << FUSES_BOD12_DIS_Pos; - - fusebits[0] &= (~FUSES_BOD12_ACTION_Msk); - fusebits[0] |= fb->bod12_action << FUSES_BOD12_ACTION_Pos; - - fusebits[1] &= (~FUSES_BOD12_HYST_Msk); - fusebits[1] |= fb->bod12_hysteresis << FUSES_BOD12_HYST_Pos; -#endif - - error_code = nvm_execute_command(NVM_COMMAND_ERASE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0); - if (error_code != STATUS_OK) { - return error_code; - } - - error_code = nvm_execute_command(NVM_COMMAND_PAGE_BUFFER_CLEAR,NVMCTRL_AUX0_ADDRESS,0); - if (error_code != STATUS_OK) { - return error_code; - } - - *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = fusebits[0]; - *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = fusebits[1]; - - error_code = nvm_execute_command(NVM_COMMAND_WRITE_AUX_ROW,NVMCTRL_AUX0_ADDRESS,0); - if (error_code != STATUS_OK) { - return error_code; - } - - return error_code; -} diff --git a/atmel-samd/asf/sam0/drivers/nvm/nvm.h b/atmel-samd/asf/sam0/drivers/nvm/nvm.h deleted file mode 100644 index 99245dd4a369a..0000000000000 --- a/atmel-samd/asf/sam0/drivers/nvm/nvm.h +++ /dev/null @@ -1,944 +0,0 @@ -/** - * \file - * - * \brief SAM Non-Volatile Memory driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef NVM_H_INCLUDED -#define NVM_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_nvm_group SAM Non-Volatile Memory (NVM) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of non-volatile memories - * within the device, for partitioning, erasing, reading, and writing of data. - * - * The following peripheral is used by this module: - * - NVM (Non-Volatile Memory) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - Atmel | SMART SAM R30 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_nvm_prerequisites - * - \ref asfdoc_sam0_nvm_module_overview - * - \ref asfdoc_sam0_nvm_special_considerations - * - \ref asfdoc_sam0_nvm_extra_info - * - \ref asfdoc_sam0_nvm_examples - * - \ref asfdoc_sam0_nvm_api_overview - * - * - * \section asfdoc_sam0_nvm_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_nvm_module_overview Module Overview - * - * The Non-Volatile Memory (NVM) module provides an interface to the device's - * Non-Volatile Memory controller, so that memory pages can be written, read, - * erased, and reconfigured in a standardized manner. - * - * \subsection asfdoc_sam0_nvm_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver feature macroSupported devices
FEATURE_NVM_RWWEESAM L21/L22, SAM D21-64K, SAM DA1, SAM C20/C21, SAM R30
FEATURE_BOD12SAM L21, SAMR30
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_nvm_module_overview_regions Memory Regions - * The NVM memory space of the SAM devices is divided into two sections: - * a Main Array section, and an Auxiliary space section. The Main Array space - * can be configured to have an (emulated) EEPROM and/or boot loader section. - * The memory layout with the EEPROM and bootloader partitions is shown in - * \ref asfdoc_sam0_nvm_module_mem_layout "the figure below". - * - * \anchor asfdoc_sam0_nvm_module_mem_layout - * \dot - * digraph memory_layout { - * size="5,5" - * node [shape=plaintext, fontname=arial] - * memory [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
End of NVM Memory Reserved EEPROM Section
Start of EEPROM Memory
End of Application Memory Application Section
Start of Application Memory
End of Bootloader Memory BOOT Section
Start of NVM Memory
- * >] - * } - * \enddot - * - * The Main Array is divided into rows and pages, where each row contains four - * pages. The size of each page may vary from 8-1024 bytes dependent of the - * device. Device specific parameters such as the page size and total number of - * pages in the NVM memory space are available via the \ref nvm_get_parameters() - * function. - * - * An NVM page number and address can be computed via the following equations: - * - * \f[ PageNum = (RowNum \times 4) + PagePosInRow \f] - * \f[ PageAddr = PageNum \times PageSize \f] - * - * \ref asfdoc_sam0_nvm_module_row_layout "The figure below" shows an example - * of the memory page and address values associated with logical row 7 of the - * NVM memory space. - * - * \anchor asfdoc_sam0_nvm_module_row_layout - * \dot - * digraph row_layout { - * size="4,4" - * node [shape=plaintext, fontname=arial] - * row [label=< - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Row 0x07 Page 0x1F Page 0x1E Page 0x1D Page 0x1C
Address 0x7C0 0x780 0x740 0x700
- * >] - * } - * \enddot - * - * \subsection asfdoc_sam0_nvm_module_overview_locking_regions Region Lock Bits - * As mentioned in \ref asfdoc_sam0_nvm_module_overview_regions, the main - * block of the NVM memory is divided into a number of individually addressable - * pages. These pages are grouped into 16 equal sized regions, where each region - * can be locked separately issuing an \ref NVM_COMMAND_LOCK_REGION command or - * by writing the LOCK bits in the User Row. Rows reserved for the EEPROM - * section are not affected by the lock bits or commands. - * - * \note By using the \ref NVM_COMMAND_LOCK_REGION or - * \ref NVM_COMMAND_UNLOCK_REGION commands the settings will remain in - * effect until the next device reset. By changing the default lock - * setting for the regions, the auxiliary space must to be written, - * however the adjusted configuration will not take effect until the next - * device reset. - * - * \note If the \ref asfdoc_sam0_nvm_special_consideration_security_bit is - * set, the auxiliary space cannot be written to. Clearing of the security - * bit can only be performed by a full chip erase. - * - * \subsection asfdoc_sam0_nvm_module_overview_sub_rw Read/Write - * Reading from the NVM memory can be performed using direct addressing into the - * NVM memory space, or by calling the \ref nvm_read_buffer() function. - * - * Writing to the NVM memory must be performed by the \ref nvm_write_buffer() - * function - additionally, a manual page program command must be issued if - * the NVM controller is configured in manual page writing mode. - * - * Before a page can be updated, the associated NVM memory row must be erased - * first via the \ref nvm_erase_row() function. Writing to a non-erased page - * will result in corrupt data being stored in the NVM memory space. - * - * \section asfdoc_sam0_nvm_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_nvm_special_consideration_pageerase Page Erasure - * The granularity of an erase is per row, while the granularity of a write is - * per page. Thus, if the user application is modifying only one page of a row, - * the remaining pages in the row must be buffered and the row erased, as an - * erase is mandatory before writing to a page. - * - * \subsection asfdoc_sam0_nvm_special_consideration_clocks Clocks - * The user must ensure that the driver is configured with a proper number of - * wait states when the CPU is running at high frequencies. - * - * \subsection asfdoc_sam0_nvm_special_consideration_security_bit Security Bit - * The User Row in the Auxiliary Space cannot be read or written when - * the Security Bit is set. The Security Bit can be set by using passing - * \ref NVM_COMMAND_SET_SECURITY_BIT to the \ref nvm_execute_command() function, - * or it will be set if one tries to access a locked region. See - * \ref asfdoc_sam0_nvm_module_overview_locking_regions. - * - * The Security Bit can only be cleared by performing a chip erase. - * - * - * \section asfdoc_sam0_nvm_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_nvm_extra. This includes: - * - \ref asfdoc_sam0_nvm_extra_acronyms - * - \ref asfdoc_sam0_nvm_extra_dependencies - * - \ref asfdoc_sam0_nvm_extra_errata - * - \ref asfdoc_sam0_nvm_extra_history - * - * - * \section asfdoc_sam0_nvm_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_nvm_exqsg. - * - * - * \section asfdoc_sam0_nvm_api_overview API Overview - * @{ - */ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Define SAMD21-64K devices */ -#if defined(SAMD21E15L) || defined(SAMD21E16L) || defined(__SAMD21E15L__) || defined(__SAMD21E16L__) \ - || defined(SAMD21E15B) || defined(SAMD21E16B) || defined(__SAMD21E15B__) || defined(__SAMD21E16B__) \ - || defined(SAMD21E15BU) || defined(SAMD21E16BU) || defined(__SAMD21E15BU__) || defined(__SAMD21E16BU__) \ - || defined(SAMD21G15L) || defined(SAMD21G16L) || defined(__SAMD21G15L__) || defined(__SAMD21G16L__) \ - || defined(SAMD21G15B) || defined(SAMD21G16B) || defined(__SAMD21G15B__) || defined(__SAMD21G16B__) \ - || defined(SAMD21J15B) || defined(SAMD21J16B) || defined(__SAMD21J15B__) || defined(__SAMD21J16B__) - -# define SAMD21_64K - -#endif - -/** - * \name Driver Feature Definition - * - * Define NVM features set according to the different device families. - * @{ -*/ -#if (SAML21) || (SAML22) || (SAMDA1) || (SAMC20) || (SAMC21) || (SAMR30) || defined(SAMD21_64K) || defined(__DOXYGEN__) -/** Read while write EEPROM emulation feature. */ -# define FEATURE_NVM_RWWEE -#endif -#if (SAML21) || (SAMR30) || defined(__DOXYGEN__) -/** Brown-out detector internal to the voltage regulator for VDDCORE. */ -#define FEATURE_BOD12 -#endif -/*@}*/ - -#if !defined(__DOXYGEN__) -/** - * \brief Mask for the error flags in the status register. - */ -# define NVM_ERRORS_MASK (NVMCTRL_STATUS_PROGE | \ - NVMCTRL_STATUS_LOCKE | \ - NVMCTRL_STATUS_NVME) -#endif - -/** - * \brief NVM error flags. - * - * Possible NVM controller error codes, which can be returned by the NVM - * controller after a command is issued. - */ -enum nvm_error { - /** No errors */ - NVM_ERROR_NONE = 0, - /** Lock error, a locked region was attempted accessed */ - NVM_ERROR_LOCK = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_LOCKE, - /** Program error, invalid command was executed */ - NVM_ERROR_PROG = NVMCTRL_STATUS_NVME | NVMCTRL_STATUS_PROGE, -}; - -/** - * \brief NVM controller commands. - */ -enum nvm_command { - /** Erases the addressed memory row */ - NVM_COMMAND_ERASE_ROW = NVMCTRL_CTRLA_CMD_ER, - - /** Write the contents of the page buffer to the addressed memory page */ - NVM_COMMAND_WRITE_PAGE = NVMCTRL_CTRLA_CMD_WP, - - /** Erases the addressed auxiliary memory row. - * - * \note This command can only be given when the security bit is not set. - */ - NVM_COMMAND_ERASE_AUX_ROW = NVMCTRL_CTRLA_CMD_EAR, - - /** Write the contents of the page buffer to the addressed auxiliary memory - * row. - * - * \note This command can only be given when the security bit is not set. - */ - NVM_COMMAND_WRITE_AUX_ROW = NVMCTRL_CTRLA_CMD_WAP, - - /** Locks the addressed memory region, preventing further modifications - * until the region is unlocked or the device is erased - */ - NVM_COMMAND_LOCK_REGION = NVMCTRL_CTRLA_CMD_LR, - - /** Unlocks the addressed memory region, allowing the region contents to be - * modified - */ - NVM_COMMAND_UNLOCK_REGION = NVMCTRL_CTRLA_CMD_UR, - - /** Clears the page buffer of the NVM controller, resetting the contents to - * all zero values - */ - NVM_COMMAND_PAGE_BUFFER_CLEAR = NVMCTRL_CTRLA_CMD_PBC, - - /** Sets the device security bit, disallowing the changing of lock bits and - * auxiliary row data until a chip erase has been performed - */ - NVM_COMMAND_SET_SECURITY_BIT = NVMCTRL_CTRLA_CMD_SSB, - - /** Enter power reduction mode in the NVM controller to reduce the power - * consumption of the system - */ - NVM_COMMAND_ENTER_LOW_POWER_MODE = NVMCTRL_CTRLA_CMD_SPRM, - - /** Exit power reduction mode in the NVM controller to allow other NVM - * commands to be issued - */ - NVM_COMMAND_EXIT_LOW_POWER_MODE = NVMCTRL_CTRLA_CMD_CPRM, -#ifdef FEATURE_NVM_RWWEE - /** Read while write (RWW) EEPROM area erase row */ - NVM_COMMAND_RWWEE_ERASE_ROW = NVMCTRL_CTRLA_CMD_RWWEEER, - /** RWW EEPROM write page */ - NVM_COMMAND_RWWEE_WRITE_PAGE = NVMCTRL_CTRLA_CMD_RWWEEWP, -#endif -}; - -/** - * \brief NVM controller power reduction mode configurations. - * - * Power reduction modes of the NVM controller, to conserve power while the - * device is in sleep. - */ -enum nvm_sleep_power_mode { - /** NVM controller exits low-power mode on first access after sleep */ - NVM_SLEEP_POWER_MODE_WAKEONACCESS = NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val, - /** NVM controller exits low-power mode when the device exits sleep mode */ - NVM_SLEEP_POWER_MODE_WAKEUPINSTANT = NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val, - /** Power reduction mode in the NVM controller disabled */ - NVM_SLEEP_POWER_MODE_ALWAYS_AWAKE = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val, -}; - -/** - * \brief NVM controller cache readmode configuration. - * - * Control how the NVM cache prefetch data from flash. - * - */ -enum nvm_cache_readmode { - /** The NVM Controller (cache system) does not insert wait states on - * a cache miss. Gives the best system performance. - */ - NVM_CACHE_READMODE_NO_MISS_PENALTY, - /** Reduces power consumption of the cache system, but inserts a - * wait state each time there is a cache miss - */ - NVM_CACHE_READMODE_LOW_POWER, - /** The cache system ensures that a cache hit or miss takes the same - * amount of time, determined by the number of programmed flash - * wait states - */ - NVM_CACHE_READMODE_DETERMINISTIC, -}; - -/** - * \brief NVM controller configuration structure. - * - * Configuration structure for the NVM controller within the device. - */ -struct nvm_config { - /** Power reduction mode during device sleep */ - enum nvm_sleep_power_mode sleep_power_mode; - /** Manual write mode; if enabled, pages loaded into the NVM buffer will - * not be written until a separate write command is issued. If disabled, - * writing to the last byte in the NVM page buffer will trigger an automatic - * write. - * - * \note If a partial page is to be written, a manual write command must be - * executed in either mode. - */ - bool manual_page_write; - /** Number of wait states to insert when reading from flash, to prevent - * invalid data from being read at high clock frequencies - */ - uint8_t wait_states; - - /** - * Setting this to true will disable the pre-fetch cache in front of the - * NVM controller - */ - bool disable_cache; -#if (SAMC20) || (SAMC21) - /** - * Setting this to true will disable the pre-fetch RWW cache in front of the - * NVM controller. - * If RWW cache is enabled, NVM cache will also be enabled. - */ - bool disable_rww_cache; -#endif - /** - * Select the mode for how the cache will pre-fetch data from the flash - */ - enum nvm_cache_readmode cache_readmode; -}; - -/** - * \brief NVM memory parameter structure. - * - * Structure containing the memory layout parameters of the NVM module. - */ -struct nvm_parameters { - /** Number of bytes per page */ - uint8_t page_size; - /** Number of pages in the main array */ - uint16_t nvm_number_of_pages; - /** Size of the emulated EEPROM memory section configured in the NVM - * auxiliary memory space */ - uint32_t eeprom_number_of_pages; - /** Size of the Bootloader memory section configured in the NVM auxiliary - * memory space */ - uint32_t bootloader_number_of_pages; -#ifdef FEATURE_NVM_RWWEE - /** Number of pages in read while write EEPROM (RWWEE) emulation area */ - uint16_t rww_eeprom_number_of_pages; -#endif -}; - -/** - * \brief Bootloader size. - * - * Available bootloader protection sizes in kilobytes. - * - */ -enum nvm_bootloader_size { - /** Boot Loader Size is 32768 bytes */ - NVM_BOOTLOADER_SIZE_128, - /** Boot Loader Size is 16384 bytes */ - NVM_BOOTLOADER_SIZE_64, - /** Boot Loader Size is 8192 bytes */ - NVM_BOOTLOADER_SIZE_32, - /** Boot Loader Size is 4096 bytes */ - NVM_BOOTLOADER_SIZE_16, - /** Boot Loader Size is 2048 bytes */ - NVM_BOOTLOADER_SIZE_8, - /** Boot Loader Size is 1024 bytes */ - NVM_BOOTLOADER_SIZE_4, - /** Boot Loader Size is 512 bytes */ - NVM_BOOTLOADER_SIZE_2, - /** Boot Loader Size is 0 bytes */ - NVM_BOOTLOADER_SIZE_0, -}; - -/** - * \brief EEPROM emulator size. - * - * Available space in flash dedicated for EEPROM emulator in bytes. - * - */ -enum nvm_eeprom_emulator_size { - /** EEPROM Size for EEPROM emulation is 16384 bytes */ - NVM_EEPROM_EMULATOR_SIZE_16384, - /** EEPROM Size for EEPROM emulation is 8192 bytes */ - NVM_EEPROM_EMULATOR_SIZE_8192, - /** EEPROM Size for EEPROM emulation is 4096 bytes */ - NVM_EEPROM_EMULATOR_SIZE_4096, - /** EEPROM Size for EEPROM emulation is 2048 bytes */ - NVM_EEPROM_EMULATOR_SIZE_2048, - /** EEPROM Size for EEPROM emulation is 1024 bytes */ - NVM_EEPROM_EMULATOR_SIZE_1024, - /** EEPROM Size for EEPROM emulation is 512 bytes */ - NVM_EEPROM_EMULATOR_SIZE_512, - /** EEPROM Size for EEPROM emulation is 256 bytes */ - NVM_EEPROM_EMULATOR_SIZE_256, - /** EEPROM Size for EEPROM emulation is 0 bytes */ - NVM_EEPROM_EMULATOR_SIZE_0, -}; - -/** - * \brief BOD33 Action. - * - * What action should be triggered when BOD33 is detected. - * - */ -enum nvm_bod33_action { - /** No action */ - NVM_BOD33_ACTION_NONE, - /** The BOD33 generates a reset */ - NVM_BOD33_ACTION_RESET, - /** The BOD33 generates an interrupt */ - NVM_BOD33_ACTION_INTERRUPT, -}; - -#ifdef FEATURE_BOD12 -/** - * \brief BOD12 Action. - * - * What action should be triggered when BOD12 is detected. - * - */ -enum nvm_bod12_action { - /** No action */ - NVM_BOD12_ACTION_NONE, - /** The BOD12 generates a reset */ - NVM_BOD12_ACTION_RESET, - /** The BOD12 generates an interrupt */ - NVM_BOD12_ACTION_INTERRUPT, -}; -#endif - -/** - * \brief WDT Window time-out period. - * - * Window mode time-out period in clock cycles. - * - */ -enum nvm_wdt_window_timeout { - /** 8 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_8, - /** 16 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_16, - /** 32 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_32, - /** 64 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_64, - /** 128 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_128, - /** 256 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_256, - /** 512 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_512, - /** 1024 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_1024, - /** 2048 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_2048, - /** 4096 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_4096, - /** 8192 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_8192, - /** 16384 clock cycles */ - NVM_WDT_WINDOW_TIMEOUT_PERIOD_16384, -}; - -/** - * \brief WDT Early warning offset. - * - * This setting determine how many GCLK_WDT cycles before a watchdog time-out period - * an early warning interrupt should be triggered. - * - */ -enum nvm_wdt_early_warning_offset { - /** 8 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_8, - /** 16 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_16, - /** 32 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_32, - /** 64 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_64, - /** 128 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_128, - /** 256 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_256, - /** 512 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_512, - /** 1024 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_1024, - /** 2048 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_2048, - /** 4096 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_4096, - /** 8192 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_8192, - /** 16384 clock cycles */ - NVM_WDT_EARLY_WARNING_OFFSET_16384, -}; - -/** - * \brief NVM user row fuse setting structure. - * - * This structure contain the layout of the first 64 bits of the user row - * which contain the fuse settings. - */ -struct nvm_fusebits { - /** Bootloader size */ - enum nvm_bootloader_size bootloader_size; - /** EEPROM emulation area size */ - enum nvm_eeprom_emulator_size eeprom_size; -#if (SAMC20) || (SAMC21) - /** BODVDD Threshold level at power on */ - uint8_t bodvdd_level; - /** BODVDD Enable at power on */ - bool bodvdd_enable; - /** BODVDD Action at power on */ - enum nvm_bod33_action bodvdd_action; - /* BODVDD Hysteresis at power on */ - bool bodvdd_hysteresis; -#else - /** BOD33 Threshold level at power on */ - uint8_t bod33_level; - /** BOD33 Enable at power on */ - bool bod33_enable; - /** BOD33 Action at power on */ - enum nvm_bod33_action bod33_action; - /* BOD33 Hysteresis at power on */ - bool bod33_hysteresis; -#endif - /** WDT Enable at power on */ - bool wdt_enable; - /** WDT Always-on at power on */ - bool wdt_always_on; - /** WDT Period at power on */ - uint8_t wdt_timeout_period; - /** WDT Window mode time-out at power on */ - enum nvm_wdt_window_timeout wdt_window_timeout; - /** WDT Early warning interrupt time offset at power on */ - enum nvm_wdt_early_warning_offset wdt_early_warning_offset; - /** WDT Window mode enabled at power on */ - bool wdt_window_mode_enable_at_poweron; - /** NVM Lock bits */ - uint16_t lockbits; -#ifdef FEATURE_BOD12 - /** BOD12 Threshold level at power on */ - uint8_t bod12_level; - /** BOD12 Enable at power on */ - bool bod12_enable; - /** BOD12 Action at power on */ - enum nvm_bod12_action bod12_action; - /* BOD12 Hysteresis at power on */ - bool bod12_hysteresis; -#endif -}; - -/** - * \name Configuration and Initialization - * @{ - */ - -/** - * \brief Initializes an NVM controller configuration structure to defaults. - * - * Initializes a given NVM controller configuration structure to a set of - * known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Power reduction mode enabled after sleep mode until first NVM access - * \li Automatic page write mode disabled - * \li Number of FLASH wait states left unchanged - * - * \param[out] config Configuration structure to initialize to default values - * - */ -static inline void nvm_get_config_defaults( - struct nvm_config *const config) -{ - /* Sanity check the parameters */ - Assert(config); - - /* Write the default configuration for the NVM configuration */ - config->sleep_power_mode = NVM_SLEEP_POWER_MODE_WAKEONACCESS; - config->manual_page_write = true; - config->wait_states = NVMCTRL->CTRLB.bit.RWS; - config->disable_cache = false; -#if (SAMC20) || (SAMC21) - config->disable_rww_cache = false; -#endif - config->cache_readmode = NVM_CACHE_READMODE_NO_MISS_PENALTY; -} - -enum status_code nvm_set_config( - const struct nvm_config *const config); - -/** - * \brief Checks if the NVM controller is ready to accept a new command. - * - * Checks the NVM controller to determine if it is currently busy execution an - * operation, or ready for a new command. - * - * \return Busy state of the NVM controller. - * - * \retval true If the hardware module is ready for a new command - * \retval false If the hardware module is busy executing a command - * - */ -static inline bool nvm_is_ready(void) -{ - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - return nvm_module->INTFLAG.reg & NVMCTRL_INTFLAG_READY; -} - -/** @} */ - -/** - * \name NVM Access Management - * @{ - */ - -void nvm_get_parameters( - struct nvm_parameters *const parameters); - -enum status_code nvm_write_buffer( - const uint32_t destination_address, - const uint8_t *buffer, - uint16_t length); - -enum status_code nvm_read_buffer( - const uint32_t source_address, - uint8_t *const buffer, - uint16_t length); - -enum status_code nvm_update_buffer( - const uint32_t destination_address, - uint8_t *const buffer, - uint16_t offset, - uint16_t length); - -enum status_code nvm_erase_row( - const uint32_t row_address); - -enum status_code nvm_execute_command( - const enum nvm_command command, - const uint32_t address, - const uint32_t parameter); - -enum status_code nvm_get_fuses(struct nvm_fusebits *fusebits); -enum status_code nvm_set_fuses(struct nvm_fusebits *fb); - -bool nvm_is_page_locked(uint16_t page_number); - -/** - * \brief Retrieves the error code of the last issued NVM operation. - * - * Retrieves the error code from the last executed NVM operation. Once - * retrieved, any error state flags in the controller are cleared. - * - * \note The \ref nvm_is_ready() function is an exception. Thus, errors - * retrieved after running this function should be valid for the function - * executed before \ref nvm_is_ready(). - * - * \return Error caused by the last NVM operation. - * - * \retval NVM_ERROR_NONE No error occurred in the last NVM operation - * - * \retval NVM_ERROR_LOCK The last NVM operation attempted to access a locked - * region - * \retval NVM_ERROR_PROG An invalid NVM command was issued - */ -static inline enum nvm_error nvm_get_error(void) -{ - enum nvm_error ret_val; - - /* Get a pointer to the module hardware instance */ - Nvmctrl *const nvm_module = NVMCTRL; - - /* Mask out non-error bits */ - ret_val = (enum nvm_error)(nvm_module->STATUS.reg & NVM_ERRORS_MASK); - - /* Clear error flags */ - nvm_module->STATUS.reg = NVM_ERRORS_MASK; - - /* Return error code from the NVM controller */ - return ret_val; -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -/** - * \page asfdoc_sam0_nvm_extra Extra Information for NVM Driver - * - * \section asfdoc_sam0_nvm_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
NVMNon-Volatile Memory
EEPROMElectrically Erasable Programmable Read-Only Memory
- * - * - * \section asfdoc_sam0_nvm_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_nvm_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_nvm_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Removed BOD12 reference, removed nvm_set_fuses() API
Added functions to read/write fuse settings
Added support for NVM cache configuration
Updated initialization function to also enable the digital interface - * clock to the module if it is disabled
Initial Release
- */ - -/** - * \page asfdoc_sam0_nvm_exqsg Examples for NVM Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_nvm_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_nvm_basic_use_case - * - * \page asfdoc_sam0_nvm_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42114E12/2015Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1
42114D12/2014Added support for SAM R21 and SAM D10/D11
42114C01/2014Added support for SAM D21
42114B06/2013Corrected documentation typos
42114A06/2013Initial document release
- */ - -#endif /* NVM_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/port/port.c b/atmel-samd/asf/sam0/drivers/port/port.c deleted file mode 100644 index 64787c6e54ac2..0000000000000 --- a/atmel-samd/asf/sam0/drivers/port/port.c +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief SAM GPIO Port Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -/** - * \brief Writes a Port pin configuration to the hardware module. - * - * Writes out a given configuration of a Port pin configuration to the hardware - * module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] config Configuration settings for the pin - */ -void port_pin_set_config( - const uint8_t gpio_pin, - const struct port_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; - pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; - pinmux_config.powersave = config->powersave; - - system_pinmux_pin_set_config(gpio_pin, &pinmux_config); -} - -/** - * \brief Writes a Port group configuration group to the hardware module. - * - * Writes out a given configuration of a Port group configuration to the - * hardware module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[out] port Base of the PORT module to write to - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] config Configuration settings for the pin group - */ -void port_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct port_config *const config) -{ - /* Sanity check arguments */ - Assert(port); - Assert(config); - - struct system_pinmux_config pinmux_config; - system_pinmux_get_config_defaults(&pinmux_config); - - pinmux_config.mux_position = SYSTEM_PINMUX_GPIO; - pinmux_config.direction = (enum system_pinmux_pin_dir)config->direction; - pinmux_config.input_pull = (enum system_pinmux_pin_pull)config->input_pull; - pinmux_config.powersave = config->powersave; - - system_pinmux_group_set_config(port, mask, &pinmux_config); -} diff --git a/atmel-samd/asf/sam0/drivers/port/port.h b/atmel-samd/asf/sam0/drivers/port/port.h deleted file mode 100644 index d52714f6c2f54..0000000000000 --- a/atmel-samd/asf/sam0/drivers/port/port.h +++ /dev/null @@ -1,792 +0,0 @@ -/** - * \file - * - * \brief SAM GPIO Port Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef PORT_H_INCLUDED -#define PORT_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_port_group SAM Port (PORT) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the device's General - * Purpose Input/Output (GPIO) pin functionality, for manual pin state reading - * and writing. - * - * The following peripheral is used by this module: - * - PORT (GPIO Management) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - Atmel | SMART SAM R30 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_port_prerequisites - * - \ref asfdoc_sam0_port_module_overview - * - \ref asfdoc_sam0_port_special_considerations - * - \ref asfdoc_sam0_port_extra_info - * - \ref asfdoc_sam0_port_examples - * - \ref asfdoc_sam0_port_api_overview - * - * - * \section asfdoc_sam0_port_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_port_module_overview Module Overview - * - * The device GPIO (PORT) module provides an interface between the user - * application logic and external hardware peripherals, when general pin state - * manipulation is required. This driver provides an easy-to-use interface to - * the physical pin input samplers and output drivers, so that pins can be read - * from or written to for general purpose external hardware control. - * - * \subsection asfdoc_sam0_port_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_PORT_INPUT_EVENTSAM L21/L22/C20/C21/R30
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_port_module_overview_pin_numbering Physical and Logical GPIO Pins - * SAM devices use two naming conventions for the I/O pins in the device; one - * physical and one logical. Each physical pin on a device package is assigned - * both a physical port and pin identifier (e.g. "PORTA.0") as well as a - * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the - * former is used to map physical pins to their physical internal device module - * counterparts, for simplicity the design of this driver uses the logical GPIO - * numbers instead. - * - * \subsection asfdoc_sam0_port_module_overview_physical Physical Connection - * - * \ref asfdoc_sam0_port_module_int_connections "The diagram below" shows how - * this module is interconnected within the device. - * - * \anchor asfdoc_sam0_port_module_int_connections - * \dot - * digraph overview { - * node [label="Port Pad" shape=square] pad; - * - * subgraph driver { - * node [label="Peripheral MUX" shape=trapezium] pinmux; - * node [label="GPIO Module" shape=ellipse] gpio; - * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals; - * } - * - * pinmux -> gpio; - * pad -> pinmux; - * pinmux -> peripherals; - * } - * \enddot - * - * - * \section asfdoc_sam0_port_special_considerations Special Considerations - * - * The SAM port pin input sampler can be disabled when the pin is configured - * in pure output mode to save power; reading the pin state of a pin configured - * in output-only mode will read the logical output state that was last set. - * - * \section asfdoc_sam0_port_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_port_extra. This includes: - * - \ref asfdoc_sam0_port_extra_acronyms - * - \ref asfdoc_sam0_port_extra_dependencies - * - \ref asfdoc_sam0_port_extra_errata - * - \ref asfdoc_sam0_port_extra_history - * - * - * \section asfdoc_sam0_port_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_port_exqsg. - * - * - * \section asfdoc_sam0_port_api_overview API Overview - * @{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Driver Feature Definition - * Define port features set according to different device family. - * @{ -*/ -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__) -/** Event input control feature support for PORT group. */ -# define FEATURE_PORT_INPUT_EVENT -#endif -/*@}*/ - -/** \name PORT Alias Macros - * @{ - */ - -/** Convenience definition for GPIO module group A on the device (if - * available). */ -#if (PORT_GROUPS > 0) || defined(__DOXYGEN__) -# define PORTA PORT->Group[0] -#endif - -#if (PORT_GROUPS > 1) || defined(__DOXYGEN__) -/** Convenience definition for GPIO module group B on the device (if - * available). */ -# define PORTB PORT->Group[1] -#endif - -#if (PORT_GROUPS > 2) || defined(__DOXYGEN__) -/** Convenience definition for GPIO module group C on the device (if - * available). */ -# define PORTC PORT->Group[2] -#endif - -#if (PORT_GROUPS > 3) || defined(__DOXYGEN__) -/** Convenience definition for GPIO module group D on the device (if - * available). */ -# define PORTD PORT->Group[3] -#endif - -/** @} */ - -/** - * \brief Port pin direction configuration enum. - * - * Enum for the possible pin direction settings of the port pin configuration - * structure, to indicate the direction the pin should use. - */ -enum port_pin_dir { - /** The pin's input buffer should be enabled, so that the pin state can - * be read */ - PORT_PIN_DIR_INPUT = SYSTEM_PINMUX_PIN_DIR_INPUT, - /** The pin's output buffer should be enabled, so that the pin state can - * be set */ - PORT_PIN_DIR_OUTPUT = SYSTEM_PINMUX_PIN_DIR_OUTPUT, - /** The pin's output and input buffers should be enabled, so that the pin - * state can be set and read back */ - PORT_PIN_DIR_OUTPUT_WTH_READBACK = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, -}; - -/** - * \brief Port pin input pull configuration enum. - * - * Enum for the possible pin pull settings of the port pin configuration - * structure, to indicate the type of logic level pull the pin should use. - */ -enum port_pin_pull { - /** No logical pull should be applied to the pin */ - PORT_PIN_PULL_NONE = SYSTEM_PINMUX_PIN_PULL_NONE, - /** Pin should be pulled up when idle */ - PORT_PIN_PULL_UP = SYSTEM_PINMUX_PIN_PULL_UP, - /** Pin should be pulled down when idle */ - PORT_PIN_PULL_DOWN = SYSTEM_PINMUX_PIN_PULL_DOWN, -}; - -#ifdef FEATURE_PORT_INPUT_EVENT -/** - * \brief Port input event action. - * - * List of port input events action on pin. - */ -enum port_input_event_action { - /** Event out to pin */ - PORT_INPUT_EVENT_ACTION_OUT = 0, - /** Set output register of pin on event */ - PORT_INPUT_EVENT_ACTION_SET, - /** Clear output register pin on event */ - PORT_INPUT_EVENT_ACTION_CLR, - /** Toggle output register pin on event */ - PORT_INPUT_EVENT_ACTION_TGL, -}; - -/** - * \brief Port input event. - * - * List of port input events. - */ -enum port_input_event{ - /** Port input event 0 */ - PORT_INPUT_EVENT_0 = 0, - /** Port input event 1 */ - PORT_INPUT_EVENT_1 = 1, - /** Port input event 2 */ - PORT_INPUT_EVENT_2 = 2, - /** Port input event 3 */ - PORT_INPUT_EVENT_3 = 3, -}; - -/** - * \brief Port input event configuration structure. - * - * Configuration structure for a port input event. - */ -struct port_input_event_config{ - /** Port input event action */ - enum port_input_event_action action; - /** GPIO pin */ - uint8_t gpio_pin; -}; -#endif - -/** - * \brief Port pin configuration structure. - * - * Configuration structure for a port pin instance. This structure should be - * initialized by the \ref port_get_config_defaults() function before being - * modified by the user application. - */ -struct port_config { - /** Port buffer input/output direction */ - enum port_pin_dir direction; - - /** Port pull-up/pull-down for input pins */ - enum port_pin_pull input_pull; - - /** Enable lowest possible powerstate on the pin - * - * \note All other configurations will be ignored, the pin will be disabled. - */ - bool powersave; -}; - -/** \name State Reading/Writing (Physical Group Orientated) - * @{ - */ - -/** - * \brief Retrieves the PORT module group instance from a given GPIO pin number. - * - * Retrieves the PORT module group instance associated with a given logical - * GPIO pin number. - * - * \param[in] gpio_pin Index of the GPIO pin to convert - * - * \return Base address of the associated PORT module. - */ -static inline PortGroup* port_get_group_from_gpio_pin( - const uint8_t gpio_pin) -{ - return system_pinmux_get_group_from_gpio_pin(gpio_pin); -} - -/** - * \brief Retrieves the state of a group of port pins that are configured as inputs. - * - * Reads the current logic level of a port module's pins and returns the - * current levels as a bitmask. - * - * \param[in] port Base of the PORT module to read from - * \param[in] mask Mask of the port pin(s) to read - * - * \return Status of the port pin(s) input buffers. - */ -static inline uint32_t port_group_get_input_level( - const PortGroup *const port, - const uint32_t mask) -{ - /* Sanity check arguments */ - Assert(port); - - return (port->IN.reg & mask); -} - -/** - * \brief Retrieves the state of a group of port pins that are configured as outputs. - * - * Reads the current logical output level of a port module's pins and returns - * the current levels as a bitmask. - * - * \param[in] port Base of the PORT module to read from - * \param[in] mask Mask of the port pin(s) to read - * - * \return Status of the port pin(s) output buffers. - */ -static inline uint32_t port_group_get_output_level( - const PortGroup *const port, - const uint32_t mask) -{ - /* Sanity check arguments */ - Assert(port); - - return (port->OUT.reg & mask); -} - -/** - * \brief Sets the state of a group of port pins that are configured as outputs. - * - * Sets the current output level of a port module's pins to a given logic - * level. - * - * \param[out] port Base of the PORT module to write to - * \param[in] mask Mask of the port pin(s) to change - * \param[in] level_mask Mask of the port level(s) to set - */ -static inline void port_group_set_output_level( - PortGroup *const port, - const uint32_t mask, - const uint32_t level_mask) -{ - /* Sanity check arguments */ - Assert(port); - - port->OUTSET.reg = (mask & level_mask); - port->OUTCLR.reg = (mask & ~level_mask); -} - -/** - * \brief Toggles the state of a group of port pins that are configured as an outputs. - * - * Toggles the current output levels of a port module's pins. - * - * \param[out] port Base of the PORT module to write to - * \param[in] mask Mask of the port pin(s) to toggle - */ -static inline void port_group_toggle_output_level( - PortGroup *const port, - const uint32_t mask) -{ - /* Sanity check arguments */ - Assert(port); - - port->OUTTGL.reg = mask; -} - -/** @} */ - -/** \name Configuration and Initialization - * @{ - */ - -/** - * \brief Initializes a Port pin/group configuration structure to defaults. - * - * Initializes a given Port pin/group configuration structure to a set of - * known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Input mode with internal pull-up enabled - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void port_get_config_defaults( - struct port_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->direction = PORT_PIN_DIR_INPUT; - config->input_pull = PORT_PIN_PULL_UP; - config->powersave = false; -} - -void port_pin_set_config( - const uint8_t gpio_pin, - const struct port_config *const config); - -void port_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct port_config *const config); - -/** @} */ - -/** \name State Reading/Writing (Logical Pin Orientated) - * @{ - */ - -/** - * \brief Retrieves the state of a port pin that is configured as an input. - * - * Reads the current logic level of a port pin and returns the current - * level as a Boolean value. - * - * \param[in] gpio_pin Index of the GPIO pin to read - * - * \return Status of the port pin's input buffer. - */ -static inline bool port_pin_get_input_level( - const uint8_t gpio_pin) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - return (port_base->IN.reg & pin_mask); -} - -/** - * \brief Retrieves the state of a port pin that is configured as an output. - * - * Reads the current logical output level of a port pin and returns the current - * level as a Boolean value. - * - * \param[in] gpio_pin Index of the GPIO pin to read - * - * \return Status of the port pin's output buffer. - */ -static inline bool port_pin_get_output_level( - const uint8_t gpio_pin) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - return (port_base->OUT.reg & pin_mask); -} - -/** - * \brief Sets the state of a port pin that is configured as an output. - * - * Sets the current output level of a port pin to a given logic level. - * - * \param[in] gpio_pin Index of the GPIO pin to write to - * \param[in] level Logical level to set the given pin to - */ -static inline void port_pin_set_output_level( - const uint8_t gpio_pin, - const bool level) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - /* Set the pin to high or low atomically based on the requested level */ - if (level) { - port_base->OUTSET.reg = pin_mask; - } else { - port_base->OUTCLR.reg = pin_mask; - } -} - -/** - * \brief Toggles the state of a port pin that is configured as an output. - * - * Toggles the current output level of a port pin. - * - * \param[in] gpio_pin Index of the GPIO pin to toggle - */ -static inline void port_pin_toggle_output_level( - const uint8_t gpio_pin) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - /* Toggle pin output level */ - port_base->OUTTGL.reg = pin_mask; -} - -/** @} */ - -#ifdef FEATURE_PORT_INPUT_EVENT - -/** \name Port Input Event - * @{ - */ - -/** - * \brief Enable the port event input. - * - * Enable the port event input with the given pin and event. - * - * \param[in] gpio_pin Index of the GPIO pin - * \param[in] n Port input event - * - * \retval STATUS_ERR_INVALID_ARG Invalid parameter - * \retval STATUS_OK Successfully - */ -static inline enum status_code port_enable_input_event( - const uint8_t gpio_pin, - const enum port_input_event n) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** - * \brief Disable the port event input. - * - * Disable the port event input with the given pin and event. - * - * \param[in] gpio_pin Index of the GPIO pin - * \param[in] gpio_pin Port input event - * - * \retval STATUS_ERR_INVALID_ARG Invalid parameter - * \retval STATUS_OK Successfully - */ -static inline enum status_code port_disable_input_event( - const uint8_t gpio_pin, - const enum port_input_event n) -{ - PortGroup *const port_base = port_get_group_from_gpio_pin(gpio_pin); - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** - * \brief Retrieve the default configuration for port input event. - * - * Fills a configuration structure with the default configuration for port input event: - * - Event output to pin - * - Event action to be executed on PIN 0 - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void port_input_event_get_config_defaults( - struct port_input_event_config *const config) -{ - Assert(config); - config->action = PORT_INPUT_EVENT_ACTION_OUT; - config->gpio_pin = 0; -} - -/** - * \brief Configure port input event. - * - * Configures port input event with the given configuration settings. - * - * \param[in] config Port input even configuration structure containing the new config - * - * \retval STATUS_ERR_INVALID_ARG Invalid parameter - * \retval STATUS_OK Successfully - */ - -static inline enum status_code port_input_event_set_config( - const enum port_input_event n, - struct port_input_event_config *const config) -{ - Assert(config); - PortGroup *const port_base = port_get_group_from_gpio_pin(config->gpio_pin); - uint8_t pin_index = config->gpio_pin % 32; - struct port_config pin_conf; - - port_get_config_defaults(&pin_conf); - /* Configure the GPIO pin as outputs*/ - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - port_pin_set_config(config->gpio_pin, &pin_conf); - - switch (n) { - case PORT_INPUT_EVENT_0: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT0(config->action) - | PORT_EVCTRL_PID0(pin_index); - break; - case PORT_INPUT_EVENT_1: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT1(config->action) - | PORT_EVCTRL_PID1(pin_index); - break; - case PORT_INPUT_EVENT_2: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT2(config->action) - | PORT_EVCTRL_PID2(pin_index); - break; - case PORT_INPUT_EVENT_3: - port_base->EVCTRL.reg |= PORT_EVCTRL_EVACT3(config->action) - | PORT_EVCTRL_PID3(pin_index); - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - return STATUS_OK; -} - -/** @} */ - -#endif - -#ifdef __cplusplus -} -#endif - -/** @} */ - -/** - * \page asfdoc_sam0_port_extra Extra Information for PORT Driver - * - * \section asfdoc_sam0_port_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
GPIOGeneral Purpose Input/Output
MUXMultiplexer
- * - * - * \section asfdoc_sam0_port_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_port_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_port_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added input event feature
Initial release
- */ - -/** - * \page asfdoc_sam0_port_exqsg Examples for PORT Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_port_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_port_basic_use_case - * - * \page asfdoc_sam0_port_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42113E12/2015Added input event feature. - * Added support for SAM L21/L22, SAM C21, SAM D09, SAMR30 and SAM DA1.
42113D12/2014Added support for SAM R21 and SAM D10/D11
42113C01/2014Added support for SAM D21
42113B06/2013Corrected documentation typos
42113A06/2013Initial document release
- */ - -#endif diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/bus_state_diagram.svg b/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/bus_state_diagram.svg deleted file mode 100644 index 4bd4175a0822a..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/bus_state_diagram.svg +++ /dev/null @@ -1,533 +0,0 @@ - - - -image/svg+xmlP + Timeout - -RESET - -Write ADDR(S) - -IDLE - -(0b01) - -S - -BUSY - -(0b11) - -P + Timeout - -UNKNOWN - -(0b00) - -OWNER - -(0b10) - -ArbitrationLost - -Command PWrite ADDR (Sr) - -Sr - - diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/bus_topology.svg b/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/bus_topology.svg deleted file mode 100644 index 80df58f30a5e2..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/bus_topology.svg +++ /dev/null @@ -1,351 +0,0 @@ - - - - - - - - - - Page-1 - - - Sheet.1 - - Box.448 - I2C DEVICE #1 - - - - I2C DEVICE #1 - - Box.450 - - - - Box.451 - - - - Bottom to top 1 - - - - - - - Bottom to top 1.453 - - - - - - - Bottom to top 1.454 - - - - - - - Bottom to top 1.455 - - - - - - - Box.449 - - - - Bottom to top 1.456 - - - - - - - Bottom to top 1.457 - - - - - - - Box.447 - - - - Bottom to top 1.458 - - - - - - - Bottom to top 1.459 - - - - - - - Sheet.15 - RP - - - - RP - - Sheet.16 - RP - - - - RP - - Sheet.17 - RS - - - - RS - - Sheet.18 - RS - - - - RS - - Box.211 - SDA - - - - SDA - - Box.465 - SCL - - - - SCL - - Side to side 1 - - - - - - - Side to side 1.467 - - - - - - - Bottom to top 1.468 - - - - - - - Side to side 1.469 - - - - - - - Box.470 - VCC - - - - VCC - - Box.471 - I2C DEVICE #2 - - - - I2C DEVICE #2 - - Box.472 - - - - Box.473 - - - - Bottom to top 1.474 - - - - - - - Bottom to top 1.475 - - - - - - - Bottom to top 1.476 - - - - - - - Bottom to top 1.477 - - - - - - - Sheet.33 - RS - - - - RS - - Sheet.34 - RS - - - - RS - - Bottom to top 1.480 - - - - - - - Box.481 - I2C DEVICE #N - - - - I2C DEVICE #N - - Box.482 - - - - Box.483 - - - - Bottom to top 1.484 - - - - - - - Bottom to top 1.485 - - - - - - - Bottom to top 1.486 - - - - - - - Bottom to top 1.487 - - - - - - - Sheet.43 - RS - - - - RS - - Sheet.44 - RS - - - - RS - - Bottom to top 1.490 - - - - - - - Sheet.46 - - - - Sheet.47 - - - - Sheet.48 - - - - Sheet.49 - Note: RS is optional - - - - Note: RS is optional - - - diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/i2c_read.svg b/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/i2c_read.svg deleted file mode 100644 index 5be8085d96085..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/i2c_read.svg +++ /dev/null @@ -1,1037 +0,0 @@ - - - - - - - - - - image/svg+xml - - - - - - - - - - - ACK - - - - - - - - START - - - - - Bit 0 - - - - - - ADDRESS - - - - - - Bit 1 - - - - - - Bit 2 - - - - - - Bit 3 - - - - - - Bit 4 - - - - - - Bit 5 - - - - - - Bit 6 - - - - - - Bit 7 - - - - - - - READ - - - - - - Bit 8 - - - - - - Bit 9 - - - - - - - DATA - - - - - - - Bit 10 - - - - - - Bit 11 - - - - - - Bit 12 - - - - - - Bit 13 - - - - - - Bit 14 - - - - - - Bit 15 - - - - - - Bit 16 - - - - - - Bit 17 - - - - - - - ACK - - - - - Bit 18 - - - - - - - - DATA - - - - - - - Bit 19 - - - - - - Bit 20 - - - - - - Bit 21 - - - - - - Bit 22 - - - - - - Bit 23 - - - - - - Bit 24 - - - - - - Bit 25 - - - - - - Bit 26 - - - - - - - - - NACK - - - - Bit 27 - - - - - - - STOP - - - - - Bit 28 - - - - diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/i2c_write.svg b/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/i2c_write.svg deleted file mode 100644 index 6f2628100d320..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/docimg/i2c_write.svg +++ /dev/null @@ -1,1031 +0,0 @@ - - - - - - - - - - image/svg+xml - - - - - - - - - - - START - - - - - Bit 0 - - - - - - - ADDRESS - - - - - - Bit 1 - - - - - - Bit 2 - - - - - - Bit 3 - - - - - - Bit 4 - - - - - - Bit 5 - - - - - - Bit 6 - - - - - - Bit 7 - - - - - - - - - WRITE - - - - - - Bit 8 - - - - - - - - - ACK - - - - - - - Bit 9 - - - - - - DATA - - - - - Bit 10 - - - - - - Bit 11 - - - - - - Bit 12 - - - - - - Bit 13 - - - - - - Bit 14 - - - - - - Bit 15 - - - - - - Bit 16 - - - - - - Bit 17 - - - - - - - - ACK - - - - - Bit 18 - - - - - - - - DATA - - - - - - Bit 19 - - - - Bit 20 - - - - - Bit 21 - - - - - - Bit 22 - - - - - - Bit 23 - - - - - - Bit 24 - - - - - - Bit 25 - - - - - - Bit 26 - - - - - - - - ACK - - - - Bit 27 - - - - - - - STOP - - - - - Bit 28 - - - - diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_common.h b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_common.h deleted file mode 100644 index de4f0d23f54fd..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_common.h +++ /dev/null @@ -1,613 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Common Driver - * - * Copyright (c) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef I2C_COMMON_H_INCLUDED -#define I2C_COMMON_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \if (I2C_MASTER_MODE && I2C_SLAVE_MODE) - * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C (SERCOM I2C) Driver - * \elseif I2C_MASTER_MODE - * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Master Mode (SERCOM I2C) Driver - * \elseif I2C_SLAVE_MODE - * \defgroup asfdoc_sam0_sercom_i2c_group SAM I2C Slave Mode (SERCOM I2C) Driver - * \endif - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the device's SERCOM - * I2C module, for the transfer of data via an I2C bus. - * The following driver API modes are covered by this manual: - * - * \if I2C_MASTER_MODE - * - Master Mode Polled APIs - * \endif - * \if I2C_MASTER_CALLBACK_MODE - * - Master Mode Callback APIs - * \endif - * \if I2C_SLAVE_MODE - * - Slave Mode Polled APIs - * \endif - * \if I2C_SLAVE_CALLBACK_MODE - * - Slave Mode Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - SERCOM (Serial Communication Interface) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_sercom_i2c_prerequisites - * - \ref asfdoc_sam0_sercom_i2c_overview - * - \ref asfdoc_sam0_sercom_i2c_special_considerations - * - \ref asfdoc_sam0_sercom_i2c_extra - * - \ref asfdoc_sam0_sercom_i2c_examples - * - \ref asfdoc_sam0_sercom_i2c_api_overview - * - * \section asfdoc_sam0_sercom_i2c_prerequisites Prerequisites - * There are no prerequisites. - * - * \section asfdoc_sam0_sercom_i2c_overview Module Overview - * The outline of this section is as follows: - * - \ref asfdoc_sam0_sercom_i2c_module_features - * - \ref asfdoc_sam0_sercom_i2c_functional_desc - * - \ref asfdoc_sam0_sercom_i2c_bus_topology - * - \ref asfdoc_sam0_sercom_i2c_transactions - * - \ref asfdoc_sam0_sercom_i2c_multi_master - * - \ref asfdoc_sam0_sercom_i2c_bus_states - * - \ref asfdoc_sam0_sercom_i2c_timeout - * - \ref asfdoc_sam0_sercom_i2c_sleep_modes - * - * \subsection asfdoc_sam0_sercom_i2c_module_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEEDSAM D21/R21/D10/D11/L21/L22/DA1/C20/C21
FEATURE_I2C_10_BIT_ADDRESSSAM D21/R21/D10/D11/L21/L22/DA1/C20/C21
FEATURE_I2C_SCL_STRETCH_MODESAM D21/R21/D10/D11/L21/L22/DA1/C20/C21
FEATURE_I2C_SCL_EXTEND_TIMEOUTSAM D21/R21/D10/D11/L21/L22/DA1/C20/C21
- * \note The specific features are only available in the driver when the selected - * device supports those features. - * \note When using the I2C high-speed mode for off-board communication, - * there are various high frequency interference, which can lead to distortion of the signals - * and communication failure. When using Xplained Pro boards in order to test I2C high-speed - * communication, the following recommendation should be followed: - * - Use the SDA-line on PA08 and SCL-line on PA09 for both boards. This will provide stronger - * pull-ups on both SDA and SCL. - * - The SCL should not be higher than 1.5MHz. - * - * \subsection asfdoc_sam0_sercom_i2c_functional_desc Functional Description - * The I2C provides a simple two-wire bidirectional bus consisting of a - * wired-AND type serial clock line (SCL) and a wired-AND type serial data line - * (SDA). - * - * The I2C bus provides a simple, but efficient method of interconnecting - * multiple master and slave devices. An arbitration mechanism is provided for - * resolving bus ownership between masters, as only one master device may own - * the bus at any given time. The arbitration mechanism relies on the wired-AND - * connections to avoid bus drivers short-circuiting. - * - * A unique address is assigned to all slave devices connected to the bus. A - * device can contain both master and slave logic, and can emulate multiple - * slave devices by responding to more than one address. - * - * \subsection asfdoc_sam0_sercom_i2c_bus_topology Bus Topology - * The I2C bus topology is illustrated in - * \ref asfdoc_sam0_sercom_i2c_bus_topology_figure "the figure below". The pull-up - * resistors (Rs) will provide a high level on the bus lines when none of the - * I2C devices are driving the bus. These are optional, and can be - * replaced with a constant current source. - * - * \anchor asfdoc_sam0_sercom_i2c_bus_topology_figure - * \image html bus_topology.svg "I2C Bus Topology" Width=100% - * - * \subsection asfdoc_sam0_sercom_i2c_transactions Transactions - * The I2C standard defines three fundamental transaction formats: - * - Master Write - * - The master transmits data packets to the slave after addressing it - * - Master Read - * - The slave transmits data packets to the master after being addressed - * - Combined Read/Write - * - A combined transaction consists of several write and read transactions - * - * A data transfer starts with the master issuing a \b Start condition on the - * bus, followed by the address of the slave together with a bit to indicate - * whether the master wants to read from or write to the slave. - * The addressed slave must respond to this by sending an \b ACK back to the - * master. - * - * After this, data packets are sent from the master or slave, according to the - * read/write bit. Each packet must be acknowledged (ACK) or not - * acknowledged (NACK) by the receiver. - * - * If a slave responds with a NACK, the master must assume that the slave - * cannot receive any more data and cancel the write operation. - * - * The master completes a transaction by issuing a \b Stop condition. - * - * A master can issue multiple \b Start conditions during a transaction; this - * is then called a \b Repeated \b Start condition. - * - * \subsubsection asfdoc_sam0_sercom_i2c_address_packets Address Packets - * The slave address consists of seven bits. The 8th bit in the transfer - * determines the data direction (read or write). An address packet always - * succeeds a \b Start or \b Repeated \b Start condition. The 8th bit is handled - * in the driver, and the user will only have to provide the 7-bit address. - * - * \subsubsection asfdoc_sam0_sercom_i2c_data_packets Data Packets - * Data packets are nine bits long, consisting of one 8-bit data byte, and an - * acknowledgement bit. Data packets follow either an address packet or another - * data packet on the bus. - * - * \subsubsection asfdoc_sam0_sercom_i2c_trans_examples Transaction Examples - * The gray bits in the following examples are sent from master to slave, and - * the white bits are sent from slave to master. - * Example of a read transaction is shown in - * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_read "the figure below". Here, the - * master first issues a \b Start condition and gets ownership of the bus. An - * address packet with the direction flag set to read is then sent and - * acknowledged by the slave. Then the slave sends one data packet which is - * acknowledged by the master. The slave sends another packet, which is not - * acknowledged by the master and indicates that the master will terminate the - * transaction. In the end, the transaction is terminated by the master issuing - * a \b Stop condition. - * - * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_read - * \image html i2c_read.svg "I2C Packet Read" Width=100% - * - * Example of a write transaction is shown in - * \ref asfdoc_sam0_sercom_i2c_trans_examples_i2c_write "the figure below". Here, the - * master first issues a \b Start condition and gets ownership of the bus. An - * address packet with the dir flag set to write is then sent and acknowledged - * by the slave. Then the master sends two data packets, each acknowledged by - * the slave. In the end, the transaction is terminated by the master issuing - * a \b Stop condition. - * - * \anchor asfdoc_sam0_sercom_i2c_trans_examples_i2c_write - * \image html i2c_write.svg "I2C Packet Write" Width=100% - * - * \subsubsection asfdoc_sam0_sercom_i2c_packet_timeout Packet Timeout - * When a master sends an I2C packet, there is no way of - * being sure that a slave will acknowledge the packet. To avoid stalling the - * device forever while waiting for an acknowledge, a user selectable timeout - * is provided in the \ref i2c_master_config struct which - * lets the driver exit a read or write operation after the specified time. - * The function will then return the STATUS_ERR_TIMEOUT flag. - * - * This is also the case for the slave when using the functions postfixed - * \c _wait. - * - * The time before the timeout occurs, will be the same as - * for \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "unknown bus state" timeout. - * - * \subsubsection asfdoc_sam0_sercom_i2c_repeated_start Repeated Start - * To issue a \b Repeated \b Start, the functions postfixed \c _no_stop must be - * used. - * These functions will not send a \b Stop condition when the transfer is done, - * thus the next transfer will start with a \b Repeated \b Start. To end the - * transaction, the functions without the \c _no_stop postfix must be used - * for the last read/write. - * - * \subsection asfdoc_sam0_sercom_i2c_multi_master Multi Master - * In a multi master environment, arbitration of the bus is important, as only - * one master can own the bus at any point. - * - * \subsubsection asfdoc_sam0_sercom_i2c_arbitration Arbitration - * - * \par Clock stretching - * The serial clock line is always driven by a master device. However, all - * devices connected to the bus are allowed stretch the low period of the clock - * to slow down the overall clock frequency or to insert wait states while - * processing data. - * Both master and slave can randomly stretch the clock, which will force the - * other device into a wait-state until the clock line goes high again. - * - * \par Arbitration on the data line - * If two masters start transmitting at the same time, they will both transmit - * until one master detects that the other master is pulling the data line low. - * When this is detected, the master not pulling the line low, will stop the - * transmission and wait until the bus is idle. - * As it is the master trying to contact the slave with the lowest address that - * will get the bus ownership, this will create an arbitration scheme always - * prioritizing the slaves with the lowest address in case of a bus collision. - * - * \subsubsection asfdoc_sam0_sercom_i2c_clock_sync Clock Synchronization - * In situations where more than one master is trying to control the bus clock - * line at the same time, a clock synchronization algorithm based on the same - * principles used for clock stretching is necessary. - * - * - * \subsection asfdoc_sam0_sercom_i2c_bus_states Bus States - * As the I2C bus is limited to one transaction at the time, - * a master that wants to perform a bus transaction must wait until the bus is - * free. - * Because of this, it is necessary for all masters in a multi-master system to - * know the current status of the bus to be able to avoid conflicts and to - * ensure data integrity. - * \li \b IDLE No activity on the bus (between a \b Stop and a new \b Start - * condition) - * \li \b OWNER If the master initiates a transaction successfully - * \li \b BUSY If another master is driving the bus - * \li \b UNKNOWN If the master has recently been enabled or connected to - * the bus. Is forced to \b IDLE after given - * \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" when - * the master module is enabled - * - * The bus state diagram can be seen in - * \ref asfdoc_sam0_sercom_i2c_bus_states_figure "the figure below". - * \li S: Start condition - * \li P: Stop condition - * \li Sr: Repeated start condition - * \anchor asfdoc_sam0_sercom_i2c_bus_states_figure - * \image html bus_state_diagram.svg "I2C Bus State Diagram" Width=100% - * - * \subsection asfdoc_sam0_sercom_i2c_timeout Bus Timing - * Inactive bus timeout for the master and SDA hold time is configurable in the - * drivers. - * - * \subsubsection asfdoc_sam0_sercom_i2c_unknown_bus_timeout Unknown Bus State Timeout - * When a master is enabled or connected to the bus, the bus state will be - * unknown until either a given timeout or a stop command has occurred. The - * timeout is configurable in the \ref i2c_master_config struct. - * The timeout time will depend on toolchain and optimization level used, as - * the timeout is a loop incrementing a value until it reaches the specified - * timeout value. - * - * \subsubsection sda_hold SDA Hold Timeout - * When using the I2C in slave mode, it will be important to - * set a SDA hold time which assures that the master will be able to pick up - * the bit sent from the slave. The SDA hold time makes sure that this is the - * case by holding the data line low for a given period after the negative edge - * on the clock. - * - * The SDA hold time is also available for the master driver, but is not a - * necessity. - * - * \subsection asfdoc_sam0_sercom_i2c_sleep_modes Operation in Sleep Modes - * The I2C module can operate in all sleep modes by setting - * the run_in_standby Boolean in the \ref i2c_master_config or - * \ref i2c_slave_config struct. - * The operation in slave and master mode is shown in - * \ref asfdoc_sam0_sercom_i2c_sleep_modes_table "the table below". - * - * \anchor asfdoc_sam0_sercom_i2c_sleep_modes_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
I2C Standby Operations
Run in standbySlaveMaster
falseDisabled, all reception is droppedGeneric Clock (GCLK) disabled when master is idle
trueWake on address match when enabledGCLK enabled while in sleep modes
- * - * - * \section asfdoc_sam0_sercom_i2c_special_considerations Special Considerations - * - * \if (I2C_MASTER_CALLBACK_MODE || I2C_SLAVE_CALLBACK_MODE) - * \subsection asfdoc_sam0_sercom_i2c_common_interrupt Interrupt-driven Operation - * While an interrupt-driven operation is in progress, subsequent calls to a - * write or read operation will return the STATUS_BUSY flag, indicating that - * only one operation is allowed at any given time. - * - * To check if another transmission can be initiated, the user can either call - * another transfer operation, or use the - * \ref i2c_master_get_job_status/\ref i2c_slave_get_job_status functions - * depending on mode. - * - * If the user would like to get callback from operations while using the - * interrupt-driven driver, the callback must be registered and then enabled - * using the "register_callback" and "enable_callback" functions. - * \else - * There are no special considerations for this driver for the APIs listed in - * this document. - * \endif - * - * \section asfdoc_sam0_sercom_i2c_extra Extra Information - * For extra information, see \ref asfdoc_sam0_sercom_i2c_extra_info_page. - * This includes: - * - \ref asfdoc_sam0_sercom_i2c_acronyms - * - \ref asfdoc_sam0_sercom_i2c_extra_dependencies - * - \ref asfdoc_sam0_sercom_i2c_extra_errata - * - \ref asfdoc_sam0_sercom_i2c_extra_history - * - * \section asfdoc_sam0_sercom_i2c_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_sercom_i2c_exqsg. - * - * \section asfdoc_sam0_sercom_i2c_api_overview API Overview - * @{ - */ - -/** - * \name Driver Feature Definition - * Define SERCOM I2C driver features set according to different device family. - * - * @{ - */ -#if (SAMD21) || (SAMR21) || (SAMD10) || (SAMD11) || (SAML21) || (SAMDA1) || \ - (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__) -/** Fast mode plus and high speed support. */ -# define FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED -/** 10-bit address support */ -# define FEATURE_I2C_10_BIT_ADDRESS -/** SCL stretch mode support */ -# define FEATURE_I2C_SCL_STRETCH_MODE -/** SCL extend timeout support */ -# define FEATURE_I2C_SCL_EXTEND_TIMEOUT -# define FEATURE_I2C_DMA_SUPPORT -#endif -/*@}*/ - -/** \brief Transfer direction - * - * For master: transfer direction or setting direction bit in address. - * For slave: direction of request from master. - */ -enum i2c_transfer_direction { - /** Master write operation is in progress */ - I2C_TRANSFER_WRITE = 0, - /** Master read operation is in progress */ - I2C_TRANSFER_READ = 1, -}; - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \page asfdoc_sam0_sercom_i2c_extra_info_page Extra Information for SERCOM I2C Driver - * - * \section asfdoc_sam0_sercom_i2c_acronyms Acronyms - * \ref asfdoc_sam0_sercom_i2c_acronyms_table "Below" is a table listing the acronyms - * used in this module, along with their intended meanings. - * - * \anchor asfdoc_sam0_sercom_i2c_acronyms_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Acronyms
AcronymDescription
SDASerial Data Line
SCLSerial Clock Line
SERCOMSerial Communication Interface
DMADirect Memory Access
- * - * \section asfdoc_sam0_sercom_i2c_extra_dependencies Dependencies - * The I2C driver has the following dependencies: - * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_sercom_i2c_extra_errata Errata - * There are no errata related to this driver. - * - * \section asfdoc_sam0_sercom_i2c_extra_history Module History - * \ref asfdoc_sam0_sercom_i2c_extra_history_table "Below" is an overview of the - * module history, detailing enhancements and fixes made to the module since - * its first release. The current version of this corresponds to the newest - * version listed in - * \ref asfdoc_sam0_sercom_i2c_extra_history_table "the table below". - * - * \anchor asfdoc_sam0_sercom_i2c_extra_history_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Module History
Changelog
- * \li Added 10-bit addressing and high speed support in SAM D21 - * \li Separate structure i2c_packet into i2c_master_packet and i2c_slave packet - *
- * \li Added support for SCL stretch and extended timeout hardware features in SAM D21 - * \li Added fast mode plus support in SAM D21 - *
Fixed incorrect logical mask for determining if a bus error has - * occurred in I2C Slave mode - *
Initial Release
- */ - -/** - * \page asfdoc_sam0_sercom_i2c_exqsg Examples for SERCOM I2C Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_sercom_i2c_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * \if I2C_MASTER_MODE - * - \subpage asfdoc_sam0_sercom_i2c_master_basic_use_case "Quick Start Guide for the I2C Master module - Basic Use Case" - * \endif - * \if I2C_MASTER_CALLBACK_MODE - * - \subpage asfdoc_sam0_sercom_i2c_master_callback_use_case "Quick Start Guide for the I2C Master module - Callback Use Case" - * - \subpage asfdoc_sam0_sercom_i2c_master_dma_use_case "Quick Start Guide for the I2C Master module - DMA Use Case" - * \endif - * \if I2C_SLAVE_MODE - * - \subpage asfdoc_sam0_sercom_i2c_slave_basic_use_case "Quick Start Guide for the I2C Slave module - Basic Use Case" - * \endif - * \if I2C_SLAVE_CALLBACK_MODE - * - \subpage asfdoc_sam0_sercom_i2c_slave_callback_use_case "Quick Start Guide for the I2C Slave module - Callback Use Case" - * - \subpage asfdoc_sam0_sercom_i2c_slave_dma_use_case "Quick Start Guide for the I2C Slave module - DMA Use Case" - * \endif - * - * \page asfdoc_sam0_sercom_i2c_document_revision_history Document Revision History - * - * \if (I2C_MASTER_MODE || I2C_MASTER_CALLBACK_MODE) - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42117E12/2015Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21
42117D12/2014Added support for 10-bit addressing and high speed in SAM D21. - * Added support for SAM R21 and SAM D10/D11.
42117C01/2014Added support for SAM D21
42117B06/2013Corrected documentation typos. Updated I2C Bus State Diagram.
42117A06/2013Initial release
- * \else - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42116E12/2015Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21
42116D12/2014Added support for 10-bit addressing and high speed in SAM D21. - * Added support for SAM R21 and SAM D10/D11.
42116C01/2014Added support for SAM D21
42116B06/2013Corrected documentation typos. Updated I2C Bus State Diagram.
42116A06/2013Initial release
- *\endif - */ - -#endif /* I2C_COMMON_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_master.h b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_master.h deleted file mode 100644 index 79c2effe8e590..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_master.h +++ /dev/null @@ -1,629 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Master Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_MASTER_H_INCLUDED -#define I2C_MASTER_H_INCLUDED - -#include "i2c_common.h" -#include -#include - -#if I2C_MASTER_CALLBACK_MODE == true -# include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef PINMUX_DEFAULT -# define PINMUX_DEFAULT 0 -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * - * @{ - */ - -/** - * \brief I2C master packet for read/write - * - * Structure to be used when transferring I2C master packets. - */ -struct i2c_master_packet { - /** Address to slave device */ - uint16_t address; - /** Length of data array */ - uint16_t data_length; - /** Data array containing all data to be transferred */ - uint8_t *data; - /** Use 10-bit addressing. Set to false if the feature is not supported by the device */ - bool ten_bit_address; - /** Use high speed transfer. Set to false if the feature is not supported by the device */ - bool high_speed; - /** High speed mode master code (0000 1XXX), valid when high_speed is true */ - uint8_t hs_master_code; -}; - -/** \brief Interrupt flags - * - * Flags used when reading or setting interrupt flags. - */ -enum i2c_master_interrupt_flag { - /** Interrupt flag used for write */ - I2C_MASTER_INTERRUPT_WRITE = 0, - /** Interrupt flag used for read */ - I2C_MASTER_INTERRUPT_READ = 1, -}; - -/** - * \brief Values for hold time after start bit. - * - * Values for the possible I2C master mode SDA internal hold times after start - * bit has been sent. - */ -enum i2c_master_start_hold_time { - /** Internal SDA hold time disabled */ - I2C_MASTER_START_HOLD_TIME_DISABLED = SERCOM_I2CM_CTRLA_SDAHOLD(0), - /** Internal SDA hold time 50ns - 100ns */ - I2C_MASTER_START_HOLD_TIME_50NS_100NS = SERCOM_I2CM_CTRLA_SDAHOLD(1), - /** Internal SDA hold time 300ns - 600ns */ - I2C_MASTER_START_HOLD_TIME_300NS_600NS = SERCOM_I2CM_CTRLA_SDAHOLD(2), - /** Internal SDA hold time 400ns - 800ns */ - I2C_MASTER_START_HOLD_TIME_400NS_800NS = SERCOM_I2CM_CTRLA_SDAHOLD(3), -}; - -/** - * \brief Values for inactive bus time-out. - * - * If the inactive bus time-out is enabled and the bus is inactive for - * longer than the time-out setting, the bus state logic will be set to idle. - */ -enum i2c_master_inactive_timeout { - /** Inactive bus time-out disabled */ - I2C_MASTER_INACTIVE_TIMEOUT_DISABLED = SERCOM_I2CM_CTRLA_INACTOUT(0), - /** Inactive bus time-out 5-6 SCL cycle time-out */ - I2C_MASTER_INACTIVE_TIMEOUT_55US = SERCOM_I2CM_CTRLA_INACTOUT(1), - /** Inactive bus time-out 10-11 SCL cycle time-out */ - I2C_MASTER_INACTIVE_TIMEOUT_105US = SERCOM_I2CM_CTRLA_INACTOUT(2), - /** Inactive bus time-out 20-21 SCL cycle time-out */ - I2C_MASTER_INACTIVE_TIMEOUT_205US = SERCOM_I2CM_CTRLA_INACTOUT(3), -}; - -/** - * \brief I2C frequencies - * - * Values for I2C speeds supported by the module. The driver - * will also support setting any other value, in which case set - * the value in the \ref i2c_master_config at desired value divided by 1000. - * - * Example: If 10KHz operation is required, give baud_rate in the configuration - * structure the value 10. - */ -enum i2c_master_baud_rate { - /** Baud rate at 100KHz (Standard-mode) */ - I2C_MASTER_BAUD_RATE_100KHZ = 100, - /** Baud rate at 400KHz (Fast-mode) */ - I2C_MASTER_BAUD_RATE_400KHZ = 400, -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Baud rate at 1MHz (Fast-mode Plus) */ - I2C_MASTER_BAUD_RATE_1000KHZ = 1000, - /** Baud rate at 3.4MHz (High-speed mode) */ - I2C_MASTER_BAUD_RATE_3400KHZ = 3400, -#endif -}; - -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED -/** - * \brief Enum for the transfer speed - * - * Enum for the transfer speed. - */ -enum i2c_master_transfer_speed { - /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */ - I2C_MASTER_SPEED_STANDARD_AND_FAST = SERCOM_I2CM_CTRLA_SPEED(0), - /** Fast-mode Plus (Fm+) up to 1MHz */ - I2C_MASTER_SPEED_FAST_MODE_PLUS = SERCOM_I2CM_CTRLA_SPEED(1), - /** High-speed mode (Hs-mode) up to 3.4MHz */ - I2C_MASTER_SPEED_HIGH_SPEED = SERCOM_I2CM_CTRLA_SPEED(2), -}; -#endif - -#if I2C_MASTER_CALLBACK_MODE == true -/** - * \brief Callback types - * - * The available callback types for the I2C master module. - */ -enum i2c_master_callback { - /** Callback for packet write complete */ - I2C_MASTER_CALLBACK_WRITE_COMPLETE = 0, - /** Callback for packet read complete */ - I2C_MASTER_CALLBACK_READ_COMPLETE = 1, - /** Callback for error */ - I2C_MASTER_CALLBACK_ERROR = 2, -# if !defined(__DOXYGEN__) - /** Total number of callbacks */ - _I2C_MASTER_CALLBACK_N = 3, -# endif -}; - -# if !defined(__DOXYGEN__) -/* Prototype for software module */ -struct i2c_master_module; - -typedef void (*i2c_master_callback_t)( - struct i2c_master_module *const module); -# endif -#endif - -/** - * \brief SERCOM I2C Master driver software device instance structure. - * - * SERCOM I2C Master driver software instance structure, used to - * retain software state information of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct i2c_master_module { -#if !defined(__DOXYGEN__) - /** Hardware instance initialized for the struct */ - Sercom *hw; - /** Module lock */ - volatile bool locked; - /** Unknown bus state timeout */ - uint16_t unknown_bus_state_timeout; - /** Buffer write timeout value */ - uint16_t buffer_timeout; - /** If true, stop condition will be sent after a read/write */ - bool send_stop; - /** If true, nack signal will be sent after a read/write */ - bool send_nack; -# if I2C_MASTER_CALLBACK_MODE == true - /** Pointers to callback functions */ - volatile i2c_master_callback_t callbacks[_I2C_MASTER_CALLBACK_N]; - /** Mask for registered callbacks */ - volatile uint8_t registered_callback; - /** Mask for enabled callbacks */ - volatile uint8_t enabled_callback; - /** The total number of bytes to transfer */ - volatile uint16_t buffer_length; - /** - * Counter used for bytes left to send in write and to count number of - * obtained bytes in read - */ - volatile uint16_t buffer_remaining; - /** Data buffer for packet write and read */ - volatile uint8_t *buffer; - /** Save direction of async request. 1 = read, 0 = write */ - volatile enum i2c_transfer_direction transfer_direction; - /** Status for status read back in error callback */ - volatile enum status_code status; -# endif -#endif -}; - -/** - * \brief Configuration structure for the I2C Master device - * - * This is the configuration structure for the I2C Master device. It - * is used as an argument for \ref i2c_master_init to provide the desired - * configurations for the module. The structure should be initialized using the - * \ref i2c_master_get_config_defaults. - */ -struct i2c_master_config { - /** Baud rate (in KHz) for I2C operations in - * standard-mode, Fast-mode, and Fast-mode Plus Transfers, - * \ref i2c_master_baud_rate */ - uint32_t baud_rate; -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Baud rate (in KHz) for I2C operations in - * High-speed mode, \ref i2c_master_baud_rate */ - uint32_t baud_rate_high_speed; - /** Transfer speed mode */ - enum i2c_master_transfer_speed transfer_speed; -#endif - /** GCLK generator to use as clock source */ - enum gclk_generator generator_source; - /** Bus hold time after start signal on data line */ - enum i2c_master_start_hold_time start_hold_time; - /** Unknown bus state \ref asfdoc_sam0_sercom_i2c_unknown_bus_timeout "timeout" */ - uint16_t unknown_bus_state_timeout; - /** Timeout for packet write to wait for slave */ - uint16_t buffer_timeout; - /** Set to keep module active in sleep modes */ - bool run_in_standby; - /** PAD0 (SDA) pinmux */ - uint32_t pinmux_pad0; - /** PAD1 (SCL) pinmux */ - uint32_t pinmux_pad1; - /** Set to enable SCL low time-out */ - bool scl_low_timeout; - /** Inactive bus time out */ - enum i2c_master_inactive_timeout inactive_timeout; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - /** Set to enable SCL stretch only after ACK bit (required for high speed) */ - bool scl_stretch_only_after_ack_bit; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - /** Set to enable slave SCL low extend time-out */ - bool slave_scl_low_extend_timeout; - /** Set to enable maser SCL low extend time-out */ - bool master_scl_low_extend_timeout; -#endif - /** Get more accurate BAUD, considering rise time(required for standard-mode and Fast-mode) */ - uint16_t sda_scl_rise_time_ns; -}; - -/** - * \name Lock/Unlock - * @{ - */ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline enum status_code i2c_master_lock( - struct i2c_master_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline void i2c_master_unlock(struct i2c_master_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \name Configuration and Initialization - * @{ - */ - -/** - * \brief Returns the synchronization status of the module - * - * Returns the synchronization status of the module. - * - * \param[in] module Pointer to software module structure - * - * \return Status of the synchronization. - * \retval true Module is busy synchronizing - * \retval false Module is not synchronizing - */ -static inline bool i2c_master_is_syncing ( - const struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_hw = &(module->hw->I2CM); - -#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1) - return (i2c_hw->STATUS.reg & SERCOM_I2CM_STATUS_SYNCBUSY); -#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2) - return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_MASK); -#else -# error Unknown SERCOM SYNCBUSY scheme! -#endif -} - -#if !defined(__DOXYGEN__) -/** - * \internal - * Wait for hardware module to sync - * - * \param[in] module Pointer to software module structure - */ -static void _i2c_master_wait_for_sync( - const struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - - while (i2c_master_is_syncing(module)) { - /* Wait for I2C module to sync. */ - } -} -#endif - -/** - * \brief Gets the I2C master default configurations - * - * Use to initialize the configuration structure to known default values. - * - * The default configuration is as follows: - * - Baudrate 100KHz - * - GCLK generator 0 - * - Do not run in standby - * - Start bit hold time 300ns - 600ns - * - Buffer timeout = 65535 - * - Unknown bus status timeout = 65535 - * - Do not run in standby - * - PINMUX_DEFAULT for SERCOM pads - * - * Those default configuration only available if the device supports it: - * - High speed baudrate 3.4MHz - * - Standard-mode and Fast-mode transfer speed - * - SCL stretch disabled - * - Slave SCL low extend time-out disabled - * - Master SCL low extend time-out disabled - * - * \param[out] config Pointer to configuration structure to be initiated - */ -static inline void i2c_master_get_config_defaults( - struct i2c_master_config *const config) -{ - /*Sanity check argument */ - Assert(config); - config->baud_rate = I2C_MASTER_BAUD_RATE_100KHZ; -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - config->baud_rate_high_speed = I2C_MASTER_BAUD_RATE_3400KHZ; - config->transfer_speed = I2C_MASTER_SPEED_STANDARD_AND_FAST; -#endif - config->generator_source = GCLK_GENERATOR_0; - config->run_in_standby = false; - config->start_hold_time = I2C_MASTER_START_HOLD_TIME_300NS_600NS; - config->buffer_timeout = 65535; - config->unknown_bus_state_timeout = 65535; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->scl_low_timeout = false; - config->inactive_timeout = I2C_MASTER_INACTIVE_TIMEOUT_DISABLED; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - config->scl_stretch_only_after_ack_bit = false; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - config->slave_scl_low_extend_timeout = false; - config->master_scl_low_extend_timeout = false; -#endif - /* The typical value is 215ns */ - config->sda_scl_rise_time_ns = 215; -} - -enum status_code i2c_master_init( - struct i2c_master_module *const module, - Sercom *const hw, - const struct i2c_master_config *const config); - -/** - * \brief Enables the I2C module - * - * Enables the requested I2C module and set the bus state to IDLE - * after the specified \ref asfdoc_sam0_sercom_i2c_timeout "timeout" period if no - * stop bit is detected. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_master_enable( - const struct i2c_master_module *const module) -{ - /* Sanity check of arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Timeout counter used to force bus state */ - uint32_t timeout_counter = 0; - - /* Wait for module to sync */ - _i2c_master_wait_for_sync(module); - - /* Enable module */ - i2c_module->CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; - -#if I2C_MASTER_CALLBACK_MODE == true - /* Enable module interrupts */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); -#endif - /* Start timeout if bus state is unknown */ - while (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(1))) { - timeout_counter++; - if(timeout_counter >= (module->unknown_bus_state_timeout)) { - /* Timeout, force bus state to idle */ - i2c_module->STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(1); - /* Workaround #1 */ - return; - } - } -} - -/** - * \brief Disable the I2C module - * - * Disables the requested I2C module. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_master_disable( - const struct i2c_master_module *const module) -{ - /* Sanity check of arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Disable module interrupts */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait for module to sync */ - _i2c_master_wait_for_sync(module); - - /* Disbale interrupt */ - i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK; - /* Clear interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MASK; - - /* Disable module */ - i2c_module->CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; - -} - -void i2c_master_reset(struct i2c_master_module *const module); - -/** @} */ - -/** -* \name Read and Write -* @{ -*/ - -enum status_code i2c_master_read_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -void i2c_master_send_stop(struct i2c_master_module *const module); - -void i2c_master_send_nack(struct i2c_master_module *const module); - -enum status_code i2c_master_read_byte( - struct i2c_master_module *const module, - uint8_t *byte); - -enum status_code i2c_master_write_byte( - struct i2c_master_module *const module, - uint8_t byte); - -enum status_code i2c_master_read_packet_wait_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -/** @} */ - -#ifdef FEATURE_I2C_DMA_SUPPORT -/** -* \name SERCOM I2C Master with DMA Interfaces -* @{ -*/ - -/** - * \brief Set I2C for DMA transfer with slave address and transfer size. - * - * This function will set the slave address, transfer size and enable the auto transfer - * mode for DMA. - * - * \param[in,out] module Pointer to the driver instance to lock - * \param[in] addr I2C slave address - * \param[in] length I2C transfer length with DMA - * \param[in] direction I2C transfer direction - * - */ -static inline void i2c_master_dma_set_transfer(struct i2c_master_module *const module, - uint16_t addr, uint8_t length, enum i2c_transfer_direction direction) -{ - module->hw->I2CM.ADDR.reg = - SERCOM_I2CM_ADDR_ADDR(addr<<1) | - SERCOM_I2CM_ADDR_LENEN | - SERCOM_I2CM_ADDR_LEN(length) | - direction; -} - -/** @} */ -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_MASTER_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_master_interrupt.h b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_master_interrupt.h deleted file mode 100644 index 249525d3c14c9..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_master_interrupt.h +++ /dev/null @@ -1,214 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Master Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_MASTER_INTERRUPT_H_INCLUDED -#define I2C_MASTER_INTERRUPT_H_INCLUDED - -#include "i2c_master.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * @{ - * - */ - -/** - * \name Callbacks - * @{ - */ -#if !defined(__DOXYGEN__) -void _i2c_master_interrupt_handler( - uint8_t instance); -#endif - -void i2c_master_register_callback( - struct i2c_master_module *const module, - i2c_master_callback_t callback, - enum i2c_master_callback callback_type); - -void i2c_master_unregister_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type); - -/** - * \brief Enables callback - * - * Enables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to enable - */ -static inline void i2c_master_enable_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Mark callback as enabled */ - module->enabled_callback |= (1 << callback_type); -} - -/** - * \brief Disables callback - * - * Disables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to disable - */ -static inline void i2c_master_disable_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Mark callback as disabled */ - module->enabled_callback &= ~(1 << callback_type); -} - -/** @} */ - -/** - * \name Read and Write, Interrupt-driven - * @{ - */ - -enum status_code i2c_master_read_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_read_packet_job_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -enum status_code i2c_master_write_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet); - -/** - * \brief Cancel any currently ongoing operation - * - * Terminates the running transfer operation. - * - * \param[in,out] module Pointer to software module structure - */ -static inline void i2c_master_cancel_job( - struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Set buffer to 0 */ - module->buffer_remaining = 0; - /* Update status */ - module->status = STATUS_ABORTED; -} - -/** - * \brief Get status from ongoing job - * - * Will return the status of a transfer operation. - * - * \param[in] module Pointer to software module structure - * - * \return Last status code from transfer operation. - * \retval STATUS_OK No error has occurred - * \retval STATUS_BUSY If transfer is in progress - * \retval STATUS_BUSY If master module is busy - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave does not - * want more data and was not able to read - */ -static inline enum status_code i2c_master_get_job_status( - struct i2c_master_module *const module) -{ - /* Check sanity */ - Assert(module); - Assert(module->hw); - - /* Return current status code */ - return module->status; -} - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_MASTER_INTERRUPT_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c deleted file mode 100644 index 4e37b4f090423..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master.c +++ /dev/null @@ -1,1050 +0,0 @@ -/** - * \file - * - * \brief SAM I2C Master Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_master.h" - -#if I2C_MASTER_CALLBACK_MODE == true -# include "i2c_master_interrupt.h" -#endif - -/* Forward declaration */ -enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module); - -enum status_code _i2c_master_address_response( - struct i2c_master_module *const module); - -enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code); - -#if !defined(__DOXYGEN__) - -/** - * \internal Sets configurations to module - * - * \param[out] module Pointer to software module structure - * \param[in] config Configuration structure with configurations to set - * - * \return Status of setting configuration. - * \retval STATUS_OK If module was configured correctly - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible - * with set GCLK frequency - */ -static enum status_code _i2c_master_set_config( - struct i2c_master_module *const module, - const struct i2c_master_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(config); - - /* Temporary variables. */ - uint32_t tmp_ctrla; - int32_t tmp_baud = 0; - int32_t tmp_baud_hs = 0; - int32_t tmp_baudlow_hs = 0; - enum status_code tmp_status_code = STATUS_OK; - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - Sercom *const sercom_hw = module->hw; - - uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw); - - /* Pin configuration */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; - - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - - /* Save timeout on unknown bus state in software module. */ - module->unknown_bus_state_timeout = config->unknown_bus_state_timeout; - - /* Save timeout on buffer write. */ - module->buffer_timeout = config->buffer_timeout; - - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } - - /* Check and set start data hold timeout. */ - if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) { - tmp_ctrla |= config->start_hold_time; - } - - /* Check and set transfer speed */ - tmp_ctrla |= config->transfer_speed; - - /* Check and set SCL low timeout. */ - if (config->scl_low_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - } - - /* Check and set inactive bus timeout. */ - if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) { - tmp_ctrla |= config->inactive_timeout; - } - - /* Check and set SCL clock stretch mode. */ - if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED)) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM; - } - - /* Check and set slave SCL low extend timeout. */ - if (config->slave_scl_low_extend_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN; - } - - /* Check and set master SCL low extend timeout. */ - if (config->master_scl_low_extend_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN; - } - - /* Write config to register CTRLA. */ - i2c_module->CTRLA.reg |= tmp_ctrla; - - /* Set configurations in CTRLB. */ - i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN; - - /* Find and set baudrate, considering sda/scl rise time */ - uint32_t fgclk = system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index); - uint32_t fscl = 1000 * config->baud_rate; - uint32_t fscl_hs = 1000 * config->baud_rate_high_speed; - uint32_t trise = config->sda_scl_rise_time_ns; - - tmp_baud = (int32_t)(div_ceil( - fgclk - fscl * (10 + fgclk * trise * 0.000000001), 2 * fscl)); - - /* For High speed mode, set the SCL ratio of high:low to 1:2. */ - if (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED) { - tmp_baudlow_hs = (int32_t)((fgclk * 2.0) / (3.0 * fscl_hs) - 1); - if (tmp_baudlow_hs) { - tmp_baud_hs = (int32_t)(fgclk / fscl_hs) - 2 - tmp_baudlow_hs; - } else { - tmp_baud_hs = (int32_t)(div_ceil(fgclk, 2 * fscl_hs)) - 1; - } - } - - /* Check that baudrate is supported at current speed. */ - if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) { - /* Baud rate acceptable. */ - i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) | - SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs) | SERCOM_I2CM_BAUD_HSBAUDLOW(tmp_baudlow_hs); - } - - return tmp_status_code; -} -#endif /* __DOXYGEN__ */ - -/** - * \brief Initializes the requested I2C hardware module - * - * Initializes the SERCOM I2C master device requested and sets the provided - * software module struct. Run this function before any further use of - * the driver. - * - * \param[out] module Pointer to software module struct - * \param[in] hw Pointer to the hardware instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible - * with set GCLK frequency - * - */ -enum status_code i2c_master_init( - struct i2c_master_module *const module, - Sercom *const hw, - const struct i2c_master_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize software module */ - module->hw = hw; - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index, gclk_index; - -#if (SAML22) || (SAMC20) - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#elif (SAML21) || (SAMR30) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC21) - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - if (sercom_index == 5) { - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - /* Turn on module in PM */ -#if (SAML21) || (SAMR30) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - - /* Check if module is enabled. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) { - return STATUS_BUSY; - } - -#if I2C_MASTER_CALLBACK_MODE == true - /* Get sercom instance index and register callback. */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _i2c_master_interrupt_handler); - _sercom_instances[instance_index] = module; - - /* Initialize values in module. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; - - module->status = STATUS_OK; - module->buffer = NULL; -#endif - - /* Set sercom module to operate in I2C master mode. */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5); - - /* Set config and return status. */ - return _i2c_master_set_config(module, config); -} - -/** - * \brief Resets the hardware module - * - * Reset the module to hardware defaults. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_master_reset(struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for sync */ - _i2c_master_wait_for_sync(module); - - /* Disable module */ - i2c_master_disable(module); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Clear all pending interrupts */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); -#endif - - /* Wait for sync */ - _i2c_master_wait_for_sync(module); - - /* Reset module */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST; -} - -#if !defined(__DOXYGEN__) -/** - * \internal - * Address response. Called when address is answered or timed out. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of address response. - * \retval STATUS_OK No error has occurred - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code _i2c_master_address_response( - struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in - * BUSY */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) { - - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; - - /* Check arbitration. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { - /* Return packet collision. */ - return STATUS_ERR_PACKET_COLLISION; - } - /* Check that slave responded with ack. */ - } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Slave busy. Issue ack and stop command. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - - /* Return bad address value. */ - return STATUS_ERR_BAD_ADDRESS; - } - - return STATUS_OK; -} - -/** - * \internal - * Waits for answer on bus. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of bus. - * \retval STATUS_OK If given response from slave device - * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout - * period - */ -enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) && - !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) { - - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; -} -#endif /* __DOXYGEN__ */ - -/** - * \internal - * Send master code for high speed transfer. - * - * \param[in,out] module Pointer to software module structure - * \param[in] hs_master_code 8-bit master code (0000 1XXX) - * - * \return Status of bus. - * \retval STATUS_OK No error happen - */ -enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code) -{ - SercomI2cm *const i2c_module = &(module->hw->I2CM); - /* Return value. */ - enum status_code tmp_status; - - /* Set NACK for high speed code */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - /* Send high speed code */ - i2c_module->ADDR.reg = hs_master_code; - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB; - - return tmp_status; -} - - -/** - * \internal - * Starts blocking read operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * - */ -static enum status_code _i2c_master_read_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; - - /* Written buffer counter. */ - uint16_t counter = 0; - - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Set address and direction bit. Will send start command on bus. */ - if (packet->ten_bit_address) { - /* - * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must - * be set and read/write bit (ADDR.ADDR[0]) equal to 0. - */ - i2c_module->ADDR.reg = (packet->address << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - if (tmp_status == STATUS_OK) { - /* - * Write ADDR[7:0] register to "11110 address[9:8] 1" - * ADDR.TENBITEN must be cleared - */ - i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - I2C_TRANSFER_READ; - } else { - return tmp_status; - } - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Set action to ack or nack. */ - if ((sclsm_flag) && (packet->data_length == 1)) { - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - } - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Read data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } - - if (module->send_nack && (((!sclsm_flag) && (tmp_data_length == 0)) || - ((sclsm_flag) && (tmp_data_length == 1)))) { - /* Set action to NACK */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - /* Save data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter++] = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - } - - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } - } - - if (module->send_stop) { - /* Send stop command unless arbitration is lost. */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - - /* Save last data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter] = i2c_module->DATA.reg; - } - - return tmp_status; -} - -/** - * \brief Reads data packet from slave - * - * Reads a data packet from the specified slave address on the I2C - * bus and sends a stop condition when finished. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = true; - module->send_nack = true; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Reads data packet from slave without sending a stop condition when done - * - * Reads a data packet from the specified slave address on the I2C - * bus without sending a stop condition when done, thus retaining ownership of - * the bus when done. To end the transaction, a - * \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = true; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts blocking read operation. - * \brief Reads data packet from slave without sending a nack signal and a stop - * condition when done - * - * Reads a data packet from the specified slave address on the I2C - * bus without sending a nack signal and a stop condition when done, - * thus retaining ownership of the bus when done. To end the transaction, a - * \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = false; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts blocking write operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK The packet was write successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -static enum status_code _i2c_master_write_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; - - _i2c_master_wait_for_sync(module); - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Set address and direction bit. Will send start command on bus. */ - if (packet->ten_bit_address) { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Buffer counter. */ - uint16_t buffer_counter = 0; - - /* Write data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } - - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = packet->data[buffer_counter++]; - - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } - - /* Check for NACK from slave. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Return bad data value. */ - tmp_status = STATUS_ERR_OVERFLOW; - break; - } - } - - if (module->send_stop) { - /* Stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - - return tmp_status; -} - -/** - * \brief Writes data packet to slave - * - * Writes a data packet to the specified slave address on the I2C bus - * and sends a stop condition when finished. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK If packet was write successfully - * \retval STATUS_BUSY If master module is busy with a job - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave does not - * want more data and was not able to read - * last data sent - */ -enum status_code i2c_master_write_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = true; - module->send_nack = true; - - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Writes data packet to slave without sending a stop condition when done - * - * Writes a data packet to the specified slave address on the I2C bus - * without sending a stop condition, thus retaining ownership of the bus when - * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition or sending a - * stop with the \ref i2c_master_send_stop function must be performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK If packet was write successfully - * \retval STATUS_BUSY If master module is busy - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave do not want - * more data - */ -enum status_code i2c_master_write_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = true; - - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Sends stop condition on bus - * - * Sends a stop condition on bus. - * - * \note This function can only be used after the - * \ref i2c_master_write_packet_wait_no_stop function. If a stop condition - * is to be sent after a read, the \ref i2c_master_read_packet_wait - * function must be used. - * - * \param[in,out] module Pointer to the software instance struct - */ -void i2c_master_send_stop(struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Send stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); -} - -/** - * \brief Sends nack signal on bus - * - * Sends a nack signal on bus. - * - * \note This function can only be used after the - * \ref i2c_master_write_packet_wait_no_nack function, - * or \ref i2c_master_read_byte function. - * \param[in,out] module Pointer to the software instance struct - */ -void i2c_master_send_nack(struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Send nack signal */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; -} - -/** - * \brief Reads one byte data from slave - * - * \param[in,out] module Pointer to software module struct - * \param[out] byte Read one byte data to slave - * - * \return Status of reading byte. - * \retval STATUS_OK One byte was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_byte( - struct i2c_master_module *const module, - uint8_t *byte) -{ - enum status_code tmp_status; - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - *byte = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - - return tmp_status; -} - -/** - * \brief Write one byte data to slave - * - * \param[in,out] module Pointer to software module struct - * \param[in] byte Send one byte data to slave - * - * \return Status of writing byte. - * \retval STATUS_OK One byte was write successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_write_byte( - struct i2c_master_module *const module, - uint8_t byte) -{ - enum status_code tmp_status; - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = byte; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - return tmp_status; -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c deleted file mode 100644 index 7551b291256f1..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_master_interrupt.c +++ /dev/null @@ -1,762 +0,0 @@ -/** - * \file - * - * \brief SAM I2C Master Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_master_interrupt.h" - -extern enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module); - -extern enum status_code _i2c_master_address_response( - struct i2c_master_module *const module); - -extern enum status_code _i2c_master_send_hs_master_code( - struct i2c_master_module *const module, - uint8_t hs_master_code);; - -/** - * \internal - * Read next data. Used by interrupt handler to get next data byte from slave. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_read( - struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - - /* Find index to save next value in buffer */ - uint16_t buffer_index = module->buffer_length; - buffer_index -= module->buffer_remaining; - - module->buffer_remaining--; - - if (sclsm_flag) { - if (module->send_nack && module->buffer_remaining == 1) { - /* Set action to NACK. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } - } else { - if (module->send_nack && module->buffer_remaining == 0) { - /* Set action to NACK. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } - } - - if (module->buffer_remaining == 0) { - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - - /* Read byte from slave and put in buffer */ - _i2c_master_wait_for_sync(module); - module->buffer[buffer_index] = i2c_module->DATA.reg; -} - -/** - * \internal - * - * Write next data. Used by interrupt handler to send next data byte to slave. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_write(struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for ack from slave */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) - { - /* Set status */ - module->status = STATUS_ERR_OVERFLOW; - /* Do not write more data */ - return; - } - - /* Find index to get next byte in buffer */ - uint16_t buffer_index = module->buffer_length; - buffer_index -= module->buffer_remaining; - - module->buffer_remaining--; - - /* Write byte from buffer to slave */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = module->buffer[buffer_index]; -} - -/** - * \internal - * Acts on slave address response. Checks for errors concerning master->slave - * handshake. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_async_address_response( - struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for error. Ignore bus-error; workaround for bus state stuck in - * BUSY. - */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) - { - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB; - - /* Check arbitration */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { - /* Return busy */ - module->status = STATUS_ERR_PACKET_COLLISION; - } - /* No slave responds */ - else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - module->status = STATUS_ERR_BAD_ADDRESS; - module->buffer_remaining = 0; - - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - } - - module->buffer_length = module->buffer_remaining; - - /* Check for status OK. */ - if (module->status == STATUS_BUSY) { - /* Call function based on transfer direction. */ - if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_master_write(module); - } else { - _i2c_master_read(module); - } - } -} - -/** - * \brief Registers callback for the specified callback type - * - * Associates the given callback function with the - * specified callback type. - * - * To enable the callback, the \ref i2c_master_enable_callback function - * must be used. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback Pointer to the function desired for the - * specified callback - * \param[in] callback_type Callback type to register - */ -void i2c_master_register_callback( - struct i2c_master_module *const module, - const i2c_master_callback_t callback, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(callback); - - /* Register callback */ - module->callbacks[callback_type] = callback; - - /* Set corresponding bit to set callback as registered */ - module->registered_callback |= (1 << callback_type); -} - -/** - * \brief Unregisters callback for the specified callback type - * - * When called, the currently registered callback for the given callback type - * will be removed. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Specifies the callback type to unregister - */ -void i2c_master_unregister_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Register callback */ - module->callbacks[callback_type] = NULL; - - /* Clear corresponding bit to set callback as unregistered */ - module->registered_callback &= ~(1 << callback_type); -} - -/** - * \internal - * Starts a read bytes operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_read_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_READ; - module->status = STATUS_BUSY; - module->send_stop = false; - module->send_nack = false; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - return STATUS_OK; -} - -/** - * \internal - * Starts a read packet operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -static enum status_code _i2c_master_read_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - enum status_code tmp_status; - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_READ; - module->status = STATUS_BUSY; - - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK or NACK. */ - if ((sclsm_flag) && (packet->data_length == 1)) { - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - } - - if (packet->ten_bit_address) { - /* - * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must - * be set and read/write bit (ADDR.ADDR[0]) equal to 0. - */ - i2c_module->ADDR.reg = (packet->address << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - if (tmp_status == STATUS_OK) { - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* - * Write ADDR[7:0] register to "11110 address[9:8] 1" - * ADDR.TENBITEN must be cleared - */ - i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - I2C_TRANSFER_READ; - } else { - return tmp_status; - } - } else { - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* Set address and direction bit. Will send start command on bus */ - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - - return STATUS_OK; -} - -/** - * \brief Initiates a read packet operation - * - * Reads a data packet from the specified slave address on the I2C - * bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_read_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we send STOP */ - module->send_stop = true; - module->send_nack = true; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Initiates a read packet operation without sending a STOP condition when done - * - * Reads a data packet from the specified slave address on the I2C bus without - * sending a stop condition, thus retaining ownership of the bus when done. - * To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another operation - */ -enum status_code i2c_master_read_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we don't send STOP */ - module->send_stop = false; - module->send_nack = true; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Initiates a read packet operation without sending a NACK signal and a - * STOP condition when done - * - * Reads a data packet from the specified slave address on the I2C bus without - * sending a nack and a stop condition, thus retaining ownership of the bus when done. - * To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another operation - */ -enum status_code i2c_master_read_packet_job_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we don't send STOP */ - module->send_stop = false; - module->send_nack = false; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts a write bytes operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting write I2C bytes. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_write_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_WRITE; - module->status = STATUS_BUSY; - module->send_stop = false; - module->send_nack = false; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - return STATUS_OK; -} - -/** - * \internal Initiates a write packet operation - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -static enum status_code _i2c_master_write_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Switch to high speed mode */ - if (packet->high_speed) { - _i2c_master_send_hs_master_code(module, packet->hs_master_code); - } - - /* Set action to ACK. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_WRITE; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* Set address and direction bit, will send start command on bus */ - if (packet->ten_bit_address) { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) | - SERCOM_I2CM_ADDR_TENBITEN; - } else { - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE | - (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos); - } - - return STATUS_OK; -} - -/** - * \brief Initiates a write packet operation - * - * Writes a data packet to the specified slave address on the I2C - * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_write_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with another job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we send STOP at end*/ - module->send_stop = true; - module->send_nack = true; - /* Start write operation */ - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Initiates a write packet operation without sending a STOP condition when done - * - * Writes a data packet to the specified slave address on the I2C bus - * without sending a stop condition, thus retaining ownership of the bus when - * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition or sending - * a stop with the \ref i2c_master_send_stop function must be performed. - * - * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another - */ -enum status_code i2c_master_write_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with another job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Do not send stop condition when done */ - module->send_stop = false; - module->send_nack = true; - /* Start write operation */ - return _i2c_master_write_packet(module, packet); -} - -/** - * \internal - * Interrupt handler for I2C master. - * - * \param[in] instance SERCOM instance that triggered the interrupt - */ -void _i2c_master_interrupt_handler( - uint8_t instance) -{ - /* Get software module for callback handling */ - struct i2c_master_module *module = - (struct i2c_master_module*)_sercom_instances[instance]; - - Assert(module); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM; - - /* Combine callback registered and enabled masks */ - uint8_t callback_mask = module->enabled_callback; - callback_mask &= module->registered_callback; - - /* Check if the module should respond to address ack */ - if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) { - /* Call function for address response */ - _i2c_master_async_address_response(module); - - /* Check if buffer write is done */ - } else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) && - (module->status == STATUS_BUSY) && - (module->transfer_direction == I2C_TRANSFER_WRITE)) { - /* Stop packet operation */ - i2c_module->INTENCLR.reg = - SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB; - - module->buffer_length = 0; - module->status = STATUS_OK; - - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } else { - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; - } - - if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) { - module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module); - } - - /* Continue buffer write/read */ - } else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){ - /* Check that bus ownership is not lost */ - if ((!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) && - (!(sclsm_flag && (module->buffer_remaining == 1)))) { - module->status = STATUS_ERR_PACKET_COLLISION; - } else if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_master_write(module); - } else { - _i2c_master_read(module); - } - } - - /* Check if read buffer transfer is complete */ - if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) && - (module->status == STATUS_BUSY) && - (module->transfer_direction == I2C_TRANSFER_READ)) { - - /* Clear read interrupt flag */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) { - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; - } - /* Stop packet operation */ - i2c_module->INTENCLR.reg = - SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB; - module->buffer_length = 0; - module->status = STATUS_OK; - - /* Call appropriate callback if enabled and registered */ - if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_READ)) { - module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module); - } else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_WRITE)) { - module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module); - } - } - - /* Check for error */ - if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) { - /* Stop packet operation */ - i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB | - SERCOM_I2CM_INTENCLR_SB; - - module->buffer_length = 0; - module->buffer_remaining = 0; - - /* Send nack and stop command unless arbitration is lost */ - if ((module->status != STATUS_ERR_PACKET_COLLISION) && - module->send_stop) { - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT | - SERCOM_I2CM_CTRLB_CMD(3); - } - - /* Call error callback if enabled and registered */ - if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) { - module->callbacks[I2C_MASTER_CALLBACK_ERROR](module); - } - } -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c deleted file mode 100644 index 1130877947813..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave.c +++ /dev/null @@ -1,745 +0,0 @@ -/** - * \file - * - * \brief SAM I2C Slave Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_slave.h" -#if I2C_SLAVE_CALLBACK_MODE == true -# include "i2c_slave_interrupt.h" -#endif - -/** - * \internal Sets configuration to module - * - * \param[out] module Pointer to software module structure - * \param[in] config Configuration structure with configurations to set - * - * \return Status of setting configuration. - * \retval STATUS_OK Module was configured correctly - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - */ -static enum status_code _i2c_slave_set_config( - struct i2c_slave_module *const module, - const struct i2c_slave_config *const config) -{ - uint32_t tmp_ctrla; - - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(config); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - Sercom *const sercom_hw = module->hw; - - module->buffer_timeout = config->buffer_timeout; - module->ten_bit_address = config->ten_bit_address; - - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; - - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - - /* Prepare config to write to register CTRLA */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } - - /* Check and set SCL clock stretch mode. */ - if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_SLAVE_SPEED_HIGH_SPEED)) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM; - } - - tmp_ctrla |= ((uint32_t)config->sda_hold_time | - config->transfer_speed | - (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) | - (config->slave_scl_low_extend_timeout << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos)); - - i2c_hw->CTRLA.reg |= tmp_ctrla; - - /* Set CTRLB configuration */ - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode; - - i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos | - config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos | - config->ten_bit_address << SERCOM_I2CS_ADDR_TENBITEN_Pos | - config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos; - - return STATUS_OK; -} - -/** - * \brief Initializes the requested I2C hardware module - * - * Initializes the SERCOM I2C slave device requested and sets the provided - * software module struct. Run this function before any further use of - * the driver. - * - * \param[out] module Pointer to software module struct - * \param[in] hw Pointer to the hardware instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - */ -enum status_code i2c_slave_init( - struct i2c_slave_module *const module, - Sercom *const hw, - const struct i2c_slave_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize software module */ - module->hw = hw; - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Check if module is enabled */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) { - return STATUS_BUSY; - } - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index, gclk_index; -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) -#if (SAML21) || (SAMR30) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - /* Turn on module in PM */ -#if (SAML21) || (SAMR30) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Get sercom instance index */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - - /* Save software module in interrupt handler */ - _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler); - - /* Save software module */ - _sercom_instances[instance_index] = module; - - /* Initialize values in module */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->nack_on_address = config->enable_nack_on_address; -#endif - - /* Set SERCOM module to operate in I2C slave mode */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x4); - - /* Set config and return status */ - return _i2c_slave_set_config(module, config); -} - -/** - * \brief Resets the hardware module - * - * This will reset the module to hardware defaults. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_slave_reset( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Reset module instance */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; - module->buffer = NULL; -#endif - - /* Disable module */ - i2c_slave_disable(module); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Clear all pending interrupts */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); -#endif - - /* Wait for sync */ - _i2c_slave_wait_for_sync(module); - - /* Reset module */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST; -} - -/** - * \internal Waits for answer on bus - * - * \param[in] module Pointer to software module structure - * - * \return Status of bus. - * \retval STATUS_OK If given response from slave device - * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout - * period - */ -static enum status_code _i2c_slave_wait_for_bus( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for reply */ - uint16_t timeout_counter = 0; - while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) { - - /* Check timeout condition */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; -} - -/** - * \brief Writes a packet to the master - * - * Writes a packet to the master. This will wait for the master to issue - * a request. - * - * \param[in] module Pointer to software module structure - * \param[in] packet Packet to write to master - * - * \return Status of packet write. - * \retval STATUS_OK Packet was written successfully - * \retval STATUS_ERR_DENIED Start condition not received, another - * interrupt flag is set - * \retval STATUS_ERR_IO There was an error in the previous transfer - * \retval STATUS_ERR_BAD_FORMAT Master wants to write data - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided - * \retval STATUS_ERR_BUSY The I2C module is busy with a job - * \retval STATUS_ERR_ERR_OVERFLOW Master NACKed before entire packet was - * transferred - * \retval STATUS_ERR_TIMEOUT No response was given within the timeout - * period - */ -enum status_code i2c_slave_write_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint16_t length = packet->data_length; - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } -#endif - - enum status_code status; - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - - if (module->ten_bit_address) { - /* ACK the first address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - - /* Wait for address interrupt */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return STATUS_ERR_TIMEOUT; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - } - - /* Check if there was an error in last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } - - /* Check direction */ - if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Write request from master, send NACK and return */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - return STATUS_ERR_BAD_FORMAT; - } - - /* Read request from master, ACK address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - - uint16_t i = 0; - - /* Wait for data interrupt */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - while (length--) { - /* Write data */ - _i2c_slave_wait_for_sync(module); - i2c_hw->DATA.reg = packet->data[i++]; - - /* Wait for response from master */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK && - length !=0) { - /* NACK from master, abort */ - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - - return STATUS_ERR_OVERFLOW; - } - /* ACK from master, continue writing */ - } - - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - - return STATUS_OK; -} - -/** - * \brief Reads a packet from the master - * - * Reads a packet from the master. This will wait for the master to issue a - * request. - * - * \param[in] module Pointer to software module structure - * \param[out] packet Packet to read from master - * - * \return Status of packet read. - * \retval STATUS_OK Packet was read successfully - * \retval STATUS_ABORTED Master sent stop condition or repeated - * start before specified length of bytes - * was received - * \retval STATUS_ERR_IO There was an error in the previous transfer - * \retval STATUS_ERR_DENIED Start condition not received, another - * interrupt flag is set - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided - * \retval STATUS_ERR_BUSY The I2C module is busy with a job - * \retval STATUS_ERR_BAD_FORMAT Master wants to read data - * \retval STATUS_ERR_ERR_OVERFLOW Last byte received overflows buffer - */ -enum status_code i2c_slave_read_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint16_t length = packet->data_length; - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } -#endif - - enum status_code status; - - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - - /* Check if there was an error in the last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master, send NACK and return */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - return STATUS_ERR_BAD_FORMAT; - } - - /* Write request from master, ACK address */ - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3); - - uint16_t i = 0; - while (length--) { - - /* Wait for next byte or stop condition */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) || - i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Master sent stop condition, or repeated start, read done */ - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - return STATUS_ABORTED; - } - - /* Read data */ - _i2c_slave_wait_for_sync(module); - packet->data[i++] = i2c_hw->DATA.reg; - - } - - /* Packet read done, wait for packet to NACK, Stop or repeated start */ - status = _i2c_slave_wait_for_bus(module); - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) { - /* Buffer is full, send NACK */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - } - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - return STATUS_OK; -} - -/** - * \brief Waits for a start condition on the bus - * - * \note This function is only available for 7-bit slave addressing. - * - * Waits for the master to issue a start condition on the bus. - * - * \note This function does not check for errors in the last transfer, - * this will be discovered when reading or writing. - * - * \param[in] module Pointer to software module structure - * - * \return Direction of the current transfer, when in slave mode. - * \retval I2C_SLAVE_DIRECTION_NONE No request from master within timeout - * period - * \retval I2C_SLAVE_DIRECTION_READ Write request from master - * \retval I2C_SLAVE_DIRECTION_WRITE Read request from master - */ -enum i2c_slave_direction i2c_slave_get_direction_wait( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - enum status_code status; - - /* Wait for address interrupt */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return I2C_SLAVE_DIRECTION_NONE; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return I2C_SLAVE_DIRECTION_NONE; - } - - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master */ - return I2C_SLAVE_DIRECTION_WRITE; - } else { - /* Write request from master */ - return I2C_SLAVE_DIRECTION_READ; - } -} - -/** - * \brief Retrieves the current module status - * - * Checks the status of the module and returns it as a bitmask of status - * flags. - * - * \param[in] module Pointer to the I2C slave software device struct - * - * \return Bitmask of status flags. - * - * \retval I2C_SLAVE_STATUS_ADDRESS_MATCH A valid address has been received - * \retval I2C_SLAVE_STATUS_DATA_READY A I2C slave byte transmission is - * successfully completed - * \retval I2C_SLAVE_STATUS_STOP_RECEIVED A stop condition is detected for a - * transaction being processed - * \retval I2C_SLAVE_STATUS_CLOCK_HOLD The slave is holding the SCL line - * low - * \retval I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT An SCL low time-out has occurred - * \retval I2C_SLAVE_STATUS_REPEATED_START Indicates a repeated start, only - * valid if \ref - * I2C_SLAVE_STATUS_ADDRESS_MATCH is - * set - * \retval I2C_SLAVE_STATUS_RECEIVED_NACK The last data packet sent was not - * acknowledged - * \retval I2C_SLAVE_STATUS_COLLISION The I2C slave was not able to - * transmit a high data or NACK bit - * \retval I2C_SLAVE_STATUS_BUS_ERROR An illegal bus condition has - * occurred on the bus - */ -uint32_t i2c_slave_get_status( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint8_t intflags = i2c_hw->INTFLAG.reg; - uint8_t status = i2c_hw->STATUS.reg; - uint32_t status_flags = 0; - - /* Check Address Match flag */ - if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) { - status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH; - } - /* Check Data Ready flag */ - if (intflags & SERCOM_I2CS_INTFLAG_DRDY) { - status_flags |= I2C_SLAVE_STATUS_DATA_READY; - } - /* Check Stop flag */ - if (intflags & SERCOM_I2CS_INTFLAG_PREC) { - status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED; - } - /* Check Clock Hold */ - if (status & SERCOM_I2CS_STATUS_CLKHOLD) { - status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD; - } - /* Check SCL Low Timeout */ - if (status & SERCOM_I2CS_STATUS_LOWTOUT) { - status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT; - } - /* Check Repeated Start */ - if (status & SERCOM_I2CS_STATUS_SR) { - status_flags |= I2C_SLAVE_STATUS_REPEATED_START; - } - /* Check Received Not Acknowledge */ - if (status & SERCOM_I2CS_STATUS_RXNACK) { - status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK; - } - /* Check Transmit Collision */ - if (status & SERCOM_I2CS_STATUS_COLL) { - status_flags |= I2C_SLAVE_STATUS_COLLISION; - } - /* Check Bus Error */ - if (status & SERCOM_I2CS_STATUS_BUSERR) { - status_flags |= I2C_SLAVE_STATUS_BUS_ERROR; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag - * - * Clears the given status flag of the module. - * - * \note Not all status flags can be cleared. - * - * \param[in] module Pointer to the I2C software device struct - * \param[in] status_flags Bit mask of status flags to clear - * - */ -void i2c_slave_clear_status( - struct i2c_slave_module *const module, - uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Clear Address Match flag */ - if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - /* Clear Data Ready flag */ - if (status_flags & I2C_SLAVE_STATUS_DATA_READY) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; - } - /* Clear Stop flag */ - if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - /* Clear SCL Low Timeout */ - if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - } - /* Clear Transmit Collision */ - if (status_flags & I2C_SLAVE_STATUS_COLLISION) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL; - } - /* Clear Bus Error */ - if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - } -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c deleted file mode 100644 index 0a6f234f8b834..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_sam0/i2c_slave_interrupt.c +++ /dev/null @@ -1,434 +0,0 @@ -/** - * \file - * - * \brief SAM I2C Slave Interrupt Driver - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_slave_interrupt.h" - -/** - * \brief Enables sending of NACK on address match - * - * Enables sending of NACK on address match, thus discarding - * any incoming transaction. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_slave_enable_nack_on_address( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - - module->nack_on_address = true; -} - -/** - * \brief Disables sending NACK on address match - * - * Disables sending of NACK on address match, thus - * acknowledging incoming transactions. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_slave_disable_nack_on_address( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - - module->nack_on_address = false; -} - -/** - * \internal - * Reads next data. Used by interrupt handler to get next data byte from master. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_slave_read( - struct i2c_slave_module *const module) -{ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Read byte from master and put in buffer. */ - *(module->buffer++) = i2c_hw->DATA.reg; - - /*Decrement remaining buffer length */ - module->buffer_remaining--; -} - -/** - * \internal - * Writes next data. Used by interrupt handler to send next data byte to master. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_slave_write( - struct i2c_slave_module *const module) -{ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Write byte from buffer to master */ - i2c_hw->DATA.reg = *(module->buffer++); - - /*Decrement remaining buffer length */ - module->buffer_remaining--; -} - -/** - * \brief Registers callback for the specified callback type - * - * Associates the given callback function with the - * specified callback type. To enable the callback, the - * \ref i2c_slave_enable_callback function must be used. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback Pointer to the function desired for the - * specified callback - * \param[in] callback_type Callback type to register - */ -void i2c_slave_register_callback( - struct i2c_slave_module *const module, - i2c_slave_callback_t callback, - enum i2c_slave_callback callback_type) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - Assert(callback); - - /* Register callback. */ - module->callbacks[callback_type] = callback; - - /* Set corresponding bit to set callback as initiated. */ - module->registered_callback |= (1 << callback_type); -} - -/** - * \brief Unregisters callback for the specified callback type - * - * Removes the currently registered callback for the given callback - * type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to unregister - */ -void i2c_slave_unregister_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - /* Register callback. */ - module->callbacks[callback_type] = NULL; - - /* Set corresponding bit to set callback as initiated. */ - module->registered_callback &= ~(1 << callback_type); -} - -/** - * \brief Initiates a reads packet operation - * - * Reads a data packet from the master. A write request must be initiated by - * the master before the packet can be read. - * - * The \ref I2C_SLAVE_CALLBACK_WRITE_REQUEST callback can be used to call this - * function. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting asynchronously reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_slave_read_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy doing async operation. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Save packet to software module. */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->buffer_length = packet->data_length; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH | - SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC; - - /* Read will begin when master initiates the transfer */ - return STATUS_OK; -} - -/** - * \brief Initiates a write packet operation - * - * Writes a data packet to the master. A read request must be initiated by - * the master before the packet can be written. - * - * The \ref I2C_SLAVE_CALLBACK_READ_REQUEST callback can be used to call this - * function. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_slave_write_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy doing async operation. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Save packet to software module. */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->buffer_length = packet->data_length; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH | - SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC; - - return STATUS_OK; -} - -/** - * \internal Interrupt handler for I2C slave - * - * \param[in] instance Sercom instance that triggered the interrupt - */ -void _i2c_slave_interrupt_handler( - uint8_t instance) -{ - /* Get software module for callback handling. */ - struct i2c_slave_module *module = - (struct i2c_slave_module*)_sercom_instances[instance]; - - Assert(module); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Combine callback registered and enabled masks. */ - uint8_t callback_mask = module->enabled_callback; - callback_mask &= module->registered_callback; - - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Address match */ - /* Check if last transfer is done - repeated start */ - if (module->buffer_length != module->buffer_remaining && - module->transfer_direction == I2C_TRANSFER_WRITE) { - - module->status = STATUS_OK; - module->buffer_length = 0; - module->buffer_remaining = 0; - - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))) { - module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module); - } - } else if (module->buffer_length != module->buffer_remaining && - module->transfer_direction == I2C_TRANSFER_READ) { - module->status = STATUS_OK; - module->buffer_length = 0; - module->buffer_remaining = 0; - - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))) { - module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module); - } - } - - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - /* An error occurred in last packet transfer */ - module->status = STATUS_ERR_IO; - - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER))) { - module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module); - } - } - if (module->nack_on_address) { - /* NACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, false); - } else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR) { - /* Set transfer direction in module instance */ - module->transfer_direction = I2C_TRANSFER_READ; - - /* Read request from master */ - if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) { - module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module); - } - - if (module->buffer_length == 0) { - /* Data buffer not set up, NACK address, workaround 13574*/ - _i2c_slave_set_ctrlb_ackact(module, false); - } else { - /* ACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - } - } else { - /* Set transfer direction in dev inst */ - module->transfer_direction = I2C_TRANSFER_WRITE; - - /* Write request from master */ - if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) { - module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module); - } - - if (module->buffer_length == 0) { - /* Data buffer not set up, NACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, false); - } else { - /* ACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - } - } - - /* ACK or NACK address, Workaround 13574 */ - _i2c_slave_set_ctrlb_cmd3(module); - - /* ACK next incoming packet, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - - } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { - /* Stop condition on bus - current transfer done */ - - /* Clear Stop interrupt */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - - /* Disable interrupts */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY; - - if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) - || (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)))) { - /* Disable address match if read/write request is not enabled */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - - if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO)) { - module->status = STATUS_OK; - module->buffer_length = 0; - module->buffer_remaining = 0; - - /* Call appropriate callback if enabled and registered */ - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_WRITE)) { - /* Read from master complete */ - module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module); - } else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_READ)) { - /* Write to master complete */ - module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module); - } - } - } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) { - /* Check if buffer is full, or NACK from master */ - if (module->buffer_remaining <= 0 || - (module->transfer_direction == I2C_TRANSFER_READ && - (module->buffer_length > module->buffer_remaining) && - (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK))) { - - module->buffer_remaining = 0; - module->buffer_length = 0; - - if (module->transfer_direction == I2C_TRANSFER_WRITE) { - /* Buffer is full, send NACK, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, false); - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - - /* Set status, new character in DATA register will overflow - * buffer */ - module->status = STATUS_ERR_OVERFLOW; - - if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR)) { - /* Read complete */ - module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module); - } - } else { - /* Release SCL and wait for new start condition */ - _i2c_slave_set_ctrlb_ackact(module, false); - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - - /* Transfer successful */ - module->status = STATUS_OK; - - /* Disable interrupts */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY; - } - - /* Continue buffer write/read */ - } else if (module->buffer_length > 0 && module->buffer_remaining > 0) { - /* Call function based on transfer direction */ - if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_slave_read(module); - } else { - _i2c_slave_write(module); - } - } - } -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c deleted file mode 100644 index ce4f58c2303ce..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master.c +++ /dev/null @@ -1,881 +0,0 @@ -/** - * \file - * - * \brief SAM D20 I2C Master Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_master.h" - -#if I2C_MASTER_CALLBACK_MODE == true -# include "i2c_master_interrupt.h" -#endif - -#if !defined(__DOXYGEN__) - -/** - * \internal Sets configurations to module - * - * \param[out] module Pointer to software module structure - * \param[in] config Configuration structure with configurations to set - * - * \return Status of setting configuration. - * \retval STATUS_OK If module was configured correctly - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baud rate is not compatible - * with set GCLK frequency - */ -static enum status_code _i2c_master_set_config( - struct i2c_master_module *const module, - const struct i2c_master_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(config); - - /* Temporary variables. */ - uint32_t tmp_ctrla; - int32_t tmp_baud; - enum status_code tmp_status_code = STATUS_OK; - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - Sercom *const sercom_hw = module->hw; - - uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw); - - /* Pin configuration */ - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; - - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - - /* Save timeout on unknown bus state in software module. */ - module->unknown_bus_state_timeout = config->unknown_bus_state_timeout; - - /* Save timeout on buffer write. */ - module->buffer_timeout = config->buffer_timeout; - - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } - - /* Check and set start data hold timeout. */ - if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) { - tmp_ctrla |= config->start_hold_time; - } - - /* Check and set SCL low timeout. */ - if (config->scl_low_timeout) { - tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUT; - } - - /* Check and set inactive bus timeout. */ - if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) { - tmp_ctrla |= config->inactive_timeout; - } - - /* Write config to register CTRLA. */ - i2c_module->CTRLA.reg |= tmp_ctrla; - - /* Set configurations in CTRLB. */ - i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN; - - /* Find and set baudrate. */ - tmp_baud = (int32_t)(div_ceil( - system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index), - (2000*(config->baud_rate))) - 5); - - /* Check that baud rate is supported at current speed. */ - if (tmp_baud > 255 || tmp_baud < 0) { - /* Baud rate not supported. */ - tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE; - } else { - /* Baud rate acceptable. */ - i2c_module->BAUD.reg = (uint8_t)tmp_baud; - } - - return tmp_status_code; -} -#endif /* __DOXYGEN__ */ - -/** - * \brief Initializes the requested I2C hardware module - * - * Initializes the SERCOM I2C master device requested and sets the provided - * software module struct. Run this function before any further use of - * the driver. - * - * \param[out] module Pointer to software module struct - * \param[in] hw Pointer to the hardware instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible - * with set GCLK frequency - * - */ -enum status_code i2c_master_init( - struct i2c_master_module *const module, - Sercom *const hw, - const struct i2c_master_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize software module */ - module->hw = hw; - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - - /* Turn on module in PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - - /* Check if module is enabled. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) { - return STATUS_BUSY; - } - -#if I2C_MASTER_CALLBACK_MODE == true - /* Get sercom instance index and register callback. */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _i2c_master_interrupt_handler); - _sercom_instances[instance_index] = module; - - /* Initialize values in module. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; - - module->status = STATUS_OK; - module->buffer = NULL; -#endif - - /* Set sercom module to operate in I2C master mode. */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE_I2C_MASTER; - - /* Set config and return status. */ - return _i2c_master_set_config(module, config); -} - -/** - * \brief Resets the hardware module - * - * Reset the module to hardware defaults. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_master_reset(struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for sync */ - _i2c_master_wait_for_sync(module); - - /* Disable module */ - i2c_master_disable(module); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Clear all pending interrupts */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); -#endif - - /* Wait for sync */ - _i2c_master_wait_for_sync(module); - - /* Reset module */ - i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST; -} - -#if !defined(__DOXYGEN__) -/** - * \internal - * Address response. Called when address is answered or timed out. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of address response. - * \retval STATUS_OK No error has occurred - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -static enum status_code _i2c_master_address_response( - struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in - * BUSY */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) { - - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; - - /* Check arbitration. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { - /* Return packet collision. */ - return STATUS_ERR_PACKET_COLLISION; - } - /* Check that slave responded with ack. */ - } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Slave busy. Issue ack and stop command. */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - - /* Return bad address value. */ - return STATUS_ERR_BAD_ADDRESS; - } - - return STATUS_OK; -} - -/** - * \internal - * Waits for answer on bus. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of bus. - * \retval STATUS_OK If given response from slave device - * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout - * period - */ -static enum status_code _i2c_master_wait_for_bus( - struct i2c_master_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) && - !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) { - - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; -} -#endif /* __DOXYGEN__ */ - -/** - * \internal - * Starts blocking read operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * - */ -static enum status_code _i2c_master_read_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; - - /* Written buffer counter. */ - uint16_t counter = 0; - - /* Set address and direction bit. Will send start command on bus. */ - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ; - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Set action to ack. */ - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Read data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } - - if (module->send_nack && tmp_data_length == 0) { - /* Set action to NACK */ - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - } else { - /* Save data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter++] = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - } - - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } - } - - if (module->send_stop) { - /* Send stop command unless arbitration is lost. */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } else { - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1); - } - - /* Save last data to buffer. */ - _i2c_master_wait_for_sync(module); - packet->data[counter] = i2c_module->DATA.reg; - } - - return tmp_status; -} - -/** - * \brief Reads data packet from slave - * - * Reads a data packet from the specified slave address on the I2C - * bus and sends a stop condition when finished. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = true; - module->send_nack = true; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Reads data packet from slave without sending a stop condition when done - * - * Reads a data packet from the specified slave address on the I2C - * bus without sending a stop condition when done, thus retaining ownership of - * the bus when done. To end the transaction, a - * \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = true; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts blocking read operation. - * \brief Reads data packet from slave without sending a nack signal and a stop - * condition when done - * - * Reads a data packet from the specified slave address on the I2C - * bus without sending a nack signal and a stop condition when done, - * thus retaining ownership of the bus when done. To end the transaction, a - * \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of reading packet. - * \retval STATUS_OK The packet was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_packet_wait_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = false; - - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts blocking write operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK The packet was write successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -static enum status_code _i2c_master_write_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Return value. */ - enum status_code tmp_status; - uint16_t tmp_data_length = packet->data_length; - - _i2c_master_wait_for_sync(module); - - /* Set address and direction bit. Will send start command on bus. */ - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE; - - /* Wait for response on bus. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Check for address response error unless previous error is - * detected. */ - if (tmp_status == STATUS_OK) { - tmp_status = _i2c_master_address_response(module); - } - - /* Check that no error has occurred. */ - if (tmp_status == STATUS_OK) { - /* Buffer counter. */ - uint16_t buffer_counter = 0; - - /* Write data buffer. */ - while (tmp_data_length--) { - /* Check that bus ownership is not lost. */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - return STATUS_ERR_PACKET_COLLISION; - } - - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = packet->data[buffer_counter++]; - - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - - /* Check for error. */ - if (tmp_status != STATUS_OK) { - break; - } - - /* Check for NACK from slave. */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Return bad data value. */ - tmp_status = STATUS_ERR_OVERFLOW; - break; - } - } - - if (module->send_stop) { - /* Stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - - return tmp_status; -} - -/** - * \brief Writes data packet to slave - * - * Writes a data packet to the specified slave address on the I2C bus - * and sends a stop condition when finished. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK If packet was write successfully - * \retval STATUS_BUSY If master module is busy with a job - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave does not - * want more data and was not able to read - * last data sent - */ -enum status_code i2c_master_write_packet_wait( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = true; - module->send_nack = true; - - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Writes data packet to slave without sending a stop condition when done - * - * Writes a data packet to the specified slave address on the I2C bus - * without sending a stop condition, thus retaining ownership of the bus when - * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition or sending a - * stop with the \ref i2c_master_send_stop function must be performed. - * - * \note This will stall the device from any other operation. For - * interrupt-driven operation, see \ref i2c_master_read_packet_job. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of write packet. - * \retval STATUS_OK If packet was write successfully - * \retval STATUS_BUSY If master module is busy - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - * \retval STATUS_ERR_TIMEOUT If timeout occurred - * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent - * data, indicating that slave do not want - * more data - */ -enum status_code i2c_master_write_packet_wait_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - -#if I2C_MASTER_CALLBACK_MODE == true - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } -#endif - - module->send_stop = false; - module->send_nack = true; - - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Sends stop condition on bus - * - * Sends a stop condition on bus. - * - * \note This function can only be used after the - * \ref i2c_master_write_packet_wait_no_stop function. If a stop condition - * is to be sent after a read, the \ref i2c_master_read_packet_wait - * function must be used. - * - * \param[in,out] module Pointer to the software instance struct - */ -void i2c_master_send_stop(struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Send stop command */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); -} - -/** - * \brief Sends nack signal on bus - * - * Sends a nack signal on bus. - * - * \note This function can only be used after the - * \ref i2c_master_write_packet_wait_no_nack function, - * or \ref i2c_master_read_byte function. - * \param[in,out] module Pointer to the software instance struct - */ -void i2c_master_send_nack(struct i2c_master_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Send nack signal */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; -} - -/** - * \brief Reads one byte data from slave - * - * \param[in,out] module Pointer to software module struct - * \param[out] byte Read one byte data to slave - * - * \return Status of reading byte. - * \retval STATUS_OK One byte was read successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_read_byte( - struct i2c_master_module *const module, - uint8_t *byte) -{ - enum status_code tmp_status; - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - *byte = i2c_module->DATA.reg; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - - return tmp_status; -} - -/** - * \brief Write one byte data to slave - * - * \param[in,out] module Pointer to software module struct - * \param[in] byte Send one byte data to slave - * - * \return Status of writing byte. - * \retval STATUS_OK One byte was write successfully - * \retval STATUS_ERR_TIMEOUT If no response was given within - * specified timeout period - * \retval STATUS_ERR_DENIED If error on bus - * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost - * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave - * acknowledged the address - */ -enum status_code i2c_master_write_byte( - struct i2c_master_module *const module, - uint8_t byte) -{ - enum status_code tmp_status; - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Write byte to slave. */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = byte; - /* Wait for response. */ - tmp_status = _i2c_master_wait_for_bus(module); - return tmp_status; -} \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c deleted file mode 100644 index 07c892a036b9a..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_master_interrupt.c +++ /dev/null @@ -1,670 +0,0 @@ -/** - * \file - * - * \brief SAM D20 I2C Master Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_master_interrupt.h" - -/** - * \internal - * Read next data. Used by interrupt handler to get next data byte from slave. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_read( - struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Find index to save next value in buffer */ - uint16_t buffer_index = module->buffer_length - module->buffer_remaining; - - module->buffer_remaining--; - - if (!module->buffer_remaining) { - /* Send nack */ - if (module->send_nack) - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } else { - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(1); - } - } else { - i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - } - - /* Read byte from slave and put in buffer */ - _i2c_master_wait_for_sync(module); - module->buffer[buffer_index] = i2c_module->DATA.reg; -} - -/** - * \internal - * - * Write next data. Used by interrupt handler to send next data byte to slave. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_write(struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for ack from slave */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) - { - /* Set status */ - module->status = STATUS_ERR_OVERFLOW; - /* Do not write more data */ - return; - } - - /* Find index to get next byte in buffer */ - uint16_t buffer_index = module->buffer_length - module->buffer_remaining; - - module->buffer_remaining--; - - /* Write byte from buffer to slave */ - _i2c_master_wait_for_sync(module); - i2c_module->DATA.reg = module->buffer[buffer_index]; -} - -/** - * \internal - * Acts on slave address response. Checks for errors concerning master->slave - * handshake. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_master_async_address_response( - struct i2c_master_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Check for error. Ignore bus-error; workaround for bus state stuck in - * BUSY. - */ - if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) - { - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB; - - /* Check arbitration */ - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) { - /* Return busy */ - module->status = STATUS_ERR_PACKET_COLLISION; - } - } - - if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) { - /* Return bad address value */ - module->status = STATUS_ERR_BAD_ADDRESS; - module->buffer_remaining = 0; - - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } - } - - module->buffer_length = module->buffer_remaining; - - /* Check for status OK. */ - if (module->status == STATUS_BUSY) { - /* Call function based on transfer direction. */ - if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_master_write(module); - } else { - _i2c_master_read(module); - } - } -} - -/** - * \brief Registers callback for the specified callback type - * - * Associates the given callback function with the - * specified callback type. - * - * To enable the callback, the \ref i2c_master_enable_callback function - * must be used. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback Pointer to the function desired for the - * specified callback - * \param[in] callback_type Callback type to register - */ -void i2c_master_register_callback( - struct i2c_master_module *const module, - const i2c_master_callback_t callback, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(callback); - - /* Register callback */ - module->callbacks[callback_type] = callback; - - /* Set corresponding bit to set callback as registered */ - module->registered_callback |= (1 << callback_type); -} - -/** - * \brief Unregisters callback for the specified callback type - * - * When called, the currently registered callback for the given callback type - * will be removed. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Specifies the callback type to unregister - */ -void i2c_master_unregister_callback( - struct i2c_master_module *const module, - enum i2c_master_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Register callback */ - module->callbacks[callback_type] = NULL; - - /* Clear corresponding bit to set callback as unregistered */ - module->registered_callback &= ~(1 << callback_type); -} - -/** - * \internal - * Starts a read bytes operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_read_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_READ; - module->status = STATUS_BUSY; - module->send_stop = false; - module->send_nack = false; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - return STATUS_OK; -} - -/** - * \internal - * Starts a read packet operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -static enum status_code _i2c_master_read_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_READ; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* Set address and direction bit. Will send start command on bus */ - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ; - - return STATUS_OK; -} - -/** - * \brief Initiates a read packet operation - * - * Reads a data packet from the specified slave address on the I2C - * bus. This is the non-blocking equivalent of \ref i2c_master_read_packet_wait. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_read_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we send STOP */ - module->send_stop = true; - module->send_nack = true; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Initiates a read packet operation without sending a STOP condition when done - * - * Reads a data packet from the specified slave address on the I2C bus without - * sending a stop condition, thus retaining ownership of the bus when done. - * To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another operation - */ -enum status_code i2c_master_read_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we don't send STOP */ - module->send_stop = false; - module->send_nack = true; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \brief Initiates a read packet operation without sending a NACK signal and a - * STOP condition when done - * - * Reads a data packet from the specified slave address on the I2C bus without - * sending a nack and a stop condition, thus retaining ownership of the bus when done. - * To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition must be - * performed. - * - * This is the non-blocking equivalent of \ref i2c_master_read_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another operation - */ -enum status_code i2c_master_read_packet_job_no_nack( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with a job */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we don't send STOP */ - module->send_stop = false; - module->send_nack = false; - /* Start reading */ - return _i2c_master_read_packet(module, packet); -} - -/** - * \internal - * Starts a write bytes operation. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting write I2C bytes. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_write_bytes( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_WRITE; - module->status = STATUS_BUSY; - module->send_stop = false; - module->send_nack = false; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - return STATUS_OK; -} - -/** - * \internal Initiates a write packet operation - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -static enum status_code _i2c_master_write_packet( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Save packet to software module */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->transfer_direction = I2C_TRANSFER_WRITE; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - i2c_module->INTENSET.reg = - SERCOM_I2CM_INTENSET_MB | SERCOM_I2CM_INTENSET_SB; - - /* Set address and direction bit, will send start command on bus */ - i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE; - - return STATUS_OK; -} - -/** - * \brief Initiates a write packet operation - * - * Writes a data packet to the specified slave address on the I2C - * bus. This is the non-blocking equivalent of \ref i2c_master_write_packet_wait. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_master_write_packet_job( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with another job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Make sure we send STOP at end*/ - module->send_stop = true; - module->send_nack = true; - /* Start write operation */ - return _i2c_master_write_packet(module, packet); -} - -/** - * \brief Initiates a write packet operation without sending a STOP condition when done - * - * Writes a data packet to the specified slave address on the I2C bus - * without sending a stop condition, thus retaining ownership of the bus when - * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or - * \ref i2c_master_write_packet_wait "write" with stop condition or sending - * a stop with the \ref i2c_master_send_stop function must be performed. - * - * This is the non-blocking equivalent of \ref i2c_master_write_packet_wait_no_stop. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet job. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another - */ -enum status_code i2c_master_write_packet_job_no_stop( - struct i2c_master_module *const module, - struct i2c_master_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy with another job. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Do not send stop condition when done */ - module->send_stop = false; - module->send_nack = true; - /* Start write operation */ - return _i2c_master_write_packet(module, packet); -} - -/** - * \internal - * Interrupt handler for I2C master. - * - * \param[in] instance SERCOM instance that triggered the interrupt - */ -void _i2c_master_interrupt_handler( - uint8_t instance) -{ - /* Get software module for callback handling */ - struct i2c_master_module *module = - (struct i2c_master_module*)_sercom_instances[instance]; - - Assert(module); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Combine callback registered and enabled masks */ - uint8_t callback_mask = module->enabled_callback & - module->registered_callback; - - /* Check if the module should respond to address ack */ - if ((module->buffer_length <= 0) && (module->buffer_remaining > 0)) { - /* Call function for address response */ - _i2c_master_async_address_response(module); - - /* Check if buffer write is done */ - } else if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) && - (module->status == STATUS_BUSY) && - (module->transfer_direction == I2C_TRANSFER_WRITE)) { - /* Stop packet operation */ - i2c_module->INTENCLR.reg = - SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB; - - module->buffer_length = 0; - module->status = STATUS_OK; - - if (module->send_stop) { - /* Send stop condition */ - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3); - } else { - /* Clear write interrupt flag */ - i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; - } - if (callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) { - module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module); - } - - /* Continue buffer write/read */ - } else if ((module->buffer_length > 0) && (module->buffer_remaining > 0)){ - /* Check that bus ownership is not lost */ - if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) { - module->status = STATUS_ERR_PACKET_COLLISION; - } else if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_master_write(module); - } else { - _i2c_master_read(module); - } - } - - /* Check if read buffer transfer is complete */ - if ((module->buffer_length > 0) && (module->buffer_remaining <= 0) && - (module->status == STATUS_BUSY) && - (module->transfer_direction == I2C_TRANSFER_READ)) { - - /* Stop packet operation */ - i2c_module->INTENCLR.reg = - SERCOM_I2CM_INTENCLR_MB | SERCOM_I2CM_INTENCLR_SB; - module->buffer_length = 0; - module->status = STATUS_OK; - - /* Call appropriate callback if enabled and registered */ - if ((callback_mask & (1 << I2C_MASTER_CALLBACK_READ_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_READ)) { - module->callbacks[I2C_MASTER_CALLBACK_READ_COMPLETE](module); - } else if ((callback_mask & (1 << I2C_MASTER_CALLBACK_WRITE_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_WRITE)) { - module->callbacks[I2C_MASTER_CALLBACK_WRITE_COMPLETE](module); - } - } - - /* Check for error */ - if ((module->status != STATUS_BUSY) && (module->status != STATUS_OK)) { - /* Stop packet operation */ - i2c_module->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MB | - SERCOM_I2CM_INTENCLR_SB; - - module->buffer_length = 0; - module->buffer_remaining = 0; - - /* Send nack and stop command unless arbitration is lost */ - if ((module->status != STATUS_ERR_PACKET_COLLISION) && - module->send_stop) { - _i2c_master_wait_for_sync(module); - i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT | - SERCOM_I2CM_CTRLB_CMD(3); - } - - /* Call error callback if enabled and registered */ - if (callback_mask & (1 << I2C_MASTER_CALLBACK_ERROR)) { - module->callbacks[I2C_MASTER_CALLBACK_ERROR](module); - } - } -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c deleted file mode 100644 index c403479a386ee..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave.c +++ /dev/null @@ -1,693 +0,0 @@ -/** - * \file - * - * \brief SAM D20 I2C Slave Driver - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_slave.h" -#if I2C_SLAVE_CALLBACK_MODE == true -# include "i2c_slave_interrupt.h" -#endif - -/** - * \internal Sets configuration to module - * - * \param[out] module Pointer to software module structure - * \param[in] config Configuration structure with configurations to set - * - * \return Status of setting configuration. - * \retval STATUS_OK Module was configured correctly - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - */ -static enum status_code _i2c_slave_set_config( - struct i2c_slave_module *const module, - const struct i2c_slave_config *const config) -{ - uint32_t tmp_ctrla; - - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(config); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - Sercom *const sercom_hw = module->hw; - - module->buffer_timeout = config->buffer_timeout; - - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - - uint32_t pad0 = config->pinmux_pad0; - uint32_t pad1 = config->pinmux_pad1; - - /* SERCOM PAD0 - SDA */ - if (pad0 == PINMUX_DEFAULT) { - pad0 = _sercom_get_default_pad(sercom_hw, 0); - } - pin_conf.mux_position = pad0 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad0 >> 16, &pin_conf); - - /* SERCOM PAD1 - SCL */ - if (pad1 == PINMUX_DEFAULT) { - pad1 = _sercom_get_default_pad(sercom_hw, 1); - } - pin_conf.mux_position = pad1 & 0xFFFF; - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK; - system_pinmux_pin_set_config(pad1 >> 16, &pin_conf); - - /* Prepare config to write to register CTRLA */ - if (config->run_in_standby || system_is_debugger_present()) { - tmp_ctrla = SERCOM_I2CS_CTRLA_RUNSTDBY; - } else { - tmp_ctrla = 0; - } - - tmp_ctrla |= config->sda_hold_time | - (config->scl_low_timeout << SERCOM_I2CS_CTRLA_LOWTOUT_Pos); - - i2c_hw->CTRLA.reg |= tmp_ctrla; - - /* Set CTRLB configuration */ - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_SMEN | config->address_mode; - - i2c_hw->ADDR.reg = config->address << SERCOM_I2CS_ADDR_ADDR_Pos | - config->address_mask << SERCOM_I2CS_ADDR_ADDRMASK_Pos | - config->enable_general_call_address << SERCOM_I2CS_ADDR_GENCEN_Pos; - - return STATUS_OK; -} - -/** - * \brief Initializes the requested I2C hardware module - * - * Initializes the SERCOM I2C slave device requested and sets the provided - * software module struct. Run this function before any further use of - * the driver. - * - * \param[out] module Pointer to software module struct - * \param[in] hw Pointer to the hardware instance - * \param[in] config Pointer to the configuration struct - * - * \return Status of initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than - * previously set - */ -enum status_code i2c_slave_init( - struct i2c_slave_module *const module, - Sercom *const hw, - const struct i2c_slave_config *const config) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize software module */ - module->hw = hw; - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Check if module is enabled. */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - - /* Check if reset is in progress. */ - if (i2c_hw->CTRLA.reg & SERCOM_I2CS_CTRLA_SWRST) { - return STATUS_BUSY; - } - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - - /* Turn on module in PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Get sercom instance index. */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - - /* Save software module in interrupt handler. */ - _sercom_set_handler(instance_index, _i2c_slave_interrupt_handler); - - /* Save software module. */ - _sercom_instances[instance_index] = module; - - /* Initialize values in module. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->nack_on_address = config->enable_nack_on_address; -#endif - - /* Set SERCOM module to operate in I2C slave mode. */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_MODE_I2C_SLAVE; - - /* Set config and return status. */ - return _i2c_slave_set_config(module, config); -} - -/** - * \brief Resets the hardware module - * - * This will reset the module to hardware defaults. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_slave_reset( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Reset module instance. */ - module->registered_callback = 0; - module->enabled_callback = 0; - module->buffer_length = 0; - module->buffer_remaining = 0; - module->buffer = NULL; -#endif - - /* Disable module */ - i2c_slave_disable(module); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Clear all pending interrupts. */ - system_interrupt_enter_critical_section(); - system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw)); - system_interrupt_leave_critical_section(); -#endif - - /* Wait for sync. */ - _i2c_slave_wait_for_sync(module); - - /* Reset module. */ - i2c_hw->CTRLA.reg = SERCOM_I2CS_CTRLA_SWRST; -} - -/** - * \internal Waits for answer on bus - * - * \param[in] module Pointer to software module structure - * - * \return Status of bus. - * \retval STATUS_OK If given response from slave device - * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout - * period - */ -static enum status_code _i2c_slave_wait_for_bus( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cm *const i2c_module = &(module->hw->I2CM); - - /* Wait for reply. */ - uint16_t timeout_counter = 0; - while ((!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC)) && - (!(i2c_module->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH))) { - - /* Check timeout condition. */ - if (++timeout_counter >= module->buffer_timeout) { - return STATUS_ERR_TIMEOUT; - } - } - return STATUS_OK; -} - -/** - * \brief Writes a packet to the master - * - * Writes a packet to the master. This will wait for the master to issue - * a request. - * - * \param[in] module Pointer to software module structure - * \param[in] packet Packet to write to master - * - * \return Status of packet write. - * \retval STATUS_OK Packet was written successfully - * \retval STATUS_ERR_DENIED Start condition not received, another - * interrupt flag is set - * \retval STATUS_ERR_IO There was an error in the previous transfer - * \retval STATUS_ERR_BAD_FORMAT Master wants to write data - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided - * \retval STATUS_ERR_BUSY The I2C module is busy with a job - * \retval STATUS_ERR_ERR_OVERFLOW Master NACKed before entire packet was - * transferred - * \retval STATUS_ERR_TIMEOUT No response was given within the timeout - * period - */ -enum status_code i2c_slave_write_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint16_t length = packet->data_length; - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } -#endif - - enum status_code status; - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - - /* Check if there was an error in last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } - - /* Check direction */ - if (!(i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Write request from master, send NACK and return, workaround 13574*/ - _i2c_slave_set_ctrlb_ackact(module, false); - _i2c_slave_set_ctrlb_cmd3(module); - return STATUS_ERR_BAD_FORMAT; - } - - /* Read request from master, ACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - _i2c_slave_set_ctrlb_cmd3(module); - - uint16_t i = 0; - - /* Wait for data interrupt */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - while (length--) { - /* Write data */ - _i2c_slave_wait_for_sync(module); - i2c_hw->DATA.reg = packet->data[i++]; - - /* Wait for response from master */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK && - length !=0) { - /* NACK from master, abort */ - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - - return STATUS_ERR_OVERFLOW; - /* Workaround: PIF will probably not be set, ignore */ - } - /* ACK from master, continue writing */ - } - - /* Release line */ - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x02); - - return STATUS_OK; -} - -/** - * \brief Reads a packet from the master - * - * Reads a packet from the master. This will wait for the master to issue a - * request. - * - * \param[in] module Pointer to software module structure - * \param[out] packet Packet to read from master - * - * \return Status of packet read. - * \retval STATUS_OK Packet was read successfully - * \retval STATUS_ABORTED Master sent stop condition or repeated - * start before specified length of bytes - * was received - * \retval STATUS_ERR_IO There was an error in the previous transfer - * \retval STATUS_ERR_DENIED Start condition not received, another - * interrupt flag is set - * \retval STATUS_ERR_INVALID_ARG Invalid argument(s) was provided - * \retval STATUS_ERR_BUSY The I2C module is busy with a job - * \retval STATUS_ERR_BAD_FORMAT Master wants to read data - * \retval STATUS_ERR_ERR_OVERFLOW Last byte received overflows buffer - */ -enum status_code i2c_slave_read_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - Assert(packet); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint16_t length = packet->data_length; - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Check if the module is busy with a job or AMATCH is enabled */ - if (module->buffer_remaining > 0 || - (i2c_hw->INTENSET.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - return STATUS_BUSY; - } -#endif - - enum status_code status; - - /* Wait for master to send address packet */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return STATUS_ERR_DENIED; - } - - /* Check if there was an error in the last transfer */ - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - return STATUS_ERR_IO; - } - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master, send NACK and return, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, false); - _i2c_slave_set_ctrlb_cmd3(module); - return STATUS_ERR_BAD_FORMAT; - } - - /* Write request from master, ACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - _i2c_slave_set_ctrlb_cmd3(module); - - uint16_t i = 0; - while (length--) { - - /* Wait for next byte or stop condition */ - status = _i2c_slave_wait_for_bus(module); - if (status != STATUS_OK) { - /* Timeout, return */ - return status; - } - - if ((i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) || - i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Master sent stop condition, or repeated start, read done */ - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - return STATUS_ABORTED; - } - - /* Read data */ - _i2c_slave_wait_for_sync(module); - packet->data[i++] = i2c_hw->DATA.reg; - - } - - /* Packet read done, wait for packet to NACK, Stop or repeated start */ - status = _i2c_slave_wait_for_bus(module); - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) { - /* Buffer is full, send NACK */ - _i2c_slave_set_ctrlb_ackact(module, false); - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - } - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { - /* Clear stop flag */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - return STATUS_OK; -} - -/** - * \brief Waits for a start condition on the bus - * - * \note This function is only available for 7-bit slave addressing. - * - * Waits for the master to issue a start condition on the bus. - * \note This function does not check for errors in the last transfer, - * this will be discovered when reading or writing. - * - * \param[in] module Pointer to software module structure - * - * \return Direction of the current transfer, when in slave mode. - * \retval I2C_SLAVE_DIRECTION_NONE No request from master within timeout - * period - * \retval I2C_SLAVE_DIRECTION_READ Write request from master - * \retval I2C_SLAVE_DIRECTION_WRITE Read request from master - */ -enum i2c_slave_direction i2c_slave_get_direction_wait( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - enum status_code status; - - /* Wait for address interrupt */ - status = _i2c_slave_wait_for_bus(module); - - if (status != STATUS_OK) { - /* Timeout, return */ - return I2C_SLAVE_DIRECTION_NONE; - } - - if (!(i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH)) { - /* Not address interrupt, something is wrong */ - return I2C_SLAVE_DIRECTION_NONE; - } - - /* Check direction */ - if ((i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR)) { - /* Read request from master */ - return I2C_SLAVE_DIRECTION_WRITE; - } else { - /* Write request from master */ - return I2C_SLAVE_DIRECTION_READ; - } -} - -/** - * \brief Retrieves the current module status - * - * Checks the status of the module and returns it as a bitmask of status - * flags. - * - * \param[in] module Pointer to the I2C slave software device struct - * - * \return Bitmask of status flags. - * - * \retval I2C_SLAVE_STATUS_ADDRESS_MATCH A valid address has been received - * \retval I2C_SLAVE_STATUS_DATA_READY A I2C slave byte transmission is - * successfully completed - * \retval I2C_SLAVE_STATUS_STOP_RECEIVED A stop condition is detected for a - * transaction being processed - * \retval I2C_SLAVE_STATUS_CLOCK_HOLD The slave is holding the SCL line - * low - * \retval I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT An SCL low time-out has occurred - * \retval I2C_SLAVE_STATUS_REPEATED_START Indicates a repeated start, only - * valid if \ref - * I2C_SLAVE_STATUS_ADDRESS_MATCH is - * set - * \retval I2C_SLAVE_STATUS_RECEIVED_NACK The last data packet sent was not - * acknowledged - * \retval I2C_SLAVE_STATUS_COLLISION The I2C slave was not able to - * transmit a high data or NACK bit - * \retval I2C_SLAVE_STATUS_BUS_ERROR An illegal bus condition has - * occurred on the bus - */ -uint32_t i2c_slave_get_status( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - uint8_t intflags = i2c_hw->INTFLAG.reg; - uint8_t status = i2c_hw->STATUS.reg; - uint32_t status_flags = 0; - - /* Check Address Match flag */ - if (intflags & SERCOM_I2CS_INTFLAG_AMATCH) { - status_flags |= I2C_SLAVE_STATUS_ADDRESS_MATCH; - } - /* Check Data Ready flag */ - if (intflags & SERCOM_I2CS_INTFLAG_DRDY) { - status_flags |= I2C_SLAVE_STATUS_DATA_READY; - } - /* Check Stop flag */ - if (intflags & SERCOM_I2CS_INTFLAG_PREC) { - status_flags |= I2C_SLAVE_STATUS_STOP_RECEIVED; - } - /* Check Clock Hold */ - if (status & SERCOM_I2CS_STATUS_CLKHOLD) { - status_flags |= I2C_SLAVE_STATUS_CLOCK_HOLD; - } - /* Check SCL Low Timeout */ - if (status & SERCOM_I2CS_STATUS_LOWTOUT) { - status_flags |= I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT; - } - /* Check Repeated Start */ - if (status & SERCOM_I2CS_STATUS_SR) { - status_flags |= I2C_SLAVE_STATUS_REPEATED_START; - } - /* Check Received Not Acknowledge */ - if (status & SERCOM_I2CS_STATUS_RXNACK) { - status_flags |= I2C_SLAVE_STATUS_RECEIVED_NACK; - } - /* Check Transmit Collision */ - if (status & SERCOM_I2CS_STATUS_COLL) { - status_flags |= I2C_SLAVE_STATUS_COLLISION; - } - /* Check Bus Error */ - if (status & SERCOM_I2CS_STATUS_BUSERR) { - status_flags |= I2C_SLAVE_STATUS_BUS_ERROR; - } - - return status_flags; -} - -/** - * \brief Clears a module status flag - * - * Clears the given status flag of the module. - * - * \note Not all status flags can be cleared. - * - * \param[in] module Pointer to the I2C software device struct - * \param[in] status_flags Bit mask of status flags to clear - * - */ -void i2c_slave_clear_status( - struct i2c_slave_module *const module, - uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Clear Address Match flag */ - if (status_flags & I2C_SLAVE_STATUS_ADDRESS_MATCH) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - /* Clear Data Ready flag */ - if (status_flags & I2C_SLAVE_STATUS_DATA_READY) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; - } - /* Clear Stop flag */ - if (status_flags & I2C_SLAVE_STATUS_STOP_RECEIVED) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - /* Clear SCL Low Timeout */ - if (status_flags & I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - } - /* Clear Transmit Collision */ - if (status_flags & I2C_SLAVE_STATUS_COLLISION) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_COLL; - } - /* Clear Bus Error */ - if (status_flags & I2C_SLAVE_STATUS_BUS_ERROR) { - i2c_hw->STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - } -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c deleted file mode 100644 index 29d222bd2cac7..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_samd20/i2c_slave_interrupt.c +++ /dev/null @@ -1,434 +0,0 @@ -/** - * \file - * - * \brief SAM D20 I2C Slave Interrupt Driver - * - * Copyright (c) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "i2c_slave_interrupt.h" - -/** - * \brief Enables sending of NACK on address match - * - * Enables sending of NACK on address match, thus discarding - * any incoming transaction. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_slave_enable_nack_on_address( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - - module->nack_on_address = true; -} - -/** - * \brief Disables sending NACK on address match - * - * Disables sending of NACK on address match, thus - * acknowledging incoming transactions. - * - * \param[in,out] module Pointer to software module structure - */ -void i2c_slave_disable_nack_on_address( - struct i2c_slave_module *const module) -{ - /* Sanity check arguments. */ - Assert(module); - - module->nack_on_address = false; -} - -/** - * \internal - * Reads next data. Used by interrupt handler to get next data byte from master. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_slave_read( - struct i2c_slave_module *const module) -{ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Read byte from master and put in buffer. */ - *(module->buffer++) = i2c_hw->DATA.reg; - - /*Decrement remaining buffer length */ - module->buffer_remaining--; -} - -/** - * \internal - * Writes next data. Used by interrupt handler to send next data byte to master. - * - * \param[in,out] module Pointer to software module structure - */ -static void _i2c_slave_write( - struct i2c_slave_module *const module) -{ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Write byte from buffer to master */ - i2c_hw->DATA.reg = *(module->buffer++); - - /*Decrement remaining buffer length */ - module->buffer_remaining--; -} - -/** - * \brief Registers callback for the specified callback type - * - * Associates the given callback function with the - * specified callback type. To enable the callback, the - * \ref i2c_slave_enable_callback function must be used. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback Pointer to the function desired for the - * specified callback - * \param[in] callback_type Callback type to register - */ -void i2c_slave_register_callback( - struct i2c_slave_module *const module, - i2c_slave_callback_t callback, - enum i2c_slave_callback callback_type) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - Assert(callback); - - /* Register callback. */ - module->callbacks[callback_type] = callback; - - /* Set corresponding bit to set callback as initiated. */ - module->registered_callback |= (1 << callback_type); -} - -/** - * \brief Unregisters callback for the specified callback type - * - * Removes the currently registered callback for the given callback - * type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to unregister - */ -void i2c_slave_unregister_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - /* Register callback. */ - module->callbacks[callback_type] = NULL; - - /* Set corresponding bit to set callback as initiated. */ - module->registered_callback &= ~(1 << callback_type); -} - -/** - * \brief Initiates a reads packet operation - * - * Reads a data packet from the master. A write request must be initiated by - * the master before the packet can be read. - * - * The \ref I2C_SLAVE_CALLBACK_WRITE_REQUEST callback can be used to call this - * function. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting asynchronously reading I2C packet. - * \retval STATUS_OK If reading was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_slave_read_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy doing async operation. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Save packet to software module. */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->buffer_length = packet->data_length; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH | - SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC; - - /* Read will begin when master initiates the transfer */ - return STATUS_OK; -} - -/** - * \brief Initiates a write packet operation - * - * Writes a data packet to the master. A read request must be initiated by - * the master before the packet can be written. - * - * The \ref I2C_SLAVE_CALLBACK_READ_REQUEST callback can be used to call this - * function. - * - * \param[in,out] module Pointer to software module struct - * \param[in,out] packet Pointer to I2C packet to transfer - * - * \return Status of starting writing I2C packet. - * \retval STATUS_OK If writing was started successfully - * \retval STATUS_BUSY If module is currently busy with another transfer - */ -enum status_code i2c_slave_write_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - Assert(packet); - - /* Check if the I2C module is busy doing async operation. */ - if (module->buffer_remaining > 0) { - return STATUS_BUSY; - } - - /* Save packet to software module. */ - module->buffer = packet->data; - module->buffer_remaining = packet->data_length; - module->buffer_length = packet->data_length; - module->status = STATUS_BUSY; - - /* Enable interrupts */ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH | - SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC; - - return STATUS_OK; -} - -/** - * \internal Interrupt handler for I2C slave - * - * \param[in] instance Sercom instance that triggered the interrupt - */ -void _i2c_slave_interrupt_handler( - uint8_t instance) -{ - /* Get software module for callback handling. */ - struct i2c_slave_module *module = - (struct i2c_slave_module*)_sercom_instances[instance]; - - Assert(module); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Combine callback registered and enabled masks. */ - uint8_t callback_mask = - module->enabled_callback & module->registered_callback; - - - if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) { - /* Address match */ - /* Check if last transfer is done - repeated start */ - if (module->buffer_length != module->buffer_remaining && - module->transfer_direction == I2C_TRANSFER_WRITE) { - - module->status = STATUS_OK; - module->buffer_length = 0; - module->buffer_remaining = 0; - - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE))) { - module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module); - } - } else if (module->buffer_length != module->buffer_remaining && - module->transfer_direction == I2C_TRANSFER_READ) { - module->status = STATUS_OK; - module->buffer_length = 0; - module->buffer_remaining = 0; - - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE))) { - module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module); - } - } - - if (i2c_hw->STATUS.reg & (SERCOM_I2CS_STATUS_BUSERR | - SERCOM_I2CS_STATUS_COLL | SERCOM_I2CS_STATUS_LOWTOUT)) { - /* An error occurred in last packet transfer */ - module->status = STATUS_ERR_IO; - - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER))) { - module->callbacks[I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER](module); - } - } - if (module->nack_on_address) { - /* NACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, false); - } else if (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_DIR) { - /* Set transfer direction in module instance */ - module->transfer_direction = I2C_TRANSFER_READ; - - /* Read request from master */ - if (callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) { - module->callbacks[I2C_SLAVE_CALLBACK_READ_REQUEST](module); - } - - if (module->buffer_length == 0) { - /* Data buffer not set up, NACK address, workaround 13574*/ - _i2c_slave_set_ctrlb_ackact(module, false); - } else { - /* ACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - } - } else { - /* Set transfer direction in dev inst */ - module->transfer_direction = I2C_TRANSFER_WRITE; - - /* Write request from master */ - if (callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)) { - module->callbacks[I2C_SLAVE_CALLBACK_WRITE_REQUEST](module); - } - - if (module->buffer_length == 0) { - /* Data buffer not set up, NACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, false); - } else { - /* ACK address, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - } - } - - /* ACK or NACK address, Workaround 13574 */ - _i2c_slave_set_ctrlb_cmd3(module); - - /* ACK next incoming packet, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, true); - - } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) { - /* Stop condition on bus - current transfer done */ - - /* Clear Stop interrupt */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - - /* Disable interrupts */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_DRDY; - - if (!((module->enabled_callback & (1 << I2C_SLAVE_CALLBACK_READ_REQUEST)) - || (module->enabled_callback == (1 << I2C_SLAVE_CALLBACK_WRITE_REQUEST)))) { - /* Disable address match if read/write request is not enabled */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } - - if (!(module->status == STATUS_ERR_OVERFLOW || module->status == STATUS_ERR_IO)) { - module->status = STATUS_OK; - module->buffer_length = 0; - module->buffer_remaining = 0; - - /* Call appropriate callback if enabled and registered */ - if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_READ_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_WRITE)) { - /* Read from master complete */ - module->callbacks[I2C_SLAVE_CALLBACK_READ_COMPLETE](module); - } else if ((callback_mask & (1 << I2C_SLAVE_CALLBACK_WRITE_COMPLETE)) - && (module->transfer_direction == I2C_TRANSFER_READ)) { - /* Write to master complete */ - module->callbacks[I2C_SLAVE_CALLBACK_WRITE_COMPLETE](module); - } - } - } else if (i2c_hw->INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) { - /* Check if buffer is full, or NACK from master */ - if (module->buffer_remaining <= 0 || - (module->transfer_direction == I2C_TRANSFER_READ && - (module->buffer_length > module->buffer_remaining) && - (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_RXNACK))) { - - module->buffer_remaining = 0; - module->buffer_length = 0; - - if (module->transfer_direction == I2C_TRANSFER_WRITE) { - /* Buffer is full, send NACK, workaround 13574 */ - _i2c_slave_set_ctrlb_ackact(module, false); - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - - /* Set status, new character in DATA register will overflow - * buffer */ - module->status = STATUS_ERR_OVERFLOW; - - if (callback_mask & (1 << I2C_SLAVE_CALLBACK_ERROR)) { - /* Read complete */ - module->callbacks[I2C_SLAVE_CALLBACK_ERROR](module); - } - } else { - /* Release SCL and wait for new start condition */ - _i2c_slave_set_ctrlb_ackact(module, false); - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x2); - - /* Transfer successful */ - module->status = STATUS_OK; - - /* Disable interrupts */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_DRDY; - } - - /* Continue buffer write/read */ - } else if (module->buffer_length > 0 && module->buffer_remaining > 0) { - /* Call function based on transfer direction */ - if (module->transfer_direction == I2C_TRANSFER_WRITE) { - _i2c_slave_read(module); - } else { - _i2c_slave_write(module); - } - } - } -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_slave.h b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_slave.h deleted file mode 100644 index 20eb78ec09ab8..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_slave.h +++ /dev/null @@ -1,753 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Slave Driver - * - * Copyright (c) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_SLAVE_H_INCLUDED -#define I2C_SLAVE_H_INCLUDED - -#include "i2c_common.h" -#include -#include - -#if I2C_SLAVE_CALLBACK_MODE == true -# include -#endif - -#ifndef PINMUX_DEFAULT -# define PINMUX_DEFAULT 0 -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * - * @{ - * - */ - -/** - * \name I2C Slave Status Flags - * - * I2C slave status flags, returned by \ref i2c_slave_get_status() and cleared - * by \ref i2c_slave_clear_status(). - * @{ - */ - -/** Address Match. - * \note Should only be cleared internally by driver. - */ -#define I2C_SLAVE_STATUS_ADDRESS_MATCH (1UL << 0) -/** Data Ready. */ -#define I2C_SLAVE_STATUS_DATA_READY (1UL << 1) -/** Stop Received. */ -#define I2C_SLAVE_STATUS_STOP_RECEIVED (1UL << 2) -/** Clock Hold. - * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is - * set. - */ -#define I2C_SLAVE_STATUS_CLOCK_HOLD (1UL << 3) -/** SCL Low Timeout. */ -#define I2C_SLAVE_STATUS_SCL_LOW_TIMEOUT (1UL << 4) -/** Repeated Start. - * \note Cannot be cleared, only valid when I2C_SLAVE_STATUS_ADDRESS_MATCH is - * set. - */ -#define I2C_SLAVE_STATUS_REPEATED_START (1UL << 5) -/** Received not acknowledge. - * \note Cannot be cleared. - */ -#define I2C_SLAVE_STATUS_RECEIVED_NACK (1UL << 6) -/** Transmit Collision. */ -#define I2C_SLAVE_STATUS_COLLISION (1UL << 7) -/** Bus error. */ -#define I2C_SLAVE_STATUS_BUS_ERROR (1UL << 8) - -/** @} */ - -/** - * \brief I2C slave packet for read/write - * - * Structure to be used when transferring I2C slave packets. - */ -struct i2c_slave_packet { - /** Length of data array */ - uint16_t data_length; - /** Data array containing all data to be transferred */ - uint8_t *data; -}; - -#if I2C_SLAVE_CALLBACK_MODE == true - /** - * \brief Callback types - * - * The available callback types for the I2C slave. - */ -enum i2c_slave_callback { - /** Callback for packet write complete */ - I2C_SLAVE_CALLBACK_WRITE_COMPLETE, - /** Callback for packet read complete */ - I2C_SLAVE_CALLBACK_READ_COMPLETE, - /** - * Callback for read request from master - can be used to - * issue a write - */ - I2C_SLAVE_CALLBACK_READ_REQUEST, - /** - * Callback for write request from master - can be used to issue a read - */ - I2C_SLAVE_CALLBACK_WRITE_REQUEST, - /** Callback for error */ - I2C_SLAVE_CALLBACK_ERROR, - /** - * Callback for error in last transfer. Discovered on a new address - * interrupt. - */ - I2C_SLAVE_CALLBACK_ERROR_LAST_TRANSFER, -# if !defined(__DOXYGEN__) - /** Total number of callbacks */ - _I2C_SLAVE_CALLBACK_N, -# endif -}; - -# if !defined(__DOXYGEN__) -/** Software module prototype */ -struct i2c_slave_module; - -/** Callback type */ -typedef void (*i2c_slave_callback_t)( - struct i2c_slave_module *const module); -# endif -#endif - -/** - * \brief Enum for the possible SDA hold times with respect to the negative - * edge of SCL - * - * Enum for the possible SDA hold times with respect to the negative edge - * of SCL. - */ -enum i2c_slave_sda_hold_time { - /** SDA hold time disabled */ - I2C_SLAVE_SDA_HOLD_TIME_DISABLED = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((0) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 50ns - 100ns */ - I2C_SLAVE_SDA_HOLD_TIME_50NS_100NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((1) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 300ns - 600ns */ - I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((2) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), - /** SDA hold time 400ns - 800ns */ - I2C_SLAVE_SDA_HOLD_TIME_400NS_800NS = - ((SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos))), -}; - -/** - * \brief Enum for the possible address modes - * - * Enum for the possible address modes. - */ -enum i2c_slave_address_mode { - /** Address match on address_mask used as a mask to address */ - I2C_SLAVE_ADDRESS_MODE_MASK = SERCOM_I2CS_CTRLB_AMODE(0), - /** Address math on both address and address_mask */ - I2C_SLAVE_ADDRESS_MODE_TWO_ADDRESSES = SERCOM_I2CS_CTRLB_AMODE(1), - /** - * Address match on range of addresses between and including address and - * address_mask - */ - I2C_SLAVE_ADDRESS_MODE_RANGE = SERCOM_I2CS_CTRLB_AMODE(2), -}; - -/** - * \brief Enum for the direction of a request - * - * Enum for the direction of a request. - */ -enum i2c_slave_direction { - /** Read */ - I2C_SLAVE_DIRECTION_READ, - /** Write */ - I2C_SLAVE_DIRECTION_WRITE, - /** No direction */ - I2C_SLAVE_DIRECTION_NONE, -}; - -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED -/** - * \brief Enum for the transfer speed - * - * Enum for the transfer speed. - */ -enum i2c_slave_transfer_speed { - /** Standard-mode (Sm) up to 100KHz and Fast-mode (Fm) up to 400KHz */ - I2C_SLAVE_SPEED_STANDARD_AND_FAST = SERCOM_I2CS_CTRLA_SPEED(0), - /** Fast-mode Plus (Fm+) up to 1MHz */ - I2C_SLAVE_SPEED_FAST_MODE_PLUS = SERCOM_I2CS_CTRLA_SPEED(1), - /** High-speed mode (Hs-mode) up to 3.4MHz */ - I2C_SLAVE_SPEED_HIGH_SPEED = SERCOM_I2CS_CTRLA_SPEED(2), -}; -#endif - -/** - * \brief SERCOM I2C slave driver software device instance structure. - * - * SERCOM I2C slave driver software instance structure, used to - * retain software state information of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct i2c_slave_module { -#if !defined(__DOXYGEN__) - /** Hardware instance initialized for the struct */ - Sercom *hw; - /** Module lock */ - volatile bool locked; - /** Timeout value for polled functions */ - uint16_t buffer_timeout; -# ifdef FEATURE_I2C_10_BIT_ADDRESS - /** Using 10-bit addressing for the slave */ - bool ten_bit_address; -# endif -# if I2C_SLAVE_CALLBACK_MODE == true - /** Nack on address match */ - bool nack_on_address; - /** Pointers to callback functions */ - volatile i2c_slave_callback_t callbacks[_I2C_SLAVE_CALLBACK_N]; - /** Mask for registered callbacks */ - volatile uint8_t registered_callback; - /** Mask for enabled callbacks */ - volatile uint8_t enabled_callback; - /** The total number of bytes to transfer */ - volatile uint16_t buffer_length; - /** - * Counter used for bytes left to send in write and to count number of - * obtained bytes in read - */ - uint16_t buffer_remaining; - /** Data buffer for packet write and read */ - volatile uint8_t *buffer; - /** Save direction of request from master. 1 = read, 0 = write. */ - volatile enum i2c_transfer_direction transfer_direction; - /** Status for status read back in error callback */ - volatile enum status_code status; -# endif -#endif -}; - -/** - * \brief Configuration structure for the I2C slave device - * - * This is the configuration structure for the I2C slave device. It is used - * as an argument for \ref i2c_slave_init to provide the desired - * configurations for the module. The structure should be initialized using the - * \ref i2c_slave_get_config_defaults. - */ -struct i2c_slave_config { - /** Set to enable the SCL low timeout */ - bool enable_scl_low_timeout; - /** SDA hold time with respect to the negative edge of SCL */ - enum i2c_slave_sda_hold_time sda_hold_time; - /** Timeout to wait for master in polled functions */ - uint16_t buffer_timeout; - /** Addressing mode */ - enum i2c_slave_address_mode address_mode; - /** Address or upper limit of address range */ - uint16_t address; - /** Address mask, second address, or lower limit of address range */ - uint16_t address_mask; -#ifdef FEATURE_I2C_10_BIT_ADDRESS - /** Enable 10-bit addressing */ - bool ten_bit_address; -#endif - /** - * Enable general call address recognition (general call address - * is defined as 0000000 with direction bit 0). - */ - bool enable_general_call_address; - -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - /** Transfer speed mode */ - enum i2c_slave_transfer_speed transfer_speed; -#endif - -#if I2C_SLAVE_CALLBACK_MODE == true - /** - * Enable NACK on address match (this can be changed after initialization - * via the \ref i2c_slave_enable_nack_on_address and - * \ref i2c_slave_disable_nack_on_address functions). - */ - bool enable_nack_on_address; -#endif - /** GCLK generator to use as clock source */ - enum gclk_generator generator_source; - /** Set to keep module active in sleep modes */ - bool run_in_standby; - /** PAD0 (SDA) pinmux */ - uint32_t pinmux_pad0; - /** PAD1 (SCL) pinmux */ - uint32_t pinmux_pad1; - /** Set to enable SCL low time-out */ - bool scl_low_timeout; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - /** Set to enable SCL stretch only after ACK bit (required for high speed) */ - bool scl_stretch_only_after_ack_bit; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - /** Set to enable slave SCL low extend time-out */ - bool slave_scl_low_extend_timeout; -#endif -}; - - -/** - * \name Lock/Unlock - * @{ - */ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline enum status_code i2c_slave_lock( - struct i2c_slave_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline void i2c_slave_unlock(struct i2c_slave_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \name Configuration and Initialization - * @{ - */ - -/** - * \brief Returns the synchronization status of the module - * - * Returns the synchronization status of the module. - * - * \param[out] module Pointer to software module structure - * - * \return Status of the synchronization. - * \retval true Module is busy synchronizing - * \retval false Module is not synchronizing - */ -static inline bool i2c_slave_is_syncing( - const struct i2c_slave_module *const module) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - - /* Return sync status */ -#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1) - return (i2c_hw->STATUS.reg & SERCOM_I2CS_STATUS_SYNCBUSY); -#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2) - return (i2c_hw->SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_MASK); -#else -# error Unknown SERCOM SYNCBUSY scheme! -#endif -} - -#if !defined(__DOXYGEN__) -/** - * \internal Wait for hardware module to sync - * - * \param[in] module Pointer to software module structure - */ -static void _i2c_slave_wait_for_sync( - const struct i2c_slave_module *const module) -{ - /* Sanity check */ - Assert(module); - - while (i2c_slave_is_syncing(module)) { - /* Wait for I2C module to sync */ - } -} -#endif - -///@cond INTERNAL -/** - * \internal Workaround for errata 13574 - * Instead set ACK/NACK of CTRLB - * - * This errata exist in part revisions of SAM D20/D21/D09 - * D10/D11/L21/L22/DA1/C20/C21/R30, but workaround can be works in all - * revision of those device. As this function operation - * should be use less cpu time as possible, so caller - * function can ignore to check revision number, and use - * this workaround in all revision of those device. - * - * \param[in,out] module Pointer to software module structure - * \param[in] send_ack true send ACK, false send NACK - */ -static inline void _i2c_slave_set_ctrlb_ackact( - struct i2c_slave_module *const module, - bool send_ack) -{ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAML21 || SAMDA1 || \ - SAML22 || SAMC20 || SAMC21 || SAMR30) - /* Workaround, Following two write are atomic */ - system_interrupt_enter_critical_section(); - i2c_hw->STATUS.reg = 0; - - if (send_ack == true) { - i2c_hw->CTRLB.reg = 0; - } - else { - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT; - } - system_interrupt_leave_critical_section(); -#else - /* Normal operation */ - if (send_ack == true) { - i2c_hw->CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - } - else { - i2c_hw->CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - } -#endif - return; -} - -/** - * \internal Workaround for SAM0 errata 13574, - * instead Set CMD3 of CTRLB - * - * This errata exist in part revisions of SAM D20/D21/D09 - * D10/D11/L21/DA1/C20/C21/R30, but workaround can be works in all - * revision of those device. As this function operation - * should be use less cpu time as possible, so caller - * function can ignore to check revision number, and use - * this workaround in all revision of those device. - * - * \param[in,out] module Pointer to software module structure - */ -static inline void _i2c_slave_set_ctrlb_cmd3( - struct i2c_slave_module *const module) -{ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if (SAMD20 || SAMD21 || SAMD09 || SAMD10 || SAMD11 || SAML21 || SAML22 || \ - SAMDA1 || SAMC20 || SAMC21 || SAMR30) - /* Workaround */ - /* - * Below code instead i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3); - * CMD=0x3 clears all interrupts, so to keep the result similar - * PREC is cleared if it was set - */ - if (i2c_hw->INTFLAG.bit.PREC) { - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; - } - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -#else - /* Normal operation */ - i2c_hw->CTRLB.reg = SERCOM_I2CS_CTRLB_CMD(0x3); -#endif - return; -} -///@endcond - -/** - * \brief Gets the I2C slave default configurations - * - * This will initialize the configuration structure to known default values. - * - * The default configuration is as follows: - * - Disable SCL low timeout - * - 300ns - 600ns SDA hold time - * - Buffer timeout = 65535 - * - Address with mask - * - Address = 0 - * - Address mask = 0 (one single address) - * - General call address disabled - * - Address nack disabled if the interrupt driver is used - * - GCLK generator 0 - * - Do not run in standby - * - PINMUX_DEFAULT for SERCOM pads - * - * Those default configuration only available if the device supports it: - * - Not using 10-bit addressing - * - Standard-mode and Fast-mode transfer speed - * - SCL stretch disabled - * - Slave SCL low extend time-out disabled - * - * \param[out] config Pointer to configuration structure to be initialized - */ -static inline void i2c_slave_get_config_defaults( - struct i2c_slave_config *const config) -{ - /*Sanity check argument */ - Assert(config); - config->enable_scl_low_timeout = false; - config->sda_hold_time = I2C_SLAVE_SDA_HOLD_TIME_300NS_600NS; - config->buffer_timeout = 65535; - config->address_mode = I2C_SLAVE_ADDRESS_MODE_MASK; - config->address = 0; - config->address_mask = 0; -#ifdef FEATURE_I2C_10_BIT_ADDRESS - config->ten_bit_address = false; -#endif - config->enable_general_call_address = false; -#ifdef FEATURE_I2C_FAST_MODE_PLUS_AND_HIGH_SPEED - config->transfer_speed = I2C_SLAVE_SPEED_STANDARD_AND_FAST; -#endif -#if I2C_SLAVE_CALLBACK_MODE == true - config->enable_nack_on_address = false; -#endif - config->generator_source = GCLK_GENERATOR_0; - config->run_in_standby = false; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->scl_low_timeout = false; -#ifdef FEATURE_I2C_SCL_STRETCH_MODE - config->scl_stretch_only_after_ack_bit = false; -#endif -#ifdef FEATURE_I2C_SCL_EXTEND_TIMEOUT - config->slave_scl_low_extend_timeout = false; -#endif -} - -enum status_code i2c_slave_init(struct i2c_slave_module *const module, - Sercom *const hw, - const struct i2c_slave_config *const config); - -/** - * \brief Enables the I2C module - * - * This will enable the requested I2C module. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_slave_enable( - const struct i2c_slave_module *const module) -{ - /* Sanity check of arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Enable global interrupt for module */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait for module to sync */ - _i2c_slave_wait_for_sync(module); - - /* Enable module */ - i2c_hw->CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; -} - - -/** - * \brief Disables the I2C module - * - * This will disable the I2C module specified in the provided software module - * structure. - * - * \param[in] module Pointer to the software module struct - */ -static inline void i2c_slave_disable( - const struct i2c_slave_module *const module) -{ - /* Sanity check of arguments */ - Assert(module); - Assert(module->hw); - - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - -#if I2C_SLAVE_CALLBACK_MODE == true - /* Disable interrupts */ - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC | - SERCOM_I2CS_INTENSET_AMATCH | SERCOM_I2CS_INTENSET_DRDY; - - /* Clear interrupt flags */ - i2c_hw->INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC | SERCOM_I2CS_INTFLAG_AMATCH | - SERCOM_I2CS_INTFLAG_DRDY; - - /* Disable global interrupt for module */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait for module to sync */ - _i2c_slave_wait_for_sync(module); - - /* Disable module */ - i2c_hw->CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; -} - -void i2c_slave_reset( - struct i2c_slave_module *const module); - -/** @} */ - -/** - * \name Read and Write - * @{ - */ - -enum status_code i2c_slave_write_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); -enum status_code i2c_slave_read_packet_wait( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); -enum i2c_slave_direction i2c_slave_get_direction_wait( - struct i2c_slave_module *const module); - -/** @} */ - -/** - * \name Status Management - * @{ - */ -uint32_t i2c_slave_get_status( - struct i2c_slave_module *const module); -void i2c_slave_clear_status( - struct i2c_slave_module *const module, - uint32_t status_flags); -/** @} */ - -#ifdef FEATURE_I2C_DMA_SUPPORT -/** - * \name SERCOM I2C slave with DMA Interfaces - * @{ - */ - -/** - * \brief Read SERCOM I2C interrupt status. - * - * Read I2C interrupt status for DMA transfer. - * - * \param[in,out] module Pointer to the driver instance to lock - * - */ -static inline uint8_t i2c_slave_dma_read_interrupt_status(struct i2c_slave_module *const module) -{ - return (uint8_t)module->hw->I2CS.INTFLAG.reg; -} - -/** - * \brief Write SERCOM I2C interrupt status. - * - * Write I2C interrupt status for DMA transfer. - * - * \param[in,out] module Pointer to the driver instance to lock - * \param[in] flag Interrupt flag status - * - */ -static inline void i2c_slave_dma_write_interrupt_status(struct i2c_slave_module *const module, - uint8_t flag) -{ - module->hw->I2CS.INTFLAG.reg = flag; -} - -/** @} */ -#endif - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_SLAVE_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h b/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h deleted file mode 100644 index cf1c4362c7989..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/i2c/i2c_slave_interrupt.h +++ /dev/null @@ -1,215 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM I2C Slave Interrupt Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef I2C_SLAVE_INTERRUPT_H_INCLUDED -#define I2C_SLAVE_INTERRUPT_H_INCLUDED - -#include "i2c_slave.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_i2c_group - * @{ - * - */ - -/** - * \name Address Match Functionality - * @{ - */ - -void i2c_slave_enable_nack_on_address( - struct i2c_slave_module *const module); -void i2c_slave_disable_nack_on_address( - struct i2c_slave_module *const module); - -/** @} */ - -/** - * \name Callbacks - * @{ - */ -#if !defined(__DOXYGEN__) -void _i2c_slave_interrupt_handler(uint8_t instance); -#endif - -void i2c_slave_register_callback( - struct i2c_slave_module *const module, - i2c_slave_callback_t callback, - enum i2c_slave_callback callback_type); - -void i2c_slave_unregister_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type); - -/** - * \brief Enables callback - * - * Enables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to enable - */ -static inline void i2c_slave_enable_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Mark callback as enabled */ - module->enabled_callback |= (1 << callback_type); - - /* Enable address callback */ - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST || - callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST) { - i2c_hw->INTENSET.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } -} - -/** - * \brief Disables callback - * - * Disables the callback specified by the callback_type. - * - * \param[in,out] module Pointer to the software module struct - * \param[in] callback_type Callback type to disable - */ -static inline void i2c_slave_disable_callback( - struct i2c_slave_module *const module, - enum i2c_slave_callback callback_type) -{ - /* Sanity check */ - Assert(module); - Assert(module->hw); - - /* Mark callback as disabled */ - module->enabled_callback &= ~(1 << callback_type); - SercomI2cs *const i2c_hw = &(module->hw->I2CS); - if (callback_type == I2C_SLAVE_CALLBACK_READ_REQUEST || - callback_type == I2C_SLAVE_CALLBACK_WRITE_REQUEST || - module->status != STATUS_BUSY) { - i2c_hw->INTENCLR.reg = SERCOM_I2CS_INTFLAG_AMATCH; - } -} - -/** @} */ - -/** - * \name Read and Write, Interrupt-Driven - * @{ - */ - - -enum status_code i2c_slave_read_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); - -enum status_code i2c_slave_write_packet_job( - struct i2c_slave_module *const module, - struct i2c_slave_packet *const packet); - -/** - * \brief Cancels any currently ongoing operation - * - * Terminates the running transfer operation. - * - * \param[in,out] module Pointer to software module structure - */ -static inline void i2c_slave_cancel_job( - struct i2c_slave_module *const module) -{ - /* Sanity check. */ - Assert(module); - Assert(module->hw); - - /* Set buffer to 0. */ - module->buffer_remaining = 0; - module->buffer_length = 0; -} - -/** - * \brief Gets status of ongoing job - * - * Will return the status of the ongoing job, or the error that occurred - * in the last transfer operation. - * The status will be cleared when starting a new job. - * - * \param[in,out] module Pointer to software module structure - * - * \return Status of job. - * \retval STATUS_OK No error has occurred - * \retval STATUS_BUSY Transfer is in progress - * \retval STATUS_ERR_IO A collision, timeout or bus error happened in - * the last transfer - * \retval STATUS_ERR_TIMEOUT A timeout occurred - * \retval STATUS_ERR_OVERFLOW Data from master overflows receive buffer - */ -static inline enum status_code i2c_slave_get_job_status( - struct i2c_slave_module *const module) -{ - /* Check sanity. */ - Assert(module); - Assert(module->hw); - - /* Return current status code. */ - return module->status; -} - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* I2C_SLAVE_INTERRUPT_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/sercom.c b/atmel-samd/asf/sam0/drivers/sercom/sercom.c deleted file mode 100644 index 637f3947fae88..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/sercom.c +++ /dev/null @@ -1,296 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "sercom.h" - -#define SHIFT 32 -#define BAUD_INT_MAX 8192 -#define BAUD_FP_MAX 8 - -#if !defined(__DOXYGEN__) -/** - * \internal Configuration structure to save current gclk status. - */ -struct _sercom_conf { - /* Status of gclk generator initialization */ - bool generator_is_set; - /* Sercom gclk generator used */ - enum gclk_generator generator_source; -}; - -static struct _sercom_conf _sercom_config; - - -/** - * \internal Calculate 64 bit division, ref can be found in - * http://en.wikipedia.org/wiki/Division_algorithm#Long_division - */ -static uint64_t long_division(uint64_t n, uint64_t d) -{ - int32_t i; - uint64_t q = 0, r = 0, bit_shift; - for (i = 63; i >= 0; i--) { - bit_shift = (uint64_t)1 << i; - - r = r << 1; - - if (n & bit_shift) { - r |= 0x01; - } - - if (r >= d) { - r = r - d; - q |= bit_shift; - } - } - - return q; -} - -/** - * \internal Calculate synchronous baudrate value (SPI/UART) - */ -enum status_code _sercom_get_sync_baud_val( - const uint32_t baudrate, - const uint32_t external_clock, - uint16_t *const baudvalue) -{ - /* Baud value variable */ - uint16_t baud_calculated = 0; - uint32_t clock_value = external_clock; - - - /* Check if baudrate is outside of valid range */ - if (baudrate > (external_clock / 2)) { - /* Return with error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - - /* Calculate BAUD value from clock frequency and baudrate */ - clock_value = external_clock / 2; - while (clock_value >= baudrate) { - clock_value = clock_value - baudrate; - baud_calculated++; - } - baud_calculated = baud_calculated - 1; - - /* Check if BAUD value is more than 255, which is maximum - * for synchronous mode */ - if (baud_calculated > 0xFF) { - /* Return with an error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } else { - *baudvalue = baud_calculated; - return STATUS_OK; - } -} - -/** - * \internal Calculate asynchronous baudrate value (UART) -*/ -enum status_code _sercom_get_async_baud_val( - const uint32_t baudrate, - const uint32_t peripheral_clock, - uint16_t *const baudval, - enum sercom_asynchronous_operation_mode mode, - enum sercom_asynchronous_sample_num sample_num) -{ - /* Temporary variables */ - uint64_t ratio = 0; - uint64_t scale = 0; - uint64_t baud_calculated = 0; - uint8_t baud_fp; - uint32_t baud_int = 0; - uint64_t temp1, temp2; - - /* Check if the baudrate is outside of valid range */ - if ((baudrate * sample_num) > peripheral_clock) { - /* Return with error code */ - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - - if(mode == SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC) { - /* Calculate the BAUD value */ - temp1 = ((sample_num * (uint64_t)baudrate) << SHIFT); - ratio = long_division(temp1, peripheral_clock); - scale = ((uint64_t)1 << SHIFT) - ratio; - baud_calculated = (65536 * scale) >> SHIFT; - } else if(mode == SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL) { - for(baud_fp = 0; baud_fp < BAUD_FP_MAX; baud_fp++) { - temp1 = BAUD_FP_MAX * (uint64_t)peripheral_clock; - temp2 = ((uint64_t)baudrate * sample_num); - baud_int = long_division(temp1, temp2); - baud_int -= baud_fp; - baud_int = baud_int / BAUD_FP_MAX; - if(baud_int < BAUD_INT_MAX) { - break; - } - } - if(baud_fp == BAUD_FP_MAX) { - return STATUS_ERR_BAUDRATE_UNAVAILABLE; - } - baud_calculated = baud_int | (baud_fp << 13); - } - - *baudval = baud_calculated; - return STATUS_OK; -} -#endif - -/** - * \brief Set GCLK channel to generator. - * - * This will set the appropriate GCLK channel to the requested GCLK generator. - * This will set the generator for all SERCOM instances, and the user will thus - * only be able to set the same generator that has previously been set, if any. - * - * After the generator has been set the first time, the generator can be changed - * using the \c force_change flag. - * - * \param[in] generator_source The generator to use for SERCOM. - * \param[in] force_change Force change the generator. - * - * \return Status code indicating the GCLK generator change operation. - * \retval STATUS_OK If the generator update request was - * successful. - * \retval STATUS_ERR_ALREADY_INITIALIZED If a generator was already configured - * and the new configuration was not - * forced. - */ -enum status_code sercom_set_gclk_generator( - const enum gclk_generator generator_source, - const bool force_change) -{ - /* Check if valid option */ - if (!_sercom_config.generator_is_set || force_change) { - /* Create and fill a GCLK configuration structure for the new config */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = generator_source; - system_gclk_chan_set_config(SERCOM_GCLK_ID, &gclk_chan_conf); - system_gclk_chan_enable(SERCOM_GCLK_ID); - - /* Save config */ - _sercom_config.generator_source = generator_source; - _sercom_config.generator_is_set = true; - - return STATUS_OK; - } else if (generator_source == _sercom_config.generator_source) { - /* Return status OK if same config */ - return STATUS_OK; - } - - /* Return invalid config to already initialized GCLK */ - return STATUS_ERR_ALREADY_INITIALIZED; -} - -/** \internal - * Creates a switch statement case entry to convert a SERCOM instance and pad - * index to the default SERCOM pad MUX setting. - */ -#define _SERCOM_PAD_DEFAULTS_CASE(n, pad) \ - case (uintptr_t)SERCOM##n: \ - switch (pad) { \ - case 0: \ - return SERCOM##n##_PAD0_DEFAULT; \ - case 1: \ - return SERCOM##n##_PAD1_DEFAULT; \ - case 2: \ - return SERCOM##n##_PAD2_DEFAULT; \ - case 3: \ - return SERCOM##n##_PAD3_DEFAULT; \ - } \ - break; - -/** - * \internal Gets the default PAD pinout for a given SERCOM. - * - * Returns the pinmux settings for the given SERCOM and pad. This is used - * for default configuration of pins. - * - * \param[in] sercom_module Pointer to the SERCOM module - * \param[in] pad PAD to get default pinout for - * - * \returns The default pinmux for the given SERCOM instance and PAD - * - */ -uint32_t _sercom_get_default_pad( - Sercom *const sercom_module, - const uint8_t pad) -{ - switch ((uintptr_t)sercom_module) { - /* Auto-generate a lookup table for the default SERCOM pad defaults */ - MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_DEFAULTS_CASE, pad) - } - - Assert(false); - return 0; -} - -/** - * \internal - * Find index of given instance. - * - * \param[in] sercom_instance Instance pointer. - * - * \return Index of given instance. - */ -uint8_t _sercom_get_sercom_inst_index( - Sercom *const sercom_instance) -{ - /* Save all available SERCOM instances for compare */ - Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS; - - /* Find index for sercom instance */ - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - if ((uintptr_t)sercom_instance == (uintptr_t)sercom_instances[i]) { - return i; - } - } - - /* Invalid data given */ - Assert(false); - return 0; -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/sercom.h b/atmel-samd/asf/sam0/drivers/sercom/sercom.h deleted file mode 100644 index 60ce6f8ad1034..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/sercom.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SERCOM_H_INCLUDED -#define SERCOM_H_INCLUDED - -#include -#include -#include -#include -#include "sercom_pinout.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* SERCOM modules should share same slow GCLK channel ID */ -#define SERCOM_GCLK_ID SERCOM0_GCLK_ID_SLOW - -#if (0x1ff >= REV_SERCOM) -# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1 -#elif (0x400 >= REV_SERCOM) -# define FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2 -#else -# error "Unknown SYNCBUSY scheme for this SERCOM revision" -#endif - -/** - * \brief sercom asynchronous operation mode - * - * Select sercom asynchronous operation mode - */ -enum sercom_asynchronous_operation_mode { - SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC = 0, - SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL, -}; - -/** - * \brief sercom asynchronous samples per bit - * - * Select number of samples per bit - */ -enum sercom_asynchronous_sample_num { - SERCOM_ASYNC_SAMPLE_NUM_3 = 3, - SERCOM_ASYNC_SAMPLE_NUM_8 = 8, - SERCOM_ASYNC_SAMPLE_NUM_16 = 16, -}; - -enum status_code sercom_set_gclk_generator( - const enum gclk_generator generator_source, - const bool force_change); - -enum status_code _sercom_get_sync_baud_val( - const uint32_t baudrate, - const uint32_t external_clock, - uint16_t *const baudval); - -enum status_code _sercom_get_async_baud_val( - const uint32_t baudrate, - const uint32_t peripheral_clock, - uint16_t *const baudval, - enum sercom_asynchronous_operation_mode mode, - enum sercom_asynchronous_sample_num sample_num); - -uint32_t _sercom_get_default_pad( - Sercom *const sercom_module, - const uint8_t pad); - -uint8_t _sercom_get_sercom_inst_index( - Sercom *const sercom_instance); -#ifdef __cplusplus -} -#endif - -#endif //__SERCOM_H_INCLUDED diff --git a/atmel-samd/asf/sam0/drivers/sercom/sercom_interrupt.c b/atmel-samd/asf/sam0/drivers/sercom/sercom_interrupt.c deleted file mode 100644 index b26d05b6e74ab..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/sercom_interrupt.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "sercom_interrupt.h" - -void *_sercom_instances[SERCOM_INST_NUM]; - -/** Save status of initialized handlers */ -static bool _handler_table_initialized = false; - -/** Void pointers for saving device instance structures */ -static void (*_sercom_interrupt_handlers[SERCOM_INST_NUM])(const uint8_t instance); - -/** - * \internal - * Default interrupt handler. - * - * \param[in] instance SERCOM instance used. - */ -static void _sercom_default_handler( - const uint8_t instance) -{ - Assert(false); -} - -/** - * \internal - * Saves the given callback handler. - * - * \param[in] instance Instance index. - * \param[in] interrupt_handler Pointer to instance callback handler. - */ -void _sercom_set_handler( - const uint8_t instance, - const sercom_handler_t interrupt_handler) -{ - /* Initialize handlers with default handler and device instances with 0 */ - if (_handler_table_initialized == false) { - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - _sercom_interrupt_handlers[i] = &_sercom_default_handler; - _sercom_instances[i] = NULL; - } - - _handler_table_initialized = true; - } - - /* Save interrupt handler */ - _sercom_interrupt_handlers[instance] = interrupt_handler; -} - - -/** \internal - * Converts a given SERCOM index to its interrupt vector index. - */ -#define _SERCOM_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_SERCOM##n, - -/** \internal - * Generates a SERCOM interrupt handler function for a given SERCOM index. - */ -#define _SERCOM_INTERRUPT_HANDLER(n, unused) \ - void SERCOM##n##_Handler(void) \ - { \ - _sercom_interrupt_handlers[n](n); \ - } - -/** - * \internal - * Returns the system interrupt vector. - * - * \param[in] sercom_instance Instance pointer - * - * \return Enum of system interrupt vector - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM0 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM1 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM2 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM3 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM4 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM5 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM6 - * \retval SYSTEM_INTERRUPT_MODULE_SERCOM7 - */ -enum system_interrupt_vector _sercom_get_interrupt_vector( - Sercom *const sercom_instance) -{ - const uint8_t sercom_int_vectors[SERCOM_INST_NUM] = - { - MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_VECT_NUM, ~) - }; - - /* Retrieve the index of the SERCOM being requested */ - uint8_t instance_index = _sercom_get_sercom_inst_index(sercom_instance); - - /* Get the vector number from the lookup table for the requested SERCOM */ - return (enum system_interrupt_vector)sercom_int_vectors[instance_index]; -} - -/** Auto-generate a set of interrupt handlers for each SERCOM in the device */ -MREPEAT(SERCOM_INST_NUM, _SERCOM_INTERRUPT_HANDLER, ~) diff --git a/atmel-samd/asf/sam0/drivers/sercom/sercom_interrupt.h b/atmel-samd/asf/sam0/drivers/sercom/sercom_interrupt.h deleted file mode 100644 index 18945f5186cc4..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/sercom_interrupt.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SERCOM_INTERRUPT_H_INCLUDED -#define SERCOM_INTERRUPT_H_INCLUDED - -#include "sercom.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Look-up table for device instances */ -extern void *_sercom_instances[SERCOM_INST_NUM]; - -typedef void (*sercom_handler_t)(uint8_t instance); - -enum system_interrupt_vector _sercom_get_interrupt_vector( - Sercom *const sercom_instance); - -void _sercom_set_handler( - const uint8_t instance, - const sercom_handler_t interrupt_handler); - -#ifdef __cplusplus -} -#endif - -#endif /* SERCOM_INTERRUPT_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/sercom_pinout.h b/atmel-samd/asf/sam0/drivers/sercom/sercom_pinout.h deleted file mode 100644 index 94ebc9cc0c7ad..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/sercom_pinout.h +++ /dev/null @@ -1,526 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM Module Pinout Definitions - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SERCOM_PINOUT_H_INCLUDED -#define SERCOM_PINOUT_H_INCLUDED - -#include - -#if SAMR21E - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - - /* SERCOM3 */ -# if SAM_PART_IS_DEFINED(SAMR21E19A) - #define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 -# else - #define SERCOM3_PAD0_DEFAULT PINMUX_PA27F_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA28F_SERCOM3_PAD1 -#endif - #define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - - /* SERCOM4 */ -# if SAM_PART_IS_DEFINED(SAMR21E19A) - #define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 -# else - #define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 -# endif - - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - -#elif SAMR21G - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PC19F_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PB31F_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PB30F_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PC18F_SERCOM4_PAD3 - - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - -#elif (SAMD09) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA08D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA09D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA30C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA31C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA24C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA25C_SERCOM1_PAD3 - -#elif (SAMD10DS) || (SAMD10DM) || (SAMD10DU) || (SAMD11DS) || (SAMD11DM) || (SAMD11DU) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA22C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA23C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA16D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA25D_SERCOM2_PAD3 - -#elif (SAMD10C) || (SAMD11C) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA08D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA09D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA30C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA31C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA24C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA25C_SERCOM1_PAD3 - -#elif SAM_PART_IS_DEFINED(SAMD21E15L) || SAM_PART_IS_DEFINED(SAMD21E16L) - - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - -#elif (SAML22N) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA20D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA21D_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PB02C_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PB21C_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PB00C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PB01C_SERCOM3_PAD3 - - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PA12C_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PA13C_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PA14C_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PA15C_SERCOM4_PAD3 - - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PB30D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PB31D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PB22D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PB23D_SERCOM5_PAD3 -#elif (SAML22J) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA20D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA21D_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PB02C_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PB13C_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PB00C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PB01C_SERCOM3_PAD3 -#elif (SAML22G) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA08C_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA09C_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA10C_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA11C_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA22D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA23D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA20D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA21D_SERCOM2_PAD3 -#elif (SAMC20E) || (SAMC21E) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - -#elif (SAMC20G) || (SAMC21G) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - - #ifdef ID_SERCOM4 - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3 - #endif - - #ifdef ID_SERCOM5 - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PB22D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PB23D_SERCOM5_PAD3 - #endif - -#elif (SAMC20J) || (SAMC21J) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA12C_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA13C_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA14C_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA15C_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA22C_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA23C_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA24C_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA25C_SERCOM3_PAD3 - - #ifdef ID_SERCOM4 - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PB08D_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PB09D_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PB10D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PB11D_SERCOM4_PAD3 - #endif - - #ifdef ID_SERCOM5 - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PB02D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PB03D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PB00D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PB01D_SERCOM5_PAD3 - #endif - -#elif (SAMDA1) - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - - #if (SAMDA1E) - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT 0 /* No available pin */ - #define SERCOM4_PAD1_DEFAULT 0 /* No available pin */ - #define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 - #else - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 - #endif - - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - -#elif (SAML21E) || (SAMR30E) - - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ - #define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - - #if !SAM_PART_IS_DEFINED(SAML21E18A) && !SAM_PART_IS_DEFINED(SAMR30E18A) - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT 0 /* No available pin */ - #define SERCOM4_PAD1_DEFAULT 0 /* No available pin */ - #define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 - - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - #endif - -#else - /* SERCOM0 */ - #define SERCOM0_PAD0_DEFAULT PINMUX_PA04D_SERCOM0_PAD0 - #define SERCOM0_PAD1_DEFAULT PINMUX_PA05D_SERCOM0_PAD1 - #define SERCOM0_PAD2_DEFAULT PINMUX_PA06D_SERCOM0_PAD2 - #define SERCOM0_PAD3_DEFAULT PINMUX_PA07D_SERCOM0_PAD3 - - /* SERCOM1 */ -#if SAM_PART_IS_DEFINED(SAMD21G15L) || SAM_PART_IS_DEFINED(SAMD21G16L) - #define SERCOM1_PAD0_DEFAULT PINMUX_PA16C_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA17C_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA18C_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA19C_SERCOM1_PAD3 -#else - #define SERCOM1_PAD0_DEFAULT PINMUX_PA00D_SERCOM1_PAD0 - #define SERCOM1_PAD1_DEFAULT PINMUX_PA01D_SERCOM1_PAD1 - #define SERCOM1_PAD2_DEFAULT PINMUX_PA30D_SERCOM1_PAD2 - #define SERCOM1_PAD3_DEFAULT PINMUX_PA31D_SERCOM1_PAD3 -#endif - - /* SERCOM2 */ - #define SERCOM2_PAD0_DEFAULT PINMUX_PA08D_SERCOM2_PAD0 - #define SERCOM2_PAD1_DEFAULT PINMUX_PA09D_SERCOM2_PAD1 - #define SERCOM2_PAD2_DEFAULT PINMUX_PA10D_SERCOM2_PAD2 - #define SERCOM2_PAD3_DEFAULT PINMUX_PA11D_SERCOM2_PAD3 - - /* SERCOM3 */ - #define SERCOM3_PAD0_DEFAULT PINMUX_PA16D_SERCOM3_PAD0 - #define SERCOM3_PAD1_DEFAULT PINMUX_PA17D_SERCOM3_PAD1 - #define SERCOM3_PAD2_DEFAULT PINMUX_PA18D_SERCOM3_PAD2 - #define SERCOM3_PAD3_DEFAULT PINMUX_PA19D_SERCOM3_PAD3 - - #if !(SAMD20E || SAMD21E) - /* SERCOM4 */ - #define SERCOM4_PAD0_DEFAULT PINMUX_PA12D_SERCOM4_PAD0 - #define SERCOM4_PAD1_DEFAULT PINMUX_PA13D_SERCOM4_PAD1 - #define SERCOM4_PAD2_DEFAULT PINMUX_PA14D_SERCOM4_PAD2 - #define SERCOM4_PAD3_DEFAULT PINMUX_PA15D_SERCOM4_PAD3 - - /* SERCOM5 */ - #define SERCOM5_PAD0_DEFAULT PINMUX_PA22D_SERCOM5_PAD0 - #define SERCOM5_PAD1_DEFAULT PINMUX_PA23D_SERCOM5_PAD1 - #define SERCOM5_PAD2_DEFAULT PINMUX_PA24D_SERCOM5_PAD2 - #define SERCOM5_PAD3_DEFAULT PINMUX_PA25D_SERCOM5_PAD3 - #endif - -#endif - -#endif /* SERCOM_PINOUT_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi/module_config/conf_spi.h b/atmel-samd/asf/sam0/drivers/sercom/spi/module_config/conf_spi.h deleted file mode 100644 index 18b4f76ef1610..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi/module_config/conf_spi.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief SAM SPI configuration - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef CONF_SPI_H_INCLUDED -# define CONF_SPI_H_INCLUDED - -# define CONF_SPI_MASTER_ENABLE true -# define CONF_SPI_SLAVE_ENABLE true - -#endif /* CONF_SPI_H_INCLUDED */ - diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi/spi.c b/atmel-samd/asf/sam0/drivers/sercom/spi/spi.c deleted file mode 100644 index c0b4acb4a0f51..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi/spi.c +++ /dev/null @@ -1,1265 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "spi.h" - -/** - * \brief Resets the SPI module - * - * This function will reset the SPI module to its power on default values and - * disable it. - * - * \param[in,out] module Pointer to the software instance struct - */ -void spi_reset( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Disable the module */ - spi_disable(module); - - while (spi_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } - - /* Software reset the module */ - spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; -} - -/** - * \brief Set the baudrate of the SPI module - * - * This function will set the baudrate of the SPI module. - * - * \param[in] module Pointer to the software instance struct - * \param[in] baudrate The baudrate wanted - * - * \return The status of the configuration. - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_OK If the configuration was written - */ -enum status_code spi_set_baudrate( - struct spi_module *const module, - uint32_t baudrate) -{ - /* Sanity check arguments */ - Assert(module); - Assert(baudrate); - Assert(module->hw); - - /* Value to write to BAUD register */ - uint16_t baud = 0; - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Disable the module */ - spi_disable(module); - - while (spi_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } - - /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); - - /* Get baud value, based on baudrate and the internal clock frequency */ - enum status_code error_code = _sercom_get_sync_baud_val( - baudrate, internal_clock, &baud); - - if (error_code != STATUS_OK) { - /* Baud rate calculation error, return status code */ - return STATUS_ERR_INVALID_ARG; - } - - spi_module->BAUD.reg = (uint8_t)baud; - - while (spi_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } - - /* Enable the module */ - spi_enable(module); - - while (spi_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } - - return STATUS_OK; -} - -# if CONF_SPI_SLAVE_ENABLE == true -/** - * \internal Clears the Transmit Complete interrupt flag. - * - * \param[in] module Pointer to the software instance struct - */ -static void _spi_clear_tx_complete_flag( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Clear interrupt flag */ - spi_module->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; -} -# endif - -/** - * \internal Writes an SPI SERCOM configuration to the hardware module. - * - * This function will write out a given configuration to the hardware module. - * Can only be done when the module is disabled. - * - * \param[in] module Pointer to the software instance struct - * \param[in] config Pointer to the configuration struct - * - * \return The status of the configuration. - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_OK If the configuration was written - */ -static enum status_code _spi_set_config( - struct spi_module *const module, - const struct spi_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(config); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - Sercom *const hw = module->hw; - - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - if(config->mode == SPI_MODE_SLAVE) { - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - } - - uint32_t pad_pinmuxes[] = { - config->pinmux_pad0, config->pinmux_pad1, - config->pinmux_pad2, config->pinmux_pad3 - }; - - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; - - if (current_pinmux == PINMUX_DEFAULT) { - current_pinmux = _sercom_get_default_pad(hw, pad); - } - - if (current_pinmux != PINMUX_UNUSED) { - pin_conf.mux_position = current_pinmux & 0xFFFF; - system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); - } - } - - module->mode = config->mode; - module->character_size = config->character_size; - module->receiver_enabled = config->receiver_enable; -# ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT - module->master_slave_select_enable = config->master_slave_select_enable; -# endif - -# if CONF_SPI_MASTER_ENABLE == true - /* Value to write to BAUD register */ - uint16_t baud = 0; -# endif - /* Value to write to CTRLA register */ - uint32_t ctrla = 0; - /* Value to write to CTRLB register */ - uint32_t ctrlb = 0; - -# if CONF_SPI_MASTER_ENABLE == true - /* Find baud value and write it */ - if (config->mode == SPI_MODE_MASTER) { - /* Find frequency of the internal SERCOMi_GCLK_ID_CORE */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - uint32_t internal_clock = system_gclk_chan_get_hz(gclk_index); - - /* Get baud value, based on baudrate and the internal clock frequency */ - enum status_code error_code = _sercom_get_sync_baud_val( - config->mode_specific.master.baudrate, - internal_clock, &baud); - - if (error_code != STATUS_OK) { - /* Baud rate calculation error, return status code */ - return STATUS_ERR_INVALID_ARG; - } - - spi_module->BAUD.reg = (uint8_t)baud; - } -# endif -# if CONF_SPI_SLAVE_ENABLE == true - if (config->mode == SPI_MODE_SLAVE) { - /* Set frame format */ - ctrla = config->mode_specific.slave.frame_format; - - /* Set address mode */ - ctrlb = config->mode_specific.slave.address_mode; - - /* Set address and address mask*/ - spi_module->ADDR.reg |= - (config->mode_specific.slave.address << SERCOM_SPI_ADDR_ADDR_Pos) | - (config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos); - - if (config->mode_specific.slave.preload_enable) { - /* Enable pre-loading of shift register */ - ctrlb |= SERCOM_SPI_CTRLB_PLOADEN; - } - } -# endif - /* Set data order */ - ctrla |= config->data_order; - - /* Set clock polarity and clock phase */ - ctrla |= config->transfer_mode; - - /* Set MUX setting */ - ctrla |= config->mux_setting; - - /* Set SPI character size */ - ctrlb |= config->character_size; - - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY; - } - - if (config->receiver_enable) { - /* Enable receiver */ - ctrlb |= SERCOM_SPI_CTRLB_RXEN; - } -# ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT - if (config->select_slave_low_detect_enable) { - /* Enable Slave Select Low Detect */ - ctrlb |= SERCOM_SPI_CTRLB_SSDE; - } -# endif -# ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT - if (config->master_slave_select_enable) { - /* Enable Master Slave Select */ - ctrlb |= SERCOM_SPI_CTRLB_MSSEN; - } -# endif - /* Write CTRLA register */ - spi_module->CTRLA.reg |= ctrla; - - /* Write CTRLB register */ - spi_module->CTRLB.reg |= ctrlb; - - return STATUS_OK; -} - -#if SPI_CALLBACK_MODE == false -/** - * \internal Checks an SPI config against current set config - * - * This function will check that the config does not alter the - * configuration of the module. If the new config changes any - * setting, the initialization will be discarded. - * - * \param[in] module Pointer to the software instance struct - * \param[in] config Pointer to the configuration struct - * - * \return The status of the configuration. - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_DENIED If configuration was different from previous - * \retval STATUS_OK If the configuration was written - */ -static enum status_code _spi_check_config( - struct spi_module *const module, - const struct spi_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(config); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - Sercom *const hw = module->hw; - - uint32_t pad_pinmuxes[] = { - config->pinmux_pad0, config->pinmux_pad1, - config->pinmux_pad2, config->pinmux_pad3 - }; - - /* Compare the current SERCOM pins against the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; - - if (current_pinmux == PINMUX_DEFAULT) { - current_pinmux = _sercom_get_default_pad(hw, pad); - } - - if (current_pinmux == PINMUX_UNUSED) { - continue; - } - - if ((current_pinmux & 0xFFFF) != - system_pinmux_pin_get_mux_position(current_pinmux >> 16)) { - module->hw = NULL; - return STATUS_ERR_DENIED; - } - } - -# if CONF_SPI_MASTER_ENABLE == true - /* Value to read BAUD register */ - uint16_t baud; - uint32_t external_clock = system_gclk_chan_get_hz(SERCOM_GCLK_ID); -# endif - /* Value to read CTRLA, CTRLB and ADDR register */ - uint32_t ctrla = 0; - uint32_t ctrlb = 0; -# if CONF_SPI_SLAVE_ENABLE == true - uint32_t addr = 0; -# endif - -# if CONF_SPI_MASTER_ENABLE == true - /* Find baud value and compare it */ - if (config->mode == SPI_MODE_MASTER) { - enum status_code error_code = _sercom_get_sync_baud_val( - config->mode_specific.master.baudrate, - external_clock, &baud); - - if (error_code != STATUS_OK) { - /* Baud rate calculation error, return status code */ - return STATUS_ERR_INVALID_ARG; - } - - if (spi_module->BAUD.reg != (uint8_t)baud) { - return STATUS_ERR_DENIED; - } - - ctrla |= SERCOM_SPI_CTRLA_MODE(0x3); - } -# endif - -# if CONF_SPI_SLAVE_ENABLE == true - if (config->mode == SPI_MODE_SLAVE) { - - /* Set frame format */ - ctrla |= config->mode_specific.slave.frame_format; - - /* Set address mode */ - ctrlb |= config->mode_specific.slave.address_mode; - - /* Set address and address mask*/ - addr |= (config->mode_specific.slave.address << SERCOM_SPI_ADDR_ADDR_Pos) | - (config->mode_specific.slave.address_mask << SERCOM_SPI_ADDR_ADDRMASK_Pos); - if (spi_module->CTRLA.reg != addr) { - return STATUS_ERR_DENIED; - } - - if (config->mode_specific.slave.preload_enable) { - /* Enable pre-loading of shift register */ - ctrlb |= SERCOM_SPI_CTRLB_PLOADEN; - } - ctrla |= SERCOM_SPI_CTRLA_MODE(0x2); - } -# endif - /* Set data order */ - ctrla |= config->data_order; - - /* Set clock polarity and clock phase */ - ctrla |= config->transfer_mode; - - /* Set MUX setting */ - ctrla |= config->mux_setting; - - /* Set SPI character size */ - ctrlb |= config->character_size; - - if (config->run_in_standby) { - /* Enable in sleep mode */ - ctrla |= SERCOM_SPI_CTRLA_RUNSTDBY; - } - - if (config->receiver_enable) { - /* Enable receiver */ - ctrlb |= SERCOM_SPI_CTRLB_RXEN; - } - -# ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT - if (config->select_slave_low_detect_enable) { - /* Enable Slave Select Low Detect */ - ctrlb |= SERCOM_SPI_CTRLB_SSDE; - } -# endif -# ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT - if (config->master_slave_select_enable) { - /* Enable Master Slave Select */ - ctrlb |= SERCOM_SPI_CTRLB_MSSEN; - } -# endif - - ctrla |= SERCOM_SPI_CTRLA_ENABLE; - - /* Check that same config is set */ - if (spi_module->CTRLA.reg == ctrla && - spi_module->CTRLB.reg == ctrlb) { - module->mode = config->mode; - module->character_size = config->character_size; - return STATUS_OK; - } - - /* Not same config, wipe module pointer and return */ - module->hw = NULL; - - return STATUS_ERR_DENIED; -} -#endif - -/** - * \brief Initializes the SERCOM SPI module - * - * This function will initialize the SERCOM SPI module, based on the values - * of the config struct. - * - * \param[out] module Pointer to the software instance struct - * \param[in] hw Pointer to hardware instance - * \param[in] config Pointer to the config struct - * - * \return Status of the initialization. - * \retval STATUS_OK Module initiated correctly - * \retval STATUS_ERR_DENIED If module is enabled - * \retval STATUS_BUSY If module is busy resetting - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - */ -enum status_code spi_init( - struct spi_module *const module, - Sercom *const hw, - const struct spi_config *const config) -{ - - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); - - /* Initialize device instance */ - module->hw = hw; - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Check if module is enabled. */ - if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_ENABLE) { -# if SPI_CALLBACK_MODE == false - /* Check if config is valid */ - return _spi_check_config(module, config); -# else - return STATUS_ERR_DENIED; -# endif - } - - /* Check if reset is in progress. */ - if (spi_module->CTRLA.reg & SERCOM_SPI_CTRLA_SWRST){ - return STATUS_BUSY; - } - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index, gclk_index; -#if (SAML21) || (SAMR30) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC21) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC20) || (SAML22) - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - /* Turn on module in PM */ -#if (SAML21) || (SAMR30) - if (sercom_index == 5) { -# ifdef ID_SERCOM5 - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); -# else - return STATUS_ERR_INVALID_ARG; -# endif - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - -# if CONF_SPI_MASTER_ENABLE == true - if (config->mode == SPI_MODE_MASTER) { - /* Set the SERCOM in SPI master mode */ - spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x3); - } -# endif - -# if CONF_SPI_SLAVE_ENABLE == true - if (config->mode == SPI_MODE_SLAVE) { - /* Set the SERCOM in SPI slave mode */ - spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(0x2); - } -# endif - -#if SPI_CALLBACK_MODE == true - /* Temporary variables */ - uint8_t i; - uint8_t instance_index; - - /* Initialize parameters */ - for (i = 0; i < SPI_CALLBACK_N; i++) { - module->callback[i] = NULL; - } - module->tx_buffer_ptr = NULL; - module->rx_buffer_ptr = NULL; - module->remaining_tx_buffer_length = 0x0000; - module->remaining_rx_buffer_length = 0x0000; - module->registered_callback = 0x00; - module->enabled_callback = 0x00; - module->status = STATUS_OK; - module->dir = SPI_DIRECTION_IDLE; - module->locked = false; - /* - * Set interrupt handler and register SPI software module struct in - * look-up table - */ - instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _spi_interrupt_handler); - _sercom_instances[instance_index] = module; -#endif - - /* Write configuration to module and return status code */ - return _spi_set_config(module, config); -} - -/** - * \brief Reads buffer of \c length SPI characters - * - * This function will read a buffer of data from an SPI peripheral by sending - * dummy SPI character if in master mode, or by waiting for data in slave mode. - * - * \note If address matching is enabled for the slave, the first character - * received and placed in the buffer will be the address. - * - * \param[in] module Pointer to the software instance struct - * \param[out] rx_data Data buffer for received data - * \param[in] length Length of data to receive - * \param[in] dummy 8- or 9-bit dummy byte to shift out in master mode - * - * \return Status of the read operation. - * \retval STATUS_OK If the read was completed - * \retval STATUS_ABORTED If transaction was ended by master before - * the entire buffer was transferred - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_TIMEOUT If the operation was not completed within the - * timeout in slave mode - * \retval STATUS_ERR_DENIED If the receiver is not enabled - * \retval STATUS_ERR_OVERFLOW If the data is overflown - */ -enum status_code spi_read_buffer_wait( - struct spi_module *const module, - uint8_t *rx_data, - uint16_t length, - uint16_t dummy) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - -# if SPI_CALLBACK_MODE == true - if (module->status == STATUS_BUSY) { - /* Check if the SPI module is busy with a job */ - return STATUS_BUSY; - } -# endif - - /* Sanity check arguments */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } -# if CONF_SPI_SLAVE_ENABLE == true - if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) { - /* Clear TX complete flag */ - _spi_clear_tx_complete_flag(module); - } -# endif - uint16_t rx_pos = 0; - - while (length--) { -# if CONF_SPI_MASTER_ENABLE == true - if (module->mode == SPI_MODE_MASTER) { - /* Wait until the module is ready to write a character */ - while (!spi_is_ready_to_write(module)) { - } - - /* Send dummy SPI character to read in master mode */ - spi_write(module, dummy); - } -# endif - -# if CONF_SPI_SLAVE_ENABLE == true - /* Start timeout period for slave */ - if (module->mode == SPI_MODE_SLAVE) { - for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) { - if (spi_is_ready_to_read(module)) { - break; - } - } - /* Check if master has ended the transaction */ - if (spi_is_write_complete(module)) { - _spi_clear_tx_complete_flag(module); - return STATUS_ABORTED; - } - - if (!spi_is_ready_to_read(module)) { - /* Not ready to read data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - } -# endif - - /* Wait until the module is ready to read a character */ - while (!spi_is_ready_to_read(module)) { - } - - uint16_t received_data = 0; - enum status_code retval = spi_read(module, &received_data); - - if (retval != STATUS_OK) { - /* Overflow, abort */ - return retval; - } - - /* Read value will be at least 8-bits long */ - rx_data[rx_pos++] = received_data; - - /* If 9-bit data, write next received byte to the buffer */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - rx_data[rx_pos++] = (received_data >> 8); - } - } - - return STATUS_OK; -} - -/** - * \brief Sends and reads a single SPI character - * - * This function will transfer a single SPI character via SPI and return the - * SPI character that is shifted into the shift register. - * - * In master mode the SPI character will be sent immediately and the received - * SPI character will be read as soon as the shifting of the data is - * complete. - * - * In slave mode this function will place the data to be sent into the transmit - * buffer. It will then block until an SPI master has shifted a complete - * SPI character, and the received data is available. - * - * \note The data to be sent might not be sent before the next transfer, as - * loading of the shift register is dependent on SCK. - * \note If address matching is enabled for the slave, the first character - * received and placed in the buffer will be the address. - * - * \param[in] module Pointer to the software instance struct - * \param[in] tx_data SPI character to transmit - * \param[out] rx_data Pointer to store the received SPI character - * - * \return Status of the operation. - * \retval STATUS_OK If the operation was completed - * \retval STATUS_ERR_TIMEOUT If the operation was not completed within the - * timeout in slave mode - * \retval STATUS_ERR_DENIED If the receiver is not enabled - * \retval STATUS_ERR_OVERFLOW If the incoming data is overflown - */ -enum status_code spi_transceive_wait( - struct spi_module *const module, - uint16_t tx_data, - uint16_t *rx_data) -{ - /* Sanity check arguments */ - Assert(module); - - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - -# if SPI_CALLBACK_MODE == true - if (module->status == STATUS_BUSY) { - /* Check if the SPI module is busy with a job */ - return STATUS_BUSY; - } -# endif - -# if CONF_SPI_SLAVE_ENABLE == true - uint16_t j; -# endif - enum status_code retval = STATUS_OK; - -# if CONF_SPI_SLAVE_ENABLE == true - /* Start timeout period for slave */ - if (module->mode == SPI_MODE_SLAVE) { - for (j = 0; j <= SPI_TIMEOUT; j++) { - if (spi_is_ready_to_write(module)) { - break; - } else if (j == SPI_TIMEOUT) { - /* Not ready to write data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - } - } -# endif - /* Wait until the module is ready to write the character */ - while (!spi_is_ready_to_write(module)) { - } - - /* Write data */ - spi_write(module, tx_data); - -# if CONF_SPI_SLAVE_ENABLE == true - /* Start timeout period for slave */ - if (module->mode == SPI_MODE_SLAVE) { - for (j = 0; j <= SPI_TIMEOUT; j++) { - if (spi_is_ready_to_read(module)) { - break; - } else if (j == SPI_TIMEOUT) { - /* Not ready to read data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - } - } -# endif - - /* Wait until the module is ready to read the character */ - while (!spi_is_ready_to_read(module)) { - } - - /* Read data */ - retval = spi_read(module, rx_data); - - return retval; -} - - /** - * \brief Selects slave device - * - * This function will drive the slave select pin of the selected device low or - * high depending on the select Boolean. - * If slave address recognition is enabled, the address will be sent to the - * slave when selecting it. - * - * \param[in] module Pointer to the software module struct - * \param[in] slave Pointer to the attached slave - * \param[in] select Boolean stating if the slave should be selected or - * deselected - * - * \return Status of the operation. - * \retval STATUS_OK If the slave device was selected - * \retval STATUS_ERR_UNSUPPORTED_DEV If the SPI module is operating in slave - * mode - * \retval STATUS_BUSY If the SPI module is not ready to write - * the slave address - */ -enum status_code spi_select_slave( - struct spi_module *const module, - struct spi_slave_inst *const slave, - const bool select) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(slave); - - /* Check that the SPI module is operating in master mode */ - if (module->mode != SPI_MODE_MASTER) { - return STATUS_ERR_UNSUPPORTED_DEV; - } -# ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT - if(!(module->master_slave_select_enable)) -# endif - { - if (select) { - /* Check if address recognition is enabled */ - if (slave->address_enabled) { - /* Check if the module is ready to write the address */ - if (!spi_is_ready_to_write(module)) { - /* Not ready, do not select slave and return */ - port_pin_set_output_level(slave->ss_pin, true); - return STATUS_BUSY; - } - - /* Drive Slave Select low */ - port_pin_set_output_level(slave->ss_pin, false); - - /* Write address to slave */ - spi_write(module, slave->address); - - if (!(module->receiver_enabled)) { - /* Flush contents of shift register shifted back from slave */ - while (!spi_is_ready_to_read(module)) { - } - uint16_t flush = 0; - spi_read(module, &flush); - } - } else { - /* Drive Slave Select low */ - port_pin_set_output_level(slave->ss_pin, false); - } - } else { - /* Drive Slave Select high */ - port_pin_set_output_level(slave->ss_pin, true); - } - } - return STATUS_OK; -} - -/** - * \brief Sends a buffer of \c length SPI characters - * - * This function will send a buffer of SPI characters via the SPI - * and discard any data that is received. To both send and receive a buffer of - * data, use the \ref spi_transceive_buffer_wait function. - * - * Note that this function does not handle the _SS (slave select) pin(s) in - * master mode; this must be handled by the user application. - * - * \param[in] module Pointer to the software instance struct - * \param[in] tx_data Pointer to the buffer to transmit - * \param[in] length Number of SPI characters to transfer - * - * \return Status of the write operation. - * \retval STATUS_OK If the write was completed - * \retval STATUS_ABORTED If transaction was ended by master before - * entire buffer was transferred - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_TIMEOUT If the operation was not completed within the - * timeout in slave mode - */ -enum status_code spi_write_buffer_wait( - struct spi_module *const module, - const uint8_t *tx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - -# if SPI_CALLBACK_MODE == true - if (module->status == STATUS_BUSY) { - /* Check if the SPI module is busy with a job */ - return STATUS_BUSY; - } -# endif - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - -# if CONF_SPI_SLAVE_ENABLE == true - if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) { - /* Clear TX complete flag */ - _spi_clear_tx_complete_flag(module); - } -# endif - - uint16_t tx_pos = 0; - uint16_t flush_length = length; - - /* Write block */ - while (length--) { -# if CONF_SPI_SLAVE_ENABLE == true - /* Start timeout period for slave */ - if (module->mode == SPI_MODE_SLAVE) { - for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) { - if (spi_is_ready_to_write(module)) { - break; - } - } - /* Check if master has ended the transaction */ - if (spi_is_write_complete(module)) { - _spi_clear_tx_complete_flag(module); - return STATUS_ABORTED; - } - - if (!spi_is_ready_to_write(module)) { - /* Not ready to write data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - } -# endif - - /* Wait until the module is ready to write a character */ - while (!spi_is_ready_to_write(module)) { - } - - /* Write value will be at least 8-bits long */ - uint16_t data_to_send = tx_data[tx_pos++]; - - /* If 9-bit data, get next byte to send from the buffer */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - data_to_send |= (tx_data[tx_pos++] << 8); - } - - /* Write the data to send */ - spi_write(module, data_to_send); - - if (module->receiver_enabled) { -# if CONF_SPI_SLAVE_ENABLE == true - /* Start timeout period for slave */ - if (module->mode == SPI_MODE_SLAVE) { - for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) { - if (length && spi_is_ready_to_write(module)) { - data_to_send = tx_data[tx_pos++]; - /* If 9-bit data, get next byte to send from the buffer */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - data_to_send |= (tx_data[tx_pos++] << 8); - } - - /* Write the data to send */ - spi_write(module, data_to_send); - length--; - } - if (spi_is_ready_to_read(module)) { - break; - } - } - - /* Check if master has ended the transaction */ - if (spi_is_write_complete(module)) { - _spi_clear_tx_complete_flag(module); - return STATUS_ABORTED; - } - - if (!spi_is_ready_to_read(module)) { - /* Not ready to read data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - } -# endif - - while (!spi_is_ready_to_read(module)) { - } - - /* Flush read buffer */ - uint16_t flush; - spi_read(module, &flush); - flush_length--; - } - } - -# if CONF_SPI_MASTER_ENABLE == true - if (module->mode == SPI_MODE_MASTER) { - /* Wait for last byte to be transferred */ - while (!spi_is_write_complete(module)) { - } - } -# endif - -# if CONF_SPI_SLAVE_ENABLE == true - if (module->mode == SPI_MODE_SLAVE) { - if (module->receiver_enabled) { - while (flush_length) { - /* Start timeout period for slave */ - for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) { - if (spi_is_ready_to_read(module)) { - break; - } - } - if (!spi_is_ready_to_read(module)) { - /* Not ready to read data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - /* Flush read buffer */ - uint16_t flush; - spi_read(module, &flush); - flush_length--; - } - } - } -# endif - return STATUS_OK; -} - -/** - * \brief Sends and receives a buffer of \c length SPI characters - * - * This function will send and receive a buffer of data via the SPI. - * - * In master mode the SPI characters will be sent immediately and the - * received SPI character will be read as soon as the shifting of the SPI - * character is complete. - * - * In slave mode this function will place the data to be sent into the transmit - * buffer. It will then block until an SPI master has shifted the complete - * buffer and the received data is available. - * - * \param[in] module Pointer to the software instance struct - * \param[in] tx_data Pointer to the buffer to transmit - * \param[out] rx_data Pointer to the buffer where received data will be stored - * \param[in] length Number of SPI characters to transfer - * - * \return Status of the operation. - * \retval STATUS_OK If the operation was completed - * \retval STATUS_ERR_INVALID_ARG If invalid argument(s) were provided - * \retval STATUS_ERR_TIMEOUT If the operation was not completed within the - * timeout in slave mode - * \retval STATUS_ERR_DENIED If the receiver is not enabled - * \retval STATUS_ERR_OVERFLOW If the data is overflown - */ -enum status_code spi_transceive_buffer_wait( - struct spi_module *const module, - uint8_t *tx_data, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - -# if SPI_CALLBACK_MODE == true - if (module->status == STATUS_BUSY) { - /* Check if the SPI module is busy with a job */ - return STATUS_BUSY; - } -# endif - - /* Sanity check arguments */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - -# if CONF_SPI_SLAVE_ENABLE == true - if ((module->mode == SPI_MODE_SLAVE) && (spi_is_write_complete(module))) { - /* Clear TX complete flag */ - _spi_clear_tx_complete_flag(module); - } -# endif - - uint16_t tx_pos = 0; - uint16_t rx_pos = 0; - uint16_t rx_length = length; - - /* Send and receive buffer */ - while (length--) { -# if CONF_SPI_SLAVE_ENABLE == true - /* Start timeout period for slave */ - if (module->mode == SPI_MODE_SLAVE) { - for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) { - if (spi_is_ready_to_write(module)) { - break; - } - } - /* Check if master has ended the transaction */ - if (spi_is_write_complete(module)) { - _spi_clear_tx_complete_flag(module); - return STATUS_ABORTED; - } - - if (!spi_is_ready_to_write(module)) { - /* Not ready to write data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - } -# endif - - /* Wait until the module is ready to write a character */ - while (!spi_is_ready_to_write(module)) { - } - - /* Write value will be at least 8-bits long */ - uint16_t data_to_send = tx_data[tx_pos++]; - - /* If 9-bit data, get next byte to send from the buffer */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - data_to_send |= (tx_data[tx_pos++] << 8); - } - - /* Write the data to send */ - spi_write(module, data_to_send); - -# if CONF_SPI_SLAVE_ENABLE == true - /* Start timeout period for slave */ - if (module->mode == SPI_MODE_SLAVE) { - for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) { - if (spi_is_ready_to_write(module)) { - data_to_send = tx_data[tx_pos++]; - /* If 9-bit data, get next byte to send from the buffer */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - data_to_send |= (tx_data[tx_pos++] << 8); - } - - /* Write the data to send */ - spi_write(module, data_to_send); - length--; - } - if (spi_is_ready_to_read(module)) { - break; - } - } - /* Check if master has ended the transaction */ - if (spi_is_write_complete(module)) { - _spi_clear_tx_complete_flag(module); - return STATUS_ABORTED; - } - - if (!spi_is_ready_to_read(module)) { - /* Not ready to read data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - } -# endif - - /* Wait until the module is ready to read a character */ - while (!spi_is_ready_to_read(module)) { - } - - enum status_code retval; - uint16_t received_data = 0; - rx_length--; - - retval = spi_read(module, &received_data); - - if (retval != STATUS_OK) { - /* Overflow, abort */ - return retval; - } - - /* Read value will be at least 8-bits long */ - rx_data[rx_pos++] = received_data; - - /* If 9-bit data, write next received byte to the buffer */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - rx_data[rx_pos++] = (received_data >> 8); - } - } - -# if CONF_SPI_MASTER_ENABLE == true - if (module->mode == SPI_MODE_MASTER) { - /* Wait for last byte to be transferred */ - while (!spi_is_write_complete(module)) { - } - } -# endif - -# if CONF_SPI_SLAVE_ENABLE == true - if (module->mode == SPI_MODE_SLAVE) { - while (rx_length) { - /* Start timeout period for slave */ - for (uint32_t i = 0; i <= SPI_TIMEOUT; i++) { - if (spi_is_ready_to_read(module)) { - break; - } - } - if (!spi_is_ready_to_read(module)) { - /* Not ready to read data within timeout period */ - return STATUS_ERR_TIMEOUT; - } - enum status_code retval; - uint16_t received_data = 0; - rx_length--; - - retval = spi_read(module, &received_data); - - if (retval != STATUS_OK) { - /* Overflow, abort */ - return retval; - } - /* Read value will be at least 8-bits long */ - rx_data[rx_pos++] = received_data; - - /* If 9-bit data, write next received byte to the buffer */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - rx_data[rx_pos++] = (received_data >> 8); - } - } - } -# endif - return STATUS_OK; -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi/spi.h b/atmel-samd/asf/sam0/drivers/sercom/spi/spi.h deleted file mode 100644 index 01d21a21ee7de..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi/spi.h +++ /dev/null @@ -1,1807 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SPI_H_INCLUDED -#define SPI_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_sercom_spi_group SAM Serial Peripheral Interface (SERCOM SPI) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the SERCOM module in - * its SPI mode to transfer SPI data frames. The following driver API modes - * are covered by this manual: - * - * - Polled APIs - * \if SPI_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - SERCOM (Serial Communication Interface) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - Atmel | SMART SAM R30 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_sercom_spi_prerequisites - * - \ref asfdoc_sam0_sercom_spi_module_overview - * - \ref asfdoc_sam0_sercom_spi_special_considerations - * - \ref asfdoc_sam0_sercom_spi_extra_info - * - \ref asfdoc_sam0_sercom_spi_examples - * - \ref asfdoc_sam0_sercom_spi_api_overview - * - * \section asfdoc_sam0_sercom_spi_prerequisites Prerequisites - * There are no prerequisites. - * - * - * \section asfdoc_sam0_sercom_spi_module_overview Module Overview - * The Serial Peripheral Interface (SPI) is a high-speed synchronous data - * transfer interface using three or four pins. It allows fast communication - * between a master device and one or more peripheral devices. - * - * A device connected to the bus must act as a master or a slave. The master - * initiates and controls all data transactions. - * The SPI master initiates a communication cycle by pulling low the Slave - * Select (SS) pin of the desired slave. The Slave Select pin is active low. - * Master and slave prepare data to be sent in their respective shift - * registers, and the master generates the required clock pulses on the SCK - * line to interchange data. Data is always shifted from master to slave on - * the Master Out - Slave In (MOSI) line, and from slave to master on the - * Master In - Slave Out (MISO) line. After each data transfer, the master can - * synchronize to the slave by pulling the SS line high. - * - * \subsection asfdoc_sam0_sercom_spi_module_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver feature macroSupported devices
FEATURE_SPI_SLAVE_SELECT_LOW_DETECTSAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30
FEATURE_SPI_HARDWARE_SLAVE_SELECTSAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30
FEATURE_SPI_ERROR_INTERRUPTSAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30
FEATURE_SPI_SYNC_SCHEME_VERSION_2SAM D21/R21/D10/D11/L21/L22/DA1/C20/C21/R30
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_sercom_spi_bus SPI Bus Connection - * In \ref asfdoc_sam0_spi_connection_example "the figure below", the - * connection between one master and one slave is shown. - * - * \anchor asfdoc_sam0_spi_connection_example - * \dot - * digraph spi_slaves_par { - * subgraph cluster_spi_master { - * shift_reg [label="Shift register", shape=box]; - * mosi_m [label="MOSI", shape=none]; - * miso_m [label="MISO", shape=none]; - * sck_m [label="SCK", shape=none]; - * ss_m [label="GPIO pin", shape=none]; - * {rank=same; mosi_m miso_m sck_m ss_m} - * label="SPI Master"; - * } - * subgraph cluster_spi_slave { - * mosi_s [label="MOSI", shape=none]; - * miso_s [label="MISO", shape=none]; - * sck_s [label="SCK", shape=none]; - * ss_s [label="SS", shape=none]; - * shift_reg_s [label="Shift register", shape=box]; - * {rank=same; mosi_s miso_s sck_s ss_s} - * label="SPI Slave"; - * rankdir=LR; - * } - * shift_reg:e -> mosi_m:w [label=""]; - * mosi_m:e -> mosi_s:w [label=""]; - * mosi_s:e -> shift_reg_s:w [label=""]; - * miso_s:w -> miso_m:e [label=""]; - * sck_m -> sck_s; - * ss_m -> ss_s; - * shift_reg_s:se -> miso_s:e [label=""]; - * miso_m:w -> shift_reg:sw [label=""]; - * rankdir=LR; - * } - * \enddot - * - * The different lines are as follows: - * - \b MISO Master Input Slave Output. The line where the data is shifted - * out from the slave and into the master. - * - \b MOSI Master Output Slave Input. The line where the data is shifted - * out from the master and into the slave. - * - \b SCK Serial Clock. Generated by the master device. - * - \b SS Slave Select. To initiate a transaction, the master must pull this - * line low. - * - * If the bus consists of several SPI slaves, they can be connected in parallel - * and the SPI master can use general I/O pins to control separate SS lines to - * each slave on the bus. - * - * It is also possible to connect all slaves in series. In this configuration, - * a common SS is provided to \c N slaves, enabling them simultaneously. The - * MISO from the \c N-1 slaves is connected to the MOSI on the next slave. The - * \c Nth slave connects its MISO back to the master. For a - * complete transaction, the master must shift \c N+1 characters. - * - * \subsection asfdoc_sam0_sercom_spi_chsize SPI Character Size - * The SPI character size is configurable to eight or nine bits. - * - * \subsection asfdoc_sam0_sercom_spi_master_mode Master Mode - * When configured as a master, the SS pin will be configured as an output. - * - * \subsubsection asfdoc_sam0_sercom_spi_master_mode_data_transfer Data Transfer - * Writing a character will start the SPI clock generator, and - * the character is transferred to the shift register when the shift - * register is empty. - * Once this is done, a new character can be written. - * As each character is shifted out from the master, a character is shifted in - * from the slave. If the receiver is enabled, the data is moved to the receive - * buffer at the completion of the frame and can be read. - * - * \subsection asfdoc_sam0_sercom_spi_slave_mode Slave Mode - * When configured as a slave, the SPI interface will remain inactive with MISO - * tri-stated as long as the SS pin is driven high. - * - * \subsubsection asfdoc_sam0_sercom_spi_slave_mode_data_transfer_slave Data Transfer - * The data register can be updated at any time. - * As the SPI slave shift register is clocked by SCK, a minimum of three SCK - * cycles are needed from the time new data is written, until the character is - * ready to be shifted out. If the shift register has not been loaded with - * data, the current contents will be transmitted. - * - * If constant transmission of data is needed in SPI slave mode, the system - * clock should be faster than SCK. - * If the receiver is enabled, the received character can be read from the - * receive buffer. When SS line is driven high, the slave will not receive any - * additional data. - * - * \subsubsection asfdoc_sam0_sercom_spi_slave_mode_addr_recognition Address Recognition - * When the SPI slave is configured with address recognition, the first - * character in a transaction is checked for an address match. If there is a - * match, the MISO output is enabled and the transaction is processed. - * If the address does not match, the complete transaction is ignored. - * - * If the device is asleep, it can be woken up by an address match in order - * to process the transaction. - * - * \note In master mode, an address packet is written by the - * \ref spi_select_slave function if the address_enabled configuration is - * set in the \ref spi_slave_inst_config struct. - * - * \subsection asfdoc_sam0_sercom_spi_data_modes Data Modes - * There are four combinations of SCK phase and polarity with respect to - * serial data. \ref asfdoc_sam0_spi_mode_table "The table below" shows the - * clock polarity (CPOL) and clock phase (CPHA) in the different modes. - * Leading edge is the first clock edge in a clock cycle and - * trailing edge is the last clock edge in a clock cycle. - * - * \anchor asfdoc_sam0_spi_mode_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
SPI Data Modes
ModeCPOLCPHALeading EdgeTrailing Edge
0 0 0 Rising, Sample Falling, Setup
1 0 1 Rising, Setup Falling, Sample
2 1 0 Falling, Sample Rising, Setup
3 1 1 Falling, Setup Rising, Sample
- * - * - * \subsection asfdoc_sam0_sercom_spi_pads SERCOM Pads - * The SERCOM pads are automatically configured as seen in - * \ref asfdoc_sam0_spi_sercom_pad_table "the table below". If the receiver - * is disabled, the data input (MISO for master, MOSI for slave) can be used - * for other purposes. - * - * In master mode, the SS pin(s) must be configured using the \ref spi_slave_inst - * struct. - * - * \anchor asfdoc_sam0_spi_sercom_pad_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
SERCOM SPI Pad Usages
Pin Master SPI Slave SPI
MOSI Output Input
MISO Input Output
SCK Output Input
SS User defined output enable Input
- * - * \subsection asfdoc_sam0_sercom_spi_sleep_modes Operation in Sleep Modes - * The SPI module can operate in all sleep modes by setting the run_in_standby - * option in the \ref spi_config struct. The operation in slave and master mode - * is shown in the table below. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
run_in_standby Slave Master
false Disabled, all reception is dropped GCLK is disabled when master is idle, wake on transmit complete
true Wake on reception GCLK is enabled while in sleep modes, wake on all interrupts
- * - * \subsection asfdoc_sam0_sercom_spi_clock_generation Clock Generation - * In SPI master mode, the clock (SCK) is generated internally using the - * SERCOM baudrate generator. In SPI slave mode, the clock is provided by - * an external master on the SCK pin. This clock is used to directly clock - * the SPI shift register. - * - * \section asfdoc_sam0_sercom_spi_special_considerations Special Considerations - * \subsection pin_mux pinmux Settings - * The pin MUX settings must be configured properly, as not all settings - * can be used in different modes of operation. - * - * \section asfdoc_sam0_sercom_spi_extra_info Extra Information - * For extra information, see \ref asfdoc_sam0_sercom_spi_extra. This includes: - * - \ref asfdoc_sam0_sercom_spi_extra_acronyms - * - \ref asfdoc_sam0_sercom_spi_extra_dependencies - * - \ref asfdoc_sam0_sercom_spi_extra_workarounds - * - \ref asfdoc_sam0_sercom_spi_extra_history - * - * \section asfdoc_sam0_sercom_spi_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_sercom_spi_exqsg. - * - * \section asfdoc_sam0_sercom_spi_api_overview API Overview - * @{ - */ - -#include -#include -#include -#include -#include -#include - -# if SPI_CALLBACK_MODE == true -# include -# endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if (CONF_SPI_MASTER_ENABLE == false) && (CONF_SPI_SLAVE_ENABLE == false) -#error "Not possible compile SPI driver, invalid driver configuration. Make sure that either/both CONF_SPI_MASTER_ENABLE/CONF_SPI_SLAVE_ENABLE is set to true." -#endif - -/** - * \name Driver Feature Definition - * Define SERCOM SPI features set according to different device family. - * @{ - */ -# if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAML21) || (SAMDA1) || \ - (SAML22) || (SAMC20) || (SAMC21) || (SAMD09) || (SAMR30) || defined(__DOXYGEN__) -/** SPI slave select low detection. */ -# define FEATURE_SPI_SLAVE_SELECT_LOW_DETECT -/** Slave select can be controlled by hardware. */ -# define FEATURE_SPI_HARDWARE_SLAVE_SELECT -/** SPI with error detect feature. */ -# define FEATURE_SPI_ERROR_INTERRUPT -/** SPI sync scheme version 2. */ -# define FEATURE_SPI_SYNC_SCHEME_VERSION_2 -# endif -/*@}*/ - -# ifndef PINMUX_DEFAULT -/** Default pinmux. */ -# define PINMUX_DEFAULT 0 -# endif - -# ifndef PINMUX_UNUSED -/** Unused pinmux. */ -# define PINMUX_UNUSED 0xFFFFFFFF -# endif - -# ifndef SPI_TIMEOUT -/** SPI timeout value. */ -# define SPI_TIMEOUT 10000 -# endif - -# if SPI_CALLBACK_MODE == true -/** - * \brief SPI Callback enum - * - * Callbacks for SPI callback driver. - * - * \note For slave mode, these callbacks will be called when a transaction - * is ended by the master pulling Slave Select high. - * - */ -enum spi_callback { - /** Callback for buffer transmitted */ - SPI_CALLBACK_BUFFER_TRANSMITTED, - /** Callback for buffer received */ - SPI_CALLBACK_BUFFER_RECEIVED, - /** Callback for buffers transceived */ - SPI_CALLBACK_BUFFER_TRANSCEIVED, - /** Callback for error */ - SPI_CALLBACK_ERROR, - /** - * Callback for transmission ended by master before the entire buffer was - * read or written from slave - */ - SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE, -# ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT - /** Callback for slave select low */ - SPI_CALLBACK_SLAVE_SELECT_LOW, -# endif -# ifdef FEATURE_SPI_ERROR_INTERRUPT - /** Callback for combined error happen */ - SPI_CALLBACK_COMBINED_ERROR, -# endif -# if !defined(__DOXYGEN__) - /** Number of available callbacks */ - SPI_CALLBACK_N, -# endif -}; -# endif - -#if SPI_CALLBACK_MODE == true -# if !defined(__DOXYGEN__) -/** - * \internal SPI transfer directions - */ -enum _spi_direction { - /** Transfer direction is read */ - SPI_DIRECTION_READ, - /** Transfer direction is write */ - SPI_DIRECTION_WRITE, - /** Transfer direction is read and write */ - SPI_DIRECTION_BOTH, - /** No transfer */ - SPI_DIRECTION_IDLE, -}; -# endif -#endif - -/** - * \brief SPI Interrupt Flags - * - * Interrupt flags for the SPI module. - * - */ -enum spi_interrupt_flag { - /** - * This flag is set when the contents of the data register has been moved - * to the shift register and the data register is ready for new data - */ - SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY = SERCOM_SPI_INTFLAG_DRE, - /** - * This flag is set when the contents of the shift register has been - * shifted out - */ - SPI_INTERRUPT_FLAG_TX_COMPLETE = SERCOM_SPI_INTFLAG_TXC, - /** This flag is set when data has been shifted into the data register */ - SPI_INTERRUPT_FLAG_RX_COMPLETE = SERCOM_SPI_INTFLAG_RXC, -# ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT - /** This flag is set when slave select low */ - SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW = SERCOM_SPI_INTFLAG_SSL, -# endif -# ifdef FEATURE_SPI_ERROR_INTERRUPT - /** This flag is set when combined error happen */ - SPI_INTERRUPT_FLAG_COMBINED_ERROR = SERCOM_SPI_INTFLAG_ERROR, -# endif -}; - -/** - * \brief SPI transfer modes enum - * - * SPI transfer mode. - */ -enum spi_transfer_mode { - /** Mode 0. Leading edge: rising, sample. Trailing edge: falling, setup */ - SPI_TRANSFER_MODE_0 = 0, - /** Mode 1. Leading edge: rising, setup. Trailing edge: falling, sample */ - SPI_TRANSFER_MODE_1 = SERCOM_SPI_CTRLA_CPHA, - /** Mode 2. Leading edge: falling, sample. Trailing edge: rising, setup */ - SPI_TRANSFER_MODE_2 = SERCOM_SPI_CTRLA_CPOL, - /** Mode 3. Leading edge: falling, setup. Trailing edge: rising, sample */ - SPI_TRANSFER_MODE_3 = SERCOM_SPI_CTRLA_CPHA | SERCOM_SPI_CTRLA_CPOL, -}; - -/** - * \brief SPI frame format enum - * - * Frame format for slave mode. - */ -enum spi_frame_format { - /** SPI frame */ - SPI_FRAME_FORMAT_SPI_FRAME = SERCOM_SPI_CTRLA_FORM(0), - /** SPI frame with address */ - SPI_FRAME_FORMAT_SPI_FRAME_ADDR = SERCOM_SPI_CTRLA_FORM(2), -}; - -/** - * \brief SPI signal MUX settings - * - * Set the functionality of the SERCOM pins. As not all combinations can be used - * in different modes of operation, proper combinations must be chosen according - * to the rest of the configuration. - * - * \note In master operation: DI is MISO, DO is MOSI. - * In slave operation: DI is MOSI, DO is MISO. - * - * See \ref asfdoc_sam0_sercom_spi_mux_settings for a description of the - * various MUX setting options. - */ -enum spi_signal_mux_setting { - /** SPI MUX combination A. DOPO: 0x0, DIPO: 0x0 */ - SPI_SIGNAL_MUX_SETTING_A = - (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination B. DOPO: 0x0, DIPO: 0x1 */ - SPI_SIGNAL_MUX_SETTING_B = - (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination C. DOPO: 0x0, DIPO: 0x2 */ - SPI_SIGNAL_MUX_SETTING_C = - (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination D. DOPO: 0x0, DIPO: 0x3 */ - SPI_SIGNAL_MUX_SETTING_D = - (0x0 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination E. DOPO: 0x1, DIPO: 0x0 */ - SPI_SIGNAL_MUX_SETTING_E = - (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination F. DOPO: 0x1, DIPO: 0x1 */ - SPI_SIGNAL_MUX_SETTING_F = - (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination G. DOPO: 0x1, DIPO: 0x2 */ - SPI_SIGNAL_MUX_SETTING_G = - (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination H. DOPO: 0x1, DIPO: 0x3 */ - SPI_SIGNAL_MUX_SETTING_H = - (0x1 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination I. DOPO: 0x2, DIPO: 0x0 */ - SPI_SIGNAL_MUX_SETTING_I = - (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination J. DOPO: 0x2, DIPO: 0x1 */ - SPI_SIGNAL_MUX_SETTING_J = - (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination K. DOPO: 0x2, DIPO: 0x2 */ - SPI_SIGNAL_MUX_SETTING_K = - (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination L. DOPO: 0x2, DIPO: 0x3 */ - SPI_SIGNAL_MUX_SETTING_L = - (0x2 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination M. DOPO: 0x3, DIPO: 0x0 */ - SPI_SIGNAL_MUX_SETTING_M = - (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x0 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination N. DOPO: 0x3, DIPO: 0x1 */ - SPI_SIGNAL_MUX_SETTING_N = - (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x1 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination O. DOPO: 0x3, DIPO: 0x2 */ - SPI_SIGNAL_MUX_SETTING_O = - (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x2 << SERCOM_SPI_CTRLA_DIPO_Pos), - /** SPI MUX combination P. DOPO: 0x3, DIPO: 0x3 */ - SPI_SIGNAL_MUX_SETTING_P = - (0x3 << SERCOM_SPI_CTRLA_DOPO_Pos) | - (0x3 << SERCOM_SPI_CTRLA_DIPO_Pos), -}; - -/** - * \brief SPI address modes enum - * - * For slave mode when using the SPI frame with address format. - * - */ -enum spi_addr_mode { - /** - * \c address_mask in the \ref spi_config struct is used as a mask to the register - */ - SPI_ADDR_MODE_MASK = SERCOM_SPI_CTRLB_AMODE(0), - /** - * The slave responds to the two unique addresses in \c address and - * \c address_mask in the \ref spi_config struct - */ - SPI_ADDR_MODE_UNIQUE = SERCOM_SPI_CTRLB_AMODE(1), - /** - * The slave responds to the range of addresses between and including \c address - * and \c address_mask in the \ref spi_config struct - */ - SPI_ADDR_MODE_RANGE = SERCOM_SPI_CTRLB_AMODE(2), -}; - -/** - * \brief SPI modes enum - * - * SPI mode selection. - */ -enum spi_mode { - /** Master mode */ - SPI_MODE_MASTER = 1, - /** Slave mode */ - SPI_MODE_SLAVE = 0, -}; - -/** - * \brief SPI data order enum - * - * SPI data order. - * - */ -enum spi_data_order { - /** The LSB of the data is transmitted first */ - SPI_DATA_ORDER_LSB = SERCOM_SPI_CTRLA_DORD, - /** The MSB of the data is transmitted first */ - SPI_DATA_ORDER_MSB = 0, -}; - -/** - * \brief SPI character size enum - * - * SPI character size. - * - */ -enum spi_character_size { - /** 8-bit character */ - SPI_CHARACTER_SIZE_8BIT = SERCOM_SPI_CTRLB_CHSIZE(0), - /** 9-bit character */ - SPI_CHARACTER_SIZE_9BIT = SERCOM_SPI_CTRLB_CHSIZE(1), -}; - -# if SPI_CALLBACK_MODE == true -/** Prototype for the device instance */ -struct spi_module; - -/** Type of the callback functions */ -typedef void (*spi_callback_t)(struct spi_module *const module); - -# if !defined(__DOXYGEN__) -/** Prototype for the interrupt handler */ -extern void _spi_interrupt_handler(uint8_t instance); -# endif -# endif - -/** - * \brief SERCOM SPI driver software device instance structure. - * - * SERCOM SPI driver software instance structure, used to retain software state - * information of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct spi_module { -# if !defined(__DOXYGEN__) - /** SERCOM hardware module */ - Sercom *hw; - /** Module lock */ - volatile bool locked; - /** SPI mode */ - enum spi_mode mode; - /** SPI character size */ - enum spi_character_size character_size; - /** Receiver enabled */ - bool receiver_enabled; -# ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT - /** Enable Hardware Slave Select */ - bool master_slave_select_enable; -# endif -# if SPI_CALLBACK_MODE == true - /** Direction of transaction */ - volatile enum _spi_direction dir; - /** Array to store callback function pointers in */ - spi_callback_t callback[SPI_CALLBACK_N]; - /** Buffer pointer to where the next received character will be put */ - volatile uint8_t *rx_buffer_ptr; - /** Buffer pointer to where the next character will be transmitted from - **/ - volatile uint8_t *tx_buffer_ptr; - /** Remaining characters to receive */ - volatile uint16_t remaining_rx_buffer_length; - /** Remaining dummy characters to send when reading */ - volatile uint16_t remaining_dummy_buffer_length; - /** Remaining characters to transmit */ - volatile uint16_t remaining_tx_buffer_length; - /** Bit mask for callbacks registered */ - uint8_t registered_callback; - /** Bit mask for callbacks enabled */ - uint8_t enabled_callback; - /** Holds the status of the ongoing or last operation */ - volatile enum status_code status; -# endif -# endif -}; - -/** - * \brief SPI peripheral slave instance structure - * - * SPI peripheral slave software instance structure, used to configure the - * correct SPI transfer mode settings for an attached slave. See - * \ref spi_select_slave. - */ -struct spi_slave_inst { - /** Pin to use as slave select */ - uint8_t ss_pin; - /** Address recognition enabled in slave device */ - bool address_enabled; - /** Address of slave device */ - uint8_t address; -}; - -/** - * \brief SPI peripheral slave configuration structure - * - * SPI Peripheral slave configuration structure. - */ -struct spi_slave_inst_config { - /** Pin to use as slave select */ - uint8_t ss_pin; - /** Enable address */ - bool address_enabled; - /** Address of slave */ - uint8_t address; -}; - -/** - * \brief SPI Master configuration structure - * - * SPI Master configuration structure. - */ -struct spi_master_config { - /** Baud rate */ - uint32_t baudrate; -}; - -/** - * \brief SPI slave configuration structure - * - * SPI slave configuration structure. - */ -struct spi_slave_config { - /** Frame format */ - enum spi_frame_format frame_format; - /** Address mode */ - enum spi_addr_mode address_mode; - /** Address */ - uint8_t address; - /** Address mask */ - uint8_t address_mask; - /** Preload data to the shift register while SS is high */ - bool preload_enable; -}; - -/** - * \brief SPI configuration structure - * - * Configuration structure for an SPI instance. This structure should be - * initialized by the \ref spi_get_config_defaults function before being - * modified by the user application. - */ -struct spi_config { - /** SPI mode */ - enum spi_mode mode; - /** Data order */ - enum spi_data_order data_order; - /** Transfer mode */ - enum spi_transfer_mode transfer_mode; - /** MUX setting */ - enum spi_signal_mux_setting mux_setting; - /** SPI character size */ - enum spi_character_size character_size; - /** Enabled in sleep modes */ - bool run_in_standby; - /** Enable receiver */ - bool receiver_enable; -# ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT - /** Enable Slave Select Low Detect */ - bool select_slave_low_detect_enable; -# endif -# ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT - /** Enable Master Slave Select */ - bool master_slave_select_enable; -# endif - /** Union for slave or master specific configuration */ - union { - /** Slave specific configuration */ - struct spi_slave_config slave; - /** Master specific configuration */ - struct spi_master_config master; - } mode_specific; - /** GCLK generator to use as clock source */ - enum gclk_generator generator_source; - /** PAD0 pinmux */ - uint32_t pinmux_pad0; - /** PAD1 pinmux */ - uint32_t pinmux_pad1; - /** PAD2 pinmux */ - uint32_t pinmux_pad2; - /** PAD3 pinmux */ - uint32_t pinmux_pad3; -}; - -/** - * \brief Determines if the SPI module is currently synchronizing to the bus. - * - * This function will check if the underlying hardware peripheral module is - * currently synchronizing across multiple clock domains to the hardware bus. - * This function can be used to delay further operations on the module until it - * is ready. - * - * \param[in] module SPI hardware module - * - * \return Synchronization status of the underlying hardware module. - * \retval true Module synchronization is ongoing - * \retval false Module synchronization is not ongoing - * - */ -static inline bool spi_is_syncing( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - -# ifdef FEATURE_SPI_SYNC_SCHEME_VERSION_2 - /* Return synchronization status */ - return (spi_module->SYNCBUSY.reg); -# else - /* Return synchronization status */ - return (spi_module->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY); -# endif -} - -/** - * \name Driver Initialization and Configuration - * @{ - */ - -/** - * \brief Initializes an SPI configuration structure to default values - * - * This function will initialize a given SPI configuration structure to a set - * of known default values. This function should be called on any new - * instance of the configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Master mode enabled - * \li MSB of the data is transmitted first - * \li Transfer mode 0 - * \li MUX Setting D - * \li Character size eight bits - * \li Not enabled in sleep mode - * \li Receiver enabled - * \li Baudrate 100000 - * \li Default pinmux settings for all pads - * \li GCLK generator 0 - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void spi_get_config_defaults( - struct spi_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->mode = SPI_MODE_MASTER; - config->data_order = SPI_DATA_ORDER_MSB; - config->transfer_mode = SPI_TRANSFER_MODE_0; - config->mux_setting = SPI_SIGNAL_MUX_SETTING_D; - config->character_size = SPI_CHARACTER_SIZE_8BIT; - config->run_in_standby = false; - config->receiver_enable = true; -# ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT - config->select_slave_low_detect_enable= true; -# endif -# ifdef FEATURE_SPI_HARDWARE_SLAVE_SELECT - config->master_slave_select_enable= false; -# endif - config->generator_source = GCLK_GENERATOR_0; - - /* Clear mode specific config */ - memset(&(config->mode_specific), 0, sizeof(config->mode_specific)); - - /* Master config defaults */ - config->mode_specific.master.baudrate = 100000; - - /* pinmux config defaults */ - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->pinmux_pad2 = PINMUX_DEFAULT; - config->pinmux_pad3 = PINMUX_DEFAULT; - -}; - -/** - * \brief Initializes an SPI peripheral slave device configuration structure to default values - * - * This function will initialize a given SPI slave device configuration - * structure to a set of known default values. This function should be called - * on any new instance of the configuration structures before being modified by - * the user application. - * - * The default configuration is as follows: - * \li Slave Select on GPIO pin 10 - * \li Addressing not enabled - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void spi_slave_inst_get_config_defaults( - struct spi_slave_inst_config *const config) -{ - Assert(config); - - config->ss_pin = 10; - config->address_enabled = false; - config->address = 0; -} - -/** - * \brief Attaches an SPI peripheral slave - * - * This function will initialize the software SPI peripheral slave, based on - * the values of the config struct. The slave can then be selected and - * optionally addressed by the \ref spi_select_slave function. - * - * \param[out] slave Pointer to the software slave instance struct - * \param[in] config Pointer to the config struct - * - */ -static inline void spi_attach_slave( - struct spi_slave_inst *const slave, - const struct spi_slave_inst_config *const config) -{ - Assert(slave); - Assert(config); - - slave->ss_pin = config->ss_pin; - slave->address_enabled = config->address_enabled; - slave->address = config->address; - - /* Get default config for pin */ - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - /* Edit config to set the pin as output */ - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - - /* Set config on Slave Select pin */ - port_pin_set_config(slave->ss_pin, &pin_conf); - port_pin_set_output_level(slave->ss_pin, true); -} - -enum status_code spi_init( - struct spi_module *const module, - Sercom *const hw, - const struct spi_config *const config); - -/** @} */ - -/** - * \name Enable/Disable - * @{ - */ - -/** - * \brief Enables the SERCOM SPI module - * - * This function will enable the SERCOM SPI module. - * - * \param[in,out] module Pointer to the software instance struct - */ -static inline void spi_enable( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - -# if SPI_CALLBACK_MODE == true - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); -# endif - - while (spi_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } - - /* Enable SPI */ - spi_module->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; -} - -/** - * \brief Disables the SERCOM SPI module - * - * This function will disable the SERCOM SPI module. - * - * \param[in,out] module Pointer to the software instance struct - */ -static inline void spi_disable( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - -# if SPI_CALLBACK_MODE == true - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); -# endif - - while (spi_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } - - /* Disbale interrupt */ - spi_module->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK; - /* Clear interrupt flag */ - spi_module->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK; - - /* Disable SPI */ - spi_module->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; -} - -void spi_reset( - struct spi_module *const module); - -/** @} */ - -enum status_code spi_set_baudrate( - struct spi_module *const module, - uint32_t baudrate); - -/** - * \name Lock/Unlock - * @{ - */ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline enum status_code spi_lock(struct spi_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline void spi_unlock(struct spi_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \name Ready to Write/Read - * @{ - */ - - /** - * \brief Checks if the SPI in master mode has shifted out last data, or if the master has ended the transfer in slave mode. - * - * This function will check if the SPI master module has shifted out last data, - * or if the slave select pin has been drawn high by the master for the SPI - * slave module. - * - * \param[in] module Pointer to the software instance struct - * - * \return Indication of whether any writes are ongoing. - * \retval true If the SPI master module has shifted out data, or slave select - * has been drawn high for SPI slave - * \retval false If the SPI master module has not shifted out data - */ -static inline bool spi_is_write_complete( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Check interrupt flag */ - return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC); -} - - /** - * \brief Checks if the SPI module is ready to write data - * - * This function will check if the SPI module is ready to write data. - * - * \param[in] module Pointer to the software instance struct - * - * \return Indication of whether the module is ready to read data or not. - * \retval true If the SPI module is ready to write data - * \retval false If the SPI module is not ready to write data - */ -static inline bool spi_is_ready_to_write( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Check interrupt flag */ - return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE); -} - -/** - * \brief Checks if the SPI module is ready to read data - * - * This function will check if the SPI module is ready to read data. - * - * \param[in] module Pointer to the software instance struct - * - * \return Indication of whether the module is ready to read data or not. - * \retval true If the SPI module is ready to read data - * \retval false If the SPI module is not ready to read data - */ -static inline bool spi_is_ready_to_read( - struct spi_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Check interrupt flag */ - return (spi_module->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC); -} -/** @} */ - -/** - * \name Read/Write - * @{ - */ - - /** - * \brief Transfers a single SPI character - * - * This function will send a single SPI character via SPI and ignore any data - * shifted in by the connected device. To both send and receive data, use the - * \ref spi_transceive_wait function or use the \ref spi_read function after - * writing a character. The \ref spi_is_ready_to_write function - * should be called before calling this function. - * - * Note that this function does not handle the SS (Slave Select) - * pin(s) in master mode; this must be handled from the user application. - * - * \note In slave mode, the data will not be transferred before a master - * initiates a transaction. - * - * \param[in] module Pointer to the software instance struct - * \param[in] tx_data Data to transmit - * - * \return Status of the procedure. - * \retval STATUS_OK If the data was written - * \retval STATUS_BUSY If the last write was not completed - */ -static inline enum status_code spi_write( - struct spi_module *module, - uint16_t tx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Check if the data register has been copied to the shift register */ - if (!spi_is_ready_to_write(module)) { - /* Data register has not been copied to the shift register, return */ - return STATUS_BUSY; - } - - /* Write the character to the DATA register */ - spi_module->DATA.reg = tx_data & SERCOM_SPI_DATA_MASK; - - return STATUS_OK; -} - -enum status_code spi_write_buffer_wait( - struct spi_module *const module, - const uint8_t *tx_data, - uint16_t length); - -/** - * \brief Reads last received SPI character - * - * This function will return the last SPI character shifted into the receive - * register by the \ref spi_write function. - * - * \note The \ref spi_is_ready_to_read function should be called before calling - * this function. - * - * \note Receiver must be enabled in the configuration. - * - * \param[in] module Pointer to the software instance struct - * \param[out] rx_data Pointer to store the received data - * - * \returns Status of the read operation. - * \retval STATUS_OK If data was read - * \retval STATUS_ERR_IO If no data is available - * \retval STATUS_ERR_OVERFLOW If the data is overflown - */ -static inline enum status_code spi_read( - struct spi_module *const module, - uint16_t *rx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomSpi *const spi_module = &(module->hw->SPI); - - /* Check if data is ready to be read */ - if (!spi_is_ready_to_read(module)) { - /* No data has been received, return */ - return STATUS_ERR_IO; - } - - /* Return value */ - enum status_code retval = STATUS_OK; - - /* Check if data is overflown */ - if (spi_module->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { - retval = STATUS_ERR_OVERFLOW; - /* Clear overflow flag */ - spi_module->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; - } - - /* Read the character from the DATA register */ - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - *rx_data = (spi_module->DATA.reg & SERCOM_SPI_DATA_MASK); - } else { - *rx_data = (uint8_t)spi_module->DATA.reg; - } - - return retval; -} - -enum status_code spi_read_buffer_wait( - struct spi_module *const module, - uint8_t *rx_data, - uint16_t length, - uint16_t dummy); - -enum status_code spi_transceive_wait( - struct spi_module *const module, - uint16_t tx_data, - uint16_t *rx_data); - -enum status_code spi_transceive_buffer_wait( - struct spi_module *const module, - uint8_t *tx_data, - uint8_t *rx_data, - uint16_t length); - -enum status_code spi_select_slave( - struct spi_module *const module, - struct spi_slave_inst *const slave, - bool select); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - - -/** - * \page asfdoc_sam0_sercom_spi_extra Extra Information for SERCOM SPI Driver - * - * \section asfdoc_sam0_sercom_spi_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
SERCOMSerial Communication Interface
SPISerial Peripheral Interface
SCKSerial Clock
MOSIMaster Output Slave Input
MISOMaster Input Slave Output
SSSlave Select
DIOData Input Output
DOData Output
DIData Input
DMADirect Memory Access
- * - * \section asfdoc_sam0_sercom_spi_extra_dependencies Dependencies - * The SPI driver has the following dependencies: - * \li \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_sercom_spi_extra_workarounds Workarounds Implemented by Driver - * No workarounds in driver. - * - * \section asfdoc_sam0_sercom_spi_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added new features as below: - * \li Slave select low detect - * \li Hardware slave select - * \li DMA support
Edited slave part of write and transceive buffer functions to ensure - * that second character is sent at the right time
Renamed the anonymous union in \c struct spi_config to - * \c mode_specific
Initial Release
- */ - -/** - * \page asfdoc_sam0_sercom_spi_exqsg Examples for SERCOM SPI Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_sercom_spi_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_sercom_spi_master_basic_use - * - \subpage asfdoc_sam0_sercom_spi_slave_basic_use - * \if SPI_CALLBACK_MODE - * - \subpage asfdoc_sam0_sercom_spi_master_callback_use - * - \subpage asfdoc_sam0_sercom_spi_slave_callback_use - * \endif - * - \subpage asfdoc_sam0_sercom_spi_dma_use_case - */ - - /** - * \page asfdoc_sam0_sercom_spi_mux_settings MUX Settings - * - * The following lists the possible internal SERCOM module pad function - * assignments for the four SERCOM pads in both SPI Master and SPI Slave - * modes. They are combinations of DOPO and DIPO in CTRLA. - * Note that this is in addition to the physical GPIO pin MUX of the device, - * and can be used in conjunction to optimize the serial data pin-out. - * - * \section asfdoc_sam0_sercom_spi_mux_settings_master Master Mode Settings - * The following table describes the SERCOM pin functionalities for the various - * MUX settings, whilst in SPI Master mode. - * - * \note If MISO is unlisted, the SPI receiver must not be enabled for the - * given MUX setting. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
CombinationDOPO / DIPOSERCOM PAD[0]SERCOM PAD[1]SERCOM PAD[2]SERCOM PAD[3]
A0x0 / 0x0MOSISCK--
B0x0 / 0x1MOSISCK--
C0x0 / 0x2MOSISCKMISO-
D0x0 / 0x3MOSISCK-MISO
E0x1 / 0x0MISO-MOSISCK
F0x1 / 0x1-MISOMOSISCK
G0x1 / 0x2--MOSISCK
H0x1 / 0x3--MOSISCK
I0x2 / 0x0MISOSCK-MOSI
J0x2 / 0x1-SCK-MOSI
K0x2 / 0x2-SCKMISOMOSI
L0x2 / 0x3-SCK-MOSI
M0x3 / 0x0MOSI--SCK
N0x3 / 0x1MOSIMISO-SCK
O0x3 / 0x2MOSI-MISOSCK
P0x3 / 0x3MOSI--SCK
- * - * - * \section asfdoc_sam0_sercom_spi_mux_settings_slave Slave Mode Settings - * The following table describes the SERCOM pin functionalities for the various - * MUX settings, whilst in SPI Slave mode. - * - * \note If MISO is unlisted, the SPI receiver must not be enabled for the - * given MUX setting. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
CombinationDOPO / DIPOSERCOM PAD[0]SERCOM PAD[1]SERCOM PAD[2]SERCOM PAD[3]
A0x0 / 0x0MISOSCK/SS-
B0x0 / 0x1MISOSCK/SS-
C0x0 / 0x2MISOSCK/SS-
D0x0 / 0x3MISOSCK/SSMOSI
E0x1 / 0x0MOSI/SSMISOSCK
F0x1 / 0x1-/SSMISOSCK
G0x1 / 0x2-/SSMISOSCK
H0x1 / 0x3-/SSMISOSCK
I0x2 / 0x0MOSISCK/SSMISO
J0x2 / 0x1-SCK/SSMISO
K0x2 / 0x2-SCK/SSMISO
L0x2 / 0x3-SCK/SSMISO
M0x3 / 0x0MISO/SS-SCK
N0x3 / 0x1MISO/SS-SCK
O0x3 / 0x2MISO/SSMOSISCK
P0x3 / 0x3MISO/SS-SCK
- * - * - * - * \page asfdoc_sam0_sercom_spi_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42115E12/2015Add SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C21 support
42115D12/2014Add SAM R21/D10/D11 support
42115C01/2014Add SAM D21 support
42115B11/2013Replaced the pad multiplexing documentation with a condensed table
42115A06/2013Initial release
- */ - -#endif /* SPI_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi/spi_interrupt.c b/atmel-samd/asf/sam0/drivers/sercom/spi/spi_interrupt.c deleted file mode 100644 index 5909843b2d440..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi/spi_interrupt.c +++ /dev/null @@ -1,741 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver - * - * Copyright (c) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "spi_interrupt.h" - -/** - * \internal - * - * Dummy byte to send when reading in master mode. - */ -uint16_t dummy_write; - -/** - * \internal - * Starts transceive of buffers with a given length - * - * \param[in] module Pointer to SPI software instance struct - * \param[in] rx_data Pointer to data to be received - * \param[in] tx_data Pointer to data to be transmitted - * \param[in] length Length of data buffer - * - */ -static void _spi_transceive_buffer( - struct spi_module *const module, - uint8_t *tx_data, - uint8_t *rx_data, - uint16_t length) -{ - Assert(module); - Assert(tx_data); - - /* Write parameters to the device instance */ - module->remaining_tx_buffer_length = length; - module->remaining_rx_buffer_length = length; - module->rx_buffer_ptr = rx_data; - module->tx_buffer_ptr = tx_data; - module->status = STATUS_BUSY; - - module->dir = SPI_DIRECTION_BOTH; - - /* Get a pointer to the hardware module instance */ - SercomSpi *const hw = &(module->hw->SPI); - - /* Enable the Data Register Empty and RX Complete Interrupt */ - hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY | - SPI_INTERRUPT_FLAG_RX_COMPLETE); - -# if CONF_SPI_SLAVE_ENABLE == true - if (module->mode == SPI_MODE_SLAVE) { - /* Clear TXC flag if set */ - hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; - /* Enable transmit complete interrupt for slave */ - hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; - } -# endif -} - -/** - * \internal - * Starts write of a buffer with a given length - * - * \param[in] module Pointer to SPI software instance struct - * \param[in] tx_data Pointer to data to be transmitted - * \param[in] length Length of data buffer - * - */ -static void _spi_write_buffer( - struct spi_module *const module, - uint8_t *tx_data, - uint16_t length) -{ - Assert(module); - Assert(tx_data); - - /* Write parameters to the device instance */ - module->remaining_tx_buffer_length = length; - module->remaining_dummy_buffer_length = length; - module->tx_buffer_ptr = tx_data; - module->status = STATUS_BUSY; - - module->dir = SPI_DIRECTION_WRITE; - - /* Get a pointer to the hardware module instance */ - SercomSpi *const hw = &(module->hw->SPI); - -# if CONF_SPI_SLAVE_ENABLE == true - if (module->mode == SPI_MODE_SLAVE) { - /* Clear TXC flag if set */ - hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; - /* Enable transmit complete interrupt for slave */ - hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; - } -# endif - - if (module->receiver_enabled) { - /* Enable the Data Register Empty and RX Complete interrupt */ - hw->INTENSET.reg = (SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY | - SPI_INTERRUPT_FLAG_RX_COMPLETE); - } else { - /* Enable the Data Register Empty interrupt */ - hw->INTENSET.reg = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY; - } -} - -/** - * \internal - * Setup SPI to read a buffer with a given length - * - * \param[in] module Pointer to SPI software instance struct - * \param[in] rx_data Pointer to data to be received - * \param[in] length Length of data buffer - * - */ -static void _spi_read_buffer( - struct spi_module *const module, - uint8_t *rx_data, - uint16_t length) -{ - Assert(module); - Assert(rx_data); - - uint8_t tmp_intenset = 0; - - /* Set length for the buffer and the pointer, and let - * the interrupt handler do the rest */ - module->remaining_rx_buffer_length = length; - module->remaining_dummy_buffer_length = length; - module->rx_buffer_ptr = rx_data; - module->status = STATUS_BUSY; - - module->dir = SPI_DIRECTION_READ; - - /* Get a pointer to the hardware module instance */ - SercomSpi *const hw = &(module->hw->SPI); - - /* Enable the RX Complete Interrupt */ - tmp_intenset = SPI_INTERRUPT_FLAG_RX_COMPLETE; - -# if CONF_SPI_MASTER_ENABLE == true - if (module->mode == SPI_MODE_MASTER && module->dir == SPI_DIRECTION_READ) { - /* Enable Data Register Empty interrupt for master */ - tmp_intenset |= SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY; - } -# endif -# if CONF_SPI_SLAVE_ENABLE == true - if (module->mode == SPI_MODE_SLAVE) { - /* Clear TXC flag if set */ - hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; - /* Enable transmit complete interrupt for slave */ - tmp_intenset |= SPI_INTERRUPT_FLAG_TX_COMPLETE; - - /* Workaround for SSL flag enable */ -#ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT - /* Clear SSL flag if set */ - hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW; - /* Enable Slave Select Low Interrupt for slave */ - tmp_intenset |= SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW; -#endif - } -# endif - - /* Enable all interrupts simultaneously */ - hw->INTENSET.reg = tmp_intenset; -} - -/** - * \brief Registers a SPI callback function - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref spi_enable_callback, in order - * for the interrupt handler to call it when the conditions for the - * callback type are met. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - * - */ -void spi_register_callback( - struct spi_module *const module, - spi_callback_t callback_func, - enum spi_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); - - /* Register callback function */ - module->callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module->registered_callback |= (1 << callback_type); -} - -/** - * \brief Unregisters a SPI callback function - * - * Unregisters a callback function which is implemented by the user. - * - * \param[in] module Pointer to SPI software instance struct - * \param[in] callback_type Callback type given by an enum - * - */ -void spi_unregister_callback( - struct spi_module *const module, - enum spi_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Unregister callback function */ - module->callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module->registered_callback &= ~(1 << callback_type); -} - -/** - * \brief Asynchronous buffer write - * - * Sets up the driver to write to the SPI from a given buffer. If registered - * and enabled, a callback function will be called when the write is finished. - * - * \param[in] module Pointer to SPI software instance struct - * \param[out] tx_data Pointer to data buffer to receive - * \param[in] length Data buffer length - * - * \returns Status of the write request operation. - * \retval STATUS_OK If the operation completed successfully - * \retval STATUS_ERR_BUSY If the SPI was already busy with a write - * operation - * \retval STATUS_ERR_INVALID_ARG If requested write length was zero - */ -enum status_code spi_write_buffer_job( - struct spi_module *const module, - uint8_t *tx_data, - uint16_t length) -{ - Assert(module); - Assert(tx_data); - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check if the SPI is busy transmitting or slave waiting for TXC*/ - if (module->status == STATUS_BUSY) { - return STATUS_BUSY; - } - - /* Issue internal write */ - _spi_write_buffer(module, tx_data, length); - - return STATUS_OK; -} - -/** - * \brief Asynchronous buffer read - * - * Sets up the driver to read from the SPI to a given buffer. If registered - * and enabled, a callback function will be called when the read is finished. - * - * \note If address matching is enabled for the slave, the first character - * received and placed in the RX buffer will be the address. - * - * \param[in] module Pointer to SPI software instance struct - * \param[out] rx_data Pointer to data buffer to receive - * \param[in] length Data buffer length - * \param[in] dummy Dummy character to send when reading in master mode - * - * \returns Status of the operation. - * \retval STATUS_OK If the operation completed successfully - * \retval STATUS_ERR_BUSY If the SPI was already busy with a read - * operation - * \retval STATUS_ERR_DENIED If the receiver is not enabled - * \retval STATUS_ERR_INVALID_ARG If requested read length was zero - */ -enum status_code spi_read_buffer_job( - struct spi_module *const module, - uint8_t *rx_data, - uint16_t length, - uint16_t dummy) -{ - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Check if the SPI is busy transmitting or slave waiting for TXC*/ - if (module->status == STATUS_BUSY) { - return STATUS_BUSY; - } - - dummy_write = dummy; - /* Issue internal read */ - _spi_read_buffer(module, rx_data, length); - return STATUS_OK; -} - -/** - * \brief Asynchronous buffer write and read - * - * Sets up the driver to write and read to and from given buffers. If registered - * and enabled, a callback function will be called when the transfer is finished. - * - * \note If address matching is enabled for the slave, the first character - * received and placed in the RX buffer will be the address. - * - * \param[in] module Pointer to SPI software instance struct - * \param[in] tx_data Pointer to data buffer to send - * \param[out] rx_data Pointer to data buffer to receive - * \param[in] length Data buffer length - * - * \returns Status of the operation. - * \retval STATUS_OK If the operation completed successfully - * \retval STATUS_ERR_BUSY If the SPI was already busy with a read - * operation - * \retval STATUS_ERR_DENIED If the receiver is not enabled - * \retval STATUS_ERR_INVALID_ARG If requested read length was zero - */ -enum status_code spi_transceive_buffer_job( - struct spi_module *const module, - uint8_t *tx_data, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Check if the SPI is busy transmitting or slave waiting for TXC*/ - if (module->status == STATUS_BUSY) { - return STATUS_BUSY; - } - - /* Issue internal transceive */ - _spi_transceive_buffer(module, tx_data, rx_data, length); - - return STATUS_OK; -} -/** - * \brief Aborts an ongoing job - * - * This function will abort the specified job type. - * - * \param[in] module Pointer to SPI software instance struct - */ -void spi_abort_job( - struct spi_module *const module) -{ - /* Pointer to the hardware module instance */ - SercomSpi *const spi_hw - = &(module->hw->SPI); - - /* Abort ongoing job */ - - /* Disable interrupts */ - spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE | - SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY | - SPI_INTERRUPT_FLAG_TX_COMPLETE; - - module->status = STATUS_ABORTED; - module->remaining_rx_buffer_length = 0; - module->remaining_dummy_buffer_length = 0; - module->remaining_tx_buffer_length = 0; - - module->dir = SPI_DIRECTION_IDLE; -} - -# if CONF_SPI_SLAVE_ENABLE == true || CONF_SPI_MASTER_ENABLE == true -/** - * \internal - * Writes a character from the TX buffer to the Data register. - * - * \param[in,out] module Pointer to SPI software instance struct - */ -static void _spi_write( - struct spi_module *const module) -{ - /* Pointer to the hardware module instance */ - SercomSpi *const spi_hw = &(module->hw->SPI); - - /* Write value will be at least 8-bits long */ - uint16_t data_to_send = *(module->tx_buffer_ptr); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; - - if (module->character_size == SPI_CHARACTER_SIZE_9BIT) { - data_to_send |= ((*(module->tx_buffer_ptr)) << 8); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; - } - - /* Write the data to send*/ - spi_hw->DATA.reg = data_to_send & SERCOM_SPI_DATA_MASK; - - /* Decrement remaining buffer length */ - (module->remaining_tx_buffer_length)--; -} -# endif - -# if CONF_SPI_MASTER_ENABLE == true -/** - * \internal - * Writes a dummy character to the Data register. - * - * \param[in,out] module Pointer to SPI software instance struct - */ -static void _spi_write_dummy( - struct spi_module *const module) -{ - /* Pointer to the hardware module instance */ - SercomSpi *const spi_hw = &(module->hw->SPI); - - /* Write dummy byte */ - spi_hw->DATA.reg = dummy_write; - - /* Decrement remaining dummy buffer length */ - module->remaining_dummy_buffer_length--; -} -# endif - -/** - * \internal - * Writes a dummy character from the to the Data register. - * - * \param[in,out] module Pointer to SPI software instance struct - */ -static void _spi_read_dummy( - struct spi_module *const module) -{ - /* Pointer to the hardware module instance */ - SercomSpi *const spi_hw = &(module->hw->SPI); - uint16_t flush = 0; - - /* Read dummy byte */ - flush = spi_hw->DATA.reg; - UNUSED(flush); - - /* Decrement remaining dummy buffer length */ - module->remaining_dummy_buffer_length--; -} - -/** - * \internal - * Reads a character from the Data register to the RX buffer. - * - * \param[in,out] module Pointer to SPI software instance struct - */ -static void _spi_read( - struct spi_module *const module) -{ - /* Pointer to the hardware module instance */ - SercomSpi *const spi_hw = &(module->hw->SPI); - - uint16_t received_data = (spi_hw->DATA.reg & SERCOM_SPI_DATA_MASK); - - /* Read value will be at least 8-bits long */ - *(module->rx_buffer_ptr) = received_data; - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; - - if(module->character_size == SPI_CHARACTER_SIZE_9BIT) { - /* 9-bit data, write next received byte to the buffer */ - *(module->rx_buffer_ptr) = (received_data >> 8); - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; - } - - /* Decrement length of the remaining buffer */ - module->remaining_rx_buffer_length--; -} - -/** - * \internal - * - * Handles interrupts as they occur, and it will run callback functions - * which are registered and enabled. - * - * \note This function will be called by the Sercom_Handler, and should - * not be called directly from any application code. - * - * \param[in] instance ID of the SERCOM instance calling the interrupt - * handler. - */ -void _spi_interrupt_handler( - uint8_t instance) -{ - /* Get device instance from the look-up table */ - struct spi_module *module - = (struct spi_module *)_sercom_instances[instance]; - - /* Pointer to the hardware module instance */ - SercomSpi *const spi_hw = &(module->hw->SPI); - - /* Combine callback registered and enabled masks. */ - uint8_t callback_mask = - module->enabled_callback & module->registered_callback; - - /* Read and mask interrupt flag register */ - uint16_t interrupt_status = spi_hw->INTFLAG.reg; - interrupt_status &= spi_hw->INTENSET.reg; - - /* Data register empty interrupt */ - if (interrupt_status & SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY) { -# if CONF_SPI_MASTER_ENABLE == true - if ((module->mode == SPI_MODE_MASTER) && - (module->dir == SPI_DIRECTION_READ)) { - /* Send dummy byte when reading in master mode */ - _spi_write_dummy(module); - if (module->remaining_dummy_buffer_length == 0) { - /* Disable the Data Register Empty Interrupt */ - spi_hw->INTENCLR.reg - = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY; - } - } -# endif - - if (0 -# if CONF_SPI_MASTER_ENABLE == true - || ((module->mode == SPI_MODE_MASTER) && - (module->dir != SPI_DIRECTION_READ)) -# endif -# if CONF_SPI_SLAVE_ENABLE == true - || ((module->mode == SPI_MODE_SLAVE) && - (module->dir != SPI_DIRECTION_READ)) -# endif - ) { - /* Write next byte from buffer */ - _spi_write(module); - if (module->remaining_tx_buffer_length == 0) { - /* Disable the Data Register Empty Interrupt */ - spi_hw->INTENCLR.reg - = SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY; - - if (module->dir == SPI_DIRECTION_WRITE && - !(module->receiver_enabled)) { - /* Enable the Data Register transmit complete Interrupt */ - spi_hw->INTENSET.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; - } - } - } - } - - /* Receive complete interrupt*/ - if (interrupt_status & SPI_INTERRUPT_FLAG_RX_COMPLETE) { - /* Check for overflow */ - if (spi_hw->STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) { - if (module->dir != SPI_DIRECTION_WRITE) { - /* Store the error code */ - module->status = STATUS_ERR_OVERFLOW; - - /* End transaction */ - module->dir = SPI_DIRECTION_IDLE; - - spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE | - SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY; - /* Run callback if registered and enabled */ - if (callback_mask & (1 << SPI_CALLBACK_ERROR)) { - (module->callback[SPI_CALLBACK_ERROR])(module); - } - } - /* Flush */ - uint16_t flush = spi_hw->DATA.reg; - UNUSED(flush); - /* Clear overflow flag */ - spi_hw->STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; - } else { - if (module->dir == SPI_DIRECTION_WRITE) { - /* Flush receive buffer when writing */ - _spi_read_dummy(module); - if (module->remaining_dummy_buffer_length == 0) { - spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE; - module->status = STATUS_OK; - module->dir = SPI_DIRECTION_IDLE; - /* Run callback if registered and enabled */ - if (callback_mask & - (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)){ - (module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED])(module); - } - } - } else { - /* Read data register */ - _spi_read(module); - - /* Check if the last character have been received */ - if (module->remaining_rx_buffer_length == 0) { - module->status = STATUS_OK; - /* Disable RX Complete Interrupt and set status */ - spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_RX_COMPLETE; - if(module->dir == SPI_DIRECTION_BOTH) { - if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSCEIVED)) { - (module->callback[SPI_CALLBACK_BUFFER_TRANSCEIVED])(module); - } - } else if (module->dir == SPI_DIRECTION_READ) { - if (callback_mask & (1 << SPI_CALLBACK_BUFFER_RECEIVED)) { - (module->callback[SPI_CALLBACK_BUFFER_RECEIVED])(module); - } - } - } - } - } - } - - /* Transmit complete */ - if (interrupt_status & SPI_INTERRUPT_FLAG_TX_COMPLETE) { -# if CONF_SPI_SLAVE_ENABLE == true - if (module->mode == SPI_MODE_SLAVE) { - /* Transaction ended by master */ - - /* Disable interrupts */ - spi_hw->INTENCLR.reg = - SPI_INTERRUPT_FLAG_TX_COMPLETE | - SPI_INTERRUPT_FLAG_RX_COMPLETE | - SPI_INTERRUPT_FLAG_DATA_REGISTER_EMPTY; - /* Clear interrupt flag */ - spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_TX_COMPLETE; - - - /* Reset all status information */ - module->dir = SPI_DIRECTION_IDLE; - module->remaining_tx_buffer_length = 0; - module->remaining_rx_buffer_length = 0; - module->status = STATUS_OK; - - if (callback_mask & - (1 << SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE)) { - (module->callback[SPI_CALLBACK_SLAVE_TRANSMISSION_COMPLETE]) - (module); - } - - } -# endif -# if CONF_SPI_MASTER_ENABLE == true - if ((module->mode == SPI_MODE_MASTER) && - (module->dir == SPI_DIRECTION_WRITE) && !(module->receiver_enabled)) { - /* Clear interrupt flag */ - spi_hw->INTENCLR.reg - = SPI_INTERRUPT_FLAG_TX_COMPLETE; - /* Buffer sent with receiver disabled */ - module->dir = SPI_DIRECTION_IDLE; - module->status = STATUS_OK; - /* Run callback if registered and enabled */ - if (callback_mask & (1 << SPI_CALLBACK_BUFFER_TRANSMITTED)){ - (module->callback[SPI_CALLBACK_BUFFER_TRANSMITTED]) - (module); - } - } -#endif - } - -# ifdef FEATURE_SPI_SLAVE_SELECT_LOW_DETECT -# if CONF_SPI_SLAVE_ENABLE == true - /* When a high to low transition is detected on the _SS pin in slave mode */ - if (interrupt_status & SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW) { - if (module->mode == SPI_MODE_SLAVE) { - /* Disable interrupts */ - spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW; - /* Clear interrupt flag */ - spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_SLAVE_SELECT_LOW; - - if (callback_mask & (1 << SPI_CALLBACK_SLAVE_SELECT_LOW)) { - (module->callback[SPI_CALLBACK_SLAVE_SELECT_LOW])(module); - } - } - } -# endif -# endif - -# ifdef FEATURE_SPI_ERROR_INTERRUPT - /* When combined error happen */ - if (interrupt_status & SPI_INTERRUPT_FLAG_COMBINED_ERROR) { - /* Disable interrupts */ - spi_hw->INTENCLR.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR; - /* Clear interrupt flag */ - spi_hw->INTFLAG.reg = SPI_INTERRUPT_FLAG_COMBINED_ERROR; - - if (callback_mask & (1 << SPI_CALLBACK_COMBINED_ERROR)) { - (module->callback[SPI_CALLBACK_COMBINED_ERROR])(module); - } - } -# endif -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi/spi_interrupt.h b/atmel-samd/asf/sam0/drivers/sercom/spi/spi_interrupt.h deleted file mode 100644 index bb7168250124f..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi/spi_interrupt.h +++ /dev/null @@ -1,190 +0,0 @@ -/** - * \file - * - * \brief SAM Serial Peripheral Interface Driver (Callback Mode) - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SPI_INTERRUPT_H_INCLUDED -#define SPI_INTERRUPT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_spi_group - * - * @{ - */ - -#include "spi.h" - -/** - * \name Callback Management - * @{ - */ - -void spi_register_callback( - struct spi_module *const module, - spi_callback_t callback_func, - enum spi_callback callback_type); - -void spi_unregister_callback( - struct spi_module *module, - enum spi_callback callback_type); - -/** - * \brief Enables an SPI callback of a given type - * - * Enables the callback function registered by the \ref spi_register_callback. - * The callback function will be called from the interrupt handler when the - * conditions for the callback type are met. - * - * \param[in] module Pointer to SPI software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void spi_enable_callback( - struct spi_module *const module, - enum spi_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Enable callback */ - module->enabled_callback |= (1 << callback_type); -} - -/** - * \brief Disables callback - * - * Disables the callback function registered by the \ref spi_register_callback, - * and the callback will not be called from the interrupt routine. - * - * \param[in] module Pointer to SPI software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void spi_disable_callback( - struct spi_module *const module, - enum spi_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Disable callback */ - module->enabled_callback &= ~(1 << callback_type); -} - -/** @} */ - - -/** - * \name Writing and Reading - * @{ - */ -enum status_code spi_write_buffer_job( - struct spi_module *const module, - uint8_t *tx_data, - uint16_t length); - -enum status_code spi_read_buffer_job( - struct spi_module *const module, - uint8_t *rx_data, - uint16_t length, - uint16_t dummy); - -enum status_code spi_transceive_buffer_job( - struct spi_module *const module, - uint8_t *tx_data, - uint8_t *rx_data, - uint16_t length); - -void spi_abort_job( - struct spi_module *const module); - -/** - * \brief Retrieves the current status of a job. - * - * Retrieves the current status of a job that was previously issued. - * - * \param[in] module Pointer to SPI software instance struct - * - * \return Current job status. - */ -static inline enum status_code spi_get_job_status( - const struct spi_module *const module) -{ - return module->status; -} - -/** - * \brief Retrieves the status of job once it ends. - * - * Waits for current job status to become non-busy, then returns its value. - * - * \param[in] module Pointer to SPI software instance struct - * - * \return Current non-busy job status. - */ -static inline enum status_code spi_get_job_status_wait( - const struct spi_module *const module) -{ - enum status_code status; - - do { - status = spi_get_job_status(module); - } while (status == STATUS_BUSY); - - return status; -} - -/** @} */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* SPI_INTERRUPT_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi.h b/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi.h deleted file mode 100644 index 3bb66ff5bb748..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief common SPI configuration - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef CONF_SPI_H_INCLUDED -# define CONF_SPI_H_INCLUDED - -# define CONF_SPI_MASTER_ENABLE true -# define CONF_SPI_SLAVE_ENABLE false - -#endif /* CONF_SPI_H_INCLUDED */ - diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h b/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h deleted file mode 100644 index 394b1fa6173c9..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/module-config/conf_spi_master_vec.h +++ /dev/null @@ -1,68 +0,0 @@ -/** - * \file - * - * \brief SERCOM SPI master with vectored I/O driver configuration - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_SPI_MASTER_VEC_H -#define CONF_SPI_MASTER_VEC_H - -#if defined(__FREERTOS__) || defined(__DOXYGEN__) -# include -# include - -# define CONF_SPI_MASTER_VEC_OS_SUPPORT -# define CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE xSemaphoreHandle -# define CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE(semaphore) \ - vSemaphoreCreateBinary(semaphore) -# define CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE(semaphore) \ - vSemaphoreDelete(semaphore) -# define CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(semaphore) \ - xSemaphoreTake((semaphore), portMAX_DELAY) -# define CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE(semaphore) \ - xSemaphoreGive((semaphore)) -# define CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(semaphore) \ - xSemaphoreGiveFromISR((semaphore), NULL) -#endif - -#endif // CONF_SPI_MASTER_VEC_H \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c b/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c deleted file mode 100644 index 89de7dd0d71bc..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/spi_master_vec.c +++ /dev/null @@ -1,588 +0,0 @@ -/** - * \file - * - * \brief SERCOM SPI master with vectored I/O driver implementation - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "spi_master_vec.h" -#include -#include -#include - -/** - * \ingroup asfdoc_sam0_sercom_spi_master_vec_group - * - * @{ - */ - -/** - * \name Internal functions - * @{ - */ - -/** \cond INTERNAL */ - -static void _spi_master_vec_int_handler(uint8_t sercom_index); - -/** - * \brief Wait for SERCOM SPI to synchronize - * - * \param[in] sercom_spi SERCOM SPI to check for synchronization. - * - * \note The implementation of this function depends on the SERCOM revision. - */ -static inline void _spi_master_vec_wait_for_sync(SercomSpi *const sercom_spi) -{ -#if defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_1) - while (sercom_spi->STATUS.reg & SERCOM_SPI_STATUS_SYNCBUSY) { - /* Intentionally left empty */ - } -#elif defined(FEATURE_SERCOM_SYNCBUSY_SCHEME_VERSION_2) - while (sercom_spi->SYNCBUSY.reg) { - /* Intentionally left empty */ - } -#else -# error Unknown SERCOM SYNCBUSY scheme! -#endif -} - -/** - * \brief Pin MUX configuration helper - * - * \param[in] pinmux Pin MUX setting to apply. Special values: - * \arg \c PINMUX_UNUSED to do nothing. - * \arg \c PINMUX_DEFAULT to use default pin MUX for the SERCOM pad. - * \param[in] sercom,padnum SERCOM pad specification, for \ref PINMUX_DEFAULT. - */ -static inline void _spi_master_vec_pinmux_helper(uint32_t pinmux, - Sercom *const sercom, uint8_t padnum) -{ - struct system_pinmux_config pin_conf; - - if (pinmux == PINMUX_DEFAULT) { - pinmux = _sercom_get_default_pad(sercom, padnum); - } - - if (pinmux == PINMUX_UNUSED) { - return; - } - - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.mux_position = pinmux & 0xFFFF; - system_pinmux_pin_set_config(pinmux >> 16, &pin_conf); -}; - -/** \endcond */ - -/** @} */ - -/** - * \brief Initialize hardware and driver instance - * - * This function configures the clock system for the specified SERCOM module, - * sets up the related pins and their MUX, initializes the SERCOM in SPI master - * mode, and prepares the driver instance for operation. - * - * \pre \ref system_init() must have been called prior to this function. - * - * The SERCOM SPI module is left disabled after initialization, and must be - * enabled with \ref spi_master_vec_enable() before a transfer can be done. - * - * \param[out] module Driver instance to initialize. - * \param[in,out] sercom SERCOM module to initialize and associate driver - * instance with. - * \param[in] config Driver configuration to use. - * - * \return Status of initialization. - * \retval STATUS_OK if initialization succeeded. - * \retval STATUS_ERR_INVALID_ARG if driver has been misconfigured. - */ -enum status_code spi_master_vec_init(struct spi_master_vec_module *const module, - Sercom *const sercom, const struct spi_master_vec_config *const config) -{ - Assert(module); - Assert(sercom); - Assert(config); - - enum status_code status; - SercomSpi *const spi_hw = &(sercom->SPI); - struct system_gclk_chan_config gclk_chan_conf; - uint16_t tmp_baud; - uint32_t sercom_index = _sercom_get_sercom_inst_index((Sercom *)spi_hw); -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - uint32_t pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; -#else - uint32_t pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; -#endif - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - uint32_t gclk_hz; - - module->sercom = sercom; - - /* Enable clock for the module interface */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - - /* Set up the GCLK for the module */ - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->gclk_generator; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->gclk_generator, false); - - _spi_master_vec_wait_for_sync(spi_hw); - - /* Set up the SERCOM SPI module as master */ - spi_hw->CTRLA.reg = SERCOM_SPI_CTRLA_MODE(0x3); - spi_hw->CTRLA.reg |= (uint32_t)config->mux_setting - | config->transfer_mode - | config->data_order - | ((config->run_in_standby || system_is_debugger_present()) ? - SERCOM_SPI_CTRLA_RUNSTDBY : 0); - - /* Get baud value from configured baudrate and internal clock rate */ - gclk_hz = system_gclk_chan_get_hz(gclk_index); - status = _sercom_get_sync_baud_val(config->baudrate, gclk_hz, &tmp_baud); - - if (status != STATUS_OK) { - /* Baud rate calculation error! */ - return STATUS_ERR_INVALID_ARG; - } - - spi_hw->BAUD.reg = (uint8_t)tmp_baud; - - /* Configure the pin multiplexers */ - _spi_master_vec_pinmux_helper(config->pinmux_pad0, sercom, 0); - _spi_master_vec_pinmux_helper(config->pinmux_pad3, sercom, 3); - - /* SERCOM PAD1 and PAD2 are used for slave SS. - * This is a SPI master driver, so control of slave SS must be left to - * the PORT module, i.e., peripheral MUX should not be set for that pin. - * DOPO controls which PAD is used for slave SS: - * If DOPO is odd, SERCOM_PAD1 is SS: SERCOM_PAD2 can be MUXed. - * If DOPO is even, SERCOM_PAD2 is SS: SERCOM_PAD1 can be MUXed. - */ - if (config->mux_setting & (1 << SERCOM_SPI_CTRLA_DOPO_Pos)) { - _spi_master_vec_pinmux_helper(config->pinmux_pad2, sercom, 2); - } else { - _spi_master_vec_pinmux_helper(config->pinmux_pad1, sercom, 1); - } - - /* Initialize our instance and register interrupt handler + data */ - module->rx_bufdesc_ptr = NULL; - module->tx_bufdesc_ptr = NULL; - module->direction = SPI_MASTER_VEC_DIRECTION_IDLE; - module->status = STATUS_OK; -#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT - CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE(module->busy_semaphore); -#endif - - _sercom_set_handler(sercom_index, _spi_master_vec_int_handler); - _sercom_instances[sercom_index] = module; - - return STATUS_OK; -} - -/** - * \brief Enable the SERCOM SPI module - * - * This function must be called after \ref spi_master_vec_init() before a - * transfer can be started. - * - * \param[in,out] module Driver instance to operate on. - */ -void spi_master_vec_enable(const struct spi_master_vec_module *const module) -{ - Assert(module); - Assert(module->sercom); - - SercomSpi *const spi_hw = &(module->sercom->SPI); - - spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC - | SERCOM_SPI_INTFLAG_TXC; - - _spi_master_vec_wait_for_sync(spi_hw); - - spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; - - system_interrupt_enable(_sercom_get_interrupt_vector(module->sercom)); -} - -/** - * \brief Disable the SERCOM SPI module - * - * \param[in,out] module Driver instance to operate on. - */ -void spi_master_vec_disable(struct spi_master_vec_module *const module) -{ - Assert(module); - Assert(module->sercom); - - SercomSpi *const spi_hw = &(module->sercom->SPI); - - system_interrupt_disable(_sercom_get_interrupt_vector(module->sercom)); - - _spi_master_vec_wait_for_sync(spi_hw); - - spi_hw->INTENCLR.reg = SERCOM_SPI_INTENCLR_MASK; - spi_hw->INTFLAG.reg = SERCOM_SPI_INTFLAG_MASK; - spi_hw->CTRLB.reg = 0; - spi_hw->CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; - module->rx_bufdesc_ptr = NULL; - module->tx_bufdesc_ptr = NULL; - module->direction = SPI_MASTER_VEC_DIRECTION_IDLE; - module->status = STATUS_OK; -} - -/** - * \brief Reset the SERCOM SPI module - * - * This function will disable and reset the SPI module to its power on default - * values. - * - * \param[in,out] module Pointer to a driver instance. - */ -void spi_master_vec_reset(struct spi_master_vec_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->sercom); - - SercomSpi *const spi_hw = &(module->sercom->SPI); - - /* Disable the module */ - spi_master_vec_disable(module); - - _spi_master_vec_wait_for_sync(spi_hw); - - /* Software reset the module */ - spi_hw->CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; - -#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT - CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE(module->busy_semaphore); -#endif -} - -/** - * \brief Start vectored I/O transfer - * - * This function initiates a uni- or bidirectional SPI transfer from/to any - * number of data buffers. The transfer is interrupt-driven and will run in the - * background, after this function has returned. - * - * The buffers to transmit from or receive into must be described in arrays of - * buffer descriptors. These arrays \e must end with descriptors that specify - * zero buffer length. The first descriptor in an array can \e not specify zero - * length. The number of bytes to transmit and to receive do not have to be - * equal. - * - * If the address for a receive buffer is set to \c NULL, the received bytes - * corresponding to that buffer descriptor will be discarded. This is useful if - * slave is already set up to transfer a number of bytes, but the master has no - * available buffer to receive them into. As an example, to receive the two - * first bytes and discard the 128 following, the buffer descriptors could be: -\code - struct spi_master_vec_bufdesc rx_buffers[3] = { - // Read two status bytes - {.data = status_buffer, .length = 2}, - // Discard 128 data bytes - {.data = NULL, .length = 128}, - // End of reception - {.length = 0}, - }; -\endcode - * - * To initiate a unidirectional transfer, pass \c NULL as the address of either - * buffer descriptor array, like this: -\code - // Transmit some buffers - spi_master_vec_transceive_buffer_job(&module, tx_buffers, NULL); - - // Receive some buffers - spi_master_vec_transceive_buffer_job(&module, NULL, rx_buffers); -\endcode - * - * \pre \ref spi_master_vec_init() and \ref spi_master_vec_enable() must have - * been called before this function. - * - * \param[in,out] module Driver instance to operate on. - * \param[in] tx_bufdescs address of buffer descriptor array for bytes to - * transmit. - * \arg \c NULL if the transfer is a simplex read. - * \param[in,out] rx_bufdescs address of buffer descriptor array for storing - * received bytes. - * \arg \c NULL if the transfer is a simplex write. - * - * \return Status of transfer start. - * \retval STATUS_OK if transfer was started. - * \retval STATUS_BUSY if a transfer is already on-going. - */ -enum status_code spi_master_vec_transceive_buffer_job( - struct spi_master_vec_module *const module, - struct spi_master_vec_bufdesc tx_bufdescs[], - struct spi_master_vec_bufdesc rx_bufdescs[]) -{ - Assert(module); - Assert(module->sercom); - Assert(tx_bufdescs || rx_bufdescs); - - SercomSpi *const spi_hw = &(module->sercom->SPI); - uint32_t tmp_ctrlb; - uint8_t tmp_intenset; - - system_interrupt_enter_critical_section(); - if (module->status == STATUS_BUSY) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } else { - module->status = STATUS_BUSY; - system_interrupt_leave_critical_section(); - } - -#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT - CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore); -#endif - - module->tx_bufdesc_ptr = tx_bufdescs; - module->rx_bufdesc_ptr = rx_bufdescs; - - if (tx_bufdescs && rx_bufdescs) { - Assert(tx_bufdescs[0].length); - Assert(rx_bufdescs[0].length); - - module->direction = SPI_MASTER_VEC_DIRECTION_BOTH; - module->tx_length = tx_bufdescs[0].length; - module->tx_head_ptr = tx_bufdescs[0].data; - module->rx_length = rx_bufdescs[0].length; - module->rx_head_ptr = rx_bufdescs[0].data; - module->tx_lead_on_rx = 0; - tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN; - tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC; - } else { - if (tx_bufdescs) { - Assert(tx_bufdescs[0].length); - - module->direction = SPI_MASTER_VEC_DIRECTION_WRITE; - module->tx_length = tx_bufdescs[0].length; - module->tx_head_ptr = tx_bufdescs[0].data; - tmp_ctrlb = 0; - tmp_intenset = SERCOM_SPI_INTFLAG_DRE; - } else { - Assert(rx_bufdescs[0].length); - - module->direction = SPI_MASTER_VEC_DIRECTION_READ; - module->rx_length = rx_bufdescs[0].length; - module->rx_head_ptr = rx_bufdescs[0].data; - module->tx_lead_on_rx = 0; - tmp_ctrlb = SERCOM_SPI_CTRLB_RXEN; - tmp_intenset = SERCOM_SPI_INTFLAG_DRE | SERCOM_SPI_INTFLAG_RXC; - } - } - - /* Ensure the SERCOM is sync'ed before writing these registers */ - _spi_master_vec_wait_for_sync(spi_hw); - - spi_hw->CTRLB.reg = tmp_ctrlb; - spi_hw->INTENSET.reg = tmp_intenset; - - return STATUS_OK; -} - -/** - * \brief Interrupt handler - * - * \param[in] sercom_index SERCOM instance number passed from the master SERCOM - * driver. - */ -static void _spi_master_vec_int_handler(uint8_t sercom_index) -{ - struct spi_master_vec_module *const module = - _sercom_instances[sercom_index]; - enum _spi_master_vec_direction dir = module->direction; - SercomSpi *const spi_hw = &(module->sercom->SPI); - uint8_t int_status; - - int_status = spi_hw->INTFLAG.reg ; - int_status &= spi_hw->INTENSET.reg; - - if (int_status & SERCOM_SPI_INTFLAG_DRE) { - uint_fast8_t tx_lead_on_rx = module->tx_lead_on_rx; - - /* If TX is ahead of RX by 2+ bytes, allow RX to catch up. - * Note: will only happen _once_ per READ or BOTH. - */ - if ((tx_lead_on_rx >= 2) && (dir != SPI_MASTER_VEC_DIRECTION_WRITE)) { - Assert((dir == SPI_MASTER_VEC_DIRECTION_READ) - || (dir == SPI_MASTER_VEC_DIRECTION_BOTH)); - Assert(int_status & SERCOM_SPI_INTFLAG_RXC); - /* Otherwise, we can send more bytes */ - } else { - module->tx_lead_on_rx = ++tx_lead_on_rx; - - /* If doing a READ, just send 0 to trigger the transfer */ - if (dir == SPI_MASTER_VEC_DIRECTION_READ) { - uint32_t tx_lead_limit; - - spi_hw->DATA.reg = 0; - -check_for_read_end: - /* With current TX'ed bytes, will we get the last RX byte? - * If so, we can disable the DRE interrupt to stop transmitting. - * - * Since a buffer can have minimum 1 byte length, this check is - * simplified by first checking if the RX end is so close that - * the max. 2 byte lead of TX may actually fill the buffers. - */ - tx_lead_limit = (module->rx_bufdesc_ptr + 1)->length; - - if (!tx_lead_limit || !(module->rx_bufdesc_ptr + 2)->length) { - tx_lead_limit += module->rx_length; - - if (tx_lead_on_rx >= tx_lead_limit) { - spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE; - } - } - /* For WRITE and BOTH, output current byte */ - } else { - spi_master_vec_buflen_t tx_length; - uint8_t *tx_head_ptr; - - tx_head_ptr = module->tx_head_ptr; - spi_hw->DATA.reg = *(tx_head_ptr++); - - /* Check if this was the last byte to send */ - tx_length = module->tx_length - 1; - - if (tx_length) { - module->tx_head_ptr = tx_head_ptr; - module->tx_length = tx_length; - } else { - /* Any more buffers left to send, perhaps? */ - tx_length = (++module->tx_bufdesc_ptr)->length; - - if (tx_length) { - module->tx_head_ptr = module->tx_bufdesc_ptr->data; - module->tx_length = tx_length; - } else { - if (dir == SPI_MASTER_VEC_DIRECTION_WRITE) { - /* Disable DRE and enable TXC to end WRITE */ - spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_DRE; - spi_hw->INTENSET.reg = SERCOM_SPI_INTFLAG_TXC; - } else { - /* For BOTH, check if we still have bytes to read */ - dir = SPI_MASTER_VEC_DIRECTION_READ; - module->direction = dir; - goto check_for_read_end; - } - } - } - } - } - } - - /* For READ and BOTH, store the received byte */ - if (int_status & SERCOM_SPI_INTFLAG_RXC) { - spi_master_vec_buflen_t rx_length; - uint8_t *rx_head_ptr; - - rx_head_ptr = module->rx_head_ptr; - if (rx_head_ptr != NULL) { - *(rx_head_ptr++) = spi_hw->DATA.reg; - } else { - uint8_t dummy; - dummy = spi_hw->DATA.reg; - UNUSED(dummy); - } - module->tx_lead_on_rx--; - - /* Check if this was the last byte to receive */ - rx_length = module->rx_length - 1; - - if (rx_length) { - module->rx_head_ptr = rx_head_ptr; - module->rx_length = rx_length; - } else { - /* Any more buffers left to receive into? */ - rx_length = (++module->rx_bufdesc_ptr)->length; - - if (rx_length) { - module->rx_head_ptr = module->rx_bufdesc_ptr->data; - module->rx_length = rx_length; - } else { - /* Disable the SPI receiver (instant effect) and RX interrupt */ - spi_hw->CTRLB.reg = 0; - spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_RXC; - - if (dir == SPI_MASTER_VEC_DIRECTION_READ) { - /* If doing READ, end the transaction here */ - dir = SPI_MASTER_VEC_DIRECTION_IDLE; - module->direction = dir; - module->status = STATUS_OK; -#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT - CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore); -#endif - } else { - /* If doing BOTH, change direction to WRITE */ - dir = SPI_MASTER_VEC_DIRECTION_WRITE; - module->direction = dir; - } - } - } - } - - /* For WRITE */ - if (int_status & SERCOM_SPI_INTFLAG_TXC) { - /* End transaction here, since last byte has been sent */ - spi_hw->INTENCLR.reg = SERCOM_SPI_INTFLAG_TXC; - - dir = SPI_MASTER_VEC_DIRECTION_IDLE; - module->direction = dir; - module->status = STATUS_OK; -#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT - CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR(module->busy_semaphore); -#endif - } -} - -/** - * @} - */ \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h b/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h deleted file mode 100644 index a10ae22f14c03..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/spi_master_vec/spi_master_vec.h +++ /dev/null @@ -1,692 +0,0 @@ -/** - * \file - * - * \brief SERCOM SPI master with vectored I/O driver include - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SPI_MASTER_VEC_H -#define SPI_MASTER_VEC_H - -#include -#include -#include -#include -#include -#include - -/** - * \defgroup asfdoc_sam0_sercom_spi_master_vec_group SAM Serial Peripheral Interface Master Driver w/ Vectored I/O (SERCOM SPI) - * - * This driver for Atmel® | SMART SAM devices provides an interface for the configuration - * and operation of the SERCOM module in SPI master mode and uses vectored I/O - * for data transfers. - * - * The following peripherals are used by this driver: - * - SERCOM (Serial Communication Interface) - * - * The following devices can use this driver: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - * The reader is assumed to be familiar with the regular SERCOM SPI driver, and - * how it is configured and operated. Configuration of this driver is done a - * similar way and actually re-uses several enumerations (configuration values) - * from the regular SERCOM SPI driver. - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_sercom_spi_master_vec_prerequisites - * - \ref asfdoc_sam0_sercom_spi_master_vec_module_overview - * - \ref asfdoc_sam0_sercom_spi_master_vec_special_considerations - * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_info - * - \ref asfdoc_sam0_sercom_spi_master_vec_examples - * - \ref asfdoc_sam0_sercom_spi_master_vec_api_overview - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_prerequisites Prerequisites - * - * This driver uses the \ref asfdoc_sam0_system_clock_group "SYSTEM clock driver" - * to select the SERCOM's clock source and to configure the SERCOM for the - * desired baud rate. Ensure that the selected clock source is configured and - * that the clock system is initialized. This is typically done indirectly with - * \ref system_init(), or directly with \ref system_clock_init(). - * - * According to the datasheet, the minimum and maximum limits for the baud rate - * is given by: \f$ \frac{1}{2^{17}} \times f_{clk} \le f_{baud} - * \le \frac{1}{2} \times f_{clk} \f$. - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_module_overview Module Overview - * - * This SERCOM SPI master driver supports uni- and bidirectional transfers of - * 8-bit data with vectored I/O, also know as scatter/gather. - * It does not implement control of SS or slave addressing since the intended - * usage is in stacks which usually have their own protocols and handshaking - * schemes. - * - * - * \subsection asfdoc_sam0_sercom_spi_master_vectored_io Vectored I/O - * - * Vectored I/O enables the transfer of data from/to any number of buffers with - * arbitrary memory locations without having to do several transfers, i.e., one - * buffer at a time. This feature is useful in stacks because it allows each - * layer of the stack to have a dedicated data buffer, thus avoiding the need - * for a centralized data buffer that the different layers must use in - * cooperation. - * - * The vectored I/O relies on arrays of buffer descriptors which must be passed - * to the driver to start a transfer. These buffer descriptors specify where in - * memory each buffer is, and how large they are. - * \ref asfdoc_sam0_vectored_io_example "The figure below" illustrates this - * for an example with three buffers of varying sizes that are transmitted. - * - * \anchor asfdoc_sam0_vectored_io_example - * \dot -digraph bufptr_to_spiord { - rankdir=LR; - subgraph cluster_bufptr { - style=invis; - bufptr_label [shape=none, label="Buffer descriptors"]; - bufptrs [shape=record, label=" [0]| [1]| [2]| [3]"]; - } - subgraph cluster_buf { - style=invis; - buf_label [shape=none, label="Memory layout"]; - bufs [shape=record, label="...|"yy"|...|"z"|"xxx"|..."]; - } - subgraph cluster_spiord { - style=invis; - spiord_label [shape=none, label="SPI transmission"]; - spiord [shape=record, label=""yy"|"xxx"|"z""]; - } - bufptrs:bf1 -> bufs:b1 -> spiord:s1; - bufptrs:bf2 -> bufs:b2 -> spiord:s2; - bufptrs:bf3 -> bufs:b3 -> spiord:s3; - bufptrs:bf4 -> "none"; -} - * \enddot - * - * Note that the last descriptor \e must indicate no next buffer in order for - * the driver to detect that the end of the buffer list has been reached. This - * means that for \c N buffers, \c N+1 buffer descriptors are needed. - * - * Bidirectional transfers are supported without any restrictions on the buffer - * descriptors, so the number of bytes and buffers to receive and transmit do - * \e not have to be the same. - * - * \sa spi_master_vec_transceive_buffer_job() for details on starting transfers. - * - * - * \subsection asfdoc_sam0_sercom_spi_master_os_support OS support - * - * Since this driver is interrupt-driven, it is possible for the MCU to run - * other code while a transfer is on-going. - * - * In a single-threaded application, this can be achieved by starting a transfer - * and then avoid any waiting for completion until absolutely required, e.g., - * when a new transfer is needed. - * - * But in a multi-threaded application, for example based on FreeRTOS, one can - * utilize \e semaphores to let the OS know when a function is waiting and thus - * blocking the thread, and that other threads can be run instead. Put another - * way, the waiting can be made efficient. - * - * This driver has an internal semaphore which is used to signal to the OS - * whenever a function is waiting for a transfer to complete. And since the - * semaphore datatypes and functions are OS-specific, the support has been made - * configurable by the use of macros. Note that support for FreeRTOS is already - * implemented, but must be enabled. - * - * \sa CONF_SPI_MASTER_VEC_OS_SUPPORT for more on the configurable OS support. - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_sercom_spi_master_vec_special_isr Interrupt safety - * - * This driver should not be used within interrupt contexts. The reason for this - * is that the driver itself is interrupt driven. Further, the configurable OS - * support is implemented with the assumption that transfers are only started - * in threads, not in interrupt service routines, because it gives the simplest - * API. - * - * - * \subsection asfdoc_sam0_sercom_spi_master_vec_special_mux Signal MUX - * - * The SERCOM module has two layers of signal multiplexing in SPI mode: - * -# SERCOM pad MUX: This routes the SPI signals to internal lines. - * -# PORT pin MUX: This routes the internal line to a device pin. - * - * Both of these layers are configured in the \ref spi_master_vec_config - * "configuration structure", using the members named \c mux_setting and - * \c pinmux_padN. These must be set in combination. - * - * The driver supplies values for the - * \ref spi_master_vec_config::mux_setting "SERCOM pad MUX" from the standard - * ASF SERCOM SPI driver. For the PORT pin MUX configuration, refer to the - * peripheral include file for the device (\c pio_samd20XNN.h ) and use the - * macros that are prefixed with \c PINMUX_, such as - * \c PINMUX_PA04D_SERCOM0_PAD0. It is also possible to use the default pin MUX - * setting for a SERCOM pad by using the \ref PINMUX_DEFAULT macro. The defaults - * are defined in the file \ref sercom_pinout.h. - * - * Note that for \ref spi_master_vec_init() to function properly with the macro - * \ref PINMUX_DEFAULT, the order of the values in \c pinmux_padN \e must be - * correct, i.e., \c pinmux_pad0 must contain the pin MUX setting for - * multiplexing SERCOM pad 0, and so on. - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_extra_info Extra Information - * - * For extra information, see - * \subpage asfdoc_sam0_sercom_spi_master_vec_extra. This includes: - * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_acronyms - * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_dependencies - * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_errata - * - \ref asfdoc_sam0_sercom_spi_master_vec_extra_history - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_sercom_spi_master_vec_exqsg. - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_api_overview API Overview - * - * @{ - */ - -/** - * Driver configuration structure - * - * \sa asfdoc_sam0_sercom_spi_master_vec_special_considerations for more - * information regarding SERCOM pad and pin MUX. - */ -struct spi_master_vec_config { - /** Baud rate in Hertz. */ - uint32_t baudrate; - /** GCLK generator to use for the SERCOM. */ - enum gclk_generator gclk_generator; - /** Enabled in sleep modes. */ - bool run_in_standby; - /** SERCOM pad MUX setting. */ - enum spi_signal_mux_setting mux_setting; - /** Transfer mode. */ - enum spi_transfer_mode transfer_mode; - /** Data order. */ - enum spi_data_order data_order; - /** Pin MUX setting for SERCOM pad 0. */ - uint32_t pinmux_pad0; - /** Pin MUX setting for SERCOM pad 1. */ - uint32_t pinmux_pad1; - /** Pin MUX setting for SERCOM pad 2. */ - uint32_t pinmux_pad2; - /** Pin MUX setting for SERCOM pad 4. */ - uint32_t pinmux_pad3; -}; - -/** Buffer length container. */ -typedef uint16_t spi_master_vec_buflen_t; - -/** Buffer descriptor structure. */ -struct spi_master_vec_bufdesc { - /** Pointer to buffer start. */ - void *data; - /** Length of buffer. */ - spi_master_vec_buflen_t length; -}; - -/** Transfer direction */ -enum _spi_master_vec_direction { - SPI_MASTER_VEC_DIRECTION_READ, - SPI_MASTER_VEC_DIRECTION_WRITE, - SPI_MASTER_VEC_DIRECTION_BOTH, - SPI_MASTER_VEC_DIRECTION_IDLE, -}; - -/** Driver instance. */ -struct spi_master_vec_module { -#if !defined(__DOXYGEN__) - Sercom *volatile sercom; - volatile bool locked; - volatile enum _spi_master_vec_direction direction; - volatile enum status_code status; - volatile spi_master_vec_buflen_t rx_length; - volatile spi_master_vec_buflen_t tx_length; - uint8_t *volatile rx_head_ptr; - uint8_t *volatile tx_head_ptr; - volatile uint_fast8_t tx_lead_on_rx; - struct spi_master_vec_bufdesc *volatile rx_bufdesc_ptr; - struct spi_master_vec_bufdesc *volatile tx_bufdesc_ptr; -# ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT - CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE busy_semaphore; -# endif -#endif -}; - -/** - * \name Configuration and Initialization - * @{ - */ - -/** - * \brief Initialize configuration with default values. - * - * \param[out] config Configuration struct to initialize. - */ -static inline void spi_master_vec_get_config_defaults( - struct spi_master_vec_config *const config) -{ - config->baudrate = 100000; - config->gclk_generator = GCLK_GENERATOR_0; - config->run_in_standby = false; - config->mux_setting = SPI_SIGNAL_MUX_SETTING_D; - config->transfer_mode = SPI_TRANSFER_MODE_0; - config->data_order = SPI_DATA_ORDER_MSB; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->pinmux_pad2 = PINMUX_DEFAULT; - config->pinmux_pad3 = PINMUX_DEFAULT; -} - -#ifdef __cplusplus -extern "C" { -#endif - -enum status_code spi_master_vec_init(struct spi_master_vec_module *const module, - Sercom *const sercom, const struct spi_master_vec_config *const config); - -/** @} */ - -/** - * \name Enable/Disable and Reset - * @{ - */ - -void spi_master_vec_enable(const struct spi_master_vec_module *const module); -void spi_master_vec_disable(struct spi_master_vec_module *const module); -void spi_master_vec_reset(struct spi_master_vec_module *const module); - -/** @} */ - -/** - * \name Lock/Unlock - * @{ - */ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock. - * - * \retval STATUS_OK if the module was locked. - * \retval STATUS_BUSY if the module was already locked. - */ -static inline enum status_code spi_master_vec_lock( - struct spi_master_vec_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock. - */ -static inline void spi_master_vec_unlock( - struct spi_master_vec_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \name Read/Write and Status - * @{ - */ - -enum status_code spi_master_vec_transceive_buffer_job( - struct spi_master_vec_module *const module, - struct spi_master_vec_bufdesc tx_bufdescs[], - struct spi_master_vec_bufdesc rx_bufdescs[]); - -/** - * \brief Get current status of transfer. - * - * \param[in] module Driver instance to operate on. - * - * \return Current status of driver instance. - * \retval STATUS_OK if idle and previous transfer succeeded. - * \retval STATUS_BUSY if a transfer is ongoing. - * \retval if previous transfer failed. - */ -static inline enum status_code spi_master_vec_get_job_status( - const struct spi_master_vec_module *const module) -{ - return module->status; -} - -/** - * \brief Get status of transfer upon job end. - * - * \param[in] module Driver instance to operate on. - * - * \return Current status of driver instance. - * \retval STATUS_OK if idle and previous transfer succeeded. - * \retval if previous transfer failed. - */ -static inline enum status_code spi_master_vec_get_job_status_wait( - const struct spi_master_vec_module *const module) -{ - enum status_code status; - -#ifdef CONF_SPI_MASTER_VEC_OS_SUPPORT - CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE(module->busy_semaphore); - status = spi_master_vec_get_job_status(module); - CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE(module->busy_semaphore); -#else - do { - status = spi_master_vec_get_job_status(module); - } while (status == STATUS_BUSY); -#endif - - return status; -} - - -/** - * \brief Start vectored I/O transfer, wait for it to end. - * - * \param[in,out] module Driver instance to operate on. - * \param[in] tx_bufdescs address of buffer descriptor array for bytes to - * transmit. - * \arg \c NULL if the transfer is a simplex read. - * \param[in,out] rx_bufdescs address of buffer descriptor array for storing - * received bytes. - * \arg \c NULL if the transfer is a simplex write. - * - * \return Status of transfer start. - * \retval STATUS_OK if transfer succeeded. - * \retval STATUS_BUSY if a transfer was already on-going. - * \retval if transfer failed. - */ -static inline enum status_code spi_master_vec_transceive_buffer_wait( - struct spi_master_vec_module *const module, - struct spi_master_vec_bufdesc tx_bufdescs[], - struct spi_master_vec_bufdesc rx_bufdescs[]) -{ - enum status_code status; - - status = spi_master_vec_transceive_buffer_job(module, tx_bufdescs, - rx_bufdescs); - - if (status == STATUS_BUSY) { - return status; - } - - return spi_master_vec_get_job_status_wait(module); -} - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \name OS Support Configuration - * @{ - */ - -/** - * \def CONF_SPI_MASTER_VEC_OS_SUPPORT - * \brief Enable support for OS - * - * Defining this symbol will enable support for an OS, e.g., FreeRTOS, by using - * the macros in this group: - * - \ref CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE - * - \ref CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE - * - \ref CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE - * - \ref CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE - * - \ref CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE - * - \ref CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR - * - * The user must ensure that these macros map to the implementation for the OS - * that is used. Further, required includes must be added alongside these macros - * in \ref conf_spi_master_vec.h. - * - * The purpose of this configuration is to enable usage of the OS' semaphore - * system to wait for transfers to end rather than continuously polling the - * transfer status, which is an inefficient approach. - */ - -/** - * \def CONF_SPI_MASTER_VEC_SEMAPHORE_TYPE - * \brief Semaphore datatype - */ - -/** - * \def CONF_SPI_MASTER_VEC_CREATE_SEMAPHORE - * \brief Create/initialize semaphore - * - * \param semaphore Semaphore member in driver instance. - */ - -/** - * \def CONF_SPI_MASTER_VEC_DELETE_SEMAPHORE - * \brief Delete semaphore - * - * \param semaphore Semaphore member in driver instance. - */ - -/** - * \def CONF_SPI_MASTER_VEC_TAKE_SEMAPHORE - * \brief Wait for and take semaphore - * - * \param semaphore Semaphore member in driver instance. - */ - -/** - * \def CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE - * \brief Give semaphore back - * - * \param semaphore Semaphore member in driver instance. - */ - -/** - * \def CONF_SPI_MASTER_VEC_GIVE_SEMAPHORE_FROM_ISR - * \brief Give semaphore back from an ISR - * - * \param semaphore Semaphore member in driver instance. - */ - -/** @} */ - -/** - * @} - */ - -/** - * \page asfdoc_sam0_sercom_spi_master_vec_extra Extra Information for SERCOM SPI Master Driver w/ Vectored I/O - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_extra_acronyms Acronyms - * - * The table below presents the acronyms used in this module. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Acronym - * Description - *
GCLKGeneric Clock
MISOMaster Input, Slave Output
MOSIMaster Output, Slave Input
SCKSerial Clock
SPISerial Peripheral Interface
SSSlave Select
- * - * - * \section asfdoc_sam0_sercom_spi_master_vec_extra_dependencies Dependencies - * - * This driver has the following dependencies: - * - \ref asfdoc_sam0_system_group "System driver" - * - \ref group_sam0_utils "Compiler driver" - * - \ref asfdoc_sam0_port_group "Port driver" - * - \ref Common SERCOM driver base - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_extra_errata Errata - * - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_sercom_spi_master_vec_extra_history Module History - * - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in the - * table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - -/** - * \page asfdoc_sam0_sercom_spi_master_vec_exqsg Examples for SERCOM SPI Master Driver w/ Vectored I/O - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_sercom_spi_master_vec_group. QSGs are - * simple examples with step-by-step instructions to configure and use this - * driver in a selection of use cases. Note that QSGs can be compiled as a - * standalone application or be added to the user application. - * - * - \subpage asfdoc_sam0_sercom_spi_master_vec_basic - */ - - /** - * \page asfdoc_sam0_sercom_spi_master_vec_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
D12/2014Add SAM L21/C21 support.
C04/2014Add SAM D10/D11 support.
B03/2014Add SAMR21 support.
A01/2014Initial release
- */ - -#endif /* SPI_MASTER_VEC_H */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/usart/docimg/usart_frame.svg b/atmel-samd/asf/sam0/drivers/sercom/usart/docimg/usart_frame.svg deleted file mode 100644 index 2a75501849496..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/usart/docimg/usart_frame.svg +++ /dev/null @@ -1,272 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - Page-1 - - - Sheet.3 - - Sheet.1 - - - - Sheet.2 - - - - - Sheet.4 - - Sheet.5 - - - - Sheet.6 - - - - - Sheet.7 - - Sheet.8 - - - - Sheet.9 - - - - - Sheet.10 - - Sheet.11 - - - - Sheet.12 - - - - - Sheet.13 - - Sheet.14 - - - - Sheet.15 - - - - - Sheet.16 - - Sheet.17 - - - - Sheet.18 - - - - - Sheet.19 - - Sheet.20 - - - - Sheet.21 - - - - - Sheet.22 - 1 - - - - 1 - - Sheet.23 - 2 - - - - 2 - - Sheet.24 - 3 - - - - 3 - - Sheet.25 - 4 - - - - 4 - - Sheet.26 - [5] - - - - [5] - - Sheet.27 - [6] - - - - [6] - - Sheet.28 - [7] - - - - [7] - - Sheet.29 - [8] - - - - [8] - - Sheet.30 - - - - Sheet.31 - - Sheet.32 - - - - Sheet.33 - - - - - Sheet.34 - - - - Sheet.35 - - - - Sheet.37 - - - - Sheet.38 - 0 - - - - 0 - - Sheet.39 - St - - - - St - - Sheet.40 - (IDLE) - - - - (IDLE) - - Sheet.41 - Sp1 - - - - Sp1 - - Sheet.42 - [Sp2] - - - - [Sp2] - - Sheet.43 - (St/IDLE) - - - - (St/IDLE) - - Sheet.44 - - - - Sheet.45 - - - - Sheet.240 - - - - Sheet.36 - - - - Sheet.241 - [P] - - - - [P] - - Sheet.242 - Frame - - - - - Frame - - diff --git a/atmel-samd/asf/sam0/drivers/sercom/usart/usart.c b/atmel-samd/asf/sam0/drivers/sercom/usart/usart.c deleted file mode 100644 index ab1c3bacff561..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/usart/usart.c +++ /dev/null @@ -1,817 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM USART Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "usart.h" -#include -#if USART_CALLBACK_MODE == true -# include "usart_interrupt.h" -#endif - -/** - * \internal - * Set Configuration of the USART module - */ -static enum status_code _usart_set_config( - struct usart_module *const module, - const struct usart_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Index for generic clock */ - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - - /* Cache new register values to minimize the number of register writes */ - uint32_t ctrla = 0; - uint32_t ctrlb = 0; -#ifdef FEATURE_USART_ISO7816 - uint32_t ctrlc = 0; -#endif - uint16_t baud = 0; - uint32_t transfer_mode; - - enum sercom_asynchronous_operation_mode mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - enum sercom_asynchronous_sample_num sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - -#ifdef FEATURE_USART_OVER_SAMPLE - switch (config->sample_rate) { - case USART_SAMPLE_RATE_16X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - break; - case USART_SAMPLE_RATE_8X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; - break; - case USART_SAMPLE_RATE_3X_ARITHMETIC: - mode = SERCOM_ASYNC_OPERATION_MODE_ARITHMETIC; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_3; - break; - case USART_SAMPLE_RATE_16X_FRACTIONAL: - mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_16; - break; - case USART_SAMPLE_RATE_8X_FRACTIONAL: - mode = SERCOM_ASYNC_OPERATION_MODE_FRACTIONAL; - sample_num = SERCOM_ASYNC_SAMPLE_NUM_8; - break; - } -#endif - - /* Set data order, internal muxing, and clock polarity */ - ctrla = (uint32_t)config->data_order | - (uint32_t)config->mux_setting | - #ifdef FEATURE_USART_OVER_SAMPLE - config->sample_adjustment | - config->sample_rate | - #endif - #ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - (config->immediate_buffer_overflow_notification << SERCOM_USART_CTRLA_IBON_Pos) | - #endif - (config->clock_polarity_inverted << SERCOM_USART_CTRLA_CPOL_Pos); - - enum status_code status_code = STATUS_OK; - - transfer_mode = (uint32_t)config->transfer_mode; -#ifdef FEATURE_USART_ISO7816 - if(config->iso7816_config.enabled) { - transfer_mode = config->iso7816_config.protocol_t; - } -#endif - /* Get baud value from mode and clock */ -#ifdef FEATURE_USART_ISO7816 - if(config->iso7816_config.enabled) { - baud = config->baudrate; - } else { -#endif - switch (transfer_mode) - { - case USART_TRANSFER_SYNCHRONOUSLY: - if (!config->use_external_clock) { - status_code = _sercom_get_sync_baud_val(config->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud); - } - - break; - - case USART_TRANSFER_ASYNCHRONOUSLY: - if (config->use_external_clock) { - status_code = - _sercom_get_async_baud_val(config->baudrate, - config->ext_clock_freq, &baud, mode, sample_num); - } else { - status_code = - _sercom_get_async_baud_val(config->baudrate, - system_gclk_chan_get_hz(gclk_index), &baud, mode, sample_num); - } - - break; - } - - /* Check if calculating the baudrate failed */ - if (status_code != STATUS_OK) { - /* Abort */ - return status_code; - } -#ifdef FEATURE_USART_ISO7816 - } -#endif - -#ifdef FEATURE_USART_IRDA - if(config->encoding_format_enable) { - usart_hw->RXPL.reg = config->receive_pulse_length; - } -#endif - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /*Set baud val */ - usart_hw->BAUD.reg = baud; - - /* Set sample mode */ - ctrla |= transfer_mode; - - if (config->use_external_clock == false) { - ctrla |= SERCOM_USART_CTRLA_MODE(0x1); - } - else { - ctrla |= SERCOM_USART_CTRLA_MODE(0x0); - } - - /* Set stopbits and enable transceivers */ - ctrlb = - #ifdef FEATURE_USART_IRDA - (config->encoding_format_enable << SERCOM_USART_CTRLB_ENC_Pos) | - #endif - #ifdef FEATURE_USART_START_FRAME_DECTION - (config->start_frame_detection_enable << SERCOM_USART_CTRLB_SFDE_Pos) | - #endif - #ifdef FEATURE_USART_COLLISION_DECTION - (config->collision_detection_enable << SERCOM_USART_CTRLB_COLDEN_Pos) | - #endif - (config->receiver_enable << SERCOM_USART_CTRLB_RXEN_Pos) | - (config->transmitter_enable << SERCOM_USART_CTRLB_TXEN_Pos); - -#ifdef FEATURE_USART_ISO7816 - if(config->iso7816_config.enabled) { - ctrla |= SERCOM_USART_CTRLA_FORM(0x07); - if (config->iso7816_config.enable_inverse) { - ctrla |= SERCOM_USART_CTRLA_TXINV | SERCOM_USART_CTRLA_RXINV; - } - ctrlb |= USART_CHARACTER_SIZE_8BIT; - - switch(config->iso7816_config.protocol_t) { - case ISO7816_PROTOCOL_T_0: - ctrlb |= (uint32_t)config->stopbits; - ctrlc |= SERCOM_USART_CTRLC_GTIME(config->iso7816_config.guard_time) | \ - (config->iso7816_config.inhibit_nack) | \ - (config->iso7816_config.successive_recv_nack) | \ - SERCOM_USART_CTRLC_MAXITER(config->iso7816_config.max_iterations); - break; - case ISO7816_PROTOCOL_T_1: - ctrlb |= USART_STOPBITS_1; - break; - } - } else { -#endif - ctrlb |= (uint32_t)config->character_size; - /* Check parity mode bits */ - if (config->parity != USART_PARITY_NONE) { - ctrla |= SERCOM_USART_CTRLA_FORM(1); - ctrlb |= config->parity; - } else { -#ifdef FEATURE_USART_LIN_SLAVE - if(config->lin_slave_enable) { - ctrla |= SERCOM_USART_CTRLA_FORM(0x4); - } else { - ctrla |= SERCOM_USART_CTRLA_FORM(0); - } -#else - ctrla |= SERCOM_USART_CTRLA_FORM(0); -#endif - } -#ifdef FEATURE_USART_ISO7816 - } -#endif - -#ifdef FEATURE_USART_LIN_MASTER - usart_hw->CTRLC.reg = ((usart_hw->CTRLC.reg) & SERCOM_USART_CTRLC_GTIME_Msk) - | config->lin_header_delay - | config->lin_break_length; - - if (config->lin_node != LIN_INVALID_MODE) { - ctrla &= ~(SERCOM_USART_CTRLA_FORM(0xf)); - ctrla |= config->lin_node; - } -#endif - - /* Set whether module should run in standby. */ - if (config->run_in_standby || system_is_debugger_present()) { - ctrla |= SERCOM_USART_CTRLA_RUNSTDBY; - } - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Write configuration to CTRLB */ - usart_hw->CTRLB.reg = ctrlb; - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Write configuration to CTRLA */ - usart_hw->CTRLA.reg = ctrla; - -#ifdef FEATURE_USART_RS485 - if ((usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_FORM_Msk) != \ - SERCOM_USART_CTRLA_FORM(0x07)) { - usart_hw->CTRLC.reg &= ~(SERCOM_USART_CTRLC_GTIME(0x7)); - usart_hw->CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(config->rs485_guard_time); - } -#endif - -#ifdef FEATURE_USART_ISO7816 - if(config->iso7816_config.enabled) { - _usart_wait_for_sync(module); - usart_hw->CTRLC.reg = ctrlc; - } -#endif - - return STATUS_OK; -} - -/** - * \brief Initializes the device - * - * Initializes the USART device based on the setting specified in the - * configuration struct. - * - * \param[out] module Pointer to USART device - * \param[in] hw Pointer to USART hardware instance - * \param[in] config Pointer to configuration struct - * - * \return Status of the initialization. - * - * \retval STATUS_OK The initialization was successful - * \retval STATUS_BUSY The USART module is busy - * resetting - * \retval STATUS_ERR_DENIED The USART has not been disabled in - * advance of initialization - * \retval STATUS_ERR_INVALID_ARG The configuration struct contains - * invalid configuration - * \retval STATUS_ERR_ALREADY_INITIALIZED The SERCOM instance has already been - * initialized with different clock - * configuration - * \retval STATUS_ERR_BAUD_UNAVAILABLE The BAUD rate given by the - * configuration - * struct cannot be reached with - * the current clock configuration - */ -enum status_code usart_init( - struct usart_module *const module, - Sercom *const hw, - const struct usart_config *const config) -{ - /* Sanity check arguments */ - Assert(module); - Assert(hw); - Assert(config); - - enum status_code status_code = STATUS_OK; - - /* Assign module pointer to software instance struct */ - module->hw = hw; - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw); - uint32_t pm_index, gclk_index; -#if (SAML22) || (SAMC20) - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#elif (SAML21) || (SAMR30) - if (sercom_index == 5) { - pm_index = MCLK_APBDMASK_SERCOM5_Pos; - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#elif (SAMC21) - pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos; - - if (sercom_index == 5){ - gclk_index = SERCOM5_GCLK_ID_CORE; - } else { - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; - } -#else - pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos; - gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE; -#endif - - if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_SWRST) { - /* The module is busy resetting itself */ - return STATUS_BUSY; - } - - if (usart_hw->CTRLA.reg & SERCOM_USART_CTRLA_ENABLE) { - /* Check the module is enabled */ - return STATUS_ERR_DENIED; - } - - /* Turn on module in PM */ -#if (SAML21) || (SAMR30) - if (sercom_index == 5) { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index); - } else { - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); - } -#else - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index); -#endif - - /* Set up the GCLK for the module */ - struct system_gclk_chan_config gclk_chan_conf; - system_gclk_chan_get_config_defaults(&gclk_chan_conf); - gclk_chan_conf.source_generator = config->generator_source; - system_gclk_chan_set_config(gclk_index, &gclk_chan_conf); - system_gclk_chan_enable(gclk_index); - sercom_set_gclk_generator(config->generator_source, false); - - /* Set character size */ - module->character_size = config->character_size; - - /* Set transmitter and receiver status */ - module->receiver_enabled = config->receiver_enable; - module->transmitter_enabled = config->transmitter_enable; - -#ifdef FEATURE_USART_LIN_SLAVE - module->lin_slave_enabled = config->lin_slave_enable; -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - module->start_frame_detection_enabled = config->start_frame_detection_enable; -#endif -#ifdef FEATURE_USART_ISO7816 - module->iso7816_mode_enabled = config->iso7816_config.enabled; -#endif - /* Set configuration according to the config struct */ - status_code = _usart_set_config(module, config); - if(status_code != STATUS_OK) { - return status_code; - } - - struct system_pinmux_config pin_conf; - system_pinmux_get_config_defaults(&pin_conf); - pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE; - - uint32_t pad_pinmuxes[] = { - config->pinmux_pad0, config->pinmux_pad1, - config->pinmux_pad2, config->pinmux_pad3 - }; - - /* Configure the SERCOM pins according to the user configuration */ - for (uint8_t pad = 0; pad < 4; pad++) { - uint32_t current_pinmux = pad_pinmuxes[pad]; - - if (current_pinmux == PINMUX_DEFAULT) { - current_pinmux = _sercom_get_default_pad(hw, pad); - } - - if (current_pinmux != PINMUX_UNUSED) { - pin_conf.mux_position = current_pinmux & 0xFFFF; - system_pinmux_pin_set_config(current_pinmux >> 16, &pin_conf); - } - } - -#if USART_CALLBACK_MODE == true - /* Initialize parameters */ - for (uint32_t i = 0; i < USART_CALLBACK_N; i++) { - module->callback[i] = NULL; - } - - module->tx_buffer_ptr = NULL; - module->rx_buffer_ptr = NULL; - module->remaining_tx_buffer_length = 0x0000; - module->remaining_rx_buffer_length = 0x0000; - module->callback_reg_mask = 0x00; - module->callback_enable_mask = 0x00; - module->rx_status = STATUS_OK; - module->tx_status = STATUS_OK; - - /* Set interrupt handler and register USART software module struct in - * look-up table */ - uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw); - _sercom_set_handler(instance_index, _usart_interrupt_handler); - _sercom_instances[instance_index] = module; -#endif - - return status_code; -} - -/** - * \brief Transmit a character via the USART - * - * This blocking function will transmit a single character via the - * USART. - * - * \param[in] module Pointer to the software instance struct - * \param[in] tx_data Data to transfer - * - * \return Status of the operation. - * \retval STATUS_OK If the operation was completed - * \retval STATUS_BUSY If the operation was not completed, due to the USART - * module being busy - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_wait( - struct usart_module *const module, - const uint16_t tx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - -#if USART_CALLBACK_MODE == true - /* Check if the USART is busy doing asynchronous operation. */ - if (module->remaining_tx_buffer_length > 0) { - return STATUS_BUSY; - } - -#else - /* Check if USART is ready for new data */ - if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE)) { - /* Return error code */ - return STATUS_BUSY; - } -#endif - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Write data to USART module */ - usart_hw->DATA.reg = tx_data; - - while (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC)) { - /* Wait until data is sent */ - } - - return STATUS_OK; -} - -/** - * \brief Receive a character via the USART - * - * This blocking function will receive a character via the USART. - * - * \param[in] module Pointer to the software instance struct - * \param[out] rx_data Pointer to received data - * - * \return Status of the operation. - * \retval STATUS_OK If the operation was completed - * \retval STATUS_BUSY If the operation was not completed, - * due to the USART module being busy - * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed, - * due to configuration mismatch between USART - * and the sender - * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed, - * due to the baudrate being too low or the - * system frequency being too high - * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due to - * data being corrupted - * \retval STATUS_ERR_DENIED If the receiver is not enabled - */ -enum status_code usart_read_wait( - struct usart_module *const module, - uint16_t *const rx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Error variable */ - uint8_t error_code; - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - -#if USART_CALLBACK_MODE == true - /* Check if the USART is busy doing asynchronous operation. */ - if (module->remaining_rx_buffer_length > 0) { - return STATUS_BUSY; - } -#endif - - /* Check if USART has new data */ - if (!(usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC)) { - /* Return error code */ - return STATUS_BUSY; - } - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Read out the status code and mask away all but the 3 LSBs*/ - error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); - - /* Check if an error has occurred during the receiving */ - if (error_code) { - /* Check which error occurred */ - if (error_code & SERCOM_USART_STATUS_FERR) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR; - - return STATUS_ERR_BAD_FORMAT; - } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - - return STATUS_ERR_OVERFLOW; - } else if (error_code & SERCOM_USART_STATUS_PERR) { - /* Clear flag by writing a 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR; - - return STATUS_ERR_BAD_DATA; - } -#ifdef FEATURE_USART_LIN_SLAVE - else if (error_code & SERCOM_USART_STATUS_ISF) { - /* Clear flag by writing 1 to it and - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF; - - return STATUS_ERR_PROTOCOL; - } -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - else if (error_code & SERCOM_USART_STATUS_COLL) { - /* Clear flag by writing 1 to it - * return with an error code */ - usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL; - - return STATUS_ERR_PACKET_COLLISION; - } -#endif - } - - /* Read data from USART module */ - *rx_data = usart_hw->DATA.reg; - - return STATUS_OK; -} - -/** - * \brief Transmit a buffer of characters via the USART - * - * This blocking function will transmit a block of \c length characters - * via the USART. - * - * \note Using this function in combination with the interrupt (\c _job) functions is - * not recommended as it has no functionality to check if there is an - * ongoing interrupt driven operation running or not. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Pointer to data to transmit - * \param[in] length Number of characters to transmit - * - * \note If using 9-bit data, the array that *tx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define TX_LEN 3 - uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133}; - usart_write_buffer_wait(&module, (uint8_t*)tx_buf, TX_LEN); - \endcode - * - * \return Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid - * arguments - * \retval STATUS_ERR_TIMEOUT If operation was not completed, due to USART - * module timing out - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_buffer_wait( - struct usart_module *const module, - const uint8_t *tx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Check if the buffer length is valid */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - uint16_t tx_pos = 0; - - /* Blocks while buffer is being transferred */ - while (length--) { - /* Wait for the USART to be ready for new data and abort - * operation if it doesn't get ready within the timeout*/ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - - /* Data to send is at least 8 bits long */ - uint16_t data_to_send = tx_data[tx_pos++]; - - /* Check if the character size exceeds 8 bit */ - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - data_to_send |= (tx_data[tx_pos++] << 8); - } - - /* Send the data through the USART module */ - usart_write_wait(module, data_to_send); - } - - /* Wait until Transmit is complete or timeout */ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - - return STATUS_OK; -} - -/** - * \brief Receive a buffer of \c length characters via the USART - * - * This blocking function will receive a block of \c length characters - * via the USART. - * - * \note Using this function in combination with the interrupt (\c *_job) - * functions is not recommended as it has no functionality to check if - * there is an ongoing interrupt driven operation running or not. - * - * \param[in] module Pointer to USART software instance struct - * \param[out] rx_data Pointer to receive buffer - * \param[in] length Number of characters to receive - * - * \note If using 9-bit data, the array that *rx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define RX_LEN 3 - uint16_t rx_buf[RX_LEN] = {0x0,}; - usart_read_buffer_wait(&module, (uint8_t*)rx_buf, RX_LEN); - \endcode - * - * \return Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to an - * invalid argument being supplied - * \retval STATUS_ERR_TIMEOUT If operation was not completed, due - * to USART module timing out - * \retval STATUS_ERR_BAD_FORMAT If the operation was not completed, - * due to a configuration mismatch - * between USART and the sender - * \retval STATUS_ERR_BAD_OVERFLOW If the operation was not completed, - * due to the baudrate being too low or the - * system frequency being too high - * \retval STATUS_ERR_BAD_DATA If the operation was not completed, due - * to data being corrupted - * \retval STATUS_ERR_DENIED If the receiver is not enabled - */ -enum status_code usart_read_buffer_wait( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Check if the buffer length is valid */ - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - uint16_t rx_pos = 0; - - /* Blocks while buffer is being received */ - while (length--) { - /* Wait for the USART to have new data and abort operation if it - * doesn't get ready within the timeout*/ - for (uint32_t i = 0; i <= USART_TIMEOUT; i++) { - if (usart_hw->INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) { - break; - } else if (i == USART_TIMEOUT) { - return STATUS_ERR_TIMEOUT; - } - } - - enum status_code retval; - uint16_t received_data = 0; - - retval = usart_read_wait(module, &received_data); - - if (retval != STATUS_OK) { - /* Overflow, abort */ - return retval; - } - - /* Read value will be at least 8-bits long */ - rx_data[rx_pos++] = received_data; - - /* If 9-bit data, write next received byte to the buffer */ - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - rx_data[rx_pos++] = (received_data >> 8); - } - } - - return STATUS_OK; -} diff --git a/atmel-samd/asf/sam0/drivers/sercom/usart/usart.h b/atmel-samd/asf/sam0/drivers/sercom/usart/usart.h deleted file mode 100644 index ac79c1116560d..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/usart/usart.h +++ /dev/null @@ -1,1593 +0,0 @@ -/** - * - * \file - * - * \brief SAM SERCOM USART Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef USART_H_INCLUDED -#define USART_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_sercom_usart_group SAM Serial USART (SERCOM USART) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the SERCOM module in - * its USART mode to transfer or receive USART data frames. The following driver - * API modes are covered by this manual: - * - * - Polled APIs - * \if USART_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - SERCOM (Serial Communication Interface) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_sercom_usart_prerequisites - * - \ref asfdoc_sam0_sercom_usart_overview - * - \ref asfdoc_sam0_sercom_usart_special_considerations - * - \ref asfdoc_sam0_sercom_usart_extra_info - * - \ref asfdoc_sam0_sercom_usart_examples - * - \ref asfdoc_sam0_sercom_usart_api_overview - * - * \section asfdoc_sam0_sercom_usart_prerequisites Prerequisites - * - * To use the USART you need to have a GCLK generator enabled and running - * that can be used as the SERCOM clock source. This can either be configured - * in conf_clocks.h or by using the system clock driver. - * - * \section asfdoc_sam0_sercom_usart_overview Module Overview - * - * This driver will use one (or more) SERCOM interface(s) in the system - * and configure it to run as a USART interface in either synchronous - * or asynchronous mode. - * - * \subsection asfdoc_sam0_sercom_usart_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_USART_SYNC_SCHEME_V2SAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_OVER_SAMPLESAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_HARDWARE_FLOW_CONTROLSAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_IRDASAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_LIN_SLAVESAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_COLLISION_DECTIONSAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_START_FRAME_DECTIONSAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATIONSAM D21/R21/D09/D10/D11/L21/L22/DA1/C20/C21
FEATURE_USART_RS485SAM C20/C21
FEATURE_USART_LIN_MASTERSAM L22/C20/C21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_sercom_usart_overview_frame_format Frame Format - * - * Communication is based on frames, where the frame format can be customized - * to accommodate a wide range of standards. A frame consists of a start bit, - * a number of data bits, an optional parity bit for error detection as well - * as a configurable length stop bit(s) - see - * \ref asfdoc_sam0_sercom_usart_frame_diagram "the figure below". - * \ref asfdoc_sam0_sercom_usart_frame_params "The table below" shows the - * available parameters you can change in a frame. - * - * \anchor asfdoc_sam0_sercom_usart_frame_params - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
USART Frame Parameters
ParameterOptions
Start bit1
Data bits5, 6, 7, 8, 9
Parity bitNone, Even, Odd
Stop bits1, 2
- * - * \anchor asfdoc_sam0_sercom_usart_frame_diagram - * \image html usart_frame.svg "USART Frame Overview" width=100% - * - * \subsection asfdoc_sam0_sercom_usart_overview_sync Synchronous Mode - * - * In synchronous mode a dedicated clock line is provided; either by the USART - * itself if in master mode, or by an external master if in slave mode. - * Maximum transmission speed is the same as the GCLK clocking the USART - * peripheral when in slave mode, and the GCLK divided by two if in - * master mode. In synchronous mode the interface needs three lines to - * communicate: - * - TX (Transmit pin) - * - RX (Receive pin) - * - XCK (Clock pin) - * - * \subsubsection asfdoc_sam0_sercom_usart_overview_sync_sampling Data Sampling - * In synchronous mode the data is sampled on either the rising or falling edge - * of the clock signal. This is configured by setting the clock polarity in the - * configuration struct. - * - * \subsection asfdoc_sam0_sercom_usart_overview_async Asynchronous Mode - * - * In asynchronous mode no dedicated clock line is used, and the communication - * is based on matching the clock speed on the transmitter and receiver. The - * clock is generated from the internal SERCOM baudrate generator, and the - * frames are synchronized by using the frame start bits. Maximum transmission - * speed is limited to the SERCOM GCLK divided by 16. - * In asynchronous mode the interface only needs two lines to communicate: - * - TX (Transmit pin) - * - RX (Receive pin) - * - * \subsubsection asfdoc_sam0_sercom_usart_overview_async_clock_matching Transmitter/receiver Clock Matching - * - * For successful transmit and receive using the asynchronous mode the receiver - * and transmitter clocks needs to be closely matched. When receiving a frame - * that does not match the selected baudrate closely enough the receiver will - * be unable to synchronize the frame(s), and garbage transmissions will - * result. - * - * \subsection asfdoc_sam0_sercom_usart_parity Parity - * Parity can be enabled to detect if a transmission was in error. This is done - * by counting the number of "1" bits in the frame. When using even parity the - * parity bit will be set if the total number of "1"s in the frame are an even - * number. If using odd parity the parity bit will be set if the total number - * of "1"s are odd. - * - * When receiving a character the receiver will count the number of "1"s in the - * frame and give an error if the received frame and parity bit disagree. - * - * \subsection asfdoc_sam0_sercom_usart_overview_pin_configuration GPIO Configuration - * - * The SERCOM module has four internal pads; the RX pin can be placed freely on - * any one of the four pads, and the TX and XCK pins have two predefined - * positions that can be selected as a pair. The pads can then be routed to an - * external GPIO pin using the normal pin multiplexing scheme on the SAM. - * - * \section asfdoc_sam0_sercom_usart_special_considerations Special Considerations - * - * \if USART_CALLBACK_MODE - * Never execute large portions of code in the callbacks. These - * are run from the interrupt routine, and thus having long callbacks will - * keep the processor in the interrupt handler for an equally long time. - * A common way to handle this is to use global flags signaling the - * main application that an interrupt event has happened, and only do the - * minimal needed processing in the callback. - * \else - * No special considerations. - * \endif - * - * \section asfdoc_sam0_sercom_usart_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_sercom_usart_extra. This includes: - * - \ref asfdoc_sam0_sercom_usart_extra_acronyms - * - \ref asfdoc_sam0_sercom_usart_extra_dependencies - * - \ref asfdoc_sam0_sercom_usart_extra_errata - * - \ref asfdoc_sam0_sercom_usart_extra_history - * - * \section asfdoc_sam0_sercom_usart_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_sercom_usart_exqsg. - * - * \section asfdoc_sam0_sercom_usart_api_overview API Overview - * @{ - */ - -#include -#include -#include - -#if USART_CALLBACK_MODE == true -# include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name Driver Feature Definition - * Define SERCOM USART features set according to different device family. - * @{ - */ -#if (SAMD21) || (SAMR21) || (SAMD09) || (SAMD10) || (SAMD11) || (SAML21) || \ - (SAML22) ||(SAMDA1) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__) -/** USART sync scheme version 2. */ -# define FEATURE_USART_SYNC_SCHEME_V2 -/** USART oversampling. */ -# define FEATURE_USART_OVER_SAMPLE -/** USART hardware control flow. */ -# define FEATURE_USART_HARDWARE_FLOW_CONTROL -/** IrDA mode. */ -# define FEATURE_USART_IRDA -/** LIN slave mode. */ -# define FEATURE_USART_LIN_SLAVE -/** USART collision detection. */ -# define FEATURE_USART_COLLISION_DECTION -/** USART start frame detection. */ -# define FEATURE_USART_START_FRAME_DECTION -/** USART start buffer overflow notification. */ -# define FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION -#endif - -#if (SAML22) || defined(__DOXYGEN__) -/** ISO7816 for smart card interfacing. */ -#define FEATURE_USART_ISO7816 -#endif -#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** LIN master mode. */ -#define FEATURE_USART_LIN_MASTER -#endif -#if (SAML22) || (SAMC20) || (SAMC21) || defined(__DOXYGEN__) -/** RS485 mode. */ -# define FEATURE_USART_RS485 -#endif -/*@}*/ - -#ifdef FEATURE_USART_LIN_MASTER -/** - * \brief LIN node type - * - * LIN node type. - */ -enum lin_node_type { - /** LIN master mode */ - LIN_MASTER_NODE = SERCOM_USART_CTRLA_FORM(0x02), - /** LIN slave mode */ - LIN_SLAVE_NODE = SERCOM_USART_CTRLA_FORM(0x04), - /** Neither LIN master nor LIN slave mode */ - LIN_INVALID_MODE = SERCOM_USART_CTRLA_FORM(0x00), -}; - -/** - * \brief LIN master command enum - * - * LIN master command enum. - */ -enum lin_master_cmd { - /** LIN master software control transmission command */ - LIN_MASTER_SOFTWARE_CONTROL_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x01), - /** LIN master automatically transmission command */ - LIN_MASTER_AUTO_TRANSMIT_CMD = SERCOM_USART_CTRLB_LINCMD(0x02), -}; - -/** - * \brief LIN master header delay - * - * LIN master header delay between break and sync transmission, - * and between the sync and identifier (ID) fields. - * This field is only valid when using automatically transmission command - */ -enum lin_master_header_delay { - /** Delay between break and sync transmission is 1 bit time. - Delay between sync and ID transmission is 1 bit time. */ - LIN_MASTER_HEADER_DELAY_0 = SERCOM_USART_CTRLC_HDRDLY(0x0), - /** Delay between break and sync transmission is 4 bit time. - Delay between sync and ID transmission is 4 bit time. */ - LIN_MASTER_HEADER_DELAY_1 = SERCOM_USART_CTRLC_HDRDLY(0x01), - /** Delay between break and sync transmission is 8 bit time. - Delay between sync and ID transmission is 4 bit time. */ - LIN_MASTER_HEADER_DELAY_2 = SERCOM_USART_CTRLC_HDRDLY(0x02), - /** Delay between break and sync transmission is 14 bit time. - Delay between sync and ID transmission is 4 bit time. */ - LIN_MASTER_HEADER_DELAY_3 = SERCOM_USART_CTRLC_HDRDLY(0x03), -}; - -/** - * \brief LIN master break length - * - * Length of the break field transmitted when in LIN master mode - */ -enum lin_master_break_length { - /** Break field transmission is 13 bit times */ - LIN_MASTER_BREAK_LENGTH_13_BIT = SERCOM_USART_CTRLC_BRKLEN(0x0), - /** Break field transmission is 17 bit times */ - LIN_MASTER_BREAK_LENGTH_17_BIT = SERCOM_USART_CTRLC_BRKLEN(0x1), - /** Break field transmission is 21 bit times */ - LIN_MASTER_BREAK_LENGTH_21_BIT = SERCOM_USART_CTRLC_BRKLEN(0x2), - /** Break field transmission is 26 bit times */ - LIN_MASTER_BREAK_LENGTH_26_BIT = SERCOM_USART_CTRLC_BRKLEN(0x3), -}; -#endif -#ifdef FEATURE_USART_ISO7816 -/** - * \brief ISO7816 protocol type - * - * ISO7816 protocol type. - */ -enum iso7816_protocol_type { - /** ISO7816 protocol type 0 */ - ISO7816_PROTOCOL_T_0 = SERCOM_USART_CTRLA_CMODE, - /** ISO7816 protocol type 1 */ - ISO7816_PROTOCOL_T_1 = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos), -}; - -/** - * \brief ISO7816 guard time - * - * The value of ISO7816 guard time. - */ -enum iso7816_guard_time { - /** The guard time is 2-bit times */ - ISO7816_GUARD_TIME_2_BIT = 2, - /** The guard time is 3-bit times */ - ISO7816_GUARD_TIME_3_BIT, - /** The guard time is 4-bit times */ - ISO7816_GUARD_TIME_4_BIT, - /** The guard time is 5-bit times */ - ISO7816_GUARD_TIME_5_BIT, - /** The guard time is 6-bit times */ - ISO7816_GUARD_TIME_6_BIT, - /** The guard time is 7-bit times */ - ISO7816_GUARD_TIME_7_BIT, -}; - -/** - * \brief ISO7816 receive NACK inhibit - * - * The value of ISO7816 receive NACK inhibit. - */ -enum iso7816_inhibit_nack { - /** The NACK is generated */ - ISO7816_INHIBIT_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos), - /** The NACK is not generated */ - ISO7816_INHIBIT_NACK_ENABLE = SERCOM_USART_CTRLC_INACK, -}; - -/** - * \brief ISO7816 disable successive receive NACK - * - * The value of ISO7816 disable successive receive NACK. - */ -enum iso7816_successive_recv_nack { - /** The successive receive NACK is enable. */ - ISO7816_SUCCESSIVE_RECV_NACK_DISABLE = (0x0ul << SERCOM_USART_CTRLC_INACK_Pos), - /** The successive receive NACK is disable. */ - ISO7816_SUCCESSIVE_RECV_NACK_ENABLE = SERCOM_USART_CTRLC_DSNACK, -}; - -/** - * \brief ISO7816 configuration struct - * - * ISO7816 configuration structure. - */ -struct iso7816_config_t { - /* ISO7816 mode enable */ - bool enabled; - /** ISO7816 protocol type */ - enum iso7816_protocol_type protocol_t; - /** Enable inverse transmission and reception */ - bool enable_inverse; - /** Guard time, which lasts two bit times */ - enum iso7816_guard_time guard_time; - /** - * Inhibit Non Acknowledge: - * - 0: the NACK is generated; - * - 1: the NACK is not generated. - */ - enum iso7816_inhibit_nack inhibit_nack; - /** - * Disable successive NACKs. - * - 0: NACK is sent on the ISO line as soon as a parity error occurs - * in the received character. Successive parity errors are counted up to - * the value in the max_iterations field. These parity errors generate - * a NACK on the ISO line. As soon as this value is reached, no additional - * NACK is sent on the ISO line. The ITERATION flag is asserted. - */ - enum iso7816_successive_recv_nack successive_recv_nack; - /* Max number of repetitions */ - uint32_t max_iterations; -}; -#endif - -#ifndef PINMUX_DEFAULT -/** Default pinmux */ -# define PINMUX_DEFAULT 0 -#endif - -#ifndef PINMUX_UNUSED -/** Unused pinmux */ -# define PINMUX_UNUSED 0xFFFFFFFF -#endif - -#ifndef USART_TIMEOUT -/** USART timeout value */ -# define USART_TIMEOUT 0xFFFF -#endif - -#if USART_CALLBACK_MODE == true -/** - * \brief USART callback enum - * - * Callbacks for the Asynchronous USART driver. - */ -enum usart_callback { - /** Callback for buffer transmitted */ - USART_CALLBACK_BUFFER_TRANSMITTED, - /** Callback for buffer received */ - USART_CALLBACK_BUFFER_RECEIVED, - /** Callback for error */ - USART_CALLBACK_ERROR, -#ifdef FEATURE_USART_LIN_SLAVE - /** Callback for break character is received */ - USART_CALLBACK_BREAK_RECEIVED, -#endif -#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - /** Callback for a change is detected on the CTS pin */ - USART_CALLBACK_CTS_INPUT_CHANGE, -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - /** Callback for a start condition is detected on the RxD line */ - USART_CALLBACK_START_RECEIVED, -#endif -# if !defined(__DOXYGEN__) - /** Number of available callbacks */ - USART_CALLBACK_N, -# endif -}; -#endif - -/** - * \brief USART Data Order enum - * - * The data order decides which MSB or LSB is shifted out first when data is - * transferred. - */ -enum usart_dataorder { - /** The MSB will be shifted out first during transmission, - * and shifted in first during reception */ - USART_DATAORDER_MSB = 0, - /** The LSB will be shifted out first during transmission, - * and shifted in first during reception */ - USART_DATAORDER_LSB = SERCOM_USART_CTRLA_DORD, -}; - -/** - * \brief USART Transfer mode enum - * - * Select USART transfer mode. - */ -enum usart_transfer_mode { - /** Transfer of data is done synchronously */ - USART_TRANSFER_SYNCHRONOUSLY = (SERCOM_USART_CTRLA_CMODE), - /** Transfer of data is done asynchronously */ - USART_TRANSFER_ASYNCHRONOUSLY = (0x0ul << SERCOM_USART_CTRLA_CMODE_Pos), -}; - -/** - * \brief USART Parity enum - * - * Select parity USART parity mode. - */ -enum usart_parity { - /** For odd parity checking, the parity bit will be set if number of - * ones being transferred is even */ - USART_PARITY_ODD = SERCOM_USART_CTRLB_PMODE, - - /** For even parity checking, the parity bit will be set if number of - * ones being received is odd */ - USART_PARITY_EVEN = 0, - - /** No parity checking will be executed, and there will be no parity bit - * in the received frame */ - USART_PARITY_NONE = 0xFF, -}; - -/** - * \brief USART signal MUX settings - * - * Set the functionality of the SERCOM pins. - * - * See \ref asfdoc_sam0_sercom_usart_mux_settings for a description of the - * various MUX setting options. - */ -enum usart_signal_mux_settings { -#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - /** MUX setting RX_0_TX_0_XCK_1 */ - USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_0_TX_2_XCK_3 */ - USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_0_TX_0_RTS_2_CTS_3 */ - USART_RX_0_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_1_TX_0_XCK_1 */ - USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_1_TX_2_XCK_3 */ - USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_1_TX_0_RTS_2_CTS_3 */ - USART_RX_1_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_2_TX_0_XCK_1 */ - USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_2_TX_2_XCK_3 */ - USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_2_TX_0_RTS_2_CTS_3 */ - USART_RX_2_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(2)), - /** MUX setting RX_3_TX_0_XCK_1 */ - USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(0)), - /** MUX setting RX_3_TX_2_XCK_3 */ - USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(1)), - /** MUX setting USART_RX_3_TX_0_RTS_2_CTS_3 */ - USART_RX_3_TX_0_RTS_2_CTS_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(2)), -#ifdef FEATURE_USART_RS485 - /** MUX setting USART_RX_0_TX_0_XCK_1_TE_2 */ - USART_RX_0_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO(3)), - /** MUX setting USART_RX_1_TX_0_XCK_1_TE_2 */ - USART_RX_1_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO(3)), - /** MUX setting USART_RX_2_TX_0_XCK_1_TE_2 */ - USART_RX_2_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO(3)), - /** MUX setting USART_RX_3_TX_0_XCK_1_TE_2 */ - USART_RX_3_TX_0_XCK_1_TE_2 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO(3)), -#endif -#else - /** MUX setting RX_0_TX_0_XCK_1 */ - USART_RX_0_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(0)), - /** MUX setting RX_0_TX_2_XCK_3 */ - USART_RX_0_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(0) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_1_TX_0_XCK_1 */ - USART_RX_1_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(1)), - /** MUX setting RX_1_TX_2_XCK_3 */ - USART_RX_1_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(1) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_2_TX_0_XCK_1 */ - USART_RX_2_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(2)), - /** MUX setting RX_2_TX_2_XCK_3 */ - USART_RX_2_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(2) | SERCOM_USART_CTRLA_TXPO), - /** MUX setting RX_3_TX_0_XCK_1 */ - USART_RX_3_TX_0_XCK_1 = (SERCOM_USART_CTRLA_RXPO(3)), - /** MUX setting RX_3_TX_2_XCK_3 */ - USART_RX_3_TX_2_XCK_3 = (SERCOM_USART_CTRLA_RXPO(3) | SERCOM_USART_CTRLA_TXPO), -#endif -}; - -/** - * \brief USART Stop Bits enum - * - * Number of stop bits for a frame. - */ -enum usart_stopbits { - /** Each transferred frame contains one stop bit */ - USART_STOPBITS_1 = 0, - /** Each transferred frame contains two stop bits */ - USART_STOPBITS_2 = SERCOM_USART_CTRLB_SBMODE, -}; - -/** - * \brief USART Character Size - * - * Number of bits for the character sent in a frame. - */ -enum usart_character_size { - /** The char being sent in a frame is five bits long */ - USART_CHARACTER_SIZE_5BIT = SERCOM_USART_CTRLB_CHSIZE(5), - /** The char being sent in a frame is six bits long */ - USART_CHARACTER_SIZE_6BIT = SERCOM_USART_CTRLB_CHSIZE(6), - /** The char being sent in a frame is seven bits long */ - USART_CHARACTER_SIZE_7BIT = SERCOM_USART_CTRLB_CHSIZE(7), - /** The char being sent in a frame is eight bits long */ - USART_CHARACTER_SIZE_8BIT = SERCOM_USART_CTRLB_CHSIZE(0), - /** The char being sent in a frame is nine bits long */ - USART_CHARACTER_SIZE_9BIT = SERCOM_USART_CTRLB_CHSIZE(1), -}; - -#ifdef FEATURE_USART_OVER_SAMPLE -/** - * \brief USART Sample Rate - * - * The value of sample rate and baudrate generation mode. - */ -enum usart_sample_rate { - /** 16x over-sampling using arithmetic baudrate generation */ - USART_SAMPLE_RATE_16X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(0), - /** 16x over-sampling using fractional baudrate generation */ - USART_SAMPLE_RATE_16X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(1), - /** 8x over-sampling using arithmetic baudrate generation */ - USART_SAMPLE_RATE_8X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(2), - /** 8x over-sampling using fractional baudrate generation */ - USART_SAMPLE_RATE_8X_FRACTIONAL = SERCOM_USART_CTRLA_SAMPR(3), - /** 3x over-sampling using arithmetic baudrate generation */ - USART_SAMPLE_RATE_3X_ARITHMETIC = SERCOM_USART_CTRLA_SAMPR(4), -}; - -/** - * \brief USART Sample Adjustment - * - * The value of sample number used for majority voting. - */ -enum usart_sample_adjustment { - /** The first, middle and last sample number used for majority voting is 7-8-9 */ - USART_SAMPLE_ADJUSTMENT_7_8_9 = SERCOM_USART_CTRLA_SAMPA(0), - /** The first, middle and last sample number used for majority voting is 9-10-11 */ - USART_SAMPLE_ADJUSTMENT_9_10_11 = SERCOM_USART_CTRLA_SAMPA(1), - /** The first, middle and last sample number used for majority voting is 11-12-13 */ - USART_SAMPLE_ADJUSTMENT_11_12_13 = SERCOM_USART_CTRLA_SAMPA(2), - /** The first, middle and last sample number used for majority voting is 13-14-15 */ - USART_SAMPLE_ADJUSTMENT_13_14_15 = SERCOM_USART_CTRLA_SAMPA(3), -}; -#endif - -#ifdef FEATURE_USART_RS485 -/** - * \brief RS485 Guard Time - * - * The value of RS485 guard time. - */ -enum rs485_guard_time { - /** The guard time is 0-bit time */ - RS485_GUARD_TIME_0_BIT = 0, - /** The guard time is 1-bit time */ - RS485_GUARD_TIME_1_BIT, - /** The guard time is 2-bit times */ - RS485_GUARD_TIME_2_BIT, - /** The guard time is 3-bit times */ - RS485_GUARD_TIME_3_BIT, - /** The guard time is 4-bit times */ - RS485_GUARD_TIME_4_BIT, - /** The guard time is 5-bit times */ - RS485_GUARD_TIME_5_BIT, - /** The guard time is 6-bit times */ - RS485_GUARD_TIME_6_BIT, - /** The guard time is 7-bit times */ - RS485_GUARD_TIME_7_BIT, -}; -#endif - -/** - * \brief USART Transceiver - * - * Select Receiver or Transmitter. - */ -enum usart_transceiver_type { - /** The parameter is for the Receiver */ - USART_TRANSCEIVER_RX, - /** The parameter is for the Transmitter */ - USART_TRANSCEIVER_TX, -}; - -/** - * \brief USART configuration struct - * - * Configuration options for USART. - */ -struct usart_config { - /** USART bit order (MSB or LSB first) */ - enum usart_dataorder data_order; - /** USART in asynchronous or synchronous mode */ - enum usart_transfer_mode transfer_mode; - /** USART parity */ - enum usart_parity parity; - /** Number of stop bits */ - enum usart_stopbits stopbits; - /** USART character size */ - enum usart_character_size character_size; - /** USART pin out */ - enum usart_signal_mux_settings mux_setting; -#ifdef FEATURE_USART_OVER_SAMPLE - /** USART sample rate */ - enum usart_sample_rate sample_rate; - /** USART sample adjustment */ - enum usart_sample_adjustment sample_adjustment; -#endif -#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - /** Controls when the buffer overflow status bit is asserted when a buffer overflow occurs */ - bool immediate_buffer_overflow_notification; -#endif -#ifdef FEATURE_USART_IRDA - /** Enable IrDA encoding format */ - bool encoding_format_enable; - /** The minimum pulse length required for a pulse to be accepted by the IrDA receiver */ - uint8_t receive_pulse_length; -#endif -#ifdef FEATURE_USART_LIN_SLAVE - /** Enable LIN Slave Support */ - bool lin_slave_enable; -#endif - -#ifdef FEATURE_USART_LIN_MASTER - /** LIN node type */ - enum lin_node_type lin_node; - /** LIN master header delay */ - enum lin_master_header_delay lin_header_delay; - /** LIN Master Break Length */ - enum lin_master_break_length lin_break_length; -#endif - -#ifdef FEATURE_USART_START_FRAME_DECTION - /** Enable start of frame dection */ - bool start_frame_detection_enable; -#endif -#ifdef FEATURE_USART_ISO7816 - /** Enable ISO7816 for smart card interfacing */ - struct iso7816_config_t iso7816_config; -#endif -#ifdef FEATURE_USART_RS485 - /** RS485 guard time */ - enum rs485_guard_time rs485_guard_time; -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - /** Enable collision dection */ - bool collision_detection_enable; -#endif - /** USART baudrate */ - uint32_t baudrate; - /** Enable receiver */ - bool receiver_enable; - /** Enable transmitter */ - bool transmitter_enable; - - /** USART Clock Polarity. - * If true, data changes on falling XCK edge and - * is sampled at rising edge. - * If false, data changes on rising XCK edge and - * is sampled at falling edge. - * */ - bool clock_polarity_inverted; - - /** States whether to use the external clock applied to the XCK pin. - * In synchronous mode the shift register will act directly on the XCK clock. - * In asynchronous mode the XCK will be the input to the USART hardware module. - */ - bool use_external_clock; - /** External clock frequency in synchronous mode. - * This must be set if \c use_external_clock is true. */ - uint32_t ext_clock_freq; - /** If true the USART will be kept running in Standby sleep mode */ - bool run_in_standby; - /** GCLK generator source */ - enum gclk_generator generator_source; - /** PAD0 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pins for PAD0, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD0 - * function. Make sure that no other alternative multiplexing I/O is associated - * with the same USARTx PAD0. - */ - uint32_t pinmux_pad0; - /** PAD1 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pins for PAD1, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD1 - * function. Make sure that no other alternative multiplexing I/O is associated - * with the same USARTx PAD1. - */ - uint32_t pinmux_pad1; - /** PAD2 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pins for PAD2, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD2 - * function. Make sure that no other alternative multiplexing I/O is associated - * with the same USARTx PAD2. - */ - uint32_t pinmux_pad2; - /** PAD3 pinmux. - * - * If current USARTx has several alternative multiplexing I/O pins for PAD3, then - * only one peripheral multiplexing I/O can be enabled for current USARTx PAD3 - * function. Make sure that no other alternative multiplexing I/O is associated - * with the same USARTx PAD3. - */ - uint32_t pinmux_pad3; -}; - -#if USART_CALLBACK_MODE == true -/** - * \brief USART module instance - * - * Forward Declaration for the device instance. - */ -struct usart_module; - -/** - * \brief USART callback type - * - * Type of the callback functions. - */ -typedef void (*usart_callback_t)(struct usart_module *const module); -#endif - -/** - * \brief SERCOM USART driver software device instance structure. - * - * SERCOM USART driver software instance structure, used to retain software - * state information of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct usart_module { -#if !defined(__DOXYGEN__) - /** Pointer to the hardware instance */ - Sercom *hw; - /** Module lock */ - volatile bool locked; - /** Character size of the data being transferred */ - enum usart_character_size character_size; - /** Receiver enabled */ - bool receiver_enabled; - /** Transmitter enabled */ - bool transmitter_enabled; -#ifdef FEATURE_USART_LIN_SLAVE - /** LIN Slave Support enabled */ - bool lin_slave_enabled; -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - /** Start of frame dection enabled */ - bool start_frame_detection_enabled; -#endif -#ifdef FEATURE_USART_ISO7816 - /** ISO7816 mode enable */ - bool iso7816_mode_enabled; -#endif -# if USART_CALLBACK_MODE == true - /** Array to store callback function pointers in */ - usart_callback_t callback[USART_CALLBACK_N]; - /** Buffer pointer to where the next received character will be put */ - volatile uint8_t *rx_buffer_ptr; - - /** Buffer pointer to where the next character will be transmitted from - **/ - volatile uint8_t *tx_buffer_ptr; - /** Remaining characters to receive */ - volatile uint16_t remaining_rx_buffer_length; - /** Remaining characters to transmit */ - volatile uint16_t remaining_tx_buffer_length; - /** Bit mask for callbacks registered */ - uint8_t callback_reg_mask; - /** Bit mask for callbacks enabled */ - uint8_t callback_enable_mask; - /** Holds the status of the ongoing or last read operation */ - volatile enum status_code rx_status; - /** Holds the status of the ongoing or last write operation */ - volatile enum status_code tx_status; -# endif -#endif -}; - - /** - * \name Lock/Unlock - * @{ - */ - -/** - * \brief Attempt to get lock on driver instance - * - * This function checks the instance's lock, which indicates whether or not it - * is currently in use, and sets the lock if it was not already set. - * - * The purpose of this is to enable exclusive access to driver instances, so - * that, e.g., transactions by different services will not interfere with each - * other. - * - * \param[in,out] module Pointer to the driver instance to lock - * - * \retval STATUS_OK If the module was locked - * \retval STATUS_BUSY If the module was already locked - */ -static inline enum status_code usart_lock( - struct usart_module *const module) -{ - enum status_code status; - - system_interrupt_enter_critical_section(); - - if (module->locked) { - status = STATUS_BUSY; - } else { - module->locked = true; - status = STATUS_OK; - } - - system_interrupt_leave_critical_section(); - - return status; -} - -/** - * \brief Unlock driver instance - * - * This function clears the instance lock, indicating that it is available for - * use. - * - * \param[in,out] module Pointer to the driver instance to lock - * - */ -static inline void usart_unlock(struct usart_module *const module) -{ - module->locked = false; -} - -/** @} */ - -/** - * \brief Check if peripheral is busy syncing registers across clock domains - * - * Return peripheral synchronization status. If doing a non-blocking - * implementation this function can be used to check the sync state and hold of - * any new actions until sync is complete. If this function is not run; the - * functions will block until the sync has completed. - * - * \param[in] module Pointer to peripheral module - * - * \return Peripheral sync status. - * - * \retval true Peripheral is busy syncing - * \retval false Peripheral is not busy syncing and can be read/written without - * stalling the bus - */ -static inline bool usart_is_syncing( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - SercomUsart *const usart_hw = &(module->hw->USART); - -#ifdef FEATURE_USART_SYNC_SCHEME_V2 - return (usart_hw->SYNCBUSY.reg); -#else - return (usart_hw->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY); -#endif -} - -#if !defined (__DOXYGEN__) -/** - * \internal - * Waits until synchronization is complete - */ -static inline void _usart_wait_for_sync( - const struct usart_module *const module) -{ - /* Sanity check */ - Assert(module); - - while (usart_is_syncing(module)) { - /* Wait until the synchronization is complete */ - } -} -#endif - -/** - * \brief Initializes the device to predefined defaults - * - * Initialize the USART device to predefined defaults: - * - 8-bit asynchronous USART - * - No parity - * - One stop bit - * - 9600 baud - * - Transmitter enabled - * - Receiver enabled - * - GCLK generator 0 as clock source - * - Default pin configuration - * - * The configuration struct will be updated with the default - * configuration. - * - * \param[in,out] config Pointer to configuration struct - */ -static inline void usart_get_config_defaults( - struct usart_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Set default config in the config struct */ - config->data_order = USART_DATAORDER_LSB; - config->transfer_mode = USART_TRANSFER_ASYNCHRONOUSLY; - config->parity = USART_PARITY_NONE; - config->stopbits = USART_STOPBITS_1; - config->character_size = USART_CHARACTER_SIZE_8BIT; - config->baudrate = 9600; - config->receiver_enable = true; - config->transmitter_enable = true; - config->clock_polarity_inverted = false; - config->use_external_clock = false; - config->ext_clock_freq = 0; - config->mux_setting = USART_RX_1_TX_2_XCK_3; - config->run_in_standby = false; - config->generator_source = GCLK_GENERATOR_0; - config->pinmux_pad0 = PINMUX_DEFAULT; - config->pinmux_pad1 = PINMUX_DEFAULT; - config->pinmux_pad2 = PINMUX_DEFAULT; - config->pinmux_pad3 = PINMUX_DEFAULT; -#ifdef FEATURE_USART_OVER_SAMPLE - config->sample_adjustment = USART_SAMPLE_ADJUSTMENT_7_8_9; - config->sample_rate = USART_SAMPLE_RATE_16X_ARITHMETIC; -#endif -#ifdef FEATURE_USART_LIN_SLAVE - config->lin_slave_enable = false; -#endif - -#ifdef FEATURE_USART_LIN_MASTER - config->lin_node = LIN_INVALID_MODE; - config->lin_header_delay = LIN_MASTER_HEADER_DELAY_0; - config->lin_break_length = LIN_MASTER_BREAK_LENGTH_13_BIT; -#endif - -#ifdef FEATURE_USART_IMMEDIATE_BUFFER_OVERFLOW_NOTIFICATION - config->immediate_buffer_overflow_notification = false; -#endif -#ifdef FEATURE_USART_START_FRAME_DECTION - config->start_frame_detection_enable = false; -#endif -#ifdef FEATURE_USART_IRDA - config->encoding_format_enable = false; - config->receive_pulse_length = 19; -#endif -#ifdef FEATURE_USART_ISO7816 - config->iso7816_config.enabled = false; - config->iso7816_config.guard_time = ISO7816_GUARD_TIME_2_BIT; - config->iso7816_config.protocol_t = ISO7816_PROTOCOL_T_0; - config->iso7816_config.enable_inverse = false; - config->iso7816_config.inhibit_nack = ISO7816_INHIBIT_NACK_DISABLE; - config->iso7816_config.successive_recv_nack = ISO7816_SUCCESSIVE_RECV_NACK_DISABLE; - config->iso7816_config.max_iterations = 7; -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - config->collision_detection_enable = false; -#endif -#ifdef FEATURE_USART_RS485 - config->rs485_guard_time = RS485_GUARD_TIME_0_BIT; -#endif -} - -enum status_code usart_init( - struct usart_module *const module, - Sercom *const hw, - const struct usart_config *const config); - -/** - * \brief Enable the module - * - * Enables the USART module. - * - * \param[in] module Pointer to USART software instance struct - */ -static inline void usart_enable( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - -#if USART_CALLBACK_MODE == true - /* Enable Global interrupt for module */ - system_interrupt_enable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Enable USART module */ - usart_hw->CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; -} - -/** - * \brief Disable module - * - * Disables the USART module. - * - * \param[in] module Pointer to USART software instance struct - */ -static inline void usart_disable( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - -#if USART_CALLBACK_MODE == true - /* Disable Global interrupt for module */ - system_interrupt_disable(_sercom_get_interrupt_vector(module->hw)); -#endif - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Disable USART module */ - usart_hw->CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; -} - -/** - * \brief Resets the USART module - * - * Disables and resets the USART module. - * - * \param[in] module Pointer to the USART software instance struct - */ -static inline void usart_reset( - const struct usart_module *const module) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - usart_disable(module); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - /* Reset module */ - usart_hw->CTRLA.reg = SERCOM_USART_CTRLA_SWRST; -} - -/** - * \name Writing and Reading - * @{ - */ -enum status_code usart_write_wait( - struct usart_module *const module, - const uint16_t tx_data); - -enum status_code usart_read_wait( - struct usart_module *const module, - uint16_t *const rx_data); - -enum status_code usart_write_buffer_wait( - struct usart_module *const module, - const uint8_t *tx_data, - uint16_t length); - -enum status_code usart_read_buffer_wait( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); -/** @} */ - -/** - * \name Enabling/Disabling Receiver and Transmitter - * @{ - */ - -/** - * \brief Enable Transceiver - * - * Enable the given transceiver. Either RX or TX. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transceiver type - */ -static inline void usart_enable_transceiver( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - switch (transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Enable RX */ - usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - module->receiver_enabled = true; - break; - - case USART_TRANSCEIVER_TX: - /* Enable TX */ - usart_hw->CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - module->transmitter_enabled = true; - break; - } - _usart_wait_for_sync(module); -} - -/** - * \brief Disable Transceiver - * - * Disable the given transceiver (RX or TX). - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transceiver type - */ -static inline void usart_disable_transceiver( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - /* Wait until synchronization is complete */ - _usart_wait_for_sync(module); - - switch (transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Disable RX */ - usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - module->receiver_enabled = false; - break; - - case USART_TRANSCEIVER_TX: - /* Disable TX */ - usart_hw->CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - module->transmitter_enabled = false; - break; - } -} - -/** @} */ - -#ifdef FEATURE_USART_LIN_MASTER -/** - * \name LIN Master Command and Status - * @{ - */ - -/** - * \brief Sending LIN command. - * - * Sending LIN command. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] cmd Cammand type - */ -static inline void lin_master_send_cmd( - struct usart_module *const module, - enum lin_master_cmd cmd) -{ - SercomUsart *const usart_hw = &(module->hw->USART); - _usart_wait_for_sync(module); - usart_hw->CTRLB.reg |= cmd; -} - -/** - * \brief Get LIN transmission status - * - * Get LIN transmission status. - * - * \param[in] module Pointer to USART software instance struct - * - * \return Status of LIN master transmission. - * \retval true Data transmission completed - * \retval false Transmission is ongoing - */ -static inline bool lin_master_transmission_status(struct usart_module *const module) -{ - SercomUsart *const usart_hw = &(module->hw->USART); - return ((usart_hw->STATUS.reg & SERCOM_USART_STATUS_TXE)? true:false); -} - -/** @} */ -#endif - -#ifdef __cplusplus -} -#endif - -/** @} */ - -/** -* \page asfdoc_sam0_sercom_usart_extra Extra Information for SERCOM USART Driver -* -* \section asfdoc_sam0_sercom_usart_extra_acronyms Acronyms -* -* Below is a table listing the acronyms used in this module, along with their -* intended meanings. -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -* -*
AcronymDescription
SERCOMSerial Communication Interface
USARTUniversal Synchronous and Asynchronous Serial Receiver and Transmitter
LSBLeast Significant Bit
MSBMost Significant Bit
DMADirect Memory Access
-* -* -* \section asfdoc_sam0_sercom_usart_extra_dependencies Dependencies -* This driver has the following dependencies: -* -* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" -* - \ref asfdoc_sam0_system_clock_group "System clock configuration" -* -* -* \section asfdoc_sam0_sercom_usart_extra_errata Errata -* There are no errata related to this driver. -* -* -* \section asfdoc_sam0_sercom_usart_extra_history Module History -* An overview of the module history is presented in the table below, with -* details on the enhancements and fixes made to the module since its first -* release. The current version of this corresponds to the newest version in -* the table. -* - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added new feature as below: - * \li ISO7816 - *
Added new features as below: - * \li LIN master - * \li RS485 - *
Added new features as below: - * \li Oversample - * \li Buffer overflow notification - * \li Irda - * \li Lin slave - * \li Start frame detection - * \li Hardware flow control - * \li Collision detection - * \li DMA support
\li Added new \c transmitter_enable and \c receiver_enable Boolean - * values to \c struct usart_config - * \li Altered \c usart_write_* and usart_read_* functions to abort with - * an error code if the relevant transceiver is not enabled - * \li Fixed \c usart_write_buffer_wait() and \c usart_read_buffer_wait() - * not aborting correctly when a timeout condition occurs
Initial Release
-*/ - -/** - * \page asfdoc_sam0_sercom_usart_exqsg Examples for SERCOM USART Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_sercom_usart_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_sercom_usart_basic_use_case - * \if USART_CALLBACK_MODE - * - \subpage asfdoc_sam0_sercom_usart_callback_use_case - * \endif - * - \subpage asfdoc_sam0_sercom_usart_dma_use_case - * - \subpage asfdoc_sam0_sercom_usart_lin_use_case - */ - -/** - * \page asfdoc_sam0_sercom_usart_mux_settings SERCOM USART MUX Settings - * - * The following lists the possible internal SERCOM module pad function - * assignments, for the four SERCOM pads when in USART mode. Note that this is - * in addition to the physical GPIO pin MUX of the device, and can be used in - * conjunction to optimize the serial data pin-out. - * - * When TX and RX are connected to the same pin, the USART will operate in - * half-duplex mode if both one transmitter and several receivers are enabled. - * - * \note When RX and XCK are connected to the same pin, the receiver must not - * be enabled if the USART is configured to use an external clock. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
MUX/PadPAD 0PAD 1PAD 2PAD 3
RX_0_TX_0_XCK_1TX / RXXCK--
RX_0_TX_2_XCK_3RX-TXXCK
RX_1_TX_0_XCK_1TXRX / XCK--
RX_1_TX_2_XCK_3-RXTXXCK
RX_2_TX_0_XCK_1TXXCKRX-
RX_2_TX_2_XCK_3--TX / RXXCK
RX_3_TX_0_XCK_1TXXCK-RX
RX_3_TX_2_XCK_3--TXRX / XCK
- * - * \page asfdoc_sam0_sercom_usart_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42118F12/2015Added support for SAM L21/L22, SAM DA1, SAM D09, SAMR30 and SAM C20/C21
42118E12/2014Added support for SAM R21 and SAM D10/D11
42118D01/2014Added support for SAM D21
42118C10/2013Replaced the pad multiplexing documentation with a condensed table
42118B06/2013Corrected documentation typos
42118A06/2013Initial release
- */ -#endif /* USART_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/sercom/usart/usart_interrupt.c b/atmel-samd/asf/sam0/drivers/sercom/usart/usart_interrupt.c deleted file mode 100644 index cc042894c8e53..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/usart/usart_interrupt.c +++ /dev/null @@ -1,666 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM USART Asynchronous Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "usart_interrupt.h" - -/** - * \internal - * Asynchronous write of a buffer with a given length - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Pointer to data to be transmitted - * \param[in] length Length of data buffer - * - */ -enum status_code _usart_write_buffer( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(tx_data); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - system_interrupt_enter_critical_section(); - - /* Check if the USART transmitter is busy */ - if (module->remaining_tx_buffer_length > 0) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Write parameters to the device instance */ - module->remaining_tx_buffer_length = length; - - system_interrupt_leave_critical_section(); - - module->tx_buffer_ptr = tx_data; - module->tx_status = STATUS_BUSY; - - /* Enable the Data Register Empty Interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_DRE; - - return STATUS_OK; -} - -/** - * \internal - * Asynchronous read of a buffer with a given length - * - * \param[in] module Pointer to USART software instance struct - * \param[in] rx_data Pointer to data to be received - * \param[in] length Length of data buffer - * - */ -enum status_code _usart_read_buffer( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - Assert(rx_data); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - system_interrupt_enter_critical_section(); - - /* Check if the USART receiver is busy */ - if (module->remaining_rx_buffer_length > 0) { - system_interrupt_leave_critical_section(); - return STATUS_BUSY; - } - - /* Set length for the buffer and the pointer, and let - * the interrupt handler do the rest */ - module->remaining_rx_buffer_length = length; - - system_interrupt_leave_critical_section(); - - module->rx_buffer_ptr = rx_data; - module->rx_status = STATUS_BUSY; - - /* Enable the RX Complete Interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXC; - -#ifdef FEATURE_USART_LIN_SLAVE - /* Enable the break character is received Interrupt */ - if(module->lin_slave_enabled) { - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXBRK; - } -#endif - -#ifdef FEATURE_USART_START_FRAME_DECTION - /* Enable a start condition is detected Interrupt */ - if(module->start_frame_detection_enabled) { - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_RXS; - } -#endif - - return STATUS_OK; -} - -/** - * \brief Registers a callback - * - * Registers a callback function, which is implemented by the user. - * - * \note The callback must be enabled by \ref usart_enable_callback - * in order for the interrupt handler to call it when the conditions for - * the callback type are met. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - * - */ -void usart_register_callback( - struct usart_module *const module, - usart_callback_t callback_func, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); - - /* Register callback function */ - module->callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module->callback_reg_mask |= (1 << callback_type); -} - -/** - * \brief Unregisters a callback - * - * Unregisters a callback function, which is implemented by the user. - * - * \param[in,out] module Pointer to USART software instance struct - * \param[in] callback_type Callback type given by an enum - * - */ -void usart_unregister_callback( - struct usart_module *const module, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Unregister callback function */ - module->callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module->callback_reg_mask &= ~(1 << callback_type); -} - -/** - * \brief Asynchronous write a single char - * - * Sets up the driver to write the data given. If registered and enabled, - * a callback function will be called when the transmit is completed. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Data to transfer - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_BUSY If operation was not completed, due to the - * USART module being busy - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_job( - struct usart_module *const module, - const uint16_t *tx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(tx_data); - - - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Call internal write buffer function with length 1 */ - return _usart_write_buffer(module, (uint8_t *)tx_data, 1); -} - -/** - * \brief Asynchronous read a single char - * - * Sets up the driver to read data from the USART module to the data - * pointer given. If registered and enabled, a callback will be called - * when the receiving is completed. - * - * \param[in] module Pointer to USART software instance struct - * \param[out] rx_data Pointer to where received data should be put - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_BUSY If operation was not completed - */ -enum status_code usart_read_job( - struct usart_module *const module, - uint16_t *const rx_data) -{ - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); - - /* Call internal read buffer function with length 1 */ - return _usart_read_buffer(module, (uint8_t *)rx_data, 1); -} - -/** - * \brief Asynchronous buffer write - * - * Sets up the driver to write a given buffer over the USART. If registered and - * enabled, a callback function will be called. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] tx_data Pointer do data buffer to transmit - * \param[in] length Length of the data to transmit - * - * \note If using 9-bit data, the array that *tx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define TX_LEN 3 - uint16_t tx_buf[TX_LEN] = {0x0111, 0x0022, 0x0133}; - usart_write_buffer_job(&module, (uint8_t*)tx_buf, TX_LEN); - \endcode - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed successfully. - * \retval STATUS_BUSY If operation was not completed, due to the - * USART module being busy - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid - * arguments - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_write_buffer_job( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(tx_data); - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the transmitter is enabled */ - if (!(module->transmitter_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Issue internal asynchronous write */ - return _usart_write_buffer(module, tx_data, length); -} - -/** - * \brief Asynchronous buffer read - * - * Sets up the driver to read from the USART to a given buffer. If registered - * and enabled, a callback function will be called. - * - * \param[in] module Pointer to USART software instance struct - * \param[out] rx_data Pointer to data buffer to receive - * \param[in] length Data buffer length - * - * \note If using 9-bit data, the array that *rx_data point to should be defined - * as uint16_t array and should be casted to uint8_t* pointer. Because it - * is an address pointer, the highest byte is not discarded. For example: - * \code - #define RX_LEN 3 - uint16_t rx_buf[RX_LEN] = {0x0,}; - usart_read_buffer_job(&module, (uint8_t*)rx_buf, RX_LEN); - \endcode - * - * \returns Status of the operation. - * \retval STATUS_OK If operation was completed - * \retval STATUS_BUSY If operation was not completed, due to the - * USART module being busy - * \retval STATUS_ERR_INVALID_ARG If operation was not completed, due to invalid - * arguments - * \retval STATUS_ERR_DENIED If the transmitter is not enabled - */ -enum status_code usart_read_buffer_job( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length) -{ - /* Sanity check arguments */ - Assert(module); - Assert(rx_data); - - if (length == 0) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check that the receiver is enabled */ - if (!(module->receiver_enabled)) { - return STATUS_ERR_DENIED; - } - - /* Issue internal asynchronous read */ - return _usart_read_buffer(module, rx_data, length); -} - -/** - * \brief Cancels ongoing read/write operation - * - * Cancels the ongoing read/write operation modifying parameters in the - * USART software struct. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transfer type to cancel - */ -void usart_abort_job( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Get a pointer to the hardware module instance */ - SercomUsart *const usart_hw = &(module->hw->USART); - - switch(transceiver_type) { - case USART_TRANSCEIVER_RX: - /* Clear the interrupt flag in order to prevent the receive - * complete callback to fire */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; - - /* Clear the software reception buffer */ - module->remaining_rx_buffer_length = 0; - - break; - - case USART_TRANSCEIVER_TX: - /* Clear the interrupt flag in order to prevent the receive - * complete callback to fire */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; - - /* Clear the software reception buffer */ - module->remaining_tx_buffer_length = 0; - - break; - } -} - -/** - * \brief Get status from the ongoing or last asynchronous transfer operation - * - * Returns the error from a given ongoing or last asynchronous transfer operation. - * Either from a read or write transfer. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] transceiver_type Transfer type to check - * - * \return Status of the given job. - * \retval STATUS_OK No error occurred during the last transfer - * \retval STATUS_BUSY A transfer is ongoing - * \retval STATUS_ERR_BAD_DATA The last operation was aborted due to a - * parity error. The transfer could be affected - * by external noise - * \retval STATUS_ERR_BAD_FORMAT The last operation was aborted due to a - * frame error - * \retval STATUS_ERR_OVERFLOW The last operation was aborted due to a - * buffer overflow - * \retval STATUS_ERR_INVALID_ARG An invalid transceiver enum given - */ -enum status_code usart_get_job_status( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Variable for status code */ - enum status_code status_code; - - switch(transceiver_type) { - case USART_TRANSCEIVER_RX: - status_code = module->rx_status; - break; - - case USART_TRANSCEIVER_TX: - status_code = module->tx_status; - break; - - default: - status_code = STATUS_ERR_INVALID_ARG; - break; - } - - return status_code; -} - -/** - * \internal - * Handles interrupts as they occur, and it will run callback functions - * which are registered and enabled. - * - * \param[in] instance ID of the SERCOM instance calling the interrupt - * handler. - */ -void _usart_interrupt_handler( - uint8_t instance) -{ - /* Temporary variables */ - uint16_t interrupt_status; - uint16_t callback_status; - uint8_t error_code; - - - /* Get device instance from the look-up table */ - struct usart_module *module - = (struct usart_module *)_sercom_instances[instance]; - - /* Pointer to the hardware module instance */ - SercomUsart *const usart_hw - = &(module->hw->USART); - - /* Wait for the synchronization to complete */ - _usart_wait_for_sync(module); - - /* Read and mask interrupt flag register */ - interrupt_status = usart_hw->INTFLAG.reg; - interrupt_status &= usart_hw->INTENSET.reg; - callback_status = module->callback_reg_mask & - module->callback_enable_mask; - - /* Check if a DATA READY interrupt has occurred, - * and if there is more to transfer */ - if (interrupt_status & SERCOM_USART_INTFLAG_DRE) { - if (module->remaining_tx_buffer_length) { - /* Write value will be at least 8-bits long */ - uint16_t data_to_send = *(module->tx_buffer_ptr); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; - - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - data_to_send |= (*(module->tx_buffer_ptr) << 8); - /* Increment 8-bit pointer */ - (module->tx_buffer_ptr)++; - } - /* Write the data to send */ - usart_hw->DATA.reg = (data_to_send & SERCOM_USART_DATA_MASK); - - if (--(module->remaining_tx_buffer_length) == 0) { - /* Disable the Data Register Empty Interrupt */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - /* Enable Transmission Complete interrupt */ - usart_hw->INTENSET.reg = SERCOM_USART_INTFLAG_TXC; - - } - } else { - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_DRE; - } - } - - /* Check if the Transmission Complete interrupt has occurred and - * that the transmit buffer is empty */ - if (interrupt_status & SERCOM_USART_INTFLAG_TXC) { - - /* Disable TX Complete Interrupt, and set STATUS_OK */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_TXC; - module->tx_status = STATUS_OK; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_BUFFER_TRANSMITTED)) { - (*(module->callback[USART_CALLBACK_BUFFER_TRANSMITTED]))(module); - } - } - - /* Check if the Receive Complete interrupt has occurred, and that - * there's more data to receive */ - if (interrupt_status & SERCOM_USART_INTFLAG_RXC) { - - if (module->remaining_rx_buffer_length) { - /* Read out the status code and mask away all but the 4 LSBs*/ - error_code = (uint8_t)(usart_hw->STATUS.reg & SERCOM_USART_STATUS_MASK); -#if !SAMD20 - /* CTS status should not be considered as an error */ - if(error_code & SERCOM_USART_STATUS_CTS) { - error_code &= ~SERCOM_USART_STATUS_CTS; - } -#endif -#ifdef FEATURE_USART_LIN_MASTER - /* TXE status should not be considered as an error */ - if(error_code & SERCOM_USART_STATUS_TXE) { - error_code &= ~SERCOM_USART_STATUS_TXE; - } -#endif - /* Check if an error has occurred during the receiving */ - if (error_code) { - /* Check which error occurred */ - if (error_code & SERCOM_USART_STATUS_FERR) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_BAD_FORMAT; - usart_hw->STATUS.reg = SERCOM_USART_STATUS_FERR; - } else if (error_code & SERCOM_USART_STATUS_BUFOVF) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_OVERFLOW; - usart_hw->STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - } else if (error_code & SERCOM_USART_STATUS_PERR) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_BAD_DATA; - usart_hw->STATUS.reg = SERCOM_USART_STATUS_PERR; - } -#ifdef FEATURE_USART_LIN_SLAVE - else if (error_code & SERCOM_USART_STATUS_ISF) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_PROTOCOL; - usart_hw->STATUS.reg = SERCOM_USART_STATUS_ISF; - } -#endif -#ifdef FEATURE_USART_COLLISION_DECTION - else if (error_code & SERCOM_USART_STATUS_COLL) { - /* Store the error code and clear flag by writing 1 to it */ - module->rx_status = STATUS_ERR_PACKET_COLLISION; - usart_hw->STATUS.reg = SERCOM_USART_STATUS_COLL; - } -#endif - - /* Run callback if registered and enabled */ - if (callback_status - & (1 << USART_CALLBACK_ERROR)) { - (*(module->callback[USART_CALLBACK_ERROR]))(module); - } - - } else { - - /* Read current packet from DATA register, - * increment buffer pointer and decrement buffer length */ - uint16_t received_data = (usart_hw->DATA.reg & SERCOM_USART_DATA_MASK); - - /* Read value will be at least 8-bits long */ - *(module->rx_buffer_ptr) = received_data; - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; - - if (module->character_size == USART_CHARACTER_SIZE_9BIT) { - /* 9-bit data, write next received byte to the buffer */ - *(module->rx_buffer_ptr) = (received_data >> 8); - /* Increment 8-bit pointer */ - module->rx_buffer_ptr += 1; - } - - /* Check if the last character have been received */ - if(--(module->remaining_rx_buffer_length) == 0) { - /* Disable RX Complete Interrupt, - * and set STATUS_OK */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - module->rx_status = STATUS_OK; - - /* Run callback if registered and enabled */ - if (callback_status - & (1 << USART_CALLBACK_BUFFER_RECEIVED)) { - (*(module->callback[USART_CALLBACK_BUFFER_RECEIVED]))(module); - } - } - } - } else { - /* This should not happen. Disable Receive Complete interrupt. */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTFLAG_RXC; - } - } - -#ifdef FEATURE_USART_HARDWARE_FLOW_CONTROL - if (interrupt_status & SERCOM_USART_INTFLAG_CTSIC) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_CTSIC; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_CTS_INPUT_CHANGE)) { - (*(module->callback[USART_CALLBACK_CTS_INPUT_CHANGE]))(module); - } - } -#endif - -#ifdef FEATURE_USART_LIN_SLAVE - if (interrupt_status & SERCOM_USART_INTFLAG_RXBRK) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXBRK; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_BREAK_RECEIVED)) { - (*(module->callback[USART_CALLBACK_BREAK_RECEIVED]))(module); - } - } -#endif - -#ifdef FEATURE_USART_START_FRAME_DECTION - if (interrupt_status & SERCOM_USART_INTFLAG_RXS) { - /* Disable interrupts */ - usart_hw->INTENCLR.reg = SERCOM_USART_INTENCLR_RXS; - /* Clear interrupt flag */ - usart_hw->INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; - - /* Run callback if registered and enabled */ - if (callback_status & (1 << USART_CALLBACK_START_RECEIVED)) { - (*(module->callback[USART_CALLBACK_START_RECEIVED]))(module); - } - } -#endif -} - diff --git a/atmel-samd/asf/sam0/drivers/sercom/usart/usart_interrupt.h b/atmel-samd/asf/sam0/drivers/sercom/usart/usart_interrupt.h deleted file mode 100644 index 26595d0a09621..0000000000000 --- a/atmel-samd/asf/sam0/drivers/sercom/usart/usart_interrupt.h +++ /dev/null @@ -1,177 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM USART Asynchronous Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef USART_INTERRUPT_H_INCLUDED -#define USART_INTERRUPT_H_INCLUDED - -#include "usart.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__DOXYGEN__) -enum status_code _usart_write_buffer( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length); - -enum status_code _usart_read_buffer( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); - -void _usart_interrupt_handler( - uint8_t instance); -#endif - -/** - * \addtogroup asfdoc_sam0_sercom_usart_group - * - * @{ - */ - -/** - * \name Callback Management - * @{ - */ -void usart_register_callback( - struct usart_module *const module, - usart_callback_t callback_func, - enum usart_callback callback_type); - -void usart_unregister_callback( - struct usart_module *module, - enum usart_callback callback_type); - -/** - * \brief Enables callback - * - * Enables the callback function registered by the \ref usart_register_callback. - * The callback function will be called from the interrupt handler when the - * conditions for the callback type are met. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void usart_enable_callback( - struct usart_module *const module, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Enable callback */ - module->callback_enable_mask |= (1 << callback_type); - -} - -/** - * \brief Disable callback - * - * Disables the callback function registered by the \ref usart_register_callback, - * and the callback will not be called from the interrupt routine. - * - * \param[in] module Pointer to USART software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void usart_disable_callback( - struct usart_module *const module, - enum usart_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Disable callback */ - module->callback_enable_mask &= ~(1 << callback_type); -} - -/** - * @} - */ - -/** - * \name Writing and Reading - * @{ - */ -enum status_code usart_write_job( - struct usart_module *const module, - const uint16_t *tx_data); - -enum status_code usart_read_job( - struct usart_module *const module, - uint16_t *const rx_data); - -enum status_code usart_write_buffer_job( - struct usart_module *const module, - uint8_t *tx_data, - uint16_t length); - -enum status_code usart_read_buffer_job( - struct usart_module *const module, - uint8_t *rx_data, - uint16_t length); - -void usart_abort_job( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type); - -enum status_code usart_get_job_status( - struct usart_module *const module, - enum usart_transceiver_type transceiver_type); -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* USART_INTERRUPT_H_INCLUDED */ - diff --git a/atmel-samd/asf/sam0/drivers/system/clock/clock.h b/atmel-samd/asf/sam0/drivers/system/clock/clock.h deleted file mode 100644 index 0d350428d50ab..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/clock/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * \file - * - * \brief SAM Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_H_INCLUDED -#define SYSTEM_CLOCK_H_INCLUDED - -#include -#include -#include - -#endif /* SYSTEM_CLOCK_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock.c b/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock.c deleted file mode 100644 index 777ac5b9b9686..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock.c +++ /dev/null @@ -1,1041 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Clock Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include -#include - -#ifndef SYSCTRL_FUSES_OSC32K_ADDR -#if (SAMR21) || (SAMD) -# define SYSCTRL_FUSES_OSC32K_ADDR FUSES_OSC32K_CAL_ADDR -# define SYSCTRL_FUSES_OSC32K_Pos FUSES_OSC32K_CAL_Pos -#elif (SAML21) -# define SYSCTRL_FUSES_OSC32K_ADDR NVMCTRL_OTP4 -# define SYSCTRL_FUSES_OSC32K_Pos 6 - -#else -# define SYSCTRL_FUSES_OSC32K_ADDR SYSCTRL_FUSES_OSC32K_CAL_ADDR -# define SYSCTRL_FUSES_OSC32K_Pos SYSCTRL_FUSES_OSC32K_CAL_Pos -#endif -#endif - -/** - * \internal - * \brief DFLL-specific data container. - */ -struct _system_clock_dfll_config { - uint32_t control; - uint32_t val; - uint32_t mul; -}; - -/** - * \internal - * \brief DPLL-specific data container. - */ -struct _system_clock_dpll_config { - uint32_t frequency; -}; - - -/** - * \internal - * \brief XOSC-specific data container. - */ -struct _system_clock_xosc_config { - uint32_t frequency; -}; - -/** - * \internal - * \brief System clock module data container. - */ -struct _system_clock_module { - volatile struct _system_clock_dfll_config dfll; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - volatile struct _system_clock_dpll_config dpll; -#endif - - volatile struct _system_clock_xosc_config xosc; - volatile struct _system_clock_xosc_config xosc32k; -}; - -/** - * \internal - * \brief Internal module instance to cache configuration values. - */ -static struct _system_clock_module _system_clock_inst = { - .dfll = { - .control = 0, - .val = 0, - .mul = 0, - }, - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - .dpll = { - .frequency = 0, - }, -#endif - .xosc = { - .frequency = 0, - }, - .xosc32k = { - .frequency = 0, - }, - }; - -/** - * \internal - * \brief Wait for sync to the DFLL control registers. - */ -static inline void _system_dfll_wait_for_sync(void) -{ - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY)) { - /* Wait for DFLL sync */ - } -} - -/** - * \internal - * \brief Wait for sync to the OSC32K control registers. - */ -static inline void _system_osc32k_wait_for_sync(void) -{ - while (!(SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY)) { - /* Wait for OSC32K sync */ - } -} - -static inline void _system_clock_source_dfll_set_config_errata_9905(void) -{ - - /* Disable ONDEMAND mode while writing configurations */ - SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_ENABLE; - _system_dfll_wait_for_sync(); - - SYSCTRL->DFLLMUL.reg = _system_clock_inst.dfll.mul; - SYSCTRL->DFLLVAL.reg = _system_clock_inst.dfll.val; - - /* Write full configuration to DFLL control register */ - SYSCTRL->DFLLCTRL.reg = 0; - _system_dfll_wait_for_sync(); - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; -} - -/** - * \brief Retrieve the frequency of a clock source. - * - * Determines the current operating frequency of a given clock source. - * - * \param[in] clock_source Clock source to get the frequency - * - * \returns Frequency of the given clock source, in Hz. - */ -uint32_t system_clock_source_get_hz( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_XOSC: - return _system_clock_inst.xosc.frequency; - - case SYSTEM_CLOCK_SOURCE_OSC8M: - return 8000000UL >> SYSCTRL->OSC8M.bit.PRESC; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - return 32768UL; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - return _system_clock_inst.xosc32k.frequency; - - case SYSTEM_CLOCK_SOURCE_DFLL: - - /* Check if the DFLL has been configured */ - if (!(_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_ENABLE)) - return 0; - - /* Make sure that the DFLL module is ready */ - _system_dfll_wait_for_sync(); - - /* Check if operating in closed loop mode */ - if ((_system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_MODE) && - !( _system_clock_inst.dfll.control & SYSCTRL_DFLLCTRL_USBCRM )) { - return system_gclk_chan_get_hz(SYSCTRL_GCLK_ID_DFLL48) * - (_system_clock_inst.dfll.mul & 0xffff); - } - - return 48000000UL; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - if (!(SYSCTRL->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE)) { - return 0; - } - - return _system_clock_inst.dpll.frequency; -#endif - - default: - return 0; - } -} - -/** - * \brief Configure the internal OSC8M oscillator clock source. - * - * Configures the 8MHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \param[in] config OSC8M configuration structure containing the new config - */ -void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config) -{ - SYSCTRL_OSC8M_Type temp = SYSCTRL->OSC8M; - - /* Use temporary struct to reduce register access */ - temp.bit.PRESC = config->prescaler; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - SYSCTRL->OSC8M = temp; -} - -/** - * \brief Configure the internal OSC32K oscillator clock source. - * - * Configures the 32KHz (nominal) internal RC oscillator with the given - * configuration settings. - * - * \param[in] config OSC32K configuration structure containing the new config - */ -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config) -{ - SYSCTRL_OSC32K_Type temp = SYSCTRL->OSC32K; - - /* Update settings via a temporary struct to reduce register access */ - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - temp.bit.STARTUP = config->startup_time; - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - SYSCTRL->OSC32K = temp; -} - -/** - * \brief Configure the external oscillator clock source. - * - * Configures the external oscillator clock source with the given configuration - * settings. - * - * \param[in] config External oscillator configuration structure containing - * the new config - */ -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config) -{ - SYSCTRL_XOSC_Type temp = SYSCTRL->XOSC; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.AMPGC = config->auto_gain_control; - - /* Set gain if automatic gain control is not selected */ - if (!config->auto_gain_control) { - if (config->frequency <= 2000000) { - temp.bit.GAIN = 0; - } else if (config->frequency <= 4000000) { - temp.bit.GAIN = 1; - } else if (config->frequency <= 8000000) { - temp.bit.GAIN = 2; - } else if (config->frequency <= 16000000) { - temp.bit.GAIN = 3; - } else if (config->frequency <= 32000000) { - temp.bit.GAIN = 4; - } - - } - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - - /* Store XOSC frequency for internal use */ - _system_clock_inst.xosc.frequency = config->frequency; - - SYSCTRL->XOSC = temp; -} - -/** - * \brief Configure the XOSC32K external 32KHz oscillator clock source. - * - * Configures the external 32KHz oscillator clock source with the given - * configuration settings. - * - * \param[in] config XOSC32K configuration structure containing the new config - */ -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config) -{ - SYSCTRL_XOSC32K_Type temp = SYSCTRL->XOSC32K; - - temp.bit.STARTUP = config->startup_time; - - if (config->external_clock == SYSTEM_CLOCK_EXTERNAL_CRYSTAL) { - temp.bit.XTALEN = 1; - } else { - temp.bit.XTALEN = 0; - } - - temp.bit.AAMPEN = config->auto_gain_control; - temp.bit.EN1K = config->enable_1khz_output; - temp.bit.EN32K = config->enable_32khz_output; - - temp.bit.ONDEMAND = config->on_demand; - temp.bit.RUNSTDBY = config->run_in_standby; - temp.bit.WRTLOCK = config->write_once; - - /* Cache the new frequency in case the user needs to check the current - * operating frequency later */ - _system_clock_inst.xosc32k.frequency = config->frequency; - - SYSCTRL->XOSC32K = temp; -} - -/** - * \brief Configure the DFLL clock source. - * - * Configures the Digital Frequency Locked Loop clock source with the given - * configuration settings. - * - * \note The DFLL will be running when this function returns, as the DFLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DFLL configuration structure containing the new config - */ -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config) -{ - _system_clock_inst.dfll.val = - SYSCTRL_DFLLVAL_COARSE(config->coarse_value) | - SYSCTRL_DFLLVAL_FINE(config->fine_value); - - _system_clock_inst.dfll.control = - (uint32_t)config->wakeup_lock | - (uint32_t)config->stable_tracking | - (uint32_t)config->quick_lock | - (uint32_t)config->chill_cycle | - ((uint32_t)config->on_demand << SYSCTRL_DFLLCTRL_ONDEMAND_Pos); - - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | - SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the closed loop mode */ - _system_clock_inst.dfll.control |= config->loop_mode; - } - if (config->loop_mode == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - - _system_clock_inst.dfll.mul = - SYSCTRL_DFLLMUL_CSTEP(config->coarse_max_step) | - SYSCTRL_DFLLMUL_FSTEP(config->fine_max_step) | - SYSCTRL_DFLLMUL_MUL(config->multiply_factor); - - /* Enable the USB recovery mode */ - _system_clock_inst.dfll.control |= config->loop_mode | - SYSCTRL_DFLLCTRL_MODE | SYSCTRL_DFLLCTRL_BPLCKC; - } -} - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL -/** - * \brief Configure the DPLL clock source. - * - * Configures the Digital Phase-Locked Loop clock source with the given - * configuration settings. - * - * \note The DPLL will be running when this function returns, as the DPLL module - * needs to be enabled in order to perform the module configuration. - * - * \param[in] config DPLL configuration structure containing the new config - */ -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config) -{ - - uint32_t tmpldr; - uint8_t tmpldrfrac; - uint32_t refclk; - - refclk = config->reference_frequency; - - /* Only reference clock REF1 can be divided */ - if (config->reference_clock == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - refclk = refclk / (2 * (config->reference_divider + 1)); - } - - /* Calculate LDRFRAC and LDR */ - tmpldr = (config->output_frequency << 4) / refclk; - tmpldrfrac = tmpldr & 0x0f; - tmpldr = (tmpldr >> 4) - 1; - - SYSCTRL->DPLLCTRLA.reg = - ((uint32_t)config->on_demand << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos) | - ((uint32_t)config->run_in_standby << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos); - - SYSCTRL->DPLLRATIO.reg = - SYSCTRL_DPLLRATIO_LDRFRAC(tmpldrfrac) | - SYSCTRL_DPLLRATIO_LDR(tmpldr); - - SYSCTRL->DPLLCTRLB.reg = - SYSCTRL_DPLLCTRLB_DIV(config->reference_divider) | - ((uint32_t)config->lock_bypass << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) | - SYSCTRL_DPLLCTRLB_LTIME(config->lock_time) | - SYSCTRL_DPLLCTRLB_REFCLK(config->reference_clock) | - ((uint32_t)config->wake_up_fast << SYSCTRL_DPLLCTRLB_WUF_Pos) | - ((uint32_t)config->low_power_enable << SYSCTRL_DPLLCTRLB_LPEN_Pos) | - SYSCTRL_DPLLCTRLB_FILTER(config->filter); - - /* - * Fck = Fckrx * (LDR + 1 + LDRFRAC / 16) - */ - _system_clock_inst.dpll.frequency = - (refclk * (((tmpldr + 1) << 4) + tmpldrfrac)) >> 4; -} -#endif - -/** - * \brief Writes the calibration values for a given oscillator clock source. - * - * Writes an oscillator calibration value to the given oscillator control - * registers. The acceptable ranges are: - * - * For OSC32K: - * - 7 bits (max value 128) - * For OSC8MHZ: - * - 8 bits (Max value 255) - * For OSCULP: - * - 5 bits (Max value 32) - * - * \note The frequency range parameter applies only when configuring the 8MHz - * oscillator and will be ignored for the other oscillators. - * - * \param[in] clock_source Clock source to calibrate - * \param[in] calibration_value Calibration value to write - * \param[in] freq_range Frequency range (8MHz oscillator only) - * - * \retval STATUS_OK The calibration value was written - * successfully. - * \retval STATUS_ERR_INVALID_ARG The setting is not valid for selected clock - * source. - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source clock_source, - const uint16_t calibration_value, - const uint8_t freq_range) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - - if (calibration_value > 0xfff || freq_range > 4) { - return STATUS_ERR_INVALID_ARG; - } - - SYSCTRL->OSC8M.bit.CALIB = calibration_value; - SYSCTRL->OSC8M.bit.FRANGE = freq_range; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - - if (calibration_value > 128) { - return STATUS_ERR_INVALID_ARG; - } - - _system_osc32k_wait_for_sync(); - SYSCTRL->OSC32K.bit.CALIB = calibration_value; - break; - - case SYSTEM_CLOCK_SOURCE_ULP32K: - - if (calibration_value > 32) { - return STATUS_ERR_INVALID_ARG; - } - - SYSCTRL->OSCULP32K.bit.CALIB = calibration_value; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - break; - } - - return STATUS_OK; -} - -/** - * \brief Enables a clock source. - * - * Enables a clock source which has been previously configured. - * - * \param[in] clock_source Clock source to enable - * - * \retval STATUS_OK Clock source was enabled successfully and - * is ready - * \retval STATUS_ERR_INVALID_ARG The clock source is not available on this - * device - */ -enum status_code system_clock_source_enable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; - return STATUS_OK; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg |= SYSCTRL_XOSC_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control |= SYSCTRL_DFLLCTRL_ENABLE; - _system_clock_source_dfll_set_config_errata_9905(); - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; - break; -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Always enabled */ - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Disables a clock source. - * - * Disables a clock source that was previously enabled. - * - * \param[in] clock_source Clock source to disable - * - * \retval STATUS_OK Clock source was disabled successfully - * \retval STATUS_ERR_INVALID_ARG An invalid or unavailable clock source was - * given - */ -enum status_code system_clock_source_disable( - const enum system_clock_source clock_source) -{ - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - SYSCTRL->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - SYSCTRL->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - SYSCTRL->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - SYSCTRL->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - _system_clock_inst.dfll.control &= ~SYSCTRL_DFLLCTRL_ENABLE; - SYSCTRL->DFLLCTRL.reg = _system_clock_inst.dfll.control; - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - SYSCTRL->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; - break; -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; -} - -/** - * \brief Checks if a clock source is ready. - * - * Checks if a given clock source is ready to be used. - * - * \param[in] clock_source Clock source to check if ready - * - * \returns Ready state of the given clock source. - * - * \retval true Clock source is enabled and ready - * \retval false Clock source is disabled or not yet ready - */ -bool system_clock_source_is_ready( - const enum system_clock_source clock_source) -{ - uint32_t mask = 0; - - switch (clock_source) { - case SYSTEM_CLOCK_SOURCE_OSC8M: - mask = SYSCTRL_PCLKSR_OSC8MRDY; - break; - - case SYSTEM_CLOCK_SOURCE_OSC32K: - mask = SYSCTRL_PCLKSR_OSC32KRDY; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC: - mask = SYSCTRL_PCLKSR_XOSCRDY; - break; - - case SYSTEM_CLOCK_SOURCE_XOSC32K: - mask = SYSCTRL_PCLKSR_XOSC32KRDY; - break; - - case SYSTEM_CLOCK_SOURCE_DFLL: - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - mask = (SYSCTRL_PCLKSR_DFLLRDY | - SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC); - } else { - mask = SYSCTRL_PCLKSR_DFLLRDY; - } - break; - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - case SYSTEM_CLOCK_SOURCE_DPLL: - return ((SYSCTRL->DPLLSTATUS.reg & - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)) == - (SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK)); -#endif - - case SYSTEM_CLOCK_SOURCE_ULP32K: - /* Not possible to disable */ - return true; - - default: - return false; - } - - return ((SYSCTRL->PCLKSR.reg & mask) == mask); -} - -/* Include some checks for conf_clocks.h validation */ -#include "clock_config_check.h" - -#if !defined(__DOXYGEN__) -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h. - */ -# define _CONF_CLOCK_GCLK_CONFIG(n, unused) \ - if (CONF_CLOCK_GCLK_##n##_ENABLE == true) { \ - struct system_gclk_gen_config gclk_conf; \ - system_gclk_gen_get_config_defaults(&gclk_conf); \ - gclk_conf.source_clock = CONF_CLOCK_GCLK_##n##_CLOCK_SOURCE; \ - gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \ - gclk_conf.run_in_standby = CONF_CLOCK_GCLK_##n##_RUN_IN_STANDBY; \ - gclk_conf.output_enable = CONF_CLOCK_GCLK_##n##_OUTPUT_ENABLE; \ - system_gclk_gen_set_config(GCLK_GENERATOR_##n, &gclk_conf); \ - system_gclk_gen_enable(GCLK_GENERATOR_##n); \ - } - -/** \internal - * - * Configures a Generic Clock Generator with the configuration from \c conf_clocks.h, - * provided that it is not the main Generic Clock Generator channel. - */ -# define _CONF_CLOCK_GCLK_CONFIG_NONMAIN(n, unused) \ - if (n > 0) { _CONF_CLOCK_GCLK_CONFIG(n, unused); } -#endif - -/** \internal - * - * Switch all peripheral clock to a not enabled general clock - * to save power. - */ -static void _switch_peripheral_gclk(void) -{ - uint32_t gclk_id; - struct system_gclk_chan_config gclk_conf; - -#if CONF_CLOCK_GCLK_1_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_1; -#elif CONF_CLOCK_GCLK_2_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_2; -#elif CONF_CLOCK_GCLK_3_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_3; -#elif CONF_CLOCK_GCLK_4_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_4; -#elif CONF_CLOCK_GCLK_5_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_5; -#elif CONF_CLOCK_GCLK_6_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_6; -#elif CONF_CLOCK_GCLK_7_ENABLE == false - gclk_conf.source_generator = GCLK_GENERATOR_7; -#else - gclk_conf.source_generator = GCLK_GENERATOR_7; -#endif - - for (gclk_id = 0; gclk_id < GCLK_NUM; gclk_id++) { - system_gclk_chan_set_config(gclk_id, &gclk_conf); - } -} - -/** - * \brief Initialize clock system based on the configuration in conf_clocks.h. - * - * This function will apply the settings in conf_clocks.h when run from the user - * application. All clock sources and GCLK generators are running when this function - * returns. - * - * \note OSC8M is always enabled and if user selects other clocks for GCLK generators, - * the OSC8M default enable can be disabled after system_clock_init. Make sure the - * clock switch successfully before disabling OSC8M. - */ -// Added dfll_fine_calibration as a parameter so that the user program can save -// and restore it. -void system_clock_init(uint16_t dfll_fine_calibration) -{ - /* Various bits in the INTFLAG register can be set to one at startup. - This will ensure that these bits are cleared */ - SYSCTRL->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY | SYSCTRL_INTFLAG_BOD33DET | - SYSCTRL_INTFLAG_DFLLRDY; - - system_flash_set_waitstates(CONF_CLOCK_FLASH_WAIT_STATES); - - /* Switch all peripheral clock to a not enabled general clock to save power. */ - _switch_peripheral_gclk(); - - /* XOSC */ -#if CONF_CLOCK_XOSC_ENABLE == true - struct system_clock_source_xosc_config xosc_conf; - system_clock_source_xosc_get_config_defaults(&xosc_conf); - - xosc_conf.external_clock = CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL; - xosc_conf.startup_time = CONF_CLOCK_XOSC_STARTUP_TIME; - xosc_conf.auto_gain_control = CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL; - xosc_conf.frequency = CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY; - xosc_conf.on_demand = CONF_CLOCK_XOSC_ON_DEMAND; - xosc_conf.run_in_standby = CONF_CLOCK_XOSC_RUN_IN_STANDBY; - - system_clock_source_xosc_set_config(&xosc_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC); -#endif - - - /* XOSC32K */ -#if CONF_CLOCK_XOSC32K_ENABLE == true - struct system_clock_source_xosc32k_config xosc32k_conf; - system_clock_source_xosc32k_get_config_defaults(&xosc32k_conf); - - xosc32k_conf.frequency = 32768UL; - xosc32k_conf.external_clock = CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL; - xosc32k_conf.startup_time = CONF_CLOCK_XOSC32K_STARTUP_TIME; - xosc32k_conf.auto_gain_control = CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL; - xosc32k_conf.enable_1khz_output = CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT; - xosc32k_conf.enable_32khz_output = CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT; - xosc32k_conf.on_demand = false; - xosc32k_conf.run_in_standby = CONF_CLOCK_XOSC32K_RUN_IN_STANDBY; - - system_clock_source_xosc32k_set_config(&xosc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_XOSC32K)); - if (CONF_CLOCK_XOSC32K_ON_DEMAND) { - SYSCTRL->XOSC32K.bit.ONDEMAND = 1; - } -#endif - - - /* OSCK32K */ -#if CONF_CLOCK_OSC32K_ENABLE == true - SYSCTRL->OSC32K.bit.CALIB = - ((*(uint32_t *)SYSCTRL_FUSES_OSC32K_ADDR >> - SYSCTRL_FUSES_OSC32K_Pos) & 0x7Ful); - - struct system_clock_source_osc32k_config osc32k_conf; - system_clock_source_osc32k_get_config_defaults(&osc32k_conf); - - osc32k_conf.startup_time = CONF_CLOCK_OSC32K_STARTUP_TIME; - osc32k_conf.enable_1khz_output = CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT; - osc32k_conf.enable_32khz_output = CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT; - osc32k_conf.on_demand = CONF_CLOCK_OSC32K_ON_DEMAND; - osc32k_conf.run_in_standby = CONF_CLOCK_OSC32K_RUN_IN_STANDBY; - - system_clock_source_osc32k_set_config(&osc32k_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC32K); -#endif - - - /* DFLL Config (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - struct system_clock_source_dfll_config dfll_conf; - system_clock_source_dfll_get_config_defaults(&dfll_conf); - - dfll_conf.loop_mode = CONF_CLOCK_DFLL_LOOP_MODE; - dfll_conf.on_demand = false; - - /* Using DFLL48M COARSE CAL value from NVM Software Calibration Area Mapping - in DFLL.COARSE helps to output a frequency close to 48 MHz.*/ -#define NVM_DFLL_COARSE_POS 58 /* DFLL48M Coarse calibration value bit position.*/ -#define NVM_DFLL_COARSE_SIZE 6 /* DFLL48M Coarse calibration value bit size.*/ - - uint32_t coarse =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_DFLL_COARSE_POS / 32)) - >> (NVM_DFLL_COARSE_POS % 32)) - & ((1 << NVM_DFLL_COARSE_SIZE) - 1); - /* In some revision chip, the coarse calibration value is not correct. */ - if (coarse == 0x3f) { - coarse = 0x1f; - } - dfll_conf.coarse_value = coarse; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN) { - dfll_conf.fine_value = CONF_CLOCK_DFLL_FINE_VALUE; - } - -# if CONF_CLOCK_DFLL_QUICK_LOCK == true - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; -# else - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE; -# endif - -# if CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK == true - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; -# else - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK; -# endif - -# if CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP == true - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; -# else - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE; -# endif - -# if CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE == true - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; -# else - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; -# endif - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - dfll_conf.multiply_factor = CONF_CLOCK_DFLL_MULTIPLY_FACTOR; - } - - dfll_conf.coarse_max_step = CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE; - dfll_conf.fine_max_step = CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE; - - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY) { - dfll_conf.fine_max_step = 10; - dfll_conf.fine_value = dfll_fine_calibration; - dfll_conf.quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - dfll_conf.stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; - dfll_conf.wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - dfll_conf.chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE; - - dfll_conf.multiply_factor = 48000; - } - - system_clock_source_dfll_set_config(&dfll_conf); -#endif - - - /* OSC8M */ - struct system_clock_source_osc8m_config osc8m_conf; - system_clock_source_osc8m_get_config_defaults(&osc8m_conf); - - osc8m_conf.prescaler = CONF_CLOCK_OSC8M_PRESCALER; - osc8m_conf.on_demand = CONF_CLOCK_OSC8M_ON_DEMAND; - osc8m_conf.run_in_standby = CONF_CLOCK_OSC8M_RUN_IN_STANDBY; - - system_clock_source_osc8m_set_config(&osc8m_conf); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_OSC8M); - - - /* GCLK */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - system_gclk_init(); - - /* Configure all GCLK generators except for the main generator, which - * is configured later after all other clock systems are set up */ - MREPEAT(GCLK_GEN_NUM, _CONF_CLOCK_GCLK_CONFIG_NONMAIN, ~); - -# if CONF_CLOCK_DFLL_ENABLE == true - /* Enable DFLL reference clock if in closed loop mode */ - if (CONF_CLOCK_DFLL_LOOP_MODE == SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED) { - struct system_gclk_chan_config dfll_gclk_chan_conf; - - system_gclk_chan_get_config_defaults(&dfll_gclk_chan_conf); - dfll_gclk_chan_conf.source_generator = CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_DFLL48, &dfll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_DFLL48); - } -# endif - -# if CONF_CLOCK_DPLL_ENABLE == true - /* Enable DPLL internal lock timer and reference clock */ - struct system_gclk_chan_config dpll_gclk_chan_conf; - system_gclk_chan_get_config_defaults(&dpll_gclk_chan_conf); - if (CONF_CLOCK_DPLL_LOCK_TIME != SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL32K, &dpll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL32K); - } - - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - dpll_gclk_chan_conf.source_generator = CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR; - system_gclk_chan_set_config(SYSCTRL_GCLK_ID_FDPLL, &dpll_gclk_chan_conf); - system_gclk_chan_enable(SYSCTRL_GCLK_ID_FDPLL); - } -# endif -#endif - - - /* DFLL Enable (Open and Closed Loop) */ -#if CONF_CLOCK_DFLL_ENABLE == true - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL)); - if (CONF_CLOCK_DFLL_ON_DEMAND) { - SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1; - } -#endif - - /* DPLL */ -#ifdef FEATURE_SYSTEM_CLOCK_DPLL -# if (CONF_CLOCK_DPLL_ENABLE == true) - - /* Enable DPLL reference clock */ - if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K) { - /* XOSC32K should have been enabled for DPLL_REF0 */ - Assert(CONF_CLOCK_XOSC32K_ENABLE); - } else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC) { - /* XOSC should have been enabled for DPLL_REF1 */ - Assert(CONF_CLOCK_XOSC_ENABLE); - } - else if (CONF_CLOCK_DPLL_REFERENCE_CLOCK == SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK) { - /* GCLK should have been enabled */ - Assert(CONF_CLOCK_CONFIGURE_GCLK); - } - else { - Assert(false); - } - - struct system_clock_source_dpll_config dpll_config; - system_clock_source_dpll_get_config_defaults(&dpll_config); - - dpll_config.on_demand = false; - dpll_config.run_in_standby = CONF_CLOCK_DPLL_RUN_IN_STANDBY; - dpll_config.lock_bypass = CONF_CLOCK_DPLL_LOCK_BYPASS; - dpll_config.wake_up_fast = CONF_CLOCK_DPLL_WAKE_UP_FAST; - dpll_config.low_power_enable = CONF_CLOCK_DPLL_LOW_POWER_ENABLE; - - dpll_config.filter = CONF_CLOCK_DPLL_FILTER; - dpll_config.lock_time = CONF_CLOCK_DPLL_LOCK_TIME; - - dpll_config.reference_clock = CONF_CLOCK_DPLL_REFERENCE_CLOCK; - dpll_config.reference_frequency = CONF_CLOCK_DPLL_REFERENCE_FREQUENCY; - dpll_config.reference_divider = CONF_CLOCK_DPLL_REFERENCE_DIVIDER; - dpll_config.output_frequency = CONF_CLOCK_DPLL_OUTPUT_FREQUENCY; - - system_clock_source_dpll_set_config(&dpll_config); - system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DPLL); - while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DPLL)); - if (CONF_CLOCK_DPLL_ON_DEMAND) { - SYSCTRL->DPLLCTRLA.bit.ONDEMAND = 1; - } - -# endif -#endif - - /* CPU and BUS clocks */ - system_cpu_clock_set_divider(CONF_CLOCK_CPU_DIVIDER); - - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBA, CONF_CLOCK_APBA_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBB, CONF_CLOCK_APBB_DIVIDER); - system_apb_clock_set_divider(SYSTEM_CLOCK_APB_APBC, CONF_CLOCK_APBC_DIVIDER); - - /* GCLK 0 */ -#if CONF_CLOCK_CONFIGURE_GCLK == true - /* Configure the main GCLK last as it might depend on other generators */ - _CONF_CLOCK_GCLK_CONFIG(0, ~); -#endif -} diff --git a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock_config_check.h b/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock_config_check.h deleted file mode 100644 index fd4757e2821b9..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock_config_check.h +++ /dev/null @@ -1,454 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CLOCK_CONFIG_CHECK_H -# define CLOCK_CONFIG_CHECK_H - -#if !defined(CONF_CLOCK_FLASH_WAIT_STATES) -# error CONF_CLOCK_FLASH_WAIT_STATES not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_CPU_DIVIDER) -# error CONF_CLOCK_CPU_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBA_DIVIDER) -# error CONF_CLOCK_APBA_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBB_DIVIDER) -# error CONF_CLOCK_APBB_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_APBC_DIVIDER) -# error CONF_CLOCK_APBC_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_PRESCALER) -# error CONF_CLOCK_OSC8M_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_ON_DEMAND) -# error CONF_CLOCK_OSC8M_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC8M_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC8M_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ENABLE) -# error CONF_CLOCK_XOSC_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY) -# error CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_STARTUP_TIME) -# error CONF_CLOCK_XOSC_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL) -# error CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_ON_DEMAND) -# error CONF_CLOCK_XOSC_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE) -# error CONF_CLOCK_XOSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL) -# error CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_STARTUP_TIME) -# error CONF_CLOCK_XOSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL) -# error CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_ON_DEMAND) -# error CONF_CLOCK_XOSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_XOSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_XOSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE) -# error CONF_CLOCK_OSC32K_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_STARTUP_TIME) -# error CONF_CLOCK_OSC32K_STARTUP_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT) -# error CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_ON_DEMAND) -# error CONF_CLOCK_OSC32K_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_OSC32K_RUN_IN_STANDBY) -# error CONF_CLOCK_OSC32K_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE) -# error CONF_CLOCK_DFLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_LOOP_MODE) -# error CONF_CLOCK_DFLL_LOOP_MODE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ON_DEMAND) -# error CONF_CLOCK_DFLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_FINE_VALUE) -# error CONF_CLOCK_DFLL_FINE_VALUE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR) -# error CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MULTIPLY_FACTOR) -# error CONF_CLOCK_DFLL_MULTIPLY_FACTOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_QUICK_LOCK) -# error CONF_CLOCK_DFLL_QUICK_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK) -# error CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP) -# error CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE) -# error CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE) -# error CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ENABLE) -# error CONF_CLOCK_DPLL_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_ON_DEMAND) -# error CONF_CLOCK_DPLL_ON_DEMAND not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_RUN_IN_STANDBY) -# error CONF_CLOCK_DPLL_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_BYPASS) -# error CONF_CLOCK_DPLL_LOCK_BYPASS not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_WAKE_UP_FAST) -# error CONF_CLOCK_DPLL_WAKE_UP_FAST not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOW_POWER_ENABLE) -# error CONF_CLOCK_DPLL_LOW_POWER_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_TIME) -# error CONF_CLOCK_DPLL_LOCK_TIME not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_CLOCK) -# error CONF_CLOCK_DPLL_REFERENCE_CLOCK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_FILTER) -# error CONF_CLOCK_DPLL_FILTER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_FREQUENCY) -# error CONF_CLOCK_DPLL_REFERENCE_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_DIVIDER) -# error CONF_CLOCK_DPLL_REFERENCE_DIVIDER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_OUTPUT_FREQUENCY) -# error CONF_CLOCK_DPLL_OUTPUT_FREQUENCY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR) -# error CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_CONFIGURE_GCLK) -# error CONF_CLOCK_CONFIGURE_GCLK not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_ENABLE) -# error CONF_CLOCK_GCLK_0_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_0_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_0_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_PRESCALER) -# error CONF_CLOCK_GCLK_0_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_0_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_0_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_ENABLE) -# error CONF_CLOCK_GCLK_1_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_1_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_1_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_PRESCALER) -# error CONF_CLOCK_GCLK_1_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_1_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_1_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_ENABLE) -# error CONF_CLOCK_GCLK_2_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_2_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_2_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_PRESCALER) -# error CONF_CLOCK_GCLK_2_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_2_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_2_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_ENABLE) -# error CONF_CLOCK_GCLK_3_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_3_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_3_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_PRESCALER) -# error CONF_CLOCK_GCLK_3_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_3_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_3_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_ENABLE) -# error CONF_CLOCK_GCLK_4_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_4_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_4_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_PRESCALER) -# error CONF_CLOCK_GCLK_4_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_4_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_4_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_ENABLE) -# error CONF_CLOCK_GCLK_5_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_5_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_5_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_PRESCALER) -# error CONF_CLOCK_GCLK_5_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_5_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_5_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_ENABLE) -# error CONF_CLOCK_GCLK_6_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_6_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_6_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_PRESCALER) -# error CONF_CLOCK_GCLK_6_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_6_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_6_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_ENABLE) -# error CONF_CLOCK_GCLK_7_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_7_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_7_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_PRESCALER) -# error CONF_CLOCK_GCLK_7_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_7_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_7_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_ENABLE) -# error CONF_CLOCK_GCLK_8_ENABLE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_RUN_IN_STANDBY) -# error CONF_CLOCK_GCLK_8_RUN_IN_STANDBY not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_CLOCK_SOURCE) -# error CONF_CLOCK_GCLK_8_CLOCK_SOURCE not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_PRESCALER) -# error CONF_CLOCK_GCLK_8_PRESCALER not defined in conf_clocks.h -#endif - -#if !defined(CONF_CLOCK_GCLK_8_OUTPUT_ENABLE) -# error CONF_CLOCK_GCLK_8_OUTPUT_ENABLE not defined in conf_clocks.h -#endif - -#endif /* CLOCK_CONFIG_CHECK_H */ diff --git a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock_feature.h b/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock_feature.h deleted file mode 100644 index ee8890a3120ee..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/clock_feature.h +++ /dev/null @@ -1,1492 +0,0 @@ -/** - * \file - * - * \brief SAM Clock Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_FEATURE_H_INCLUDED -#define SYSTEM_CLOCK_FEATURE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_clock_group SAM System Clock Management (SYSTEM CLOCK) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's clocking related functions. This includes - * the various clock sources, bus clocks, and generic clocks within the device, - * with functions to manage the enabling, disabling, source selection, and - * prescaling of clocks to various internal peripherals. - * - * The following peripherals are used by this module: - * - * - GCLK (Generic Clock Management) - * - PM (Power Management) - * - SYSCTRL (Clock Source Control) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM DA1 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_clock_prerequisites - * - \ref asfdoc_sam0_system_clock_module_overview - * - \ref asfdoc_sam0_system_clock_special_considerations - * - \ref asfdoc_sam0_system_clock_extra_info - * - \ref asfdoc_sam0_system_clock_examples - * - \ref asfdoc_sam0_system_clock_api_overview - * - * - * \section asfdoc_sam0_system_clock_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_clock_module_overview Module Overview - * The SAM devices contain a sophisticated clocking system, which is designed - * to give the maximum flexibility to the user application. This system allows - * a system designer to tune the performance and power consumption of the device - * in a dynamic manner, to achieve the best trade-off between the two for a - * particular application. - * - * This driver provides a set of functions for the configuration and management - * of the various clock related functionality within the device. - * - * \subsection asfdoc_sam0_system_clock_module_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_SYSTEM_CLOCK_DPLLSAM D21, SAM R21, SAM D10, SAM D11, SAM DA1
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_sources Clock Sources - * The SAM devices have a number of master clock source modules, each of - * which being capable of producing a stabilized output frequency, which can then - * be fed into the various peripherals and modules within the device. - * - * Possible clock source modules include internal R/C oscillators, internal - * DFLL modules, as well as external crystal oscillators and/or clock inputs. - * - * \subsection asfdoc_sam0_system_clock_module_overview_cpu_clock CPU / Bus Clocks - * The CPU and AHB/APBx buses are clocked by the same physical clock source - * (referred in this module as the Main Clock), however the APBx buses may - * have additional prescaler division ratios set to give each peripheral bus a - * different clock speed. - * - * The general main clock tree for the CPU and associated buses is shown in - * \ref asfdoc_sam0_system_clock_module_clock_tree "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_clock_tree - * \dot - * digraph overview { - * rankdir=LR; - * clk_src [label="Clock Sources", shape=none, height=0]; - * node [label="CPU Bus" shape=ellipse] cpu_bus; - * node [label="AHB Bus" shape=ellipse] ahb_bus; - * node [label="APBA Bus" shape=ellipse] apb_a_bus; - * node [label="APBB Bus" shape=ellipse] apb_b_bus; - * node [label="APBC Bus" shape=ellipse] apb_c_bus; - * node [label="Main Bus\nPrescaler" shape=square] main_prescaler; - * node [label="APBA Bus\nPrescaler" shape=square] apb_a_prescaler; - * node [label="APBB Bus\nPrescaler" shape=square] apb_b_prescaler; - * node [label="APBC Bus\nPrescaler" shape=square] apb_c_prescaler; - * node [label="", shape=polygon, sides=4, distortion=0.6, orientation=90, style=filled, fillcolor=black, height=0.9, width=0.2] main_clock_mux; - * - * clk_src -> main_clock_mux; - * main_clock_mux -> main_prescaler; - * main_prescaler -> cpu_bus; - * main_prescaler -> ahb_bus; - * main_prescaler -> apb_a_prescaler; - * main_prescaler -> apb_b_prescaler; - * main_prescaler -> apb_c_prescaler; - * apb_a_prescaler -> apb_a_bus; - * apb_b_prescaler -> apb_b_bus; - * apb_c_prescaler -> apb_c_bus; - * } - * \enddot - * - * \subsection asfdoc_sam0_system_clock_module_overview_clock_masking Clock Masking - * To save power, the input clock to one or more peripherals on the AHB and APBx - * buses can be masked away - when masked, no clock is passed into the module. - * Disabling of clocks of unused modules will prevent all access to the masked - * module, but will reduce the overall device power consumption. - * - * \subsection asfdoc_sam0_system_clock_module_overview_gclk Generic Clocks - * Within the SAM devices there are a number of Generic Clocks; these are used to - * provide clocks to the various peripheral clock domains in the device in a - * standardized manner. One or more master source clocks can be selected as the - * input clock to a Generic Clock Generator, which can prescale down the input - * frequency to a slower rate for use in a peripheral. - * - * Additionally, a number of individually selectable Generic Clock Channels are - * provided, which multiplex and gate the various generator outputs for one or - * more peripherals within the device. This setup allows for a single common - * generator to feed one or more channels, which can then be enabled or disabled - * individually as required. - * - * \anchor asfdoc_sam0_system_clock_module_chain_overview - * \dot - * digraph overview { - * rankdir=LR; - * node [label="Clock\nSource a" shape=square] system_clock_source; - * node [label="Generator 1" shape=square] clock_gen; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Peripheral x" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * node [label="Peripheral y" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * - * system_clock_source -> clock_gen; - * clock_gen -> clock_chan0; - * clock_chan0 -> peripheral0; - * clock_gen -> clock_chan1; - * clock_chan1 -> peripheral1; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_chain_example Clock Chain Example - * An example setup of a complete clock chain within the device is shown in - * \ref asfdoc_sam0_system_clock_module_chain_example_fig "the figure below". - * - * \anchor asfdoc_sam0_system_clock_module_chain_example_fig - * \dot - * digraph overview { - * rankdir=LR; - * node [label="External\nOscillator" shape=square] system_clock_source0; - * node [label="Generator 0" shape=square] clock_gen0; - * node [label="Channel x" shape=square] clock_chan0; - * node [label="Core CPU" shape=ellipse style=filled fillcolor=lightgray] peripheral0; - * - * system_clock_source0 -> clock_gen0; - * clock_gen0 -> clock_chan0; - * clock_chan0 -> peripheral0; - * node [label="8MHz R/C\nOscillator (OSC8M)" shape=square fillcolor=white] system_clock_source1; - * node [label="Generator 1" shape=square] clock_gen1; - * node [label="Channel y" shape=square] clock_chan1; - * node [label="Channel z" shape=square] clock_chan2; - * node [label="SERCOM\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral1; - * node [label="Timer\nModule" shape=ellipse style=filled fillcolor=lightgray] peripheral2; - * - * system_clock_source1 -> clock_gen1; - * clock_gen1 -> clock_chan1; - * clock_gen1 -> clock_chan2; - * clock_chan1 -> peripheral1; - * clock_chan2 -> peripheral2; - * } - * \enddot - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_generators Generic Clock Generators - * Each Generic Clock generator within the device can source its input clock - * from one of the provided Source Clocks, and prescale the output for one or - * more Generic Clock Channels in a one-to-many relationship. The generators - * thus allow for several clocks to be generated of different frequencies, - * power usages, and accuracies, which can be turned on and off individually to - * disable the clocks to multiple peripherals as a group. - * - * \subsubsection asfdoc_sam0_system_clock_module_overview_gclk_channels Generic Clock Channels - * To connect a Generic Clock Generator to a peripheral within the - * device, a Generic Clock Channel is used. Each peripheral or - * peripheral group has an associated Generic Clock Channel, which serves as the - * clock input for the peripheral(s). To supply a clock to the peripheral - * module(s), the associated channel must be connected to a running Generic - * Clock Generator and the channel enabled. - * - * \section asfdoc_sam0_system_clock_special_considerations Special Considerations - * - * There are no special considerations for this module. - * - * - * \section asfdoc_sam0_system_clock_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_clock_extra. This includes: - * - \ref asfdoc_sam0_system_clock_extra_acronyms - * - \ref asfdoc_sam0_system_clock_extra_dependencies - * - \ref asfdoc_sam0_system_clock_extra_errata - * - \ref asfdoc_sam0_system_clock_extra_history - * - * - * \section asfdoc_sam0_system_clock_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_clock_exqsg. - * - * - * \section asfdoc_sam0_system_clock_api_overview API Overview - * @{ - */ - -#include -#include - -/** - * \name Driver Feature Definition - * Define system clock features set according to different device family. - * @{ - */ -#if (SAMD21) || (SAMR21) || (SAMD11) || (SAMD10) || (SAMDA1) || defined(__DOXYGEN__) -/** Digital Phase Locked Loop (DPLL) feature support. */ -# define FEATURE_SYSTEM_CLOCK_DPLL -#endif -/*@}*/ - -/** - * \brief Available start-up times for the XOSC32K. - * - * Available external 32KHz oscillator start-up times, as a number of external - * clock cycles. - */ -enum system_xosc32k_startup { - /** Wait zero clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_0, - /** Wait 32 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_32, - /** Wait 2048 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_4096, - /** Wait 16384 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_32768, - /** Wait 65536 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_65536, - /** Wait 131072 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC32K_STARTUP_131072, -}; - -/** - * \brief Available start-up times for the XOSC. - * - * Available external oscillator start-up times, as a number of external clock - * cycles. - */ -enum system_xosc_startup { - /** Wait one clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_1, - /** Wait two clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_2, - /** Wait four clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_4, - /** Wait eight clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_8, - /** Wait 16 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_16, - /** Wait 32 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_32, - /** Wait 64 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_64, - /** Wait 128 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_128, - /** Wait 256 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_256, - /** Wait 512 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_512, - /** Wait 1024 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_1024, - /** Wait 2048 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_2048, - /** Wait 4096 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_4096, - /** Wait 8192 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_8192, - /** Wait 16384 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_16384, - /** Wait 32768 clock cycles until the clock source is considered stable */ - SYSTEM_XOSC_STARTUP_32768, -}; - -/** - * \brief Available start-up times for the OSC32K. - * - * Available internal 32KHz oscillator start-up times, as a number of internal - * OSC32K clock cycles. - */ -enum system_osc32k_startup { - /** Wait three clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_3, - /** Wait four clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_4, - /** Wait six clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_6, - /** Wait ten clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_10, - /** Wait 18 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_18, - /** Wait 34 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_34, - /** Wait 66 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_66, - /** Wait 130 clock cycles until the clock source is considered stable */ - SYSTEM_OSC32K_STARTUP_130, -}; - -/** - * \brief Division prescalers for the internal 8MHz system clock. - * - * Available prescalers for the internal 8MHz (nominal) system clock. - */ -enum system_osc8m_div { - /** Do not divide the 8MHz RC oscillator output */ - SYSTEM_OSC8M_DIV_1, - /** Divide the 8MHz RC oscillator output by two */ - SYSTEM_OSC8M_DIV_2, - /** Divide the 8MHz RC oscillator output by four */ - SYSTEM_OSC8M_DIV_4, - /** Divide the 8MHz RC oscillator output by eight */ - SYSTEM_OSC8M_DIV_8, -}; - -/** - * \brief Frequency range for the internal 8MHz RC oscillator. - * - * Internal 8MHz RC oscillator frequency range setting. - */ -enum system_osc8m_frequency_range { - /** Frequency range 4MHz to 6MHz */ - SYSTEM_OSC8M_FREQUENCY_RANGE_4_TO_6, - /** Frequency range 6MHz to 8MHz */ - SYSTEM_OSC8M_FREQUENCY_RANGE_6_TO_8, - /** Frequency range 8MHz to 11MHz */ - SYSTEM_OSC8M_FREQUENCY_RANGE_8_TO_11, - /** Frequency range 11MHz to 15MHz */ - SYSTEM_OSC8M_FREQUENCY_RANGE_11_TO_15, -}; - -/** - * \brief Main CPU and APB/AHB bus clock source prescaler values. - * - * Available division ratios for the CPU and APB/AHB bus clocks. - */ -enum system_main_clock_div { - /** Divide Main clock by one */ - SYSTEM_MAIN_CLOCK_DIV_1, - /** Divide Main clock by two */ - SYSTEM_MAIN_CLOCK_DIV_2, - /** Divide Main clock by four */ - SYSTEM_MAIN_CLOCK_DIV_4, - /** Divide Main clock by eight */ - SYSTEM_MAIN_CLOCK_DIV_8, - /** Divide Main clock by 16 */ - SYSTEM_MAIN_CLOCK_DIV_16, - /** Divide Main clock by 32 */ - SYSTEM_MAIN_CLOCK_DIV_32, - /** Divide Main clock by 64 */ - SYSTEM_MAIN_CLOCK_DIV_64, - /** Divide Main clock by 128 */ - SYSTEM_MAIN_CLOCK_DIV_128, -}; - -/** - * \brief External clock source types. - * - * Available external clock source types. - */ -enum system_clock_external { - /** The external clock source is a crystal oscillator */ - SYSTEM_CLOCK_EXTERNAL_CRYSTAL, - /** The connected clock source is an external logic level clock signal */ - SYSTEM_CLOCK_EXTERNAL_CLOCK, -}; - -/** - * \brief Operating modes of the DFLL clock source. - * - * Available operating modes of the DFLL clock source module. - */ -enum system_clock_dfll_loop_mode { - /** The DFLL is operating in open loop mode with no feedback */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN, - /** The DFLL is operating in closed loop mode with frequency feedback from - * a low frequency reference clock - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED = SYSCTRL_DFLLCTRL_MODE, - -#ifdef SYSCTRL_DFLLCTRL_USBCRM - /** The DFLL is operating in USB recovery mode with frequency feedback - * from USB SOF. - */ - SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY = SYSCTRL_DFLLCTRL_USBCRM, -#endif -}; - -/** - * \brief Locking behavior for the DFLL during device wake-up. - * - * DFLL lock behavior modes on device wake-up from sleep. - */ -enum system_clock_dfll_wakeup_lock { - /** Keep DFLL lock when the device wakes from sleep */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP, - /** Lose DFLL lock when the devices wakes from sleep */ - SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_LOSE = SYSCTRL_DFLLCTRL_LLAW, -}; - -/** - * \brief Fine tracking behavior for the DFLL once a lock has been acquired. - * - * DFLL fine tracking behavior modes after a lock has been acquired. - */ -enum system_clock_dfll_stable_tracking { - /** Keep tracking after the DFLL has gotten a fine lock */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK, - /** Stop tracking after the DFLL has gotten a fine lock */ - SYSTEM_CLOCK_DFLL_STABLE_TRACKING_FIX_AFTER_LOCK = SYSCTRL_DFLLCTRL_STABLE, -}; - -/** - * \brief Chill-cycle behavior of the DFLL module. - * - * DFLL chill-cycle behavior modes of the DFLL module. A chill cycle is a period - * of time when the DFLL output frequency is not measured by the unit, to allow - * the output to stabilize after a change in the input clock source. - */ -enum system_clock_dfll_chill_cycle { - /** Enable a chill cycle, where the DFLL output frequency is not measured */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE, - /** Disable a chill cycle, where the DFLL output frequency is not measured */ - SYSTEM_CLOCK_DFLL_CHILL_CYCLE_DISABLE = SYSCTRL_DFLLCTRL_CCDIS, -}; - -/** - * \brief QuickLock settings for the DFLL module. - * - * DFLL QuickLock settings for the DFLL module, to allow for a faster lock of - * the DFLL output frequency at the expense of accuracy. - */ -enum system_clock_dfll_quick_lock { - /** Enable the QuickLock feature for looser lock requirements on the DFLL */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE, - /** Disable the QuickLock feature for strict lock requirements on the DFLL */ - SYSTEM_CLOCK_DFLL_QUICK_LOCK_DISABLE = SYSCTRL_DFLLCTRL_QLDIS, -}; - -/** - * \brief Available clock sources in the system. - * - * Clock sources available to the GCLK generators. - */ -enum system_clock_source { - /** Internal 8MHz RC oscillator */ - SYSTEM_CLOCK_SOURCE_OSC8M = GCLK_SOURCE_OSC8M, - /** Internal 32KHz RC oscillator */ - SYSTEM_CLOCK_SOURCE_OSC32K = GCLK_SOURCE_OSC32K, - /** External oscillator */ - SYSTEM_CLOCK_SOURCE_XOSC = GCLK_SOURCE_XOSC , - /** External 32KHz oscillator */ - SYSTEM_CLOCK_SOURCE_XOSC32K = GCLK_SOURCE_XOSC32K, - /** Digital Frequency Locked Loop (DFLL) */ - SYSTEM_CLOCK_SOURCE_DFLL = GCLK_SOURCE_DFLL48M, - /** Internal Ultra Low Power 32KHz oscillator */ - SYSTEM_CLOCK_SOURCE_ULP32K = GCLK_SOURCE_OSCULP32K, - /** Generator input pad */ - SYSTEM_CLOCK_SOURCE_GCLKIN = GCLK_SOURCE_GCLKIN, - /** Generic clock generator one output */ - SYSTEM_CLOCK_SOURCE_GCLKGEN1 = GCLK_SOURCE_GCLKGEN1, -#ifdef FEATURE_SYSTEM_CLOCK_DPLL - /** Digital Phase Locked Loop (DPLL). - * Check \c FEATURE_SYSTEM_CLOCK_DPLL for which device support it. - */ - SYSTEM_CLOCK_SOURCE_DPLL = GCLK_SOURCE_FDPLL, -#endif -}; - -/** - * \brief List of APB peripheral buses. - * - * Available bus clock domains on the APB bus. - */ -enum system_clock_apb_bus { - /** Peripheral bus A on the APB bus */ - SYSTEM_CLOCK_APB_APBA, - /** Peripheral bus B on the APB bus */ - SYSTEM_CLOCK_APB_APBB, - /** Peripheral bus C on the APB bus */ - SYSTEM_CLOCK_APB_APBC, -}; - -/** - * \brief Configuration structure for XOSC. - * - * External oscillator clock configuration structure. - */ -struct system_clock_source_xosc_config { - /** External clock type */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time */ - enum system_xosc_startup startup_time; - /** Enable automatic amplitude gain control */ - bool auto_gain_control; - /** External clock/crystal frequency */ - uint32_t frequency; - /** Keep the XOSC enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC won't run - * until requested by a peripheral. */ - bool on_demand; -}; - -/** - * \brief Configuration structure for XOSC32K. - * - * External 32KHz oscillator clock configuration structure. - */ -struct system_clock_source_xosc32k_config { - /** External clock type */ - enum system_clock_external external_clock; - /** Crystal oscillator start-up time */ - enum system_xosc32k_startup startup_time; - /** Enable automatic amplitude control */ - bool auto_gain_control; - /** Enable 1KHz output */ - bool enable_1khz_output; - /** Enable 32KHz output */ - bool enable_32khz_output; - /** External clock/crystal frequency */ - uint32_t frequency; - /** Keep the XOSC32K enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the XOSC32K won't run - * until requested by a peripheral. */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock */ - bool write_once; -}; - -/** - * \brief Configuration structure for OSC8M. - * - * Internal 8MHz (nominal) oscillator configuration structure. - */ -struct system_clock_source_osc8m_config { - /** Internal 8MHz RC oscillator prescaler */ - enum system_osc8m_div prescaler; - /** Keep the OSC8M enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC8M won't run - * until requested by a peripheral. */ - bool on_demand; -}; - -/** - * \brief Configuration structure for OSC32K. - * - * Internal 32KHz (nominal) oscillator configuration structure. - */ -struct system_clock_source_osc32k_config { - /** Startup time */ - enum system_osc32k_startup startup_time; - /** Enable 1KHz output */ - bool enable_1khz_output; - /** Enable 32KHz output */ - bool enable_32khz_output; - /** Keep the OSC32K enabled in standby sleep mode */ - bool run_in_standby; - /** Run On Demand. If this is set the OSC32K won't run - * until requested by a peripheral */ - bool on_demand; - /** Lock configuration after it has been written, - * a device reset will release the lock */ - bool write_once; -}; - -/** - * \brief Configuration structure for DFLL. - * - * DFLL oscillator configuration structure. - */ -struct system_clock_source_dfll_config { - /** Loop mode */ - enum system_clock_dfll_loop_mode loop_mode; - /** Run On Demand. If this is set the DFLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Enable Quick Lock */ - enum system_clock_dfll_quick_lock quick_lock; - /** Enable Chill Cycle */ - enum system_clock_dfll_chill_cycle chill_cycle; - /** DFLL lock state on wakeup */ - enum system_clock_dfll_wakeup_lock wakeup_lock; - /** DFLL tracking after fine lock */ - enum system_clock_dfll_stable_tracking stable_tracking; - /** Coarse calibration value (Open loop mode) */ - uint8_t coarse_value; - /** Fine calibration value (Open loop mode) */ - uint16_t fine_value; - /** Coarse adjustment maximum step size (Closed loop mode) */ - uint8_t coarse_max_step; - /** Fine adjustment maximum step size (Closed loop mode) */ - uint16_t fine_max_step; - /** DFLL multiply factor (Closed loop mode */ - uint16_t multiply_factor; -}; - -/** - * \name External Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC. - * - * Fills a configuration structure with the default configuration for an - * external oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode enabled - * - Frequency of 12MHz - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc_get_config_defaults( - struct system_clock_source_xosc_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC_STARTUP_16384; - config->auto_gain_control = true; - config->frequency = 12000000UL; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_xosc_set_config( - struct system_clock_source_xosc_config *const config); - -/** - * @} - */ - - -/** - * \name External 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for XOSC32K. - * - * Fills a configuration structure with the default configuration for an - * external 32KHz oscillator module: - * - External Crystal - * - Start-up time of 16384 external clock cycles - * - Automatic crystal gain control mode disabled - * - Frequency of 32.768KHz - * - 1KHz clock output disabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_xosc32k_get_config_defaults( - struct system_clock_source_xosc32k_config *const config) -{ - Assert(config); - - config->external_clock = SYSTEM_CLOCK_EXTERNAL_CRYSTAL; - config->startup_time = SYSTEM_XOSC32K_STARTUP_16384; - config->auto_gain_control = false; - config->frequency = 32768UL; - config->enable_1khz_output = false; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->write_once = false; -} - -void system_clock_source_xosc32k_set_config( - struct system_clock_source_xosc32k_config *const config); -/** - * @} - */ - - -/** - * \name Internal 32KHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC32K. - * - * Fills a configuration structure with the default configuration for an - * internal 32KHz oscillator module: - * - 1KHz clock output enabled - * - 32KHz clock output enabled - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - Set startup time to 130 cycles - * - Don't lock registers after configuration has been written - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc32k_get_config_defaults( - struct system_clock_source_osc32k_config *const config) -{ - Assert(config); - - config->enable_1khz_output = true; - config->enable_32khz_output = true; - config->run_in_standby = false; - config->on_demand = true; - config->startup_time = SYSTEM_OSC32K_STARTUP_130; - config->write_once = false; -} - -void system_clock_source_osc32k_set_config( - struct system_clock_source_osc32k_config *const config); - -/** - * @} - */ - - -/** - * \name Internal 8MHz Oscillator Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for OSC8M. - * - * Fills a configuration structure with the default configuration for an - * internal 8MHz (nominal) oscillator module: - * - Clock output frequency divided by a factor of eight - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_osc8m_get_config_defaults( - struct system_clock_source_osc8m_config *const config) -{ - Assert(config); - - config->prescaler = SYSTEM_OSC8M_DIV_8; - config->run_in_standby = false; - config->on_demand = true; -} - -void system_clock_source_osc8m_set_config( - struct system_clock_source_osc8m_config *const config); - -/** - * @} - */ - - -/** - * \name Internal DFLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DFLL. - * - * Fills a configuration structure with the default configuration for a - * DFLL oscillator module: - * - Open loop mode - * - QuickLock mode enabled - * - Chill cycle enabled - * - Output frequency lock maintained during device wake-up - * - Continuous tracking of the output frequency - * - Default tracking values at the mid-points for both coarse and fine - * tracking parameters - * - Don't run in STANDBY sleep mode - * - Run only when requested by peripheral (on demand) - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dfll_get_config_defaults( - struct system_clock_source_dfll_config *const config) -{ - Assert(config); - - config->loop_mode = SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN; - config->quick_lock = SYSTEM_CLOCK_DFLL_QUICK_LOCK_ENABLE; - config->chill_cycle = SYSTEM_CLOCK_DFLL_CHILL_CYCLE_ENABLE; - config->wakeup_lock = SYSTEM_CLOCK_DFLL_WAKEUP_LOCK_KEEP; - config->stable_tracking = SYSTEM_CLOCK_DFLL_STABLE_TRACKING_TRACK_AFTER_LOCK; - config->on_demand = true; - - /* Open loop mode calibration value */ - config->coarse_value = 0x1f / 4; /* Midpoint */ - config->fine_value = 0xff / 4; /* Midpoint */ - - /* Closed loop mode */ - config->coarse_max_step = 1; - config->fine_max_step = 1; - config->multiply_factor = 6; /* Multiply 8MHz by 6 to get 48MHz */ -} - -void system_clock_source_dfll_set_config( - struct system_clock_source_dfll_config *const config); - -/** - * @} - */ - -/** - * \name Clock Source Management - * @{ - */ -enum status_code system_clock_source_write_calibration( - const enum system_clock_source system_clock_source, - const uint16_t calibration_value, - const uint8_t freq_range); - -enum status_code system_clock_source_enable( - const enum system_clock_source system_clock_source); - -enum status_code system_clock_source_disable( - const enum system_clock_source clk_source); - -bool system_clock_source_is_ready( - const enum system_clock_source clk_source); - -uint32_t system_clock_source_get_hz( - const enum system_clock_source clk_source); - -/** - * @} - */ - -/** - * \name Main Clock Management - * @{ - */ - -/** - * \brief Set main CPU clock divider. - * - * Sets the clock divider used on the main clock to provide the CPU clock. - * - * \param[in] divider CPU clock divider to set - */ -static inline void system_cpu_clock_set_divider( - const enum system_main_clock_div divider) -{ - Assert(((uint32_t)divider & PM_CPUSEL_CPUDIV_Msk) == divider); - PM->CPUSEL.reg = (uint32_t)divider; -} - -/** - * \brief Retrieves the current frequency of the CPU core. - * - * Retrieves the operating frequency of the CPU core, obtained from the main - * generic clock and the set CPU bus divider. - * - * \return Current CPU frequency in Hz. - */ -static inline uint32_t system_cpu_clock_get_hz(void) -{ - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> PM->CPUSEL.reg); -} - -/** - * \brief Set APBx clock divider. - * - * Set the clock divider used on the main clock to provide the clock for the - * given APBx bus. - * - * \param[in] divider APBx bus divider to set - * \param[in] bus APBx bus to set divider - * - * \returns Status of the clock division change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given - * \retval STATUS_OK The APBx clock was set successfully - */ -static inline enum status_code system_apb_clock_set_divider( - const enum system_clock_apb_bus bus, - const enum system_main_clock_div divider) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBASEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBB: - PM->APBBSEL.reg = (uint32_t)divider; - break; - case SYSTEM_CLOCK_APB_APBC: - PM->APBCSEL.reg = (uint32_t)divider; - break; - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Retrieves the current frequency of a ABPx. - * - * Retrieves the operating frequency of an APBx bus, obtained from the main - * generic clock and the set APBx bus divider. - * - * \return Current APBx bus frequency in Hz. - */ -static inline uint32_t system_apb_clock_get_hz( - const enum system_clock_apb_bus bus) -{ - uint16_t bus_divider = 0; - - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - bus_divider = PM->APBASEL.reg; - break; - case SYSTEM_CLOCK_APB_APBB: - bus_divider = PM->APBBSEL.reg; - break; - case SYSTEM_CLOCK_APB_APBC: - bus_divider = PM->APBCSEL.reg; - break; - default: - Assert(false); - return 0; - } - - return (system_gclk_gen_get_hz(GCLK_GENERATOR_0) >> bus_divider); -} - - -/** - * @} - */ - -/** - * \name Bus Clock Masking - * @{ - */ - -/** - * \brief Set bits in the clock mask for the AHB bus. - * - * This function will set bits in the clock mask for the AHB bus. - * Any bits set to 1 will enable that clock, 0 bits in the mask - * will be ignored. - * - * \param[in] ahb_mask AHB clock mask to enable - */ -static inline void system_ahb_clock_set_mask( - const uint32_t ahb_mask) -{ - PM->AHBMASK.reg |= ahb_mask; -} - -/** - * \brief Clear bits in the clock mask for the AHB bus. - * - * This function will clear bits in the clock mask for the AHB bus. - * Any bits set to 1 will disable that clock, 0 bits in the mask - * will be ignored. - * - * \param[in] ahb_mask AHB clock mask to disable - */ -static inline void system_ahb_clock_clear_mask( - const uint32_t ahb_mask) -{ - PM->AHBMASK.reg &= ~ahb_mask; -} - -/** - * \brief Set bits in the clock mask for an APBx bus. - * - * This function will set bits in the clock mask for an APBx bus. - * Any bits set to 1 will enable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to set clock mask bits for, a mask of \c PM_APBxMASK_* - * constants from the device header files - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus given - * \retval STATUS_OK The clock mask was set successfully - */ -static inline enum status_code system_apb_clock_set_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg |= mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg |= mask; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - - } - - return STATUS_OK; -} - -/** - * \brief Clear bits in the clock mask for an APBx bus. - * - * This function will clear bits in the clock mask for an APBx bus. - * Any bits set to 1 will disable the corresponding module clock, zero bits in - * the mask will be ignored. - * - * \param[in] mask APBx clock mask, a \c SYSTEM_CLOCK_APB_APBx constant from - * the device header files - * \param[in] bus Bus to clear clock mask bits - * - * \returns Status indicating the result of the clock mask change operation. - * - * \retval STATUS_ERR_INVALID_ARG Invalid bus ID was given - * \retval STATUS_OK The clock mask was changed successfully - */ -static inline enum status_code system_apb_clock_clear_mask( - const enum system_clock_apb_bus bus, - const uint32_t mask) -{ - switch (bus) { - case SYSTEM_CLOCK_APB_APBA: - PM->APBAMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBB: - PM->APBBMASK.reg &= ~mask; - break; - - case SYSTEM_CLOCK_APB_APBC: - PM->APBCMASK.reg &= ~mask; - break; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * @} - */ - -#ifdef FEATURE_SYSTEM_CLOCK_DPLL -/** - * \brief Reference clock source of the DPLL module. - */ -enum system_clock_source_dpll_reference_clock { - /** Select XOSC32K as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K, - /** Select XOSC as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC, - /** Select GCLK as clock reference. */ - SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_GCLK, -}; - -/** - * \brief Lock time-out value of the DPLL module. - */ -enum system_clock_source_dpll_lock_time { - /** Set no time-out as default. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT, - /** Set time-out if no lock within 8ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_8MS = 0x04, - /** Set time-out if no lock within 9ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_9MS, - /** Set time-out if no lock within 10ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_10MS, - /** Set time-out if no lock within 11ms. */ - SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_11MS, -}; - -/** - * \brief Filter type of the DPLL module. - */ -enum system_clock_source_dpll_filter { - /** Default filter mode. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT, - /** Low bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_LOW_BANDWIDTH_FILTER, - /** High bandwidth filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_BANDWIDTH_FILTER, - /** High damping filter. */ - SYSTEM_CLOCK_SOURCE_DPLL_FILTER_HIGH_DAMPING_FILTER, -}; - -/** - * \brief Configuration structure for DPLL. - * - * DPLL oscillator configuration structure. - */ -struct system_clock_source_dpll_config { - /** Run On Demand. If this is set the DPLL won't run - * until requested by a peripheral. */ - bool on_demand; - /** Keep the DPLL enabled in standby sleep mode. */ - bool run_in_standby; - /** Bypass lock signal. */ - bool lock_bypass; - /** Wake up fast. If this is set DPLL output clock is enabled after - * the startup time. */ - bool wake_up_fast; - /** Enable low power mode. */ - bool low_power_enable; - - /** Output frequency of the clock. */ - uint32_t output_frequency; - /** Reference frequency of the clock. */ - uint32_t reference_frequency; - /** Devider of reference clock. */ - uint16_t reference_divider; - - /** Filter type of the DPLL module. */ - enum system_clock_source_dpll_filter filter; - /** Lock time-out value of the DPLL module. */ - enum system_clock_source_dpll_lock_time lock_time; - /** Reference clock source of the DPLL module. */ - enum system_clock_source_dpll_reference_clock reference_clock; -}; - -/** - * \name Internal DPLL Management - * @{ - */ - -/** - * \brief Retrieve the default configuration for DPLL. - * - * Fills a configuration structure with the default configuration for a - * DPLL oscillator module: - * - Run only when requested by peripheral (on demand) - * - Don't run in STANDBY sleep mode - * - Lock bypass disabled - * - Fast wake up disabled - * - Low power mode disabled - * - Output frequency is 48MHz - * - Reference clock frequency is 32768Hz - * - Not divide reference clock - * - Select REF0 as reference clock - * - Set lock time to default mode - * - Use default filter - * - * \param[out] config Configuration structure to fill with default values - */ -static inline void system_clock_source_dpll_get_config_defaults( - struct system_clock_source_dpll_config *const config) -{ - config->on_demand = true; - config->run_in_standby = false; - config->lock_bypass = false; - config->wake_up_fast = false; - config->low_power_enable = false; - - config->output_frequency = 48000000; - config->reference_frequency = 32768; - config->reference_divider = 1; - config->reference_clock = SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K; - - config->lock_time = SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT; - config->filter = SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT; -}; - -void system_clock_source_dpll_set_config( - struct system_clock_source_dpll_config *const config); - -/* @} */ -#endif - -/** - * \name System Clock Initialization - * @{ - */ - -void system_clock_init(uint16_t dfll_fine_calibration); - -/** - * @} - */ - -/** - * \name System Flash Wait States - * @{ - */ - -/** - * \brief Set flash controller wait states. - * - * Will set the number of wait states that are used by the onboard - * flash memory. The number of wait states depend on both device - * supply voltage and CPU speed. The required number of wait states - * can be found in the electrical characteristics of the device. - * - * \param[in] wait_states Number of wait states to use for internal flash - */ -static inline void system_flash_set_waitstates(uint8_t wait_states) -{ - Assert(NVMCTRL_CTRLB_RWS((uint32_t)wait_states) == - ((uint32_t)wait_states << NVMCTRL_CTRLB_RWS_Pos)); - - NVMCTRL->CTRLB.bit.RWS = wait_states; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * \page asfdoc_sam0_system_clock_extra Extra Information for SYSTEM CLOCK Driver - * - * \section asfdoc_sam0_system_clock_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DFLLDigital Frequency Locked Loop
MUXMultiplexer
OSC32KInternal 32KHz Oscillator
OSC8MInternal 8MHz Oscillator
PLLPhase Locked Loop
OSCOscillator
XOSCExternal Oscillator
XOSC32KExternal 32KHz Oscillator
AHBAdvanced High-performance Bus
APBAdvanced Peripheral Bus
DPLLDigital Phase Locked Loop
- * - * - * \section asfdoc_sam0_system_clock_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_clock_extra_errata Errata - * - * - This driver implements experimental workaround for errata 9905 - * - * "The DFLL clock must be requested before being configured otherwise a - * write access to a DFLL register can freeze the device." - * This driver will enable and configure the DFLL before the ONDEMAND bit is set. - * - * - * \section asfdoc_sam0_system_clock_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
- * \li Corrected OSC32K startup time definitions - * \li Support locking of OSC32K and XOSC32K config register (default: false) - * \li Added DPLL support, functions added: - * \c system_clock_source_dpll_get_config_defaults() and - * \c system_clock_source_dpll_set_config() - * \li Moved gclk channel locking feature out of the config struct - * functions added: - * \c system_gclk_chan_lock(), - * \c system_gclk_chan_is_locked() - * \c system_gclk_chan_is_enabled() and - * \c system_gclk_gen_is_enabled() - *
Fixed \c system_gclk_chan_disable() deadlocking if a channel is enabled - * and configured to a failed/not running clock generator
- * \li Changed default value for CONF_CLOCK_DFLL_ON_DEMAND from \c true to \c false - * \li Fixed system_flash_set_waitstates() failing with an assertion - * if an odd number of wait states provided - *
- * \li Updated DFLL configuration function to implement workaround for - * errata 9905 in the DFLL module - * \li Updated \c system_clock_init() to reset interrupt flags before - * they are used - * \li Fixed \c system_clock_source_get_hz() to return correcy DFLL - * frequency number - *
\li Fixed \c system_clock_source_is_ready not returning the correct - * state for \c SYSTEM_CLOCK_SOURCE_OSC8M - * \li Renamed the various \c system_clock_source_*_get_default_config() - * functions to \c system_clock_source_*_get_config_defaults() to - * match the remainder of ASF - * \li Added OSC8M calibration constant loading from the device signature - * row when the oscillator is initialized - * \li Updated default configuration of the XOSC32 to disable Automatic - * Gain Control due to silicon errata - *
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_clock_exqsg Examples for System Clock Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_clock_group. QSGs are simple - * examples with step-by-step instructions to configure and use this driver in - * a selection of use cases. Note that a QSG can be compiled as a standalone - * application or be added to the user application. - * - * - \subpage asfdoc_sam0_system_clock_basic_use_case - * - \subpage asfdoc_sam0_system_gclk_basic_use_case - * - * \page asfdoc_sam0_system_clock_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42119E12/2015Added support for SAM DA1 and SAM D09
42119D12/2014Added support for SAM R21 and SAM D10/D11
42119C01/2014Added support for SAM D21
42119B06/2013Corrected documentation typos. Fixed missing steps in the Basic - * Use Case Quick Start Guide
42119A06/2013Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_CLOCK_FEATURE_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/gclk.c b/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/gclk.c deleted file mode 100644 index 79b5a5813f083..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/gclk.c +++ /dev/null @@ -1,522 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Generic Clock Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus, This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval false if the module has completed synchronization - * \retval true if the module synchronization is ongoing - */ -static inline bool system_gclk_is_syncing(void) -{ - if (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY){ - return true; - } - - return false; -} - -/** - * \brief Initializes the GCLK driver. - * - * Initializes the Generic Clock module, disabling and resetting all active - * Generic Clock Generators and Channels to their power-on default values. - */ -void system_gclk_init(void) -{ - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBA, PM_APBAMASK_GCLK); - - /* Software reset the module to ensure it is re-initialized correctly */ - GCLK->CTRL.reg = GCLK_CTRL_SWRST; - while (GCLK->CTRL.reg & GCLK_CTRL_SWRST) { - /* Wait for reset to complete */ - } -} - -/** - * \brief Writes a Generic Clock Generator configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock Generator configuration - * to the hardware module. - * - * \note Changing the clock source on the fly (on a running - * generator) can take additional time if the clock source is configured - * to only run on-demand (ONDEMAND bit is set) and it is not currently - * running (no peripheral is requesting the clock source). In this case - * the GCLK will request the new clock while still keeping a request to - * the old clock source until the new clock source is ready. - * - * \note This function will not start a generator that is not already running; - * to start the generator, call \ref system_gclk_gen_enable() - * after configuring a generator. - * - * \param[in] generator Generic Clock Generator index to configure - * \param[in] config Configuration settings for the generator - */ -void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Cache new register configurations to minimize sync requirements. */ - uint32_t new_genctrl_config = (generator << GCLK_GENCTRL_ID_Pos); - uint32_t new_gendiv_config = (generator << GCLK_GENDIV_ID_Pos); - - /* Select the requested source clock for the generator */ - new_genctrl_config |= config->source_clock << GCLK_GENCTRL_SRC_Pos; - - /* Configure the clock to be either high or low when disabled */ - if (config->high_when_disabled) { - new_genctrl_config |= GCLK_GENCTRL_OOV; - } - - /* Configure if the clock output to I/O pin should be enabled. */ - if (config->output_enable) { - new_genctrl_config |= GCLK_GENCTRL_OE; - } - - /* Set division factor */ - if (config->division_factor > 1) { - /* Check if division is a power of two */ - if (((config->division_factor & (config->division_factor - 1)) == 0)) { - /* Determine the index of the highest bit set to get the - * division factor that must be loaded into the division - * register */ - - uint32_t div2_count = 0; - - uint32_t mask; - for (mask = (1UL << 1); mask < config->division_factor; - mask <<= 1) { - div2_count++; - } - - /* Set binary divider power of 2 division factor */ - new_gendiv_config |= div2_count << GCLK_GENDIV_DIV_Pos; - new_genctrl_config |= GCLK_GENCTRL_DIVSEL; - } else { - /* Set integer division factor */ - - new_gendiv_config |= - (config->division_factor) << GCLK_GENDIV_DIV_Pos; - - /* Enable non-binary division with increased duty cycle accuracy */ - new_genctrl_config |= GCLK_GENCTRL_IDC; - } - - } - - /* Enable or disable the clock in standby mode */ - if (config->run_in_standby) { - new_genctrl_config |= GCLK_GENCTRL_RUNSTDBY; - } - - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the correct generator */ - *((uint8_t*)&GCLK->GENDIV.reg) = generator; - - /* Write the new generator configuration */ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - GCLK->GENDIV.reg = new_gendiv_config; - - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - GCLK->GENCTRL.reg = new_genctrl_config | (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Enables a Generic Clock Generator that was previously configured. - * - * Starts the clock generation of a Generic Clock Generator that was previously - * configured via a call to \ref system_gclk_gen_set_config(). - * - * \param[in] generator Generic Clock Generator index to enable - */ -void system_gclk_gen_enable( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Enable generator */ - GCLK->GENCTRL.reg |= GCLK_GENCTRL_GENEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock Generator that was previously enabled. - * - * Stops the clock generation of a Generic Clock Generator that was previously - * started via a call to \ref system_gclk_gen_enable(). - * - * \param[in] generator Generic Clock Generator index to disable - */ -void system_gclk_gen_disable( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Disable generator */ - GCLK->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; - while (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN) { - /* Wait for clock to become disabled */ - } - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock Generator is enabled. - * - * \param[in] generator Generic Clock Generator index to check - * - * \return The enabled status. - * \retval true The Generic Clock Generator is enabled - * \retval false The Generic Clock Generator is disabled - */ -bool system_gclk_gen_is_enabled( - const uint8_t generator) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Select the requested generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - /* Obtain the enabled status */ - enabled = (GCLK->GENCTRL.reg & GCLK_GENCTRL_GENEN); - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock generator. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * generator, used as a source to a Generic Clock Channel module. - * - * \param[in] generator Generic Clock Generator index - * - * \return The frequency of the generic clock generator, in Hz. - */ -uint32_t system_gclk_gen_get_hz( - const uint8_t generator) -{ - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - system_interrupt_enter_critical_section(); - - /* Select the appropriate generator */ - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - /* Get the frequency of the source connected to the GCLK generator */ - uint32_t gen_input_hz = system_clock_source_get_hz( - (enum system_clock_source)GCLK->GENCTRL.bit.SRC); - - *((uint8_t*)&GCLK->GENCTRL.reg) = generator; - - uint8_t divsel = GCLK->GENCTRL.bit.DIVSEL; - - /* Select the appropriate generator division register */ - *((uint8_t*)&GCLK->GENDIV.reg) = generator; - while (system_gclk_is_syncing()) { - /* Wait for synchronization */ - }; - - uint32_t divider = GCLK->GENDIV.bit.DIV; - - system_interrupt_leave_critical_section(); - - /* Check if the generator is using fractional or binary division */ - if (!divsel && divider > 1) { - gen_input_hz /= divider; - } else if (divsel) { - gen_input_hz >>= (divider+1); - } - - return gen_input_hz; -} - -/** - * \brief Writes a Generic Clock configuration to the hardware module. - * - * Writes out a given configuration of a Generic Clock configuration to the - * hardware module. If the clock is currently running, it will be stopped. - * - * \note Once called the clock will not be running; to start the clock, - * call \ref system_gclk_chan_enable() after configuring a clock channel. - * - * \param[in] channel Generic Clock channel to configure - * \param[in] config Configuration settings for the clock - * - */ -void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Cache the new config to reduce sync requirements */ - uint32_t new_clkctrl_config = (channel << GCLK_CLKCTRL_ID_Pos); - - /* Select the desired generic clock generator */ - new_clkctrl_config |= config->source_generator << GCLK_CLKCTRL_GEN_Pos; - - /* Disable generic clock channel */ - system_gclk_chan_disable(channel); - - /* Write the new configuration */ - GCLK->CLKCTRL.reg = new_clkctrl_config; -} - -/** - * \brief Enables a Generic Clock that was previously configured. - * - * Starts the clock generation of a Generic Clock that was previously - * configured via a call to \ref system_gclk_chan_set_config(). - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_enable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Enable the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Disables a Generic Clock that was previously enabled. - * - * Stops the clock generation of a Generic Clock that was previously started - * via a call to \ref system_gclk_chan_enable(). - * - * \param[in] channel Generic Clock channel to disable - */ -void system_gclk_chan_disable( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Sanity check WRTLOCK */ - Assert(!GCLK->CLKCTRL.bit.WRTLOCK); - - /* Switch to known-working source so that the channel can be disabled */ - uint32_t prev_gen_id = GCLK->CLKCTRL.bit.GEN; - GCLK->CLKCTRL.bit.GEN = 0; - - /* Disable the generic clock */ - GCLK->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; - while (GCLK->CLKCTRL.reg & GCLK_CLKCTRL_CLKEN) { - /* Wait for clock to become disabled */ - } - - /* Restore previous configured clock generator */ - GCLK->CLKCTRL.bit.GEN = prev_gen_id; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is enabled. - * - * \param[in] channel Generic Clock Channel index - * - * \return The enabled status. - * \retval true The Generic Clock channel is enabled - * \retval false The Generic Clock channel is disabled - */ -bool system_gclk_chan_is_enabled( - const uint8_t channel) -{ - bool enabled; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - enabled = GCLK->CLKCTRL.bit.CLKEN; - - system_interrupt_leave_critical_section(); - - return enabled; -} - -/** - * \brief Locks a Generic Clock channel from further configuration writes. - * - * Locks a generic clock channel from further configuration writes. It is only - * possible to unlock the channel configuration through a power on reset. - * - * \param[in] channel Generic Clock channel to enable - */ -void system_gclk_chan_lock( - const uint8_t channel) -{ - system_interrupt_enter_critical_section(); - - /* Select the requested generator channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - - /* Lock the generic clock */ - GCLK->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK | GCLK_CLKCTRL_CLKEN; - - system_interrupt_leave_critical_section(); -} - -/** - * \brief Determins if the specified Generic Clock channel is locked. - * - * \param[in] channel Generic Clock Channel index - * - * \return The lock status. - * \retval true The Generic Clock channel is locked - * \retval false The Generic Clock channel is not locked - */ -bool system_gclk_chan_is_locked( - const uint8_t channel) -{ - bool locked; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - locked = GCLK->CLKCTRL.bit.WRTLOCK; - - system_interrupt_leave_critical_section(); - - return locked; -} - -/** - * \brief Retrieves the clock frequency of a Generic Clock channel. - * - * Determines the clock frequency (in Hz) of a specified Generic Clock - * channel, used as a source to a device peripheral module. - * - * \param[in] channel Generic Clock Channel index - * - * \return The frequency of the generic clock channel, in Hz. - */ -uint32_t system_gclk_chan_get_hz( - const uint8_t channel) -{ - uint8_t gen_id; - - system_interrupt_enter_critical_section(); - - /* Select the requested generic clock channel */ - *((uint8_t*)&GCLK->CLKCTRL.reg) = channel; - gen_id = GCLK->CLKCTRL.bit.GEN; - - system_interrupt_leave_critical_section(); - - /* Return the clock speed of the associated GCLK generator */ - return system_gclk_gen_get_hz(gen_id); -} diff --git a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/module_config/conf_clocks.h b/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/module_config/conf_clocks.h deleted file mode 100644 index 17357f7cc9bff..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/clock/clock_samd21_r21_da/module_config/conf_clocks.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - * \file - * - * \brief SAM D21/R21/DA0/DA1 Clock configuration - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -#ifndef CONF_CLOCKS_H_INCLUDED -# define CONF_CLOCKS_H_INCLUDED - -/* System clock bus configuration */ -# define CONF_CLOCK_FLASH_WAIT_STATES 0 -# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 - -/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */ -# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1 -# define CONF_CLOCK_OSC8M_ON_DEMAND true -# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ -# define CONF_CLOCK_XOSC_ENABLE false -# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL -# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 -# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true -# define CONF_CLOCK_XOSC_ON_DEMAND true -# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ -# define CONF_CLOCK_XOSC32K_ENABLE false -# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 -# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false -# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false -# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_XOSC32K_ON_DEMAND true -# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ -# define CONF_CLOCK_OSC32K_ENABLE false -# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 -# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ON_DEMAND true -# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ -# define CONF_CLOCK_DFLL_ENABLE false -# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN -# define CONF_CLOCK_DFLL_ON_DEMAND false - -/* DFLL open loop mode configuration */ -# define CONF_CLOCK_DFLL_FINE_VALUE (512) - -/* DFLL closed loop mode configuration */ -# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 -# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR 1465 //(48000000 / 32768) -# define CONF_CLOCK_DFLL_QUICK_LOCK true -# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true -# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true -# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true -# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4) -# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4) - -/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ -# define CONF_CLOCK_DPLL_ENABLE false -# define CONF_CLOCK_DPLL_ON_DEMAND true -# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false -# define CONF_CLOCK_DPLL_LOCK_BYPASS false -# define CONF_CLOCK_DPLL_WAKE_UP_FAST false -# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false - -# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT -# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K -# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT - -# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 -# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 -# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 - -/* DPLL GCLK reference configuration */ -# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 -/* DPLL GCLK lock timer configuration */ -# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 - -/* Set this to true to configure the GCLK when running clocks_init. If set to - * false, none of the GCLK generators will be configured in clocks_init(). */ -# define CONF_CLOCK_CONFIGURE_GCLK true - -/* Configure GCLK generator 0 (Main Clock) */ -# define CONF_CLOCK_GCLK_0_ENABLE true -# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_0_PRESCALER 1 -# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false - -/* Configure GCLK generator 1 */ -# define CONF_CLOCK_GCLK_1_ENABLE false -# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K -# define CONF_CLOCK_GCLK_1_PRESCALER 1 -# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false - -/* Configure GCLK generator 2 (RTC) */ -# define CONF_CLOCK_GCLK_2_ENABLE false -# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K -# define CONF_CLOCK_GCLK_2_PRESCALER 32 -# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false - -/* Configure GCLK generator 3 */ -# define CONF_CLOCK_GCLK_3_ENABLE false -# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_3_PRESCALER 1 -# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false - -/* Configure GCLK generator 4 */ -# define CONF_CLOCK_GCLK_4_ENABLE false -# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_4_PRESCALER 1 -# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false - -/* Configure GCLK generator 5 */ -# define CONF_CLOCK_GCLK_5_ENABLE false -# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_5_PRESCALER 1 -# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false - -/* Configure GCLK generator 6 */ -# define CONF_CLOCK_GCLK_6_ENABLE false -# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_6_PRESCALER 1 -# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false - -/* Configure GCLK generator 7 */ -# define CONF_CLOCK_GCLK_7_ENABLE false -# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_7_PRESCALER 1 -# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false - -/* Configure GCLK generator 8 */ -# define CONF_CLOCK_GCLK_8_ENABLE false -# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_8_PRESCALER 1 -# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false - -#endif /* CONF_CLOCKS_H_INCLUDED */ - diff --git a/atmel-samd/asf/sam0/drivers/system/clock/gclk.h b/atmel-samd/asf/sam0/drivers/system/clock/gclk.h deleted file mode 100644 index ff26eac9ebadc..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/clock/gclk.h +++ /dev/null @@ -1,307 +0,0 @@ -/** - * \file - * - * \brief SAM Generic Clock Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_CLOCK_GCLK_H_INCLUDED -#define SYSTEM_CLOCK_GCLK_H_INCLUDED - -/** - * \addtogroup asfdoc_sam0_system_clock_group - * - * @{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief List of available GCLK generators. - * - * List of Available GCLK generators. This enum is used in the peripheral - * device drivers to select the GCLK generator to be used for its operation. - * - * The number of GCLK generators available is device dependent. - */ -enum gclk_generator { - /** GCLK generator channel 0 */ - GCLK_GENERATOR_0, -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 0) - /** GCLK generator channel 1 */ - GCLK_GENERATOR_1, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 1) - /** GCLK generator channel 2 */ - GCLK_GENERATOR_2, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 2) - /** GCLK generator channel 3 */ - GCLK_GENERATOR_3, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 3) - /** GCLK generator channel 4 */ - GCLK_GENERATOR_4, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 4) - /** GCLK generator channel 5 */ - GCLK_GENERATOR_5, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 5) - /** GCLK generator channel 6 */ - GCLK_GENERATOR_6, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 6) - /** GCLK generator channel 7 */ - GCLK_GENERATOR_7, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 7) - /** GCLK generator channel 8 */ - GCLK_GENERATOR_8, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 8) - /** GCLK generator channel 9 */ - GCLK_GENERATOR_9, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 9) - /** GCLK generator channel 10 */ - GCLK_GENERATOR_10, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 10) - /** GCLK generator channel 11 */ - GCLK_GENERATOR_11, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 11) - /** GCLK generator channel 12 */ - GCLK_GENERATOR_12, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 12) - /** GCLK generator channel 13 */ - GCLK_GENERATOR_13, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 13) - /** GCLK generator channel 14 */ - GCLK_GENERATOR_14, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 14) - /** GCLK generator channel 15 */ - GCLK_GENERATOR_15, -#endif -#if defined(__DOXYGEN__) || (GCLK_GEN_NUM_MSB > 15) - /** GCLK generator channel 16 */ - GCLK_GENERATOR_16, -#endif -}; - -/** - * \brief Generic Clock Generator configuration structure. - * - * Configuration structure for a Generic Clock Generator channel. This - * structure should be initialized by the - * \ref system_gclk_gen_get_config_defaults() function before being modified by - * the user application. - */ -struct system_gclk_gen_config { - /** Source clock input channel index, see the \ref system_clock_source */ - uint8_t source_clock; - /** If \c true, the generator output level is high when disabled */ - bool high_when_disabled; - /** Integer division factor of the clock output compared to the input */ - uint32_t division_factor; - /** If \c true, the clock is kept enabled during device standby mode */ - bool run_in_standby; - /** If \c true, enables GCLK generator clock output to a GPIO pin */ - bool output_enable; -}; - -/** - * \brief Generic Clock configuration structure. - * - * Configuration structure for a Generic Clock channel. This structure - * should be initialized by the \ref system_gclk_chan_get_config_defaults() - * function before being modified by the user application. - */ -struct system_gclk_chan_config { - /** Generic Clock Generator source channel */ - enum gclk_generator source_generator; -}; - -/** \name Generic Clock Management - * @{ - */ -void system_gclk_init(void); - -/** @} */ - - -/** - * \name Generic Clock Management (Generators) - * @{ - */ - -/** - * \brief Initializes a Generic Clock Generator configuration structure to defaults. - * - * Initializes a given Generic Clock Generator configuration structure to - * a set of known default values. This function should be called on all - * new instances of these configuration structures before being modified - * by the user application. - * - * The default configuration is: - * \li The clock is generated undivided from the source frequency - * \li The clock generator output is low when the generator is disabled - * \li The input clock is sourced from input clock channel 0 - * \li The clock will be disabled during sleep - * \li The clock output will not be routed to a physical GPIO pin - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void system_gclk_gen_get_config_defaults( - struct system_gclk_gen_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->division_factor = 1; - config->high_when_disabled = false; -#if SAML21 || SAML22 || SAMR30 - config->source_clock = GCLK_SOURCE_OSC16M; -#elif (SAMC20) || (SAMC21) - config->source_clock = GCLK_SOURCE_OSC48M; -#else - config->source_clock = GCLK_SOURCE_OSC8M; -#endif - config->run_in_standby = false; - config->output_enable = false; -} - -void system_gclk_gen_set_config( - const uint8_t generator, - struct system_gclk_gen_config *const config); - -void system_gclk_gen_enable( - const uint8_t generator); - -void system_gclk_gen_disable( - const uint8_t generator); - -bool system_gclk_gen_is_enabled( - const uint8_t generator); - -/** @} */ - - -/** - * \name Generic Clock Management (Channels) - * @{ - */ - -/** - * \brief Initializes a Generic Clock configuration structure to defaults. - * - * Initializes a given Generic Clock configuration structure to a set of - * known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li The clock is sourced from the Generic Clock Generator channel 0 - * \li The clock configuration will not be write-locked when set - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void system_gclk_chan_get_config_defaults( - struct system_gclk_chan_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->source_generator = GCLK_GENERATOR_0; -} - -void system_gclk_chan_set_config( - const uint8_t channel, - struct system_gclk_chan_config *const config); - -void system_gclk_chan_enable( - const uint8_t channel); - -void system_gclk_chan_disable( - const uint8_t channel); - -bool system_gclk_chan_is_enabled( - const uint8_t channel); - -void system_gclk_chan_lock( - const uint8_t channel); - -bool system_gclk_chan_is_locked( - const uint8_t channel); - -/** @} */ - - -/** - * \name Generic Clock Frequency Retrieval - * @{ - */ - -uint32_t system_gclk_gen_get_hz( - const uint8_t generator); - -uint32_t system_gclk_chan_get_hz( - const uint8_t channel); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** @} */ - -#endif diff --git a/atmel-samd/asf/sam0/drivers/system/docimg/performance_level_transition.svg b/atmel-samd/asf/sam0/drivers/system/docimg/performance_level_transition.svg deleted file mode 100644 index e0c86a6274851..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/docimg/performance_level_transition.svg +++ /dev/null @@ -1,1006 +0,0 @@ - - - - - - - - image/svg+xml - - - - - - - - - diff --git a/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt.c b/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt.c deleted file mode 100644 index 24ee27ffa28c4..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt.c +++ /dev/null @@ -1,217 +0,0 @@ -/** - * \file - * - * \brief SAM System Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include "system_interrupt.h" - -/** - * \brief Check if a interrupt line is pending. - * - * Checks if the requested interrupt vector is pending. - * - * \param[in] vector Interrupt vector number to check - * - * \returns A boolean identifying if the requested interrupt vector is pending. - * - * \retval true Specified interrupt vector is pending - * \retval false Specified interrupt vector is not pending - * - */ -bool system_interrupt_is_pending( - const enum system_interrupt_vector vector) -{ - bool result; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - result = ((NVIC->ISPR[0] & (1 << vector)) != 0); - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - result = ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) != 0); - } else { - Assert(false); - result = false; - } - - return result; -} - -/** - * \brief Set a interrupt vector as pending. - * - * Set the requested interrupt vector as pending (i.e. issues a software - * interrupt request for the specified vector). The software handler will be - * handled (if enabled) in a priority order based on vector number and - * configured priority settings. - * - * \param[in] vector Interrupt vector number which is set as pending - * - * \returns Status code identifying if the vector was successfully set as - * pending. - * - * \retval STATUS_OK If no error was detected - * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given - */ -enum status_code system_interrupt_set_pending( - const enum system_interrupt_vector vector) -{ - enum status_code status = STATUS_OK; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - NVIC->ISPR[0] = (1 << vector); - } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { - /* Note: Because NMI has highest priority it will be executed - * immediately after it has been set pending */ - SCB->ICSR = SCB_ICSR_NMIPENDSET_Msk; - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->ICSR = SCB_ICSR_PENDSTSET_Msk; - } else { - /* The user want to set something unsupported as pending */ - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } - - return status; -} - -/** - * \brief Clear pending interrupt vector. - * - * Clear a pending interrupt vector, so the software handler is not executed. - * - * \param[in] vector Interrupt vector number to clear - * - * \returns A status code identifying if the interrupt pending state was - * successfully cleared. - * - * \retval STATUS_OK If no error was detected - * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given - */ -enum status_code system_interrupt_clear_pending( - const enum system_interrupt_vector vector) -{ - enum status_code status = STATUS_OK; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - NVIC->ICPR[0] = (1 << vector); - } else if (vector == SYSTEM_INTERRUPT_NON_MASKABLE) { - /* Note: Clearing of NMI pending interrupts does not make sense and is - * not supported by the device, as it has the highest priority and will - * always be executed at the moment it is set */ - return STATUS_ERR_INVALID_ARG; - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; - } else { - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } - - return status; -} - -/** - * \brief Set interrupt vector priority level. - * - * Set the priority level of an external interrupt or exception. - * - * \param[in] vector Interrupt vector to change - * \param[in] priority_level New vector priority level to set - * - * \returns Status code indicating if the priority level of the interrupt was - * successfully set. - * - * \retval STATUS_OK If no error was detected - * \retval STATUS_INVALID_ARG If an unsupported interrupt vector number was given - */ -enum status_code system_interrupt_set_priority( - const enum system_interrupt_vector vector, - const enum system_interrupt_priority_level priority_level) -{ - enum status_code status = STATUS_OK; - - if (vector >= _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START) { - uint8_t register_num = vector / 4; - uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); - - NVIC->IP[register_num] = - (NVIC->IP[register_num] & ~(_SYSTEM_INTERRUPT_PRIORITY_MASK << priority_pos)) | - (priority_level << priority_pos); - - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - SCB->SHP[1] = (priority_level << _SYSTEM_INTERRUPT_SYSTICK_PRI_POS); - } else { - Assert(false); - status = STATUS_ERR_INVALID_ARG; - } - - return status; -} - -/** - * \brief Get interrupt vector priority level. - * - * Retrieves the priority level of the requested external interrupt or exception. - * - * \param[in] vector Interrupt vector of which the priority level will be read - * - * \return Currently configured interrupt priority level of the given interrupt - * vector. - */ -enum system_interrupt_priority_level system_interrupt_get_priority( - const enum system_interrupt_vector vector) -{ - uint8_t register_num = vector / 4; - uint8_t priority_pos = ((vector % 4) * 8) + (8 - __NVIC_PRIO_BITS); - - enum system_interrupt_priority_level priority = SYSTEM_INTERRUPT_PRIORITY_LEVEL_0; - - if (vector >= 0) { - priority = (enum system_interrupt_priority_level) - ((NVIC->IP[register_num] >> priority_pos) & _SYSTEM_INTERRUPT_PRIORITY_MASK); - } else if (vector == SYSTEM_INTERRUPT_SYSTICK) { - priority = (enum system_interrupt_priority_level) - ((SCB->SHP[1] >> _SYSTEM_INTERRUPT_SYSTICK_PRI_POS) & _SYSTEM_INTERRUPT_PRIORITY_MASK); - } - - return priority; -} - diff --git a/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt.h b/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt.h deleted file mode 100644 index 0b7834369ca6d..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt.h +++ /dev/null @@ -1,429 +0,0 @@ -/** - * \file - * - * \brief SAM System Interrupt Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_INTERRUPT_H_INCLUDED -#define SYSTEM_INTERRUPT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_interrupt_group SAM System Interrupt (SYSTEM INTERRUPT) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of internal software and - * hardware interrupts/exceptions. - * - * The following peripheral is used by this module: - * - NVIC (Nested Vector Interrupt Controller) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_interrupt_prerequisites - * - \ref asfdoc_sam0_system_interrupt_module_overview - * - \ref asfdoc_sam0_system_interrupt_special_considerations - * - \ref asfdoc_sam0_system_interrupt_extra_info - * - \ref asfdoc_sam0_system_interrupt_examples - * - \ref asfdoc_sam0_system_interrupt_api_overview - * - * - * \section asfdoc_sam0_system_interrupt_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_interrupt_module_overview Module Overview - * - * The ARM® Cortex® M0+ core contains an interrupt and exception vector table, which - * can be used to configure the device's interrupt handlers; individual - * interrupts and exceptions can be enabled and disabled, as well as configured - * with a variable priority. - * - * This driver provides a set of wrappers around the core interrupt functions, - * to expose a simple API for the management of global and individual interrupts - * within the device. - * - * \subsection asfdoc_sam0_system_interrupt_module_overview_criticalsec Critical Sections - * In some applications it is important to ensure that no interrupts may be - * executed by the system whilst a critical portion of code is being run; for - * example, a buffer may be copied from one context to another - during which - * interrupts must be disabled to avoid corruption of the source buffer contents - * until the copy has completed. This driver provides a basic API to enter and - * exit nested critical sections, so that global interrupts can be kept disabled - * for as long as necessary to complete a critical application code section. - * - * \subsection asfdoc_sam0_system_interrupt_module_overview_softints Software Interrupts - * For some applications, it may be desirable to raise a module or core - * interrupt via software. For this reason, a set of APIs to set an interrupt or - * exception as pending are provided to the user application. - * - * \section asfdoc_sam0_system_interrupt_special_considerations Special Considerations - * - * Interrupts from peripherals in the SAM devices are on a per-module basis; - * an interrupt raised from any source within a module will cause a single, - * module-common handler to execute. It is the user application or driver's - * responsibility to de-multiplex the module-common interrupt to determine the - * exact interrupt cause. - * - * \section asfdoc_sam0_system_interrupt_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_interrupt_extra. This includes: - * - \ref asfdoc_sam0_system_interrupt_extra_acronyms - * - \ref asfdoc_sam0_system_interrupt_extra_dependencies - * - \ref asfdoc_sam0_system_interrupt_extra_errata - * - \ref asfdoc_sam0_system_interrupt_extra_history - * - * - * \section asfdoc_sam0_system_interrupt_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_interrupt_exqsg. - * - * \section asfdoc_sam0_system_interrupt_api_overview API Overview - * @{ - */ - -#include -#include -#include "system_interrupt_features.h" - -/** - * \brief Table of possible system interrupt/exception vector priorities. - * - * Table of all possible interrupt and exception vector priorities within the - * device. - */ -enum system_interrupt_priority_level { - /** Priority level 0, the highest possible interrupt priority */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_0 = 0, - /** Priority level 1 */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_1 = 1, - /** Priority level 2 */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_2 = 2, - /** Priority level 3, the lowest possible interrupt priority */ - SYSTEM_INTERRUPT_PRIORITY_LEVEL_3 = 3, -}; - -/** - * \name Critical Section Management - * @{ - */ - -/** - * \brief Enters a critical section. - * - * Disables global interrupts. To support nested critical sections, an internal - * count of the critical section nesting will be kept, so that global interrupts - * are only re-enabled upon leaving the outermost nested critical section. - * - */ -static inline void system_interrupt_enter_critical_section(void) -{ - cpu_irq_enter_critical(); -} - -/** - * \brief Leaves a critical section. - * - * Enables global interrupts. To support nested critical sections, an internal - * count of the critical section nesting will be kept, so that global interrupts - * are only re-enabled upon leaving the outermost nested critical section. - * - */ -static inline void system_interrupt_leave_critical_section(void) -{ - cpu_irq_leave_critical(); -} - -/** @} */ - -/** - * \name Interrupt Enabling/Disabling - * @{ - */ - -/** - * \brief Check if global interrupts are enabled. - * - * Checks if global interrupts are currently enabled. - * - * \returns A boolean that identifies if the global interrupts are enabled or not. - * - * \retval true Global interrupts are currently enabled - * \retval false Global interrupts are currently disabled - * - */ -static inline bool system_interrupt_is_global_enabled(void) -{ - return cpu_irq_is_enabled(); -} - -/** - * \brief Enables global interrupts. - * - * Enables global interrupts in the device to fire any enabled interrupt handlers. - */ -static inline void system_interrupt_enable_global(void) -{ - cpu_irq_enable(); -} - -/** - * \brief Disables global interrupts. - * - * Disabled global interrupts in the device, preventing any enabled interrupt - * handlers from executing. - */ -static inline void system_interrupt_disable_global(void) -{ - cpu_irq_disable(); -} - -/** - * \brief Checks if an interrupt vector is enabled or not. - * - * Checks if a specific interrupt vector is currently enabled. - * - * \param[in] vector Interrupt vector number to check - * - * \returns A variable identifying if the requested interrupt vector is enabled. - * - * \retval true Specified interrupt vector is currently enabled - * \retval false Specified interrupt vector is currently disabled - * - */ -static inline bool system_interrupt_is_enabled( - const enum system_interrupt_vector vector) -{ - return (bool)((NVIC->ISER[0] >> (uint32_t)vector) & 0x00000001); -} - -/** - * \brief Enable interrupt vector. - * - * Enables execution of the software handler for the requested interrupt vector. - * - * \param[in] vector Interrupt vector to enable - */ -static inline void system_interrupt_enable( - const enum system_interrupt_vector vector) -{ - NVIC->ISER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); -} - -/** - * \brief Disable interrupt vector. - * - * Disables execution of the software handler for the requested interrupt vector. - * - * \param[in] vector Interrupt vector to disable - */ -static inline void system_interrupt_disable( - const enum system_interrupt_vector vector) -{ - NVIC->ICER[0] = (uint32_t)(1 << ((uint32_t)vector & 0x0000001f)); -} - -/** @} */ - -/** - * \name Interrupt State Management - * @{ - */ - -/** - * \brief Get active interrupt (if any). - * - * Return the vector number for the current executing software handler, if any. - * - * \return Interrupt number that is currently executing. - */ -static inline enum system_interrupt_vector system_interrupt_get_active(void) -{ - uint32_t IPSR = __get_IPSR(); - /* The IPSR returns the Exception number, which with an offset 16 to IRQ number. */ - return (enum system_interrupt_vector)((IPSR & _SYSTEM_INTERRUPT_IPSR_MASK) - 16); -} - -bool system_interrupt_is_pending( - const enum system_interrupt_vector vector); - -enum status_code system_interrupt_set_pending( - const enum system_interrupt_vector vector); - -enum status_code system_interrupt_clear_pending( - const enum system_interrupt_vector vector); - -/** @} */ - -/** - * \name Interrupt Priority Management - * @{ - */ - -enum status_code system_interrupt_set_priority( - const enum system_interrupt_vector vector, - const enum system_interrupt_priority_level priority_level); - -enum system_interrupt_priority_level system_interrupt_get_priority( - const enum system_interrupt_vector vector); - -/** @} */ - -/** @} */ - -/** - * \page asfdoc_sam0_system_interrupt_extra Extra Information for SYSTEM INTERRUPT Driver - * - * \section asfdoc_sam0_system_interrupt_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
ISRInterrupt Service Routine
NMINon-maskable Interrupt
SERCOMSerial Communication Interface
- * - * - * \section asfdoc_sam0_system_interrupt_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_interrupt_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_system_interrupt_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - *
Changelog
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_interrupt_exqsg Examples for SYSTEM INTERRUPT Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_interrupt_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_system_interrupt_critsec_use_case - * - \subpage asfdoc_sam0_system_interrupt_enablemodint_use_case - * - * \page asfdoc_sam0_system_interrupt_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42122E12/2015Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21
42122D12/2014Added support for SAM R21 and SAM D10/D11
42122C01/2014Added support for SAM D21
42122B06/2013Corrected documentation typos
42122A06/2013Initial release
- */ - -#ifdef __cplusplus -} -#endif - -#endif // #ifndef SYSTEM_INTERRUPT_H_INCLUDED diff --git a/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h b/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h deleted file mode 100644 index 25dfa838db747..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/interrupt/system_interrupt_samd21/system_interrupt_features.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - * \file - * - * \brief SAM D21 System Interrupt Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef SYSTEM_INTERRUPT_FEATURES_H_INCLUDED -#define SYSTEM_INTERRUPT_FEATURES_H_INCLUDED - -#if !defined(__DOXYGEN__) - -/* Generates a interrupt vector table enum list entry for a given module type - and index (e.g. "SYSTEM_INTERRUPT_MODULE_TC0 = TC0_IRQn,"). */ -# define _MODULE_IRQn(n, module) \ - SYSTEM_INTERRUPT_MODULE_##module##n = module##n##_IRQn, - -/* Generates interrupt vector table enum list entries for all instances of a - given module type on the selected device. */ -# define _SYSTEM_INTERRUPT_MODULES(name) \ - MREPEAT(name##_INST_NUM, _MODULE_IRQn, name) - -# define _SYSTEM_INTERRUPT_IPSR_MASK 0x0000003f -# define _SYSTEM_INTERRUPT_PRIORITY_MASK 0x00000003 - -# define _SYSTEM_INTERRUPT_EXTERNAL_VECTOR_START 0 - -# define _SYSTEM_INTERRUPT_SYSTICK_PRI_POS 30 -#endif - -/** - * \addtogroup asfdoc_sam0_system_interrupt_group - * @{ - */ - -/** - * \brief Table of possible system interrupt/exception vector numbers. - * - * Table of all possible interrupt and exception vector indexes within the - * SAM D21 device. Check peripherals configuration in SAM D21 datasheet for - * available vector index for specific device. - * - */ -#if defined(__DOXYGEN__) -/** \note The actual enumeration name is "system_interrupt_vector". */ -enum system_interrupt_vector_samd21 { -#else -enum system_interrupt_vector { -#endif - /** Interrupt vector index for a NMI interrupt */ - SYSTEM_INTERRUPT_NON_MASKABLE = NonMaskableInt_IRQn, - /** Interrupt vector index for a Hard Fault memory access exception */ - SYSTEM_INTERRUPT_HARD_FAULT = HardFault_IRQn, - /** Interrupt vector index for a Supervisor Call exception */ - SYSTEM_INTERRUPT_SV_CALL = SVCall_IRQn, - /** Interrupt vector index for a Pending Supervisor interrupt */ - SYSTEM_INTERRUPT_PENDING_SV = PendSV_IRQn, - /** Interrupt vector index for a System Tick interrupt */ - SYSTEM_INTERRUPT_SYSTICK = SysTick_IRQn, - - /** Interrupt vector index for a Power Manager peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_PM = PM_IRQn, - /** Interrupt vector index for a System Control peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_SYSCTRL = SYSCTRL_IRQn, - /** Interrupt vector index for a Watch Dog peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_WDT = WDT_IRQn, - /** Interrupt vector index for a Real Time Clock peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_RTC = RTC_IRQn, - /** Interrupt vector index for an External Interrupt peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_EIC = EIC_IRQn, - /** Interrupt vector index for a Non Volatile Memory Controller interrupt */ - SYSTEM_INTERRUPT_MODULE_NVMCTRL = NVMCTRL_IRQn, - /** Interrupt vector index for a Direct Memory Access interrupt */ - SYSTEM_INTERRUPT_MODULE_DMA = DMAC_IRQn, -#if defined(__DOXYGEN__) || defined(ID_USB) - /** Interrupt vector index for a Universal Serial Bus interrupt */ - SYSTEM_INTERRUPT_MODULE_USB = USB_IRQn, -#endif - /** Interrupt vector index for an Event System interrupt */ - SYSTEM_INTERRUPT_MODULE_EVSYS = EVSYS_IRQn, -#if defined(__DOXYGEN__) - /** Interrupt vector index for a SERCOM peripheral interrupt. - * - * Each specific device may contain several SERCOM peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_SERCOM0). - */ - SYSTEM_INTERRUPT_MODULE_SERCOMn = SERCOMn_IRQn, - - /** Interrupt vector index for a Timer/Counter Control peripheral interrupt. - * - * Each specific device may contain several TCC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TCC0). - */ - SYSTEM_INTERRUPT_MODULE_TCCn = TCCn_IRQn, - - /** Interrupt vector index for a Timer/Counter peripheral interrupt. - * - * Each specific device may contain several TC peripherals; each module - * instance will have its own entry in the table, with the instance number - * substituted for "n" in the entry name (e.g. - * \c SYSTEM_INTERRUPT_MODULE_TC3). - */ - SYSTEM_INTERRUPT_MODULE_TCn = TCn_IRQn, -#else - _SYSTEM_INTERRUPT_MODULES(SERCOM) - - _SYSTEM_INTERRUPT_MODULES(TCC) - - SYSTEM_INTERRUPT_MODULE_TC3 = TC3_IRQn, - SYSTEM_INTERRUPT_MODULE_TC4 = TC4_IRQn, - SYSTEM_INTERRUPT_MODULE_TC5 = TC5_IRQn, -# if defined(ID_TC6) - SYSTEM_INTERRUPT_MODULE_TC6 = TC6_IRQn, -# endif -# if defined(ID_TC7) - SYSTEM_INTERRUPT_MODULE_TC7 = TC7_IRQn, -# endif -#endif - -#if defined(__DOXYGEN__) || defined(ID_ADC) - /** Interrupt vector index for an Analog-to-Digital peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_ADC = ADC_IRQn, -#endif - -#if defined(__DOXYGEN__) || defined(ID_AC) - /** Interrupt vector index for an Analog Comparator peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_AC = AC_IRQn, -#endif - -#if defined(__DOXYGEN__) || defined(ID_DAC) - /** Interrupt vector index for a Digital-to-Analog peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_DAC = DAC_IRQn, -#endif -#if defined(__DOXYGEN__) || defined(ID_PTC) - /** Interrupt vector index for a Peripheral Touch Controller peripheral - * interrupt */ - SYSTEM_INTERRUPT_MODULE_PTC = PTC_IRQn, -#endif -#if defined(__DOXYGEN__) || defined(ID_I2S) - /** Interrupt vector index for a Inter-IC Sound Interface peripheral - * interrupt */ - SYSTEM_INTERRUPT_MODULE_I2S = I2S_IRQn, -#endif -#if defined(__DOXYGEN__) || defined(ID_AC1) - /** Interrupt vector index for an Analog Comparator 1 peripheral interrupt */ - SYSTEM_INTERRUPT_MODULE_AC1 = AC1_IRQn, -#endif -}; - -/** @} */ - -#endif diff --git a/atmel-samd/asf/sam0/drivers/system/pinmux/pinmux.c b/atmel-samd/asf/sam0/drivers/system/pinmux/pinmux.c deleted file mode 100644 index a2c9c7cdcc752..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/pinmux/pinmux.c +++ /dev/null @@ -1,311 +0,0 @@ -/** - * \file - * - * \brief SAM Pin Multiplexer Driver - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -/** - * \internal - * Writes out a given configuration of a Port pin configuration to the - * hardware module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] port Base of the PORT module to configure - * \param[in] pin_mask Mask of the port pin to configure - * \param[in] config Configuration settings for the pin - */ -static void _system_pinmux_config( - PortGroup *const port, - const uint32_t pin_mask, - const struct system_pinmux_config *const config) -{ - Assert(port); - Assert(config); - - /* Track the configuration bits into a temporary variable before writing */ - uint32_t pin_cfg = 0; - - /* Enabled powersave mode, don't create configuration */ - if (!config->powersave) { - /* Enable the pin peripheral MUX flag if non-GPIO selected (pinmux will - * be written later) and store the new MUX mask */ - if (config->mux_position != SYSTEM_PINMUX_GPIO) { - pin_cfg |= PORT_WRCONFIG_PMUXEN; - pin_cfg |= (config->mux_position << PORT_WRCONFIG_PMUX_Pos); - } - - /* Check if the user has requested that the input buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_INPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Enable input buffer flag */ - pin_cfg |= PORT_WRCONFIG_INEN; - - /* Enable pull-up/pull-down control flag if requested */ - if (config->input_pull != SYSTEM_PINMUX_PIN_PULL_NONE) { - pin_cfg |= PORT_WRCONFIG_PULLEN; - } - - /* Clear the port DIR bits to disable the output buffer */ - port->DIRCLR.reg = pin_mask; - } - - /* Check if the user has requested that the output buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Cannot use a pull-up if the output driver is enabled, - * if requested the input buffer can only sample the current - * output state */ - pin_cfg &= ~PORT_WRCONFIG_PULLEN; - } - } else { - port->DIRCLR.reg = pin_mask; - } - - /* The Write Configuration register (WRCONFIG) requires the - * pins to to grouped into two 16-bit half-words - split them out here */ - uint32_t lower_pin_mask = (pin_mask & 0xFFFF); - uint32_t upper_pin_mask = (pin_mask >> 16); - - /* Configure the lower 16-bits of the port to the desired configuration, - * including the pin peripheral multiplexer just in case it is enabled */ - port->WRCONFIG.reg - = (lower_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | - pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG; - - /* Configure the upper 16-bits of the port to the desired configuration, - * including the pin peripheral multiplexer just in case it is enabled */ - port->WRCONFIG.reg - = (upper_pin_mask << PORT_WRCONFIG_PINMASK_Pos) | - pin_cfg | PORT_WRCONFIG_WRPMUX | PORT_WRCONFIG_WRPINCFG | - PORT_WRCONFIG_HWSEL; - - if(!config->powersave) { - /* Set the pull-up state once the port pins are configured if one was - * requested and it does not violate the valid set of port - * configurations */ - if (pin_cfg & PORT_WRCONFIG_PULLEN) { - /* Set the OUT register bits to enable the pull-up if requested, - * clear to enable pull-down */ - if (config->input_pull == SYSTEM_PINMUX_PIN_PULL_UP) { - port->OUTSET.reg = pin_mask; - } else { - port->OUTCLR.reg = pin_mask; - } - } - - /* Check if the user has requested that the output buffer be enabled */ - if ((config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT) || - (config->direction == SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK)) { - /* Set the port DIR bits to enable the output buffer */ - port->DIRSET.reg = pin_mask; - } - } -} - -/** - * \brief Writes a Port pin configuration to the hardware module. - * - * Writes out a given configuration of a Port pin configuration to the hardware - * module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] config Configuration settings for the pin - */ -void system_pinmux_pin_set_config( - const uint8_t gpio_pin, - const struct system_pinmux_config *const config) -{ - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_mask = (1UL << (gpio_pin % 32)); - - _system_pinmux_config(port, pin_mask, config); -} - -/** - * \brief Writes a Port pin group configuration to the hardware module. - * - * Writes out a given configuration of a Port pin group configuration to the - * hardware module. - * - * \note If the pin direction is set as an output, the pull-up/pull-down input - * configuration setting is ignored. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] config Configuration settings for the pin - */ -void system_pinmux_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct system_pinmux_config *const config) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - _system_pinmux_config(port, (1UL << i), config); - } - } -} - -/** - * \brief Configures the input sampling mode for a group of pins. - * - * Configures the input sampling mode for a group of pins, to - * control when the physical I/O pin value is sampled and - * stored inside the microcontroller. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New pin sampling mode to configure - */ -void system_pinmux_group_set_input_sample_mode( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_sample mode) -{ - Assert(port); - - if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { - port->CTRL.reg |= mask; - } else { - port->CTRL.reg &= ~mask; - } -} - -#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER -/** - * \brief Configures the output slew rate mode for a group of pins. - * - * Configures the output slew rate mode for a group of pins, to - * control the speed at which the physical output pin can react to - * logical changes of the I/O pin value. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New pin slew rate mode to configure - */ -void system_pinmux_group_set_output_slew_rate( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_slew_rate mode) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { - port->PINCFG[i].reg |= PORT_PINCFG_SLEWLIM; - } else { - port->PINCFG[i].reg &= ~PORT_PINCFG_SLEWLIM; - } - } - } -} -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH -/** - * \brief Configures the output driver strength mode for a group of pins. - * - * Configures the output drive strength for a group of pins, to - * control the amount of current the pad is able to sink/source. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New output driver strength mode to configure - */ -void system_pinmux_group_set_output_strength( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_strength mode) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { - port->PINCFG[i].reg |= PORT_PINCFG_DRVSTR; - } else { - port->PINCFG[i].reg &= ~PORT_PINCFG_DRVSTR; - } - } - } -} -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN -/** - * \brief Configures the output driver mode for a group of pins. - * - * Configures the output driver mode for a group of pins, to - * control the pad behavior. - * - * \param[in] port Base of the PORT module to configure - * \param[in] mask Mask of the port pin(s) to configure - * \param[in] mode New pad output driver mode to configure - */ -void system_pinmux_group_set_output_drive( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_drive mode) -{ - Assert(port); - - for (int i = 0; i < 32; i++) { - if (mask & (1UL << i)) { - if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { - port->PINCFG[i].reg |= PORT_PINCFG_ODRAIN; - } else { - port->PINCFG[i].reg &= ~PORT_PINCFG_ODRAIN; - } - } - } -} -#endif diff --git a/atmel-samd/asf/sam0/drivers/system/pinmux/pinmux.h b/atmel-samd/asf/sam0/drivers/system/pinmux/pinmux.h deleted file mode 100644 index 015389c3fed45..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/pinmux/pinmux.h +++ /dev/null @@ -1,675 +0,0 @@ -/** - * \file - * - * \brief SAM Pin Multiplexer Driver - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef PINMUX_H_INCLUDED -#define PINMUX_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_system_pinmux_group SAM System Pin Multiplexer (SYSTEM PINMUX) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides - * an interface for the configuration and management of the device's physical - * I/O Pins, to alter the direction and input/drive characteristics as well as - * to configure the pin peripheral multiplexer selection. - * - * The following peripheral is used by this module: - * - PORT (Port I/O Management) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_pinmux_prerequisites - * - \ref asfdoc_sam0_system_pinmux_module_overview - * - \ref asfdoc_sam0_system_pinmux_special_considerations - * - \ref asfdoc_sam0_system_pinmux_extra_info - * - \ref asfdoc_sam0_system_pinmux_examples - * - \ref asfdoc_sam0_system_pinmux_api_overview - * - * - * \section asfdoc_sam0_system_pinmux_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_pinmux_module_overview Module Overview - * - * The SAM devices contain a number of General Purpose I/O pins, used to - * interface the user application logic and internal hardware peripherals to - * an external system. The Pin Multiplexer (PINMUX) driver provides a method - * of configuring the individual pin peripheral multiplexers to select - * alternate pin functions. - * - * \subsection asfdoc_sam0_system_pinmux_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTHSAM L21, SAM C20/C21
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_system_pinmux_physical_logical_pins Physical and Logical GPIO Pins - * SAM devices use two naming conventions for the I/O pins in the device; one - * physical and one logical. Each physical pin on a device package is assigned - * both a physical port and pin identifier (e.g. "PORTA.0") as well as a - * monotonically incrementing logical GPIO number (e.g. "GPIO0"). While the - * former is used to map physical pins to their physical internal device module - * counterparts, for simplicity the design of this driver uses the logical GPIO - * numbers instead. - * - * \subsection asfdoc_sam0_system_pinmux_peripheral_muxing Peripheral Multiplexing - * SAM devices contain a peripheral MUX, which is individually controllable - * for each I/O pin of the device. The peripheral MUX allows you to select the - * function of a physical package pin - whether it will be controlled as a user - * controllable GPIO pin, or whether it will be connected internally to one of - * several peripheral modules (such as an I2C module). When a pin is - * configured in GPIO mode, other peripherals connected to the same pin will be - * disabled. - * - * \subsection asfdoc_sam0_system_pinmux_pad_characteristics Special Pad Characteristics - * There are several special modes that can be selected on one or more I/O pins - * of the device, which alter the input and output characteristics of the pad. - * - * \subsubsection asfdoc_sam0_system_pinmux_drive_strength Drive Strength - * The Drive Strength configures the strength of the output driver on the - * pad. Normally, there is a fixed current limit that each I/O pin can safely - * drive, however some I/O pads offer a higher drive mode which increases this - * limit for that I/O pin at the expense of an increased power consumption. - * - * \subsubsection asfdoc_sam0_system_pinmux_slew_rate Slew Rate - * The Slew Rate configures the slew rate of the output driver, limiting the - * rate at which the pad output voltage can change with time. - * - * \subsubsection asfdoc_sam0_system_pinmux_input_sample_mode Input Sample Mode - * The Input Sample Mode configures the input sampler buffer of the pad. By - * default, the input buffer is only sampled "on-demand", i.e. when the user - * application attempts to read from the input buffer. This mode is the most - * power efficient, but increases the latency of the input sample by two clock - * cycles of the port clock. To reduce latency, the input sampler can instead - * be configured to always sample the input buffer on each port clock cycle, at - * the expense of an increased power consumption. - * - * \subsection asfdoc_sam0_system_pinmux_module_overview_physical Physical Connection - * - * \ref asfdoc_sam0_system_pinmux_intconnections "The diagram below" shows - * how this module is interconnected within the device: - * - * \anchor asfdoc_sam0_system_pinmux_intconnections - * \dot - * digraph overview { - * node [label="Port Pad" shape=square] pad; - * - * subgraph driver { - * node [label="Peripheral MUX" shape=trapezium] pinmux; - * node [label="GPIO Module" shape=ellipse shape=ellipse style=filled fillcolor=lightgray] gpio; - * node [label="Other Peripheral Modules" shape=ellipse style=filled fillcolor=lightgray] peripherals; - * } - * - * pinmux -> gpio; - * pad -> pinmux; - * pinmux -> peripherals; - * } - * \enddot - * - * \section asfdoc_sam0_system_pinmux_special_considerations Special Considerations - * - * The SAM port pin input sampling mode is set in groups of four physical - * pins; setting the sampling mode of any pin in a sub-group of eight I/O pins - * will configure the sampling mode of the entire sub-group. - * - * High Drive Strength output driver mode is not available on all device pins - - * refer to your device specific datasheet. - * - * - * \section asfdoc_sam0_system_pinmux_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_pinmux_extra. This includes: - * - \ref asfdoc_sam0_system_pinmux_extra_acronyms - * - \ref asfdoc_sam0_system_pinmux_extra_dependencies - * - \ref asfdoc_sam0_system_pinmux_extra_errata - * - \ref asfdoc_sam0_system_pinmux_extra_history - * - * - * \section asfdoc_sam0_system_pinmux_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_system_pinmux_exqsg. - * - * - * \section asfdoc_sam0_system_pinmux_api_overview API Overview - * @{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*@{*/ -#if (SAML21) || (SAMC20) || (SAMC21) || (SAMD21) || (SAMD10) || (SAMD11) || (SAMR30) || defined(__DOXYGEN__) -/** Output Driver Strength Selection feature support */ -# define FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH -#endif -/*@}*/ - -/** Peripheral multiplexer index to select GPIO mode for a pin */ -#define SYSTEM_PINMUX_GPIO (1 << 7) - -/** - * \brief Port pin direction configuration enum. - * - * Enum for the possible pin direction settings of the port pin configuration - * structure, to indicate the direction the pin should use. - */ -enum system_pinmux_pin_dir { - /** The pin's input buffer should be enabled, so that the pin state can - * be read */ - SYSTEM_PINMUX_PIN_DIR_INPUT, - /** The pin's output buffer should be enabled, so that the pin state can - * be set (but not read back) */ - SYSTEM_PINMUX_PIN_DIR_OUTPUT, - /** The pin's output and input buffers should both be enabled, so that the - * pin state can be set and read back */ - SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK, -}; - -/** - * \brief Port pin input pull configuration enum. - * - * Enum for the possible pin pull settings of the port pin configuration - * structure, to indicate the type of logic level pull the pin should use. - */ -enum system_pinmux_pin_pull { - /** No logical pull should be applied to the pin */ - SYSTEM_PINMUX_PIN_PULL_NONE, - /** Pin should be pulled up when idle */ - SYSTEM_PINMUX_PIN_PULL_UP, - /** Pin should be pulled down when idle */ - SYSTEM_PINMUX_PIN_PULL_DOWN, -}; - -/** - * \brief Port pin digital input sampling mode enum. - * - * Enum for the possible input sampling modes for the port pin configuration - * structure, to indicate the type of sampling a port pin should use. - */ -enum system_pinmux_pin_sample { - /** Pin input buffer should continuously sample the pin state */ - SYSTEM_PINMUX_PIN_SAMPLE_CONTINUOUS, - /** Pin input buffer should be enabled when the IN register is read */ - SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND, -}; - -/** - * \brief Port pin configuration structure. - * - * Configuration structure for a port pin instance. This structure should - * be initialized by the \ref system_pinmux_get_config_defaults() function - * before being modified by the user application. - */ -struct system_pinmux_config { - /** MUX index of the peripheral that should control the pin, if peripheral - * control is desired. For GPIO use, this should be set to - * \ref SYSTEM_PINMUX_GPIO. */ - uint8_t mux_position; - - /** Port buffer input/output direction */ - enum system_pinmux_pin_dir direction; - - /** Logic level pull of the input buffer */ - enum system_pinmux_pin_pull input_pull; - - /** Enable lowest possible powerstate on the pin - * - * \note All other configurations will be ignored, the pin will be disabled. - */ - bool powersave; -}; - -/** \name Configuration and Initialization - * @{ - */ - -/** - * \brief Initializes a Port pin configuration structure to defaults. - * - * Initializes a given Port pin configuration structure to a set of - * known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li Non peripheral (i.e. GPIO) controlled - * \li Input mode with internal pull-up enabled - * - * \param[out] config Configuration structure to initialize to default values - */ -static inline void system_pinmux_get_config_defaults( - struct system_pinmux_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Default configuration values */ - config->mux_position = SYSTEM_PINMUX_GPIO; - config->direction = SYSTEM_PINMUX_PIN_DIR_INPUT; - config->input_pull = SYSTEM_PINMUX_PIN_PULL_UP; - config->powersave = false; -} - -void system_pinmux_pin_set_config( - const uint8_t gpio_pin, - const struct system_pinmux_config *const config); - -void system_pinmux_group_set_config( - PortGroup *const port, - const uint32_t mask, - const struct system_pinmux_config *const config); - -/** @} */ - -/** \name Special Mode Configuration (Physical Group Orientated) - * @{ - */ - -/** - * \brief Retrieves the PORT module group instance from a given GPIO pin number. - * - * Retrieves the PORT module group instance associated with a given logical - * GPIO pin number. - * - * \param[in] gpio_pin Index of the GPIO pin to convert - * - * \return Base address of the associated PORT module. - */ -static inline PortGroup* system_pinmux_get_group_from_gpio_pin( - const uint8_t gpio_pin) -{ - uint8_t port_index = (gpio_pin / 128); - uint8_t group_index = (gpio_pin / 32); - - /* Array of available ports */ - Port *const ports[PORT_INST_NUM] = PORT_INSTS; - - if (port_index < PORT_INST_NUM) { - return &(ports[port_index]->Group[group_index]); - } else { - Assert(false); - return NULL; - } -} - -void system_pinmux_group_set_input_sample_mode( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_sample mode); - -/** @} */ - -/** \name Special Mode Configuration (Logical Pin Orientated) - * @{ - */ - -/** - * \brief Retrieves the currently selected MUX position of a logical pin. - * - * Retrieves the selected MUX peripheral on a given logical GPIO pin. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * - * \return Currently selected peripheral index on the specified pin. - */ -static inline uint8_t system_pinmux_pin_get_mux_position( - const uint8_t gpio_pin) -{ - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (!(port->PINCFG[pin_index].reg & PORT_PINCFG_PMUXEN)) { - return SYSTEM_PINMUX_GPIO; - } - - uint32_t pmux_reg = port->PMUX[pin_index / 2].reg; - - if (pin_index & 1) { - return (pmux_reg & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - } - else { - return (pmux_reg & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - } -} - -/** - * \brief Configures the input sampling mode for a GPIO pin. - * - * Configures the input sampling mode for a GPIO input, to - * control when the physical I/O pin value is sampled and - * stored inside the microcontroller. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New pin sampling mode to configure - */ -static inline void system_pinmux_pin_set_input_sample_mode( - const uint8_t gpio_pin, - const enum system_pinmux_pin_sample mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_SAMPLE_ONDEMAND) { - port->CTRL.reg |= (1 << pin_index); - } else { - port->CTRL.reg &= ~(1 << pin_index); - } -} - -/** @} */ - -#ifdef FEATURE_SYSTEM_PINMUX_DRIVE_STRENGTH -/** - * \brief Port pin drive output strength enum. - * - * Enum for the possible output drive strengths for the port pin - * configuration structure, to indicate the driver strength the pin should - * use. - */ -enum system_pinmux_pin_strength { - /** Normal output driver strength */ - SYSTEM_PINMUX_PIN_STRENGTH_NORMAL, - /** High current output driver strength */ - SYSTEM_PINMUX_PIN_STRENGTH_HIGH, -}; - -/** - * \brief Configures the output driver strength mode for a GPIO pin. - * - * Configures the output drive strength for a GPIO output, to - * control the amount of current the pad is able to sink/source. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New output driver strength mode to configure - */ -static inline void system_pinmux_pin_set_output_strength( - const uint8_t gpio_pin, - const enum system_pinmux_pin_strength mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_STRENGTH_HIGH) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_DRVSTR; - } - else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_DRVSTR; - } -} - -void system_pinmux_group_set_output_strength( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_strength mode); -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_SLEWRATE_LIMITER -/** - * \brief Port pin output slew rate enum. - * - * Enum for the possible output drive slew rates for the port pin - * configuration structure, to indicate the driver slew rate the pin should - * use. - */ -enum system_pinmux_pin_slew_rate { - /** Normal pin output slew rate */ - SYSTEM_PINMUX_PIN_SLEW_RATE_NORMAL, - /** Enable slew rate limiter on the pin */ - SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED, -}; - -/** - * \brief Configures the output slew rate mode for a GPIO pin. - * - * Configures the output slew rate mode for a GPIO output, to - * control the speed at which the physical output pin can react to - * logical changes of the I/O pin value. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New pin slew rate mode to configure - */ -static inline void system_pinmux_pin_set_output_slew_rate( - const uint8_t gpio_pin, - const enum system_pinmux_pin_slew_rate mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_SLEW_RATE_LIMITED) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_SLEWLIM; - } - else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_SLEWLIM; - } -} - -void system_pinmux_group_set_output_slew_rate( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_slew_rate mode); -#endif - -#ifdef FEATURE_SYSTEM_PINMUX_OPEN_DRAIN -/** - * \brief Port pin output drive mode enum. - * - * Enum for the possible output drive modes for the port pin configuration - * structure, to indicate the output mode the pin should use. - */ -enum system_pinmux_pin_drive { - /** Use totem pole output drive mode */ - SYSTEM_PINMUX_PIN_DRIVE_TOTEM, - /** Use open drain output drive mode */ - SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN, -}; - -/** - * \brief Configures the output driver mode for a GPIO pin. - * - * Configures the output driver mode for a GPIO output, to - * control the pad behavior. - * - * \param[in] gpio_pin Index of the GPIO pin to configure - * \param[in] mode New pad output driver mode to configure - */ -static inline void system_pinmux_pin_set_output_drive( - const uint8_t gpio_pin, - const enum system_pinmux_pin_drive mode) -{ - PortGroup* const port = system_pinmux_get_group_from_gpio_pin(gpio_pin); - uint32_t pin_index = (gpio_pin % 32); - - if (mode == SYSTEM_PINMUX_PIN_DRIVE_OPEN_DRAIN) { - port->PINCFG[pin_index].reg |= PORT_PINCFG_ODRAIN; - } - else { - port->PINCFG[pin_index].reg &= ~PORT_PINCFG_ODRAIN; - } -} - -void system_pinmux_group_set_output_drive( - PortGroup *const port, - const uint32_t mask, - const enum system_pinmux_pin_drive mode); -#endif - -#ifdef __cplusplus -} -#endif - -/** @} */ - -/** - * \page asfdoc_sam0_system_pinmux_extra Extra Information for SYSTEM PINMUX Driver - * - * \section asfdoc_sam0_system_pinmux_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
GPIOGeneral Purpose Input/Output
MUXMultiplexer
- * - * - * \section asfdoc_sam0_system_pinmux_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_pinmux_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_system_pinmux_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Removed code of open drain, slew limit and drive strength - * features
Fixed broken sampling mode function implementations, which wrote - * corrupt configuration values to the device registers
Added missing NULL pointer asserts to the PORT driver functions
Initial Release
- */ - -/** - * \page asfdoc_sam0_system_pinmux_exqsg Examples for SYSTEM PINMUX Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_pinmux_group. QSGs are simple - * examples with step-by-step instructions to configure and use this driver in a - * selection of use cases. Note that a QSG can be compiled as a standalone - * application or be added to the user application. - * - * - \subpage asfdoc_sam0_system_pinmux_basic_use_case - * - * \page asfdoc_sam0_system_pinmux_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42121F12/2015Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C20/C21
42121E12/2014Added support for SAM R21 and SAM D10/D11
42121D01/2014Added support for SAM D21
42121C09/2013Fixed incorrect documentation for the device pin sampling mode
42121B06/2013Corrected documentation typos
42121A06/2013Initial release
- */ - -#endif diff --git a/atmel-samd/asf/sam0/drivers/system/power/power_sam_d_r/power.h b/atmel-samd/asf/sam0/drivers/system/power/power_sam_d_r/power.h deleted file mode 100644 index fe884dea27d75..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/power/power_sam_d_r/power.h +++ /dev/null @@ -1,224 +0,0 @@ -/** - * \file - * - * \brief SAM Power related functionality - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef POWER_H_INCLUDED -#define POWER_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Voltage references within the device. - * - * List of available voltage references (VREF) that may be used within the - * device. - */ -enum system_voltage_reference { - /** Temperature sensor voltage reference */ - SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE, - /** Bandgap voltage reference */ - SYSTEM_VOLTAGE_REFERENCE_BANDGAP, -}; - -/** - * \brief Device sleep modes. - * - * List of available sleep modes in the device. A table of clocks available in - * different sleep modes can be found in \ref asfdoc_sam0_system_module_overview_sleep_mode. - */ -enum system_sleepmode { - /** IDLE 0 sleep mode */ - SYSTEM_SLEEPMODE_IDLE_0, - /** IDLE 1 sleep mode */ - SYSTEM_SLEEPMODE_IDLE_1, - /** IDLE 2 sleep mode */ - SYSTEM_SLEEPMODE_IDLE_2, - /** Standby sleep mode */ - SYSTEM_SLEEPMODE_STANDBY, -}; - - - -/** - * \name Voltage References - * @{ - */ - -/** - * \brief Enable the selected voltage reference - * - * Enables the selected voltage reference source, making the voltage reference - * available on a pin as well as an input source to the analog peripherals. - * - * \param[in] vref Voltage reference to enable - */ -static inline void system_voltage_reference_enable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_TSEN; - break; - - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg |= SYSCTRL_VREF_BGOUTEN; - break; - - default: - Assert(false); - return; - } -} - -/** - * \brief Disable the selected voltage reference - * - * Disables the selected voltage reference source. - * - * \param[in] vref Voltage reference to disable - */ -static inline void system_voltage_reference_disable( - const enum system_voltage_reference vref) -{ - switch (vref) { - case SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_TSEN; - break; - - case SYSTEM_VOLTAGE_REFERENCE_BANDGAP: - SYSCTRL->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; - break; - - default: - Assert(false); - return; - } -} - -/** - * @} - */ - - -/** - * \name Device Sleep Control - * @{ - */ - -/** - * \brief Set the sleep mode of the device - * - * Sets the sleep mode of the device; the configured sleep mode will be entered - * upon the next call of the \ref system_sleep() function. - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see \ref asfdoc_sam0_system_module_overview_sleep_mode. - * - * \param[in] sleep_mode Sleep mode to configure for the next sleep operation - * - * \retval STATUS_OK Operation completed successfully - * \retval STATUS_ERR_INVALID_ARG The requested sleep mode was invalid or not - * available - */ -static inline enum status_code system_set_sleepmode( - const enum system_sleepmode sleep_mode) -{ -#if (SAMD20) - /* Errata 13140: Make sure that the Flash does not power all the way down - * when in sleep mode. This errata has been fixed as of revision D of SAMD21 */ - NVMCTRL->CTRLB.bit.SLEEPPRM = NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val; -#endif - - switch (sleep_mode) { - case SYSTEM_SLEEPMODE_IDLE_0: - case SYSTEM_SLEEPMODE_IDLE_1: - case SYSTEM_SLEEPMODE_IDLE_2: - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - PM->SLEEP.reg = sleep_mode; - break; - - case SYSTEM_SLEEPMODE_STANDBY: - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - break; - - default: - return STATUS_ERR_INVALID_ARG; - } - - return STATUS_OK; -} - -/** - * \brief Put the system to sleep waiting for interrupt - * - * Executes a device DSB (Data Synchronization Barrier) instruction to ensure - * all ongoing memory accesses have completed, then a WFI (Wait For Interrupt) - * instruction to place the device into the sleep mode specified by - * \ref system_set_sleepmode until woken by an interrupt. - */ -static inline void system_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * @} - */ - -/** @} */ -#ifdef __cplusplus -} -#endif - -#endif /* POWER_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/system/reset/reset_sam_d_r/reset.h b/atmel-samd/asf/sam0/drivers/system/reset/reset_sam_d_r/reset.h deleted file mode 100644 index befed28e8a4d6..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/reset/reset_sam_d_r/reset.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - * \file - * - * \brief SAM Reset related functionality - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef RESET_H_INCLUDED -#define RESET_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup asfdoc_sam0_system_group - * @{ - */ - -/** - * \brief Reset causes of the system. - * - * List of possible reset causes of the system. - */ -enum system_reset_cause { - /** The system was last reset by a software reset */ - SYSTEM_RESET_CAUSE_SOFTWARE = PM_RCAUSE_SYST, - /** The system was last reset by the watchdog timer */ - SYSTEM_RESET_CAUSE_WDT = PM_RCAUSE_WDT, - /** The system was last reset because the external reset line was pulled low */ - SYSTEM_RESET_CAUSE_EXTERNAL_RESET = PM_RCAUSE_EXT, - /** The system was last reset by the BOD33 */ - SYSTEM_RESET_CAUSE_BOD33 = PM_RCAUSE_BOD33, - /** The system was last reset by the BOD12 */ - SYSTEM_RESET_CAUSE_BOD12 = PM_RCAUSE_BOD12, - /** The system was last reset by the POR (Power on reset) */ - SYSTEM_RESET_CAUSE_POR = PM_RCAUSE_POR, -}; - - -/** - * \name Reset Control - * @{ - */ - -/** - * \brief Reset the MCU. - * - * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources, - * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set). - * - */ -static inline void system_reset(void) -{ - NVIC_SystemReset(); -} - -/** - * \brief Return the reset cause. - * - * Retrieves the cause of the last system reset. - * - * \return An enum value indicating the cause of the last system reset. - */ -static inline enum system_reset_cause system_get_reset_cause(void) -{ - return (enum system_reset_cause)PM->RCAUSE.reg; -} - -/** - * @} - */ - -/** @} */ -#ifdef __cplusplus -} -#endif - -#endif /* RESET_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/system/system.c b/atmel-samd/asf/sam0/drivers/system/system.c deleted file mode 100644 index 62f2d646300ee..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/system.c +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * \brief SAM System related functionality - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include - -/** - * \internal - * Dummy initialization function, used as a weak alias target for the various - * init functions called by \ref system_init(). - */ -void _system_dummy_init(void); -void _system_dummy_init(void) -{ - return; -} - -#if !defined(__DOXYGEN__) -# if defined(__GNUC__) -void system_clock_init(uint16_t dfll_fine_calibration) WEAK __attribute__((alias("_system_dummy_init"))); -void system_board_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -void _system_events_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -void _system_extint_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -void _system_divas_init(void) WEAK __attribute__((alias("_system_dummy_init"))); -# elif defined(__ICCARM__) -void system_clock_init(uint16_t dfll_fine_calibration); -void system_board_init(void); -void _system_events_init(void); -void _system_extint_init(void); -void _system_divas_init(void); -# pragma weak system_clock_init=_system_dummy_init -# pragma weak system_board_init=_system_dummy_init -# pragma weak _system_events_init=_system_dummy_init -# pragma weak _system_extint_init=_system_dummy_init -# pragma weak _system_divas_init=_system_dummy_init -# endif -#endif - -/** - * \brief Initialize system - * - * This function will call the various initialization functions within the - * system namespace. If a given optional system module is not available, the - * associated call will effectively be a NOP (No Operation). - * - * Currently the following initialization functions are supported: - * - System clock initialization (via the SYSTEM CLOCK sub-module) - * - Board hardware initialization (via the Board module) - * - Event system driver initialization (via the EVSYS module) - * - External Interrupt driver initialization (via the EXTINT module) - */ -void system_init(uint16_t dfll_fine_calibration) -{ - /* Configure GCLK and clock sources according to conf_clocks.h */ - system_clock_init(dfll_fine_calibration); - - /* Initialize board hardware */ - system_board_init(); - - /* Initialize EVSYS hardware */ - _system_events_init(); - - /* Initialize External hardware */ - _system_extint_init(); - - /* Initialize DIVAS hardware */ - _system_divas_init(); -} diff --git a/atmel-samd/asf/sam0/drivers/system/system.h b/atmel-samd/asf/sam0/drivers/system/system.h deleted file mode 100644 index a0be5b7051000..0000000000000 --- a/atmel-samd/asf/sam0/drivers/system/system.h +++ /dev/null @@ -1,727 +0,0 @@ -/** - * \file - * - * \brief SAM System related functionality - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef SYSTEM_H_INCLUDED -#define SYSTEM_H_INCLUDED - -#include -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_system_group SAM System (SYSTEM) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the device's system relation functionality, necessary for - * the basic device operation. This is not limited to a single peripheral, but - * extends across multiple hardware peripherals. - * - * The following peripherals are used by this module: - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - PM (Power Manager) - * - RSTC (Reset Controller) - * - SUPC (Supply Controller) - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - PM (Power Manager) - * - RSTC (Reset Controller) - * - SUPC (Supply Controller) - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - SYSCTRL (System Control) - * - PM (Power Manager) - * \endif - * - * The following devices can use this module: - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - Atmel | SMART SAM L21 - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - Atmel | SMART SAM C20/C21 - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM DA1 - * \endif - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_system_prerequisites - * - \ref asfdoc_sam0_system_module_overview - * - \ref asfdoc_sam0_system_special_considerations - * - \ref asfdoc_sam0_system_extra_info - * - \ref asfdoc_sam0_system_examples - * - \ref asfdoc_sam0_system_api_overview - * - * - * \section asfdoc_sam0_system_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_system_module_overview Module Overview - * - * The System driver provides a collection of interfaces between the user - * application logic, and the core device functionality (such as clocks, reset - * cause determination, etc.) that is required for all applications. It contains - * a number of sub-modules that control one specific aspect of the device: - * - * - System Core (this module) - * - \ref asfdoc_sam0_system_clock_group "System Clock Control" (sub-module) - * - \ref asfdoc_sam0_system_interrupt_group "System Interrupt Control" (sub-module) - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Control" (sub-module) - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * \subsection asfdoc_sam0_system_module_overview_vreg_l21 Voltage Regulator - * The SAM device controls the voltage regulators for the core (VDDCORE) and - * backup (VDDBU) domains. It sets the voltage regulators according to the sleep - * modes, the performance level, or the user configuration. - * - * In active mode, the voltage regulator can be chosen on the fly between a LDO - * or a Buck converter. In standby mode, the low power voltage regulator is used - * to supply VDDCORE. - * - * \subsection asfdoc_sam0_system_module_overview_bbps Battery Backup Power Switch - * The SAM device supports connection of a battery backup to the VBAT power pin. - * It includes functionality that enables automatic power switching between main - * power and battery backup power. This will ensure power to the backup domain, - * when the main battery or power source is unavailable. - * \endif - * - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * \subsection asfdoc_sam0_system_module_overview_vreg_c21 Voltage Regulator - * The SAM device controls the voltage regulators for the core (VDDCORE). It sets - * the voltage regulators according to the sleep modes. - * - * There are a selectable reference voltage and voltage dependent on the temperature - * which can be used by analog modules like the ADC. - * \endif - * - * \subsection asfdoc_sam0_system_module_overview_vref Voltage References - * The various analog modules within the SAM devices (such as AC, ADC, and - * DAC) require a voltage reference to be configured to act as a reference point - * for comparisons and conversions. - * - * The SAM devices contain multiple references, including an internal - * temperature sensor and a fixed band-gap voltage source. When enabled, the - * associated voltage reference can be selected within the desired peripheral - * where applicable. - * - * \subsection asfdoc_sam0_system_module_overview_reset_cause System Reset Cause - * In some applications there may be a need to execute a different program - * flow based on how the device was reset. For example, if the cause of reset - * was the Watchdog timer (WDT), this might indicate an error in the application, - * and a form of error handling or error logging might be needed. - * - * For this reason, an API is provided to retrieve the cause of the last system - * reset, so that appropriate action can be taken. - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * There are three groups of reset sources: - * - Power supply reset: Resets caused by an electrical issue. It covers POR and BOD reset. - * - User reset: Resets caused by the application. It covers external reset, - * system reset, and watchdog reset. - * - Backup reset: Resets caused by a backup mode exit condition. - * - * \subsection asfdoc_sam0_system_module_overview_performance_level Performance Level - * Performance level allows the user to adjust the regulator output voltage to reduce - * power consumption. The user can on the fly select the most suitable performance - * level, depending on the application demands. - * - * The SAM device can operate at two different performance levels (PL0 and PL2). - * When operating at PL0, the voltage applied on the full logic area is reduced - * by voltage scaling. This voltage scaling technique allows to reduce the active - * power consumption while decreasing the maximum frequency of the device. When - * operating at PL2, the voltage regulator supplies the highest voltage, allowing - * the device to run at higher clock speeds. - * - * Performance level transition is possible only when the device is in active - * mode. After a reset, the device starts at the lowest performance level - * (lowest power consumption and lowest max. frequency). The application can then - * switch to another performance level at any time without any stop in the code - * execution. As shown in \ref asfdoc_sam0_system_performance_level_transition_figure. - * - * \note When scaling down the performance level, the bus frequency should first be - * scaled down in order to not exceed the maximum frequency allowed for the - * low performance level. - * When scaling up the performance level (e.g. from PL0 to PL2), check the performance - * level status before increasing the bus frequency. It can be increased only - * when the performance level transition is completed. - * - * \anchor asfdoc_sam0_system_performance_level_transition_figure - * \image html performance_level_transition.svg "Performance Level Transition" - * - * \subsection asfdoc_sam0_system_module_overview_power_domain Power Domain Gating - * Power domain gating allows power saving by reducing the voltage in logic - * areas in the device to a low-power supply. The feature is available in - * Standby sleep mode and will reduce the voltage in domains where all peripherals - * are idle. Internal logic will maintain its content, meaning the corresponding - * peripherals will not need to be reconfigured when normal operating voltage - * is returned. Most power domains can be in the following three states: - * - * - Active state: The power domain is powered on. - * - Retention state: The main voltage supply for the power domain is switched off, - * while maintaining a secondary low-power supply for the sequential cells. The - * logic context is restored when waking up. - * - Off state: The power domain is entirely powered off. The logic context is lost. - * - * The SAM L21 device contains three power domains which can be controlled using - * power domain gating, namely PD0, PD1, and PD2. These power domains can be - * configured to the following cases: - * - Default with no sleepwalking peripherals: A power domain is automatically set - * to retention state in standby sleep mode if no activity require it. The application - * can force all power domains to remain in active state during standby sleep mode - * in order to accelerate wakeup time. - * - Default with sleepwalking peripherals: If one or more peripherals are enabled - * to perform sleepwalking tasks in standby sleep mode, the corresponding power - * domain (PDn) remains in active state as well as all inferior power domains (PDn) in order - * to perform a sleepwalking task. The superior power domain is then automatically - * set to active state. At the end of the sleepwalking task, the device can either - * be woken up or the superior power domain can return to retention state. - * - * Power domains can be linked to each other, it allows a power domain (PDn) to be kept - * in active state if the inferior power domain (PDn-1) is in active state too. - * - * \ref asfdoc_sam0_system_power_domain_overview_table illustrates the - * four cases to consider in standby mode. - * - * \anchor asfdoc_sam0_system_power_domain_overview_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Sleep Mode versus Power Domain State Overview
Sleep modePD0PD1PD2PDTOPPDBACKUP
Idleactiveactiveactiveactiveactive
Standby - Case 1activeactiveactiveactiveactive
Standby - Case 2activeactiveretentionactiveactive
Standby - Case 3activeretentionretentionactiveactive
Standby - Case 4retentionretentionretentionactiveactive
Backupoffoffoffoffactive
Offoffoffoffoffoff
- * - * \subsection asfdoc_sam0_system_module_overview_ram_state RAMs Low Power Mode - * By default, in standby sleep mode, RAM is in low power mode (back biased) - * if its power domain is in retention state. - * \ref asfdoc_sam0_system_power_ram_state_table lists RAMs low power mode. - * - * \anchor asfdoc_sam0_system_power_ram_state_table - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
RAM Back-biasing Mode
RAM modeDescription
Retention Back-biasing modeRAM is back-biased if its power domain is in retention mode
Standby Back-biasing modeRAM is back-biased if the device is in standby mode
Standby OFF modeRAM is OFF if the device is in standby mode
Always OFF modeRAM is OFF if the device is in RET mode
- * - * \endif - * - * \subsection asfdoc_sam0_system_module_overview_sleep_mode Sleep Modes - * The SAM devices have several sleep modes. The sleep mode controls - * which clock systems on the device will remain enabled or disabled when the - * device enters a low power sleep mode. - * \ref asfdoc_sam0_system_module_sleep_mode_table "The table below" lists the - * clock settings of the different sleep modes. - * - * \anchor asfdoc_sam0_system_module_sleep_mode_table - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \else - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
SAM Device Sleep Modes
Sleep modeSystem clockCPU clockAHB/AHB clockGCLK clocksOscillators (ONDEMAND = 0)Oscillators (ONDEMAND = 1)Regulator modeRAM mode
IdleRunStopRun if requestedRunRunRun if requestedNormalNormal
StandbyStopStopRun if requestedRun if requestedRun if requested or RUNSTDBY = 1Run if requestedLow pwerLow pwer
BackupStopStopStopStopStopStopBackupOff
OffOffOffOffOffOffOffOffOff
Sleep modeCPU clockAHB clockAPB clocksClock sourcesSystem clock32KHzReg modeRAM mode
Idle 0StopRunRunRunRunRunNormalNormal
Idle 1StopStopRunRunRunRunNormalNormal
Idle 2StopStopStopRunRunRunNormalNormal
StandbyStopStopStopStopStopStopLow PowerSource/Drain biasing
- * - * Before entering device sleep, one of the available sleep modes must be set. - * The device will automatically wake up in response to an interrupt being - * generated or upon any other sleep mode exit condition. - * - * Some peripheral clocks will remain enabled during sleep, depending on their - * configuration. If desired, the modules can remain clocked during sleep to allow - * them continue to operate while other parts of the system are powered down - * to save power. - * - * - * \section asfdoc_sam0_system_special_considerations Special Considerations - * - * Most of the functions in this driver have device specific restrictions and - * caveats; refer to your device datasheet. - * - * - * \section asfdoc_sam0_system_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_system_extra. This includes: - * - \ref asfdoc_sam0_system_extra_acronyms - * - \ref asfdoc_sam0_system_extra_dependencies - * - \ref asfdoc_sam0_system_extra_errata - * - \ref asfdoc_sam0_system_extra_history - * - * - * \section asfdoc_sam0_system_examples Examples - * - * For SYSTEM module related examples, refer to the sub-modules listed in - * the \ref asfdoc_sam0_system_module_overview "Module Overview". - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_drivers_power_exqsg. - * \endif - * - * - * \section asfdoc_sam0_system_api_overview API Overview - * @{ - */ - -/** - * \name System Debugger - * @{ - */ - -/** - * \brief Check if debugger is present. - * - * Check if debugger is connected to the onboard debug system (DAP). - * - * \return A bool identifying if a debugger is present. - * - * \retval true Debugger is connected to the system - * \retval false Debugger is not connected to the system - * - */ -static inline bool system_is_debugger_present(void) -{ - return DSU->STATUSB.reg & DSU_STATUSB_DBGPRES; -} - -/** - * @} - */ - -/** - * \name System Identification - * @{ - */ - -/** - * \brief Retrieve the device identification signature. - * - * Retrieves the signature of the current device. - * - * \return Device ID signature as a 32-bit integer. - */ -static inline uint32_t system_get_device_id(void) -{ - return DSU->DID.reg; -} - -/** - * @} - */ - -/** - * \name System Initialization - * @{ - */ - -void system_init(uint16_t dfll_fine_calibration); - -/** - * @} - */ - - -/** - * @} - */ - -/** - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * \page asfdoc_sam0_drivers_power_exqsg Examples for SYSTEM Driver - * - * This is a list of the available Quick Start Guides (QSGs) and example - * applications for \ref asfdoc_sam0_system_group. QSGs are simple examples with step-by-step instructions to - * configure and use this driver in a selection of - * use cases. Note that a QSG can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_power_basic_use_case - * \endif - * - * \page asfdoc_sam0_system_extra Extra Information for SYSTEM Driver - * - * \section asfdoc_sam0_system_extra_acronyms Acronyms - * Below is a table listing the acronyms used in this module, along with their - * intended meanings. - * - * - * - * - * - * - * - * - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - * - * - * - * \endif - *
AcronymDefinition
PMPower Manager
SUPCSupply Controller
RSTCReset Controller
SUPCSupply Controller
RSTCReset Controller
SYSCTRLSystem control interface
- * - * - * \section asfdoc_sam0_system_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - None - * - * - * \section asfdoc_sam0_system_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_system_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - * - * - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * - * \endif - *
Changelog
Initial Release
Initial Release
Added new \c system_reset() to reset the complete MCU with some exceptions
Added new \c system_get_device_id() function to retrieved the device - * ID
Initial Release
- * - * \page asfdoc_sam0_system_document_revision_history Document Revision History - * - * - * - * - * - * - * - * \if DEVICE_SAML21_SYSTEM_SUPPORT - * - * - * - * - * - * \endif - * \if DEVICE_SAMC21_SYSTEM_SUPPORT - * - * - * - * - * - * \endif - * \if DEVICE_SAMD21_SYSTEM_SUPPORT - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * \endif - *
Doc. Rev.DateComments
42449A07/2015Initial document release
42484A12/2015Initial document release.
42120E12/2015Added support for SAM DA1 and SAM D09
42120D12/2014Added support for SAM R21 and SAM D10/D11
42120C01/2014Added support for SAM D21
42120B06/2013Corrected documentation typos
42120A06/2013Initial document release
- */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/tc/docimg/overview.svg b/atmel-samd/asf/sam0/drivers/tc/docimg/overview.svg deleted file mode 100644 index 895ba938c7a13..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tc/docimg/overview.svg +++ /dev/null @@ -1,434 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Master slide - - - - - - - - - - - C - o - u - n - t - e - r - - - - - - P - r - e - s - c - a - l - e - r - - - - - - B - a - s - e - - C - o - u - n - t - e - r - - - - - - C - o - n - t - r - o - l - - L - o - g - i - c - - - - - - - - - - - - - - - - - - C - o - m - p - a - r - e - - C - a - p - t - u - r - e - - n - - - - - - - - - C - o - m - p - a - r - e - - C - a - p - t - u - r - e - - . - . - . - - - - - - - - - C - o - m - p - a - r - e - - C - a - p - t - u - r - e - - 1 - - - - - - - - - C - o - n - t - r - o - l - - L - o - g - i - c - - - - - - C - o - m - p - a - r - e - - C - a - p - t - u - r - e - - 0 - - - - - - W - a - v - e - f - o - r - m - - G - e - n - e - r - a - t - i - o - n - - - - - - - - - - C - C - 0 - - - - - - - - - - = - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - G - C - L - K - _ - T - C - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I - n - t - e - r - r - u - p - t - / - E - v - e - n - t - - C - h - a - n - n - e - l - - - - - - I - n - t - e - r - r - u - p - t - / - E - v - e - n - t - - C - h - a - n - n - e - l - - - - - - W - O - x - - O - u - t - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/tc/docimg/pwm_match_ex.svg b/atmel-samd/asf/sam0/drivers/tc/docimg/pwm_match_ex.svg deleted file mode 100644 index 3eed8c70f3314..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tc/docimg/pwm_match_ex.svg +++ /dev/null @@ -1,431 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Master slide - - - - - - - - - - - - - - - - T - i - m - e - - - - - - - - - - - - - - - - - - - - - - - - C - o - m - p - a - r - e - - m - a - t - c - h - - v - a - l - u - e - - - - - - - - - - - - - - - - - - - - - R - e - l - o - a - d - - t - o - - T - O - P - - v - a - l - u - e - - - - - - - - - - - - - - - - - - C - o - u - n - t - - i - s - - w - r - i - t - t - e - n - - u - s - i - n - g - - t - c - _ - s - e - t - _ - c - o - u - n - t - _ - v - a - l - u - e - ( - ) - - - - - - - - - - - - - - T - O - P - - v - a - l - u - e - - h - a - s - - b - e - e - n - - c - h - a - n - g - e - d - - u - s - i - n - g - - t - c - _ - s - e - t - _ - t - o - p - _ - v - a - l - u - e - ( - ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - M - a - t - c - h - - - - - - - - - P - W - M - - i - n - v - e - r - t - e - d - - o - u - t - p - u - t - - - - - - M - a - x - - - - - - C - o - u - n - t - e - r - - v - a - l - u - e - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/tc/docimg/pwm_normal_ex.svg b/atmel-samd/asf/sam0/drivers/tc/docimg/pwm_normal_ex.svg deleted file mode 100644 index 072e1fc893c9d..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tc/docimg/pwm_normal_ex.svg +++ /dev/null @@ -1,386 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Master slide - - - - - - - - C - o - u - n - t - e - r - - v - a - l - u - e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - i - m - e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - M - a - t - c - h - - - - - - - - - - - - - - - - - - - - - - - - P - W - M - - o - u - t - p - u - t - - - - - - R - e - l - o - a - d - - c - o - u - n - t - e - r - - t - o - - z - e - r - o - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C - o - m - p - a - r - e - - v - a - l - u - e - - h - a - s - - b - e - e - n - - c - h - a - n - g - e - d - - w - i - t - h - - t - c - _ - s - e - t - _ - c - o - m - p - a - r - e - _ - v - a - l - u - e - ( - ) - - - - - - - - - - - - - - - - - - - T - O - P - - = - - M - a - x - - - - - - C - o - m - p - a - r - e - - m - a - t - c - h - - v - a - l - u - e - - - - \ No newline at end of file diff --git a/atmel-samd/asf/sam0/drivers/tc/tc.h b/atmel-samd/asf/sam0/drivers/tc/tc.h deleted file mode 100644 index 7bf7420461c6c..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tc/tc.h +++ /dev/null @@ -1,1790 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TC_H_INCLUDED -#define TC_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_tc_group SAM Timer/Counter (TC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the timer modules within the device, for waveform - * generation and timing operations. The following driver API modes are covered - * by this manual: - * - * - Polled APIs - * \if TC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * - * The following peripheral is used by this module: - * - TC (Timer/Counter) - * - * The following devices can use this module: - * - Atmel | SMART SAM D20/D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D09/D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_tc_prerequisites - * - \ref asfdoc_sam0_tc_module_overview - * - \ref asfdoc_sam0_tc_special_considerations - * - \ref asfdoc_sam0_tc_extra_info - * - \ref asfdoc_sam0_tc_examples - * - \ref asfdoc_sam0_tc_api_overview - * - * - * \section asfdoc_sam0_tc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * - * \section asfdoc_sam0_tc_module_overview Module Overview - * - * The Timer/Counter (TC) module provides a set of timing and counting related - * functionality, such as the generation of periodic waveforms, the capturing - * of a periodic waveform's frequency/duty cycle, and software timekeeping for - * periodic operations. TC modules can be configured to use an 8-, 16-, or - * 32-bit counter size. - * - * This TC module for the SAM is capable of the following functions: - * - * - Generation of PWM signals - * - Generation of timestamps for events - * - General time counting - * - Waveform period capture - * - Waveform frequency capture - * - * \ref asfdoc_sam0_tc_block_diagram "The diagram below" shows the overview - * of the TC module design. - * - * \anchor asfdoc_sam0_tc_block_diagram - * \image html overview.svg "Basic Overview of the TC Module" - * - * - * \subsection asfdoc_sam0_tc_features Driver Feature Macro Definition - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Driver Feature MacroSupported devices
FEATURE_TC_DOUBLE_BUFFEREDSAM L21/L22/C20/C21
FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2SAM L21/L22/C20/C21
FEATURE_TC_STAMP_PW_CAPTURESAM L21/L22/C20/C21
FEATURE_TC_READ_SYNCSAM L21/L22/C20/C21
FEATURE_TC_IO_CAPTURESAM L21/L22/C20/C21
FEATURE_TC_GENERATE_DMA_TRIGGERSAM L21/L22
- * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_tc_module_overview_func_desc Functional Description - * Independent of the configured counter size, each TC module can be set up - * in one of two different modes; capture and compare. - * - * In capture mode, the counter value is stored when a configurable event - * occurs. This mode can be used to generate timestamps used in event capture, - * or it can be used for the measurement of a periodic input signal's - * frequency/duty cycle. - * - * In compare mode, the counter value is compared against one or more of the - * configured channel compare values. When the counter value coincides with a - * compare value an action can be taken automatically by the module, such as - * generating an output event or toggling a pin when used for frequency or - * Pulse Width Modulation (PWM) signal generation. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * \subsection asfdoc_sam0_tc_module_overview_tc_size Timer/Counter Size - * Each timer module can be configured in one of three different counter - * sizes; 8-, 16-, and 32-bit. The size of the counter determines the maximum - * value it can count to before an overflow occurs and the count is reset back - * to zero. \ref asfdoc_sam0_tc_count_size_vs_top "The table below" shows the - * maximum values for each of the possible counter sizes. - * - * \anchor asfdoc_sam0_tc_count_size_vs_top - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Timer Counter Sizes and Their Maximum Count Values
Counter sizeMax. (hexadecimal)Max. (decimal)
8-bit0xFF255
16-bit0xFFFF65,535
32-bit0xFFFFFFFF4,294,967,295
- * - * When using the counter in 16- or 32-bit count mode, Compare Capture - * register 0 (CC0) is used to store the period value when running in PWM - * generation match mode. - * - * When using 32-bit counter size, two 16-bit counters are chained together - * in a cascade formation. Except in SAM D09/D10/D11. Even numbered TC modules - * (e.g. TC0, TC2) can be configured as 32-bit counters. The odd numbered - * counters will act as slaves to the even numbered masters, and will not - * be reconfigurable until the master timer is disabled. The pairing of timer - * modules for 32-bit mode is shown in \ref asfdoc_sam0_tc_module_ms_pairs - * "the table below". - * - * \anchor asfdoc_sam0_tc_module_ms_pairs - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TC Master and Slave Module Pairings
Master TC moduleSlave TC module
TC0TC1
TC2TC3
......
TCn-1TCn
- * - * In SAM D09/D10/D11, odd numbered TC modules (e.g. TC1) can be configured as 32-bit - * counters. The even numbered (e.g. TC2) counters will act as slaves to the odd - * numbered masters. - * - * \subsection asfdoc_sam0_tc_module_overview_clock Clock Settings - * - * \subsubsection asfdoc_sam0_tc_module_overview_clock_selection Clock Selection - * Each TC peripheral is clocked asynchronously to the system clock by a GCLK - * (Generic Clock) channel. The GCLK channel connects to any of the GCLK - * generators. The GCLK generators are configured to use one of the available - * clock sources on the system such as internal oscillator, external crystals, - * etc. See the \ref asfdoc_sam0_system_clock_group "Generic Clock driver" - *for - * more information. - * - * \subsubsection asfdoc_sam0_tc_module_overview_clock_prescaler Prescaler - * Each TC module in the SAM has its own individual clock prescaler, which - * can be used to divide the input clock frequency used in the counter. This - * prescaler only scales the clock used to provide clock pulses for the counter - * to count, and does not affect the digital register interface portion of - * the module, thus the timer registers will synchronize to the raw GCLK - * frequency input to the module. - * - * As a result of this, when selecting a GCLK frequency and timer prescaler - * value the user application should consider both the timer resolution - * required and the synchronization frequency, to avoid lengthy - * synchronization times of the module if a very slow GCLK frequency is fed - * into the TC module. It is preferable to use a higher module GCLK frequency - * as the input to the timer, and prescale this down as much as possible to - * obtain a suitable counter frequency in latency-sensitive applications. - * - * \subsubsection asfdoc_sam0_tc_module_overview_clock_reloading Reloading - * Timer modules also contain a configurable reload action, used when a - * re-trigger event occurs. Examples of a re-trigger event are the counter - * reaching the maximum value when counting up, or when an event from the event - * system tells the counter to re-trigger. The reload action determines if the - * prescaler should be reset, and when this should happen. The counter will - * always be reloaded with the value it is set to start counting from. The user - * can choose between three different reload actions, described in - * \ref asfdoc_sam0_tc_module_reload_act "the table below". - * - * \anchor asfdoc_sam0_tc_module_reload_act - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TC Module Reload Actions
Reload actionDescription
\ref TC_RELOAD_ACTION_GCLK Reload TC counter value on next GCLK cycle. Leave prescaler - * as-is.
\ref TC_RELOAD_ACTION_PRESC Reloads TC counter value on next prescaler clock. Leave prescaler - * as-is.
\ref TC_RELOAD_ACTION_RESYNC Reload TC counter value on next GCLK cycle. Clear prescaler to - * zero.
- * - * The reload action to use will depend on the specific application being - * implemented. One example is when an external trigger for a reload occurs; if - * the TC uses the prescaler, the counter in the prescaler should not have a - * value between zero and the division factor. The TC counter and the counter - * in the prescaler should both start at zero. When the counter is set to - * re-trigger when it reaches the maximum value on the other hand, this is not the - * right option to use. In such a case it would be better if the prescaler is - * left unaltered when the re-trigger happens, letting the counter reset on the - * next GCLK cycle. - * - * \subsection asfdoc_sam0_tc_module_overview_compare_match Compare Match Operations - * In compare match operation, Compare/Capture registers are used in comparison - * with the counter value. When the timer's count value matches the value of a - * compare channel, a user defined action can be taken. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_timer Basic Timer - * - * A Basic Timer is a simple application where compare match operations are used - * to determine when a specific period has elapsed. In Basic Timer operations, - * one or more values in the module's Compare/Capture registers are used to - * specify the time (as a number of prescaled GCLK cycles) when an action should - * be taken by the microcontroller. This can be an Interrupt Service Routine - * (ISR), event generator via the event system, or a software flag that is - * polled via the user application. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg Waveform Generation - * - * Waveform generation enables the TC module to generate square waves, or if - * combined with an external passive low-pass filter; analog waveforms. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_pwm Waveform Generation - PWM - * - * Pulse width modulation is a form of waveform generation and a signalling - * technique that can be useful in many situations. When PWM mode is used, - * a digital pulse train with a configurable frequency and duty cycle can be - * generated by the TC module and output to a GPIO pin of the device. - * - * Often PWM is used to communicate a control or information parameter to an - * external circuit or component. Differing impedances of the source generator - * and sink receiver circuits are less of an issue when using PWM compared to - * using an analog voltage value, as noise will not generally affect the - * signal's integrity to a meaningful extent. - * - * \ref asfdoc_sam0_tc_module_pwm_normal_diag "The figure below" illustrates - * operations and different states of the counter and its output when running - * the counter in PWM normal mode. As can be seen, the TOP value is unchanged - * and is set to MAX. The compare match value is changed at several points to - * illustrate the resulting waveform output changes. The PWM output is set to - * normal (i.e. non-inverted) output mode. - * - * \anchor asfdoc_sam0_tc_module_pwm_normal_diag - * \image html pwm_normal_ex.svg "Example of PWM in Normal Mode, and Different Counter Operations" - * - * - * In \ref asfdoc_sam0_tc_module_pwm_match_diag "the figure below", the - * counter is set to generate PWM in Match mode. The PWM output is inverted via - * the appropriate configuration option in the TC driver configuration - * structure. In this example, the counter value is changed once, but the - * compare match value is kept unchanged. As can be seen, it is possible to - * change the TOP value when running in PWM match mode. - * - * \anchor asfdoc_sam0_tc_module_pwm_match_diag - * \image html pwm_match_ex.svg "Example of PWM in Match Mode and Different Counter Operations" - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_wg_freq Waveform Generation - Frequency - * - * Frequency Generation mode is in many ways identical to PWM - * generation. However, in Frequency Generation a toggle only occurs - * on the output when a match on a capture channels occurs. When the - * match is made, the timer value is reset, resulting in a variable - * frequency square wave with a fixed 50% duty cycle. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt Capture Operations - * - * In capture operations, any event from the event system or a pin change can - * trigger a capture of the counter value. This captured counter value can be - * used as a timestamp for the event, or it can be used in frequency and pulse - * width capture. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_event_capture Capture Operations - Event - * - * Event capture is a simple use of the capture functionality, - * designed to create timestamps for specific events. When the TC - * module's input capture pin is externally toggled, the current timer - * count value is copied into a buffered register which can then be - * read out by the user application. - * - * Note that when performing any capture operation, there is a risk that the - * counter reaches its top value (MAX) when counting up, or the bottom value - * (zero) when counting down, before the capture event occurs. This can distort - * the result, making event timestamps to appear shorter than reality; the - * user application should check for timer overflow when reading a capture - * result in order to detect this situation and perform an appropriate - * adjustment. - * - * Before checking for a new capture, \ref TC_STATUS_COUNT_OVERFLOW - * should be checked. The response to an overflow error is left to the user - * application, however it may be necessary to clear both the capture overflow - * flag and the capture flag upon each capture reading. - * - * \subsubsection asfdoc_sam0_tc_module_overview_compare_match_capt_pwc Capture Operations - Pulse Width - * - * Pulse Width Capture mode makes it possible to measure the pulse width and - * period of PWM signals. This mode uses two capture channels of the counter. - * This means that the counter module used for Pulse Width Capture can not be - * used for any other purpose. There are two modes for pulse width capture; - * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture - * channel 0 is used for storing the pulse width and capture channel 1 stores - * the observed period. While in PPW mode, the roles of the two capture channels - * are reversed. - * - * As in the above example it is necessary to poll on interrupt flags to see - * if a new capture has happened and check that a capture overflow error has - * not occurred. - * - * \subsection asfdoc_sam0_tc_module_overview_oneshot One-shot Mode - * - * TC modules can be configured into a one-shot mode. When configured in this - * manner, starting the timer will cause it to count until the next overflow - * or underflow condition before automatically halting, waiting to be manually - * triggered by the user application software or an event signal from the event - * system. - * - * \subsubsection asfdoc_sam0_tc_module_overview_inversion Wave Generation Output Inversion - * - * The output of the wave generation can be inverted by hardware if desired, - * resulting in the logically inverted value being output to the configured - * device GPIO pin. - * - * - * \section asfdoc_sam0_tc_special_considerations Special Considerations - * - * The number of capture compare registers in each TC module is dependent on - * the specific SAM device being used, and in some cases the counter size. - * - * The maximum amount of capture compare registers available in any SAM - * device is two when running in 32-bit mode and four in 8- and 16-bit modes. - * - * - * \section asfdoc_sam0_tc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_tc_extra. This includes: - * - \ref asfdoc_sam0_tc_extra_acronyms - * - \ref asfdoc_sam0_tc_extra_dependencies - * - \ref asfdoc_sam0_tc_extra_errata - * - \ref asfdoc_sam0_tc_extra_history - * - * - * \section asfdoc_sam0_tc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_tc_exqsg. - * - * \section asfdoc_sam0_tc_api_overview API Overview - * @{ - */ - -#include -#include -#include -#include - -/** - * Define port features set according to different device family - * @{ -*/ -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) || defined(__DOXYGEN__) -/** TC double buffered. */ -# define FEATURE_TC_DOUBLE_BUFFERED -/** SYNCBUSY scheme version 2. */ -# define FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2 -/** TC time stamp capture and pulse width capture. */ -# define FEATURE_TC_STAMP_PW_CAPTURE -/** Read synchronization of COUNT. */ -# define FEATURE_TC_READ_SYNC -/** I/O pin edge capture. */ -# define FEATURE_TC_IO_CAPTURE -#endif - -#if (SAML21XXXB) || (SAMR30) || defined(__DOXYGEN__) -/** Generate Direct Memory Access (DMA) triggers. */ -# define FEATURE_TC_GENERATE_DMA_TRIGGER -#endif -/*@}*/ - -#if !defined(__DOXYGEN__) -#if SAMD20 || SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30 -# define TC_INSTANCE_OFFSET 0 -#endif -#if SAMD21 || SAMR21 || SAMDA1 -# define TC_INSTANCE_OFFSET 3 -#endif -#if SAMD09 || SAMD10 || SAMD11 -# define TC_INSTANCE_OFFSET 1 -#endif - -#if SAMD20 -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC8_NUM -#elif SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30 -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC0_CC_NUM -#elif SAMD09 || SAMD10 || SAMD11 -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC1_CC8_NUM -#else -# define NUMBER_OF_COMPARE_CAPTURE_CHANNELS TC3_CC8_NUM - /* Same number for 8-, 16- or 32-bit TC and all TC instances */ -#endif - -/** TC Instance MAX ID Number. */ -#if SAMD20E || SAMD20G || SAMD21G || SAMD21E || SAMR21 -# if SAMD21GXXL -# define TC_INST_MAX_ID 7 -# else -# define TC_INST_MAX_ID 5 -# endif -#elif SAML21 || SAMC20 || SAMC21 || SAMR30 -# define TC_INST_MAX_ID 4 -#elif SAML22 -# define TC_INST_MAX_ID 3 -#elif SAMD09 || SAMD10 || SAMD11 -# define TC_INST_MAX_ID 2 -#else -# define TC_INST_MAX_ID 7 -#endif - -#endif - -#if TC_ASYNC == true -# include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#if TC_ASYNC == true -/** Enum for the possible callback types for the TC module. */ -enum tc_callback { - /** Callback for TC overflow */ - TC_CALLBACK_OVERFLOW, - /** Callback for capture overflow error */ - TC_CALLBACK_ERROR, - /** Callback for capture compare channel 0 */ - TC_CALLBACK_CC_CHANNEL0, - /** Callback for capture compare channel 1 */ - TC_CALLBACK_CC_CHANNEL1, -# if !defined(__DOXYGEN__) - /** Number of available callbacks */ - TC_CALLBACK_N, -# endif -}; -#endif - -/** - * \name Module Status Flags - * - * TC status flags, returned by \ref tc_get_status() and cleared by - * \ref tc_clear_status(). - * - * @{ - */ - -/** Timer channel 0 has matched against its compare value, or has captured a - * new value. - */ -#define TC_STATUS_CHANNEL_0_MATCH (1UL << 0) - -/** Timer channel 1 has matched against its compare value, or has captured a - * new value. - */ -#define TC_STATUS_CHANNEL_1_MATCH (1UL << 1) - -/** Timer register synchronization has completed, and the synchronized count - * value may be read. - */ -#define TC_STATUS_SYNC_READY (1UL << 2) - -/** A new value was captured before the previous value was read, resulting in - * lost data. - */ -#define TC_STATUS_CAPTURE_OVERFLOW (1UL << 3) - -/** The timer count value has overflowed from its maximum value to its minimum - * when counting upward, or from its minimum value to its maximum when - * counting downward. - */ -#define TC_STATUS_COUNT_OVERFLOW (1UL << 4) - -#ifdef FEATURE_TC_DOUBLE_BUFFERED -/** Channel 0 compare or capture buffer valid. */ -#define TC_STATUS_CHN0_BUFFER_VALID (1UL << 5) -/** Channel 1 compare or capture buffer valid. */ -#define TC_STATUS_CHN1_BUFFER_VALID (1UL << 6) -/** Period buffer valid. */ -#define TC_STATUS_PERIOD_BUFFER_VALID (1UL << 7) -#endif -/** @} */ - -/** - * \brief Index of the compare capture channels. - * - * This enum is used to specify which capture/compare channel to do - * operations on. - */ -enum tc_compare_capture_channel { - /** Index of compare capture channel 0 */ - TC_COMPARE_CAPTURE_CHANNEL_0, - /** Index of compare capture channel 1 */ - TC_COMPARE_CAPTURE_CHANNEL_1, -}; - -/** - * \name TC Wave Generation Mode - * - * @{ - */ -#if SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30 -/** TC wave generation mode: normal frequency. */ -#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_WAVE_WAVEGEN_NFRQ -/** TC wave generation mode: match frequency. */ -#define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_WAVE_WAVEGEN_MFRQ -/** TC wave generation mode: normal PWM. */ -#define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_WAVE_WAVEGEN_NPWM -/** TC wave generation mode: match PWM. */ -#define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_WAVE_WAVEGEN_MPWM -#else -/** TC wave generation mode: normal frequency. */ -#define TC_WAVE_GENERATION_NORMAL_FREQ_MODE TC_CTRLA_WAVEGEN_NFRQ -/** TC wave generation mode: match frequency. */ -#define TC_WAVE_GENERATION_MATCH_FREQ_MODE TC_CTRLA_WAVEGEN_MFRQ -/** TC wave generation mode: normal PWM. */ -#define TC_WAVE_GENERATION_NORMAL_PWM_MODE TC_CTRLA_WAVEGEN_NPWM -/** TC wave generation mode: match PWM. */ -#define TC_WAVE_GENERATION_MATCH_PWM_MODE TC_CTRLA_WAVEGEN_MPWM -#endif -/** @} */ - -/** - * \brief TC wave generation mode enum. - * - * This enum is used to select which mode to run the wave - * generation in. - * - */ -enum tc_wave_generation { - /** Top is maximum, except in 8-bit counter size where it is the PER - * register - */ - TC_WAVE_GENERATION_NORMAL_FREQ = TC_WAVE_GENERATION_NORMAL_FREQ_MODE, - - /** Top is CC0, except in 8-bit counter size where it is the PER - * register - */ - TC_WAVE_GENERATION_MATCH_FREQ = TC_WAVE_GENERATION_MATCH_FREQ_MODE, - - /** Top is maximum, except in 8-bit counter size where it is the PER - * register - */ - TC_WAVE_GENERATION_NORMAL_PWM = TC_WAVE_GENERATION_NORMAL_PWM_MODE, - - /** Top is CC0, except in 8-bit counter size where it is the PER - * register - */ - TC_WAVE_GENERATION_MATCH_PWM = TC_WAVE_GENERATION_MATCH_PWM_MODE, -}; - -/** - * \brief Specifies if the counter is 8-, 16-, or 32-bit. - * - * This enum specifies the maximum value it is possible to count to. - */ -enum tc_counter_size { - /** The counter's maximum value is 0xFF, the period register is - * available to be used as top value - */ - TC_COUNTER_SIZE_8BIT = TC_CTRLA_MODE_COUNT8, - - /** The counter's maximum value is 0xFFFF. There is no separate - * period register, to modify top one of the capture compare - * registers has to be used. This limits the amount of - * available channels. - */ - TC_COUNTER_SIZE_16BIT = TC_CTRLA_MODE_COUNT16, - - /** The counter's maximum value is 0xFFFFFFFF. There is no separate - * period register, to modify top one of the capture compare - * registers has to be used. This limits the amount of - * available channels. - */ - TC_COUNTER_SIZE_32BIT = TC_CTRLA_MODE_COUNT32, -}; - -/** - * \brief TC Counter reload action enum. - * - * This enum specify how the counter and prescaler should reload. - */ -enum tc_reload_action { - /** The counter is reloaded/reset on the next GCLK and starts - * counting on the prescaler clock - */ - TC_RELOAD_ACTION_GCLK = TC_CTRLA_PRESCSYNC_GCLK, - - /** The counter is reloaded/reset on the next prescaler clock - */ - TC_RELOAD_ACTION_PRESC = TC_CTRLA_PRESCSYNC_PRESC, - - /** The counter is reloaded/reset on the next GCLK, and the - * prescaler is restarted as well - */ - TC_RELOAD_ACTION_RESYNC = TC_CTRLA_PRESCSYNC_RESYNC, -}; - -/** - * \brief TC clock prescaler values. - * - * This enum is used to choose the clock prescaler - * configuration. The prescaler divides the clock frequency of the TC - * module to make the counter count slower. - */ -enum tc_clock_prescaler { - /** Divide clock by 1 */ - TC_CLOCK_PRESCALER_DIV1 = TC_CTRLA_PRESCALER(0), - /** Divide clock by 2 */ - TC_CLOCK_PRESCALER_DIV2 = TC_CTRLA_PRESCALER(1), - /** Divide clock by 4 */ - TC_CLOCK_PRESCALER_DIV4 = TC_CTRLA_PRESCALER(2), - /** Divide clock by 8 */ - TC_CLOCK_PRESCALER_DIV8 = TC_CTRLA_PRESCALER(3), - /** Divide clock by 16 */ - TC_CLOCK_PRESCALER_DIV16 = TC_CTRLA_PRESCALER(4), - /** Divide clock by 64 */ - TC_CLOCK_PRESCALER_DIV64 = TC_CTRLA_PRESCALER(5), - /** Divide clock by 256 */ - TC_CLOCK_PRESCALER_DIV256 = TC_CTRLA_PRESCALER(6), - /** Divide clock by 1024 */ - TC_CLOCK_PRESCALER_DIV1024 = TC_CTRLA_PRESCALER(7), -}; - -/** - * \brief TC module count direction. - * - * Timer/Counter count direction. - */ -enum tc_count_direction { - /** Timer should count upward from zero to MAX */ - TC_COUNT_DIRECTION_UP, - - /** Timer should count downward to zero from MAX */ - TC_COUNT_DIRECTION_DOWN, -}; - -/** - * \name Waveform Inversion Mode - * - * @{ - */ -#if SAML21 || SAML22 || SAMC20 || SAMC21 || SAMR30 -/** Waveform inversion CC0 mode. */ -#define TC_WAVEFORM_INVERT_CC0_MODE TC_DRVCTRL_INVEN(1) -/** Waveform inversion CC1 mode. */ -#define TC_WAVEFORM_INVERT_CC1_MODE TC_DRVCTRL_INVEN(2) -#else -/** Waveform inversion CC0 mode. */ -#define TC_WAVEFORM_INVERT_CC0_MODE TC_CTRLC_INVEN(1) -/** Waveform inversion CC1 mode. */ -#define TC_WAVEFORM_INVERT_CC1_MODE TC_CTRLC_INVEN(2) -#endif - -/** - * \brief Waveform inversion mode. - * - * Output waveform inversion mode. - */ -enum tc_waveform_invert_output { - /** No inversion of the waveform output */ - TC_WAVEFORM_INVERT_OUTPUT_NONE = 0, - /** Invert output from compare channel 0 */ - TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_0 = TC_WAVEFORM_INVERT_CC0_MODE, - /** Invert output from compare channel 1 */ - TC_WAVEFORM_INVERT_OUTPUT_CHANNEL_1 = TC_WAVEFORM_INVERT_CC1_MODE, -}; - -/** - * \brief Action to perform when the TC module is triggered by an event. - * - * Event action to perform when the module is triggered by an event. - */ -enum tc_event_action { - /** No event action */ - TC_EVENT_ACTION_OFF = TC_EVCTRL_EVACT_OFF, - /** Re-trigger on event */ - TC_EVENT_ACTION_RETRIGGER = TC_EVCTRL_EVACT_RETRIGGER, - /** Increment counter on event */ - TC_EVENT_ACTION_INCREMENT_COUNTER = TC_EVCTRL_EVACT_COUNT, - /** Start counter on event */ - TC_EVENT_ACTION_START = TC_EVCTRL_EVACT_START, - - /** Store period in capture register 0, pulse width in capture - * register 1 - */ - TC_EVENT_ACTION_PPW = TC_EVCTRL_EVACT_PPW, - - /** Store pulse width in capture register 0, period in capture - * register 1 - */ - TC_EVENT_ACTION_PWP = TC_EVCTRL_EVACT_PWP, -#ifdef FEATURE_TC_STAMP_PW_CAPTURE - /** Time stamp capture */ - TC_EVENT_ACTION_STAMP = TC_EVCTRL_EVACT_STAMP, - /** Pulse width capture */ - TC_EVENT_ACTION_PW = TC_EVCTRL_EVACT_PW, -#endif -}; - -/** - * \brief TC event enable/disable structure. - * - * Event flags for the \ref tc_enable_events() and \ref tc_disable_events(). - */ -struct tc_events { - /** Generate an output event on a compare channel match */ - bool generate_event_on_compare_channel - [NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; - /** Generate an output event on counter overflow */ - bool generate_event_on_overflow; - /** Perform the configured event action when an incoming event is signalled */ - bool on_event_perform_action; - /** Specifies if the input event source is inverted, when used in PWP or - * PPW event action modes - */ - bool invert_event_input; - /** Specifies which event to trigger if an event is triggered */ - enum tc_event_action event_action; -}; - -/** - * \brief Configuration struct for TC module in 8-bit size counter mode. - */ -struct tc_8bit_config { - /** Initial timer count value */ - uint8_t value; - /** Where to count to or from depending on the direction on the counter */ - uint8_t period; - /** Value to be used for compare match on each channel */ - uint8_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -}; - -/** - * \brief Configuration struct for TC module in 16-bit size counter mode. - */ -struct tc_16bit_config { - /** Initial timer count value */ - uint16_t value; - /** Value to be used for compare match on each channel */ - uint16_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -}; - -/** - * \brief Configuration struct for TC module in 32-bit size counter mode. - */ -struct tc_32bit_config { - /** Initial timer count value */ - uint32_t value; - /** Value to be used for compare match on each channel */ - uint32_t compare_capture_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -}; - -/** - * \brief Configuration struct for TC module in 32-bit size counter mode. - */ -struct tc_pwm_channel { - /** When \c true, PWM output for the given channel is enabled */ - bool enabled; - /** Specifies pin output for each channel */ - uint32_t pin_out; - /** Specifies Multiplexer (MUX) setting for each output channel pin */ - uint32_t pin_mux; -}; - -/** - * \brief TC configuration structure. - * - * Configuration struct for a TC instance. This structure should be - * initialized by the \ref tc_get_config_defaults function before being - * modified by the user application. - */ -struct tc_config { - /** GCLK generator used to clock the peripheral */ - enum gclk_generator clock_source; - - /** When \c true the module is enabled during standby */ - bool run_in_standby; -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - /** Run on demand */ - bool on_demand; -#endif - /** Specifies either 8-, 16-, or 32-bit counter size */ - enum tc_counter_size counter_size; - /** Specifies the prescaler value for GCLK_TC */ - enum tc_clock_prescaler clock_prescaler; - /** Specifies which waveform generation mode to use */ - enum tc_wave_generation wave_generation; - - /** Specifies the reload or reset time of the counter and prescaler - * resynchronization on a re-trigger event for the TC - */ - enum tc_reload_action reload_action; - - /** Specifies which channel(s) to invert the waveform on. - For SAM L21/L22/C20/C21, it's also used to invert I/O input pin. */ - uint8_t waveform_invert_output; - - /** Specifies which channel(s) to enable channel capture - * operation on - */ - bool enable_capture_on_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -#ifdef FEATURE_TC_IO_CAPTURE - /** Specifies which channel(s) to enable I/O capture - * operation on - */ - bool enable_capture_on_IO[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; -#endif - - /** When \c true, one-shot will stop the TC on next hardware or software - * re-trigger event or overflow/underflow - */ - bool oneshot; - - /** Specifies the direction for the TC to count */ - enum tc_count_direction count_direction; - - /** Specifies the PWM channel for TC */ - struct tc_pwm_channel pwm_channel[NUMBER_OF_COMPARE_CAPTURE_CHANNELS]; - - /** Access the different counter size settings through this configuration member. */ - union { - /** Struct for 8-bit specific timer configuration */ - struct tc_8bit_config counter_8_bit; - /** Struct for 16-bit specific timer configuration */ - struct tc_16bit_config counter_16_bit; - /** Struct for 32-bit specific timer configuration */ - struct tc_32bit_config counter_32_bit; - }; - -#ifdef FEATURE_TC_DOUBLE_BUFFERED - /** Set to \c true to enable double buffering write. When enabled any write - * through \ref tc_set_top_value(), \ref tc_set_compare_value() and - * will direct to the buffer register as buffered - * value, and the buffered value will be committed to effective register - * on UPDATE condition, if update is not locked. - */ - bool double_buffering_enabled; -#endif -}; - -#if TC_ASYNC == true -/** Forward Declaration for the device instance. */ -struct tc_module; - -/** Type of the callback functions. */ -typedef void (*tc_callback_t)(struct tc_module *const module); -#endif - -/** - * \brief TC software device instance structure. - * - * TC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved for module-internal use only. - */ -struct tc_module { -#if !defined(__DOXYGEN__) - /** Hardware module pointer of the associated Timer/Counter peripheral */ - Tc *hw; - - /** Size of the initialized Timer/Counter module configuration */ - enum tc_counter_size counter_size; -# if TC_ASYNC == true - /** Array of callbacks */ - tc_callback_t callback[TC_CALLBACK_N]; - /** Bit mask for callbacks registered */ - uint8_t register_callback_mask; - /** Bit mask for callbacks enabled */ - uint8_t enable_callback_mask; -# endif -#ifdef FEATURE_TC_DOUBLE_BUFFERED - /** Set to \c true to enable double buffering write */ - bool double_buffering_enabled; -#endif -#endif -}; - -#if !defined(__DOXYGEN__) -uint8_t _tc_get_inst_index( - Tc *const hw); -#endif - -/** - * \name Driver Initialization and Configuration - * @{ - */ - -/** - * \brief Determines if the hardware module(s) are currently synchronizing to - * the bus. - * - * Checks to see if the underlying hardware peripheral module(s) are currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Synchronization status of the underlying hardware module(s). - * - * \retval false If the module has completed synchronization - * \retval true If the module synchronization is ongoing - */ -static inline bool tc_is_syncing( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - return (tc_module->SYNCBUSY.reg); -#else - return (tc_module->STATUS.reg & TC_STATUS_SYNCBUSY); -#endif -} - -/** - * \brief Initializes config with predefined default values. - * - * This function will initialize a given TC configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structures before being - * modified by the user application. - * - * The default configuration is as follows: - * \li GCLK generator 0 (GCLK main) clock source - * \li 16-bit counter size on the counter - * \li No prescaler - * \li Normal frequency wave generation - * \li GCLK reload action - * \li Don't run in standby - * \li Don't run on demand for SAM L21/L22/C20/C21 - * \li No inversion of waveform output - * \li No capture enabled - * \li No I/O capture enabled for SAM L21/L22/C20/C21 - * \li No event input enabled - * \li Count upward - * \li Don't perform one-shot operations - * \li No event action - * \li No channel 0 PWM output - * \li No channel 1 PWM output - * \li Counter starts on 0 - * \li Capture compare channel 0 set to 0 - * \li Capture compare channel 1 set to 0 - * \li No PWM pin output enabled - * \li Pin and MUX configuration not set - * \li Double buffer disabled (if have this feature) - * - * \param[out] config Pointer to a TC module configuration structure to set - */ -static inline void tc_get_config_defaults( - struct tc_config *const config) -{ - /* Sanity check arguments */ - Assert(config); - - /* Write default config to config struct */ - config->clock_source = GCLK_GENERATOR_0; - config->counter_size = TC_COUNTER_SIZE_16BIT; - config->clock_prescaler = TC_CLOCK_PRESCALER_DIV1; - config->wave_generation = TC_WAVE_GENERATION_NORMAL_FREQ; - config->reload_action = TC_RELOAD_ACTION_GCLK; - config->run_in_standby = false; -#if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) - config->on_demand = false; -#endif - config->waveform_invert_output = TC_WAVEFORM_INVERT_OUTPUT_NONE; - config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_0] = false; - config->enable_capture_on_channel[TC_COMPARE_CAPTURE_CHANNEL_1] = false; -#ifdef FEATURE_TC_IO_CAPTURE - config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_0] = false; - config->enable_capture_on_IO[TC_COMPARE_CAPTURE_CHANNEL_1] = false; -#endif - - config->count_direction = TC_COUNT_DIRECTION_UP; - config->oneshot = false; - - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].enabled = false; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_out = 0; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_0].pin_mux = 0; - - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].enabled = false; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_out = 0; - config->pwm_channel[TC_COMPARE_CAPTURE_CHANNEL_1].pin_mux = 0; - - config->counter_16_bit.value = 0x0000; - config->counter_16_bit.compare_capture_channel\ - [TC_COMPARE_CAPTURE_CHANNEL_0] = 0x0000; - config->counter_16_bit.compare_capture_channel\ - [TC_COMPARE_CAPTURE_CHANNEL_1] = 0x0000; -#ifdef FEATURE_TC_DOUBLE_BUFFERED - config->double_buffering_enabled = false; -#endif - -} - -enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config); - -/** @} */ - -/** - * \name Event Management - * @{ - */ - -/** - * \brief Enables a TC module event input or output. - * - * Enables one or more input or output events to or from the TC module. - * See \ref tc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to enable - */ -static inline void tc_enable_events( - struct tc_module *const module_inst, - struct tc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tc *const tc_module = module_inst->hw; - - uint32_t event_mask = 0; - - if (events->invert_event_input == true) { - event_mask |= TC_EVCTRL_TCINV; - } - - if (events->on_event_perform_action == true) { - event_mask |= TC_EVCTRL_TCEI; - } - - if (events->generate_event_on_overflow == true) { - event_mask |= TC_EVCTRL_OVFEO; - } - - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (events->generate_event_on_compare_channel[i] == true) { - event_mask |= (TC_EVCTRL_MCEO(1) << i); - } - } - - tc_module->COUNT8.EVCTRL.reg |= event_mask | events->event_action; -} - -/** - * \brief Disables a TC module event input or output. - * - * Disables one or more input or output events to or from the TC module. - * See \ref tc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to disable - */ -static inline void tc_disable_events( - struct tc_module *const module_inst, - struct tc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tc *const tc_module = module_inst->hw; - - uint32_t event_mask = 0; - - if (events->invert_event_input == true) { - event_mask |= TC_EVCTRL_TCINV; - } - - if (events->on_event_perform_action == true) { - event_mask |= TC_EVCTRL_TCEI; - } - - if (events->generate_event_on_overflow == true) { - event_mask |= TC_EVCTRL_OVFEO; - } - - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (events->generate_event_on_compare_channel[i] == true) { - event_mask |= (TC_EVCTRL_MCEO(1) << i); - } - } - - tc_module->COUNT8.EVCTRL.reg &= ~event_mask; -} - -/** @} */ - -/** - * \name Enable/Disable/Reset - * @{ - */ - -enum status_code tc_reset( - const struct tc_module *const module_inst); - -/** - * \brief Enable the TC module. - * - * Enables a TC module that has been previously initialized. The counter will - * start when the counter is enabled. - * - * \note When the counter is configured to re-trigger on an event, the counter - * will not start until the start function is used. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_enable( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Enable TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_ENABLE; -} - -/** - * \brief Disables the TC module. - * - * Disables a TC module and stops the counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_disable( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Disbale interrupt */ - tc_module->INTENCLR.reg = TC_INTENCLR_MASK; - /* Clear interrupt flag */ - tc_module->INTFLAG.reg = TC_INTFLAG_MASK; - - /* Disable TC module */ - tc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; -} - -/** @} */ - -/** - * \name Get/Set Count Value - * @{ - */ - -uint32_t tc_get_count_value( - const struct tc_module *const module_inst); - -enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count); - -/** @} */ - -/** - * \name Start/Stop Counter - * @{ - */ - -/** - * \brief Stops the counter. - * - * This function will stop the counter. When the counter is stopped - * the value in the count value is set to 0 if the counter was - * counting up, or maximum if the counter was counting - * down when stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_stop_counter( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_STOP_Val); -} - -/** - * \brief Starts the counter. - * - * Starts or restarts an initialized TC module's counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_start_counter( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_RETRIGGER_Val); -} - -/** @} */ - -#ifdef FEATURE_TC_DOUBLE_BUFFERED -/** - * \name Double Buffering - * @{ - */ - -/** - * \brief Update double buffer. - * - * Update double buffer. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_update_double_buffer( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_UPDATE_Val); -} -/** @} */ -#endif - -#ifdef FEATURE_TC_READ_SYNC -/** - * \name Count Read Synchronization - * @{ - */ - -/** - * \brief Read synchronization of COUNT. - * - * Read synchronization of COUNT. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_sync_read_count( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_READSYNC_Val); -} -/** @} */ -#endif - -#ifdef FEATURE_TC_GENERATE_DMA_TRIGGER -/** - * \name Generate TC DMA Triggers Command - * @{ - */ - -/** - * \brief TC DMA Trigger. - * - * TC DMA trigger command. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tc_dma_trigger_command( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tc_module->CTRLBCLR.reg = TC_CTRLBCLR_CMD_NONE; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - -#if (SAMC20) || (SAMC21) || (SAML22) || (SAML21XXXB) || (SAMR30) - /* Write command to execute */ - tc_module->CTRLBSET.reg = TC_CTRLBSET_CMD(TC_CTRLBSET_CMD_DMAOS_Val); -#endif -} -/** @} */ -#endif - -/** - * \name Get Capture Set Compare - * @{ - */ - -uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index); - -enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare_value); - -/** @} */ - -/** - * \name Set Top Value - * @{ - */ - -enum status_code tc_set_top_value( - const struct tc_module *const module_inst, - const uint32_t top_value); - -/** @} */ - -/** - * \name Status Management - * @{ - */ - -/** - * \brief Retrieves the current module status. - * - * Retrieves the status of the module, giving overall state information. - * - * \param[in] module_inst Pointer to the TC software instance struct - * - * \return Bitmask of \c TC_STATUS_* flags. - * - * \retval TC_STATUS_CHANNEL_0_MATCH Timer channel 0 compare/capture match - * \retval TC_STATUS_CHANNEL_1_MATCH Timer channel 1 compare/capture match - * \retval TC_STATUS_SYNC_READY Timer read synchronization has completed - * \retval TC_STATUS_CAPTURE_OVERFLOW Timer capture data has overflowed - * \retval TC_STATUS_COUNT_OVERFLOW Timer count value has overflowed - * \retval TC_STATUS_CHN0_BUFFER_VALID Timer count channel 0 compare/capture buffer valid - * \retval TC_STATUS_CHN1_BUFFER_VALID Timer count channel 1 compare/capture buffer valid - * \retval TC_STATUS_PERIOD_BUFFER_VALID Timer count period buffer valid - */ -static inline uint32_t tc_get_status( - struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - uint32_t int_flags = tc_module->INTFLAG.reg; - - uint32_t status_flags = 0; - - /* Check for TC channel 0 match */ - if (int_flags & TC_INTFLAG_MC(1)) { - status_flags |= TC_STATUS_CHANNEL_0_MATCH; - } - - /* Check for TC channel 1 match */ - if (int_flags & TC_INTFLAG_MC(2)) { - status_flags |= TC_STATUS_CHANNEL_1_MATCH; - } - -#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) - /* Check for TC read synchronization ready */ - if (int_flags & TC_INTFLAG_SYNCRDY) { - status_flags |= TC_STATUS_SYNC_READY; - } -#endif - - /* Check for TC capture overflow */ - if (int_flags & TC_INTFLAG_ERR) { - status_flags |= TC_STATUS_CAPTURE_OVERFLOW; - } - - /* Check for TC count overflow */ - if (int_flags & TC_INTFLAG_OVF) { - status_flags |= TC_STATUS_COUNT_OVERFLOW; - } -#ifdef FEATURE_TC_DOUBLE_BUFFERED - uint8_t double_buffer_valid_status = tc_module->STATUS.reg; - - /* Check channel 0 compare or capture buffer valid */ - if (double_buffer_valid_status & TC_STATUS_CCBUFV0) { - status_flags |= TC_STATUS_CHN0_BUFFER_VALID; - } - /* Check channel 0 compare or capture buffer valid */ - if (double_buffer_valid_status & TC_STATUS_CCBUFV1) { - status_flags |= TC_STATUS_CHN1_BUFFER_VALID; - } - /* Check period buffer valid */ - if (double_buffer_valid_status & TC_STATUS_PERBUFV) { - status_flags |= TC_STATUS_PERIOD_BUFFER_VALID; - } -#endif - - return status_flags; -} - -/** - * \brief Clears a module status flag. - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the TC software instance struct - * \param[in] status_flags Bitmask of \c TC_STATUS_* flags to clear - */ -static inline void tc_clear_status( - struct tc_module *const module_inst, - const uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - uint32_t int_flags = 0; - - /* Check for TC channel 0 match */ - if (status_flags & TC_STATUS_CHANNEL_0_MATCH) { - int_flags |= TC_INTFLAG_MC(1); - } - - /* Check for TC channel 1 match */ - if (status_flags & TC_STATUS_CHANNEL_1_MATCH) { - int_flags |= TC_INTFLAG_MC(2); - } - -#if !defined(FEATURE_TC_SYNCBUSY_SCHEME_VERSION_2) - /* Check for TC read synchronization ready */ - if (status_flags & TC_STATUS_SYNC_READY) { - int_flags |= TC_INTFLAG_SYNCRDY; - } -#endif - - /* Check for TC capture overflow */ - if (status_flags & TC_STATUS_CAPTURE_OVERFLOW) { - int_flags |= TC_INTFLAG_ERR; - } - - /* Check for TC count overflow */ - if (status_flags & TC_STATUS_COUNT_OVERFLOW) { - int_flags |= TC_INTFLAG_OVF; - } - - /* Clear interrupt flag */ - tc_module->INTFLAG.reg = int_flags; -} - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \page asfdoc_sam0_tc_extra Extra Information for TC Driver - * - * \section asfdoc_sam0_tc_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DMADirect Memory Access
TCTimer Counter
PWMPulse Width Modulation
PWPPulse Width Period
PPWPeriod Pulse Width
- * - * - * \section asfdoc_sam0_tc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_tc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_tc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Added support for SAM D21 and do some modifications as below: - * \li Clean up in the configuration structure, the counter size - * setting specific registers is accessed through the counter_8_bit, - * counter_16_bit, and counter_32_bit structures - * \li All event related settings moved into the tc_event structure
Added automatic digital clock interface enable for the slave TC - * module when a timer is initialized in 32-bit mode
Initial release
- */ - -/** - * \page asfdoc_sam0_tc_exqsg Examples for TC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_tc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_tc_basic_use_case - * - \subpage asfdoc_sam0_tc_macth_freq_use_case - * \if TC_CALLBACK_MODE - * - \subpage asfdoc_sam0_tc_timer_use_case - * - \subpage asfdoc_sam0_tc_callback_use_case - * \endif - * - \subpage asfdoc_sam0_tc_dma_use_case - * - * \page asfdoc_sam0_tc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev. - * Date - * Comments - *
42123E12/2015Added support for SAM L21/L22, SAM DA1, SAM D09, and SAM C21
42123D12/2014Added timer use case. - * Added support for SAM R21 and SAM D10/D11
42123C01/2014Added support for SAM D21
42123B06/2013Corrected documentation typos
42123A06/2013Initial document release
- */ - -#endif /* TC_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/tc/tc_interrupt.c b/atmel-samd/asf/sam0/drivers/tc/tc_interrupt.c deleted file mode 100644 index 3a5cf7e45ab7a..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tc/tc_interrupt.c +++ /dev/null @@ -1,199 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Callback Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tc_interrupt.h" - -void *_tc_instances[TC_INST_NUM]; - -void _tc_interrupt_handler(uint8_t instance); - -/** - * \brief Registers a callback. - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref tc_enable_callback, - * in order for the interrupt handler to call it when the conditions for the - * callback type is met. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - */ -enum status_code tc_register_callback( - struct tc_module *const module, - tc_callback_t callback_func, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); - - /* Register callback function */ - module->callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->register_callback_mask |= TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->register_callback_mask |= TC_INTFLAG_MC(2); - } - else { - module->register_callback_mask |= (1 << callback_type); - } - return STATUS_OK; -} - -/** - * \brief Unregisters a callback. - * - * Unregisters a callback function implemented by the user. The callback should be - * disabled before it is unregistered. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -enum status_code tc_unregister_callback( - struct tc_module *const module, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Unregister callback function */ - module->callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->register_callback_mask &= ~TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->register_callback_mask &= ~TC_INTFLAG_MC(2); - } - else { - module->register_callback_mask &= ~(1 << callback_type); - } - return STATUS_OK; -} - -/** - * \internal ISR handler for TC - * - * Auto-generate a set of interrupt handlers for each TC in the device. - */ -#define _TC_INTERRUPT_HANDLER(n, m) \ - void TC##n##_Handler(void) \ - { \ - _tc_interrupt_handler(m); \ - } - -#if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G) - _TC_INTERRUPT_HANDLER(0,0) - _TC_INTERRUPT_HANDLER(1,1) - _TC_INTERRUPT_HANDLER(4,2) -#else - MRECURSION(TC_INST_NUM, _TC_INTERRUPT_HANDLER, TC_INST_MAX_ID) -#endif - - -/** - * \internal Interrupt Handler for TC module - * - * Handles interrupts as they occur, it will run the callback functions - * that are registered and enabled. - * - * \param[in] instance ID of the TC instance calling the interrupt - * handler - */ -void _tc_interrupt_handler( - uint8_t instance) -{ - /* Temporary variable */ - uint8_t interrupt_and_callback_status_mask; - - /* Get device instance from the look-up table */ - struct tc_module *module - = (struct tc_module *)_tc_instances[instance]; - - /* Read and mask interrupt flag register */ - interrupt_and_callback_status_mask = module->hw->COUNT8.INTFLAG.reg & - module->register_callback_mask & - module->enable_callback_mask; - - /* Check if an Overflow interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_OVF) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_OVERFLOW])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; - } - - /* Check if an Error interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_ERR) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_ERROR])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; - } - - /* Check if an Match/Capture Channel 0 interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(1)) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_CC_CHANNEL0])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(1); - } - - /* Check if an Match/Capture Channel 1 interrupt has occurred */ - if (interrupt_and_callback_status_mask & TC_INTFLAG_MC(2)) { - /* Invoke registered and enabled callback function */ - (module->callback[TC_CALLBACK_CC_CHANNEL1])(module); - /* Clear interrupt flag */ - module->hw->COUNT8.INTFLAG.reg = TC_INTFLAG_MC(2); - } -} diff --git a/atmel-samd/asf/sam0/drivers/tc/tc_interrupt.h b/atmel-samd/asf/sam0/drivers/tc/tc_interrupt.h deleted file mode 100644 index 56c7264ad7858..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tc/tc_interrupt.h +++ /dev/null @@ -1,179 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Callback Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TC_INTERRUPT_H_INCLUDED -#define TC_INTERRUPT_H_INCLUDED - -#include "tc.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__DOXYGEN__) -extern void *_tc_instances[TC_INST_NUM]; - -# define _TC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TC##n, -/** - * \internal Get the interrupt vector for the given device instance - * - * \param[in] TC module instance number - * - * \return Interrupt vector for of the given TC module instance. - */ -static enum system_interrupt_vector _tc_interrupt_get_interrupt_vector( - uint32_t inst_num) -{ - static uint8_t tc_interrupt_vectors[TC_INST_NUM] = - { -#if (SAML21E) || (SAML21G) || (SAMR30E) || (SAMR30G) - SYSTEM_INTERRUPT_MODULE_TC0, - SYSTEM_INTERRUPT_MODULE_TC1, - SYSTEM_INTERRUPT_MODULE_TC4 -#else - MRECURSION(TC_INST_NUM, _TC_INTERRUPT_VECT_NUM, TC_INST_MAX_ID) -#endif - }; - - return (enum system_interrupt_vector)tc_interrupt_vectors[inst_num]; -} -#endif /* !defined(__DOXYGEN__) */ - -/** - * \name Callback Management - * {@ - */ - -enum status_code tc_register_callback( - struct tc_module *const module, - tc_callback_t callback_func, - const enum tc_callback callback_type); - -enum status_code tc_unregister_callback( - struct tc_module *const module, - const enum tc_callback callback_type); - -/** - * \brief Enables callback. - * - * Enables the callback function registered by the \ref - * tc_register_callback. The callback function will be called from the - * interrupt handler when the conditions for the callback type are - * met. This function will also enable the appropriate interrupts. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void tc_enable_callback( - struct tc_module *const module, - const enum tc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - - /* Enable interrupts for this TC module */ - system_interrupt_enable(_tc_interrupt_get_interrupt_vector(_tc_get_inst_index(module->hw))); - - /* Enable callback */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->enable_callback_mask |= TC_INTFLAG_MC(1); - module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->enable_callback_mask |= TC_INTFLAG_MC(2); - module->hw->COUNT8.INTENSET.reg = TC_INTFLAG_MC(2); - } - else { - module->enable_callback_mask |= (1 << callback_type); - module->hw->COUNT8.INTENSET.reg = (1 << callback_type); - } -} - -/** - * \brief Disables callback. - * - * Disables the callback function registered by the \ref - * tc_register_callback, and the callback will not be called from the - * interrupt routine. The function will also disable the appropriate - * interrupts. - * - * \param[in] module Pointer to TC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -static inline void tc_disable_callback( - struct tc_module *const module, - const enum tc_callback callback_type){ - /* Sanity check arguments */ - Assert(module); - - /* Disable callback */ - if (callback_type == TC_CALLBACK_CC_CHANNEL0) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(1); - module->enable_callback_mask &= ~TC_INTFLAG_MC(1); - } - else if (callback_type == TC_CALLBACK_CC_CHANNEL1) { - module->hw->COUNT8.INTENCLR.reg = TC_INTFLAG_MC(2); - module->enable_callback_mask &= ~TC_INTFLAG_MC(2); - } - else { - module->hw->COUNT8.INTENCLR.reg = (1 << callback_type); - module->enable_callback_mask &= ~(1 << callback_type); - } -} - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* TC_INTERRUPT_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/tc/tc_sam_d_r/tc.c b/atmel-samd/asf/sam0/drivers/tc/tc_sam_d_r/tc.c deleted file mode 100644 index 3d4a428b7c3e2..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tc/tc_sam_d_r/tc.c +++ /dev/null @@ -1,685 +0,0 @@ -/** - * \file - * - * \brief SAM TC - Timer Counter Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tc.h" - -#if TC_ASYNC == true -# include "tc_interrupt.h" -# include - -/** \internal - * Converts a given TC index to its interrupt vector index. - */ -# define _TC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TC##n, -#endif - -#if !defined(__DOXYGEN__) -# define _TC_GCLK_ID(n,unused) TPASTE3(TC,n,_GCLK_ID) , -# define _TC_PM_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TC,n) , - -# define TC_INST_GCLK_ID { MRECURSION(TC_INST_NUM, _TC_GCLK_ID, TC_INST_MAX_ID) } -# define TC_INST_PM_APBCMASK { MRECURSION(TC_INST_NUM, _TC_PM_APBCMASK, TC_INST_MAX_ID) } - -#endif - -/** - * \internal Find the index of given TC module instance. - * - * \param[in] TC module instance pointer - * - * \return Index of the given TC module instance. - */ -uint8_t _tc_get_inst_index( - Tc *const hw) -{ - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if (hw == tc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} - - -/** - * \brief Initializes a hardware TC module instance. - * - * Enables the clock and initializes the TC module, based on the given - * configuration values. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the TC hardware module - * \param[in] config Pointer to the TC configuration options struct - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY Hardware module was busy when the - * initialization procedure was attempted - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the - * hardware module is configured in 32-bit - * slave mode - */ -enum status_code tc_init( - struct tc_module *const module_inst, - Tc *const hw, - const struct tc_config *const config) -{ - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(config); - - /* Temporary variable to hold all updates to the CTRLA - * register before they are written to it */ - uint16_t ctrla_tmp = 0; - /* Temporary variable to hold all updates to the CTRLBSET - * register before they are written to it */ - uint8_t ctrlbset_tmp = 0; - /* Temporary variable to hold all updates to the CTRLC - * register before they are written to it */ - uint8_t ctrlc_tmp = 0; - /* Temporary variable to hold TC instance number */ - uint8_t instance = _tc_get_inst_index(hw); - - /* Array of GLCK ID for different TC instances */ - uint8_t inst_gclk_id[] = TC_INST_GCLK_ID; - /* Array of PM APBC mask bit position for different TC instances */ - uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK; - - //struct system_pinmux_config pin_config; - struct system_gclk_chan_config gclk_chan_config; - -#if TC_ASYNC == true - /* Initialize parameters */ - for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { - module_inst->callback[i] = NULL; - } - module_inst->register_callback_mask = 0x00; - module_inst->enable_callback_mask = 0x00; - - /* Register this instance for callbacks*/ - _tc_instances[instance] = module_inst; -#endif - - /* Associate the given device instance with the hardware module */ - module_inst->hw = hw; - -#if SAMD09 || SAMD10 || SAMD11 - /* Check if even numbered TC modules are being configured in 32-bit - * counter size. Only odd numbered counters are allowed to be - * configured in 32-bit counter size. - */ - if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - !((instance + TC_INSTANCE_OFFSET) & 0x01)) { - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -#else - // /* Check if odd numbered TC modules are being configured in 32-bit - // * counter size. Only even numbered counters are allowed to be - // * configured in 32-bit counter size. - // */ - // if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && - // ((instance + TC_INSTANCE_OFFSET) & 0x01)) { - // Assert(false); - // return STATUS_ERR_INVALID_ARG; - // } -#endif - - /* Make the counter size variable in the module_inst struct reflect - * the counter size in the module - */ - module_inst->counter_size = config->counter_size; - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { - /* We are in the middle of a reset. Abort. */ - return STATUS_BUSY; - } - - if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { - /* Module is used as a slave */ - return STATUS_ERR_DENIED; - } - - if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { - /* Module must be disabled before initialization. Abort. */ - return STATUS_ERR_DENIED; - } - - // /* Set up the TC PWM out pin for channel 0 */ - // if (config->pwm_channel[0].enabled) { - // system_pinmux_get_config_defaults(&pin_config); - // pin_config.mux_position = config->pwm_channel[0].pin_mux; - // pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - // system_pinmux_pin_set_config( - // config->pwm_channel[0].pin_out, &pin_config); - // } - // - // /* Set up the TC PWM out pin for channel 1 */ - // if (config->pwm_channel[1].enabled) { - // system_pinmux_get_config_defaults(&pin_config); - // pin_config.mux_position = config->pwm_channel[1].pin_mux; - // pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - // system_pinmux_pin_set_config( - // config->pwm_channel[1].pin_out, &pin_config); - // } - - /* Enable the user interface clock in the PM */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - inst_pm_apbmask[instance]); - - // /* Enable the slave counter if counter_size is 32-bit */ - // if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) - // { - // /* Enable the user interface clock in the PM */ - // system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - // inst_pm_apbmask[instance + 1]); - // } - - /* Setup clock for module */ - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->clock_source; - system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); - system_gclk_chan_enable(inst_gclk_id[instance]); - - /* Set ctrla register */ - ctrla_tmp = - (uint32_t)config->counter_size | - (uint32_t)config->wave_generation | - (uint32_t)config->reload_action | - (uint32_t)config->clock_prescaler; - - if (config->run_in_standby) { - ctrla_tmp |= TC_CTRLA_RUNSTDBY; - } - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLA.reg = ctrla_tmp; - - /* Set ctrlb register */ - if (config->oneshot) { - ctrlbset_tmp = TC_CTRLBSET_ONESHOT; - } - - if (config->count_direction) { - ctrlbset_tmp |= TC_CTRLBSET_DIR; - } - - /* Clear old ctrlb configuration */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLBCLR.reg = 0xFF; - - /* Check if we actually need to go into a wait state. */ - if (ctrlbset_tmp) { - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - /* Write configuration to register */ - hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; - } - - /* Set ctrlc register*/ - ctrlc_tmp = config->waveform_invert_output; - for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { - if (config->enable_capture_on_channel[i] == true) { - ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i); - } - } - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - hw->COUNT8.CTRLC.reg = ctrlc_tmp; - - /* Write configuration to register */ - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Switch for TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - // while (tc_is_syncing(module_inst)) { - // /* Wait for sync */ - // } - // - // hw->COUNT8.COUNT.reg = - // config->counter_8_bit.value; - // - // - // while (tc_is_syncing(module_inst)) { - // /* Wait for sync */ - // } - // - // hw->COUNT8.PER.reg = - // config->counter_8_bit.period; - // - // while (tc_is_syncing(module_inst)) { - // /* Wait for sync */ - // } - // - // hw->COUNT8.CC[0].reg = - // config->counter_8_bit.compare_capture_channel[0]; - // - // while (tc_is_syncing(module_inst)) { - // /* Wait for sync */ - // } - // - // hw->COUNT8.CC[1].reg = - // config->counter_8_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.COUNT.reg - = config->counter_16_bit.value; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[0].reg = - config->counter_16_bit.compare_capture_channel[0]; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - hw->COUNT16.CC[1].reg = - config->counter_16_bit.compare_capture_channel[1]; - - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - // while (tc_is_syncing(module_inst)) { - // /* Wait for sync */ - // } - // - // hw->COUNT32.COUNT.reg - // = config->counter_32_bit.value; - // - // while (tc_is_syncing(module_inst)) { - // /* Wait for sync */ - // } - // - // hw->COUNT32.CC[0].reg = - // config->counter_32_bit.compare_capture_channel[0]; - // - // while (tc_is_syncing(module_inst)) { - // /* Wait for sync */ - // } - // - // hw->COUNT32.CC[1].reg = - // config->counter_32_bit.compare_capture_channel[1]; - - return STATUS_OK; - } - - Assert(false); - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Sets TC module count value. - * - * Sets the current timer count value of a initialized TC module. The - * specified TC module may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] count New timer count value to set - * - * \return Status of the count update procedure. - * - * \retval STATUS_OK The timer count was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified - */ -enum status_code tc_set_count_value( - const struct tc_module *const module_inst, - const uint32_t count) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Write to based on the TC counter_size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.COUNT.reg = (uint8_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.COUNT.reg = (uint16_t)count; - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.COUNT.reg = (uint32_t)count; - return STATUS_OK; - - default: - return STATUS_ERR_INVALID_ARG; - } -} - -/** - * \brief Get TC module count value. - * - * Retrieves the current count value of a TC module. The specified TC module - * may be started or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Count value of the specified TC module. - */ -uint32_t tc_get_count_value( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read from based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - return (uint32_t)tc_module->COUNT8.COUNT.reg; - - case TC_COUNTER_SIZE_16BIT: - return (uint32_t)tc_module->COUNT16.COUNT.reg; - - case TC_COUNTER_SIZE_32BIT: - return tc_module->COUNT32.COUNT.reg; - } - - Assert(false); - return 0; -} - -/** - * \brief Gets the TC module capture value. - * - * Retrieves the capture value in the indicated TC module capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the Compare Capture channel to read - * - * \return Capture value stored in the specified timer channel. - */ -uint32_t tc_get_capture_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT8.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT16.CC[channel_index].reg; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - return tc_module->COUNT32.CC[channel_index].reg; - } - } - - Assert(false); - return 0; -} - -/** - * \brief Sets a TC module compare value. - * - * Writes a compare value to the given TC module compare/capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied - */ -enum status_code tc_set_compare_value( - const struct tc_module *const module_inst, - const enum tc_compare_capture_channel channel_index, - const uint32_t compare) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - /* Read out based on the TC counter size */ - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT8.CC[channel_index].reg = - (uint8_t)compare; - return STATUS_OK; - } - - case TC_COUNTER_SIZE_16BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT16.CC[channel_index].reg = - (uint16_t)compare; - return STATUS_OK; - } - - case TC_COUNTER_SIZE_32BIT: - if (channel_index < - NUMBER_OF_COMPARE_CAPTURE_CHANNELS) { - tc_module->COUNT32.CC[channel_index].reg = - (uint32_t)compare; - return STATUS_OK; - } - } - - return STATUS_ERR_INVALID_ARG; -} - -/** - * \brief Resets the TC module. - * - * Resets the TC module, restoring all hardware module registers to their - * default values and disabling the module. The TC module will not be - * accessible while the reset is being performed. - * - * \note When resetting a 32-bit counter only the master TC module's instance - * structure should be passed to the function. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Status of the procedure. - * \retval STATUS_OK The module was reset successfully - * \retval STATUS_ERR_UNSUPPORTED_DEV A 32-bit slave TC module was passed to - * the function. Only use reset on master - * TC - */ -enum status_code tc_reset( - const struct tc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module hardware instance */ - TcCount8 *const tc_module = &(module_inst->hw->COUNT8); - - if (tc_module->STATUS.reg & TC_STATUS_SLAVE) { - return STATUS_ERR_UNSUPPORTED_DEV; - } - - /* Disable this module if it is running */ - if (tc_module->CTRLA.reg & TC_CTRLA_ENABLE) { - tc_disable(module_inst); - while (tc_is_syncing(module_inst)) { - /* wait while module is disabling */ - } - } - - /* Reset this TC module */ - tc_module->CTRLA.reg |= TC_CTRLA_SWRST; - - return STATUS_OK; -} - -/** - * \brief Set the timer TOP/period value. - * - * For 8-bit counter size this function writes the top value to the period - * register. - * - * For 16- and 32-bit counter size this function writes the top value to - * Capture Compare register 0. The value in this register can not be used for - * any other purpose. - * - * \note This function is designed to be used in PWM or frequency - * match modes only, when the counter is set to 16- or 32-bit counter - * size. In 8-bit counter size it will always be possible to change the - * top value even in normal mode. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New timer TOP value to set - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG The configured TC module counter size in the - * module instance is invalid - */ -enum status_code tc_set_top_value ( - const struct tc_module *const module_inst, - const uint32_t top_value) -{ - Assert(module_inst); - Assert(module_inst->hw); - Assert(top_value); - - Tc *const tc_module = module_inst->hw; - - while (tc_is_syncing(module_inst)) { - /* Wait for sync */ - } - - switch (module_inst->counter_size) { - case TC_COUNTER_SIZE_8BIT: - tc_module->COUNT8.PER.reg = (uint8_t)top_value; - return STATUS_OK; - - case TC_COUNTER_SIZE_16BIT: - tc_module->COUNT16.CC[0].reg = (uint16_t)top_value; - return STATUS_OK; - - case TC_COUNTER_SIZE_32BIT: - tc_module->COUNT32.CC[0].reg = (uint32_t)top_value; - return STATUS_OK; - - default: - Assert(false); - return STATUS_ERR_INVALID_ARG; - } -} diff --git a/atmel-samd/asf/sam0/drivers/tcc/docimg/overview.svg b/atmel-samd/asf/sam0/drivers/tcc/docimg/overview.svg deleted file mode 100644 index b3d7ef0b38fa7..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tcc/docimg/overview.svg +++ /dev/null @@ -1,2278 +0,0 @@ - - - - - TCC_Block - - - - - image/svg+xml - - TCC_Block - - - - - - - - Base Counter - - - - - - - - - Compare - / - Capture - ( - Unit x - = - { - 0 - , - 1 - , - … - , - 3 - } - ) - - - Counter - - - - - - - = - - - CCx - - - CCBx - - - - - - - Waveform - Generation - - - - - - - - - - - - BV - - - - - = - - - PER - B - - - PER - - - COUNT - - - BV - - - = - 0 - " - count - " - " - clear - " - " - direction - " - " - load - " - - - - - - - - - - - Control Logic - - - Prescaler - - - OVF - ( - INT - / - Event - / - DMA Req - .) - - - ERR - ( - INT Req - .) - TOP - " - match - " - - - - - - - - - MC - x - ( - INT - / - Event - / - DMA Req - .) - - - - - Control Logic - " - capture - " - - - - - - - " - e - v - " - U - P - D - A - T - E - BOTTOM - - - - - - - - Recoverable - Faults - - - - - - - O - u - t - p - u - t - M - a - t - r - i - x - - - - D - e - a - d - - - T - i - m - e - I - n - s - e - r - t - i - o - n - - - SWAP - - P - a - t - t - e - r - n - G - e - n - e - r - a - t - i - o - n - - N - o - n - - - r - e - c - o - v - e - r - a - b - l - e - F - a - u - l - t - s - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - WO - [ - 0 - ] - WO - [ - 1 - ] - WO - [ - 2 - ] - WO - [ - 3 - ] - WO - [ - 4 - ] - WO - [ - 5 - ] - WO - [ - 6 - ] - WO - [ - 7 - ] - - - Event - System - - - "TCCx_EV0" - - - - - - - - - "TCCx_EV1" - "TCCx_MCx" - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/atmel-samd/asf/sam0/drivers/tcc/docimg/pwm_match_ex.svg b/atmel-samd/asf/sam0/drivers/tcc/docimg/pwm_match_ex.svg deleted file mode 100644 index dbce68d31fb96..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tcc/docimg/pwm_match_ex.svg +++ /dev/null @@ -1,1464 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - Master slide - - - - - - - - - - - - - - - T - i - m - e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - R - e - l - o - a - d - - t - o - - T - O - P - - v - a - l - u - e - - - - - - - - - - - - - - - - - - C - o - u - n - t - - i - s - - w - r - i - t - t - e - n - - - - - - - - - - - - - - - - T - O - P - - v - a - l - u - e - - h - a - s - - b - e - e - n - - c - h - a - n - g - e - d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - M - a - t - c - h - - - - - - - - - P - W - M - - i - n - v - e - r - t - e - d - - o - u - t - p - u - t - - - - - - M - a - x - - - - - - C - o - u - n - t - e - r - - v - a - l - u - e - - - - - - - - - - - - - - - - - - - - - - - (COUNT) - (CC0) - (CC0) - (COUNT) - Compare/Matchvalue(CCx) - - diff --git a/atmel-samd/asf/sam0/drivers/tcc/docimg/pwm_single_ex.svg b/atmel-samd/asf/sam0/drivers/tcc/docimg/pwm_single_ex.svg deleted file mode 100644 index 8450d04408125..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tcc/docimg/pwm_single_ex.svg +++ /dev/null @@ -1,1387 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - Master slide - - - - - - - C - o - u - n - t - e - r - - v - a - l - u - e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - T - i - m - e - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - M - a - t - c - h - - - - - - - - - - - - - - - - - - - - - - - - P - W - M - - o - u - t - p - u - t - - - - - - R - e - l - o - a - d - - c - o - u - n - t - e - r - - t - o - - z - e - r - o - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C - o - m - p - a - r - e - - v - a - l - u - e - - h - a - s - - b - e - e - n - - c - h - a - n - g - e - d - - - - - - - - - - - - - - - - - - - - - - - TOP/Period= Max(PER) - - - - - Compare/Matchvalue(CCx) - - - - - - (CCx) - (COUNT) - - diff --git a/atmel-samd/asf/sam0/drivers/tcc/tcc.c b/atmel-samd/asf/sam0/drivers/tcc/tcc.c deleted file mode 100644 index e46cf287aea42..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tcc/tcc.c +++ /dev/null @@ -1,1604 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - Timer Counter for Control Applications Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tcc.h" - -#if TCC_ASYNC == true -# include "tcc_callback.h" -# include - -/** \internal - * Converts a given TCC index to its interrupt vector index. - */ -# define _TCC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TCC##n, -#endif - -#define _SIZE_MAX(size) ((size==32u) ? 0xFFFFFFFF : ( \ - (1u << size) - 1)) - -#define _SIZE_MAX_WITH_DITHER 0x03FFFFFF - -/* Extension support mapping bits */ -#define _TCC_DITHERING_B 16u -#define _TCC_PG_B 8u -#define _TCC_SWAP_B 4u -#define _TCC_DTI_B 2u -#define _TCC_OTMX_B 1u - -#if !defined(__DOXYGEN__) - -# define _TCC_GCLK_ID(n,unused) TPASTE3(TCC,n,_GCLK_ID), -# if (SAML21) || (SAML22) || (SAMC20) || (SAMC21) || (SAMR30) -# define _TCC_APBCMASK(n,unused) TPASTE2(MCLK_APBCMASK_TCC,n), -# else -# define _TCC_APBCMASK(n,unused) TPASTE2(PM_APBCMASK_TCC,n), -# endif - -# define _TCC_SIZE(n,unused) TPASTE3(TCC,n,_SIZE), -# define _TCC_MAX(n,unused) _SIZE_MAX(TPASTE3(TCC,n,_SIZE)), -# define _TCC_EXT(n,unused) TPASTE3(TCC,n,_EXT), -# define _TCC_CC_NUM(n,unused) min(TPASTE3(TCC,n,_CC_NUM),TCC_NUM_CHANNELS), -# define _TCC_OW_NUM(n,unused) min(TPASTE3(TCC,n,_OW_NUM),TCC_NUM_WAVE_OUTPUTS), - -# define TCC_GCLK_IDS { MREPEAT(TCC_INST_NUM, _TCC_GCLK_ID, 0) } -# define TCC_APBCMASKS { MREPEAT(TCC_INST_NUM, _TCC_APBCMASK, 0) } - -# define TCC_SIZES { MREPEAT(TCC_INST_NUM, _TCC_SIZE, 0) } -# define TCC_MAXS { MREPEAT(TCC_INST_NUM, _TCC_MAX, 0) } -# define TCC_EXTS { MREPEAT(TCC_INST_NUM, _TCC_EXT, 0) } -# define TCC_CC_NUMS { MREPEAT(TCC_INST_NUM, _TCC_CC_NUM, 0) } -# define TCC_OW_NUMS { MREPEAT(TCC_INST_NUM, _TCC_OW_NUM, 0) } - -#endif - -/* List of available TCC modules. */ -const Tcc *const tcc_modules[TCC_INST_NUM] = TCC_INSTS; - -/* List of TCC GCLK IDs */ -const uint8_t _tcc_gclk_ids[TCC_INST_NUM] = TCC_GCLK_IDS; - -/* List of TCC APBC Masks */ -const uint32_t _tcc_apbcmasks[TCC_INST_NUM] = TCC_APBCMASKS; - -/* List of extension support of TCC modules. */ -const uint8_t _tcc_exts[TCC_INST_NUM] = TCC_EXTS; - -/* List of sizes support of TCC modules. */ -const uint8_t _tcc_sizes[TCC_INST_NUM] = TCC_SIZES; - -/* List of maximumvalues supported of TCC modules. */ -const uint32_t _tcc_maxs[TCC_INST_NUM] = TCC_MAXS; - -/* List of available channel number of TCC modules. */ -const uint8_t _tcc_cc_nums[TCC_INST_NUM] = TCC_CC_NUMS; - -/* List of available output number of TCC modules. */ -const uint8_t _tcc_ow_nums[TCC_INST_NUM] = TCC_OW_NUMS; - -/** - * \internal Find the index of the given TCC module instance. - * - * \param[in] The TCC module instance pointer - * - * \return Index of the given TCC module instance. - */ -uint8_t _tcc_get_inst_index( - Tcc *const hw) -{ - /* Find index for TCC instance. */ - for (uint32_t i = 0; i < TCC_INST_NUM; i++) { - if (hw == tcc_modules[i]) { - return i; - } - } - - /* Invalid data given. */ - Assert(false); - return 0; -} - -/** - * \brief Initializes config with predefined default values. - * - * This function will initialize a given TCC configuration structure to - * a set of known default values. This function should be called on - * any new instance of the configuration structures before being - * modified by the user application. - * - * The default configuration is as follows: - * \li Don't run in standby - * \li When setting top, compare, or pattern by API, do double buffering write - * \li The base timer/counter configurations: - * - GCLK generator 0 clock source - * - No prescaler - * - GCLK reload action - * - Count upward - * - Don't perform one-shot operations - * - Counter starts on 0 - * - Period/top value set to maximum - * \li The match/capture configurations: - * - All Capture compare channel value set to 0 - * - No capture enabled (all channels use compare function) - * - Normal frequency wave generation - * - Waveform generation polarity set to 0 - * - Don't perform ramp on waveform - * \li The waveform extension configurations: - * - No recoverable fault is enabled, fault actions are disabled, filter - * is set to 0 - * - No non-recoverable fault state output is enabled and filter is 0 - * - No inversion of waveform output - * \li No channel output enabled - * \li No PWM pin output enabled - * \li Pin and MUX configuration not set - * - * \param[out] config Pointer to a TCC module configuration structure to set - * \param[in] hw Pointer to the TCC hardware module - * - */ -void tcc_get_config_defaults( - struct tcc_config *const config, - Tcc *const hw) -{ - /* TCC instance index */ - uint8_t module_index = _tcc_get_inst_index(hw); - - /* Base counter defaults */ - config->counter.count = 0; - - config->counter.period = _tcc_maxs[module_index]; - - config->counter.clock_source = GCLK_GENERATOR_0; - config->counter.clock_prescaler = TCC_CLOCK_PRESCALER_DIV1; - config->counter.reload_action = TCC_RELOAD_ACTION_GCLK; - - config->counter.direction = TCC_COUNT_DIRECTION_UP; - config->counter.oneshot = false; - -#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER - config->counter.dma_trigger_mode = TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE; -#endif - - /* Match/Capture defaults */ -# define _TCC_CHANNEL_MATCH_VALUE_INIT(n, value) \ - config->compare.match[n] = value; - MREPEAT(TCC_NUM_CHANNELS, - _TCC_CHANNEL_MATCH_VALUE_INIT, 0) -# undef _TCC_CHANNEL_MATCH_VALUE_INIT - - /* Wave polarity defaults */ -# define _TCC_CHANNEL_WAVE_POLARITY_INIT(n, value) \ - config->compare.wave_polarity[n] = value; - MREPEAT(TCC_NUM_CHANNELS, - _TCC_CHANNEL_WAVE_POLARITY_INIT, TCC_WAVE_POLARITY_0) -# undef _TCC_CHANNEL_WAVE_POLARITY_INIT - - config->compare.wave_generation = TCC_WAVE_GENERATION_NORMAL_FREQ; - config->compare.wave_ramp = TCC_RAMP_RAMP1; - -# define _TCC_CHANNEL_FUNCTION_INIT(n, value) \ - config->compare.channel_function[n] = value; - MREPEAT(TCC_NUM_CHANNELS, - _TCC_CHANNEL_FUNCTION_INIT, TCC_CHANNEL_FUNCTION_COMPARE) -# undef _TCC_CHANNEL_FUNCTION_INIT - - /* Recoverable fault defaults */ -# define _TCC_FAULT_FUNCTION_INIT(n, dummy) \ - config->wave_ext.recoverable_fault[n].filter_value = 0; \ - config->wave_ext.recoverable_fault[n].blanking_cycles = 0; \ - config->wave_ext.recoverable_fault[n].restart = false; \ - config->wave_ext.recoverable_fault[n].keep = false; \ - config->wave_ext.recoverable_fault[n].qualification = false; \ - config->wave_ext.recoverable_fault[n].source = TCC_FAULT_SOURCE_DISABLE; \ - config->wave_ext.recoverable_fault[n].blanking = TCC_FAULT_BLANKING_DISABLE; \ - config->wave_ext.recoverable_fault[n].halt_action = TCC_FAULT_HALT_ACTION_DISABLE; \ - config->wave_ext.recoverable_fault[n].capture_action = TCC_FAULT_CAPTURE_DISABLE; \ - config->wave_ext.recoverable_fault[n].capture_channel = TCC_FAULT_CAPTURE_CHANNEL_0; - MREPEAT(TCC_NUM_FAULTS, _TCC_FAULT_FUNCTION_INIT, 0) -# undef _TCC_FAULT_FUNCTION_INIT - - /* Non-recoverable fault defaults */ -# define _TCC_NRF_FUNCTION_INIT(n, dummy) \ - config->wave_ext.non_recoverable_fault[n].filter_value = 0; \ - config->wave_ext.non_recoverable_fault[n].output = TCC_FAULT_STATE_OUTPUT_OFF; - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_NRF_FUNCTION_INIT, 0) -# undef _TCC_NRF_FUNCTION_INIT - - /* Output inversion defaults */ -# define _TCC_OUT_INVERT_INIT(n, value) \ - config->wave_ext.invert[n] = value; - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_OUT_INVERT_INIT, false) -# undef _TCC_OUT_INVERT_INIT - -# define _TCC_CHANNEL_OUT_PIN_INIT(n, dummy) \ - config->pins.enable_wave_out_pin[n] = false;\ - config->pins.wave_out_pin[TCC_WAVE_OUTPUT_##n] = 0; \ - config->pins.wave_out_pin_mux[TCC_WAVE_OUTPUT_##n] = 0; - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_CHANNEL_OUT_PIN_INIT, 0) -# undef _TCC_CHANNEL_OUT_PIN_INIT - - config->double_buffering_enabled = true; - config->run_in_standby = false; -} - - -/** - * \brief Build CTRLA register value from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - * - * \return Configuration validation status. - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: - * assigned dither mode is invalid for module; - * used capture channel is invalid for module - */ -static inline enum status_code _tcc_build_ctrla( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - uint32_t ctrla = 0; - - int i; - for (i = 0; i < TCC_NUM_CHANNELS; i ++) { - if (config->capture.channel_function[i] == - TCC_CHANNEL_FUNCTION_CAPTURE) { - - if (i > _tcc_cc_nums[module_index]) { - /* Channel not supported */ - return STATUS_ERR_INVALID_ARG; - } - ctrla |= (TCC_CTRLA_CPTEN0 << i); - } - } - - if (config->run_in_standby) { - ctrla |= TCC_CTRLA_RUNSTDBY; - } - ctrla |= config->counter.reload_action << TCC_CTRLA_PRESCSYNC_Pos; - ctrla |= config->counter.clock_prescaler << TCC_CTRLA_PRESCALER_Pos; - - *value_buffer = ctrla; - return STATUS_OK; -} - -/** - * \brief Build CTRLB register value from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - */ -static inline void _tcc_build_ctrlb( - const uint8_t module_index, - const struct tcc_config *const config, - uint8_t *value_buffer) -{ - uint8_t ctrlb = 0; - - // if (config->counter.oneshot) { - // ctrlb |= TCC_CTRLBSET_ONESHOT; - // } - // if (config->counter.direction == TCC_COUNT_DIRECTION_DOWN) { - // ctrlb |= TCC_CTRLBSET_DIR; - // } - - *value_buffer = ctrlb; -} - -/** - * \brief Build FAULTs register values from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built values - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned fault - * capture channel is invalid; assigned filter - * value is invalid - */ -static inline enum status_code _tcc_build_faults( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - struct tcc_recoverable_fault_config *cfg; - uint8_t cc_num = _tcc_cc_nums[module_index]; - uint32_t fault; - int i; - for (i = 0; i < TCC_NUM_FAULTS; i ++) { - cfg = (struct tcc_recoverable_fault_config *) - &config->wave_ext.recoverable_fault[i]; - if (cfg->capture_channel >= cc_num) { - return STATUS_ERR_INVALID_ARG; - } - if (cfg->filter_value > 0xF) { - return STATUS_ERR_INVALID_ARG; - } - fault = TCC_FCTRLA_FILTERVAL(cfg->filter_value) - | TCC_FCTRLA_BLANKVAL(cfg->blanking_cycles) - | (cfg->restart ? TCC_FCTRLA_RESTART : 0) - | (cfg->keep ? TCC_FCTRLA_KEEP : 0) - | (cfg->qualification ? TCC_FCTRLA_QUAL : 0) - | TCC_FCTRLA_SRC(cfg->source) - | TCC_FCTRLA_BLANK(cfg->blanking) - | TCC_FCTRLA_HALT(cfg->halt_action) - | TCC_FCTRLA_CAPTURE(cfg->capture_action) - | TCC_FCTRLA_CHSEL(cfg->capture_channel); - value_buffer[i] = fault; - } - return STATUS_OK; -} - -/** - * \brief Build DRVCTRL register values from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line - * is invalid; filter value is invalid - */ -static inline enum status_code _tcc_build_drvctrl( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - uint32_t i; - uint8_t ow_num = _tcc_ow_nums[module_index]; - uint32_t drvctrl; - - drvctrl = 0; - - for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) { - if (config->wave_ext.invert[i]) { - if (i >= ow_num) { - return STATUS_ERR_INVALID_ARG; - } - drvctrl |= (TCC_DRVCTRL_INVEN0 << i); - } - if (config->wave_ext.non_recoverable_fault[i].output != - TCC_FAULT_STATE_OUTPUT_OFF) { - if (i >= ow_num) { - return STATUS_ERR_INVALID_ARG; - } - if (config->wave_ext.non_recoverable_fault[i].output == - TCC_FAULT_STATE_OUTPUT_1) { - drvctrl |= (TCC_DRVCTRL_NRE0 | TCC_DRVCTRL_NRV0) << i; - } else { - drvctrl |= (TCC_DRVCTRL_NRE0) << i; - } - } - } - *value_buffer = drvctrl; - return STATUS_OK; -} - -/** - * \brief Build WAVE & WAVEB register values from configuration. - * - * \param[in] module_index The software module instance index - * \param[in] config Pointer to the TCC configuration options struct - * \param[out] value_buffer Pointer to the buffer to fill with built value - * - * \retval STATUS_OK Configuration values are good and register - * value built and save to buffer - * \retval STATUS_ERR_INVALID_ARG Invalid parameter found: assigned output line - * is invalid; circular and double buffering - * conflict; assigned function not supported by - * module - */ -static inline enum status_code _tcc_build_waves( - const uint8_t module_index, - const struct tcc_config *const config, - uint32_t *value_buffer) -{ - int n; - - uint8_t cc_num = _tcc_cc_nums[module_index]; - struct tcc_match_wave_config const *wav_cfg = &config->compare; - - uint32_t wave; - - wave = TCC_WAVE_RAMP(wav_cfg->wave_ramp) | - TCC_WAVE_WAVEGEN(wav_cfg->wave_generation); - - for (n = 0; n < TCC_NUM_CHANNELS; n++) { - if (wav_cfg->wave_polarity[n]) { - if (n >= cc_num) { - return STATUS_ERR_INVALID_ARG; - } - wave |= (TCC_WAVE_POL0 << n); - } - } - - value_buffer[0] = wave; - - return STATUS_OK; -} - -/** - * \brief Initializes a hardware TCC module instance. - * - * Enables the clock and initializes the given TCC module, based on the given - * configuration values. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the TCC hardware module - * \param[in] config Pointer to the TCC configuration options struct - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_BUSY The hardware module was busy when the - * initialization procedure was attempted - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - * \retval STATUS_ERR_DENIED The hardware module was already enabled - */ -enum status_code tcc_init( - struct tcc_module *const module_inst, - Tcc *const hw, - const struct tcc_config *const config) -{ - int i; - - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(config); - - /* TCC instance index */ - uint8_t module_index = _tcc_get_inst_index(hw); - - /* Enable the user interface clock for TCC */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, - _tcc_apbcmasks[module_index]); - - /* Check if it's enabled. */ - if (hw->CTRLA.reg & TCC_CTRLA_ENABLE) { - return STATUS_ERR_DENIED; - } - /* Check if it's resetting */ - if (hw->CTRLA.reg & TCC_CTRLA_SWRST) { - return STATUS_ERR_DENIED; - } - - enum status_code status; - - /* Check COUNT, PER, CCx */ - uint32_t count_max = _tcc_maxs[module_index]; - - /* Check all counter values */ - if ((config->counter.count > count_max) - || (config->counter.period > count_max) - ) { - return STATUS_ERR_INVALID_ARG; - } - - /* Check all channel values */ - for (i = 0; i < TCC_NUM_CHANNELS; i ++) { - if ((config->compare.match[i] > count_max) - ) { - return STATUS_ERR_INVALID_ARG; - } - } - - /* Check all outputs */ - for (i = 0; i < TCC_NUM_WAVE_OUTPUTS; i ++) { - if (!config->pins.enable_wave_out_pin[i]) { - continue; - } - /* Output line is not supported */ - if (i >= _tcc_ow_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - } - - /* CTRLA settings */ - uint32_t ctrla = 0; - status = _tcc_build_ctrla(module_index, config, &ctrla); - if (STATUS_OK != status) { - return status; - } - - /* CTRLB settings */ - uint8_t ctrlb; - _tcc_build_ctrlb(module_index, config, &ctrlb); - - /* FAULTs settings */ - uint32_t faults[TCC_NUM_FAULTS]; - - status = _tcc_build_faults(module_index, config, faults); - if (STATUS_OK != status) { - return status; - } - - /* DRVCTRL */ - uint32_t drvctrl = 0; - - status = _tcc_build_drvctrl(module_index, config, &drvctrl); - if (STATUS_OK != status) { - return status; - } - - /* WAVE */ - uint32_t waves[1]; - - status = _tcc_build_waves(module_index, config, waves); - if (STATUS_OK != status) { - return status; - } - - /* Initialize module */ -#if TCC_ASYNC - /* Initialize parameters */ - for (i = 0; i < TCC_CALLBACK_N; i ++) { - module_inst->callback[i] = NULL; - } - module_inst->register_callback_mask = 0; - module_inst->enable_callback_mask = 0; - _tcc_instances[module_index] = module_inst; -#endif - - module_inst->hw = hw; - - module_inst->double_buffering_enabled = config->double_buffering_enabled; - - /* Setup clock for module */ - struct system_gclk_chan_config gclk_chan_config; - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = config->counter.clock_source; - system_gclk_chan_set_config(_tcc_gclk_ids[module_index], &gclk_chan_config); - system_gclk_chan_enable(_tcc_gclk_ids[module_index]); - - /* Initialize pins */ - // struct system_pinmux_config pin_config; - // for (i = 0; i < _tcc_ow_nums[module_index]; i ++) { - // if (!config->pins.enable_wave_out_pin[i]) { - // continue; - // } - // - // system_pinmux_get_config_defaults(&pin_config); - // pin_config.mux_position = config->pins.wave_out_pin_mux[i]; - // pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; - // system_pinmux_pin_set_config( - // config->pins.wave_out_pin[i], &pin_config); - // } - - /* Write to registers */ - - hw->CTRLA.reg = ctrla; - while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - - hw->CTRLBCLR.reg = 0xFF; - while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - hw->CTRLBSET.reg = ctrlb; - - hw->FCTRLA.reg = faults[0]; - hw->FCTRLB.reg = faults[1]; - - hw->DRVCTRL.reg = drvctrl; - -#if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30) - while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_WAVE | TCC_SYNCBUSY_WAVEB)) { - /* Wait for sync */ - } -#endif - hw->WAVE.reg = waves[0]; - - while (hw->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) { - /* Wait for sync */ - } - hw->COUNT.reg = config->counter.count; - -#if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30) - while (hw->SYNCBUSY.reg & (TCC_SYNCBUSY_PER | TCC_SYNCBUSY_PERB)) { - /* Wait for sync */ - } -#endif - hw->PER.reg = (config->counter.period); - - for (i = 0; i < _tcc_cc_nums[module_index]; i ++) { -#if (!SAML21) && (!SAMC20) && (!SAMC21) && (!SAML22) && (!SAMR30) - while (hw->SYNCBUSY.reg & ( - (TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CCB0) << i)) { - /* Wait for sync */ - } -#endif - hw->CC[i].reg = (config->compare.match[i]); - } - - return STATUS_OK; -} - - -/** - * \brief Enables the TCC module event input or output. - * - * Enables one or more input or output events to or from the TCC module. - * See \ref tcc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to enable or - * configure - * - * \return Status of the events setup procedure. - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_INVALID_ARG An invalid configuration option or argument - * was supplied - */ -enum status_code tcc_enable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tcc *const tcc_module = module_inst->hw; - - /* Check if it's enabled or resetting. */ - if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) { - return STATUS_ERR_DENIED; - } - - uint32_t evctrl = tcc_module->EVCTRL.reg; - - /* Setup event output action */ - if (events->output_config.modify_generation_selection) { - evctrl &= ~ TCC_EVCTRL_CNTSEL_Msk; - switch(events->output_config.generation_selection) { - case TCC_EVENT_GENERATION_SELECTION_START: - evctrl |= TCC_EVCTRL_CNTSEL_START; - break; - case TCC_EVENT_GENERATION_SELECTION_END: - evctrl |= TCC_EVCTRL_CNTSEL_END; - break; - case TCC_EVENT_GENERATION_SELECTION_BETWEEN: - evctrl |= TCC_EVCTRL_CNTSEL_BETWEEN; - break; - case TCC_EVENT_GENERATION_SELECTION_BOUNDARY: - evctrl |= TCC_EVCTRL_CNTSEL_BOUNDARY; - break; - default: - Assert(false); - /* Wrong configuration */ - return STATUS_ERR_INVALID_ARG; - } - } - /* Setup input event0 */ - if (events->on_input_event_perform_action[0]) { - evctrl |= TCC_EVCTRL_TCEI0; - } - if (events->input_config[0].invert) { - evctrl |= TCC_EVCTRL_TCINV0; - } - if (events->input_config[0].modify_action) { - evctrl &= ~ TCC_EVCTRL_EVACT0_Msk; - switch(events->input_config[0].action) { - case TCC_EVENT0_ACTION_OFF: - evctrl |= TCC_EVCTRL_EVACT0_OFF; - break; - case TCC_EVENT0_ACTION_RETRIGGER: - evctrl |= TCC_EVCTRL_EVACT0_RETRIGGER; - break; - case TCC_EVENT0_ACTION_COUNT_EVENT: - evctrl |= TCC_EVCTRL_EVACT0_COUNTEV; - break; - case TCC_EVENT0_ACTION_START: - evctrl |= TCC_EVCTRL_EVACT0_START; - break; - case TCC_EVENT0_ACTION_INCREMENT: - evctrl |= TCC_EVCTRL_EVACT0_INC; - break; - case TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE: - evctrl |= TCC_EVCTRL_EVACT0_COUNT; - break; - case TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT: - evctrl |= TCC_EVCTRL_EVACT0_FAULT; - break; - default: - Assert(false); - /* Wrong configuration */ - return STATUS_ERR_INVALID_ARG; - } - } - /* Setup input event1 */ - if (events->on_input_event_perform_action[1]) { - evctrl |= TCC_EVCTRL_TCEI1; - } - if (events->input_config[1].invert) { - evctrl |= TCC_EVCTRL_TCINV1; - } - if (events->input_config[1].modify_action) { - evctrl &= ~ TCC_EVCTRL_EVACT1_Msk; - switch(events->input_config[1].action) { - case TCC_EVENT1_ACTION_OFF: - evctrl |= TCC_EVCTRL_EVACT1_OFF; - break; - case TCC_EVENT1_ACTION_RETRIGGER: - evctrl |= TCC_EVCTRL_EVACT1_RETRIGGER; - break; - case TCC_EVENT1_ACTION_DIR_CONTROL: - evctrl |= TCC_EVCTRL_EVACT1_DIR; - break; - case TCC_EVENT1_ACTION_STOP: - evctrl |= TCC_EVCTRL_EVACT1_STOP; - break; - case TCC_EVENT1_ACTION_DECREMENT: - evctrl |= TCC_EVCTRL_EVACT1_DEC; - break; - case TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE: - evctrl |= TCC_EVCTRL_EVACT1_PPW | - TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1; - break; - case TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE: - evctrl |= TCC_EVCTRL_EVACT1_PWP | - TCC_EVCTRL_MCEI0 | TCC_EVCTRL_MCEI1; - break; - case TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT: - evctrl |= TCC_EVCTRL_EVACT1_FAULT; - break; - default: - Assert(false); - /* Wrong configuration */ - return STATUS_ERR_INVALID_ARG; - } - } - uint32_t ch; - for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) { - if (events->generate_event_on_channel[ch]) { - evctrl |= (TCC_EVCTRL_MCEO(1) << ch); - } - if (events->on_event_perform_channel_action[ch]) { - evctrl |= (TCC_EVCTRL_MCEI(1) << ch); - } - } - if (events->generate_event_on_counter_overflow) { - evctrl |= TCC_EVCTRL_OVFEO; - } - if (events->generate_event_on_counter_retrigger) { - evctrl |= TCC_EVCTRL_TRGEO; - } - if (events->generate_event_on_counter_event) { - evctrl |= TCC_EVCTRL_CNTEO; - } - - tcc_module->EVCTRL.reg = evctrl; - - return STATUS_OK; -} - -/** - * \brief Disables the event input or output of a TCC instance. - * - * Disables one or more input or output events for the given TCC module. - * See \ref tcc_events for a list of events this module supports. - * - * \note Events cannot be altered while the module is enabled. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] events Struct containing flags of events to disable - */ -void tcc_disable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(events); - - Tcc *const tcc_module = module_inst->hw; - - /* Check if it's enabled or resetting. */ - if (tcc_module->CTRLA.reg & (TCC_CTRLA_ENABLE | TCC_CTRLA_SWRST)) { - return; - } - - - uint32_t evctrl = 0; - uint32_t ch; - for(ch = 0; ch < TCC_NUM_CHANNELS; ch ++) { - if (events->generate_event_on_channel[ch]) { - evctrl |= (TCC_EVCTRL_MCEO(1) << ch); - } - if (events->on_event_perform_channel_action[ch]) { - evctrl |= (TCC_EVCTRL_MCEI(1) << ch); - } - } - if (events->generate_event_on_counter_overflow) { - evctrl |= TCC_EVCTRL_OVFEO; - } - if (events->generate_event_on_counter_retrigger) { - evctrl |= TCC_EVCTRL_TRGEO; - } - if (events->generate_event_on_counter_event) { - evctrl |= TCC_EVCTRL_CNTEO; - } - if (events->on_input_event_perform_action[0]) { - evctrl |= TCC_EVCTRL_TCEI0; - } - if (events->on_input_event_perform_action[1]) { - evctrl |= TCC_EVCTRL_TCEI1; - } - if (events->input_config[0].invert) { - evctrl |= TCC_EVCTRL_TCINV0; - } - if (events->input_config[1].invert) { - evctrl |= TCC_EVCTRL_TCINV1; - } - - tcc_module->EVCTRL.reg &= ~evctrl; -} - - - -/** - * \brief Sets count value for the given TCC module. - * - * Sets the timer count value of an initialized TCC module. The - * specified TCC module can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] count New timer count value to set - * - * \return Status which indicates whether the new value is set. - * - * \retval STATUS_OK The timer count was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid timer counter size was specified - */ -enum status_code tcc_set_count_value( - const struct tcc_module *const module_inst, - const uint32_t count) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - uint32_t max_count = _tcc_maxs[module_index]; - - if (count > max_count) { - return STATUS_ERR_INVALID_ARG; - } - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) { - /* Wait for sync */ - } - - /* Write to based on the TCC dithering */ - tcc_module->COUNT.reg = (count); - - return STATUS_OK; -} - -/** - * \brief Get count value of the given TCC module. - * - * Retrieves the current count value of a TCC module. The specified TCC module - * can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Count value of the specified TCC module. - */ -uint32_t tcc_get_count_value( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance*/ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait last command done */ - do { - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (TCC_CTRLBSET_CMD_NONE == last_cmd) { - /* Issue read command and break */ - tcc_module->CTRLBSET.bit.CMD = TCC_CTRLBSET_CMD_READSYNC_Val; - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - break; - } else if (TCC_CTRLBSET_CMD_READSYNC == last_cmd) { - /* Command have been issued */ - break; - } - } while (1); - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) { - /* Wait for sync */ - } - return (tcc_module->COUNT.reg); -} - - - -/** - * \brief Gets the TCC module capture value. - * - * Retrieves the capture value in the indicated TCC module capture channel. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the Compare Capture channel to read - * - * \return Capture value stored in the specified timer channel. - */ -uint32_t tcc_get_capture_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - Assert(channel_index < _tcc_cc_nums[_tcc_get_inst_index(module_inst->hw)]); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while(tcc_module->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << channel_index)) { - /* Sync wait */ - } - - return tcc_module->CC[channel_index].reg; -} - -/** - * \internal - * \brief Sets a TCC module compare value/buffer. - * - * Writes a compare value to the given TCC module compare/capture channel or - * buffer one. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value/buffer value to set - * \param[in] double_buffering_enabled Set to \c true to write to CCBx - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * compare value exceed resolution - */ -static enum status_code _tcc_set_compare_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare, - const bool double_buffering_enabled) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - /* Check index */ - if (channel_index >= _tcc_cc_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - - uint32_t max_count = _tcc_maxs[module_index]; - - /* Check compare value */ - if (compare > max_count) { - return STATUS_ERR_INVALID_ARG; - } - - if (double_buffering_enabled) { -#if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30) - tcc_module->CCBUF[channel_index].reg = compare; -#else - while(tcc_module->SYNCBUSY.reg & - (TCC_SYNCBUSY_CCB0 << channel_index)) { - /* Sync wait */ - } - tcc_module->CCB[channel_index].reg = compare; -#endif - } else { - while(tcc_module->SYNCBUSY.reg & (TCC_SYNCBUSY_CC0 << channel_index)) { - /* Sync wait */ - } - tcc_module->CC[channel_index].reg = compare; - } - return STATUS_OK; -} - - -/** - * \brief Sets a TCC module compare value. - * - * Writes a compare value to the given TCC module compare/capture channel. - * - * If double buffering is enabled it always write to the buffer - * register. The value will then be updated immediately by calling - * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit - * is cleared and the UPDATE condition happen. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * compare value exceed resolution - */ -enum status_code tcc_set_compare_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare) -{ - /* Sanity check arguments */ - Assert(module_inst); - - return _tcc_set_compare_value(module_inst, channel_index, compare, - module_inst->double_buffering_enabled); -} - -/** - * \brief Sets a TCC module compare value and buffer value. - * - * Writes compare value and buffer to the given TCC module compare/capture - * channel. Usually as preparation for double buffer or circulared double buffer - * (circular buffer). - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] channel_index Index of the compare channel to write to - * \param[in] compare New compare value to set - * \param[in] compare_buffer New compare buffer value to set - * - * \return Status of the compare update procedure. - * - * \retval STATUS_OK The compare value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * compare value exceed resolution - */ -enum status_code tcc_set_double_buffer_compare_values( - struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare, const uint32_t compare_buffer) -{ - /* Sanity check arguments */ - Assert(module_inst); - - enum status_code status; - status = _tcc_set_compare_value(module_inst, channel_index, compare, false); - if (status != STATUS_OK) { - return status; - } - return _tcc_set_compare_value(module_inst, channel_index, compare_buffer, - true); -} - - -/** - * \internal - * \brief Set the timer TOP/PERIOD buffer/value. - * - * This function writes the given value to the PER/PERB register. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New value to be loaded into the PER/PERB register - * \param[in] double_buffering_enabled Set to \c true to write to PERB - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * top/period value exceed resolution - */ -static enum status_code _tcc_set_top_value( - const struct tcc_module *const module_inst, - const uint32_t top_value, - const bool double_buffering_enabled) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - uint32_t max_count = _tcc_maxs[module_index]; - - /* Check compare value */ - if (top_value > max_count) { - return STATUS_ERR_INVALID_ARG; - } - - if (double_buffering_enabled) { -#if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30) - tcc_module->PERBUF.reg = top_value; -#else - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PERB) { - /* Sync wait */ - } - tcc_module->PERB.reg = top_value; -#endif - } else { - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PER) { - /* Sync wait */ - } - tcc_module->PER.reg = top_value; - } - return STATUS_OK; -} - - -/** - * \brief Set the timer TOP/PERIOD value. - * - * This function writes the given value to the PER/PERB register. - * - * If double buffering is enabled it always write to the buffer - * register (PERB). The value will then be updated immediately by calling - * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit - * is cleared and the UPDATE condition happen. - * - * When using MFRQ, the top value is defined by the CC0 register value and the - * PER value is ignored, so - * \ref tcc_set_compare_value (module,channel_0,value) must be used instead of - * this function to change the actual top value in that case. - * For all other waveforms operation the top value is defined by PER register - * value. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New value to be loaded into the PER/PERB register - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * top/period value exceed resolution - */ -enum status_code tcc_set_top_value( - const struct tcc_module *const module_inst, - const uint32_t top_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - - return _tcc_set_top_value(module_inst, top_value, - module_inst->double_buffering_enabled); -} - -/** - * \brief Set the timer TOP/PERIOD value and buffer value. - * - * This function writes the given value to the PER and PERB register. Usually as - * preparation for double buffer or circulared double buffer (circular buffer). - * - * When using MFRQ, the top values are defined by the CC0 and CCB0, the PER and - * PERB values are ignored, so - * \ref tcc_set_double_buffer_compare_values (module,channel_0,value,buffer) must - * be used instead of this function to change the actual top values in that - * case. For all other waveforms operation the top values are defined by PER and - * PERB registers values. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] top_value New value to be loaded into the PER register - * \param[in] top_buffer_value New value to be loaded into the PERB register - * - * \return Status of the TOP set procedure. - * - * \retval STATUS_OK The timer TOP value was updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid channel index was supplied or - * top/period value exceed resolution - */ -enum status_code tcc_set_double_buffer_top_values( - const struct tcc_module *const module_inst, - const uint32_t top_value, const uint32_t top_buffer_value) -{ - /* Sanity check arguments */ - Assert(module_inst); - - enum status_code status; - status = _tcc_set_top_value(module_inst, top_value, false); - if (status != STATUS_OK) { - return status; - } - return _tcc_set_top_value(module_inst, top_buffer_value, true); -} - - -/** - * \brief Sets the TCC module waveform output pattern. - * - * Force waveform output line to generate specific pattern (0, 1, or as is). - * - * If double buffering is enabled it always write to the buffer - * register. The value will then be updated immediately by calling - * \ref tcc_force_double_buffer_update(), or be updated when the lock update bit - * is cleared and the UPDATE condition happen. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] line_index Output line index - * \param[in] pattern Output pattern to use (\ref tcc_output_pattern) - * - * \return Status of the pattern set procedure. - * - * \retval STATUS_OK The PATT register is updated successfully - * \retval STATUS_ERR_INVALID_ARG An invalid line index was supplied - */ -enum status_code tcc_set_pattern( - const struct tcc_module *const module_inst, - const uint32_t line_index, - const enum tcc_output_pattern pattern) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - /* Get number of output lines */ - uint8_t ow_num = _tcc_ow_nums[module_index]; - - /* Check if line number is OK */ - if (line_index >= ow_num) { - return STATUS_ERR_INVALID_ARG; - } - - uint32_t patt_value; - - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) { - /* Sync wait */ - } - patt_value = tcc_module->PATT.reg; - if (TCC_OUTPUT_PATTERN_DISABLE == pattern) { - patt_value &= ~(TCC_PATT_PGE0 << line_index); - } else if (TCC_OUTPUT_PATTERN_0 == pattern) { - patt_value &= ~(TCC_PATT_PGV0 << line_index); - patt_value |= (TCC_PATT_PGE0 << line_index); - } else { - patt_value |= ((TCC_PATT_PGE0 | TCC_PATT_PGV0) << line_index); - } - - if (module_inst->double_buffering_enabled) { -#if (SAML21) || (SAMC20) || (SAMC21) || (SAML22) || (SAMR30) - tcc_module->PATTBUF.reg = patt_value; -#else - while(tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_PATTB) { - /* Sync wait */ - } - tcc_module->PATTB.reg = patt_value; -#endif - } else { - tcc_module->PATT.reg = patt_value; - } - return STATUS_OK; -} - -/** - * \brief Retrieves the current module status. - * - * Retrieves the status of the module, giving overall state information. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - * \return Bitmask of \c TCC_STATUS_* flags. - * - * \retval TCC_STATUS_CHANNEL_MATCH_CAPTURE(n) Channel n match/capture has occured - * \retval TCC_STATUS_CHANNEL_OUTPUT(n) Channel n match/capture output state - * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) Non-recoverable fault x has occured - * \retval TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) Recoverable fault n has occured - * \retval TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) Non-recoverable fault x input present - * \retval TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) Recoverable fault n input present - * \retval TCC_STATUS_SYNC_READY None of register is syncing - * \retval TCC_STATUS_CAPTURE_OVERFLOW Timer capture data has overflowed - * \retval TCC_STATUS_COUNTER_EVENT Timer counter event has occurred - * \retval TCC_STATUS_COUNT_OVERFLOW Timer count value has overflowed - * \retval TCC_STATUS_COUNTER_RETRIGGERED Timer counter has been retriggered - * \retval TCC_STATUS_STOP Timer counter has been stopped - * \retval TCC_STATUS_RAMP_CYCLE_INDEX Wave ramp index for cycle - */ -uint32_t tcc_get_status( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint32_t int_flags = module_inst->hw->INTFLAG.reg; - uint32_t status_flags = module_inst->hw->STATUS.reg; - uint32_t status = 0; - int i; - - /* SYNC */ - if (module_inst->hw->SYNCBUSY.reg == 0) { - status |= TCC_STATUS_SYNC_READY; - } - - /* Channels */ - for (i = 0; i < TCC_NUM_CHANNELS; i++) { - if (int_flags & TCC_INTFLAG_MC(i)) { - status |= TCC_STATUS_CHANNEL_MATCH_CAPTURE(i); - } - if (status_flags & TCC_STATUS_CMP(i)) { - status |= TCC_STATUS_CHANNEL_OUTPUT(i); - } - } - /* Non-recoverable fault state */ - if ((int_flags & TCC_INTFLAG_FAULT1) || - (status_flags & TCC_STATUS_FAULT1)) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1); - } - if ((int_flags & TCC_INTFLAG_FAULT0) || - (status_flags & TCC_STATUS_FAULT0)) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0); - } - /* Non-recoverable fault inputs */ - if (status_flags & TCC_STATUS_FAULT0IN) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(0); - } - if (status_flags & TCC_STATUS_FAULT1IN) { - status |= TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(1); - } - /* Recoverable fault state */ - if ((int_flags & TCC_INTFLAG_FAULTB) || - (status_flags & TCC_STATUS_FAULTB)) { - status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1); - } - if ((int_flags & TCC_INTFLAG_FAULTA) || - (status_flags & TCC_STATUS_FAULTA)) { - status |= TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0); - } - /* Recoverable fault inputs */ - if (status_flags & TCC_STATUS_FAULTAIN) { - status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(0); - } - if (status_flags & TCC_STATUS_FAULTBIN) { - status |= TCC_STATUS_RECOVERABLE_FAULT_PRESENT(1); - } - - /* Check for TCC capture overflow */ - if (int_flags & TCC_INTFLAG_ERR) { - status |= TCC_STATUS_CAPTURE_OVERFLOW; - } - /* Check for TCC count counter */ - if (int_flags & TCC_INTFLAG_CNT) { - status |= TCC_STATUS_COUNTER_EVENT; - } - /* Check for TCC count retrigger */ - if (int_flags & TCC_INTFLAG_TRG) { - status |= TCC_STATUS_COUNTER_RETRIGGERED; - } - /* Check for TCC count overflow */ - if (int_flags & TCC_INTFLAG_OVF) { - status |= TCC_STATUS_COUNT_OVERFLOW; - } - /* Check for TCC count stop */ - if (status_flags & TCC_STATUS_STOP) { - status |= TCC_STATUS_STOPPED; - } - /* Check for TCC RAMP index */ - if (status_flags & TCC_STATUS_IDX) { - status |= TCC_STATUS_RAMP_CYCLE_INDEX; - } - return status; -} - -/** - * \brief Clears a module status flag. - * - * Clears the given status flag of the module. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * \param[in] status_flags Bitmask of \c TCC_STATUS_* flags to clear - */ -void tcc_clear_status( - struct tcc_module *const module_inst, - const uint32_t status_flags) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint32_t int_clr = 0; - uint32_t status_clr = 0; - int i; - - /* Channels */ - for (i = 0; i < TCC_NUM_CHANNELS; i++) { - if (status_flags & TCC_STATUS_CHANNEL_MATCH_CAPTURE(i)) { - int_clr |= TCC_INTFLAG_MC(i); - } - } - /* Faults */ - if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(1)) { - int_clr |= TCC_INTFLAG_FAULT1; - status_clr |= TCC_STATUS_FAULT1; - } - if (status_flags & TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(0)) { - int_clr |= TCC_INTFLAG_FAULT0; - status_clr |= TCC_STATUS_FAULT0; - } - if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(1)) { - int_clr |= TCC_INTFLAG_FAULTB; - status_clr |= TCC_STATUS_FAULTB; - } - if (status_flags & TCC_STATUS_RECOVERABLE_FAULT_OCCUR(0)) { - int_clr |= TCC_INTFLAG_FAULTA; - status_clr |= TCC_STATUS_FAULTA; - } - /* Check for TCC capture overflow */ - if (status_flags & TCC_STATUS_CAPTURE_OVERFLOW) { - int_clr |= TCC_INTFLAG_ERR; - } - /* Check for TCC count counter */ - if (status_flags & TCC_STATUS_COUNTER_EVENT) { - int_clr |= TCC_INTFLAG_CNT; - } - /* Check for TCC count retrigger */ - if (status_flags & TCC_STATUS_COUNTER_RETRIGGERED) { - int_clr = TCC_INTFLAG_TRG; - } - /* Check for TCC count overflow */ - if (status_flags & TCC_STATUS_COUNT_OVERFLOW) { - int_clr |= TCC_INTFLAG_OVF; - } - /* Clear status flag */ - module_inst->hw->STATUS.reg = status_clr; - /* Clear interrupt flag */ - module_inst->hw->INTFLAG.reg = int_clr; -} - -/** - * \brief Enable circular option for double buffered compare values. - * - * Enable circular option for the double buffered channel compare values. - * On each UPDATE condition, the contents of CCBx and CCx are switched, meaning - * that the contents of CCBx are transferred to CCx and the contents of CCx are - * transferred to CCBx. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * \param[in] channel_index Index of the compare channel to set up to - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_INVALID_ARG An invalid channel index is supplied - */ -enum status_code tcc_enable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - /* Check index */ - if (channel_index > 3) { - return STATUS_ERR_INVALID_ARG; - } - if (channel_index >= _tcc_cc_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - - tcc_module->WAVE.reg |= (TCC_WAVE_CICCEN0 << channel_index); - - return STATUS_OK; -} - -/** - * \brief Disable circular option for double buffered compare values. - * - * Stop circularing the double buffered compare values. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * \param[in] channel_index Index of the compare channel to set up to - * - * \retval STATUS_OK The module was initialized successfully - * \retval STATUS_INVALID_ARG An invalid channel index is supplied - */ -enum status_code tcc_disable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - /* Get a index of the module */ - uint8_t module_index = _tcc_get_inst_index(tcc_module); - - /* Check index */ - if (channel_index > 3) { - return STATUS_ERR_INVALID_ARG; - } - if (channel_index >= _tcc_cc_nums[module_index]) { - return STATUS_ERR_INVALID_ARG; - } - - tcc_module->WAVE.reg &= ~(TCC_WAVE_CICCEN0 << channel_index); - - return STATUS_OK; -} diff --git a/atmel-samd/asf/sam0/drivers/tcc/tcc.h b/atmel-samd/asf/sam0/drivers/tcc/tcc.h deleted file mode 100644 index 782c4322b43bf..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tcc/tcc.h +++ /dev/null @@ -1,2494 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - Timer Counter for Control Applications Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef TCC_H_INCLUDED -#define TCC_H_INCLUDED - -/** - * \defgroup asfdoc_sam0_tcc_group SAM Timer Counter for Control Applications (TCC) Driver - * - * This driver for Atmel® | SMART ARM®-based microcontrollers provides an interface for the configuration - * and management of the TCC module within the device, for waveform - * generation and timing operations. It also provides extended options for - * control applications. - * - * The following driver API modes are covered - * by this manual: - * - * - Polled APIs - * \if TCC_CALLBACK_MODE - * - Callback APIs - * \endif - * - * The following peripheral is used by this module: - * - TCC (Timer/Counter for Control Applications) - * - * The following devices can use this module: - * - Atmel | SMART SAM D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D10/D11 - * - Atmel | SMART SAM L21/L22 - * - Atmel | SMART SAM DA1 - * - Atmel | SMART SAM C20/C21 - * - Atmel | SMART SAM R30 - * - * The outline of this documentation is as follows: - * - \ref asfdoc_sam0_tcc_prerequisites - * - \ref asfdoc_sam0_tcc_module_overview - * - \ref asfdoc_sam0_tcc_special_considerations - * - \ref asfdoc_sam0_tcc_extra_info - * - \ref asfdoc_sam0_tcc_examples - * - \ref asfdoc_sam0_tcc_api_overview - * - * \section asfdoc_sam0_tcc_prerequisites Prerequisites - * - * There are no prerequisites for this module. - * - * \section asfdoc_sam0_tcc_module_overview Module Overview - * - * The Timer/Counter for Control Applications (TCC) module provides a set of - * timing and counting related functionality, such as the generation of periodic - * waveforms, the capturing of a periodic waveform's frequency/duty cycle, - * software timekeeping for periodic operations, waveform extension control, - * fault detection etc. - * - * The counter size of the TCC modules can be 16- or 24-bit depending on - * the TCC instance. - * Refer \ref asfdoc_sam0_tcc_special_considerations_tcc_d21 and - * \ref asfdoc_sam0_tcc_special_considerations_tcc_d11 for details on TCC instances. - * - * The TCC module for the SAM includes the following functions: - * - * - Generation of PWM signals - * - Generation of timestamps for events - * - General time counting - * - Waveform period capture - * - Waveform frequency capture - * - Additional control for generated waveform outputs - * - Fault protection for waveform generation - * - * \ref asfdoc_sam0_tcc_block_diagram "The diagram below" shows the overview - * of the TCC Module. - * - * \anchor asfdoc_sam0_tcc_block_diagram - * \image html overview.svg "Overview of the TCC Module" - * - * \subsection asfdoc_sam0_tcc_module_overview_parts Functional Description - * The TCC module consists of following sections: - * - Base Counter - * - Compare/Capture channels, with waveform generation - * - Waveform extension control and fault detection - * - Interface to the event system, DMAC, and the interrupt system - * - * The base counter can be configured to either count a prescaled generic - * clock or events from the event system.(TCEx, with event action configured - * to counting). - * The counter value can be used by compare/capture channels which can be - * set up either in compare mode or capture mode. - * - * In capture mode, the counter value is stored when a configurable event - * occurs. This mode can be used to generate timestamps used in event capture, - * or it can be used for the measurement of a periodic input signal's - * frequency/duty cycle. - * - * In compare mode, the counter value is compared against one or more of the - * configured channels' compare values. When the counter value coincides with a - * compare value an action can be taken automatically by the module, such as - * generating an output event or toggling a pin when used for frequency or PWM - * signal generation. - * - * \note The connection of events between modules requires the use of the - * \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)" - * to route output event of one module to the the input event of another. - * For more information on event routing, refer to the event driver - * documentation. - * - * In compare mode, when output signal is generated, extended waveform controls - * are available, to arrange the compare outputs into specific formats. - * The Output matrix can change the channel output routing. Pattern generation - * unit can overwrite the output signal line to specific state. - * The Fault protection feature of the TCC supports recoverable and - * non-recoverable faults. - * - * \subsection asfdoc_sam0_tcc_module_overview_tc Base Timer/Counter - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_size Timer/Counter Size - * Each TCC has a counter size of either 16- or 24-bits. The size of the - * counter determines the maximum value it can count to before an overflow - * occurs. - * \ref asfdoc_sam0_tcc_count_size_vs_top "The table below" shows the - * maximum values for each of the possible counter sizes. - * - * \anchor asfdoc_sam0_tcc_count_size_vs_top - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Timer Counter Sizes and Their Maximum Count Values
Counter sizeMax. (hexadecimal)Max. (decimal)
16-bit0xFFFF65,535
24-bit0xFFFFFF16,777,215
- * - * The period/top value of the counter can be set, to define counting period. - * This will allow the counter to overflow when the counter value reaches the - * period/top value. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_clk Timer/Counter Clock and Prescaler - * TCC is clocked asynchronously to the system clock by a GCLK - * (Generic Clock) channel. The GCLK channel can be connected to any of the GCLK - * generators. The GCLK generators are configured to use one of the available - * clock sources in the system such as internal oscillator, external crystals, - * etc. See the \ref asfdoc_sam0_system_clock_group "Generic Clock driver" for - * more information. - * - * Each TCC module in the SAM has its own individual clock prescaler, which - * can be used to divide the input clock frequency used by the counter. This - * prescaler only scales the clock used to provide clock pulses for the counter - * to count, and does not affect the digital register interface portion of - * the module, thus the timer registers will be synchronized to the raw GCLK - * frequency input to the module. - * - * As a result of this, when selecting a GCLK frequency and timer prescaler - * value, the user application should consider both the timer resolution - * required and the synchronization frequency to avoid lengthy - * synchronization times of the module if a very slow GCLK frequency is fed - * into the TCC module. It is preferable to use a higher module GCLK frequency - * as the input to the timer, and prescale this down as much as possible to - * obtain a suitable counter frequency in latency-sensitive applications. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_ctrl Timer/Counter Control Inputs (Events) - * - * The TCC can take several actions on the occurrence of an input event. - * The event actions are listed - * in \ref asfdoc_sam0_tcc_module_event_act "events action settings". - * - * \anchor asfdoc_sam0_tcc_module_event_act - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Event Actions
Event actionDescriptionApplied event
TCC_EVENT_ACTION_OFFNo action on the event inputAll
TCC_EVENT_ACTION_RETRIGGERRe-trigger Counter on eventAll
TCC_EVENT_ACTION_NON_RECOVERABLE_FAULTGenerate Non-Recoverable Fault on eventAll
TCC_EVENT_ACTION_STARTCounter start on eventEV0
TCC_EVENT_ACTION_DIR_CONTROLCounter direction controlEV0
TCC_EVENT_ACTION_DECREMENTCounter decrement on eventEV0
TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURECapture pulse period and pulse widthEV0
TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURECapture pulse width and pulse periodEV0
TCC_EVENT_ACTION_STOPCounter stop on eventEV1
TCC_EVENT_ACTION_COUNT_EVENTCounter count on eventEV1
TCC_EVENT_ACTION_INCREMENTCounter increment on eventEV1
TCC_EVENT_ACTION_COUNT_DURING_ACTIVECounter count during active state of asynchronous eventEV1
- * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_reload Timer/Counter Reloading - * - * The TCC also has a configurable reload action, used when a - * re-trigger event occurs. Examples of a re-trigger event could be the counter - * reaching the maximum value when counting up, or when an event from the event - * system makes the counter to re-trigger. The reload action determines if the - * prescaler should be reset, and on which clock. The counter will - * always be reloaded with the value it is set to start counting. The user - * can choose between three different reload actions, described in - * \ref asfdoc_sam0_tcc_module_reload_act "the table below". - * - * \anchor asfdoc_sam0_tcc_module_reload_act - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Reload Actions
Reload actionDescription
TCC_RELOAD_ACTION_GCLKReload TCC counter value on next GCLK cycle. Leave prescaler - * as-is.
TCC_RELOAD_ACTION_PRESCReloads TCC counter value on next prescaler clock. Leave prescaler - * as-is.
TCC_RELOAD_ACTION_RESYNCReload TCC counter value on next GCLK cycle. Clear prescaler to - * zero.
- * - * The reload action to use will depend on the specific application being - * implemented. One example is when an external trigger for a reload occurs; if - * the TCC uses the prescaler, the counter in the prescaler should not have a - * value between zero and the division factor. The counter in the TCC module - * and the counter in the prescaler should both start at zero. - * If the counter is set to re-trigger when it reaches the maximum value, - * this is not the right option to use. In such a case it would be better if - * the prescaler is left unaltered when the re-trigger happens, letting the - * counter reset on the next GCLK cycle. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_tc_oneshot One-shot Mode - * - * The TCC module can be configured in one-shot mode. When configured in this - * manner, starting the timer will cause it to count until the next overflow - * or underflow condition before automatically halting, waiting to be manually - * triggered by the user application software or an event from the event - * system. - * - * \subsection asfdoc_sam0_tcc_module_overview_capt Capture Operations - * - * In capture operations, any event from the event system or a pin change can - * trigger a capture of the counter value. This captured counter value can be - * used as timestamps for the events, or it can be used in frequency and pulse - * width capture. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_capt_ev Capture Operations - Event - * - * Event capture is a simple use of the capture functionality, - * designed to create timestamps for specific events. When the input event - * appears, the current counter value is copied into the corresponding - * compare/capture register, which can then be read by the user application. - * - * Note that when performing any capture operation, there is a risk that the - * counter reaches its top value (MAX) when counting up, or the bottom value - * (zero) when counting down, before the capture event occurs. This can distort - * the result, making event timestamps to appear shorter than they really are. - * In this case, the user application should check for timer overflow when - * reading a capture result in order to detect this situation and perform an - * appropriate adjustment. - * - * Before checking for a new capture, \ref TCC_STATUS_COUNT_OVERFLOW - * should be checked. The response to an overflow error is left to the user - * application, however, it may be necessary to clear both the overflow - * flag and the capture flag upon each capture reading. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_capt_pulse Capture Operations - Pulse Width - * - * Pulse Width Capture mode makes it possible to measure the pulse width and - * period of PWM signals. This mode uses two capture channels of the counter. - * There are two modes for pulse width capture; - * Pulse Width Period (PWP) and Period Pulse Width (PPW). In PWP mode, capture - * channel 0 is used for storing the pulse width and capture channel 1 stores - * the observed period. While in PPW mode, the roles of the two capture channels - * are reversed. - * - * As in the above example it is necessary to poll on interrupt flags to see - * if a new capture has happened and check that a capture overflow error has - * not occurred. - * - * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to set up the input - * event to perform pulse width capture. - * - * \subsection asfdoc_sam0_tcc_module_overview_mc Compare Match Operation - * - * In compare match operation, Compare/Capture registers are compared - * with the counter value. When the timer's count value matches the value of a - * compare channel, a user defined action can be taken. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_timer Basic Timer - * - * A Basic Timer is a simple application where compare match operation is used - * to determine when a specific period has elapsed. In Basic Timer operations, - * one or more values in the module's Compare/Capture registers are used to - * specify the time (in terms of the number of prescaled GCLK cycles, or - * input events) at which - * an action should be taken by the microcontroller. This can be an Interrupt - * Service Routine (ISR), event generation via the event system, or a software - * flag that is polled from the user application. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave Waveform Generation - * - * Waveform generation enables the TCC module to generate square waves, or, if - * combined with an external passive low-pass filter, analog waveforms. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_pwm Waveform Generation - PWM - * - * Pulse width modulation is a form of waveform generation and a signalling - * technique that can be useful in many applications. When PWM mode is used, - * a digital pulse train with a configurable frequency and duty cycle can be - * generated by the TCC module and output to a GPIO pin of the device. - * - * Often PWM is used to communicate a control or information parameter to an - * external circuit or component. Differing impedances of the source generator - * and sink receiver circuits is less of an issue when using PWM compared to - * using an analog voltage value, as noise will not generally affect the - * signal's integrity to a meaningful extent. - * - * \ref asfdoc_sam0_tcc_module_pwm_single_diag "The figure below" illustrates - * operations and different states of the counter and its output when using - * the timer in Normal PWM mode (Single Slope). As can be seen, the TOP/PERIOD - * value is - * unchanged and is set to MAX. The compare match value is changed at several - * points to illustrate the resulting waveform output changes. The PWM output is - * set to normal (i.e. non-inverted) output mode. - * - * \anchor asfdoc_sam0_tcc_module_pwm_single_diag - * \image html pwm_single_ex.svg "Example Of PWM In Single-Slope Mode, and Different Counter Operations" - * - * Several PWM modes are supported by the TCC module, refer to - * datasheet for the details on PWM waveform generation. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_mc_wave_freq Waveform Generation - Frequency - * - * Normal Frequency Generation is in many ways identical to PWM generation. - * However, only in Frequency Generation, a toggle occurs on the output when a - * match on a compare channels occurs. - * - * When the Match Frequency Generation is used, the timer value is reset on - * match condition, resulting in a variable frequency square wave with a - * fixed 50% duty cycle. - * - * \subsection asfdoc_sam0_tcc_module_overview_ext Waveform Extended Controls - * - * \subsubsection asfdoc_sam0_tcc_module_overview_ext_pat Pattern Generation - * - * Pattern insertion allows the TCC module to change the actual pin output level - * without modifying the compare/match settings. - * - * \anchor asfdoc_sam0_tcc_module_pattern_gen - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Output Pattern Generation
PatternDescription
TCC_OUTPUT_PATTERN_DISABLEPattern disabled, generate output as is
TCC_OUTPUT_PATTERN_0Generate pattern 0 on output (keep the output LOW)
TCC_OUTPUT_PATTERN_1Generate pattern 1 on output (keep the output HIGH)
- * - * \subsubsection asfdoc_sam0_tcc_module_overview_ext_r_fault Recoverable Faults - * - * The recoverable faults can trigger one or several of following fault actions: - * -# *Halt* action: The recoverable faults can halt the TCC timer/counter, - * so that the final output wave is kept at a defined state. When the fault - * state is removed it is possible to recover the counter and waveform - * generation. The halt action is defined as: - * \anchor asfdoc_sam0_tcc_module_fault_halt_action - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Recoverable Fault Halt Actions
ActionDescription
TCC_FAULT_HALT_ACTION_DISABLEHalt action is disabled
TCC_FAULT_HALT_ACTION_HW_HALTThe timer/counter is halted as long as the corresponding fault is - * present
TCC_FAULT_HALT_ACTION_SW_HALTThe timer/counter is halted until the corresponding fault is removed - * and fault state cleared by software
TCC_FAULT_HALT_ACTION_NON_RECOVERABLEForce all the TCC output pins to a pre-defined level, as what - * Non-Recoverable Fault do
- * -# *Restart* action: When enabled, the recoverable faults can restart the TCC - * timer/counter. - * -# *Keep* action: When enabled, the recoverable faults can keep the - * corresponding channel output to zero when the fault condition is present. - * -# *Capture* action: When the recoverable fault occurs, the capture action can - * time stamps the corresponding fault. The following capture mode is - * supported: - * \anchor asfdoc_sam0_tcc_module_fault_capt_action - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Recoverable Fault Capture Actions
ActionDescription
TCC_FAULT_CAPTURE_DISABLECapture action is disabled
TCC_FAULT_CAPTURE_EACHEquivalent to standard capture operation, on each fault occurrence - * the time stamp is captured
TCC_FAULT_CAPTURE_MINIMUMGet the minimum time stamped value in all time stamps
TCC_FAULT_CAPTURE_MAXIMUMGet the maximum time stamped value in all time stamps
TCC_FAULT_CAPTURE_SMALLERTime stamp the fault input if the value is smaller than last one
TCC_FAULT_CAPTURE_BIGGERTime stamp the fault input if the value is bigger than last one
TCC_FAULT_CAPTURE_CHANGETime stamp the fault input if the time stamps changes its increment - * direction
- * - * In TCC module, only the first two compare channels (CC0 and CC1) can work - * with recoverable fault inputs. The corresponding event inputs (TCCx MC0 - * and TCCx MC1) are then used as fault inputs respectively. - * The faults are called Fault A and Fault B. - * - * The recoverable fault can be filtered or effected by corresponding channel - * output. On fault condition there are many other settings that can be chosen. - * Refer to data sheet for more details about the recoverable fault - * operations. - * - * \subsubsection asfdoc_sam0_tcc_module_overview_ext_n_fault Non-Recoverable Faults - * - * The non-recoverable faults force all the TCC output pins to a pre-defined - * level (can be forced to 0 or 1). The input control signal of non-recoverable - * fault is from timer/counter event (TCCx EV0 and TCCx EV1). - * To enable non-recoverable fault, - * corresponding TCEx event action must be set to non-recoverable fault action - * (\ref TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT). - * Refer to \ref asfdoc_sam0_tcc_module_overview_tc_ctrl to see the available - * event input action. - * - * \subsection asfdoc_sam0_tcc_module_overview_buffering Double and Circular Buffering - * - * The pattern, period, and the compare channels registers are double buffered. - * For these options there are effective registers (PATT, PER, and CCx) and - * buffer registers (PATTB, PERB, and CCx). When writing to the buffer - * registers, the values are buffered and will be committed to effective - * registers on UPDATE condition. - * - * Usually the buffered value is cleared after it is committed, but there is also - * an option to circular the register buffers. The period (PER) and four lowest - * compare channels register (CCx, x is 0 ~ 3) support this function. When - * circular buffer is used, on UPDATE the previous period or compare values are - * copied back into the corresponding period buffer and compare buffers. - * This way, the register value and its buffer register value is actually - * switched on UPDATE condition, and will be switched back on next UPDATE - * condition. - * - * For input capture, the buffer register (CCBx) and the corresponding capture - * channel register (CCx) act like a FIFO. When regular register (CCx) is empty - * or read, any content in the buffer register is passed to regular one. - * - * In TCC module driver, when the double buffering write is enabled, any - * write through \ref tcc_set_top_value(), \ref tcc_set_compare_value(), and - * \ref tcc_set_pattern() will be done to the corresponding buffer register. - * Then the value in the buffer register will be transferred to the regular - * register on the next UPDATE condition or by a force UPDATE using - * \ref tcc_force_double_buffer_update(). - * - * \subsection asfdoc_sam0_tcc_module_overview_sleep Sleep Mode - * - * TCC modules can be configured to operate in any sleep mode, with its "run - * in standby" function enabled. It can wake up the device using interrupts or - * perform internal actions with the help of the Event System. - * - * \section asfdoc_sam0_tcc_special_considerations Special Considerations - * - * \subsection asfdoc_sam0_tcc_special_considerations_specific_features Driver Feature Macro Definition - * \ref asfdoc_sam0_tcc_feature_table "The table below" shows some specific features - * of the TCC Module. - * - * \anchor asfdoc_sam0_tcc_feature_table - * - * - * - * - * - * - * - * - * - * - *
TCC Module Specific Features
Driver Feature MacroSupported devices
FEATURE_TCC_GENERATE_DMA_TRIGGERSAM L21/L22/R30
- * - * \note The specific features are only available in the driver when the - * selected device supports those features. - * - * \subsection asfdoc_sam0_tcc_special_considerations_tcc_feature Module Features - * - * The features of TCC, such as timer/counter size, number of compare capture - * channels, and number of outputs, are dependent on the TCC module instance being - * used. - * - * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d21 SAM TCC Feature List - * For SAM D21/R21/L21/L22/DA1/C21/R30, the TCC features are: - * \anchor asfdoc_sam0_tcc_features_d21 - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC module features for SAM D21/R21/L21/L22/DA1/C21/R30
TCC#Match/Capture channelsWave outputsCounter size [bits]FaultDitheringOutput matrixDead-Time insertionSWAPPattern
04824YYYYYY
12424YYY
22216Y
- * - * \subsubsection asfdoc_sam0_tcc_special_considerations_tcc_d11 SAM D10/D11 TCC Feature List - * For SAM D10/D11, the TCC features are: - * \anchor asfdoc_sam0_tcc_features_d11 - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
TCC Module Features For SAM D10/D11
TCC#Match/Capture channelsWave outputsCounter size [bits]FaultDitheringOutput matrixDead-Time insertionSWAPPattern
04824YYYYYY
- * - * \subsection asfdoc_sam0_tcc_special_considerations_tcc_pin Channels vs. Pinouts - * - * As the TCC module may have more waveform output pins than the number of - * compare/capture channels, the free pins (with number higher than number of - * channels) will reuse the waveform generated by channels subsequently. E.g., - * if the number of channels is four and the number of wave output pins is eight, channel - * 0 output will be available on out pin 0 and 4, channel 1 output - * on wave out pin 1 and 5, and so on. - * - * \section asfdoc_sam0_tcc_extra_info Extra Information - * - * For extra information, see \ref asfdoc_sam0_tcc_extra. This includes: - * - \ref asfdoc_sam0_tcc_extra_acronyms - * - \ref asfdoc_sam0_tcc_extra_dependencies - * - \ref asfdoc_sam0_tcc_extra_errata - * - \ref asfdoc_sam0_tcc_extra_history - * - * - * \section asfdoc_sam0_tcc_examples Examples - * - * For a list of examples related to this driver, see - * \ref asfdoc_sam0_tcc_exqsg. - * - * \section asfdoc_sam0_tcc_api_overview API Overview - * @{ - */ - -#include -#include -#include -#include - -/** Maximum number of channels supported by the driver - * (Channel index from 0 to \c TCC_NUM_CHANNELS - 1). - */ -#define TCC_NUM_CHANNELS 4 - -/** Maximum number of wave outputs lines supported by the driver - * (Output line index from 0 to \c TCC_NUM_WAVE_OUTPUTS - 1). - */ -#define TCC_NUM_WAVE_OUTPUTS 8 - -/** Maximum number of (recoverable) faults supported by the driver. */ -#define TCC_NUM_FAULTS 2 - -#if TCC_ASYNC == true -# include -#endif - -/** - * \name Driver Feature Definition - * Define port features set according to different device family. - * @{ -*/ -#if (SAML21) || (SAML22) || (SAMR30) || defined(__DOXYGEN__) -/** Generate DMA triggers */ -# define FEATURE_TCC_GENERATE_DMA_TRIGGER -#endif -/*@}*/ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Generates a table enum list entry for a given type - and index (e.g. "TCC_CALLBACK_MC_CHANNEL_0,"). */ -#define _TCC_ENUM(n, type) TCC_##type##_##n, - -/** Generates table enum list entries for all channels of a - given type and channel number on TCC module. */ -#define _TCC_CHANNEL_ENUM_LIST(type) \ - MREPEAT(TCC_NUM_CHANNELS, _TCC_ENUM, type##_CHANNEL) -/** Generates table enum list entries for all output of a - given type and waveform output number on TCC module. */ -#define _TCC_WO_ENUM_LIST(type) \ - MREPEAT(TCC_NUM_WAVE_OUTPUTS, _TCC_ENUM, type) - - -#if TCC_ASYNC == true -/** Enum for the possible callback types for the TCC module. */ -enum tcc_callback { - /** Callback for TCC overflow */ - TCC_CALLBACK_OVERFLOW, - /** Callback for TCC Retrigger */ - TCC_CALLBACK_RETRIGGER, - /** Callback for TCC counter event */ - TCC_CALLBACK_COUNTER_EVENT, - /** Callback for capture overflow error */ - TCC_CALLBACK_ERROR, - /** Callback for Recoverable Fault A */ - TCC_CALLBACK_FAULTA, - /** Callback for Recoverable Fault B */ - TCC_CALLBACK_FAULTB, - /** Callback for Non-Recoverable Fault 0 */ - TCC_CALLBACK_FAULT0, - /** Callback for Non-Recoverable Fault 1 */ - TCC_CALLBACK_FAULT1, - -# if defined(__DOXYGEN__) - /** Channel callback type table for TCC - * - * Each TCC module may contain several callback types for channels; each - * channel will have its own callback type in the table, with the channel - * index number substituted for "n" in the channel callback type - * (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0). - */ - TCC_CALLBACK_CHANNEL_n = n, -# else - /** Callbacks for Match/Capture channels, e.g., TCC_CALLBACK_CHANNEL_0 */ - _TCC_CHANNEL_ENUM_LIST(CALLBACK) -# endif - -# if !defined(__DOXYGEN__) - /** Number of available callbacks */ - TCC_CALLBACK_N -# endif -}; -#endif /* #if TCC_ASYNC == true */ - -/** - * \name Module Status Flags - * - * TCC status flags, returned by \ref tcc_get_status() and cleared by - * \ref tcc_clear_status(). - * - * @{ - */ - -/** Timer channel \c ch (0 ~ 3) has matched against its compare value, - * or has captured a new value. - */ -#define TCC_STATUS_CHANNEL_MATCH_CAPTURE(ch) (1UL << (ch)) -/** Timer channel \c ch (0 ~ 3) match/compare output state. */ -#define TCC_STATUS_CHANNEL_OUTPUT(ch) (1UL << ((ch)+8)) -/** A Non-Recoverable Fault \c x (0 ~ 1) has occurred. */ -#define TCC_STATUS_NON_RECOVERABLE_FAULT_OCCUR(x) (1UL << ((x)+16)) -/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) has occured. */ -#define TCC_STATUS_RECOVERABLE_FAULT_OCCUR(n) (1UL << ((n)+18)) -/** The Non-Recoverable Fault \c x (0 ~ 1) input is present. */ -#define TCC_STATUS_NON_RECOVERABLE_FAULT_PRESENT(x) (1UL << ((x)+20)) -/** A Recoverable Fault \c n (0 ~ 1 representing A ~ B) is present. */ -#define TCC_STATUS_RECOVERABLE_FAULT_PRESENT(n) (1UL << ((n)+22)) -/** Timer registers synchronization has completed, and the synchronized count - * value may be read. - */ -#define TCC_STATUS_SYNC_READY (1UL << 23) -/** A new value was captured before the previous value was read, resulting in - * lost data. - */ -#define TCC_STATUS_CAPTURE_OVERFLOW (1UL << 24) -/** A counter event occurred. */ -#define TCC_STATUS_COUNTER_EVENT (1UL << 25) -/** A counter retrigger occurred. */ -#define TCC_STATUS_COUNTER_RETRIGGERED (1UL << 26) -/** The timer count value has overflowed from its maximum value to its minimum - * when counting upward, or from its minimum value to its maximum when - * counting downward. - */ -#define TCC_STATUS_COUNT_OVERFLOW (1UL << 27) -/** Ramp period cycle index. - * In ramp operation, each two period cycles are marked as cycle A and B, - * the index 0 represents cycle A and 1 represents cycle B. */ -#define TCC_STATUS_RAMP_CYCLE_INDEX (1UL << 28) -/** The counter has been stopped (due to disable, stop command, or one-shot). */ -#define TCC_STATUS_STOPPED (1UL << 29) - -/** @} */ - -/** - * \brief Index of the match capture channels - * - * This enum is used to specify which capture/match channel to do - * operations on. - */ -enum tcc_match_capture_channel { -# if defined(__DOXYGEN__) - /** Match capture channel index table for TCC - * - * Each TCC module may contain several match capture channels; each channel - * will have its own index in the table, with the index number substituted - * for "n" in the index name (e.g. \c TCC_MATCH_CAPTURE_CHANNEL_0). - */ - TCC_MATCH_CAPTURE_CHANNEL_n = n, -# else - /** Indexes of match capture channels, e.g., TCC_MATCH_CAPTURE_CHANNEL_0 */ - _TCC_CHANNEL_ENUM_LIST(MATCH_CAPTURE) -# endif -# if !defined(__DOXYGEN__) - /** Number of supported channels */ - TCC_MATCH_CAPTURE_CHANNEL_N -# endif -}; - -/** - * \brief Index of the wave outputs - * - * This enum is used to specify which wave output to do - * operations on. - */ -enum tcc_wave_output { -# if defined(__DOXYGEN__) - /** Waveform output index table for TCC - * - * Each TCC module may contain several wave outputs; each output - * will have its own index in the table, with the index number substituted - * for "n" in the index name (e.g. \c TCC_WAVE_OUTPUT_0). - */ - TCC_WAVE_OUTPUT_n = n, -# else - /** Indexes of match capture channels, e.g., TCC_WAVEFORM_OUTPUT_0 */ - _TCC_WO_ENUM_LIST(WAVE_OUTPUT) -# endif -# if !defined(__DOXYGEN__) - /** Number of supported channels */ - TCC_WAVE_OUTPUT_N -# endif -}; - -/** - * \brief TCC wave generation mode enum - * - * This enum is used to specify the waveform generation mode. - * - */ -enum tcc_wave_generation { - /** Normal Frequency: Top is the PER register, output toggled on each - * compare match */ - TCC_WAVE_GENERATION_NORMAL_FREQ = 0, - /** Match Frequency: Top is CC0 register, output toggles on each update - * condition */ - TCC_WAVE_GENERATION_MATCH_FREQ = 1, - /** Single-Slope PWM: Top is the PER register, CCx controls duty cycle - * (output active when count is greater than CCx) */ - TCC_WAVE_GENERATION_SINGLE_SLOPE_PWM = 2, - - /** Double-slope (count up and down), non centre-aligned: Top is the PER - * register, CC[x] controls duty cycle while counting up and CC[x+N/2] - * controls it while counting down */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_CRITICAL = 4, - /** Double-slope (count up and down), interrupt/event at Bottom (Top is the - * PER register, output active when count is greater than CCx) */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTTOM = 5, - /** Double-slope (count up and down), interrupt/event at Bottom and Top: (Top is the - * PER register, output active when count is lower than CCx) */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_BOTH = 6, - /** Double-slope (count up and down), interrupt/event at Top (Top is the - * PER register, output active when count is greater than CCx) */ - TCC_WAVE_GENERATION_DOUBLE_SLOPE_TOP = 7, -}; - -/** - * \brief Polarity of TCC wave generation on channels - * - * Specifies whether the wave output needs to be inverted or not. - */ -enum tcc_wave_polarity { - /** Wave output is not inverted */ - TCC_WAVE_POLARITY_0, - /** Wave output is inverted */ - TCC_WAVE_POLARITY_1 -}; - -/** - * \brief TCC pattern generator for outputs - * - * Used when disabling output pattern or when selecting a specific pattern. - */ -enum tcc_output_pattern { - /** SWAP output pattern is not used */ - TCC_OUTPUT_PATTERN_DISABLE, - /** Pattern 0 is applied to SWAP output */ - TCC_OUTPUT_PATTERN_0, - /** Pattern 1 is applied to SWAP output */ - TCC_OUTPUT_PATTERN_1 -}; - -/** - * \brief Ramp Operations which are supported in single-slope PWM generation - * - * Ramp operations which are supported in single-slope PWM generation. - */ -enum tcc_ramp { - /** Default timer/counter PWM operation */ - TCC_RAMP_RAMP1 = 0, - - /** Uses a single channel (CC0) to control both CC0/CC1 compare outputs. - * In cycle A, the channel 0 output is disabled, and - * in cycle B, the channel 1 output is disabled. */ - TCC_RAMP_RAMP2A, - - /** Uses channels CC0 and CC1 to control compare outputs. - * In cycle A, the channel 0 output is disabled, and - * in cycle B, the channel 1 output is disabled.*/ - TCC_RAMP_RAMP2 -}; - -/** - * \brief Ramp Index for TCC wave generation - * - * In ramp operation, each two period cycles are marked as cycle A and B, - * the index 0 represents cycle A and 1 represents cycle B. - */ -enum tcc_ramp_index { - /** Default, cycle index toggles. */ - TCC_RAMP_INDEX_DEFAULT, - /** Force next cycle to be cycle B (set to 1) */ - TCC_RAMP_INDEX_FORCE_B, - /** Force next cycle to be cycle A (clear to 0) */ - TCC_RAMP_INDEX_FORCE_A, - /** Force next cycle keeping the same as current */ - TCC_RAMP_INDEX_FORCE_KEEP -}; - -/** - * \brief TCC output inversion - * - * Used when enabling or disabling output inversion. - */ -enum tcc_output_invertion { - /** Output inversion not to be enabled */ - TCC_OUTPUT_INVERTION_DISABLE, - /** Invert the output from WO[x] */ - TCC_OUTPUT_INVERTION_ENABLE -}; - -/** - * \brief TCC Counter reload action enum - * - * This enum specify how the counter is reloaded and whether the prescaler - * should be restarted. - */ -enum tcc_reload_action { - /** The counter is reloaded/reset on the next GCLK and starts - * counting on the prescaler clock - */ - TCC_RELOAD_ACTION_GCLK, - /** The counter is reloaded/reset on the next prescaler clock - */ - TCC_RELOAD_ACTION_PRESC, - /** The counter is reloaded/reset on the next GCLK, and the - * prescaler is restarted as well - */ - TCC_RELOAD_ACTION_RESYNC -}; - - -/** - * \brief TCC clock prescaler values - * - * This enum is used to choose the clock prescaler - * configuration. The prescaler divides the clock frequency of the TCC - * module to operate TCC at a slower clock rate. - */ -enum tcc_clock_prescaler { - /** Divide clock by 1 */ - TCC_CLOCK_PRESCALER_DIV1, - /** Divide clock by 2 */ - TCC_CLOCK_PRESCALER_DIV2, - /** Divide clock by 4 */ - TCC_CLOCK_PRESCALER_DIV4, - /** Divide clock by 8 */ - TCC_CLOCK_PRESCALER_DIV8, - /** Divide clock by 16 */ - TCC_CLOCK_PRESCALER_DIV16, - /** Divide clock by 64 */ - TCC_CLOCK_PRESCALER_DIV64, - /** Divide clock by 256 */ - TCC_CLOCK_PRESCALER_DIV256, - /** Divide clock by 1024 */ - TCC_CLOCK_PRESCALER_DIV1024 -}; - -/** - * \brief TCC module count direction - * - * Used when selecting the Timer/Counter count direction. - */ -enum tcc_count_direction { - /** Timer should count upward */ - TCC_COUNT_DIRECTION_UP, - /** Timer should count downward */ - TCC_COUNT_DIRECTION_DOWN, -}; - -#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER -/** - * \brief TCC module counter overflow DMA request mode - * - * Used when selecting the Timer/Counter overflow DMA request mode. - */ -enum tcc_count_overflow_dma_trigger_mode { - /** TCC generates a DMA request on each cycle when an update condition - * is detected - */ - TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_CONTINUE, - /** When an update condition is detected, the TCC generates a DMA trigger - * on the cycle following the DMA One-Shot Command written to the Control - * B register - */ - TCC_COUNT_OVERFLOW_DMA_TRIGGER_MODE_ONE_SHOT, -}; -#endif - -/** - * \brief Action to perform when the TCC module is triggered by events - * - * Event action to perform when the module is triggered by events. - */ -enum tcc_event_action { - /** No event action */ - TCC_EVENT_ACTION_OFF, - /** Stop counting, the counter will maintain its current value, waveforms - * are set to a defined Non-Recoverable State output - * (\ref tcc_non_recoverable_state_output). */ - TCC_EVENT_ACTION_STOP, - /** Re-trigger counter on event, may generate an event if the re-trigger - * event output is enabled. - * \note When re-trigger event action is enabled, enabling the counter - * will not start until the next incoming event appears. */ - TCC_EVENT_ACTION_RETRIGGER, - - /** Start counter when previously stopped. - * Start counting on the event rising edge. Further events will not - * restart the counter; - * the counter keeps on counting using prescaled GCLK_TCCx, until it - * reaches TOP or Zero - * depending on the direction. */ - TCC_EVENT_ACTION_START, - /** Count events; i.e. Increment or decrement depending on count - * direction. */ - TCC_EVENT_ACTION_COUNT_EVENT, - /** The event source must be an asynchronous event, input value will - * overrides the direction settings (input low: counting up, input high: - * counting down). */ - TCC_EVENT_ACTION_DIR_CONTROL, - /** Increment the counter on event, irrespective of count direction */ - TCC_EVENT_ACTION_INCREMENT, - /** Decrement the counter on event, irrespective of count direction */ - TCC_EVENT_ACTION_DECREMENT, - /** Count during active state of asynchronous event. In this case, - * depending on the count direction, the count will be incremented - * or decremented on each prescaled GCLK_TCCx, as long as the input - * event remains active. */ - TCC_EVENT_ACTION_COUNT_DURING_ACTIVE, - - /** Store period in capture register 0, pulse width in capture - * register 1 - */ - TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE, - /** Store pulse width in capture register 0, period in capture - * register 1 - */ - TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE, - - /** Generate Non-Recoverable Fault on event */ - TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT, -}; - - -/** - * \brief Action to be performed when the TCC module is triggered by event0 - * - * Event action to perform when the module is triggered by event0. - */ -enum tcc_event0_action { - /** No event action */ - TCC_EVENT0_ACTION_OFF = TCC_EVENT_ACTION_OFF, - /** Re-trigger Counter on event */ - TCC_EVENT0_ACTION_RETRIGGER = TCC_EVENT_ACTION_RETRIGGER, - /** Count events (increment or decrement, depending on count direction) - */ - TCC_EVENT0_ACTION_COUNT_EVENT = TCC_EVENT_ACTION_COUNT_EVENT, - /** Start counter on event */ - TCC_EVENT0_ACTION_START = TCC_EVENT_ACTION_START, - /** Increment counter on event */ - TCC_EVENT0_ACTION_INCREMENT = TCC_EVENT_ACTION_INCREMENT, - /** Count during active state of asynchronous event */ - TCC_EVENT0_ACTION_COUNT_DURING_ACTIVE = TCC_EVENT_ACTION_COUNT_DURING_ACTIVE, - - /** Generate Non-Recoverable Fault on event */ - TCC_EVENT0_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT -}; - -/** - * \brief Action to perform when the TCC module is triggered by event1 - * - * Event action to perform when the module is triggered by event1. - */ -enum tcc_event1_action { - /** No event action */ - TCC_EVENT1_ACTION_OFF = TCC_EVENT_ACTION_OFF, - /** Re-trigger Counter on event */ - TCC_EVENT1_ACTION_RETRIGGER = TCC_EVENT_ACTION_RETRIGGER, - /** The event source must be an asynchronous event, and the input value - * will override the direction settings. - * If TCEINVx is 0 and input event is LOW: counter will count up. - * If TCEINVx is 0 and input event is HIGH: counter will count down. - */ - TCC_EVENT1_ACTION_DIR_CONTROL = TCC_EVENT_ACTION_DIR_CONTROL, - /** Stop counter on event */ - TCC_EVENT1_ACTION_STOP = TCC_EVENT_ACTION_STOP, - /** Decrement on event */ - TCC_EVENT1_ACTION_DECREMENT = TCC_EVENT_ACTION_DECREMENT, - - /** Store period in capture register 0, pulse width in capture - * register 1 - */ - TCC_EVENT1_ACTION_PERIOD_PULSE_WIDTH_CAPTURE = TCC_EVENT_ACTION_PERIOD_PULSE_WIDTH_CAPTURE, - /** Store pulse width in capture register 0, period in capture - * register 1 - */ - TCC_EVENT1_ACTION_PULSE_WIDTH_PERIOD_CAPTURE = TCC_EVENT_ACTION_PULSE_WIDTH_PERIOD_CAPTURE, - - /** Generate Non-Recoverable Fault on event */ - TCC_EVENT1_ACTION_NON_RECOVERABLE_FAULT = TCC_EVENT_ACTION_NON_RECOVERABLE_FAULT -}; - -/** - * \brief On which part of the counter cycle the counter event output is generated - * - * This enum is used to define the point at which the counter event is generated. - */ -enum tcc_event_generation_selection { - /** Counter Event is generated when a new counter cycle starts */ - TCC_EVENT_GENERATION_SELECTION_START, - /** Counter Event is generated when a counter cycle ends */ - TCC_EVENT_GENERATION_SELECTION_END, - /** Counter Event is generated when a counter cycle ends, except for the - * first and last cycles */ - TCC_EVENT_GENERATION_SELECTION_BETWEEN, - /** Counter Event is generated when a new counter cycle starts or ends */ - TCC_EVENT_GENERATION_SELECTION_BOUNDARY -}; - -/** - * \brief TCC channel operation modes - * - * To set a timer channel either in compare or in capture mode. - */ -enum tcc_channel_function { - /** TCC channel performs compare operation */ - TCC_CHANNEL_FUNCTION_COMPARE, - /** TCC channel performs capture operation */ - TCC_CHANNEL_FUNCTION_CAPTURE -}; - -/** - * \brief TCC (recoverable) fault Halt action - */ -enum tcc_fault_halt_action { - /** Halt action disabled. */ - TCC_FAULT_HALT_ACTION_DISABLE, - /** Hardware halt action, counter is halted until restart */ - TCC_FAULT_HALT_ACTION_HW_HALT, - /** Software halt action, counter is halted until fault bit cleared */ - TCC_FAULT_HALT_ACTION_SW_HALT, - /** Non-Recoverable fault, force output to pre-defined level */ - TCC_FAULT_HALT_ACTION_NON_RECOVERABLE -}; - -/** - * \brief TCC (recoverable) fault Capture action - */ -enum tcc_fault_capture_action { - /** Capture disabled */ - TCC_FAULT_CAPTURE_DISABLE, - /** Capture on Fault, each value is captured */ - TCC_FAULT_CAPTURE_EACH, - /** Capture the minimum detection, but notify on smaller ones */ - TCC_FAULT_CAPTURE_MINIMUM, - /** Capture the maximum detection, but notify on bigger ones */ - TCC_FAULT_CAPTURE_MAXIMUM, - /** Capture if the value is smaller than last, notify event or interrupt - * if previous stamp is confirmed to be "local minimum" (not bigger than - * current stamp). */ - TCC_FAULT_CAPTURE_SMALLER, - /** Capture if the value is bigger than last, notify event or interrupt - * if previous stamp is confirmed to be "local maximum" (not smaller than - * current stamp). */ - TCC_FAULT_CAPTURE_BIGGER, - /** Capture if the time stamps changes its increment direction */ - TCC_FAULT_CAPTURE_CHANGE -}; - -/** - * \brief Capture Channel triggered by TCC (recoverable) fault - */ -enum tcc_fault_capture_channel { - /** Recoverable fault triggers channel 0 capture operation */ - TCC_FAULT_CAPTURE_CHANNEL_0, - /** Recoverable fault triggers channel 1 capture operation */ - TCC_FAULT_CAPTURE_CHANNEL_1, - /** Recoverable fault triggers channel 2 capture operation */ - TCC_FAULT_CAPTURE_CHANNEL_2, - /** Recoverable fault triggers channel 3 capture operation */ - TCC_FAULT_CAPTURE_CHANNEL_3 -}; - -/** - * \brief TCC (recoverable) fault Input Source - */ -enum tcc_fault_source { - /** Fault input is disabled */ - TCC_FAULT_SOURCE_DISABLE, - /** Match Capture Event x (x=0,1) input */ - TCC_FAULT_SOURCE_ENABLE, - /** Inverted MCEx (x=0,1) event input */ - TCC_FAULT_SOURCE_INVERT, - /** Alternate fault (A or B) state at the end of the previous period */ - TCC_FAULT_SOURCE_ALTFAULT -}; - -/** - * \brief TCC (recoverable) fault Input Blanking Start Point - */ -enum tcc_fault_blanking { - /** No blanking */ - TCC_FAULT_BLANKING_DISABLE, - /** Blanking applied from rising edge of the output waveform */ - TCC_FAULT_BLANKING_RISING_EDGE, - /** Blanking applied from falling edge of the output waveform */ - TCC_FAULT_BLANKING_FALLING_EDGE, - /** Blanking applied from each toggle of the output waveform */ - TCC_FAULT_BLANKING_BOTH_EDGE -}; - -/** - * \brief TCC (recoverable) fault Input Qualification Action - */ -enum tcc_fault_qualification { - /** The input is not disabled on compare condition */ - TCC_FAULT_QUALIFICATION_DISABLE, - /** The input is disabled when match output signal is at inactive level */ - TCC_FAULT_QUALIFICATION_BY_OUTPUT -}; - -/** - * \brief TCC (recoverable) fault Output Keep Action - */ -enum tcc_fault_keep { - /** Disable keeping, wave output released as soon as fault is released */ - TCC_FAULT_KEEP_DISABLE, - /** Keep wave output until end of TCC cycle */ - TCC_FAULT_KEEP_TILL_END -}; - -/** - * \brief TCC Non-recoverable State Outupt - */ -enum tcc_fault_state_output { - /** Non-recoverable fault output is tri-stated */ - TCC_FAULT_STATE_OUTPUT_OFF, - /** Non-recoverable fault force output 0 */ - TCC_FAULT_STATE_OUTPUT_0, - /** Non-recoverable fault force output 1 */ - TCC_FAULT_STATE_OUTPUT_1 -}; - -/** - * \brief TCC (recoverable) fault Restart Action - */ -enum tcc_fault_restart { - /** Restart Action disabled */ - TCC_FAULT_RESTART_DISABLE, - /** Restart Action enabled */ - TCC_FAULT_RESTART_ENABLE -}; - -/** - * \brief Configuration struct for TCC module recoverable fault - */ -struct tcc_recoverable_fault_config { - /** Fault filter value applied on MCEx event input line (0x0 ~ 0xF). - * Must be 0 when MCEx event is used as synchronous event. - * Apply to both recoverable and non-recoverable fault. */ - uint8_t filter_value; - /** Fault blanking value (0 ~ 255), disable input source for several TCC - * clocks after the detection of the waveform edge */ - uint8_t blanking_cycles; - - /** Set to \c true to enable restart action */ - bool restart; - /** Set to \c true to enable keep action (keep until end of TCC cycle) */ - bool keep; - - /** Set to \c true to enable input qualification - * (disable input when output is inactive) */ - bool qualification; - - /** Specifies if the event input generates recoverable Fault. - * The event system channel connected to MCEx event input must be - * configured as asynchronous. - */ - enum tcc_fault_source source; - /** Fault Blanking Start Point for recoverable Fault */ - enum tcc_fault_blanking blanking; - - /** Halt action for recoverable Fault */ - enum tcc_fault_halt_action halt_action; - /** Capture action for recoverable Fault */ - enum tcc_fault_capture_action capture_action; - /** Channel triggered by recoverable Fault */ - enum tcc_fault_capture_channel capture_channel; -}; - -/** - * \brief Configuration struct for TCC module non-recoverable fault - */ -struct tcc_non_recoverable_fault_config { - /** Fault filter value applied on TCEx event input line (0x0 ~ 0xF). - * Must be 0 when TCEx event is used as synchronous event. */ - uint8_t filter_value; - /** Output */ - enum tcc_fault_state_output output; -}; - -/** - * \brief TCC input event enable/disable/configure structure - * - * For configuring an input event. - */ -struct tcc_input_event_config { - /** Event action on incoming event */ - enum tcc_event_action action; - /** Modify event action */ - bool modify_action; - /** Invert incoming event input line */ - bool invert; -}; - -/** - * \brief TCC output event enable/disable/configure structure - * - * Structure used for configuring an output event. - */ -struct tcc_output_event_config { - /** It decides which part of the counter cycle the counter event output - * is generated */ - enum tcc_event_generation_selection generation_selection; - /** A switch to allow enable/disable of events, without modifying the - * event output configuration - */ - bool modify_generation_selection; -}; - -/** - * \brief TCC event enable/disable structure - * - * Event flags for the \ref tcc_enable_events() and \ref tcc_disable_events(). - */ -struct tcc_events { - /** Input events configuration */ - struct tcc_input_event_config input_config[2]; - /** Output event configuration */ - struct tcc_output_event_config output_config; - - /** Perform the configured event action when an incoming event is - * signalled */ - bool on_input_event_perform_action[2]; - - /** Perform the configured event action when an incoming channel event is - * signalled */ - bool on_event_perform_channel_action[TCC_NUM_CHANNELS]; - /** Generate an output event on a channel capture/match. - * Specify which channels will generate events */ - bool generate_event_on_channel[TCC_NUM_CHANNELS]; - - /** Generate an output event on counter overflow/underflow */ - bool generate_event_on_counter_overflow; - /** Generate an output event on counter retrigger */ - bool generate_event_on_counter_retrigger; - /** Generate an output event on counter boundary. - * See \ref tcc_event_output_action. */ - bool generate_event_on_counter_event; -}; - -/** - * \brief Configuration struct for the TCC module base counter - * - * Structure for configuring a TCC as a counter. - */ -struct tcc_counter_config { - /** Value to initialize the count register */ - uint32_t count; - /** Period/top and period/top buffer values for counter */ - uint32_t period; - - /** When \c true, the counter will be stopped on the next hardware or - * software re-trigger event or overflow/underflow - */ - bool oneshot; - -#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER - /** Counter overflow trigger a DMA request mode */ - enum tcc_count_overflow_dma_trigger_mode dma_trigger_mode; -#endif - - /** Specifies the direction for the TCC to count */ - enum tcc_count_direction direction; - - /** GCLK generator used to clock the peripheral */ - enum gclk_generator clock_source; - /** Specifies the prescaler value for GCLK_TCC */ - enum tcc_clock_prescaler clock_prescaler; - /** Specifies the reload or reset time of the counter and prescaler - * resynchronization on a re-trigger event for the TCC - */ - enum tcc_reload_action reload_action; -}; - -/** - * \brief Configuration struct for the TCC module capture - * - * Structure used when configuring TCC channels in capture mode. - */ -struct tcc_capture_config { - /** Channel functions selection (capture/match) */ - enum tcc_channel_function channel_function[TCC_NUM_CHANNELS]; -}; - -/** - * \brief Configuration struct for the TCC module match/wave generation - * - * The structure, which helps to configure a TCC channel for compare - * operation and wave generation. - */ -struct tcc_match_wave_config { - /** Channel functions selection (capture/match) */ - enum tcc_channel_function channel_function[TCC_NUM_CHANNELS]; - - /** Specifies polarity for match output waveform generation */ - enum tcc_wave_polarity wave_polarity[TCC_NUM_CHANNELS]; - /** Specifies which waveform generation mode to use */ - enum tcc_wave_generation wave_generation; - /** Specifies Ramp mode for waveform generation */ - enum tcc_ramp wave_ramp; - - /** Value to be used for compare match on each channel */ - uint32_t match[TCC_NUM_CHANNELS]; -}; - -/** - * \brief Configuration struct for the TCC module waveform extension - * - * This structure is used to specify the waveform extension features for TCC. - */ -struct tcc_wave_extension_config { - /** Configuration for recoverable faults */ - struct tcc_recoverable_fault_config - recoverable_fault[TCC_NUM_FAULTS]; - /** Configuration for non-recoverable faults */ - struct tcc_non_recoverable_fault_config - non_recoverable_fault[TCC_NUM_WAVE_OUTPUTS]; - - /** Invert waveform final outputs lines */ - bool invert[TCC_NUM_WAVE_OUTPUTS]; -}; - -/** - * \brief Configuration struct for the TCC module output pins - * - * Structure which is used when taking wave output from TCC. - */ -struct tcc_pins_config { - /** Specifies pin output for each channel */ - uint32_t wave_out_pin[TCC_NUM_WAVE_OUTPUTS]; - /** Specifies MUX setting for each output channel pin */ - uint32_t wave_out_pin_mux[TCC_NUM_WAVE_OUTPUTS]; - /** When \c true, PWM output pin for the given channel is enabled */ - bool enable_wave_out_pin[TCC_NUM_WAVE_OUTPUTS]; -}; - -/** - * \brief TCC configuration structure - * - * Configuration struct for a TCC instance. This structure should be - * initialized by the \ref tcc_get_config_defaults function before being - * modified by the user application. - */ -struct tcc_config { - /** Structure for configuring TCC base timer/counter */ - struct tcc_counter_config counter; - /** TCC match/capture configurations */ - union { - /** Helps to configure a TCC channel in capture mode */ - struct tcc_capture_config capture; - /** For configuring a TCC channel in compare mode */ - struct tcc_match_wave_config compare; - /** Serves the same purpose as compare. Used as an alias for - * compare, - * when a TCC channel is configured for wave generation */ - struct tcc_match_wave_config wave; - }; - - /** Structure for configuring TCC waveform extension */ - struct tcc_wave_extension_config wave_ext; - - /** Structure for configuring TCC output pins */ - struct tcc_pins_config pins; - - /** Set to \c true to enable double buffering write. When enabled any write - * through \ref tcc_set_top_value(), \ref tcc_set_compare_value() and - * \ref tcc_set_pattern() will direct to the buffer register as buffered - * value, and the buffered value will be committed to effective register - * on UPDATE condition, if update is not locked. - * - * \note The init values in \ref tcc_config for \ref tcc_init are always - * filled to effective registers, no matter if double buffering is - * enabled or not. - */ - bool double_buffering_enabled; - - /** When \c true the module is enabled during standby */ - bool run_in_standby; -}; - -#if TCC_ASYNC == true -/* Forward Declaration for the device instance. */ -struct tcc_module; - -/** Type definition for the TCC callback function. */ -typedef void (*tcc_callback_t)(struct tcc_module *const module); -#endif - -/** - * \brief TCC software device instance structure - * - * TCC software instance structure, used to retain software state information - * of an associated hardware module instance. - * - * \note The fields of this structure should not be altered by the user - * application; they are reserved only for module-internal use. - */ -struct tcc_module { - /** Hardware module pointer of the associated Timer/Counter peripheral. */ - Tcc *hw; - -# if TCC_ASYNC == true - /** Array of callbacks */ - tcc_callback_t callback[TCC_CALLBACK_N]; - /** Bit mask for callbacks registered */ - uint32_t register_callback_mask; - /** Bit mask for callbacks enabled */ - uint32_t enable_callback_mask; -# endif - - /** Set to \c true to write to buffered registers */ - bool double_buffering_enabled; -}; - -#if !defined(__DOXYGEN__) -uint8_t _tcc_get_inst_index( - Tcc *const hw); -#endif - -/** - * \name Driver Initialization and Configuration - * @{ - */ - -/** - * \brief Determines if the hardware module is currently synchronizing to the bus - * - * Checks to see if the underlying hardware peripheral module is currently - * synchronizing across multiple clock domains to the hardware bus. This - * function can be used to delay further operations on a module until such time - * that it is ready, to prevent blocking delays for synchronization in the - * user application. - * - * \param[in] module_inst Pointer to the software module instance struct - * - * \return Synchronization status of the underlying hardware module. - * - * \retval false If the module has completed synchronization - * \retval true If the module synchronization is ongoing - */ -static inline bool tcc_is_syncing( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return (module_inst->hw->SYNCBUSY.reg > 0); -} - - -void tcc_get_config_defaults( - struct tcc_config *const config, - Tcc *const hw); - -enum status_code tcc_init( - struct tcc_module *const module_inst, - Tcc *const hw, - const struct tcc_config *const config); - -/** @} */ - -/** - * \name Event Management - * @{ - */ - -enum status_code tcc_enable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events); - -void tcc_disable_events( - struct tcc_module *const module_inst, - struct tcc_events *const events); - -/** @} */ - -/** - * \name Enable/Disable/Reset - * @{ - */ - -/** - * \brief Enable the TCC module - * - * Enables a TCC module that has been previously initialized. The counter will - * start when the counter is enabled. - * - * \note When the counter is configured to re-trigger on an event, the counter - * will not start until the next incoming event appears. Then it - * restarts on any following event. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_enable( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) { - /* Wait for sync */ - } - - /* Enable the TCC module */ - tcc_module->CTRLA.reg |= TCC_CTRLA_ENABLE; -} - -/** - * \brief Disables the TCC module - * - * Disables a TCC module and stops the counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_disable( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) { - /* Wait for sync */ - } - - /* Disbale interrupt */ - tcc_module->INTENCLR.reg = TCC_INTENCLR_MASK; - /* Clear interrupt flag */ - tcc_module->INTFLAG.reg = TCC_INTFLAG_MASK; - - /* Disable the TCC module */ - tcc_module->CTRLA.reg &= ~TC_CTRLA_ENABLE; -} - -/** - * \brief Resets the TCC module - * - * Resets the TCC module, restoring all hardware module registers to their - * default values and disabling the module. The TCC module will not be - * accessible while the reset is being performed. - * - * \note When resetting a 32-bit counter only the master TCC module's instance - * structure should be passed to the function. - * - * \param[in] module_inst Pointer to the software module instance struct - * - */ -static inline void tcc_reset( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - /* Disable this module if it is running */ - if (tcc_module->CTRLA.reg & TCC_CTRLA_ENABLE) { - tcc_disable(module_inst); - while (tcc_is_syncing(module_inst)) { - /* wait while module is disabling */ - } - } - - /* Reset this TC module */ - tcc_module->CTRLA.reg |= TCC_CTRLA_SWRST; -} - -/** @} */ - - -/** - * \name Set/Toggle Count Direction - * @{ - */ - -/** - * \brief Sets the TCC module count direction - * - * Sets the count direction of an initialized TCC module. The - * specified TCC module can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] dir New timer count direction to set - */ -static inline void tcc_set_count_direction( - const struct tcc_module *const module_inst, - enum tcc_count_direction dir) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - - /* Set count direction */ - if (TCC_COUNT_DIRECTION_DOWN == dir) { - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR; - return; - } - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR; -} - -/** - * \brief Toggles the TCC module count direction - * - * Toggles the count direction of an initialized TCC module. The - * specified TCC module can remain running or stopped. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_toggle_count_direction( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - bool dir_value_1 = tcc_module->CTRLBSET.bit.DIR; - if (dir_value_1) { - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_DIR; - } else { - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_DIR; - } -} - -/** @} */ - -/** - * \name Get/Set Count Value - * @{ - */ - -uint32_t tcc_get_count_value( - const struct tcc_module *const module_inst); - -enum status_code tcc_set_count_value( - const struct tcc_module *const module_inst, - const uint32_t count); - -/** @} */ - -/** - * \name Stop/Restart Counter - * @{ - */ - -/** - * \brief Stops the counter - * - * This function will stop the counter. When the counter is stopped - * the value in the count register is set to 0 if the counter was - * counting up, or maximum or the top value if the counter was counting - * down. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_stop_counter( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (last_cmd == TCC_CTRLBSET_CMD_NONE) { - break; - } else if (last_cmd == TCC_CTRLBSET_CMD_STOP) { - /* Command have been issued */ - return; - } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) { - /* Cancel RETRIGGER command and issue STOP */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_STOP; -} - -/** - * \brief Starts the counter from beginning - * - * Restarts an initialized TCC module's counter. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_restart_counter( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (last_cmd == TCC_CTRLBSET_CMD_NONE) { - break; - } else if (last_cmd == TCC_CTRLBSET_CMD_RETRIGGER) { - /* Command have been issued */ - return; - } else if (last_cmd == TCC_CTRLBSET_CMD_STOP) { - /* Cancel STOP command and issue RETRIGGER */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_Msk; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_RETRIGGER; -} - -/** @} */ - -#ifdef FEATURE_TCC_GENERATE_DMA_TRIGGER -/** - * \name Generate TCC DMA Triggers Command - * @{ - */ - -/** - * \brief TCC DMA Trigger. - * - * TCC DMA trigger command. - * - * \param[in] module_inst Pointer to the software module instance struct - */ -static inline void tcc_dma_trigger_command( - const struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - - /* Make certain that there are no conflicting commands in the register */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBCLR_CMD_NONE; - - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - -#if !(SAML21 || SAML22 || SAMR30) - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMATRG; -#endif - -#if (SAML21XXXB) || (SAML22) || (SAMR30) - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_DMAOS; -#endif -} -/** @} */ -#endif - -/** - * \name Get/Set Compare/Capture Register - * @{ - */ - -uint32_t tcc_get_capture_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index); - -enum status_code tcc_set_compare_value( - const struct tcc_module *const module_inst, - const enum tcc_match_capture_channel channel_index, - const uint32_t compare); - -/** @} */ - -/** - * \name Set Top Value - * @{ - */ - -enum status_code tcc_set_top_value( - const struct tcc_module *const module_inst, - const uint32_t top_value); - -/** @} */ - - -/** - * \name Set Output Pattern - * @{ - */ - -enum status_code tcc_set_pattern( - const struct tcc_module *const module_inst, - const uint32_t line_index, - const enum tcc_output_pattern pattern); - -/** @} */ - - -/** - * \name Set Ramp Index - * @{ - */ - -/** - * \brief Sets the TCC module ramp index on next cycle - * - * In RAMP2 and RAMP2A operation, we can force either cycle A or cycle B at - * the output, on the next clock cycle. - * When ramp index command is disabled, cycle A and cycle B will appear at - * the output, on alternate clock cycles. - * See \ref tcc_ramp. - * - * \param[in] module_inst Pointer to the software module instance struct - * \param[in] ramp_index Ramp index (\ref tcc_ramp_index) of the next cycle - */ -static inline void tcc_set_ramp_index( - const struct tcc_module *const module_inst, - const enum tcc_ramp_index ramp_index) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - if (TCC_RAMP_INDEX_DEFAULT == ramp_index) { - /* Cancel pending command */ - tcc_module->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD_HOLD; - return; - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_IDXCMD_Msk; - if (last_cmd == TCC_CTRLBSET_IDXCMD_DISABLE) { - break; - } else if (last_cmd == TCC_CTRLBSET_IDXCMD(ramp_index)) { - /* Command have been issued */ - return; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(ramp_index); -} - -/** @} */ - -/** - * \name Status Management - * @{ - */ - -/** - * \brief Checks if the timer/counter is running - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - * \return Status which indicates whether the module is running. - * - * \retval true The timer/counter is running - * \retval false The timer/counter is stopped - */ -static inline bool tcc_is_running( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return !module_inst->hw->STATUS.bit.STOP; -} - -uint32_t tcc_get_status( - struct tcc_module *const module_inst); - -void tcc_clear_status( - struct tcc_module *const module_inst, - const uint32_t status_flags); - -/** @} */ - -/** - * \name Double Buffering Management - * @{ - */ - -/** - * \brief Enable TCC double buffering write - * - * When double buffering write is enabled, the following function will write - * values to buffered registers instead of effective ones (buffered): - * - PERB: through \ref tcc_set_top_value() - * - CCBx(x is 0~3): through \ref tcc_set_compare_value() - * - PATTB: through \ref tcc_set_pattern() - * - * Then, on UPDATE condition the buffered registers are committed to regular ones - * to take effect. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_enable_double_buffering( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - - module_inst->double_buffering_enabled = true; -} - -/** - * \brief Disable TCC double buffering Write - * - * When double buffering write is disabled, following function will write values - * to effective registers (not buffered): - * - PER: through \ref tcc_set_top_value() - * - CCx(x is 0~3): through \ref tcc_set_compare_value() - * - PATT: through \ref tcc_set_pattern() - * - * \note This function does not lock double buffer update, which means on next - * UPDATE condition the last written buffered values will be committed to - * take effect. Invoke \ref tcc_lock_double_buffer_update() before this - * function to disable double buffering update, if this change is not - * expected. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_disable_double_buffering( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->double_buffering_enabled = false; -} - -/** - * \brief Lock the TCC double buffered registers updates - * - * Locks the double buffered registers so they will not be updated through - * their buffered values on UPDATE conditions. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - */ -static inline void tcc_lock_double_buffer_update( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - module_inst->hw->CTRLBSET.reg = TCC_CTRLBSET_LUPD; -} - -/** - * \brief Unlock the TCC double buffered registers updates - * - * Unlock the double buffered registers so they will be updated through - * their buffered values on UPDATE conditions. - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - */ -static inline void tcc_unlock_double_buffer_update( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - while (module_inst->hw->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - module_inst->hw->CTRLBCLR.reg = TCC_CTRLBCLR_LUPD; -} - -/** - * \brief Force the TCC double buffered registers to update once - * - * \param[in] module_inst Pointer to the TCC software instance struct - * - */ -static inline void tcc_force_double_buffer_update( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Get a pointer to the module's hardware instance */ - Tcc *const tcc_module = module_inst->hw; - uint32_t last_cmd; - - /* Wait until last command is done */ - do { - while (tcc_module->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) { - /* Wait for sync */ - } - last_cmd = tcc_module->CTRLBSET.reg & TCC_CTRLBSET_CMD_Msk; - if (last_cmd == TCC_CTRLBSET_CMD_NONE) { - break; - } else if (last_cmd == TCC_CTRLBSET_CMD_UPDATE) { - /* Command have been issued */ - return; - } - } while (1); - - /* Write command to execute */ - tcc_module->CTRLBSET.reg = TCC_CTRLBSET_CMD_UPDATE; -} - -/** - * \brief Enable Circular option for double buffered Top/Period Values - * - * Enable circular option for the double buffered top/period values. - * On each UPDATE condition, the contents of PERB and PER are switched, meaning - * that the contents of PERB are transferred to PER and the contents of PER are - * transferred to PERB. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_enable_circular_buffer_top( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->WAVE.reg |= TCC_WAVE_CIPEREN; -} - -/** - * \brief Disable Circular option for double buffered Top/Period Values - * - * Stop circularing the double buffered top/period values. - * - * \param[in] module_inst Pointer to the TCC software instance struct - */ -static inline void tcc_disable_circular_buffer_top( - struct tcc_module *const module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->WAVE.reg &= ~TCC_WAVE_CIPEREN; -} - -enum status_code tcc_set_double_buffer_top_values( - const struct tcc_module *const module_inst, - const uint32_t top_value, const uint32_t top_buffer_value); - - -enum status_code tcc_enable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index); -enum status_code tcc_disable_circular_buffer_compare( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index); -enum status_code tcc_set_double_buffer_compare_values( - struct tcc_module *const module_inst, - enum tcc_match_capture_channel channel_index, - const uint32_t compare, - const uint32_t compare_buffer); - - -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -/** - * \page asfdoc_sam0_tcc_extra Extra Information for TCC Driver - * - * \section asfdoc_sam0_tcc_extra_acronyms Acronyms - * The table below presents the acronyms used in this module: - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
AcronymDescription
DMADirect Memory Access
TCCTimer Counter for Control Applications
PWMPulse Width Modulation
PWPPulse Width Period
PPWPeriod Pulse Width
- * - * - * \section asfdoc_sam0_tcc_extra_dependencies Dependencies - * This driver has the following dependencies: - * - * - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver" - * - * - * \section asfdoc_sam0_tcc_extra_errata Errata - * There are no errata related to this driver. - * - * - * \section asfdoc_sam0_tcc_extra_history Module History - * An overview of the module history is presented in the table below, with - * details on the enhancements and fixes made to the module since its first - * release. The current version of this corresponds to the newest version in - * the table. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Changelog
Add double buffering functionality
Add fault handling functionality
Initial Release
- */ - -/** - * \page asfdoc_sam0_tcc_exqsg Examples for TCC Driver - * - * This is a list of the available Quick Start guides (QSGs) and example - * applications for \ref asfdoc_sam0_tcc_group. QSGs are simple examples with - * step-by-step instructions to configure and use this driver in a selection of - * use cases. Note that QSGs can be compiled as a standalone application or be - * added to the user application. - * - * - \subpage asfdoc_sam0_tcc_basic_use_case - * - \subpage asfdoc_sam0_tcc_buffering_use_case - * \if TCC_CALLBACK_MODE - * - \subpage asfdoc_sam0_tcc_timer_use_case - * - \subpage asfdoc_sam0_tcc_callback_use_case - * - \subpage asfdoc_sam0_tcc_faultx_use_case - * - \subpage asfdoc_sam0_tcc_faultn_use_case - * \endif - * - \subpage asfdoc_sam0_tcc_dma_use_case - * - * \page asfdoc_sam0_tcc_document_revision_history Document Revision History - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Doc. Rev.DateComments
42256C12/2015Added support for SAM L21/L22, SAM DA1, and SAM C20/C21
42256B12/2014Added fault handling functionality. - * Added double buffering functionality with use case. - * Added timer use case. - * Added SAM R21/D10/D11 support.
42256A01/2014Initial release
- */ - -#endif /* TCC_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/tcc/tcc_callback.c b/atmel-samd/asf/sam0/drivers/tcc/tcc_callback.c deleted file mode 100644 index aa1d5e3e94776..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tcc/tcc_callback.c +++ /dev/null @@ -1,245 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - Timer Counter for Control Applications Callback Driver - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "tcc_callback.h" - -void *_tcc_instances[TCC_INST_NUM]; - -void _tcc_interrupt_handler(uint8_t module_index); - -const uint32_t _tcc_intflag[TCC_CALLBACK_N] = { - TCC_INTFLAG_OVF, - TCC_INTFLAG_TRG, - TCC_INTFLAG_CNT, - TCC_INTFLAG_ERR, - TCC_INTFLAG_FAULTA, - TCC_INTFLAG_FAULTB, - TCC_INTFLAG_FAULT0, - TCC_INTFLAG_FAULT1, -#define _TCC_INTFLAG_MC(n,dummy) TCC_INTFLAG_MC##n, - /* TCC_INTFLAG_MC0 ~ ... */ - MREPEAT(TCC_NUM_CHANNELS, _TCC_INTFLAG_MC, 0) -#undef _TCC_INTFLAG_MC -}; - -# define _TCC_INTERRUPT_VECT_NUM(n, unused) \ - SYSTEM_INTERRUPT_MODULE_TCC##n, -/** - * \internal Get the interrupt vector for the given device instance - * - * \param[in] The TCC module instance number - * - * \return Interrupt vector for of the given TCC module instance. - */ -static enum system_interrupt_vector _tcc_interrupt_get_interrupt_vector( - uint32_t inst_num) -{ - static uint8_t tcc_interrupt_vectors[TCC_INST_NUM] = { - MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_VECT_NUM, 0) - }; - - return (enum system_interrupt_vector)tcc_interrupt_vectors[inst_num]; -} - -/** - * \brief Registers a callback - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref tcc_enable_callback, - * in order for the interrupt handler to call it when the conditions for the - * callback type is met. - * - * \param[in] module Pointer to TCC software instance struct - * \param[in] callback_func Pointer to callback function - * \param[in] callback_type Callback type given by an enum - */ -enum status_code tcc_register_callback( - struct tcc_module *const module, - tcc_callback_t callback_func, - const enum tcc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(callback_func); - - /* Register callback function */ - module->callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module->register_callback_mask |= _tcc_intflag[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Unregisters a callback - * - * Unregisters a callback function implemented by the user. The callback should - * be disabled before it is unregistered. - * - * \param[in] module Pointer to TCC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -enum status_code tcc_unregister_callback( - struct tcc_module *const module, - const enum tcc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - - /* Unregister callback function */ - module->callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module->register_callback_mask &= ~_tcc_intflag[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Enables callback - * - * Enables the callback function registered by the \ref - * tcc_register_callback. The callback function will be called from the - * interrupt handler when the conditions for the callback type are - * met. This function will also enable the appropriate interrupts. - * - * \param[in] module Pointer to TCC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -void tcc_enable_callback( - struct tcc_module *const module, - const enum tcc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Enable interrupts for this TCC module */ - system_interrupt_enable(_tcc_interrupt_get_interrupt_vector( - _tcc_get_inst_index(module->hw))); - - /* Enable channel or other callbacks */ - module->enable_callback_mask |= _tcc_intflag[callback_type]; - module->hw->INTENSET.reg = _tcc_intflag[callback_type]; -} - -/** - * \brief Disables callback - * - * Disables the callback function registered by the \ref - * tcc_register_callback, and the callback will not be called from the - * interrupt routine. The function will also disable the appropriate - * interrupts. - * - * \param[in] module Pointer to TCC software instance struct - * \param[in] callback_type Callback type given by an enum - */ -void tcc_disable_callback( - struct tcc_module *const module, - const enum tcc_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module); - Assert(module->hw); - - /* Disable interrupts for this TCC module */ - system_interrupt_disable(_tcc_interrupt_get_interrupt_vector( - _tcc_get_inst_index(module->hw))); - - /* Disable channel or other callbacks */ - module->enable_callback_mask &= ~_tcc_intflag[callback_type]; - module->hw->INTENCLR.reg = _tcc_intflag[callback_type]; -} - - -/** - * \internal ISR handler for TCC - * - * Auto-generate a set of interrupt handlers for each TCC in the device. - */ -#define _TCC_INTERRUPT_HANDLER(n, m) \ - void TCC##n##_Handler(void) \ - { \ - _tcc_interrupt_handler(n); \ - } - -MREPEAT(TCC_INST_NUM, _TCC_INTERRUPT_HANDLER, 0) - -/** - * \internal Interrupt handler for the TCC module - * - * Handles interrupts as they occur, it will run the callback functions - * that are registered and enabled. - * - * \param[in] module_index ID of the TCC instance calling the interrupt - * handler - */ -void _tcc_interrupt_handler( - uint8_t module_index) -{ - int i; - - uint32_t interrupt_and_callback_status_mask; - - struct tcc_module *module = - (struct tcc_module *)_tcc_instances[module_index]; - - interrupt_and_callback_status_mask = (module->hw->INTFLAG.reg & - module->register_callback_mask & - module->enable_callback_mask); - - /* Check if callback interrupt has occured */ - for (i = 0; i < TCC_CALLBACK_N; i ++) { - if (interrupt_and_callback_status_mask & _tcc_intflag[i]) { - /* Invoke the registered and enabled callback function */ - (module->callback[i])(module); - /* Clear interrupt flag */ - module->hw->INTFLAG.reg = _tcc_intflag[i]; - } - } -} diff --git a/atmel-samd/asf/sam0/drivers/tcc/tcc_callback.h b/atmel-samd/asf/sam0/drivers/tcc/tcc_callback.h deleted file mode 100644 index 37b0bbb72797f..0000000000000 --- a/atmel-samd/asf/sam0/drivers/tcc/tcc_callback.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - Timer Counter for Control Applications Callback Driver - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef TCC_CALLBACK_H_INCLUDED -#define TCC_CALLBACK_H_INCLUDED - -#include "tcc.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if !defined(__DOXYGEN__) -extern void *_tcc_instances[TCC_INST_NUM]; -#endif - - -/** - * \name Callback Management - * {@ - */ - -enum status_code tcc_register_callback( - struct tcc_module *const module, - tcc_callback_t callback_func, - const enum tcc_callback callback_type); - -enum status_code tcc_unregister_callback( - struct tcc_module *const module, - const enum tcc_callback callback_type); - -void tcc_enable_callback( - struct tcc_module *const module, - const enum tcc_callback callback_type); - -void tcc_disable_callback( - struct tcc_module *const module, - const enum tcc_callback callback_type); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* TCC_CALLBACK_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.dual/doxyfile.doxygen b/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.dual/doxyfile.doxygen deleted file mode 100644 index 2fa7ea9d16c82..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.dual/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../usb_dual.c ../../usb_dual.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.dual/doxygen_module_mainpage.h b/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.dual/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.dual/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.udd/doxyfile.doxygen b/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.udd/doxyfile.doxygen deleted file mode 100644 index 80878283519ee..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.udd/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "SAM D21/R21/D11/L21/L22/DA1 USB UDD interface" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../usb_device_udd.c - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.udd/doxygen_module_mainpage.h b/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.udd/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.udd/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.uhd/doxyfile.doxygen b/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.uhd/doxyfile.doxygen deleted file mode 100644 index 917c97665ef9a..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.uhd/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "SAM D21/R21/L21/DA1 USB UHD interface" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = NO - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES += asf_license_start=" " -ALIASES += asf_license_stop=" " - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = YES - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../usb_host_uhd.c - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = ../.. - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. 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This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.uhd/doxygen_module_mainpage.h b/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.uhd/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/doxygen/sam0.drivers.usb.uhd/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
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- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_device_udd.c b/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_device_udd.c deleted file mode 100644 index d40b02126f92f..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_device_udd.c +++ /dev/null @@ -1,1276 +0,0 @@ -/** - * \file - * - * \brief USB Device wrapper layer for compliance with common driver UDD - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include - -// Get USB device configuration -#include "conf_usb.h" -#include "udd.h" -#include "usb.h" -#include "usb_dual.h" -#include "sleepmgr.h" - -/** - * \ingroup usb_device_group - * \defgroup usb_device_udd_group USB Device Driver Implement (UDD) - * USB low-level driver for USB device mode - * @{ - */ -// Check USB device configuration -#ifdef USB_DEVICE_HS_SUPPORT -# error The High speed mode is not supported on this part, please remove USB_DEVICE_HS_SUPPORT in conf_usb.h -#endif - -#if !(SAMD21) && !(SAMR21) && !(SAMD11) && !(SAML21) && !(SAML22) && !(SAMDA1) && !(SAMR30) -# error The current USB Device Driver supports only SAMD21/R21/D11/L21/L22/DA1 -#endif - -#ifndef UDC_REMOTEWAKEUP_LPM_ENABLE -#define UDC_REMOTEWAKEUP_LPM_ENABLE() -#endif -#ifndef UDC_REMOTEWAKEUP_LPM_DISABLE -#define UDC_REMOTEWAKEUP_LPM_DISABLE() -#endif -#ifndef UDC_SUSPEND_LPM_EVENT -#define UDC_SUSPEND_LPM_EVENT() -#endif - -/* for debug text */ -#ifdef USB_DEBUG -# define dbg_print printf -#else -# define dbg_print(...) -#endif - -/** Maximum size of a transfer in multi-packet mode */ -#define UDD_ENDPOINT_MAX_TRANS ((8*1024)-1) - -/** USB software device instance structure */ -struct usb_module usb_device; - -/** - * \name Clock management - * - * @{ - */ -#ifndef UDD_CLOCK_GEN -#if (SAML21) || (SAML22) || (SAMR30) -# define UDD_CLOCK_GEN GCLK_GENERATOR_3 -#elif (SAMDA1) -# define UDD_CLOCK_GEN GCLK_GENERATOR_1 -#else -# define UDD_CLOCK_GEN GCLK_GENERATOR_0 -#endif -#endif -#ifndef UDD_CLOCK_SOURCE -# define UDD_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL -#endif -static inline void udd_wait_clock_ready(void) -{ - - if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DPLL) { -#if (SAML21) || (SAML22) || (SAMR30) - #define DPLL_READY_FLAG (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK) - - while((OSCCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG); - } -#else -#define DPLL_READY_FLAG (SYSCTRL_DPLLSTATUS_ENABLE | \ - SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK) - - while((SYSCTRL->DPLLSTATUS.reg & DPLL_READY_FLAG) != DPLL_READY_FLAG); - } -#endif - - if (UDD_CLOCK_SOURCE == SYSTEM_CLOCK_SOURCE_DFLL) { -#if (SAML21) || (SAML22) || (SAMR30) -#define DFLL_READY_FLAG (OSCCTRL_STATUS_DFLLRDY | \ - OSCCTRL_STATUS_DFLLLCKF | OSCCTRL_STATUS_DFLLLCKC) - - /* In USB recovery mode the status is not checked */ - if (!(OSCCTRL->DFLLCTRL.reg & OSCCTRL_DFLLCTRL_USBCRM)) { - while((OSCCTRL->STATUS.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG); - } else { - while((OSCCTRL->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) != OSCCTRL_STATUS_DFLLRDY); - } - } -#else -#define DFLL_READY_FLAG (SYSCTRL_PCLKSR_DFLLRDY | \ - SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC) - - /* In USB recovery mode the status is not checked */ - if (!(SYSCTRL->DFLLCTRL.reg & SYSCTRL_DFLLCTRL_USBCRM)) { - while((SYSCTRL->PCLKSR.reg & DFLL_READY_FLAG) != DFLL_READY_FLAG); - } else { - while((SYSCTRL->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) != SYSCTRL_PCLKSR_DFLLRDY); - } - } -#endif -} -/** @} */ - -/** - * \name Power management - * - * @{ - */ -#ifndef UDD_NO_SLEEP_MGR - -#include "sleepmgr.h" -/** States of USB interface */ -enum udd_usb_state_enum { - UDD_STATE_OFF, - UDD_STATE_SUSPEND, - UDD_STATE_SUSPEND_LPM, - UDD_STATE_IDLE, -}; - -/** \brief Manages the sleep mode following the USB state - * - * \param new_state New USB state - */ -static void udd_sleep_mode(enum udd_usb_state_enum new_state) -{ - enum sleepmgr_mode sleep_mode[] = { - SLEEPMGR_ACTIVE, /* UDD_STATE_OFF (not used) */ - #if (SAML21) || (SAML22) || (SAMR30) - SLEEPMGR_IDLE, /* UDD_STATE_SUSPEND */ - SLEEPMGR_IDLE, /* UDD_STATE_SUSPEND_LPM */ - SLEEPMGR_IDLE, /* UDD_STATE_IDLE */ - #else - SLEEPMGR_IDLE_2, /* UDD_STATE_SUSPEND */ - SLEEPMGR_IDLE_1, /* UDD_STATE_SUSPEND_LPM */ - SLEEPMGR_IDLE_0, /* UDD_STATE_IDLE */ - #endif - }; - - static enum udd_usb_state_enum udd_state = UDD_STATE_OFF; - - if (udd_state == new_state) { - return; // No change - } - if (new_state != UDD_STATE_OFF) { - /* Lock new limit */ - sleepmgr_lock_mode(sleep_mode[new_state]); - } - if (udd_state != UDD_STATE_OFF) { - /* Unlock old limit */ - sleepmgr_unlock_mode(sleep_mode[udd_state]); - } - udd_state = new_state; -} - -#else -# define udd_sleep_mode(arg) -#endif -/** @} */ - -/** - * \name Control endpoint low level management routine. - * - * This function performs control endpoint management. - * It handles the SETUP/DATA/HANDSHAKE phases of a control transaction. - * - * @{ - */ - -/** - * \brief Buffer to store the data received on control endpoint (SETUP/OUT endpoint 0) - * - * Used to avoid a RAM buffer overflow in case of the payload buffer - * is smaller than control endpoint size - */ -UDC_BSS(4) -uint8_t udd_ctrl_buffer[USB_DEVICE_EP_CTRL_SIZE]; - -/** Bit definitions about endpoint control state machine for udd_ep_control_state */ -typedef enum { - UDD_EPCTRL_SETUP = 0, //!< Wait a SETUP packet - UDD_EPCTRL_DATA_OUT = 1, //!< Wait a OUT data packet - UDD_EPCTRL_DATA_IN = 2, //!< Wait a IN data packet - UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP = 3, //!< Wait a IN ZLP packet - UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP = 4, //!< Wait a OUT ZLP packet - UDD_EPCTRL_STALL_REQ = 5, //!< STALL enabled on IN & OUT packet -} udd_ctrl_ep_state_t; - -/** Global variable to give and record information of the set up request management */ -udd_ctrl_request_t udd_g_ctrlreq; - -/** State of the endpoint control management */ -static udd_ctrl_ep_state_t udd_ep_control_state; - -/** Total number of data received/sent during data packet phase with previous payload buffers */ -static uint16_t udd_ctrl_prev_payload_nb_trans; - -/** Number of data received/sent to/from udd_g_ctrlreq.payload buffer */ -static uint16_t udd_ctrl_payload_nb_trans; - -/** @} */ - -/** - * \name Management of bulk/interrupt/isochronous endpoints - * - * The UDD manages the data transfer on endpoints: - * - Start data transfer on endpoint with USB Device DMA - * - Send a ZLP packet if requested - * - Call callback registered to signal end of transfer - * The transfer abort and stall feature are supported. - * - * @{ - */ - -/** - * \brief Buffer to store the data received on bulk/interrupt endpoints - * - * Used to avoid a RAM buffer overflow in case of the user buffer - * is smaller than endpoint size - * - * \warning The protected interrupt endpoint size is 512 bytes maximum. - * \warning The isochronous and endpoint is not protected by this system and - * the user must always use a buffer corresponding at endpoint size. - */ -#if (defined USB_DEVICE_LOW_SPEED) -UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][8]; -#elif (defined USB_DEVICE_HS_SUPPORT) -UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][512]; -#else -UDC_BSS(4) uint8_t udd_ep_out_cache_buffer[USB_DEVICE_MAX_EP][64]; -#endif - -/** Structure definition about job registered on an endpoint */ -typedef struct { - union { - //! Callback to call at the end of transfer - udd_callback_trans_t call_trans; - //! Callback to call when the endpoint halt is cleared - udd_callback_halt_cleared_t call_nohalt; - }; - //! Buffer located in internal RAM to send or fill during job - uint8_t *buf; - //! Size of buffer to send or fill - iram_size_t buf_size; - //! Total number of data transferred on endpoint - iram_size_t nb_trans; - //! Endpoint size - uint16_t ep_size; - //! A job is registered on this endpoint - uint8_t busy:1; - //! A short packet is requested for this job on endpoint IN - uint8_t b_shortpacket:1; - //! The cache buffer is currently used on endpoint OUT - uint8_t b_use_out_cache_buffer:1; -} udd_ep_job_t; - -/** Array to register a job on bulk/interrupt/isochronous endpoint */ -static udd_ep_job_t udd_ep_job[2 * USB_DEVICE_MAX_EP]; - -/** @} */ - -/** - * \brief Get the detailed job by endpoint number - * \param[in] ep Endpoint Address - * \retval pointer to an udd_ep_job_t structure instance - */ -static udd_ep_job_t* udd_ep_get_job(udd_ep_id_t ep) -{ - return &udd_ep_job[(2 * (ep & USB_EP_ADDR_MASK) + ((ep & USB_EP_DIR_IN) ? 1 : 0)) - 2]; -} - -/** - * \brief Endpoint IN process, continue to send packets or zero length packet - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void udd_ep_trans_in_next(void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - udd_ep_id_t ep = ep_callback_para->endpoint_address; - uint16_t ep_size, nb_trans; - uint16_t next_trans; - udd_ep_id_t ep_num; - udd_ep_job_t *ptr_job; - - ptr_job = udd_ep_get_job(ep); - ep_num = ep & USB_EP_ADDR_MASK; - - ep_size = ptr_job->ep_size; - /* Update number of data transferred */ - nb_trans = ep_callback_para->sent_bytes; - ptr_job->nb_trans += nb_trans; - - /* Need to send other data */ - if (ptr_job->nb_trans != ptr_job->buf_size) { - next_trans = ptr_job->buf_size - ptr_job->nb_trans; - if (UDD_ENDPOINT_MAX_TRANS < next_trans) { - /* The USB hardware support a maximum - * transfer size of UDD_ENDPOINT_MAX_TRANS Bytes */ - next_trans = UDD_ENDPOINT_MAX_TRANS -(UDD_ENDPOINT_MAX_TRANS % ep_size); - } - /* Need ZLP, if requested and last packet is not a short packet */ - ptr_job->b_shortpacket = ptr_job->b_shortpacket && (0 == (next_trans % ep_size)); - usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans); - return; - } - - /* Need to send a ZLP after all data transfer */ - if (ptr_job->b_shortpacket) { - ptr_job->b_shortpacket = false; - /* Start new transfer */ - usb_device_endpoint_write_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],0); - return; - } - - /* Job complete then call callback */ - ptr_job->busy = false; - if (NULL != ptr_job->call_trans) { - ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep); - } -} - -/** - * \brief Endpoint OUT process, continue to receive packets or zero length packet - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void udd_ep_trans_out_next(void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - udd_ep_id_t ep = ep_callback_para->endpoint_address; - uint16_t ep_size, nb_trans; - uint16_t next_trans; - udd_ep_id_t ep_num; - udd_ep_job_t *ptr_job; - - ptr_job = udd_ep_get_job(ep); - ep_num = ep & USB_EP_ADDR_MASK; - - ep_size = ptr_job->ep_size; - /* Update number of data transferred */ - nb_trans = ep_callback_para->received_bytes; - - /* Can be necessary to copy data receive from cache buffer to user buffer */ - if (ptr_job->b_use_out_cache_buffer) { - memcpy(&ptr_job->buf[ptr_job->nb_trans], udd_ep_out_cache_buffer[ep_num - 1], ptr_job->buf_size % ep_size); - } - - /* Update number of data transferred */ - ptr_job->nb_trans += nb_trans; - if (ptr_job->nb_trans > ptr_job->buf_size) { - ptr_job->nb_trans = ptr_job->buf_size; - } - - /* If all previous data requested are received and user buffer not full - * then need to receive other data */ - if ((nb_trans == ep_callback_para->out_buffer_size) && (ptr_job->nb_trans != ptr_job->buf_size)) { - next_trans = ptr_job->buf_size - ptr_job->nb_trans; - if (UDD_ENDPOINT_MAX_TRANS < next_trans) { - /* The USB hardware support a maximum transfer size - * of UDD_ENDPOINT_MAX_TRANS Bytes */ - next_trans = UDD_ENDPOINT_MAX_TRANS - (UDD_ENDPOINT_MAX_TRANS % ep_size); - } else { - next_trans -= next_trans % ep_size; - } - - if (next_trans < ep_size) { - /* Use the cache buffer for Bulk or Interrupt size endpoint */ - ptr_job->b_use_out_cache_buffer = true; - usb_device_endpoint_read_buffer_job(&usb_device,ep_num,udd_ep_out_cache_buffer[ep_num - 1],ep_size); - } else { - usb_device_endpoint_read_buffer_job(&usb_device,ep_num,&ptr_job->buf[ptr_job->nb_trans],next_trans); - } - return; - } - - /* Job complete then call callback */ - ptr_job->busy = false; - if (NULL != ptr_job->call_trans) { - ptr_job->call_trans(UDD_EP_TRANSFER_OK, ptr_job->nb_trans, ep); - } -} - -/** - * \brief Endpoint Transfer Complete callback function, to do the next transfer depends on the direction(IN or OUT) - * \param[in] module_inst Pointer to USB module instance - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void udd_ep_transfer_process(struct usb_module *module_inst, void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - udd_ep_id_t ep = ep_callback_para->endpoint_address; - - if (ep & USB_EP_DIR_IN) { - udd_ep_trans_in_next(pointer); - } else { - udd_ep_trans_out_next(pointer); - } -} - -void udd_ep_abort(udd_ep_id_t ep) -{ - udd_ep_job_t *ptr_job; - - usb_device_endpoint_abort_job(&usb_device, ep); - - /* Job complete then call callback */ - ptr_job = udd_ep_get_job(ep); - if (!ptr_job->busy) { - return; - } - ptr_job->busy = false; - if (NULL != ptr_job->call_trans) { - /* It can be a Transfer or stall callback */ - ptr_job->call_trans(UDD_EP_TRANSFER_ABORT, ptr_job->nb_trans, ep); - } -} - -bool udd_is_high_speed(void) -{ -#if SAMD21 || SAMR21 || SAMD11 || SAML21 || SAML22 || SAMDA1 || SAMR30 - return false; -#endif -} - -uint16_t udd_get_frame_number(void) -{ - return usb_device_get_frame_number(&usb_device); -} - -uint16_t udd_get_micro_frame_number(void) -{ - return usb_device_get_micro_frame_number(&usb_device); -} - -void udd_ep_free(udd_ep_id_t ep) -{ - struct usb_device_endpoint_config config_ep; - usb_device_endpoint_get_config_defaults(&config_ep); - - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - udd_ep_abort(ep); - - config_ep.ep_address = ep; - config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_DISABLE; - usb_device_endpoint_set_config(&usb_device, &config_ep); - usb_device_endpoint_unregister_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT); - usb_device_endpoint_disable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT); -} - -bool udd_ep_alloc(udd_ep_id_t ep, uint8_t bmAttributes, uint16_t MaxEndpointSize) -{ - struct usb_device_endpoint_config config_ep; - usb_device_endpoint_get_config_defaults(&config_ep); - - config_ep.ep_address = ep; - - if(MaxEndpointSize <= 8) { - config_ep.ep_size = USB_ENDPOINT_8_BYTE; - } else if(MaxEndpointSize <= 16) { - config_ep.ep_size = USB_ENDPOINT_16_BYTE; - } else if(MaxEndpointSize <= 32) { - config_ep.ep_size = USB_ENDPOINT_32_BYTE; - } else if(MaxEndpointSize <= 64) { - config_ep.ep_size = USB_ENDPOINT_64_BYTE; - } else if(MaxEndpointSize <= 128) { - config_ep.ep_size = USB_ENDPOINT_128_BYTE; - } else if(MaxEndpointSize <= 256) { - config_ep.ep_size = USB_ENDPOINT_256_BYTE; - } else if(MaxEndpointSize <= 512) { - config_ep.ep_size = USB_ENDPOINT_512_BYTE; - } else if(MaxEndpointSize <= 1023) { - config_ep.ep_size = USB_ENDPOINT_1023_BYTE; - } else { - return false; - } - udd_ep_job_t *ptr_job = udd_ep_get_job(ep); - ptr_job->ep_size = MaxEndpointSize; - - bmAttributes = bmAttributes & USB_EP_TYPE_MASK; - - /* Check endpoint type */ - if(USB_EP_TYPE_ISOCHRONOUS == bmAttributes) { - config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS; - } else if (USB_EP_TYPE_BULK == bmAttributes) { - config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_BULK; - } else if (USB_EP_TYPE_INTERRUPT == bmAttributes) { - config_ep.ep_type = USB_DEVICE_ENDPOINT_TYPE_INTERRUPT; - } else { - return false; - } - - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - - if (STATUS_OK != usb_device_endpoint_set_config(&usb_device, &config_ep)) { - return false; - } - usb_device_endpoint_register_callback(&usb_device,ep_num,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,udd_ep_transfer_process); - usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT); - usb_device_endpoint_enable_callback(&usb_device,ep,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL); - - return true; -} - -bool udd_ep_is_halted(udd_ep_id_t ep) -{ - return usb_device_endpoint_is_halted(&usb_device, ep); -} - -bool udd_ep_set_halt(udd_ep_id_t ep) -{ - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - - if (USB_DEVICE_MAX_EP < ep_num) { - return false; - } - - usb_device_endpoint_set_halt(&usb_device, ep); - - udd_ep_abort(ep); - return true; -} - -bool udd_ep_clear_halt(udd_ep_id_t ep) -{ - udd_ep_job_t *ptr_job; - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - - if (USB_DEVICE_MAX_EP < ep_num) { - return false; - } - ptr_job = udd_ep_get_job(ep); - - usb_device_endpoint_clear_halt(&usb_device, ep); - - /* If a job is register on clear halt action then execute callback */ - if (ptr_job->busy == true) { - ptr_job->busy = false; - ptr_job->call_nohalt(); - } - - return true; -} - -bool udd_ep_wait_stall_clear(udd_ep_id_t ep, udd_callback_halt_cleared_t callback) -{ - udd_ep_id_t ep_num; - udd_ep_job_t *ptr_job; - - ep_num = ep & USB_EP_ADDR_MASK; - if (USB_DEVICE_MAX_EP < ep_num) { - return false; - } - - ptr_job = udd_ep_get_job(ep); - if (ptr_job->busy == true) { - return false; /* Job already on going */ - } - - /* Wait clear halt endpoint */ - if (usb_device_endpoint_is_halted(&usb_device, ep)) { - /* Endpoint halted then registers the callback */ - ptr_job->busy = true; - ptr_job->call_nohalt = callback; - return true; - } else if (usb_device_endpoint_is_configured(&usb_device, ep)) { - callback(); /* Endpoint not halted then call directly callback */ - return true; - } else { - return false; - } -} - -/** - * \brief Control Endpoint stall sending data - */ -static void udd_ctrl_stall_data(void) -{ - udd_ep_control_state = UDD_EPCTRL_STALL_REQ; - - usb_device_endpoint_set_halt(&usb_device, USB_EP_DIR_IN); - usb_device_endpoint_clear_halt(&usb_device, USB_EP_DIR_OUT); -} - -bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket, uint8_t * buf, iram_size_t buf_size, udd_callback_trans_t callback) -{ - udd_ep_id_t ep_num; - udd_ep_job_t *ptr_job; - irqflags_t flags; - - ep_num = ep & USB_EP_ADDR_MASK; - - if ((USB_DEVICE_MAX_EP < ep_num) || (udd_ep_is_halted(ep))) { - return false; - } - - ptr_job = udd_ep_get_job(ep); - - flags = cpu_irq_save(); - if (ptr_job->busy == true) { - cpu_irq_restore(flags); - return false; /* Job already on going */ - } - ptr_job->busy = true; - cpu_irq_restore(flags); - - /* No job running, set up a new one */ - ptr_job->buf = buf; - ptr_job->buf_size = buf_size; - ptr_job->nb_trans = 0; - ptr_job->call_trans = callback; - ptr_job->b_shortpacket = b_shortpacket; - ptr_job->b_use_out_cache_buffer = false; - - /* Initialize value to simulate a empty transfer */ - uint16_t next_trans; - - if (ep & USB_EP_DIR_IN) { - if (0 != ptr_job->buf_size) { - next_trans = ptr_job->buf_size; - if (UDD_ENDPOINT_MAX_TRANS < next_trans) { - next_trans = UDD_ENDPOINT_MAX_TRANS - - (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size); - } - ptr_job->b_shortpacket = ptr_job->b_shortpacket && - (0 == (next_trans % ptr_job->ep_size)); - } else if (true == ptr_job->b_shortpacket) { - ptr_job->b_shortpacket = false; /* avoid to send zero length packet again */ - next_trans = 0; - } else { - ptr_job->busy = false; - if (NULL != ptr_job->call_trans) { - ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep); - } - return true; - } - return (STATUS_OK == - usb_device_endpoint_write_buffer_job(&usb_device, - ep_num,&ptr_job->buf[0],next_trans)); - } else { - if (0 != ptr_job->buf_size) { - next_trans = ptr_job->buf_size; - if (UDD_ENDPOINT_MAX_TRANS < next_trans) { - /* The USB hardware support a maximum transfer size - * of UDD_ENDPOINT_MAX_TRANS Bytes */ - next_trans = UDD_ENDPOINT_MAX_TRANS - - (UDD_ENDPOINT_MAX_TRANS % ptr_job->ep_size); - } else { - next_trans -= next_trans % ptr_job->ep_size; - } - if (next_trans < ptr_job->ep_size) { - ptr_job->b_use_out_cache_buffer = true; - return (STATUS_OK == - usb_device_endpoint_read_buffer_job(&usb_device, ep_num, - udd_ep_out_cache_buffer[ep_num - 1], - ptr_job->ep_size)); - } else { - return (STATUS_OK == - usb_device_endpoint_read_buffer_job(&usb_device, ep_num, - &ptr_job->buf[0],next_trans)); - } - } else { - ptr_job->busy = false; - if (NULL != ptr_job->call_trans) { - ptr_job->call_trans(UDD_EP_TRANSFER_OK, 0, ep); - } - return true; - } - } -} - -void udd_set_address(uint8_t address) -{ - usb_device_set_address(&usb_device,address); -} - -uint8_t udd_getaddress(void) -{ - return usb_device_get_address(&usb_device); -} - -void udd_send_remotewakeup(void) -{ - uint32_t try = 5; - udd_wait_clock_ready(); - udd_sleep_mode(UDD_STATE_IDLE); - while(2 != usb_get_state_machine_status(&usb_device) && try --) { - usb_device_send_remote_wake_up(&usb_device); - } -} - -void udd_set_setup_payload( uint8_t *payload, uint16_t payload_size ) -{ - udd_g_ctrlreq.payload = payload; - udd_g_ctrlreq.payload_size = payload_size; -} - -/** - * \brief Control Endpoint translate the data in buffer into Device Request Struct - */ -static void udd_ctrl_fetch_ram(void) -{ - udd_g_ctrlreq.req.bmRequestType = udd_ctrl_buffer[0]; - udd_g_ctrlreq.req.bRequest = udd_ctrl_buffer[1]; - udd_g_ctrlreq.req.wValue = ((uint16_t)(udd_ctrl_buffer[3]) << 8) + udd_ctrl_buffer[2]; - udd_g_ctrlreq.req.wIndex = ((uint16_t)(udd_ctrl_buffer[5]) << 8) + udd_ctrl_buffer[4]; - udd_g_ctrlreq.req.wLength = ((uint16_t)(udd_ctrl_buffer[7]) << 8) + udd_ctrl_buffer[6]; -} - -/** - * \brief Control Endpoint send out zero length packet - */ -static void udd_ctrl_send_zlp_in(void) -{ - udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP; - usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer); - usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload,0); -} - -/** - * \brief Process control endpoint IN transaction - */ -static void udd_ctrl_in_sent(void) -{ - static bool b_shortpacket = false; - uint16_t nb_remain; - - nb_remain = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans; - - if (0 == nb_remain) { - /* All content of current buffer payload are sent Update number of total data sending by previous payload buffer */ - udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans; - if ((udd_g_ctrlreq.req.wLength == udd_ctrl_prev_payload_nb_trans) || b_shortpacket) { - /* All data requested are transferred or a short packet has been sent, then it is the end of data phase. - * Generate an OUT ZLP for handshake phase */ - udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP; - usb_device_endpoint_setup_buffer_job(&usb_device,udd_ctrl_buffer); - return; - } - /* Need of new buffer because the data phase is not complete */ - if ((!udd_g_ctrlreq.over_under_run) || (!udd_g_ctrlreq.over_under_run())) { - /* Under run then send zlp on IN - * Here nb_remain=0, this allows to send a IN ZLP */ - } else { - /* A new payload buffer is given */ - udd_ctrl_payload_nb_trans = 0; - nb_remain = udd_g_ctrlreq.payload_size; - } - } - - /* Continue transfer and send next data */ - if (nb_remain >= USB_DEVICE_EP_CTRL_SIZE) { - nb_remain = USB_DEVICE_EP_CTRL_SIZE; - b_shortpacket = false; - } else { - b_shortpacket = true; - } - - /* Link payload buffer directly on USB hardware */ - usb_device_endpoint_write_buffer_job(&usb_device,0,udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans,nb_remain); - - udd_ctrl_payload_nb_trans += nb_remain; -} - -/** - * \brief Process control endpoint OUT transaction - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void udd_ctrl_out_received(void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - - uint16_t nb_data; - nb_data = ep_callback_para->received_bytes; /* Read data received during OUT phase */ - - if (udd_g_ctrlreq.payload_size < (udd_ctrl_payload_nb_trans + nb_data)) { - /* Payload buffer too small */ - nb_data = udd_g_ctrlreq.payload_size - udd_ctrl_payload_nb_trans; - } - - memcpy((uint8_t *) (udd_g_ctrlreq.payload + udd_ctrl_payload_nb_trans), udd_ctrl_buffer, nb_data); - udd_ctrl_payload_nb_trans += nb_data; - - if ((USB_DEVICE_EP_CTRL_SIZE != nb_data) || \ - (udd_g_ctrlreq.req.wLength <= (udd_ctrl_prev_payload_nb_trans + udd_ctrl_payload_nb_trans))) { - /* End of reception because it is a short packet - * or all data are transferred */ - - /* Before send ZLP, call intermediate callback - * in case of data receive generate a stall */ - udd_g_ctrlreq.payload_size = udd_ctrl_payload_nb_trans; - if (NULL != udd_g_ctrlreq.over_under_run) { - if (!udd_g_ctrlreq.over_under_run()) { - /* Stall ZLP */ - udd_ep_control_state = UDD_EPCTRL_STALL_REQ; - /* Stall all packets on IN & OUT control endpoint */ - udd_ep_set_halt(0); - /* Ack reception of OUT to replace NAK by a STALL */ - return; - } - } - /* Send IN ZLP to ACK setup request */ - udd_ctrl_send_zlp_in(); - return; - } - - if (udd_g_ctrlreq.payload_size == udd_ctrl_payload_nb_trans) { - /* Overrun then request a new payload buffer */ - if (!udd_g_ctrlreq.over_under_run) { - /* No callback available to request a new payload buffer - * Stall ZLP */ - udd_ep_control_state = UDD_EPCTRL_STALL_REQ; - /* Stall all packets on IN & OUT control endpoint */ - udd_ep_set_halt(0); - return; - } - if (!udd_g_ctrlreq.over_under_run()) { - /* No new payload buffer delivered - * Stall ZLP */ - udd_ep_control_state = UDD_EPCTRL_STALL_REQ; - /* Stall all packets on IN & OUT control endpoint */ - udd_ep_set_halt(0); - return; - } - /* New payload buffer available - * Update number of total data received */ - udd_ctrl_prev_payload_nb_trans += udd_ctrl_payload_nb_trans; - - /* Reinitialize reception on payload buffer */ - udd_ctrl_payload_nb_trans = 0; - } - usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE); -} - -/** - * \internal - * \brief Endpoint 0 (control) SETUP received callback - * \param[in] module_inst pointer to USB module instance - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void _usb_ep0_on_setup(struct usb_module *module_inst, void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - - if (UDD_EPCTRL_SETUP != udd_ep_control_state) { - if (NULL != udd_g_ctrlreq.callback) { - udd_g_ctrlreq.callback(); - } - udd_ep_control_state = UDD_EPCTRL_SETUP; - } - if ( 8 != ep_callback_para->received_bytes) { - udd_ctrl_stall_data(); - return; - } else { - udd_ctrl_fetch_ram(); - if (false == udc_process_setup()) { - udd_ctrl_stall_data(); - return; - } else if (Udd_setup_is_in()) { - udd_ctrl_prev_payload_nb_trans = 0; - udd_ctrl_payload_nb_trans = 0; - udd_ep_control_state = UDD_EPCTRL_DATA_IN; - usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE); - udd_ctrl_in_sent(); - } else { - if(0 == udd_g_ctrlreq.req.wLength) { - udd_ctrl_send_zlp_in(); - return; - } else { - udd_ctrl_prev_payload_nb_trans = 0; - udd_ctrl_payload_nb_trans = 0; - udd_ep_control_state = UDD_EPCTRL_DATA_OUT; - /* Initialize buffer size and enable OUT bank */ - usb_device_endpoint_read_buffer_job(&usb_device,0,udd_ctrl_buffer,USB_DEVICE_EP_CTRL_SIZE); - } - } - } -} - -/** - * \brief Control Endpoint Process when underflow condition has occurred - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void udd_ctrl_underflow(void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - - if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) { - /* Host want to stop OUT transaction - * then stop to wait OUT data phase and wait IN ZLP handshake */ - udd_ctrl_send_zlp_in(); - } else if (UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP == udd_ep_control_state) { - /* A OUT handshake is waiting by device, - * but host want extra IN data then stall extra IN data */ - usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address); - } -} - -/** - * \brief Control Endpoint Process when overflow condition has occurred - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void udd_ctrl_overflow(void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - - if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) { - /* Host want to stop IN transaction - * then stop to wait IN data phase and wait OUT ZLP handshake */ - udd_ep_control_state = UDD_EPCTRL_HANDSHAKE_WAIT_OUT_ZLP; - } else if (UDD_EPCTRL_HANDSHAKE_WAIT_IN_ZLP == udd_ep_control_state) { - /* A IN handshake is waiting by device, - * but host want extra OUT data then stall extra OUT data and following status stage */ - usb_device_endpoint_set_halt(&usb_device, ep_callback_para->endpoint_address); - } -} - -/** - * \internal - * \brief Control endpoint transfer fail callback function - * \param[in] module_inst Pointer to USB module instance - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void _usb_ep0_on_tansfer_fail(struct usb_module *module_inst, void* pointer) -{ - struct usb_endpoint_callback_parameter *ep_callback_para = (struct usb_endpoint_callback_parameter*)pointer; - - if(ep_callback_para->endpoint_address & USB_EP_DIR_IN) { - udd_ctrl_underflow(pointer); - } else { - udd_ctrl_overflow(pointer); - } -} - -/** - * \internal - * \brief Control endpoint transfer complete callback function - * \param[in] module_inst Pointer to USB module instance - * \param[in] pointer Pointer to the endpoint transfer status parameter struct from driver layer. - */ -static void _usb_ep0_on_tansfer_ok(struct usb_module *module_inst, void * pointer) -{ - if (UDD_EPCTRL_DATA_OUT == udd_ep_control_state) { /* handshake Out for status stage */ - udd_ctrl_out_received(pointer); - } else if (UDD_EPCTRL_DATA_IN == udd_ep_control_state) { /* handshake In for status stage */ - udd_ctrl_in_sent(); - } else { - if (NULL != udd_g_ctrlreq.callback) { - udd_g_ctrlreq.callback(); - } - udd_ep_control_state = UDD_EPCTRL_SETUP; - } -} - -/** - * \brief Enable Control Endpoint - * \param[in] module_inst Pointer to USB module instance - */ -static void udd_ctrl_ep_enable(struct usb_module *module_inst) -{ - /* USB Device Endpoint0 Configuration */ - struct usb_device_endpoint_config config_ep0; - - usb_device_endpoint_get_config_defaults(&config_ep0); - config_ep0.ep_size = (enum usb_endpoint_size)(32 - clz(((uint32_t)Min(Max(USB_DEVICE_EP_CTRL_SIZE, 8), 1024) << 1) - 1) - 1 - 3); - usb_device_endpoint_set_config(module_inst,&config_ep0); - - usb_device_endpoint_setup_buffer_job(module_inst,udd_ctrl_buffer); - - usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP, _usb_ep0_on_setup ); - usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT,_usb_ep0_on_tansfer_ok ); - usb_device_endpoint_register_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL,_usb_ep0_on_tansfer_fail ); - usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_RXSTP); - usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRCPT); - usb_device_endpoint_enable_callback(module_inst,0,USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL); - -#ifdef USB_DEVICE_LPM_SUPPORT - // Enable LPM feature - usb_device_set_lpm_mode(module_inst, USB_DEVICE_LPM_ACK); -#endif - - udd_ep_control_state = UDD_EPCTRL_SETUP; -} - -/** - * \internal - * \brief Control endpoint Suspend callback function - * \param[in] module_inst Pointer to USB module instance - * \param[in] pointer Pointer to the callback parameter from driver layer. - */ -static void _usb_on_suspend(struct usb_module *module_inst, void *pointer) -{ - usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP); - udd_sleep_mode(UDD_STATE_SUSPEND); -#ifdef UDC_SUSPEND_EVENT - UDC_SUSPEND_EVENT(); -#endif -} - -#ifdef USB_DEVICE_LPM_SUPPORT -static void _usb_device_lpm_suspend(struct usb_module *module_inst, void *pointer) -{ - dbg_print("LPM_SUSP\n"); - - uint32_t *lpm_wakeup_enable; - lpm_wakeup_enable = (uint32_t *)pointer; - - usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP); - usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP); - -//#warning Here the sleep mode must be choose to have a DFLL startup time < bmAttribut.HIRD - udd_sleep_mode(UDD_STATE_SUSPEND_LPM); // Enter in LPM SUSPEND mode - if ((*lpm_wakeup_enable)) { - UDC_REMOTEWAKEUP_LPM_ENABLE(); - } - if (!(*lpm_wakeup_enable)) { - UDC_REMOTEWAKEUP_LPM_DISABLE(); - } - UDC_SUSPEND_LPM_EVENT(); -} -#endif - -/** - * \internal - * \brief Control endpoint SOF callback function - * \param[in] module_inst Pointer to USB module instance - * \param[in] pointer Pointer to the callback parameter from driver layer. - */ -static void _usb_on_sof_notify(struct usb_module *module_inst, void *pointer) -{ - udc_sof_notify(); -#ifdef UDC_SOF_EVENT - UDC_SOF_EVENT(); -#endif -} - -/** - * \internal - * \brief Control endpoint Reset callback function - * \param[in] module_inst Pointer to USB module instance - * \param[in] pointer Pointer to the callback parameter from driver layer. - */ -static void _usb_on_bus_reset(struct usb_module *module_inst, void *pointer) -{ - // Reset USB Device Stack Core - udc_reset(); - usb_device_set_address(module_inst,0); - udd_ctrl_ep_enable(module_inst); -} - -/** - * \internal - * \brief Control endpoint Wakeup callback function - * \param[in] module_inst Pointer to USB module instance - * \param[in] pointer Pointer to the callback parameter from driver layer. - */ -static void _usb_on_wakeup(struct usb_module *module_inst, void *pointer) -{ - udd_wait_clock_ready(); - - usb_device_disable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND); -#ifdef USB_DEVICE_LPM_SUPPORT - usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP); -#endif - udd_sleep_mode(UDD_STATE_IDLE); -#ifdef UDC_RESUME_EVENT - UDC_RESUME_EVENT(); -#endif -} - -void udd_detach(void) -{ - usb_device_detach(&usb_device); - udd_sleep_mode(UDD_STATE_SUSPEND); -} - -void udd_attach(void) -{ - udd_sleep_mode(UDD_STATE_IDLE); - usb_device_attach(&usb_device); - - usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND, _usb_on_suspend); - usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_SOF, _usb_on_sof_notify); - usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_RESET, _usb_on_bus_reset); - usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP, _usb_on_wakeup); - - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SUSPEND); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_SOF); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_RESET); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_WAKEUP); -#ifdef USB_DEVICE_LPM_SUPPORT - usb_device_register_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP, _usb_device_lpm_suspend); - usb_device_enable_callback(&usb_device, USB_DEVICE_CALLBACK_LPMSUSP); -#endif -} - -#if USB_VBUS_EIC -/** - * \name USB VBUS PAD management - * - * @{ - */ - - /** Check if USB VBus is available */ -# define is_usb_vbus_high() port_pin_get_input_level(USB_VBUS_PIN) - -/** - * \internal - * \brief USB VBUS pin change handler - */ -static void _uhd_vbus_handler(void) -{ - extint_chan_disable_callback(USB_VBUS_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); -# ifndef USB_DEVICE_ATTACH_AUTO_DISABLE - if (is_usb_vbus_high()) { - udd_attach(); - } else { - udd_detach(); - } -# endif -# ifdef UDC_VBUS_EVENT - UDC_VBUS_EVENT(is_usb_vbus_high()); -# endif - extint_chan_enable_callback(USB_VBUS_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); -} - -/** - * \internal - * \brief USB VBUS pin configuration - */ -static void _usb_vbus_config(void) -{ - - /* Initialize EIC for vbus checking */ - struct extint_chan_conf eint_chan_conf; - extint_chan_get_config_defaults(&eint_chan_conf); - - eint_chan_conf.gpio_pin = USB_VBUS_PIN; - eint_chan_conf.gpio_pin_mux = USB_VBUS_EIC_MUX; - eint_chan_conf.gpio_pin_pull = EXTINT_PULL_NONE; - eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH; - eint_chan_conf.filter_input_signal = true; - - extint_chan_disable_callback(USB_VBUS_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); - extint_chan_set_config(USB_VBUS_EIC_LINE, &eint_chan_conf); - extint_register_callback(_uhd_vbus_handler, - USB_VBUS_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); - extint_chan_enable_callback(USB_VBUS_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); -} -/** @} */ -#endif - -bool udd_include_vbus_monitoring(void) -{ -#if USB_VBUS_EIC - return true; -#else - return false; -#endif -} - -void udd_enable(void) -{ - irqflags_t flags; - - /* To avoid USB interrupt before end of initialization */ - flags = cpu_irq_save(); - -#if USB_ID_EIC - if (usb_dual_enable()) { - /* The current mode has been started by otg_dual_enable() */ - cpu_irq_restore(flags); - return; - } -#endif - struct usb_config config_usb; - - /* USB Module configuration */ - usb_get_config_defaults(&config_usb); - config_usb.source_generator = UDD_CLOCK_GEN; - usb_init(&usb_device, USB, &config_usb); - - /* USB Module Enable */ - usb_enable(&usb_device); - - /* Check clock after enable module, request the clock */ - udd_wait_clock_ready(); - - udd_sleep_mode(UDD_STATE_SUSPEND); - -#if USB_VBUS_EIC - _usb_vbus_config(); - if (is_usb_vbus_high()) { - /* USB Attach */ - _uhd_vbus_handler(); - } -#else - // No VBus detect, assume always high -# ifndef USB_DEVICE_ATTACH_AUTO_DISABLE - udd_attach(); -# endif -#endif - - cpu_irq_restore(flags); -} - -void udd_disable(void) -{ - irqflags_t flags; - - udd_detach(); - - udd_sleep_mode(UDD_STATE_OFF); - - flags = cpu_irq_save(); - usb_dual_disable(); - cpu_irq_restore(flags); -} -/** @} */ diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_dual.c b/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_dual.c deleted file mode 100644 index 4b9adee94adcf..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_dual.c +++ /dev/null @@ -1,178 +0,0 @@ -/** - * \file - * - * \brief SAM USB Dual Role driver file. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include "usb_dual.h" - -#ifndef UDD_ENABLE -# define udc_start() -# define udc_stop() -#else -#include -#endif - -#ifndef UHD_ENABLE -# define uhc_start(void) -# define uhc_stop(b_id_stop) -#else -#include -#endif - -/* State of USB dual role initialization */ -static bool _initialized = false; - -#define _usb_is_id_device() port_pin_get_input_level(USB_ID_PIN) - -#if USB_ID_EIC -static void usb_id_handler(void); - -/** - * \name USB ID PAD management - * - * @{ - */ - -/** - * USB ID pin configuration - */ -static void usb_id_config(void) -{ - struct extint_chan_conf eint_chan_conf; - extint_chan_get_config_defaults(&eint_chan_conf); - - eint_chan_conf.gpio_pin = USB_ID_PIN; - eint_chan_conf.gpio_pin_mux = USB_ID_EIC_MUX; - eint_chan_conf.detection_criteria = EXTINT_DETECT_BOTH; - eint_chan_conf.filter_input_signal = true; - - extint_chan_disable_callback(USB_ID_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); - extint_chan_set_config(USB_ID_EIC_LINE, &eint_chan_conf); - extint_register_callback(usb_id_handler, - USB_ID_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); - extint_chan_enable_callback(USB_ID_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); -} - -/** - * USB ID pin change handler - */ -static void usb_id_handler(void) -{ - extint_chan_disable_callback(USB_ID_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); - if (_usb_is_id_device()) { - uhc_stop(false); - UHC_MODE_CHANGE(false); - udc_start(); - } else { - udc_stop(); - UHC_MODE_CHANGE(true); - uhc_start(); - } - extint_chan_enable_callback(USB_ID_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); -} -#endif -/** @} */ - -/** - * \brief Initialize the USB peripheral and set right role according to ID pin - * - * \return \c true if the ID pin management has been started, otherwise \c false. - */ -bool usb_dual_enable(void) -{ - if (_initialized) { - return false; // Dual role already initialized - } - -#if USB_ID_EIC - _initialized = true; - - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - /* Set USB ID Pin as inputs */ - pin_conf.direction = PORT_PIN_DIR_INPUT; - pin_conf.input_pull = PORT_PIN_PULL_UP; - port_pin_set_config(USB_ID_PIN, &pin_conf); - - usb_id_config(); - if (_usb_is_id_device()) { - UHC_MODE_CHANGE(false); - udc_start(); - } else { - UHC_MODE_CHANGE(true); - uhc_start(); - } - - /** - * End of host or device startup, - * the current mode selected is already started now - */ - return true; // ID pin management has been enabled -#else - return false; // ID pin management has not been enabled -#endif -} - -/** - * \brief Deinitialize the dual role driver - */ -void usb_dual_disable(void) -{ - if (!_initialized) { - return; // Dual role not initialized - } - _initialized = false; - -#if USB_ID_EIC - extint_chan_disable_callback(USB_ID_EIC_LINE, - EXTINT_CALLBACK_TYPE_DETECT); -#endif -} - diff --git a/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_dual.h b/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_dual.h deleted file mode 100644 index 60125d3d6f40c..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/stack_interface/usb_dual.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * \brief SAM USB Dual Role driver header file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_DUAL_H_ -#define _USB_DUAL_H_ - -#include "compiler.h" -#include "preprocessor.h" - -/* Get USB pads pins configuration in board configuration */ -#include "conf_board.h" -#include "board.h" -#include "extint.h" -#include "port.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup usb_group - * \defgroup usb_dual_group USB dual role driver - * USB low-level driver for dual role features - * - * @{ - */ - -bool usb_dual_enable(void); -void usb_dual_disable(void); - -/** - * @name USB ID pin management - * - * The ID pin come from the USB connector (A and B receptable) and - * allows to select the USB mode between host or device. - * The ID pin can be managed through EIC pin. - * This feature is optional, and it is enabled if USB_ID_PIN - * is defined in board.h and CONF_BOARD_USB_ID_DETECT defined in - * conf_board.h. -* -* @{ -*/ -#define USB_ID_DETECT (defined(CONF_BOARD_USB_ID_DETECT)) -#define USB_ID_EIC (defined(USB_ID_PIN) && USB_ID_DETECT) -/** @} */ - -/** - * @name USB Vbus management - * - * The VBus line can be monitored through a EIC pin and - * a basic resistor voltage divider. - * This feature is optional, and it is enabled if USB_VBUS_PIN - * is defined in board.h and CONF_BOARD_USB_VBUS_DETECT defined in - * conf_board.h. - * - * @{ - */ -#define USB_VBUS_DETECT (defined(CONF_BOARD_USB_VBUS_DETECT)) -#define USB_VBUS_EIC (defined(USB_VBUS_PIN) && USB_VBUS_DETECT) -/** @} */ - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // _USB_DUAL_H_ diff --git a/atmel-samd/asf/sam0/drivers/usb/usb.h b/atmel-samd/asf/sam0/drivers/usb/usb.h deleted file mode 100644 index fa29b1ffed0cb..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/usb.h +++ /dev/null @@ -1,833 +0,0 @@ -/** - * \file - * - * \brief SAM USB Driver - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef USB_H_INCLUDED -#define USB_H_INCLUDED - -#include -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup asfdoc_sam0_usb_group SAM Universal Serial Bus (USB) - * - * The Universal Serial Bus (USB) module complies with the USB 2.1 specification. - * - * The following peripherals are used by this module: - * - USB (Universal Serial Bus) - * - * The following devices can use this module: - * - Atmel | SMART SAM D21 - * - Atmel | SMART SAM R21 - * - Atmel | SMART SAM D11 (Only USB device support on SAM D11 device) - * - Atmel | SMART SAM L21 - * - Atmel | SMART SAM L22 (Only USB device support on SAM L22 device) - * - Atmel | SMART SAM DA1 - * - * The USB module covers following mode: - * \if USB_DEVICE_MODE - * - USB Device Mode - * \endif - * \if USB_HOST_MODE - * - USB Host Mode - * \endif - * - * The USB module covers following speed: - * \if USB_HS_MODE - * - USB High Speed (480Mbit/s) - * \endif - * - USB Full Speed (12Mbit/s) - * \if USB_LS_MODE - * - USB Low Speed (1.5Mbit/s) - * \endif - * - * \if USB_LPM_MODE - * The USB module supports Link Power Management (LPM-L1) protocol. - * \endif - * - * USB support needs whole set of enumeration process, to make the device - * recognizable and usable. The USB driver is designed to interface to the - * USB Stack in Atmel Software Framework (ASF). - * - * \if USB_DEVICE_MODE - * \section asfdoc_sam0_usb_device USB Device Mode - * The ASF USB Device Stack has defined the USB Device Driver (UDD) interface, - * to support USB device operations. The USB module device driver complies with - * this interface, so that the USB Device Stack can work based on the - * USB module. - * - * Refer to - * "ASF - USB Device Stack" for more details. - * \endif - * - * \if USB_HOST_MODE - * \section adfdoc_sam0_usb_host USB Host Mode - * The ASF USB Host Stack has defined the USB Host Driver (UHD) interface, - * to support USB host operations. The USB module host driver complies with - * this interface, so that the USB Host Stack can work based on the USB module. - * - * Refer to - * "ASF - USB Host Stack" for more details. - * \endif - */ - -/** Enum for the speed status for the USB module */ -enum usb_speed { - USB_SPEED_LOW, - USB_SPEED_FULL, -}; - -/** Enum for the possible callback types for the USB in host module */ -enum usb_host_callback { - USB_HOST_CALLBACK_SOF, - USB_HOST_CALLBACK_RESET, - USB_HOST_CALLBACK_WAKEUP, - USB_HOST_CALLBACK_DNRSM, - USB_HOST_CALLBACK_UPRSM, - USB_HOST_CALLBACK_RAMACER, - USB_HOST_CALLBACK_CONNECT, - USB_HOST_CALLBACK_DISCONNECT, - USB_HOST_CALLBACK_N, -}; - -/** Enum for the possible callback types for the USB pipe in host module */ -enum usb_host_pipe_callback { - USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE, - USB_HOST_PIPE_CALLBACK_ERROR, - USB_HOST_PIPE_CALLBACK_SETUP, - USB_HOST_PIPE_CALLBACK_STALL, - USB_HOST_PIPE_CALLBACK_N, -}; - -/** - * \brief Host pipe types. - */ -enum usb_host_pipe_type { - USB_HOST_PIPE_TYPE_DISABLE, - USB_HOST_PIPE_TYPE_CONTROL, - USB_HOST_PIPE_TYPE_ISO, - USB_HOST_PIPE_TYPE_BULK, - USB_HOST_PIPE_TYPE_INTERRUPT, - USB_HOST_PIPE_TYPE_EXTENDED, -}; - -/** - * \brief Host pipe token types. - */ -enum usb_host_pipe_token { - USB_HOST_PIPE_TOKEN_SETUP, - USB_HOST_PIPE_TOKEN_IN, - USB_HOST_PIPE_TOKEN_OUT, -}; - -/** - * \brief Enumeration for the possible callback types for the USB in device module - */ -enum usb_device_callback { - USB_DEVICE_CALLBACK_SOF, - USB_DEVICE_CALLBACK_RESET, - USB_DEVICE_CALLBACK_WAKEUP, - USB_DEVICE_CALLBACK_RAMACER, - USB_DEVICE_CALLBACK_SUSPEND, - USB_DEVICE_CALLBACK_LPMNYET, - USB_DEVICE_CALLBACK_LPMSUSP, - USB_DEVICE_CALLBACK_N, -}; - -/** - * \brief Enumeration for the possible callback types for the USB endpoint in device module - */ -enum usb_device_endpoint_callback { - USB_DEVICE_ENDPOINT_CALLBACK_TRCPT, - USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL, - USB_DEVICE_ENDPOINT_CALLBACK_RXSTP, - USB_DEVICE_ENDPOINT_CALLBACK_STALL, - USB_DEVICE_EP_CALLBACK_N, -}; - -/** - * \brief Device Endpoint types. - */ -enum usb_device_endpoint_type { - USB_DEVICE_ENDPOINT_TYPE_DISABLE, - USB_DEVICE_ENDPOINT_TYPE_CONTROL, - USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS, - USB_DEVICE_ENDPOINT_TYPE_BULK, - USB_DEVICE_ENDPOINT_TYPE_INTERRUPT, -}; - -/** - * \brief Endpoint Size - */ -enum usb_endpoint_size { - USB_ENDPOINT_8_BYTE, - USB_ENDPOINT_16_BYTE, - USB_ENDPOINT_32_BYTE, - USB_ENDPOINT_64_BYTE, - USB_ENDPOINT_128_BYTE, - USB_ENDPOINT_256_BYTE, - USB_ENDPOINT_512_BYTE, - USB_ENDPOINT_1023_BYTE, -}; - -/** - * \brief Link Power Management Handshake. - */ -enum usb_device_lpm_mode { - USB_DEVICE_LPM_NOT_SUPPORT, - USB_DEVICE_LPM_ACK, - USB_DEVICE_LPM_NYET, -}; - -/** - * \brief Module structure - */ -struct usb_module; - -/** - * \name Host Callback Functions Types - * @{ - */ -typedef void (*usb_host_callback_t)(struct usb_module *module_inst); -typedef void (*usb_host_pipe_callback_t)(struct usb_module *module_inst, void *); -/** @} */ - -/** - * \name Device Callback Functions Types - * @{ - */ -typedef void (*usb_device_callback_t)(struct usb_module *module_inst, void* pointer); -typedef void (*usb_device_endpoint_callback_t)(struct usb_module *module_inst, void* pointer); -/** @} */ - - -/** USB configurations */ -struct usb_config { - /** \c true for host, \c false for device. */ - bool select_host_mode; - /** When \c true the module is enabled during standby. */ - bool run_in_standby; - /** Generic Clock Generator source channel. */ - enum gclk_generator source_generator; - /** Speed mode */ - enum usb_speed speed_mode; -}; - -/** - * \brief USB software module instance structure. - * - * USB software module instance structure, used to retain software state - * information of an associated hardware module instance. - * - */ -struct usb_module { - /** Hardware module pointer of the associated USB peripheral. */ - Usb *hw; - -#if !SAMD11 && !SAML22 - /** Array to store host related callback functions */ - usb_host_callback_t host_callback[USB_HOST_CALLBACK_N]; - usb_host_pipe_callback_t host_pipe_callback[USB_PIPE_NUM][USB_HOST_PIPE_CALLBACK_N]; - /** Bit mask for host callbacks registered */ - uint8_t host_registered_callback_mask; - /** Bit mask for host callbacks enabled */ - uint8_t host_enabled_callback_mask; - /** Bit mask for host pipe callbacks registered */ - uint8_t host_pipe_registered_callback_mask[USB_PIPE_NUM]; - /** Bit mask for host pipe callbacks enabled */ - uint8_t host_pipe_enabled_callback_mask[USB_PIPE_NUM]; -#endif - - /** Array to store device related callback functions */ - usb_device_callback_t device_callback[USB_DEVICE_CALLBACK_N]; - usb_device_endpoint_callback_t device_endpoint_callback[USB_EPT_NUM][USB_DEVICE_EP_CALLBACK_N]; - /** Bit mask for device callbacks registered */ - uint16_t device_registered_callback_mask; - /** Bit mask for device callbacks enabled */ - uint16_t device_enabled_callback_mask; - /** Bit mask for device endpoint callbacks registered */ - uint8_t device_endpoint_registered_callback_mask[USB_EPT_NUM]; - /** Bit mask for device endpoint callbacks enabled */ - uint8_t device_endpoint_enabled_callback_mask[USB_EPT_NUM]; -}; - -/** USB host pipe configurations */ -struct usb_host_pipe_config { - /** device address */ - uint8_t device_address; - /** endpoint address */ - uint8_t endpoint_address; - /** Pipe type */ - enum usb_host_pipe_type pipe_type; - /** interval */ - uint8_t binterval; - /** pipe size */ - uint16_t size; -}; - -/** USB device endpoint configurations */ -struct usb_device_endpoint_config { - /** device address */ - uint8_t ep_address; - /** endpoint size */ - enum usb_endpoint_size ep_size; - /** automatic zero length packet mode, \c true to enable */ - bool auto_zlp; - /** type of endpoint with Bank */ - enum usb_device_endpoint_type ep_type; -}; - -/** USB host pipe callback status parameter structure */ -struct usb_pipe_callback_parameter { - /** current pipe number */ - uint8_t pipe_num; - /** pipe error status */ - uint8_t pipe_error_status; - /** actual transferred data size */ - uint16_t transfered_size; - /** required data size */ - uint16_t required_size; -}; - -/** USB device endpoint callback status parameter structure */ -struct usb_endpoint_callback_parameter { - uint16_t received_bytes; - uint16_t sent_bytes; - uint16_t out_buffer_size; - uint8_t endpoint_address; -}; - -void usb_enable(struct usb_module *module_inst); -void usb_disable(struct usb_module *module_inst); - -/** - * \brief Get the status of USB module's state machine - * - * \param module_inst Pointer to USB module instance - */ -static inline uint8_t usb_get_state_machine_status(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return module_inst->hw->DEVICE.FSMSTATUS.reg; -} - -void usb_get_config_defaults(struct usb_config *module_config); -enum status_code usb_init(struct usb_module *module_inst, Usb *const hw, - struct usb_config *module_config); - -#if !SAMD11 && !SAML22 -/** - * \brief Enable the USB host by setting the VBUS OK - * - * \param module_inst Pointer to USB software instance struct - */ -static inline void usb_host_enable(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.CTRLB.bit.VBUSOK = 1; -} - -/** - * \brief Send the USB reset - * - * \param module_inst Pointer to USB software instance struct - */ -static inline void usb_host_send_reset(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.CTRLB.bit.BUSRESET = 1; -} - -/** - * \brief Enable the USB SOF generation - * - * \param module_inst Pointer to USB software instance struct - */ -static inline void usb_host_enable_sof(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.CTRLB.bit.SOFE = 1; -} - -/** - * \brief Disable the USB SOF generation - * - * \param module_inst Pointer to USB software instance struct - */ -static inline void usb_host_disable_sof(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.CTRLB.bit.SOFE = 0; -} - -/** - * \brief Check the USB SOF generation status - * - * \param module_inst Pointer to USB software instance struct - * - * \return USB SOF generation status, \c true if SOF generation is ON. - */ -static inline bool usb_host_is_sof_enabled(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return module_inst->hw->HOST.CTRLB.bit.SOFE; -} - -/** - * \brief Send the USB host resume - * - * \param module_inst Pointer to USB software instance struct - */ -static inline void usb_host_send_resume(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.CTRLB.bit.RESUME= 1; -} - -/** - * \brief Send the USB host LPM resume - * - * \param module_inst Pointer to USB software instance struct - */ -static inline void usb_host_send_l1_resume(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.CTRLB.bit.L1RESUME = 1; -} - -/** - * \brief Get the speed mode of USB host - * - * \param module_inst Pointer to USB module instance struct - * - * \return USB speed mode (\ref usb_speed). - */ -static inline enum usb_speed usb_host_get_speed(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - if (module_inst->hw->HOST.STATUS.bit.SPEED == 0) { - return USB_SPEED_FULL; - } else { - return USB_SPEED_LOW; - } -} - -/** - * \brief Get the frame number - * - * \param module_inst Pointer to USB software instance struct - * - * \return frame number value. - */ -static inline uint16_t usb_host_get_frame_number(struct usb_module *module_inst) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return (uint16_t)(module_inst->hw->HOST.FNUM.bit.FNUM); -} -#endif - -/** - * \brief Attach USB device to the bus - * - * \param module_inst Pointer to USB device module instance - */ -static inline void usb_device_attach(struct usb_module *module_inst) -{ - module_inst->hw->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; -} - -/** - * \brief Detach USB device from the bus - * - * \param module_inst Pointer to USB device module instance - */ -static inline void usb_device_detach(struct usb_module *module_inst) -{ - module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; -} - -/** - * \brief Get the speed mode of USB device - * - * \param module_inst Pointer to USB device module instance - * \return USB Speed mode (\ref usb_speed). - */ -static inline enum usb_speed usb_device_get_speed(struct usb_module *module_inst) -{ - if (!(module_inst->hw->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk)) { - return USB_SPEED_FULL; - } else { - return USB_SPEED_LOW; - } -} - -/** - * \brief Get the address of USB device - * - * \param module_inst Pointer to USB device module instance - * \return USB device address value. - */ -static inline uint8_t usb_device_get_address(struct usb_module *module_inst) -{ - return ((uint8_t)(module_inst->hw->DEVICE.DADD.bit.DADD)); -} - -/** - * \brief Set the speed mode of USB device - * - * \param module_inst Pointer to USB device module instance - * \param address USB device address value - */ -static inline void usb_device_set_address(struct usb_module *module_inst, uint8_t address) -{ - module_inst->hw->DEVICE.DADD.reg = USB_DEVICE_DADD_ADDEN | address; -} - -/** - * \brief Get the frame number of USB device - * - * \param module_inst Pointer to USB device module instance - * \return USB device frame number value. - */ -static inline uint16_t usb_device_get_frame_number(struct usb_module *module_inst) -{ - return ((uint16_t)(module_inst->hw->DEVICE.FNUM.bit.FNUM)); -} - -/** - * \brief Get the micro-frame number of USB device - * - * \param module_inst Pointer to USB device module instance - * \return USB device micro-frame number value. - */ -static inline uint16_t usb_device_get_micro_frame_number(struct usb_module *module_inst) -{ - return ((uint16_t)(module_inst->hw->DEVICE.FNUM.reg)); -} - -/** - * \brief USB device send the resume wakeup - * - * \param module_inst Pointer to USB device module instance - */ -static inline void usb_device_send_remote_wake_up(struct usb_module *module_inst) -{ - module_inst->hw->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; -} - -/** - * \brief USB device set the LPM mode - * - * \param module_inst Pointer to USB device module instance - * \param lpm_mode LPM mode - */ -static inline void usb_device_set_lpm_mode(struct usb_module *module_inst, - enum usb_device_lpm_mode lpm_mode) -{ - module_inst->hw->DEVICE.CTRLB.bit.LPMHDSK = lpm_mode; -} - -/** - * \name USB Host Callback Management - * @{ - */ -enum status_code usb_host_register_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type, - usb_host_callback_t callback_func); -enum status_code usb_host_unregister_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type); -enum status_code usb_host_enable_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type); -enum status_code usb_host_disable_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type); -/** @} */ - -/** - * \name USB Device Callback Management - * @{ - */ -enum status_code usb_device_register_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type, - usb_device_callback_t callback_func); -enum status_code usb_device_unregister_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type); -enum status_code usb_device_enable_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type); -enum status_code usb_device_disable_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type); -/** @} */ - -/** - * \name USB Host Pipe Configuration - * @{ - */ -void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config); -enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num, - struct usb_host_pipe_config *ep_config); -enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num, - struct usb_host_pipe_config *ep_config); -/** @} */ - -/** - * \name USB Device Endpoint Configuration - * @{ - */ -void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config); -enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst, - struct usb_device_endpoint_config *ep_config); -bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep); -/** @} */ - -/** - * \name USB Host Pipe Callback Management - * @{ - */ -enum status_code usb_host_pipe_register_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type, - usb_host_pipe_callback_t callback_func); -enum status_code usb_host_pipe_unregister_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type); -enum status_code usb_host_pipe_enable_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type); -enum status_code usb_host_pipe_disable_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type); -/** @} */ - -/** - * \name USB Device Endpoint Callback Management - * @{ - */ -enum status_code usb_device_endpoint_register_callback( - struct usb_module *module_inst, uint8_t ep_num, - enum usb_device_endpoint_callback callback_type, - usb_device_endpoint_callback_t callback_func); -enum status_code usb_device_endpoint_unregister_callback( - struct usb_module *module_inst, uint8_t ep_num, - enum usb_device_endpoint_callback callback_type); -enum status_code usb_device_endpoint_enable_callback( - struct usb_module *module_inst, uint8_t ep, - enum usb_device_endpoint_callback callback_type); -enum status_code usb_device_endpoint_disable_callback( - struct usb_module *module_inst, uint8_t ep, - enum usb_device_endpoint_callback callback_type); -/** @} */ - -/** - * \name USB Host Pipe Job Management - * @{ - */ -enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst, - uint8_t pipe_num, uint8_t *buf); -enum status_code usb_host_pipe_read_job(struct usb_module *module_inst, - uint8_t pipe_num, uint8_t *buf, uint32_t buf_size); -enum status_code usb_host_pipe_write_job(struct usb_module *module_inst, - uint8_t pipe_num, uint8_t *buf, uint32_t buf_size); -enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num); -enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst, - uint8_t pipe_num, bool b_remotewakeup, uint8_t hird); -/** @} */ - -/** - * \name USB Device Endpoint Job Management - * @{ - */ -enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num, - uint8_t* pbuf, uint32_t buf_size); -enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num, - uint8_t* pbuf, uint32_t buf_size); -enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst, - uint8_t* pbuf); -void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep); -/** @} */ - -#if !SAMD11 && !SAML22 -/** - * \name USB Host Pipe Operations - * @{ - */ - -/** - * \brief Freeze a pipe - * - * \param module_inst Pointer to USB module instance - * \param pipe_num Pipe number - */ -static inline void usb_host_pipe_freeze(struct usb_module *module_inst, uint8_t pipe_num) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE; -} - -/** - * \brief Unfreeze a pipe - * - * \param module_inst Pointer to USB module instance - * \param pipe_num Pipe number - */ -static inline void usb_host_pipe_unfreeze(struct usb_module *module_inst, uint8_t pipe_num) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_PFREEZE; -} - -/** - * \brief Check if the pipe is frozen - * - * \param module_inst Pointer to USB module instance - * \param pipe_num Pipe number - */ -static inline bool usb_host_pipe_is_frozen(struct usb_module *module_inst, uint8_t pipe_num) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - return (module_inst->hw->HOST.HostPipe[pipe_num].PSTATUS.bit.PFREEZE == 1); -} - -/** - * \brief Set the data toggle bit of pipe - * - * \param module_inst Pointer to USB module instance - * \param pipe_num Pipe number - */ -static inline void usb_host_pipe_set_toggle(struct usb_module *module_inst, uint8_t pipe_num) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_DTGL; -} - -/** - * \brief Clear the data toggle bit of pipe - * - * \param module_inst Pointer to USB module instance - * \param pipe_num Pipe number - */ -static inline void usb_host_pipe_clear_toggle(struct usb_module *module_inst, uint8_t pipe_num) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_DTGL; -} - -/** - * \brief Set the auto zero length packet of pipe - * - * \param module_inst Pointer to USB module instance - * \param pipe_num Pipe number - * \param value \c true to enable auto ZLP and \c false to disable - */ -void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value); - -/** @} */ -#endif - -/** - * \name USB Device Endpoint Operations - * @{ - */ - -bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep); -void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep); -void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* USB_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/drivers/usb/usb_sam_d_r/usb.c b/atmel-samd/asf/sam0/drivers/usb/usb_sam_d_r/usb.c deleted file mode 100644 index a6fe3420d77b3..0000000000000 --- a/atmel-samd/asf/sam0/drivers/usb/usb_sam_d_r/usb.c +++ /dev/null @@ -1,2041 +0,0 @@ -/** - * \file - * - * \brief SAM USB Driver. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include -#include "usb.h" - -/** Fields definition from a LPM TOKEN */ -#define USB_LPM_ATTRIBUT_BLINKSTATE_MASK (0xF << 0) -#define USB_LPM_ATTRIBUT_HIRD_MASK (0xF << 4) -#define USB_LPM_ATTRIBUT_REMOTEWAKE_MASK (1 << 8) -#define USB_LPM_ATTRIBUT_BLINKSTATE(value) ((value & 0xF) << 0) -#define USB_LPM_ATTRIBUT_HIRD(value) ((value & 0xF) << 4) -#define USB_LPM_ATTRIBUT_REMOTEWAKE(value) ((value & 1) << 8) -#define USB_LPM_ATTRIBUT_BLINKSTATE_L1 USB_LPM_ATTRIBUT_BLINKSTATE(1) - -/** - * \brief Mask selecting the index part of an endpoint address - */ -#define USB_EP_ADDR_MASK 0x0f - -/** - * \brief Endpoint transfer direction is IN - */ -#define USB_EP_DIR_IN 0x80 - -/** - * \brief Endpoint transfer direction is OUT - */ -#define USB_EP_DIR_OUT 0x00 - -/** - * \name USB SRAM data containing pipe descriptor table - * The content of the USB SRAM can be : - * - modified by USB hardware interface to update pipe status. - * Thereby, it is read by software. - * - modified by USB software to control pipe. - * Thereby, it is read by hardware. - * This data section is volatile. - * - * @{ - */ -COMPILER_PACK_SET(1) -COMPILER_WORD_ALIGNED -union { - UsbDeviceDescriptor usb_endpoint_table[USB_EPT_NUM]; -#if !SAMD11 - UsbHostDescriptor usb_pipe_table[USB_PIPE_NUM]; -#endif -} usb_descriptor_table; -COMPILER_PACK_RESET() -/** @} */ - -/** - * \brief Local USB module instance - */ -static struct usb_module *_usb_instances; - -#if !SAMD11 -/** - * \brief Host pipe callback structure variable - */ -static struct usb_pipe_callback_parameter pipe_callback_para; -#endif - -/* Device LPM callback variable */ -static uint32_t device_callback_lpm_wakeup_enable; - -/** - * \brief Device endpoint callback parameter variable, used to transfer info to UDD wrapper layer - */ -static struct usb_endpoint_callback_parameter ep_callback_para; - -/** - * \internal USB Device IRQ Mask Bits Map - */ -static const uint16_t _usb_device_irq_bits[USB_DEVICE_CALLBACK_N] = { - USB_DEVICE_INTFLAG_SOF, - USB_DEVICE_INTFLAG_EORST, - USB_DEVICE_INTFLAG_WAKEUP | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_UPRSM, - USB_DEVICE_INTFLAG_RAMACER, - USB_DEVICE_INTFLAG_SUSPEND, - USB_DEVICE_INTFLAG_LPMNYET, - USB_DEVICE_INTFLAG_LPMSUSP, -}; - -/** - * \internal USB Device IRQ Mask Bits Map - */ -static const uint8_t _usb_endpoint_irq_bits[USB_DEVICE_EP_CALLBACK_N] = { - USB_DEVICE_EPINTFLAG_TRCPT_Msk, - USB_DEVICE_EPINTFLAG_TRFAIL_Msk, - USB_DEVICE_EPINTFLAG_RXSTP, - USB_DEVICE_EPINTFLAG_STALL_Msk -}; - -#if !SAMD11 -/** - * \brief Bit mask for pipe job busy status - */ -uint32_t host_pipe_job_busy_status = 0; - -/** - * \brief Registers a USB host callback - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref usb_host_enable_callback, - * in order for the interrupt handler to call it when the conditions for the - * callback type is met. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * \param[in] callback_func Pointer to callback function - * - * \return Status of the registration operation. - * \retval STATUS_OK The callback was registered successfully. - */ -enum status_code usb_host_register_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type, - usb_host_callback_t callback_func) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(callback_func); - - /* Register callback function */ - module_inst->host_callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module_inst->host_registered_callback_mask |= (1 << callback_type); - - return STATUS_OK; -} - -/** - * \brief Unregisters a USB host callback - * - * Unregisters an asynchronous callback implemented by the user. Removing it - * from the internal callback registration table. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the de-registration operation. - * \retval STATUS_OK The callback was unregistered successfully. - */ -enum status_code usb_host_unregister_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - - /* Unregister callback function */ - module_inst->host_callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module_inst->host_registered_callback_mask &= ~(1 << callback_type); - - return STATUS_OK; -} - -/** - * \brief Enables USB host callback generation for a given type. - * - * Enables asynchronous callbacks for a given logical type. - * This must be called before USB host generate callback events. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback enable operation. - * \retval STATUS_OK The callback was enabled successfully. - */ -enum status_code usb_host_enable_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Enable callback */ - module_inst->host_enabled_callback_mask |= (1 << callback_type); - - if (callback_type == USB_HOST_CALLBACK_SOF) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; - } - if (callback_type == USB_HOST_CALLBACK_RESET) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; - } - if (callback_type == USB_HOST_CALLBACK_WAKEUP) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; - } - if (callback_type == USB_HOST_CALLBACK_DNRSM) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; - } - if (callback_type == USB_HOST_CALLBACK_UPRSM) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; - } - if (callback_type == USB_HOST_CALLBACK_RAMACER) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; - } - if (callback_type == USB_HOST_CALLBACK_CONNECT) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; - } - if (callback_type == USB_HOST_CALLBACK_DISCONNECT) { - module_inst->hw->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; - } - - return STATUS_OK; -} - -/** - * \brief Disables USB host callback generation for a given type. - * - * Disables asynchronous callbacks for a given logical type. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback disable operation. - * \retval STATUS_OK The callback was disabled successfully. - */ -enum status_code usb_host_disable_callback(struct usb_module *module_inst, - enum usb_host_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Disable callback */ - module_inst->host_enabled_callback_mask &= ~(1 << callback_type); - - if (callback_type == USB_HOST_CALLBACK_SOF) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_HSOF; - } - if (callback_type == USB_HOST_CALLBACK_RESET) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RST; - } - if (callback_type == USB_HOST_CALLBACK_WAKEUP) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_WAKEUP; - } - if (callback_type == USB_HOST_CALLBACK_DNRSM) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DNRSM; - } - if (callback_type == USB_HOST_CALLBACK_UPRSM) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_UPRSM; - } - if (callback_type == USB_HOST_CALLBACK_RAMACER) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_RAMACER; - } - if (callback_type == USB_HOST_CALLBACK_CONNECT) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DCONN; - } - if (callback_type == USB_HOST_CALLBACK_DISCONNECT) { - module_inst->hw->HOST.INTENCLR.reg = USB_HOST_INTENCLR_DDISC; - } - - return STATUS_OK; -} - -/** - * \brief Initializes an USB host pipe configuration structure to defaults. - * - * Initializes a given USB host pipe configuration structure to a - * set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li device address is 0 - * \li endpoint address is 0 - * \li pipe type is control - * \li interval is 0 - * \li pipe size is 8 - * - * \param[out] ep_config Configuration structure to initialize to default values - */ -void usb_host_pipe_get_config_defaults(struct usb_host_pipe_config *ep_config) -{ - /* Sanity check arguments */ - Assert(ep_config); - /* Write default config to config struct */ - ep_config->device_address = 0; - ep_config->endpoint_address = 0; - ep_config->pipe_type = USB_HOST_PIPE_TYPE_CONTROL; - ep_config->binterval = 0; - ep_config->size = 8; -} - -/** - * \brief Writes an USB host pipe configuration to the hardware module. - * - * Writes out a given configuration of an USB host pipe - * configuration to the hardware module. If the pipe is already configured, - * the new configuration will replace the existing one. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] ep_config Configuration settings for the pipe - * - * \return Status of the host pipe configuration operation. - * \retval STATUS_OK The host pipe was configured successfully. - */ -enum status_code usb_host_pipe_set_config(struct usb_module *module_inst, uint8_t pipe_num, - struct usb_host_pipe_config *ep_config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - Assert(ep_config); - - /* set pipe config */ - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.BK = 0; - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = ep_config->pipe_type; - module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg = - ep_config->binterval; - if (ep_config->endpoint_address == 0) { - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN = - USB_HOST_PIPE_TOKEN_SETUP; - } else if (ep_config->endpoint_address & USB_EP_DIR_IN) { - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN = - USB_HOST_PIPE_TOKEN_IN; - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = - USB_HOST_PSTATUSSET_BK0RDY; - } else { - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN = - USB_HOST_PIPE_TOKEN_OUT; - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = - USB_HOST_PSTATUSCLR_BK0RDY; - } - - memset((uint8_t *)&usb_descriptor_table.usb_pipe_table[pipe_num], 0, - sizeof(usb_descriptor_table.usb_pipe_table[0])); - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR = - ep_config->device_address; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM = - ep_config->endpoint_address & USB_EP_ADDR_MASK; - if (ep_config->size == 1023) { - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = 0x07; - } else { - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE = - (32 - clz(((uint32_t)min(max(ep_config->size, 8), 1024) << 1) - 1) - 1 - 3); - } - - /* Clear busy status */ - host_pipe_job_busy_status &= ~(1 << pipe_num); - - return STATUS_OK; -} - -/** - * \brief Gets an USB host pipe configuration. - * - * Gets out the configuration of an USB host pipe from the hardware module. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[out] ep_config Configuration settings for the pipe - * - * \return Status of the get host pipe configuration operation. - * \retval STATUS_OK The host pipe configuration was read successfully. - */ -enum status_code usb_host_pipe_get_config(struct usb_module *module_inst, uint8_t pipe_num, - struct usb_host_pipe_config *ep_config) -{ - uint32_t size; - - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - Assert(ep_config); - /* get pipe config from setting register */ - ep_config->device_address = - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PDADDR; - ep_config->endpoint_address = - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].CTRL_PIPE.bit.PEPNUM; - - if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN == - USB_HOST_PIPE_TOKEN_IN) { - ep_config->endpoint_address |= USB_EP_DIR_IN; - } - - ep_config->pipe_type = (enum usb_host_pipe_type)module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE; - ep_config->binterval = - module_inst->hw->HOST.HostPipe[pipe_num].BINTERVAL.reg; - size = usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.SIZE; - if (size == 0x07) { - ep_config->size = 1023; - } else { - ep_config->size = (8 << size); - } - - return STATUS_OK; -} - -/** - * \brief Registers a USB host pipe callback - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref usb_host_pipe_enable_callback, - * in order for the interrupt handler to call it when the conditions for the - * callback type is met. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] callback_type Callback type given by an enum - * \param[in] callback_func Pointer to callback function - * - * \return Status of the registration operation. - * \retval STATUS_OK The callback was registered successfully. - */ -enum status_code usb_host_pipe_register_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type, - usb_host_pipe_callback_t callback_func) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(pipe_num < USB_PIPE_NUM); - Assert(callback_func); - - /* Register callback function */ - module_inst->host_pipe_callback[pipe_num][callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module_inst->host_pipe_registered_callback_mask[pipe_num] |= (1 << callback_type); - - return STATUS_OK; -} - -/** - * \brief Unregisters a USB host pipe callback - * - * Unregisters an asynchronous callback implemented by the user. Removing it - * from the internal callback registration table. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the de-registration operation. - * \retval STATUS_OK The callback was unregistered successfully. - */ -enum status_code usb_host_pipe_unregister_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(pipe_num < USB_PIPE_NUM); - - /* Unregister callback function */ - module_inst->host_pipe_callback[pipe_num][callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module_inst->host_pipe_registered_callback_mask[pipe_num] &= ~(1 << callback_type); - - return STATUS_OK; -} - -/** - * \brief Enables USB host pipe callback generation for a given type. - * - * Enables asynchronous callbacks for a given logical type. - * This must be called before USB host pipe generate callback events. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback enable operation. - * \retval STATUS_OK The callback was enabled successfully. - */ -enum status_code usb_host_pipe_enable_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - - /* Enable callback */ - module_inst->host_pipe_enabled_callback_mask[pipe_num] |= (1 << callback_type); - - if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT_Msk; - } - if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = - USB_HOST_PINTENSET_TRFAIL | USB_HOST_PINTENSET_PERR; - } - if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } - if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } - - return STATUS_OK; -} - -/** - * \brief Disables USB host callback generation for a given type. - * - * Disables asynchronous callbacks for a given logical type. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback disable operation. - * \retval STATUS_OK The callback was disabled successfully. - */ -enum status_code usb_host_pipe_disable_callback( - struct usb_module *module_inst, uint8_t pipe_num, - enum usb_host_pipe_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - - /* Enable callback */ - module_inst->host_pipe_enabled_callback_mask[pipe_num] &= ~(1 << callback_type); - - if (callback_type == USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TRCPT_Msk; - } - if (callback_type == USB_HOST_PIPE_CALLBACK_ERROR) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = - USB_HOST_PINTENCLR_TRFAIL| USB_HOST_PINTENCLR_PERR; - } - if (callback_type == USB_HOST_PIPE_CALLBACK_SETUP) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_TXSTP; - } - if (callback_type == USB_HOST_PIPE_CALLBACK_STALL) { - module_inst->hw->HOST.HostPipe[pipe_num].PINTENCLR.reg = USB_HOST_PINTENCLR_STALL; - } - - return STATUS_OK; -} - -/** - * \brief Sends the setup package. - * - * Sends the setup package. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] buf Pointer to data buffer - * - * \return Status of the setup operation. - * \retval STATUS_OK The setup job was set successfully. - * \retval STATUS_BUSY The pipe is busy. - * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured. - */ -enum status_code usb_host_pipe_setup_job(struct usb_module *module_inst, - uint8_t pipe_num, uint8_t *buf) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - - if (host_pipe_job_busy_status & (1 << pipe_num)) { - return STATUS_BUSY; - } - - /* Set busy status */ - host_pipe_job_busy_status |= 1 << pipe_num; - - if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE == - USB_HOST_PIPE_TYPE_DISABLE) { - return STATUS_ERR_NOT_INITIALIZED; - } - - /* get pipe config from setting register */ - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = - 8; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = - 0; - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN = - USB_HOST_PIPE_TOKEN_SETUP; - - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY; - usb_host_pipe_unfreeze(module_inst, pipe_num); - - return STATUS_OK; -} - -/** - * \brief USB host pipe read job. - * - * USB host pipe read job by set and start an in transaction transfer. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] buf Pointer to data buffer - * \param[in] buf_size Data buffer size - * \note The buffer length should not larger than 0x3FFF - * - * \return Status of the setting operation. - * \retval STATUS_OK The read job was set successfully. - * \retval STATUS_BUSY The pipe is busy. - * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured. - */ -enum status_code usb_host_pipe_read_job(struct usb_module *module_inst, - uint8_t pipe_num, uint8_t *buf, uint32_t buf_size) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - - if (host_pipe_job_busy_status & (1 << pipe_num)) { - return STATUS_BUSY; - } - - /* Set busy status */ - host_pipe_job_busy_status |= 1 << pipe_num; - - if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE == - USB_HOST_PIPE_TYPE_DISABLE) { - return STATUS_ERR_NOT_INITIALIZED; - } - - /* get pipe config from setting register */ - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = - 0; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = - buf_size; - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN = - USB_HOST_PIPE_TOKEN_IN; - - /* Start transfer */ - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSCLR.reg = USB_HOST_PSTATUSCLR_BK0RDY; - usb_host_pipe_unfreeze(module_inst, pipe_num); - - return STATUS_OK; -} - -/** - * \brief USB host pipe write job. - * - * USB host pipe write job by set and start an out transaction transfer. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] buf Pointer to data buffer - * \param[in] buf_size Data buffer size - * \note The buffer length should not larger than 0x3FFF - * - * \return Status of the setting operation. - * \retval STATUS_OK The write job was set successfully. - * \retval STATUS_BUSY The pipe is busy. - * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured. - */ -enum status_code usb_host_pipe_write_job(struct usb_module *module_inst, - uint8_t pipe_num, uint8_t *buf, uint32_t buf_size) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - - if (host_pipe_job_busy_status & (1 << pipe_num)) { - return STATUS_BUSY; - } - - /* Set busy status */ - host_pipe_job_busy_status |= 1 << pipe_num; - - if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE == - USB_HOST_PIPE_TYPE_DISABLE) { - return STATUS_ERR_NOT_INITIALIZED; - } - - /* get pipe config from setting register */ - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].ADDR.reg = (uint32_t)buf; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = - buf_size; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = - 0; - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTOKEN = - USB_HOST_PIPE_TOKEN_OUT; - - /* Start transfer */ - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY; - usb_host_pipe_unfreeze(module_inst, pipe_num); - - return STATUS_OK; -} - -/** - * \brief USB host abort a pipe job. - * - * USB host pipe abort job by freeze the pipe. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * - * \return Status of the setting operation. - * \retval STATUS_OK The abort job was set successfully. - * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured. - */ -enum status_code usb_host_pipe_abort_job(struct usb_module *module_inst, uint8_t pipe_num) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - - if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE == - USB_HOST_PIPE_TYPE_DISABLE) { - return STATUS_ERR_NOT_INITIALIZED; - } - - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_PFREEZE; - - /* Clear busy status */ - host_pipe_job_busy_status &= ~(1 << pipe_num); - - return STATUS_OK; -} - -/** - * \brief Sends the LPM package. - * - * Sends the LPM package. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] b_remotewakeup Remote wake up flag - * \param[in] hird Host Initiated Resume Duration - * - * \return Status of the setup operation. - * \retval STATUS_OK The setup job was set successfully. - * \retval STATUS_BUSY The pipe is busy. - * \retval STATUS_ERR_NOT_INITIALIZED The pipe has not been configured. - */ -enum status_code usb_host_pipe_lpm_job(struct usb_module *module_inst, - uint8_t pipe_num, bool b_remotewakeup, uint8_t hird) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(pipe_num < USB_PIPE_NUM); - - if (host_pipe_job_busy_status & (1 << pipe_num)) { - return STATUS_BUSY; - } - - /* Set busy status */ - host_pipe_job_busy_status |= 1 << pipe_num; - - if (module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE == - USB_HOST_PIPE_TYPE_DISABLE) { - return STATUS_ERR_NOT_INITIALIZED; - } - - module_inst->hw->HOST.HostPipe[pipe_num].PCFG.bit.PTYPE = - USB_HOST_PIPE_TYPE_EXTENDED; - - /* get pipe config from setting register */ - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.SUBPID = 0x3; - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].EXTREG.bit.VARIABLE = - USB_LPM_ATTRIBUT_REMOTEWAKE(b_remotewakeup) | - USB_LPM_ATTRIBUT_HIRD(hird) | - USB_LPM_ATTRIBUT_BLINKSTATE_L1; - - module_inst->hw->HOST.HostPipe[pipe_num].PSTATUSSET.reg = USB_HOST_PSTATUSSET_BK0RDY; - usb_host_pipe_unfreeze(module_inst, pipe_num); - - return STATUS_OK; -} - -/** - * \internal - * \brief Function called by USB interrupt to manage USB host interrupts - * - * USB host interrupt events are split into four sections: - * - USB line events - * (Device dis/connection, SOF, reset, resume, wakeup, error) - * - Pipe events - * (End of data transfer, setup, stall, error) - */ -static void _usb_host_interrupt_handler(void) -{ - uint32_t pipe_int; - uint32_t flags; - - /* Manage pipe interrupts */ - pipe_int = ctz(_usb_instances->hw->HOST.PINTSMRY.reg); - if (pipe_int < 32) { - /* pipe interrupts */ - - /* get interrupt flags */ - flags = _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg; - - /* host pipe transfer complete interrupt */ - if (flags & USB_HOST_PINTFLAG_TRCPT_Msk) { - /* Clear busy status */ - host_pipe_job_busy_status &= ~(1 << pipe_int); - /* clear the flag */ - _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg = - USB_HOST_PINTFLAG_TRCPT_Msk; - if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] & - (1 << USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE)) { - pipe_callback_para.pipe_num = pipe_int; - if (_usb_instances->hw->HOST.HostPipe[pipe_int].PCFG.bit.PTOKEN == - USB_HOST_PIPE_TOKEN_IN) { - /* in */ - pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT; - pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE; - usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0; - } else { - /* out */ - pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE; - pipe_callback_para.required_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT; - usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 0; - if (0 == pipe_callback_para.transfered_size) { - pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.BYTE_COUNT; - } - } - (_usb_instances->host_pipe_callback[pipe_int] - [USB_HOST_PIPE_CALLBACK_TRANSFER_COMPLETE])(_usb_instances, &pipe_callback_para); - } - } - - /* host pipe transfer fail interrupt */ - if (flags & USB_HOST_PINTFLAG_TRFAIL) { - /* Clear busy status */ - host_pipe_job_busy_status &= ~(1 << pipe_int); - /* clear the flag */ - _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg = - USB_HOST_PINTFLAG_TRFAIL; - } - - /* host pipe error interrupt */ - if (flags & USB_HOST_PINTFLAG_PERR) { - /* Clear busy status */ - host_pipe_job_busy_status &= ~(1 << pipe_int); - /* clear the flag */ - _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg = - USB_HOST_PINTFLAG_PERR; - if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] & - (1 << USB_HOST_PIPE_CALLBACK_ERROR)) { - pipe_callback_para.pipe_num = pipe_int; - pipe_callback_para.pipe_error_status = - usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].STATUS_PIPE.reg & 0x1F; - (_usb_instances->host_pipe_callback[pipe_int] - [USB_HOST_PIPE_CALLBACK_ERROR])(_usb_instances, &pipe_callback_para); - } - } - - /* host pipe transmitted setup interrupt */ - if (flags & USB_HOST_PINTFLAG_TXSTP) { - /* Clear busy status */ - host_pipe_job_busy_status &= ~(1 << pipe_int); - /* clear the flag */ - _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg = - USB_HOST_PINTFLAG_TXSTP; - if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] & - (1 << USB_HOST_PIPE_CALLBACK_SETUP)) { - pipe_callback_para.pipe_num = pipe_int; - pipe_callback_para.transfered_size = usb_descriptor_table.usb_pipe_table[pipe_int].HostDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE; - (_usb_instances->host_pipe_callback[pipe_int] - [USB_HOST_PIPE_CALLBACK_SETUP])(_usb_instances, NULL); - } - } - - /* host pipe stall interrupt */ - if (flags & USB_HOST_PINTFLAG_STALL) { - /* Clear busy status */ - host_pipe_job_busy_status &= ~(1 << pipe_int); - /* clear the flag */ - _usb_instances->hw->HOST.HostPipe[pipe_int].PINTFLAG.reg = - USB_HOST_PINTFLAG_STALL; - if(_usb_instances->host_pipe_enabled_callback_mask[pipe_int] & - (1 << USB_HOST_PIPE_CALLBACK_STALL)) { - pipe_callback_para.pipe_num = pipe_int; - (_usb_instances->host_pipe_callback[pipe_int] - [USB_HOST_PIPE_CALLBACK_STALL])(_usb_instances, &pipe_callback_para); - } - } - - } else { - /* host interrupts */ - - /* get interrupt flags */ - flags = _usb_instances->hw->HOST.INTFLAG.reg; - - /* host SOF interrupt */ - if (flags & USB_HOST_INTFLAG_HSOF) { - /* clear the flag */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_SOF)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_SOF])(_usb_instances); - } - } - - /* host reset interrupt */ - if (flags & USB_HOST_INTFLAG_RST) { - /* Clear busy status */ - host_pipe_job_busy_status = 0; - /* clear the flag */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RESET)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_RESET])(_usb_instances); - } - } - - /* host upstream resume interrupts */ - if (flags & USB_HOST_INTFLAG_UPRSM) { - /* clear the flags */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_UPRSM)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_UPRSM])(_usb_instances); - } - } - - /* host downstream resume interrupts */ - if (flags & USB_HOST_INTFLAG_DNRSM) { - /* clear the flags */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DNRSM)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_DNRSM])(_usb_instances); - } - } - - /* host wakeup interrupts */ - if (flags & USB_HOST_INTFLAG_WAKEUP) { - /* clear the flags */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_WAKEUP)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_WAKEUP])(_usb_instances); - } - } - - /* host ram access interrupt */ - if (flags & USB_HOST_INTFLAG_RAMACER) { - /* Clear busy status */ - host_pipe_job_busy_status = 0; - /* clear the flag */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_RAMACER)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_RAMACER])(_usb_instances); - } - } - - /* host connect interrupt */ - if (flags & USB_HOST_INTFLAG_DCONN) { - /* Clear busy status */ - host_pipe_job_busy_status = 0; - /* clear the flag */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_CONNECT)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_CONNECT])(_usb_instances); - } - } - - /* host disconnect interrupt */ - if (flags & USB_HOST_INTFLAG_DDISC) { - /* Clear busy status */ - host_pipe_job_busy_status = 0; - /* clear the flag */ - _usb_instances->hw->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; - if(_usb_instances->host_enabled_callback_mask & (1 << USB_HOST_CALLBACK_DISCONNECT)) { - (_usb_instances->host_callback[USB_HOST_CALLBACK_DISCONNECT])(_usb_instances); - } - } - - } -} - -/** - * \brief Sets USB host pipe auto ZLP setting value - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] pipe_num Pipe to configure - * \param[in] value Auto ZLP setting value, \c true to enable - * - */ -void usb_host_pipe_set_auto_zlp(struct usb_module *module_inst, uint8_t pipe_num, bool value) -{ - Assert(module_inst); - - usb_descriptor_table.usb_pipe_table[pipe_num].HostDescBank[0].PCKSIZE.bit.AUTO_ZLP = value; -} -#endif - -/** - * \brief Registers a USB device callback - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref usb_device_enable_callback, - * in order for the interrupt handler to call it when the conditions for the - * callback type is met. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * \param[in] callback_func Pointer to callback function - * - * \return Status of the registration operation. - * \retval STATUS_OK The callback was registered successfully. - */ -enum status_code usb_device_register_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type, - usb_device_callback_t callback_func) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(callback_func); - - /* Register callback function */ - module_inst->device_callback[callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module_inst->device_registered_callback_mask |= _usb_device_irq_bits[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Unregisters a USB device callback - * - * Unregisters an asynchronous callback implemented by the user. Removing it - * from the internal callback registration table. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the de-registration operation. - * \retval STATUS_OK The callback was unregistered successfully. - */ -enum status_code usb_device_unregister_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - - /* Unregister callback function */ - module_inst->device_callback[callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module_inst->device_registered_callback_mask &= ~_usb_device_irq_bits[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Enables USB device callback generation for a given type. - * - * Enables asynchronous callbacks for a given logical type. - * This must be called before USB device generate callback events. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback enable operation. - * \retval STATUS_OK The callback was enabled successfully. - */ -enum status_code usb_device_enable_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* clear related flag */ - module_inst->hw->DEVICE.INTFLAG.reg = _usb_device_irq_bits[callback_type]; - - /* Enable callback */ - module_inst->device_enabled_callback_mask |= _usb_device_irq_bits[callback_type]; - - module_inst->hw->DEVICE.INTENSET.reg = _usb_device_irq_bits[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Disables USB device callback generation for a given type. - * - * Disables asynchronous callbacks for a given logical type. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback disable operation. - * \retval STATUS_OK The callback was disabled successfully. - */ -enum status_code usb_device_disable_callback(struct usb_module *module_inst, - enum usb_device_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* Disable callback */ - module_inst->device_enabled_callback_mask &= ~_usb_device_irq_bits[callback_type]; - - module_inst->hw->DEVICE.INTENCLR.reg = _usb_device_irq_bits[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Registers a USB device endpoint callback - * - * Registers a callback function which is implemented by the user. - * - * \note The callback must be enabled by \ref usb_device_endpoint_enable_callback, - * in order for the interrupt handler to call it when the conditions for the - * callback type is met. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] ep_num Endpoint to configure - * \param[in] callback_type Callback type given by an enum - * \param[in] callback_func Pointer to callback function - * - * \return Status of the registration operation. - * \retval STATUS_OK The callback was registered successfully. - */ -enum status_code usb_device_endpoint_register_callback( - struct usb_module *module_inst, uint8_t ep_num, - enum usb_device_endpoint_callback callback_type, - usb_device_endpoint_callback_t callback_func) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(ep_num < USB_EPT_NUM); - Assert(callback_func); - - /* Register callback function */ - module_inst->device_endpoint_callback[ep_num][callback_type] = callback_func; - - /* Set the bit corresponding to the callback_type */ - module_inst->device_endpoint_registered_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Unregisters a USB device endpoint callback - * - * Unregisters an callback implemented by the user. Removing it - * from the internal callback registration table. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] ep_num Endpoint to configure - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the de-registration operation. - * \retval STATUS_OK The callback was unregistered successfully. - */ -enum status_code usb_device_endpoint_unregister_callback( - struct usb_module *module_inst, uint8_t ep_num, - enum usb_device_endpoint_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(ep_num < USB_EPT_NUM); - - /* Unregister callback function */ - module_inst->device_endpoint_callback[ep_num][callback_type] = NULL; - - /* Clear the bit corresponding to the callback_type */ - module_inst->device_endpoint_registered_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type]; - - return STATUS_OK; -} - -/** - * \brief Enables USB device endpoint callback generation for a given type. - * - * Enables callbacks for a given logical type. - * This must be called before USB device pipe generate callback events. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] ep Endpoint to configure - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback enable operation. - * \retval STATUS_OK The callback was enabled successfully. - */ -enum status_code usb_device_endpoint_enable_callback( - struct usb_module *module_inst, uint8_t ep, - enum usb_device_endpoint_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - Assert(ep_num < USB_EPT_NUM); - - /* Enable callback */ - module_inst->device_endpoint_enabled_callback_mask[ep_num] |= _usb_endpoint_irq_bits[callback_type]; - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) { - if (ep_num == 0) { // control endpoint - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0 | USB_DEVICE_EPINTENSET_TRCPT1; - } else if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } - } - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) { - if (ep_num == 0) { // control endpoint - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0 | USB_DEVICE_EPINTENSET_TRFAIL1; - } else if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } - } - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) { - if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } - } - - return STATUS_OK; -} - -/** - * \brief Disables USB device endpoint callback generation for a given type. - * - * Disables callbacks for a given logical type. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] ep Endpoint to configure - * \param[in] callback_type Callback type given by an enum - * - * \return Status of the callback disable operation. - * \retval STATUS_OK The callback was disabled successfully. - */ -enum status_code usb_device_endpoint_disable_callback( - struct usb_module *module_inst, uint8_t ep, - enum usb_device_endpoint_callback callback_type) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - Assert(ep_num < USB_EPT_NUM); - - /* Enable callback */ - module_inst->device_endpoint_enabled_callback_mask[ep_num] &= ~_usb_endpoint_irq_bits[callback_type]; - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRCPT) { - if (ep_num == 0) { // control endpoint - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT0 | USB_DEVICE_EPINTENCLR_TRCPT1; - } else if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRCPT0; - } - } - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL) { - if (ep_num == 0) { // control endpoint - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0 | USB_DEVICE_EPINTENCLR_TRFAIL1; - } else if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_TRFAIL0; - } - } - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_RXSTP) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_RXSTP; - } - - if (callback_type == USB_DEVICE_ENDPOINT_CALLBACK_STALL) { - if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTENCLR.reg = USB_DEVICE_EPINTENCLR_STALL0; - } - } - - return STATUS_OK; -} - -/** - * \brief Initializes an USB device endpoint configuration structure to defaults. - * - * Initializes a given USB device endpoint configuration structure to a - * set of known default values. This function should be called on all new - * instances of these configuration structures before being modified by the - * user application. - * - * The default configuration is as follows: - * \li endpoint address is 0 - * \li endpoint size is 8 bytes - * \li auto_zlp is false - * \li endpoint type is control - * - * \param[out] ep_config Configuration structure to initialize to default values - */ -void usb_device_endpoint_get_config_defaults(struct usb_device_endpoint_config *ep_config) -{ - /* Sanity check arguments */ - Assert(ep_config); - - /* Write default config to config struct */ - ep_config->ep_address = 0; - ep_config->ep_size = USB_ENDPOINT_8_BYTE; - ep_config->auto_zlp = false; - ep_config->ep_type = USB_DEVICE_ENDPOINT_TYPE_CONTROL; -} - -/** - * \brief Writes an USB device endpoint configuration to the hardware module. - * - * Writes out a given configuration of an USB device endpoint - * configuration to the hardware module. If the pipe is already configured, - * the new configuration will replace the existing one. - * - * \param[in] module_inst Pointer to USB software instance struct - * \param[in] ep_config Configuration settings for the endpoint - * - * \return Status of the device endpoint configuration operation - * \retval STATUS_OK The device endpoint was configured successfully - * \retval STATUS_ERR_DENIED The endpoint address is already configured - */ -enum status_code usb_device_endpoint_set_config(struct usb_module *module_inst, - struct usb_device_endpoint_config *ep_config) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(ep_config); - - uint8_t ep_num = ep_config->ep_address & USB_EP_ADDR_MASK; - uint8_t ep_bank = (ep_config->ep_address & USB_EP_DIR_IN) ? 1 : 0; - - switch (ep_config->ep_type) { - case USB_DEVICE_ENDPOINT_TYPE_DISABLE: - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(0) | USB_DEVICE_EPCFG_EPTYPE1(0); - return STATUS_OK; - - case USB_DEVICE_ENDPOINT_TYPE_CONTROL: - if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0 && \ - (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg = USB_DEVICE_EPCFG_EPTYPE0(1) | USB_DEVICE_EPCFG_EPTYPE1(1); - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY; - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY; - } else { - return STATUS_ERR_DENIED; - } - if (true == ep_config->auto_zlp) { - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - } else { - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - } - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.SIZE = ep_config->ep_size; - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.SIZE = ep_config->ep_size; - return STATUS_OK; - - case USB_DEVICE_ENDPOINT_TYPE_ISOCHRONOUS: - if (ep_bank) { - if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){ - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(2); - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY; - } else { - return STATUS_ERR_DENIED; - } - } else { - if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){ - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(2); - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY; - } else { - return STATUS_ERR_DENIED; - } - } - break; - - case USB_DEVICE_ENDPOINT_TYPE_BULK: - if (ep_bank) { - if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){ - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(3); - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY; - } else { - return STATUS_ERR_DENIED; - } - } else { - if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){ - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(3); - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY; - } else { - return STATUS_ERR_DENIED; - } - } - break; - - case USB_DEVICE_ENDPOINT_TYPE_INTERRUPT: - if (ep_bank) { - if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE1_Msk) == 0){ - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(4); - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY; - } else { - return STATUS_ERR_DENIED; - } - } else { - if ((module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg & USB_DEVICE_EPCFG_EPTYPE0_Msk) == 0){ - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(4); - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY; - } else { - return STATUS_ERR_DENIED; - } - } - break; - - default: - break; - } - - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.bit.SIZE = ep_config->ep_size; - - if (true == ep_config->auto_zlp) { - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - } else { - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[ep_bank].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - } - - return STATUS_OK; -} - -/** - * \brief Check if current endpoint is configured - * - * \param module_inst Pointer to USB software instance struct - * \param ep Endpoint address (direction & number) - * - * \return \c true if endpoint is configured and ready to use - */ -bool usb_device_endpoint_is_configured(struct usb_module *module_inst, uint8_t ep) -{ - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - uint8_t flag; - - if (ep & USB_EP_DIR_IN) { - flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1); - } else { - flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0); - } - return ((enum usb_device_endpoint_type)(flag) != USB_DEVICE_ENDPOINT_TYPE_DISABLE); -} - - -/** - * \brief Abort ongoing job on the endpoint - * - * \param module_inst Pointer to USB software instance struct - * \param ep Endpoint address - */ -void usb_device_endpoint_abort_job(struct usb_module *module_inst, uint8_t ep) -{ - uint8_t ep_num; - ep_num = ep & USB_EP_ADDR_MASK; - - // Stop transfer - if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK1RDY; - // Eventually ack a transfer occur during abort - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK0RDY; - // Eventually ack a transfer occur during abort - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; - } -} - -/** - * \brief Check if endpoint is halted - * - * \param module_inst Pointer to USB software instance struct - * \param ep Endpoint address - * - * \return \c true if the endpoint is halted - */ -bool usb_device_endpoint_is_halted(struct usb_module *module_inst, uint8_t ep) -{ - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - - if (ep & USB_EP_DIR_IN) { - return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1); - } else { - return (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0); - } -} - -/** - * \brief Halt the endpoint (send STALL) - * - * \param module_inst Pointer to USB software instance struct - * \param ep Endpoint address - */ -void usb_device_endpoint_set_halt(struct usb_module *module_inst, uint8_t ep) -{ - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - - // Stall endpoint - if (ep & USB_EP_DIR_IN) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ1; - } else { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_STALLRQ0; - } -} - -/** - * \brief Clear endpoint halt state - * - * \param module_inst Pointer to USB software instance struct - * \param ep Endpoint address - */ -void usb_device_endpoint_clear_halt(struct usb_module *module_inst, uint8_t ep) -{ - uint8_t ep_num = ep & USB_EP_ADDR_MASK; - - if (ep & USB_EP_DIR_IN) { - if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ1) { - // Remove stall request - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ1; - if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; - // The Stall has occurred, then reset data toggle - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLIN; - } - } - } else { - if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUS.reg & USB_DEVICE_EPSTATUSSET_STALLRQ0) { - // Remove stall request - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_STALLRQ0; - if (module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) { - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; - // The Stall has occurred, then reset data toggle - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSSET_DTGLOUT; - } - } - } -} - -/** - * \brief Start write buffer job on a endpoint - * - * \param module_inst Pointer to USB module instance - * \param ep_num Endpoint number - * \param pbuf Pointer to buffer - * \param buf_size Size of buffer - * - * \return Status of procedure - * \retval STATUS_OK Job started successfully - * \retval STATUS_ERR_DENIED Endpoint is not ready - */ -enum status_code usb_device_endpoint_write_buffer_job(struct usb_module *module_inst,uint8_t ep_num, - uint8_t* pbuf, uint32_t buf_size) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(ep_num < USB_EPT_NUM); - - uint8_t flag; - flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE1); - if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) { - return STATUS_ERR_DENIED; - }; - - /* get endpoint configuration from setting register */ - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].ADDR.reg = (uint32_t)pbuf; - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.MULTI_PACKET_SIZE = 0; - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT = buf_size; - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSSET.reg = USB_DEVICE_EPSTATUSSET_BK1RDY; - - return STATUS_OK; -} - -/** - * \brief Start read buffer job on a endpoint - * - * \param module_inst Pointer to USB module instance - * \param ep_num Endpoint number - * \param pbuf Pointer to buffer - * \param buf_size Size of buffer - * - * \return Status of procedure - * \retval STATUS_OK Job started successfully - * \retval STATUS_ERR_DENIED Endpoint is not ready - */ -enum status_code usb_device_endpoint_read_buffer_job(struct usb_module *module_inst,uint8_t ep_num, - uint8_t* pbuf, uint32_t buf_size) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - Assert(ep_num < USB_EPT_NUM); - - uint8_t flag; - flag = (uint8_t)(module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPCFG.bit.EPTYPE0); - if ((enum usb_device_endpoint_type)(flag) == USB_DEVICE_ENDPOINT_TYPE_DISABLE) { - return STATUS_ERR_DENIED; - }; - - /* get endpoint configuration from setting register */ - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf; - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = buf_size; - usb_descriptor_table.usb_endpoint_table[ep_num].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0; - module_inst->hw->DEVICE.DeviceEndpoint[ep_num].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY; - - return STATUS_OK; -} - -/** - * \brief Start setup packet read job on a endpoint - * - * \param module_inst Pointer to USB device module instance - * \param pbuf Pointer to buffer - * - * \return Status of procedure - * \retval STATUS_OK Job started successfully - * \retval STATUS_ERR_DENIED Endpoint is not ready - */ -enum status_code usb_device_endpoint_setup_buffer_job(struct usb_module *module_inst, - uint8_t* pbuf) -{ - /* Sanity check arguments */ - Assert(module_inst); - Assert(module_inst->hw); - - /* get endpoint configuration from setting register */ - usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].ADDR.reg = (uint32_t)pbuf; - usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE = 8; - usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT = 0; - module_inst->hw->DEVICE.DeviceEndpoint[0].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUSCLR_BK0RDY; - - return STATUS_OK; -} - -static void _usb_device_interrupt_handler(void) -{ - uint16_t ep_inst; - uint16_t flags, flags_run; - ep_inst = _usb_instances->hw->DEVICE.EPINTSMRY.reg; - - /* device interrupt */ - if (0 == ep_inst) { - int i; - - /* get interrupt flags */ - flags = _usb_instances->hw->DEVICE.INTFLAG.reg; - flags_run = flags & - _usb_instances->device_enabled_callback_mask & - _usb_instances->device_registered_callback_mask; - - for (i = 0; i < USB_DEVICE_CALLBACK_N; i ++) { - if (flags & _usb_device_irq_bits[i]) { - _usb_instances->hw->DEVICE.INTFLAG.reg = - _usb_device_irq_bits[i]; - } - if (flags_run & _usb_device_irq_bits[i]) { - if (i == USB_DEVICE_CALLBACK_LPMSUSP) { - device_callback_lpm_wakeup_enable = - usb_descriptor_table.usb_endpoint_table[0].DeviceDescBank[0].EXTREG.bit.VARIABLE - & USB_LPM_ATTRIBUT_REMOTEWAKE_MASK; - } - (_usb_instances->device_callback[i])(_usb_instances, &device_callback_lpm_wakeup_enable); - } - } - - } else { - /* endpoint interrupt */ - - for (uint8_t i = 0; i < USB_EPT_NUM; i++) { - - if (ep_inst & (1 << i)) { - flags = _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg; - flags_run = flags & - _usb_instances->device_endpoint_enabled_callback_mask[i] & - _usb_instances->device_endpoint_registered_callback_mask[i]; - - // endpoint transfer stall interrupt - if (flags & USB_DEVICE_EPINTFLAG_STALL_Msk) { - if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) { - _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; - ep_callback_para.endpoint_address = USB_EP_DIR_IN | i; - } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) { - _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; - ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i; - } - - if (flags_run & USB_DEVICE_EPINTFLAG_STALL_Msk) { - (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_STALL])(_usb_instances,&ep_callback_para); - } - return; - } - - // endpoint received setup interrupt - if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { - _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; - if(_usb_instances->device_endpoint_enabled_callback_mask[i] & _usb_endpoint_irq_bits[USB_DEVICE_ENDPOINT_CALLBACK_RXSTP]) { - ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT); - (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_RXSTP])(_usb_instances,&ep_callback_para); - } - return; - } - - // endpoint transfer complete interrupt - if (flags & USB_DEVICE_EPINTFLAG_TRCPT_Msk) { - if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) { - _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; - ep_callback_para.endpoint_address = USB_EP_DIR_IN | i; - ep_callback_para.sent_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].PCKSIZE.bit.BYTE_COUNT); - - } else if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) { - _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; - ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i; - ep_callback_para.received_bytes = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.BYTE_COUNT); - ep_callback_para.out_buffer_size = (uint16_t)(usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].PCKSIZE.bit.MULTI_PACKET_SIZE); - } - if(flags_run & USB_DEVICE_EPINTFLAG_TRCPT_Msk) { - (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRCPT])(_usb_instances,&ep_callback_para); - } - return; - } - - // endpoint transfer fail interrupt - if (flags & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) { - if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) { - _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; - if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) { - usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[1].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW; - } - ep_callback_para.endpoint_address = USB_EP_DIR_IN | i; - if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) { - return; - } - } else if(_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) { - _usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; - if (usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) { - usb_descriptor_table.usb_endpoint_table[i].DeviceDescBank[0].STATUS_BK.reg &= ~USB_DEVICE_STATUS_BK_ERRORFLOW; - } - ep_callback_para.endpoint_address = USB_EP_DIR_OUT | i; - if (_usb_instances->hw->DEVICE.DeviceEndpoint[i].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) { - return; - } - } - - if(flags_run & USB_DEVICE_EPINTFLAG_TRFAIL_Msk) { - (_usb_instances->device_endpoint_callback[i][USB_DEVICE_ENDPOINT_CALLBACK_TRFAIL])(_usb_instances,&ep_callback_para); - } - return; - } - } - } - } -} - -/** - * \brief Enable the USB module peripheral - * - * \param module_inst pointer to USB module instance - */ -void usb_enable(struct usb_module *module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE; - while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE); -} - -/** - * \brief Disable the USB module peripheral - * - * \param module_inst pointer to USB module instance - */ -void usb_disable(struct usb_module *module_inst) -{ - Assert(module_inst); - Assert(module_inst->hw); - - module_inst->hw->DEVICE.INTENCLR.reg = USB_DEVICE_INTENCLR_MASK; - module_inst->hw->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MASK; - module_inst->hw->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE; - while (module_inst->hw->DEVICE.SYNCBUSY.reg == USB_SYNCBUSY_ENABLE); -} - -/** - * \brief Interrupt handler for the USB module. - */ -void USB_Handler(void) -{ - if (_usb_instances->hw->DEVICE.CTRLA.bit.MODE) { -#if !SAMD11 - /*host mode ISR */ - _usb_host_interrupt_handler(); -#endif - } else { - /*device mode ISR */ - _usb_device_interrupt_handler(); - } -} - -/** - * \brief Get the default USB module settings - * - * \param[out] module_config Configuration structure to initialize to default values - */ -void usb_get_config_defaults(struct usb_config *module_config) -{ - Assert(module_config); - - /* Sanity check arguments */ - Assert(module_config); - /* Write default configuration to config struct */ - module_config->select_host_mode = 0; - module_config->run_in_standby = 1; - module_config->source_generator = GCLK_GENERATOR_0; - module_config->speed_mode = USB_SPEED_FULL; -} - -#define NVM_USB_PAD_TRANSN_POS 45 -#define NVM_USB_PAD_TRANSN_SIZE 5 -#define NVM_USB_PAD_TRANSP_POS 50 -#define NVM_USB_PAD_TRANSP_SIZE 5 -#define NVM_USB_PAD_TRIM_POS 55 -#define NVM_USB_PAD_TRIM_SIZE 3 - -/** - * \brief Initializes USB module instance - * - * Enables the clock and initializes the USB module, based on the given - * configuration values. - * - * \param[in,out] module_inst Pointer to the software module instance struct - * \param[in] hw Pointer to the USB hardware module - * \param[in] module_config Pointer to the USB configuration options struct - * - * \return Status of the initialization procedure. - * - * \retval STATUS_OK The module was initialized successfully - */ -enum status_code usb_init(struct usb_module *module_inst, Usb *const hw, - struct usb_config *module_config) -{ - /* Sanity check arguments */ - Assert(hw); - Assert(module_inst); - Assert(module_config); - - uint32_t i,j; - uint32_t pad_transn, pad_transp, pad_trim; - struct system_pinmux_config pin_config; - struct system_gclk_chan_config gclk_chan_config; - -#if !SAMD11 - host_pipe_job_busy_status = 0; -#endif - - _usb_instances = module_inst; - - /* Associate the software module instance with the hardware module */ - module_inst->hw = hw; - - /* Turn on the digital interface clock */ - system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB, PM_APBBMASK_USB); - - /* Set up the USB DP/DN pins */ - system_pinmux_get_config_defaults(&pin_config); - pin_config.mux_position = MUX_PA24G_USB_DM; - system_pinmux_pin_set_config(PIN_PA24G_USB_DM, &pin_config); - pin_config.mux_position = MUX_PA25G_USB_DP; - system_pinmux_pin_set_config(PIN_PA25G_USB_DP, &pin_config); - - /* Setup clock for module */ - system_gclk_chan_get_config_defaults(&gclk_chan_config); - gclk_chan_config.source_generator = module_config->source_generator; - system_gclk_chan_set_config(USB_GCLK_ID, &gclk_chan_config); - system_gclk_chan_enable(USB_GCLK_ID); - - /* Reset */ - hw->DEVICE.CTRLA.bit.SWRST = 1; - while (hw->DEVICE.SYNCBUSY.bit.SWRST) { - /* Sync wait */ - } - - /* Change QOS values to have the best performance and correct USB behaviour */ - USB->DEVICE.QOSCTRL.bit.CQOS = 2; - USB->DEVICE.QOSCTRL.bit.DQOS = 2; - - /* Load Pad Calibration */ - pad_transn =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_USB_PAD_TRANSN_POS / 32)) - >> (NVM_USB_PAD_TRANSN_POS % 32)) - & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1); - - if (pad_transn == 0x1F) { - pad_transn = 5; - } - - hw->DEVICE.PADCAL.bit.TRANSN = pad_transn; - - pad_transp =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_USB_PAD_TRANSP_POS / 32)) - >> (NVM_USB_PAD_TRANSP_POS % 32)) - & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1); - - if (pad_transp == 0x1F) { - pad_transp = 29; - } - - hw->DEVICE.PADCAL.bit.TRANSP = pad_transp; - - pad_trim =( *((uint32_t *)(NVMCTRL_OTP4) - + (NVM_USB_PAD_TRIM_POS / 32)) - >> (NVM_USB_PAD_TRIM_POS % 32)) - & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1); - - if (pad_trim == 0x7) { - pad_trim = 3; - } - - hw->DEVICE.PADCAL.bit.TRIM = pad_trim; - - /* Set the configuration */ - hw->DEVICE.CTRLA.bit.MODE = module_config->select_host_mode; - hw->DEVICE.CTRLA.bit.RUNSTDBY = module_config->run_in_standby; - hw->DEVICE.DESCADD.reg = (uint32_t)(&usb_descriptor_table.usb_endpoint_table[0]); - if (USB_SPEED_FULL == module_config->speed_mode) { - module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_FS_Val; - } else if(USB_SPEED_LOW == module_config->speed_mode) { - module_inst->hw->DEVICE.CTRLB.bit.SPDCONF = USB_DEVICE_CTRLB_SPDCONF_LS_Val; - } - - memset((uint8_t *)(&usb_descriptor_table.usb_endpoint_table[0]), 0, - sizeof(usb_descriptor_table.usb_endpoint_table)); - -#if !SAMD11 - /* callback related init */ - for (i = 0; i < USB_HOST_CALLBACK_N; i++) { - module_inst->host_callback[i] = NULL; - }; - for (i = 0; i < USB_PIPE_NUM; i++) { - for (j = 0; j < USB_HOST_PIPE_CALLBACK_N; j++) { - module_inst->host_pipe_callback[i][j] = NULL; - } - }; - module_inst->host_registered_callback_mask = 0; - module_inst->host_enabled_callback_mask = 0; - for (i = 0; i < USB_PIPE_NUM; i++) { - module_inst->host_pipe_registered_callback_mask[i] = 0; - module_inst->host_pipe_enabled_callback_mask[i] = 0; - } -#endif - - /* device callback related */ - for (i = 0; i < USB_DEVICE_CALLBACK_N; i++) { - module_inst->device_callback[i] = NULL; - } - for (i = 0; i < USB_EPT_NUM; i++) { - for(j = 0; j < USB_DEVICE_EP_CALLBACK_N; j++) { - module_inst->device_endpoint_callback[i][j] = NULL; - } - } - module_inst->device_registered_callback_mask = 0; - module_inst->device_enabled_callback_mask = 0; - for (j = 0; j < USB_EPT_NUM; j++) { - module_inst->device_endpoint_registered_callback_mask[j] = 0; - module_inst->device_endpoint_enabled_callback_mask[j] = 0; - } - - /* Enable interrupts for this USB module */ - system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_USB); - - return STATUS_OK; -} - - diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/ac.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/ac.h deleted file mode 100644 index 9ede7e095e5d6..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/ac.h +++ /dev/null @@ -1,559 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_AC_COMPONENT_ -#define _SAMD21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2205 -#define REV_AC 0x112 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE 0x00ul /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (0x1ul << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (0x1ul << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ -#define AC_CTRLA_RUNSTDBY_Msk (0x1ul << AC_CTRLA_RUNSTDBY_Pos) -#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) -#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ -#define AC_CTRLA_LPMUX (0x1ul << AC_CTRLA_LPMUX_Pos) -#define AC_CTRLA_MASK 0x87ul /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE 0x00ul /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (0x3ul << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK 0x03ul /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE 0x0000ul /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (0x3ul << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (0x1ul << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ -#define AC_EVCTRL_COMPEI_Msk (0x3ul << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_MASK 0x0313ul /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE 0x00ul /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (0x3ul << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (0x1ul << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK 0x13ul /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE 0x00ul /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (0x3ul << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (0x1ul << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK 0x13ul /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE 0x00ul /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (0x3ul << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (0x1ul << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK 0x13ul /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE 0x00ul /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (0x3ul << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (0x3ul << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK 0x33ul /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE 0x00ul /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (0x3ul << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ -#define AC_STATUSB_SYNCBUSY (0x1ul << AC_STATUSB_SYNCBUSY_Pos) -#define AC_STATUSB_MASK 0x83ul /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ -#define AC_STATUSC_RESETVALUE 0x00ul /**< \brief (AC_STATUSC reset_value) Status C */ - -#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ -#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) -#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ -#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) -#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ -#define AC_STATUSC_STATE_Msk (0x3ul << AC_STATUSC_STATE_Pos) -#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) -#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ -#define AC_STATUSC_WSTATE0_Msk (0x3ul << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) -#define AC_STATUSC_WSTATE0_ABOVE_Val 0x0ul /**< \brief (AC_STATUSC) Signal is above window */ -#define AC_STATUSC_WSTATE0_INSIDE_Val 0x1ul /**< \brief (AC_STATUSC) Signal is inside window */ -#define AC_STATUSC_WSTATE0_BELOW_Val 0x2ul /**< \brief (AC_STATUSC) Signal is below window */ -#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_MASK 0x33ul /**< \brief (AC_STATUSC) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE 0x00ul /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (0x1ul << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (0x3ul << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val 0x0ul /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val 0x1ul /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val 0x2ul /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val 0x3ul /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK 0x07ul /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE 0x00000000ul /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (0x1ul << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (0x1ul << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (0x3ul << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val 0x0ul /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val 0x1ul /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (0x3ul << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val 0x0ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val 0x1ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val 0x2ul /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val 0x3ul /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (0x7ul << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val 0x4ul /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val 0x5ul /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val 0x6ul /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val 0x7ul /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (0x3ul << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (0x1ul << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (0x3ul << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val 0x1ul /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val 0x2ul /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYST (0x1ul << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (0x7ul << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val 0x0ul /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val 0x1ul /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val 0x2ul /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_MASK 0x070BB76Ful /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE 0x00ul /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (0x3Ful << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK 0x3Ful /**< \brief (AC_SCALER) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/adc.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/adc.h deleted file mode 100644 index 918051e1cb12e..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/adc.h +++ /dev/null @@ -1,699 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_ADC_COMPONENT_ -#define _SAMD21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2204 -#define REV_ADC 0x120 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ -#define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ -#define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ -#define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos) -#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ -#define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ -#define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ - -#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ -#define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) -#define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */ -#define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ -#define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ -#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ -#define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */ -#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ -#define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos) -#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) -#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ -#define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos) -#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) -#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ -#define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) -#define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */ -#define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */ -#define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */ -#define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */ -#define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */ -#define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */ -#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ -#define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ -#define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ -#define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ -#define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ -#define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos) -#define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ -#define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos) -#define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ -#define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ -#define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ -#define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ -#define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos) -#define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ -#define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos) -#define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ -#define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos) -#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) -#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ -#define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos) -#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) -#define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/dac.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/dac.h deleted file mode 100644 index 79cfe0ce6893b..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/dac.h +++ /dev/null @@ -1,286 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DAC_COMPONENT_ -#define _SAMD21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DAC Digital Analog Converter */ -/*@{*/ - -#define DAC_U2214 -#define REV_DAC 0x110 - -/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ -#define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ -#define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos) -#define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ - uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ - uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ - uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ - uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ -#define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos) -#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ -#define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos) -#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ -#define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos) -#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ -#define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos) -#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ -#define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos) -#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ -#define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */ -#define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */ -#define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */ -#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ - uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ -#define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ -#define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos) -#define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ -#define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos) -#define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ - __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ - __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ -#define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ -#define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ -#define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos) -#define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ -#define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos) -#define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ -#define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ -#define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ -#define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ - RoReg8 Reserved2[0x2]; - __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/dmac.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/dmac.h deleted file mode 100644 index 49430bb917861..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/component/dmac.h +++ /dev/null @@ -1,1087 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DMAC_COMPONENT_ -#define _SAMD21_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x110 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (0x1ul << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (0x1ul << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (0x1ul << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (0xFul << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK 0x0F07ul /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (0x3ul << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_CRCCTRL) Byte bus access */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_CRCCTRL) Half-word bus access */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_CRCCTRL) Word bus access */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (0x3ul << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val 0x0ul /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val 0x1ul /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (0x3Ful << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val 0x0ul /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val 0x1ul /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK 0x3F0Ful /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (0xFFFFFFFFul << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE 0x00000000ul /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (0xFFFFFFFFul << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK 0xFFFFFFFFul /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (0x1ul << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (0x1ul << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK 0x03ul /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (0x1ul << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK 0x01ul /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ -#define DMAC_QOSCTRL_RESETVALUE 0x15ul /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ - -#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ -#define DMAC_QOSCTRL_WRBQOS_Msk (0x3ul << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) -#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_WRBQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_WRBQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ -#define DMAC_QOSCTRL_FQOS_Msk (0x3ul << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) -#define DMAC_QOSCTRL_FQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_FQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_FQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_FQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ -#define DMAC_QOSCTRL_DQOS_Msk (0x3ul << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) -#define DMAC_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_MASK 0x3Ful /**< \brief (DMAC_QOSCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE 0x00000000ul /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (0xFFFul << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK 0x00000FFFul /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE 0x00000000ul /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (0xFul << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (0x1ul << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (0xFul << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (0x1ul << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (0xFul << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (0x1ul << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (0xFul << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (0x1ul << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK 0x8F8F8F8Ful /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE 0x0000ul /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (0xFul << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (0x1ul << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (0x1ul << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (0x1ul << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (0x1ul << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (0x1ul << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (0x1ul << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK 0xE70Ful /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE 0x00000000ul /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (0xFFFul << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK 0x00000FFFul /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (0xFFFul << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK 0x00000FFFul /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE 0x00000000ul /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (0xFFFul << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK 0x00000FFFul /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE 0x00000000ul /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (0xFul << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (0x1Ful << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (0x1ul << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (0xFFFFul << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK 0xFFFF9F0Ful /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (0xFFFFFFFFul << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE 0x00000000ul /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (0xFFFFFFFFul << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK 0xFFFFFFFFul /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE 0x00ul /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (0xFul << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) -#define DMAC_CHID_MASK 0x0Ful /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE 0x00ul /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (0x1ul << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (0x1ul << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_MASK 0x03ul /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE 0x00000000ul /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (0x7ul << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) -#define DMAC_CHCTRLB_EVACT_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val 0x4ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val 0x5ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val 0x6ul /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (0x1ul << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (0x1ul << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (0x3ul << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) -#define DMAC_CHCTRLB_LVL_LVL0_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ -#define DMAC_CHCTRLB_LVL_LVL1_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ -#define DMAC_CHCTRLB_LVL_LVL2_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ -#define DMAC_CHCTRLB_LVL_LVL3_Val 0x3ul /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ -#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Peripheral Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (0x3Ful << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val 0x0ul /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (0x3ul << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val 0x0ul /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val 0x2ul /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val 0x3ul /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (0x3ul << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val 0x0ul /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val 0x1ul /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val 0x2ul /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK 0x03C03F7Ful /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (0x1ul << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (0x1ul << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (0x1ul << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK 0x07ul /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (0x1ul << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (0x1ul << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (0x1ul << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK 0x07ul /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE 0x00ul /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Transfer Error */ -#define DMAC_CHINTFLAG_TERR (0x1ul << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (0x1ul << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (0x1ul << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK 0x07ul /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE 0x00ul /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (0x1ul << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (0x1ul << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Fetch Error */ -#define DMAC_CHSTATUS_FERR (0x1ul << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK 0x07ul /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE 0x0000ul /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (0x1ul << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (0x3ul << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val 0x0ul /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val 0x1ul /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val 0x3ul /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (0x3ul << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val 0x0ul /**< \brief (DMAC_BTCTRL) No action */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val 0x1ul /**< \brief (DMAC_BTCTRL) Channel in normal operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val 0x2ul /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val 0x3ul /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (0x3ul << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val 0x0ul /**< \brief (DMAC_BTCTRL) 8-bit access */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val 0x1ul /**< \brief (DMAC_BTCTRL) 16-bit access */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val 0x2ul /**< \brief (DMAC_BTCTRL) 32-bit access */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (0x1ul << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (0x1ul << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (0x1ul << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val 0x0ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val 0x1ul /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (0x7ul << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val 0x0ul /**< \brief (DMAC_BTCTRL) Next ADDR <- ADDR + (1<Atmel Support - */ - -#ifndef _SAMD21E15A_PIO_ -#define _SAMD21E15A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E15A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h deleted file mode 100644 index 1ab51260fc45b..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15b.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15B_PIO_ -#define _SAMD21E15B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E15B_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h deleted file mode 100644 index 7fdf91adbf47c..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15bu.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E15BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15BU_PIO_ -#define _SAMD21E15BU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E15BU_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h deleted file mode 100644 index 3938fd62b2402..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e15l.h +++ /dev/null @@ -1,620 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E15L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15L_PIO_ -#define _SAMD21E15L_PIO_ - -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for AC1 peripheral ========== */ -#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */ -#define MUX_PB04B_AC1_AIN0 1L -#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0) -#define PORT_PB04B_AC1_AIN0 (1ul << 4) -#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */ -#define MUX_PB05B_AC1_AIN1 1L -#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1) -#define PORT_PB05B_AC1_AIN1 (1ul << 5) -#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */ -#define MUX_PB02B_AC1_AIN2 1L -#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2) -#define PORT_PB02B_AC1_AIN2 (1ul << 2) -#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */ -#define MUX_PB03B_AC1_AIN3 1L -#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3) -#define PORT_PB03B_AC1_AIN3 (1ul << 3) -#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */ -#define MUX_PA24H_AC1_CMP0 7L -#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0) -#define PORT_PA24H_AC1_CMP0 (1ul << 24) -#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */ -#define MUX_PA25H_AC1_CMP1 7L -#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1) -#define PORT_PA25H_AC1_CMP1 (1ul << 25) - -#endif /* _SAMD21E15L_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h deleted file mode 100644 index 8ebe8bbed7c14..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16a.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E16A_PIO_ -#define _SAMD21E16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E16A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h deleted file mode 100644 index 0a12729b3915e..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16b.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16B_PIO_ -#define _SAMD21E16B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E16B_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h deleted file mode 100644 index ab890b5cc6eee..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16bu.h +++ /dev/null @@ -1,641 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16BU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16BU_PIO_ -#define _SAMD21E16BU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E16BU_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h deleted file mode 100644 index 85ac1e76eba69..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e16l.h +++ /dev/null @@ -1,620 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E16L - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16L_PIO_ -#define _SAMD21E16L_PIO_ - -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for AC1 peripheral ========== */ -#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */ -#define MUX_PB04B_AC1_AIN0 1L -#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0) -#define PORT_PB04B_AC1_AIN0 (1ul << 4) -#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */ -#define MUX_PB05B_AC1_AIN1 1L -#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1) -#define PORT_PB05B_AC1_AIN1 (1ul << 5) -#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */ -#define MUX_PB02B_AC1_AIN2 1L -#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2) -#define PORT_PB02B_AC1_AIN2 (1ul << 2) -#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */ -#define MUX_PB03B_AC1_AIN3 1L -#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3) -#define PORT_PB03B_AC1_AIN3 (1ul << 3) -#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */ -#define MUX_PA24H_AC1_CMP0 7L -#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0) -#define PORT_PA24H_AC1_CMP0 (1ul << 24) -#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */ -#define MUX_PA25H_AC1_CMP1 7L -#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1) -#define PORT_PA25H_AC1_CMP1 (1ul << 25) - -#endif /* _SAMD21E16L_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h deleted file mode 100644 index cced9bdc93d3f..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e17a.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E17A_PIO_ -#define _SAMD21E17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E17A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h deleted file mode 100644 index fa4b94953a346..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21e18a.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21E18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21E18A_PIO_ -#define _SAMD21E18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21E18A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h deleted file mode 100644 index 9c29c035bf2c7..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G15A_PIO_ -#define _SAMD21G15A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G15A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h deleted file mode 100644 index be61191bb55d2..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15b.h +++ /dev/null @@ -1,915 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15B_PIO_ -#define _SAMD21G15B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G15B_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h deleted file mode 100644 index 2a3133ca71603..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g15l.h +++ /dev/null @@ -1,904 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G15L - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15L_PIO_ -#define _SAMD21G15L_PIO_ - -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for AC1 peripheral ========== */ -#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */ -#define MUX_PB04B_AC1_AIN0 1L -#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0) -#define PORT_PB04B_AC1_AIN0 (1ul << 4) -#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */ -#define MUX_PB05B_AC1_AIN1 1L -#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1) -#define PORT_PB05B_AC1_AIN1 (1ul << 5) -#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */ -#define MUX_PB02B_AC1_AIN2 1L -#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2) -#define PORT_PB02B_AC1_AIN2 (1ul << 2) -#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */ -#define MUX_PB03B_AC1_AIN3 1L -#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3) -#define PORT_PB03B_AC1_AIN3 (1ul << 3) -#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */ -#define MUX_PA24H_AC1_CMP0 7L -#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0) -#define PORT_PA24H_AC1_CMP0 (1ul << 24) -#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */ -#define MUX_PA25H_AC1_CMP1 7L -#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1) -#define PORT_PA25H_AC1_CMP1 (1ul << 25) - -#endif /* _SAMD21G15L_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h deleted file mode 100644 index c5781d9119a0d..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G16A_PIO_ -#define _SAMD21G16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G16A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h deleted file mode 100644 index 0c86fcc9b3d00..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16b.h +++ /dev/null @@ -1,915 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16B_PIO_ -#define _SAMD21G16B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G16B_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h deleted file mode 100644 index e46e4132c01c2..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g16l.h +++ /dev/null @@ -1,904 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G16L - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16L_PIO_ -#define _SAMD21G16L_PIO_ - -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for AC1 peripheral ========== */ -#define PIN_PB04B_AC1_AIN0 36L /**< \brief AC1 signal: AIN0 on PB04 mux B */ -#define MUX_PB04B_AC1_AIN0 1L -#define PINMUX_PB04B_AC1_AIN0 ((PIN_PB04B_AC1_AIN0 << 16) | MUX_PB04B_AC1_AIN0) -#define PORT_PB04B_AC1_AIN0 (1ul << 4) -#define PIN_PB05B_AC1_AIN1 37L /**< \brief AC1 signal: AIN1 on PB05 mux B */ -#define MUX_PB05B_AC1_AIN1 1L -#define PINMUX_PB05B_AC1_AIN1 ((PIN_PB05B_AC1_AIN1 << 16) | MUX_PB05B_AC1_AIN1) -#define PORT_PB05B_AC1_AIN1 (1ul << 5) -#define PIN_PB02B_AC1_AIN2 34L /**< \brief AC1 signal: AIN2 on PB02 mux B */ -#define MUX_PB02B_AC1_AIN2 1L -#define PINMUX_PB02B_AC1_AIN2 ((PIN_PB02B_AC1_AIN2 << 16) | MUX_PB02B_AC1_AIN2) -#define PORT_PB02B_AC1_AIN2 (1ul << 2) -#define PIN_PB03B_AC1_AIN3 35L /**< \brief AC1 signal: AIN3 on PB03 mux B */ -#define MUX_PB03B_AC1_AIN3 1L -#define PINMUX_PB03B_AC1_AIN3 ((PIN_PB03B_AC1_AIN3 << 16) | MUX_PB03B_AC1_AIN3) -#define PORT_PB03B_AC1_AIN3 (1ul << 3) -#define PIN_PA24H_AC1_CMP0 24L /**< \brief AC1 signal: CMP0 on PA24 mux H */ -#define MUX_PA24H_AC1_CMP0 7L -#define PINMUX_PA24H_AC1_CMP0 ((PIN_PA24H_AC1_CMP0 << 16) | MUX_PA24H_AC1_CMP0) -#define PORT_PA24H_AC1_CMP0 (1ul << 24) -#define PIN_PA25H_AC1_CMP1 25L /**< \brief AC1 signal: CMP1 on PA25 mux H */ -#define MUX_PA25H_AC1_CMP1 7L -#define PINMUX_PA25H_AC1_CMP1 ((PIN_PA25H_AC1_CMP1 << 16) | MUX_PA25H_AC1_CMP1) -#define PORT_PA25H_AC1_CMP1 (1ul << 25) - -#endif /* _SAMD21G16L_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h deleted file mode 100644 index 6bf8421f8a41b..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g17a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G17A_PIO_ -#define _SAMD21G17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G17A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h deleted file mode 100644 index 4515df062548f..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g17au.h +++ /dev/null @@ -1,866 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G17AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G17AU_PIO_ -#define _SAMD21G17AU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G17AU_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h deleted file mode 100644 index 06605fadf9499..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g18a.h +++ /dev/null @@ -1,918 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G18A_PIO_ -#define _SAMD21G18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G18A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h deleted file mode 100644 index f4ff76b1d9807..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21g18au.h +++ /dev/null @@ -1,866 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21G18AU - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - /* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21G18AU_PIO_ -#define _SAMD21G18AU_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) - -#endif /* _SAMD21G18AU_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h deleted file mode 100644 index e113f94d7ce92..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j15a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J15A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J15A_PIO_ -#define _SAMD21J15A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J15A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h deleted file mode 100644 index d0056e08b4f2a..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j15b.h +++ /dev/null @@ -1,1189 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J15B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15B_PIO_ -#define _SAMD21J15B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J15B_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h deleted file mode 100644 index fe330c4dff4a1..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j16a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J16A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J16A_PIO_ -#define _SAMD21J16A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J16A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h deleted file mode 100644 index 1628f5b2a7aba..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j16b.h +++ /dev/null @@ -1,1189 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J16B - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16B_PIO_ -#define _SAMD21J16B_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J16B_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h deleted file mode 100644 index 990f75fef477b..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j17a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J17A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J17A_PIO_ -#define _SAMD21J17A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J17A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h deleted file mode 100644 index 4ca3810cb2b56..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/pio/samd21j18a.h +++ /dev/null @@ -1,1192 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD21J18A - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21J18A_PIO_ -#define _SAMD21J18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (1ul << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (1ul << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (1ul << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (1ul << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (1ul << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (1ul << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (1ul << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (1ul << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (1ul << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (1ul << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (1ul << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (1ul << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (1ul << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (1ul << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (1ul << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (1ul << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (1ul << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (1ul << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (1ul << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (1ul << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (1ul << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (1ul << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (1ul << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (1ul << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (1ul << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (1ul << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (1ul << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA28 28 /**< \brief Pin Number for PA28 */ -#define PORT_PA28 (1ul << 28) /**< \brief PORT Mask for PA28 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (1ul << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (1ul << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (1ul << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (1ul << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (1ul << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (1ul << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (1ul << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (1ul << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (1ul << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (1ul << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (1ul << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (1ul << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (1ul << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (1ul << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (1ul << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (1ul << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (1ul << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (1ul << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (1ul << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (1ul << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (1ul << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (1ul << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (1ul << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (1ul << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PB14H_GCLK_IO0 46L /**< \brief GCLK signal: IO0 on PB14 mux H */ -#define MUX_PB14H_GCLK_IO0 7L -#define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) -#define PORT_PB14H_GCLK_IO0 (1ul << 14) -#define PIN_PB22H_GCLK_IO0 54L /**< \brief GCLK signal: IO0 on PB22 mux H */ -#define MUX_PB22H_GCLK_IO0 7L -#define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) -#define PORT_PB22H_GCLK_IO0 (1ul << 22) -#define PIN_PA14H_GCLK_IO0 14L /**< \brief GCLK signal: IO0 on PA14 mux H */ -#define MUX_PA14H_GCLK_IO0 7L -#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) -#define PORT_PA14H_GCLK_IO0 (1ul << 14) -#define PIN_PA27H_GCLK_IO0 27L /**< \brief GCLK signal: IO0 on PA27 mux H */ -#define MUX_PA27H_GCLK_IO0 7L -#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) -#define PORT_PA27H_GCLK_IO0 (1ul << 27) -#define PIN_PA28H_GCLK_IO0 28L /**< \brief GCLK signal: IO0 on PA28 mux H */ -#define MUX_PA28H_GCLK_IO0 7L -#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) -#define PORT_PA28H_GCLK_IO0 (1ul << 28) -#define PIN_PA30H_GCLK_IO0 30L /**< \brief GCLK signal: IO0 on PA30 mux H */ -#define MUX_PA30H_GCLK_IO0 7L -#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) -#define PORT_PA30H_GCLK_IO0 (1ul << 30) -#define PIN_PB15H_GCLK_IO1 47L /**< \brief GCLK signal: IO1 on PB15 mux H */ -#define MUX_PB15H_GCLK_IO1 7L -#define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) -#define PORT_PB15H_GCLK_IO1 (1ul << 15) -#define PIN_PB23H_GCLK_IO1 55L /**< \brief GCLK signal: IO1 on PB23 mux H */ -#define MUX_PB23H_GCLK_IO1 7L -#define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) -#define PORT_PB23H_GCLK_IO1 (1ul << 23) -#define PIN_PA15H_GCLK_IO1 15L /**< \brief GCLK signal: IO1 on PA15 mux H */ -#define MUX_PA15H_GCLK_IO1 7L -#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) -#define PORT_PA15H_GCLK_IO1 (1ul << 15) -#define PIN_PB16H_GCLK_IO2 48L /**< \brief GCLK signal: IO2 on PB16 mux H */ -#define MUX_PB16H_GCLK_IO2 7L -#define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) -#define PORT_PB16H_GCLK_IO2 (1ul << 16) -#define PIN_PA16H_GCLK_IO2 16L /**< \brief GCLK signal: IO2 on PA16 mux H */ -#define MUX_PA16H_GCLK_IO2 7L -#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) -#define PORT_PA16H_GCLK_IO2 (1ul << 16) -#define PIN_PA17H_GCLK_IO3 17L /**< \brief GCLK signal: IO3 on PA17 mux H */ -#define MUX_PA17H_GCLK_IO3 7L -#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) -#define PORT_PA17H_GCLK_IO3 (1ul << 17) -#define PIN_PB17H_GCLK_IO3 49L /**< \brief GCLK signal: IO3 on PB17 mux H */ -#define MUX_PB17H_GCLK_IO3 7L -#define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) -#define PORT_PB17H_GCLK_IO3 (1ul << 17) -#define PIN_PA10H_GCLK_IO4 10L /**< \brief GCLK signal: IO4 on PA10 mux H */ -#define MUX_PA10H_GCLK_IO4 7L -#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) -#define PORT_PA10H_GCLK_IO4 (1ul << 10) -#define PIN_PA20H_GCLK_IO4 20L /**< \brief GCLK signal: IO4 on PA20 mux H */ -#define MUX_PA20H_GCLK_IO4 7L -#define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) -#define PORT_PA20H_GCLK_IO4 (1ul << 20) -#define PIN_PB10H_GCLK_IO4 42L /**< \brief GCLK signal: IO4 on PB10 mux H */ -#define MUX_PB10H_GCLK_IO4 7L -#define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) -#define PORT_PB10H_GCLK_IO4 (1ul << 10) -#define PIN_PA11H_GCLK_IO5 11L /**< \brief GCLK signal: IO5 on PA11 mux H */ -#define MUX_PA11H_GCLK_IO5 7L -#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) -#define PORT_PA11H_GCLK_IO5 (1ul << 11) -#define PIN_PA21H_GCLK_IO5 21L /**< \brief GCLK signal: IO5 on PA21 mux H */ -#define MUX_PA21H_GCLK_IO5 7L -#define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) -#define PORT_PA21H_GCLK_IO5 (1ul << 21) -#define PIN_PB11H_GCLK_IO5 43L /**< \brief GCLK signal: IO5 on PB11 mux H */ -#define MUX_PB11H_GCLK_IO5 7L -#define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) -#define PORT_PB11H_GCLK_IO5 (1ul << 11) -#define PIN_PA22H_GCLK_IO6 22L /**< \brief GCLK signal: IO6 on PA22 mux H */ -#define MUX_PA22H_GCLK_IO6 7L -#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) -#define PORT_PA22H_GCLK_IO6 (1ul << 22) -#define PIN_PB12H_GCLK_IO6 44L /**< \brief GCLK signal: IO6 on PB12 mux H */ -#define MUX_PB12H_GCLK_IO6 7L -#define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) -#define PORT_PB12H_GCLK_IO6 (1ul << 12) -#define PIN_PA23H_GCLK_IO7 23L /**< \brief GCLK signal: IO7 on PA23 mux H */ -#define MUX_PA23H_GCLK_IO7 7L -#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) -#define PORT_PA23H_GCLK_IO7 (1ul << 23) -#define PIN_PB13H_GCLK_IO7 45L /**< \brief GCLK signal: IO7 on PB13 mux H */ -#define MUX_PB13H_GCLK_IO7 7L -#define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) -#define PORT_PB13H_GCLK_IO7 (1ul << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA16A_EIC_EXTINT0 16L /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 0L -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PB00A_EIC_EXTINT0 32L /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 0L -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PB16A_EIC_EXTINT0 48L /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 0L -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (1ul << 16) -#define PIN_PA00A_EIC_EXTINT0 0L /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 0L -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (1ul << 0) -#define PIN_PA17A_EIC_EXTINT1 17L /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 0L -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PB01A_EIC_EXTINT1 33L /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 0L -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PB17A_EIC_EXTINT1 49L /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 0L -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (1ul << 17) -#define PIN_PA01A_EIC_EXTINT1 1L /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 0L -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (1ul << 1) -#define PIN_PA18A_EIC_EXTINT2 18L /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 0L -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (1ul << 18) -#define PIN_PA02A_EIC_EXTINT2 2L /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 0L -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PB02A_EIC_EXTINT2 34L /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 0L -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (1ul << 2) -#define PIN_PA03A_EIC_EXTINT3 3L /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 0L -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA19A_EIC_EXTINT3 19L /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 0L -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (1ul << 19) -#define PIN_PB03A_EIC_EXTINT3 35L /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 0L -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (1ul << 3) -#define PIN_PA04A_EIC_EXTINT4 4L /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 0L -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA20A_EIC_EXTINT4 20L /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 0L -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (1ul << 20) -#define PIN_PB04A_EIC_EXTINT4 36L /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 0L -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (1ul << 4) -#define PIN_PA05A_EIC_EXTINT5 5L /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 0L -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA21A_EIC_EXTINT5 21L /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 0L -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (1ul << 21) -#define PIN_PB05A_EIC_EXTINT5 37L /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 0L -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (1ul << 5) -#define PIN_PA06A_EIC_EXTINT6 6L /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 0L -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PA22A_EIC_EXTINT6 22L /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 0L -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PB06A_EIC_EXTINT6 38L /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 0L -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (1ul << 6) -#define PIN_PB22A_EIC_EXTINT6 54L /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 0L -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (1ul << 22) -#define PIN_PA07A_EIC_EXTINT7 7L /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 0L -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PA23A_EIC_EXTINT7 23L /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 0L -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PB07A_EIC_EXTINT7 39L /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 0L -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (1ul << 7) -#define PIN_PB23A_EIC_EXTINT7 55L /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 0L -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (1ul << 23) -#define PIN_PA28A_EIC_EXTINT8 28L /**< \brief EIC signal: EXTINT8 on PA28 mux A */ -#define MUX_PA28A_EIC_EXTINT8 0L -#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) -#define PORT_PA28A_EIC_EXTINT8 (1ul << 28) -#define PIN_PB08A_EIC_EXTINT8 40L /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 0L -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (1ul << 8) -#define PIN_PA09A_EIC_EXTINT9 9L /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 0L -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PB09A_EIC_EXTINT9 41L /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 0L -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (1ul << 9) -#define PIN_PA10A_EIC_EXTINT10 10L /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 0L -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA30A_EIC_EXTINT10 30L /**< \brief EIC signal: EXTINT10 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT10 0L -#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) -#define PORT_PA30A_EIC_EXTINT10 (1ul << 30) -#define PIN_PB10A_EIC_EXTINT10 42L /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 0L -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (1ul << 10) -#define PIN_PA11A_EIC_EXTINT11 11L /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 0L -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA31A_EIC_EXTINT11 31L /**< \brief EIC signal: EXTINT11 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT11 0L -#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) -#define PORT_PA31A_EIC_EXTINT11 (1ul << 31) -#define PIN_PB11A_EIC_EXTINT11 43L /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 0L -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (1ul << 11) -#define PIN_PA12A_EIC_EXTINT12 12L /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 0L -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA24A_EIC_EXTINT12 24L /**< \brief EIC signal: EXTINT12 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT12 0L -#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) -#define PORT_PA24A_EIC_EXTINT12 (1ul << 24) -#define PIN_PB12A_EIC_EXTINT12 44L /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 0L -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (1ul << 12) -#define PIN_PA13A_EIC_EXTINT13 13L /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 0L -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PA25A_EIC_EXTINT13 25L /**< \brief EIC signal: EXTINT13 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT13 0L -#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) -#define PORT_PA25A_EIC_EXTINT13 (1ul << 25) -#define PIN_PB13A_EIC_EXTINT13 45L /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 0L -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (1ul << 13) -#define PIN_PB14A_EIC_EXTINT14 46L /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 0L -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PB30A_EIC_EXTINT14 62L /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 0L -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (1ul << 30) -#define PIN_PA14A_EIC_EXTINT14 14L /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 0L -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (1ul << 14) -#define PIN_PA15A_EIC_EXTINT15 15L /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 0L -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PA27A_EIC_EXTINT15 27L /**< \brief EIC signal: EXTINT15 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT15 0L -#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) -#define PORT_PA27A_EIC_EXTINT15 (1ul << 27) -#define PIN_PB15A_EIC_EXTINT15 47L /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 0L -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (1ul << 15) -#define PIN_PB31A_EIC_EXTINT15 63L /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 0L -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (1ul << 31) -#define PIN_PA08A_EIC_NMI 8L /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI 0L -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (1ul << 8) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24G_USB_DM 24L /**< \brief USB signal: DM on PA24 mux G */ -#define MUX_PA24G_USB_DM 6L -#define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) -#define PORT_PA24G_USB_DM (1ul << 24) -#define PIN_PA25G_USB_DP 25L /**< \brief USB signal: DP on PA25 mux G */ -#define MUX_PA25G_USB_DP 6L -#define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) -#define PORT_PA25G_USB_DP (1ul << 25) -#define PIN_PA23G_USB_SOF_1KHZ 23L /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ -#define MUX_PA23G_USB_SOF_1KHZ 6L -#define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) -#define PORT_PA23G_USB_SOF_1KHZ (1ul << 23) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 4L /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 3L -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (1ul << 4) -#define PIN_PA08C_SERCOM0_PAD0 8L /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 2L -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (1ul << 8) -#define PIN_PA05D_SERCOM0_PAD1 5L /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 3L -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (1ul << 5) -#define PIN_PA09C_SERCOM0_PAD1 9L /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 2L -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (1ul << 9) -#define PIN_PA06D_SERCOM0_PAD2 6L /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 3L -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (1ul << 6) -#define PIN_PA10C_SERCOM0_PAD2 10L /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 2L -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (1ul << 10) -#define PIN_PA07D_SERCOM0_PAD3 7L /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 3L -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (1ul << 7) -#define PIN_PA11C_SERCOM0_PAD3 11L /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 2L -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (1ul << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA16C_SERCOM1_PAD0 16L /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 2L -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (1ul << 16) -#define PIN_PA00D_SERCOM1_PAD0 0L /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 3L -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (1ul << 0) -#define PIN_PA17C_SERCOM1_PAD1 17L /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 2L -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (1ul << 17) -#define PIN_PA01D_SERCOM1_PAD1 1L /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 3L -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (1ul << 1) -#define PIN_PA30D_SERCOM1_PAD2 30L /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 3L -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (1ul << 30) -#define PIN_PA18C_SERCOM1_PAD2 18L /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 2L -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (1ul << 18) -#define PIN_PA31D_SERCOM1_PAD3 31L /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 3L -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (1ul << 31) -#define PIN_PA19C_SERCOM1_PAD3 19L /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 2L -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (1ul << 19) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA08D_SERCOM2_PAD0 8L /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD0 3L -#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) -#define PORT_PA08D_SERCOM2_PAD0 (1ul << 8) -#define PIN_PA12C_SERCOM2_PAD0 12L /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 2L -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (1ul << 12) -#define PIN_PA09D_SERCOM2_PAD1 9L /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD1 3L -#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) -#define PORT_PA09D_SERCOM2_PAD1 (1ul << 9) -#define PIN_PA13C_SERCOM2_PAD1 13L /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 2L -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (1ul << 13) -#define PIN_PA10D_SERCOM2_PAD2 10L /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 3L -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (1ul << 10) -#define PIN_PA14C_SERCOM2_PAD2 14L /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 2L -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (1ul << 14) -#define PIN_PA11D_SERCOM2_PAD3 11L /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 3L -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (1ul << 11) -#define PIN_PA15C_SERCOM2_PAD3 15L /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 2L -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA16D_SERCOM3_PAD0 16L /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD0 3L -#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) -#define PORT_PA16D_SERCOM3_PAD0 (1ul << 16) -#define PIN_PA22C_SERCOM3_PAD0 22L /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 2L -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (1ul << 22) -#define PIN_PA17D_SERCOM3_PAD1 17L /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD1 3L -#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) -#define PORT_PA17D_SERCOM3_PAD1 (1ul << 17) -#define PIN_PA23C_SERCOM3_PAD1 23L /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 2L -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (1ul << 23) -#define PIN_PA18D_SERCOM3_PAD2 18L /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 3L -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (1ul << 18) -#define PIN_PA20D_SERCOM3_PAD2 20L /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 3L -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (1ul << 20) -#define PIN_PA24C_SERCOM3_PAD2 24L /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 2L -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (1ul << 24) -#define PIN_PA19D_SERCOM3_PAD3 19L /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 3L -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (1ul << 19) -#define PIN_PA21D_SERCOM3_PAD3 21L /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 3L -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (1ul << 21) -#define PIN_PA25C_SERCOM3_PAD3 25L /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 2L -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (1ul << 25) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA12D_SERCOM4_PAD0 12L /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD0 3L -#define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) -#define PORT_PA12D_SERCOM4_PAD0 (1ul << 12) -#define PIN_PB08D_SERCOM4_PAD0 40L /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 3L -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (1ul << 8) -#define PIN_PB12C_SERCOM4_PAD0 44L /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 2L -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (1ul << 12) -#define PIN_PA13D_SERCOM4_PAD1 13L /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD1 3L -#define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) -#define PORT_PA13D_SERCOM4_PAD1 (1ul << 13) -#define PIN_PB09D_SERCOM4_PAD1 41L /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 3L -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (1ul << 9) -#define PIN_PB13C_SERCOM4_PAD1 45L /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 2L -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (1ul << 13) -#define PIN_PA14D_SERCOM4_PAD2 14L /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 3L -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (1ul << 14) -#define PIN_PB10D_SERCOM4_PAD2 42L /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 3L -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (1ul << 10) -#define PIN_PB14C_SERCOM4_PAD2 46L /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 2L -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (1ul << 14) -#define PIN_PA15D_SERCOM4_PAD3 15L /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 3L -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (1ul << 15) -#define PIN_PB11D_SERCOM4_PAD3 43L /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 3L -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (1ul << 11) -#define PIN_PB15C_SERCOM4_PAD3 47L /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 2L -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (1ul << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PB16C_SERCOM5_PAD0 48L /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 2L -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (1ul << 16) -#define PIN_PA22D_SERCOM5_PAD0 22L /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD0 3L -#define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) -#define PORT_PA22D_SERCOM5_PAD0 (1ul << 22) -#define PIN_PB02D_SERCOM5_PAD0 34L /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 3L -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (1ul << 2) -#define PIN_PB30D_SERCOM5_PAD0 62L /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD0 3L -#define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) -#define PORT_PB30D_SERCOM5_PAD0 (1ul << 30) -#define PIN_PB17C_SERCOM5_PAD1 49L /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 2L -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (1ul << 17) -#define PIN_PA23D_SERCOM5_PAD1 23L /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD1 3L -#define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) -#define PORT_PA23D_SERCOM5_PAD1 (1ul << 23) -#define PIN_PB03D_SERCOM5_PAD1 35L /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 3L -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (1ul << 3) -#define PIN_PB31D_SERCOM5_PAD1 63L /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD1 3L -#define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) -#define PORT_PB31D_SERCOM5_PAD1 (1ul << 31) -#define PIN_PA24D_SERCOM5_PAD2 24L /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 3L -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (1ul << 24) -#define PIN_PB00D_SERCOM5_PAD2 32L /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 3L -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (1ul << 0) -#define PIN_PB22D_SERCOM5_PAD2 54L /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 3L -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (1ul << 22) -#define PIN_PA20C_SERCOM5_PAD2 20L /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 2L -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (1ul << 20) -#define PIN_PA25D_SERCOM5_PAD3 25L /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 3L -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (1ul << 25) -#define PIN_PB01D_SERCOM5_PAD3 33L /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 3L -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (1ul << 1) -#define PIN_PB23D_SERCOM5_PAD3 55L /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 3L -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (1ul << 23) -#define PIN_PA21C_SERCOM5_PAD3 21L /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 2L -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (1ul << 21) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA04E_TCC0_WO0 4L /**< \brief TCC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TCC0_WO0 4L -#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) -#define PORT_PA04E_TCC0_WO0 (1ul << 4) -#define PIN_PA08E_TCC0_WO0 8L /**< \brief TCC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TCC0_WO0 4L -#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) -#define PORT_PA08E_TCC0_WO0 (1ul << 8) -#define PIN_PB30E_TCC0_WO0 62L /**< \brief TCC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TCC0_WO0 4L -#define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) -#define PORT_PB30E_TCC0_WO0 (1ul << 30) -#define PIN_PA05E_TCC0_WO1 5L /**< \brief TCC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TCC0_WO1 4L -#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) -#define PORT_PA05E_TCC0_WO1 (1ul << 5) -#define PIN_PA09E_TCC0_WO1 9L /**< \brief TCC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TCC0_WO1 4L -#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) -#define PORT_PA09E_TCC0_WO1 (1ul << 9) -#define PIN_PB31E_TCC0_WO1 63L /**< \brief TCC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TCC0_WO1 4L -#define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) -#define PORT_PB31E_TCC0_WO1 (1ul << 31) -#define PIN_PA10F_TCC0_WO2 10L /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 5L -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (1ul << 10) -#define PIN_PA18F_TCC0_WO2 18L /**< \brief TCC0 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC0_WO2 5L -#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) -#define PORT_PA18F_TCC0_WO2 (1ul << 18) -#define PIN_PA11F_TCC0_WO3 11L /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 5L -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (1ul << 11) -#define PIN_PA19F_TCC0_WO3 19L /**< \brief TCC0 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC0_WO3 5L -#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) -#define PORT_PA19F_TCC0_WO3 (1ul << 19) -#define PIN_PA14F_TCC0_WO4 14L /**< \brief TCC0 signal: WO4 on PA14 mux F */ -#define MUX_PA14F_TCC0_WO4 5L -#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) -#define PORT_PA14F_TCC0_WO4 (1ul << 14) -#define PIN_PA22F_TCC0_WO4 22L /**< \brief TCC0 signal: WO4 on PA22 mux F */ -#define MUX_PA22F_TCC0_WO4 5L -#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) -#define PORT_PA22F_TCC0_WO4 (1ul << 22) -#define PIN_PB10F_TCC0_WO4 42L /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 5L -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (1ul << 10) -#define PIN_PB16F_TCC0_WO4 48L /**< \brief TCC0 signal: WO4 on PB16 mux F */ -#define MUX_PB16F_TCC0_WO4 5L -#define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) -#define PORT_PB16F_TCC0_WO4 (1ul << 16) -#define PIN_PA15F_TCC0_WO5 15L /**< \brief TCC0 signal: WO5 on PA15 mux F */ -#define MUX_PA15F_TCC0_WO5 5L -#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) -#define PORT_PA15F_TCC0_WO5 (1ul << 15) -#define PIN_PA23F_TCC0_WO5 23L /**< \brief TCC0 signal: WO5 on PA23 mux F */ -#define MUX_PA23F_TCC0_WO5 5L -#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) -#define PORT_PA23F_TCC0_WO5 (1ul << 23) -#define PIN_PB11F_TCC0_WO5 43L /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 5L -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (1ul << 11) -#define PIN_PB17F_TCC0_WO5 49L /**< \brief TCC0 signal: WO5 on PB17 mux F */ -#define MUX_PB17F_TCC0_WO5 5L -#define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) -#define PORT_PB17F_TCC0_WO5 (1ul << 17) -#define PIN_PA12F_TCC0_WO6 12L /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 5L -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (1ul << 12) -#define PIN_PA20F_TCC0_WO6 20L /**< \brief TCC0 signal: WO6 on PA20 mux F */ -#define MUX_PA20F_TCC0_WO6 5L -#define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) -#define PORT_PA20F_TCC0_WO6 (1ul << 20) -#define PIN_PB12F_TCC0_WO6 44L /**< \brief TCC0 signal: WO6 on PB12 mux F */ -#define MUX_PB12F_TCC0_WO6 5L -#define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) -#define PORT_PB12F_TCC0_WO6 (1ul << 12) -#define PIN_PA16F_TCC0_WO6 16L /**< \brief TCC0 signal: WO6 on PA16 mux F */ -#define MUX_PA16F_TCC0_WO6 5L -#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) -#define PORT_PA16F_TCC0_WO6 (1ul << 16) -#define PIN_PA13F_TCC0_WO7 13L /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 5L -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (1ul << 13) -#define PIN_PA21F_TCC0_WO7 21L /**< \brief TCC0 signal: WO7 on PA21 mux F */ -#define MUX_PA21F_TCC0_WO7 5L -#define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) -#define PORT_PA21F_TCC0_WO7 (1ul << 21) -#define PIN_PB13F_TCC0_WO7 45L /**< \brief TCC0 signal: WO7 on PB13 mux F */ -#define MUX_PB13F_TCC0_WO7 5L -#define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) -#define PORT_PB13F_TCC0_WO7 (1ul << 13) -#define PIN_PA17F_TCC0_WO7 17L /**< \brief TCC0 signal: WO7 on PA17 mux F */ -#define MUX_PA17F_TCC0_WO7 5L -#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) -#define PORT_PA17F_TCC0_WO7 (1ul << 17) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PA06E_TCC1_WO0 6L /**< \brief TCC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TCC1_WO0 4L -#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) -#define PORT_PA06E_TCC1_WO0 (1ul << 6) -#define PIN_PA10E_TCC1_WO0 10L /**< \brief TCC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TCC1_WO0 4L -#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) -#define PORT_PA10E_TCC1_WO0 (1ul << 10) -#define PIN_PA30E_TCC1_WO0 30L /**< \brief TCC1 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TCC1_WO0 4L -#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) -#define PORT_PA30E_TCC1_WO0 (1ul << 30) -#define PIN_PA07E_TCC1_WO1 7L /**< \brief TCC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TCC1_WO1 4L -#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) -#define PORT_PA07E_TCC1_WO1 (1ul << 7) -#define PIN_PA11E_TCC1_WO1 11L /**< \brief TCC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TCC1_WO1 4L -#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) -#define PORT_PA11E_TCC1_WO1 (1ul << 11) -#define PIN_PA31E_TCC1_WO1 31L /**< \brief TCC1 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TCC1_WO1 4L -#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) -#define PORT_PA31E_TCC1_WO1 (1ul << 31) -#define PIN_PA08F_TCC1_WO2 8L /**< \brief TCC1 signal: WO2 on PA08 mux F */ -#define MUX_PA08F_TCC1_WO2 5L -#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) -#define PORT_PA08F_TCC1_WO2 (1ul << 8) -#define PIN_PA24F_TCC1_WO2 24L /**< \brief TCC1 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC1_WO2 5L -#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) -#define PORT_PA24F_TCC1_WO2 (1ul << 24) -#define PIN_PB30F_TCC1_WO2 62L /**< \brief TCC1 signal: WO2 on PB30 mux F */ -#define MUX_PB30F_TCC1_WO2 5L -#define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) -#define PORT_PB30F_TCC1_WO2 (1ul << 30) -#define PIN_PA09F_TCC1_WO3 9L /**< \brief TCC1 signal: WO3 on PA09 mux F */ -#define MUX_PA09F_TCC1_WO3 5L -#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) -#define PORT_PA09F_TCC1_WO3 (1ul << 9) -#define PIN_PA25F_TCC1_WO3 25L /**< \brief TCC1 signal: WO3 on PA25 mux F */ -#define MUX_PA25F_TCC1_WO3 5L -#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) -#define PORT_PA25F_TCC1_WO3 (1ul << 25) -#define PIN_PB31F_TCC1_WO3 63L /**< \brief TCC1 signal: WO3 on PB31 mux F */ -#define MUX_PB31F_TCC1_WO3 5L -#define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) -#define PORT_PB31F_TCC1_WO3 (1ul << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA12E_TCC2_WO0 12L /**< \brief TCC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TCC2_WO0 4L -#define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) -#define PORT_PA12E_TCC2_WO0 (1ul << 12) -#define PIN_PA16E_TCC2_WO0 16L /**< \brief TCC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TCC2_WO0 4L -#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) -#define PORT_PA16E_TCC2_WO0 (1ul << 16) -#define PIN_PA00E_TCC2_WO0 0L /**< \brief TCC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TCC2_WO0 4L -#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) -#define PORT_PA00E_TCC2_WO0 (1ul << 0) -#define PIN_PA13E_TCC2_WO1 13L /**< \brief TCC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TCC2_WO1 4L -#define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) -#define PORT_PA13E_TCC2_WO1 (1ul << 13) -#define PIN_PA17E_TCC2_WO1 17L /**< \brief TCC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TCC2_WO1 4L -#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) -#define PORT_PA17E_TCC2_WO1 (1ul << 17) -#define PIN_PA01E_TCC2_WO1 1L /**< \brief TCC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TCC2_WO1 4L -#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) -#define PORT_PA01E_TCC2_WO1 (1ul << 1) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 18L /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 4L -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (1ul << 18) -#define PIN_PA14E_TC3_WO0 14L /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 4L -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (1ul << 14) -#define PIN_PA19E_TC3_WO1 19L /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 4L -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (1ul << 19) -#define PIN_PA15E_TC3_WO1 15L /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 4L -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (1ul << 15) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 22L /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 4L -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (1ul << 22) -#define PIN_PB08E_TC4_WO0 40L /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 4L -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (1ul << 8) -#define PIN_PB12E_TC4_WO0 44L /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 4L -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (1ul << 12) -#define PIN_PA23E_TC4_WO1 23L /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 4L -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (1ul << 23) -#define PIN_PB09E_TC4_WO1 41L /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 4L -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (1ul << 9) -#define PIN_PB13E_TC4_WO1 45L /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 4L -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (1ul << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 24L /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 4L -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (1ul << 24) -#define PIN_PB10E_TC5_WO0 42L /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 4L -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (1ul << 10) -#define PIN_PB14E_TC5_WO0 46L /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 4L -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (1ul << 14) -#define PIN_PA25E_TC5_WO1 25L /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 4L -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (1ul << 25) -#define PIN_PB11E_TC5_WO1 43L /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 4L -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (1ul << 11) -#define PIN_PB15E_TC5_WO1 47L /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 4L -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (1ul << 15) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PB02E_TC6_WO0 34L /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 4L -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (1ul << 2) -#define PIN_PB16E_TC6_WO0 48L /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 4L -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (1ul << 16) -#define PIN_PB03E_TC6_WO1 35L /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 4L -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (1ul << 3) -#define PIN_PB17E_TC6_WO1 49L /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 4L -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (1ul << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 20L /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 4L -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (1ul << 20) -#define PIN_PB00E_TC7_WO0 32L /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 4L -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (1ul << 0) -#define PIN_PB22E_TC7_WO0 54L /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 4L -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (1ul << 22) -#define PIN_PA21E_TC7_WO1 21L /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 4L -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (1ul << 21) -#define PIN_PB01E_TC7_WO1 33L /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 4L -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (1ul << 1) -#define PIN_PB23E_TC7_WO1 55L /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 4L -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (1ul << 23) -/* ========== PORT definition for ADC peripheral ========== */ -#define PIN_PA02B_ADC_AIN0 2L /**< \brief ADC signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC_AIN0 1L -#define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) -#define PORT_PA02B_ADC_AIN0 (1ul << 2) -#define PIN_PA03B_ADC_AIN1 3L /**< \brief ADC signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC_AIN1 1L -#define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) -#define PORT_PA03B_ADC_AIN1 (1ul << 3) -#define PIN_PB08B_ADC_AIN2 40L /**< \brief ADC signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC_AIN2 1L -#define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) -#define PORT_PB08B_ADC_AIN2 (1ul << 8) -#define PIN_PB09B_ADC_AIN3 41L /**< \brief ADC signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC_AIN3 1L -#define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) -#define PORT_PB09B_ADC_AIN3 (1ul << 9) -#define PIN_PA04B_ADC_AIN4 4L /**< \brief ADC signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC_AIN4 1L -#define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) -#define PORT_PA04B_ADC_AIN4 (1ul << 4) -#define PIN_PA05B_ADC_AIN5 5L /**< \brief ADC signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC_AIN5 1L -#define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) -#define PORT_PA05B_ADC_AIN5 (1ul << 5) -#define PIN_PA06B_ADC_AIN6 6L /**< \brief ADC signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC_AIN6 1L -#define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) -#define PORT_PA06B_ADC_AIN6 (1ul << 6) -#define PIN_PA07B_ADC_AIN7 7L /**< \brief ADC signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC_AIN7 1L -#define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) -#define PORT_PA07B_ADC_AIN7 (1ul << 7) -#define PIN_PB00B_ADC_AIN8 32L /**< \brief ADC signal: AIN8 on PB00 mux B */ -#define MUX_PB00B_ADC_AIN8 1L -#define PINMUX_PB00B_ADC_AIN8 ((PIN_PB00B_ADC_AIN8 << 16) | MUX_PB00B_ADC_AIN8) -#define PORT_PB00B_ADC_AIN8 (1ul << 0) -#define PIN_PB01B_ADC_AIN9 33L /**< \brief ADC signal: AIN9 on PB01 mux B */ -#define MUX_PB01B_ADC_AIN9 1L -#define PINMUX_PB01B_ADC_AIN9 ((PIN_PB01B_ADC_AIN9 << 16) | MUX_PB01B_ADC_AIN9) -#define PORT_PB01B_ADC_AIN9 (1ul << 1) -#define PIN_PB02B_ADC_AIN10 34L /**< \brief ADC signal: AIN10 on PB02 mux B */ -#define MUX_PB02B_ADC_AIN10 1L -#define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) -#define PORT_PB02B_ADC_AIN10 (1ul << 2) -#define PIN_PB03B_ADC_AIN11 35L /**< \brief ADC signal: AIN11 on PB03 mux B */ -#define MUX_PB03B_ADC_AIN11 1L -#define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) -#define PORT_PB03B_ADC_AIN11 (1ul << 3) -#define PIN_PB04B_ADC_AIN12 36L /**< \brief ADC signal: AIN12 on PB04 mux B */ -#define MUX_PB04B_ADC_AIN12 1L -#define PINMUX_PB04B_ADC_AIN12 ((PIN_PB04B_ADC_AIN12 << 16) | MUX_PB04B_ADC_AIN12) -#define PORT_PB04B_ADC_AIN12 (1ul << 4) -#define PIN_PB05B_ADC_AIN13 37L /**< \brief ADC signal: AIN13 on PB05 mux B */ -#define MUX_PB05B_ADC_AIN13 1L -#define PINMUX_PB05B_ADC_AIN13 ((PIN_PB05B_ADC_AIN13 << 16) | MUX_PB05B_ADC_AIN13) -#define PORT_PB05B_ADC_AIN13 (1ul << 5) -#define PIN_PB06B_ADC_AIN14 38L /**< \brief ADC signal: AIN14 on PB06 mux B */ -#define MUX_PB06B_ADC_AIN14 1L -#define PINMUX_PB06B_ADC_AIN14 ((PIN_PB06B_ADC_AIN14 << 16) | MUX_PB06B_ADC_AIN14) -#define PORT_PB06B_ADC_AIN14 (1ul << 6) -#define PIN_PB07B_ADC_AIN15 39L /**< \brief ADC signal: AIN15 on PB07 mux B */ -#define MUX_PB07B_ADC_AIN15 1L -#define PINMUX_PB07B_ADC_AIN15 ((PIN_PB07B_ADC_AIN15 << 16) | MUX_PB07B_ADC_AIN15) -#define PORT_PB07B_ADC_AIN15 (1ul << 7) -#define PIN_PA08B_ADC_AIN16 8L /**< \brief ADC signal: AIN16 on PA08 mux B */ -#define MUX_PA08B_ADC_AIN16 1L -#define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) -#define PORT_PA08B_ADC_AIN16 (1ul << 8) -#define PIN_PA09B_ADC_AIN17 9L /**< \brief ADC signal: AIN17 on PA09 mux B */ -#define MUX_PA09B_ADC_AIN17 1L -#define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) -#define PORT_PA09B_ADC_AIN17 (1ul << 9) -#define PIN_PA10B_ADC_AIN18 10L /**< \brief ADC signal: AIN18 on PA10 mux B */ -#define MUX_PA10B_ADC_AIN18 1L -#define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) -#define PORT_PA10B_ADC_AIN18 (1ul << 10) -#define PIN_PA11B_ADC_AIN19 11L /**< \brief ADC signal: AIN19 on PA11 mux B */ -#define MUX_PA11B_ADC_AIN19 1L -#define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) -#define PORT_PA11B_ADC_AIN19 (1ul << 11) -#define PIN_PA04B_ADC_VREFP 4L /**< \brief ADC signal: VREFP on PA04 mux B */ -#define MUX_PA04B_ADC_VREFP 1L -#define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) -#define PORT_PA04B_ADC_VREFP (1ul << 4) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 4L /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 1L -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (1ul << 4) -#define PIN_PA05B_AC_AIN1 5L /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 1L -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (1ul << 5) -#define PIN_PA06B_AC_AIN2 6L /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 1L -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (1ul << 6) -#define PIN_PA07B_AC_AIN3 7L /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 1L -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (1ul << 7) -#define PIN_PA12H_AC_CMP0 12L /**< \brief AC signal: CMP0 on PA12 mux H */ -#define MUX_PA12H_AC_CMP0 7L -#define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) -#define PORT_PA12H_AC_CMP0 (1ul << 12) -#define PIN_PA18H_AC_CMP0 18L /**< \brief AC signal: CMP0 on PA18 mux H */ -#define MUX_PA18H_AC_CMP0 7L -#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) -#define PORT_PA18H_AC_CMP0 (1ul << 18) -#define PIN_PA13H_AC_CMP1 13L /**< \brief AC signal: CMP1 on PA13 mux H */ -#define MUX_PA13H_AC_CMP1 7L -#define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) -#define PORT_PA13H_AC_CMP1 (1ul << 13) -#define PIN_PA19H_AC_CMP1 19L /**< \brief AC signal: CMP1 on PA19 mux H */ -#define MUX_PA19H_AC_CMP1 7L -#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) -#define PORT_PA19H_AC_CMP1 (1ul << 19) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT 2L /**< \brief DAC signal: VOUT on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT 1L -#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) -#define PORT_PA02B_DAC_VOUT (1ul << 2) -#define PIN_PA03B_DAC_VREFP 3L /**< \brief DAC signal: VREFP on PA03 mux B */ -#define MUX_PA03B_DAC_VREFP 1L -#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) -#define PORT_PA03B_DAC_VREFP (1ul << 3) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA11G_I2S_FS0 11L /**< \brief I2S signal: FS0 on PA11 mux G */ -#define MUX_PA11G_I2S_FS0 6L -#define PINMUX_PA11G_I2S_FS0 ((PIN_PA11G_I2S_FS0 << 16) | MUX_PA11G_I2S_FS0) -#define PORT_PA11G_I2S_FS0 (1ul << 11) -#define PIN_PA21G_I2S_FS0 21L /**< \brief I2S signal: FS0 on PA21 mux G */ -#define MUX_PA21G_I2S_FS0 6L -#define PINMUX_PA21G_I2S_FS0 ((PIN_PA21G_I2S_FS0 << 16) | MUX_PA21G_I2S_FS0) -#define PORT_PA21G_I2S_FS0 (1ul << 21) -#define PIN_PB12G_I2S_FS1 44L /**< \brief I2S signal: FS1 on PB12 mux G */ -#define MUX_PB12G_I2S_FS1 6L -#define PINMUX_PB12G_I2S_FS1 ((PIN_PB12G_I2S_FS1 << 16) | MUX_PB12G_I2S_FS1) -#define PORT_PB12G_I2S_FS1 (1ul << 12) -#define PIN_PA09G_I2S_MCK0 9L /**< \brief I2S signal: MCK0 on PA09 mux G */ -#define MUX_PA09G_I2S_MCK0 6L -#define PINMUX_PA09G_I2S_MCK0 ((PIN_PA09G_I2S_MCK0 << 16) | MUX_PA09G_I2S_MCK0) -#define PORT_PA09G_I2S_MCK0 (1ul << 9) -#define PIN_PB17G_I2S_MCK0 49L /**< \brief I2S signal: MCK0 on PB17 mux G */ -#define MUX_PB17G_I2S_MCK0 6L -#define PINMUX_PB17G_I2S_MCK0 ((PIN_PB17G_I2S_MCK0 << 16) | MUX_PB17G_I2S_MCK0) -#define PORT_PB17G_I2S_MCK0 (1ul << 17) -#define PIN_PB10G_I2S_MCK1 42L /**< \brief I2S signal: MCK1 on PB10 mux G */ -#define MUX_PB10G_I2S_MCK1 6L -#define PINMUX_PB10G_I2S_MCK1 ((PIN_PB10G_I2S_MCK1 << 16) | MUX_PB10G_I2S_MCK1) -#define PORT_PB10G_I2S_MCK1 (1ul << 10) -#define PIN_PA10G_I2S_SCK0 10L /**< \brief I2S signal: SCK0 on PA10 mux G */ -#define MUX_PA10G_I2S_SCK0 6L -#define PINMUX_PA10G_I2S_SCK0 ((PIN_PA10G_I2S_SCK0 << 16) | MUX_PA10G_I2S_SCK0) -#define PORT_PA10G_I2S_SCK0 (1ul << 10) -#define PIN_PA20G_I2S_SCK0 20L /**< \brief I2S signal: SCK0 on PA20 mux G */ -#define MUX_PA20G_I2S_SCK0 6L -#define PINMUX_PA20G_I2S_SCK0 ((PIN_PA20G_I2S_SCK0 << 16) | MUX_PA20G_I2S_SCK0) -#define PORT_PA20G_I2S_SCK0 (1ul << 20) -#define PIN_PB11G_I2S_SCK1 43L /**< \brief I2S signal: SCK1 on PB11 mux G */ -#define MUX_PB11G_I2S_SCK1 6L -#define PINMUX_PB11G_I2S_SCK1 ((PIN_PB11G_I2S_SCK1 << 16) | MUX_PB11G_I2S_SCK1) -#define PORT_PB11G_I2S_SCK1 (1ul << 11) -#define PIN_PA07G_I2S_SD0 7L /**< \brief I2S signal: SD0 on PA07 mux G */ -#define MUX_PA07G_I2S_SD0 6L -#define PINMUX_PA07G_I2S_SD0 ((PIN_PA07G_I2S_SD0 << 16) | MUX_PA07G_I2S_SD0) -#define PORT_PA07G_I2S_SD0 (1ul << 7) -#define PIN_PA19G_I2S_SD0 19L /**< \brief I2S signal: SD0 on PA19 mux G */ -#define MUX_PA19G_I2S_SD0 6L -#define PINMUX_PA19G_I2S_SD0 ((PIN_PA19G_I2S_SD0 << 16) | MUX_PA19G_I2S_SD0) -#define PORT_PA19G_I2S_SD0 (1ul << 19) -#define PIN_PA08G_I2S_SD1 8L /**< \brief I2S signal: SD1 on PA08 mux G */ -#define MUX_PA08G_I2S_SD1 6L -#define PINMUX_PA08G_I2S_SD1 ((PIN_PA08G_I2S_SD1 << 16) | MUX_PA08G_I2S_SD1) -#define PORT_PA08G_I2S_SD1 (1ul << 8) -#define PIN_PB16G_I2S_SD1 48L /**< \brief I2S signal: SD1 on PB16 mux G */ -#define MUX_PB16G_I2S_SD1 6L -#define PINMUX_PB16G_I2S_SD1 ((PIN_PB16G_I2S_SD1 << 16) | MUX_PB16G_I2S_SD1) -#define PORT_PB16G_I2S_SD1 (1ul << 16) - -#endif /* _SAMD21J18A_PIO_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21.h deleted file mode 100644 index 2e615135aac67..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAMD21 - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAMD21_ -#define _SAMD21_ - -/** - * \defgroup SAMD21_definitions SAMD21 Device Definitions - * \brief SAMD21 CMSIS Definitions. - */ - -#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__) - #include "samd21e15a.h" -#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__) - #include "samd21e16a.h" -#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__) - #include "samd21e17a.h" -#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__) - #include "samd21e18a.h" -#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__) - #include "samd21g15a.h" -#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__) - #include "samd21g16a.h" -#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__) - #include "samd21g17a.h" -#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__) - #include "samd21g17au.h" -#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__) - #include "samd21g18a.h" -#elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__) - #include "samd21g18au.h" -#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__) - #include "samd21j15a.h" -#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__) - #include "samd21j16a.h" -#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__) - #include "samd21j17a.h" -#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__) - #include "samd21j18a.h" -#elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__) - #include "samd21e15b.h" -#elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__) - #include "samd21e15bu.h" -#elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__) - #include "samd21e15l.h" -#elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__) - #include "samd21e16b.h" -#elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__) - #include "samd21e16bu.h" -#elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__) - #include "samd21e16l.h" -#elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__) - #include "samd21g15b.h" -#elif defined(__SAMD21G15L__) || defined(__ATSAMD21G15L__) - #include "samd21g15l.h" -#elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__) - #include "samd21g16b.h" -#elif defined(__SAMD21G16L__) || defined(__ATSAMD21G16L__) - #include "samd21g16l.h" -#elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__) - #include "samd21j15b.h" -#elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__) - #include "samd21j16b.h" -#else - #error Library does not support the specified device. -#endif - -#endif /* _SAMD21_ */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15a.h deleted file mode 100644 index 405627e39b757..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15a.h +++ /dev/null @@ -1,557 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15A_ -#define _SAMD21E15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions - * This file defines all structures and symbols for SAMD21E15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1001000DUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15b.h deleted file mode 100644 index e0d7f89b8b895..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15b.h +++ /dev/null @@ -1,561 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15B - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15B_ -#define _SAMD21E15B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15B_definitions SAMD21E15B definitions - * This file defines all structures and symbols for SAMD21E15B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15B_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e15b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011427UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 1 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15B_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15bu.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15bu.h deleted file mode 100644 index 712124e8c7f50..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15bu.h +++ /dev/null @@ -1,561 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15BU - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15BU_ -#define _SAMD21E15BU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15BU_definitions SAMD21E15BU definitions - * This file defines all structures and symbols for SAMD21E15BU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15BU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15BU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e15bu.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011456UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 1 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15BU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15BU_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15l.h deleted file mode 100644 index 63d45a8e6c6ba..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e15l.h +++ /dev/null @@ -1,540 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E15L - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E15L_ -#define _SAMD21E15L_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E15L_definitions SAMD21E15L definitions - * This file defines all structures and symbols for SAMD21E15L: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pvReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pvReserved26; - void* pvReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void AC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc_lighting.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/ac1.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 (0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 ((Ac *)0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define AC_INST_NUM 2 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC, AC1 } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15L_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e15l.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1001143FUL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 0 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15L */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15L_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16a.h deleted file mode 100644 index 355a9f70ad42a..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16a.h +++ /dev/null @@ -1,557 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16A_ -#define _SAMD21E16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions - * This file defines all structures and symbols for SAMD21E16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1001000CUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16b.h deleted file mode 100644 index 1d9f1b72c7a67..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16b.h +++ /dev/null @@ -1,561 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16B - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16B_ -#define _SAMD21E16B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16B_definitions SAMD21E16B definitions - * This file defines all structures and symbols for SAMD21E16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16B_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011426UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 1 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16B_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16bu.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16bu.h deleted file mode 100644 index 19b75a0b77fb9..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16bu.h +++ /dev/null @@ -1,561 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16BU - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16BU_ -#define _SAMD21E16BU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16BU_definitions SAMD21E16BU definitions - * This file defines all structures and symbols for SAMD21E16BU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16BU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16BU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e16bu.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011455UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 1 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16BU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16BU_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16l.h deleted file mode 100644 index ea3e71e4a7a84..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e16l.h +++ /dev/null @@ -1,540 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16L - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16L_ -#define _SAMD21E16L_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16L_definitions SAMD21E16L definitions - * This file defines all structures and symbols for SAMD21E16L: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pvReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pvReserved26; - void* pvReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void AC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc_lighting.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/ac1.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 (0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 ((Ac *)0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define AC_INST_NUM 2 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC, AC1 } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16L_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e16l.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1001143EUL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 0 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16L */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16L_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e17a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e17a.h deleted file mode 100644 index e4eb4badff65f..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e17a.h +++ /dev/null @@ -1,557 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E17A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E17A_ -#define _SAMD21E17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions - * This file defines all structures and symbols for SAMD21E17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1001000BUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E17A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e18a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e18a.h deleted file mode 100644 index 08c0f0c6723dc..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21e18a.h +++ /dev/null @@ -1,557 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E18A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E18A_ -#define _SAMD21E18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions - * This file defines all structures and symbols for SAMD21E18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1001000AUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E18A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15a.h deleted file mode 100644 index 7b280b6c0f5d6..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15a.h +++ /dev/null @@ -1,569 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G15A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15A_ -#define _SAMD21G15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions - * This file defines all structures and symbols for SAMD21G15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010008UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15b.h deleted file mode 100644 index 0d490fe5dc998..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15b.h +++ /dev/null @@ -1,573 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G15B - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15B_ -#define _SAMD21G15B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15B_definitions SAMD21G15B definitions - * This file defines all structures and symbols for SAMD21G15B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15B_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g15b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011424UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15B_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15l.h deleted file mode 100644 index d0d9d06a98fc7..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g15l.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G15L - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15L_ -#define _SAMD21G15L_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15L_definitions SAMD21G15L definitions - * This file defines all structures and symbols for SAMD21G15L: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15L_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15L Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15L Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15L Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15L Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G15L Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G15L Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G15L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21G15L Analog Comparators 1 (AC1) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pvReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pvReserved26; - void* pvReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void AC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15L_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc_lighting.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15L_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/ac1.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15L_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15L_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 (0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 ((Ac *)0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define AC_INST_NUM 2 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC, AC1 } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15L_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g15l.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15L */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011458UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 0 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15L */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15L_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16a.h deleted file mode 100644 index c09b6eb0c2f75..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16a.h +++ /dev/null @@ -1,569 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G16A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16A_ -#define _SAMD21G16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions - * This file defines all structures and symbols for SAMD21G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010007UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16b.h deleted file mode 100644 index 19220f35f089a..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16b.h +++ /dev/null @@ -1,573 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G16B - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16B_ -#define _SAMD21G16B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16B_definitions SAMD21G16B definitions - * This file defines all structures and symbols for SAMD21G16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16B_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011423UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16B_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16l.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16l.h deleted file mode 100644 index 833345ce98954..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g16l.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G16L - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16L_ -#define _SAMD21G16L_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16L_definitions SAMD21G16L definitions - * This file defines all structures and symbols for SAMD21G16L: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16L_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16L-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16L Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16L System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16L Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16L Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16L External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16L Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16L Direct Memory Access Controller (DMAC) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16L Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16L Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16L Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16L Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16L Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16L Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16L Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16L Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16L Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16L Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16L Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16L Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16L Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G16L Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G16L Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G16L Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16L Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16L Digital Analog Converter (DAC) */ - AC1_IRQn = 28, /**< 28 SAMD21G16L Analog Comparators 1 (AC1) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pvReserved7; - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pvReserved26; - void* pvReserved27; - void* pfnAC1_Handler; /* 28 Analog Comparators 1 */ -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void AC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16L_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc_lighting.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16L_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/ac1.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16L_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_AC1 85 /**< \brief Analog Comparators 1 (AC1) */ - -#define ID_PERIPH_COUNT 86 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16L_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 (0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC1 ((Ac *)0x42005400UL) /**< \brief (AC1) APB Base Address */ -#define AC_INST_NUM 2 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC, AC1 } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16L */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16L_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g16l.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16L */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011457UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 0 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16L */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16L_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g17a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g17a.h deleted file mode 100644 index 2f8573e5fb293..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g17a.h +++ /dev/null @@ -1,569 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17A_ -#define _SAMD21G17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions - * This file defines all structures and symbols for SAMD21G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010006UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g17au.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g17au.h deleted file mode 100644 index 7741063f225c4..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g17au.h +++ /dev/null @@ -1,581 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17AU - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17AU_ -#define _SAMD21G17AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions - * This file defines all structures and symbols for SAMD21G17AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010010UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17AU_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g18a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g18a.h deleted file mode 100644 index b6b2c5b8f542c..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g18a.h +++ /dev/null @@ -1,569 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18A_ -#define _SAMD21G18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions - * This file defines all structures and symbols for SAMD21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010005UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g18au.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g18au.h deleted file mode 100644 index e111aa7f207b4..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21g18au.h +++ /dev/null @@ -1,581 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18AU - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18AU_ -#define _SAMD21G18AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions - * This file defines all structures and symbols for SAMD21G18AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x1001000FUL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18AU_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j15a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j15a.h deleted file mode 100644 index 8e582fbc423ff..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j15a.h +++ /dev/null @@ -1,581 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J15A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15A_ -#define _SAMD21J15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions - * This file defines all structures and symbols for SAMD21J15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010003UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J15A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j15b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j15b.h deleted file mode 100644 index d60dfdce5d37a..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j15b.h +++ /dev/null @@ -1,585 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J15B - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15B_ -#define _SAMD21J15B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J15B_definitions SAMD21J15B definitions - * This file defines all structures and symbols for SAMD21J15B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15B_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j15b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x8000UL /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x1000UL /* 4 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011421UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x400UL /* 1 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J15B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J15B_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j16a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j16a.h deleted file mode 100644 index 8cbf537709ba0..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j16a.h +++ /dev/null @@ -1,581 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J16A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16A_ -#define _SAMD21J16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions - * This file defines all structures and symbols for SAMD21J16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010002UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J16A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j16b.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j16b.h deleted file mode 100644 index 97388d8ec3e89..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j16b.h +++ /dev/null @@ -1,585 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J16B - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16B_ -#define _SAMD21J16B_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J16B_definitions SAMD21J16B definitions - * This file defines all structures and symbols for SAMD21J16B: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16B-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL_AUX3 (0x0080A000UL) /**< \brief (NVMCTRL) AUX3 Base Address */ -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16B_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j16b.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x10000UL /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x2000UL /* 8 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10011420UL -#define EIC_EXTINT_NUM 16 -#define NVMCTRL_RWW_EEPROM_SIZE 0x800UL /* 2 kB */ -#define PORT_GROUPS 2 -#define USB_HOST 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J16B */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J16B_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j17a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j17a.h deleted file mode 100644 index e6397a1ea71d0..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j17a.h +++ /dev/null @@ -1,581 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J17A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J17A_ -#define _SAMD21J17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions - * This file defines all structures and symbols for SAMD21J17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x20000UL /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010001UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J17A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j18a.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j18a.h deleted file mode 100644 index b23bd6bd698ea..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/include/samd21j18a.h +++ /dev/null @@ -1,581 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J18A - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J18A_ -#define _SAMD21J18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions - * This file defines all structures and symbols for SAMD21J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#define CAST(type, value) ((type *)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE 0x40000UL /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE 0x8000UL /* 32 kB */ - -#define FLASH_ADDR (0x00000000u) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR (0x00800000u) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR (0x20000000u) /**< HMCRAMC0 base address */ -#define HPB0_ADDR (0x40000000u) /**< HPB0 base address */ -#define HPB1_ADDR (0x41000000u) /**< HPB1 base address */ -#define HPB2_ADDR (0x42000000u) /**< HPB2 base address */ -#define PPB_ADDR (0xE0000000u) /**< PPB base address */ - -#define DSU_DID_RESETVALUE 0x10010000UL -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J18A_H */ diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c b/atmel-samd/asf/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c deleted file mode 100644 index 4877122706393..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/gcc/startup_samd21.c +++ /dev/null @@ -1,305 +0,0 @@ -/** - * \file - * - * \brief gcc starttup file for SAMD21 - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include - -#include "samd21.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _sidata; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void HardFault_Handler( void ) __attribute__( ( naked ) ); -void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_USB -void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_SERCOM4 -void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SERCOM5 -void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#ifdef ID_TC6 -void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC7 -void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_ADC -void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_AC -void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_DAC -void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_PTC -void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_I2S -void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_AC1 -void AC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); -#endif - -/* Exception Table */ -__attribute__ ((used, section(".vectors"))) -const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void*) (&_estack), - - .pfnReset_Handler = (void*) Reset_Handler, - .pfnNMI_Handler = (void*) NMI_Handler, - .pfnHardFault_Handler = (void*) HardFault_Handler, - .pvReservedM12 = (void*) (0UL), /* Reserved */ - .pvReservedM11 = (void*) (0UL), /* Reserved */ - .pvReservedM10 = (void*) (0UL), /* Reserved */ - .pvReservedM9 = (void*) (0UL), /* Reserved */ - .pvReservedM8 = (void*) (0UL), /* Reserved */ - .pvReservedM7 = (void*) (0UL), /* Reserved */ - .pvReservedM6 = (void*) (0UL), /* Reserved */ - .pfnSVC_Handler = (void*) SVC_Handler, - .pvReservedM4 = (void*) (0UL), /* Reserved */ - .pvReservedM3 = (void*) (0UL), /* Reserved */ - .pfnPendSV_Handler = (void*) PendSV_Handler, - .pfnSysTick_Handler = (void*) SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void*) PM_Handler, /* 0 Power Manager */ - .pfnSYSCTRL_Handler = (void*) SYSCTRL_Handler, /* 1 System Control */ - .pfnWDT_Handler = (void*) WDT_Handler, /* 2 Watchdog Timer */ - .pfnRTC_Handler = (void*) RTC_Handler, /* 3 Real-Time Counter */ - .pfnEIC_Handler = (void*) EIC_Handler, /* 4 External Interrupt Controller */ - .pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - .pfnDMAC_Handler = (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ -#ifdef ID_USB - .pfnUSB_Handler = (void*) USB_Handler, /* 7 Universal Serial Bus */ -#else - .pvReserved7 = (void*) (0UL), /* 7 Reserved */ -#endif - .pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 8 Event System Interface */ - .pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - .pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - .pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - .pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ -#ifdef ID_SERCOM4 - .pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ -#else - .pvReserved13 = (void*) (0UL), /* 13 Reserved */ -#endif -#ifdef ID_SERCOM5 - .pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ -#else - .pvReserved14 = (void*) (0UL), /* 14 Reserved */ -#endif - .pfnTCC0_Handler = (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - .pfnTCC1_Handler = (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - .pfnTCC2_Handler = (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - .pfnTC3_Handler = (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - .pfnTC4_Handler = (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - .pfnTC5_Handler = (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ -#ifdef ID_TC6 - .pfnTC6_Handler = (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ -#else - .pvReserved21 = (void*) (0UL), /* 21 Reserved */ -#endif -#ifdef ID_TC7 - .pfnTC7_Handler = (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ -#else - .pvReserved22 = (void*) (0UL), /* 22 Reserved */ -#endif -#ifdef ID_ADC - .pfnADC_Handler = (void*) ADC_Handler, /* 23 Analog Digital Converter */ -#else - .pvReserved23 = (void*) (0UL), /* 23 Reserved */ -#endif -#ifdef ID_AC - .pfnAC_Handler = (void*) AC_Handler, /* 24 Analog Comparators 0 */ -#else - .pvReserved24 = (void*) (0UL), /* 24 Reserved */ -#endif -#ifdef ID_DAC - .pfnDAC_Handler = (void*) DAC_Handler, /* 25 Digital Analog Converter */ -#else - .pvReserved25 = (void*) (0UL), /* 25 Reserved */ -#endif -#ifdef ID_PTC - .pfnPTC_Handler = (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ -#else - .pvReserved26 = (void*) (0UL), /* 26 Reserved */ -#endif -#ifdef ID_I2S - .pfnI2S_Handler = (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */ -#else - .pvReserved27 = (void*) (0UL), /* 27 Reserved */ -#endif -#ifdef ID_AC1 - .pfnAC1_Handler = (void*) AC1_Handler /* 28 Analog Comparators 1 */ -#else - .pvReserved28 = (void*) (0UL) /* 28 Reserved */ -#endif -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -__attribute__ ((used))void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_sidata; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *) & _sfixed; - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Change default QOS values to have the best performance and correct USB behaviour */ - SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; -#if defined(ID_USB) - USB->DEVICE.QOSCTRL.bit.CQOS = 2; - USB->DEVICE.QOSCTRL.bit.DQOS = 2; -#endif - DMAC->QOSCTRL.bit.DQOS = 2; - DMAC->QOSCTRL.bit.FQOS = 2; - DMAC->QOSCTRL.bit.WRBQOS = 2; - - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; - - /* Initialize the C library */ - //__libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (true); -} - -extern uint32_t _ezero; - -void HardFault_Handler(void) -{ -#ifdef ENABLE_MICRO_TRACE_BUFFER - // Turn off the micro trace buffer so we don't fill it up in the infinite - // loop below. - REG_MTB_MASTER = 0x00000000 + 6; -#endif -#ifdef CIRCUITPY_CANARY_WORD - // If the canary is intact, then kill it and reset so we have a chance to - // read our files. - if (_ezero == CIRCUITPY_CANARY_WORD) { - _ezero = CIRCUITPY_SAFE_RESTART_WORD; - NVIC_SystemReset(); - } -#endif - while(true) {} -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (true) { - } -} diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c b/atmel-samd/asf/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c deleted file mode 100644 index 2e8aae7d8394d..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/iar/startup_samd21.c +++ /dev/null @@ -1,259 +0,0 @@ -/** - * \file - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "samd21.h" - -typedef void (*intfunc) (void); -typedef union { intfunc __fun; void * __ptr; } intvec_elem; - -void __iar_program_start(void); -int __low_level_init(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -#pragma weak NMI_Handler = Dummy_Handler -#pragma weak HardFault_Handler = Dummy_Handler -#pragma weak SVC_Handler = Dummy_Handler -#pragma weak PendSV_Handler = Dummy_Handler -#pragma weak SysTick_Handler = Dummy_Handler - -/* Peripherals handlers */ -#pragma weak PM_Handler = Dummy_Handler -#pragma weak SYSCTRL_Handler = Dummy_Handler -#pragma weak WDT_Handler = Dummy_Handler -#pragma weak RTC_Handler = Dummy_Handler -#pragma weak EIC_Handler = Dummy_Handler -#pragma weak NVMCTRL_Handler = Dummy_Handler -#pragma weak DMAC_Handler = Dummy_Handler -#ifdef ID_USB -#pragma weak USB_Handler = Dummy_Handler -#endif -#pragma weak EVSYS_Handler = Dummy_Handler -#pragma weak SERCOM0_Handler = Dummy_Handler -#pragma weak SERCOM1_Handler = Dummy_Handler -#pragma weak SERCOM2_Handler = Dummy_Handler -#pragma weak SERCOM3_Handler = Dummy_Handler -#ifdef ID_SERCOM4 -#pragma weak SERCOM4_Handler = Dummy_Handler -#endif -#ifdef ID_SERCOM5 -#pragma weak SERCOM5_Handler = Dummy_Handler -#endif -#pragma weak TCC0_Handler = Dummy_Handler -#pragma weak TCC1_Handler = Dummy_Handler -#pragma weak TCC2_Handler = Dummy_Handler -#pragma weak TC3_Handler = Dummy_Handler -#pragma weak TC4_Handler = Dummy_Handler -#pragma weak TC5_Handler = Dummy_Handler -#ifdef ID_TC6 -#pragma weak TC6_Handler = Dummy_Handler -#endif -#ifdef ID_TC7 -#pragma weak TC7_Handler = Dummy_Handler -#endif -#ifdef ID_ADC -#pragma weak ADC_Handler = Dummy_Handler -#endif -#ifdef ID_AC -#pragma weak AC_Handler = Dummy_Handler -#endif -#ifdef ID_DAC -#pragma weak DAC_Handler = Dummy_Handler -#endif -#ifdef ID_PTC -#pragma weak PTC_Handler = Dummy_Handler -#endif -#ifdef ID_I2S -#pragma weak I2S_Handler = Dummy_Handler -#endif -#ifdef ID_AC1 -#pragma weak AC1_Handler = Dummy_Handler -#endif - -/* Exception Table */ -#pragma language = extended -#pragma segment = "CSTACK" - -/* The name "__vector_table" has special meaning for C-SPY: */ -/* it is where the SP start value is found, and the NVIC vector */ -/* table register (VTOR) is initialized to this address if != 0 */ - -#pragma section = ".intvec" -#pragma location = ".intvec" -const DeviceVectors __vector_table[] = { - (void*) __sfe("CSTACK"), - (void*) Reset_Handler, - (void*) NMI_Handler, - (void*) HardFault_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) SVC_Handler, - (void*) (0UL), /* Reserved */ - (void*) (0UL), /* Reserved */ - (void*) PendSV_Handler, - (void*) SysTick_Handler, - - /* Configurable interrupts */ - (void*) PM_Handler, /* 0 Power Manager */ - (void*) SYSCTRL_Handler, /* 1 System Control */ - (void*) WDT_Handler, /* 2 Watchdog Timer */ - (void*) RTC_Handler, /* 3 Real-Time Counter */ - (void*) EIC_Handler, /* 4 External Interrupt Controller */ - (void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - (void*) DMAC_Handler, /* 6 Direct Memory Access Controller */ -#ifdef ID_USB - (void*) USB_Handler, /* 7 Universal Serial Bus */ -#else - (void*) (0UL), /* 7 Reserved */ -#endif - (void*) EVSYS_Handler, /* 8 Event System Interface */ - (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ -#ifdef ID_SERCOM4 - (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ -#else - (void*) (0UL), /* 13 Reserved */ -#endif -#ifdef ID_SERCOM5 - (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ -#else - (void*) (0UL), /* 14 Reserved */ -#endif - (void*) TCC0_Handler, /* 15 Timer Counter Control 0 */ - (void*) TCC1_Handler, /* 16 Timer Counter Control 1 */ - (void*) TCC2_Handler, /* 17 Timer Counter Control 2 */ - (void*) TC3_Handler, /* 18 Basic Timer Counter 0 */ - (void*) TC4_Handler, /* 19 Basic Timer Counter 1 */ - (void*) TC5_Handler, /* 20 Basic Timer Counter 2 */ -#ifdef ID_TC6 - (void*) TC6_Handler, /* 21 Basic Timer Counter 3 */ -#else - (void*) (0UL), /* 21 Reserved */ -#endif -#ifdef ID_TC7 - (void*) TC7_Handler, /* 22 Basic Timer Counter 4 */ -#else - (void*) (0UL), /* 22 Reserved */ -#endif -#ifdef ID_ADC - (void*) ADC_Handler, /* 23 Analog Digital Converter */ -#else - (void*) (0UL), /* 23 Reserved */ -#endif -#ifdef ID_AC - (void*) AC_Handler, /* 24 Analog Comparators 0 */ -#else - (void*) (0UL), /* 24 Reserved */ -#endif -#ifdef ID_DAC - (void*) DAC_Handler, /* 25 Digital Analog Converter */ -#else - (void*) (0UL), /* 25 Reserved */ -#endif -#ifdef ID_PTC - (void*) PTC_Handler, /* 26 Peripheral Touch Controller */ -#else - (void*) (0UL), /* 26 Reserved */ -#endif -#ifdef ID_I2S - (void*) I2S_Handler, /* 27 Inter-IC Sound Interface */ -#else - (void*) (0UL), /* 27 Reserved */ -#endif -#ifdef ID_AC1 - (void*) AC1_Handler /* 28 Analog Comparators 1 */ -#else - (void*) (0UL) /* 28 Reserved */ -#endif -}; - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -int __low_level_init(void) -{ - uint32_t *pSrc = __section_begin(".intvec"); - - SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); - - return 1; /* if return 0, the data sections will not be initialized */ -} - -/**------------------------------------------------------------------------------ - * This is the code that gets called on processor reset. To initialize the - * device. - *------------------------------------------------------------------------------*/ -void Reset_Handler(void) -{ - /* Change default QOS values to have the best performance and correct USB behaviour */ - SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; -#if defined(ID_USB) - USB->DEVICE.QOSCTRL.bit.CQOS = 2; - USB->DEVICE.QOSCTRL.bit.DQOS = 2; -#endif - DMAC->QOSCTRL.bit.DQOS = 2; - DMAC->QOSCTRL.bit.FQOS = 2; - DMAC->QOSCTRL.bit.WRBQOS = 2; - - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; - - __iar_program_start(); -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/system_samd21.c b/atmel-samd/asf/sam0/utils/cmsis/samd21/source/system_samd21.c deleted file mode 100644 index f3ebdc8b768bc..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/system_samd21.c +++ /dev/null @@ -1,81 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "samd21.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (1000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/system_samd21.h b/atmel-samd/asf/sam0/utils/cmsis/samd21/source/system_samd21.h deleted file mode 100644 index 564f47f3597cf..0000000000000 --- a/atmel-samd/asf/sam0/utils/cmsis/samd21/source/system_samd21.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SYSTEM_SAMD21_H_INCLUDED_ -#define _SYSTEM_SAMD21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD21_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/utils/compiler.h b/atmel-samd/asf/sam0/utils/compiler.h deleted file mode 100644 index 72cd7db683d57..0000000000000 --- a/atmel-samd/asf/sam0/utils/compiler.h +++ /dev/null @@ -1,1174 +0,0 @@ -/** - * \file - * - * \brief Commonly used includes, types and macros. - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef UTILS_COMPILER_H_INCLUDED -#define UTILS_COMPILER_H_INCLUDED - -/** - * \defgroup group_sam0_utils Compiler abstraction layer and code utilities - * - * Compiler abstraction layer and code utilities for Cortex-M0+ based Atmel SAM devices. - * This module provides various abstraction layers and utilities to make code compatible between different compilers. - * - * @{ - */ - -#if (defined __ICCARM__) -# include -#endif - -#include -#include -#include -#include -#include - -#ifndef __ASSEMBLY__ - -#include -#include -#include -#include - -/** - * \def UNUSED - * \brief Marking \a v as a unused parameter or value. - */ -#define UNUSED(v) (void)(v) - -/** - * \def barrier - * \brief Memory barrier - */ -#ifdef __GNUC__ -# define barrier() asm volatile("" ::: "memory") -#else -# define barrier() asm ("") -#endif - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param[in] arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - - -/** - * \brief Set aligned boundary. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif (defined __ICCARM__) -# define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#endif - -/** - * \brief Set word-aligned boundary. - */ -#if (defined __GNUC__) || defined(__CC_ARM) -#define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) -#elif (defined __ICCARM__) -#define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) -#endif - -/** - * \def __always_inline - * \brief The function should always be inlined. - * - * This annotation instructs the compiler to ignore its inlining - * heuristics and inline the function no matter how big it thinks it - * becomes. - */ -#if defined(__CC_ARM) -# define __always_inline __forceinline -#elif (defined __GNUC__) -# define __always_inline __attribute__((__always_inline__)) -#elif (defined __ICCARM__) -# define __always_inline _Pragma("inline=forced") -#endif - -/** - * \def __no_inline - * \brief The function should never be inlined - * - * This annotation instructs the compiler to ignore its inlining - * heuristics and not inline the function no matter how small it thinks it - * becomes. - */ -#if defined(__CC_ARM) -# define __no_inline __attribute__((noinline)) -#elif (defined __GNUC__) -# define __no_inline __attribute__((noinline)) -#elif (defined __ICCARM__) -# define __no_inline _Pragma("inline=never") -#endif - - -/** \brief This macro is used to test fatal errors. - * - * The macro tests if the expression is false. If it is, a fatal error is - * detected and the application hangs up. If \c TEST_SUITE_DEFINE_ASSERT_MACRO - * is defined, a unit test version of the macro is used, to allow execution - * of further tests after a false expression. - * - * \param[in] expr Expression to evaluate and supposed to be nonzero. - */ -#if defined(_ASSERT_ENABLE_) -# if defined(TEST_SUITE_DEFINE_ASSERT_MACRO) -# include "unit_test/suite.h" -# else -# undef TEST_SUITE_DEFINE_ASSERT_MACRO -# define Assert(expr) \ - {\ - if (!(expr)) asm("BKPT #0");\ - } -# endif -#else -# define Assert(expr) ((void) 0) -#endif - -/* Define WEAK attribute */ -#if defined ( __CC_ARM ) -# define WEAK __attribute__ ((weak)) -#elif defined ( __ICCARM__ ) -# define WEAK __weak -#elif defined ( __GNUC__ ) -# define WEAK __attribute__ ((weak)) -#endif - -/* Define NO_INIT attribute */ -#if defined ( __CC_ARM ) -# define NO_INIT __attribute__((zero_init)) -#elif defined ( __ICCARM__ ) -# define NO_INIT __no_init -#elif defined ( __GNUC__ ) -# define NO_INIT __attribute__((section(".no_init"))) -#endif - -#include "interrupt.h" - -/** \name Usual Types - * @{ */ -#ifndef __cplusplus -# if !defined(__bool_true_false_are_defined) -typedef unsigned char bool; -# endif -#endif -typedef uint16_t le16_t; -typedef uint16_t be16_t; -typedef uint32_t le32_t; -typedef uint32_t be32_t; -typedef uint32_t iram_size_t; -/** @} */ - -/** \name Aliasing Aggregate Types - * @{ */ - -/** 16-bit union. */ -typedef union -{ - int16_t s16; - uint16_t u16; - int8_t s8[2]; - uint8_t u8[2]; -} Union16; - -/** 32-bit union. */ -typedef union -{ - int32_t s32; - uint32_t u32; - int16_t s16[2]; - uint16_t u16[2]; - int8_t s8[4]; - uint8_t u8[4]; -} Union32; - -/** 64-bit union. */ -typedef union -{ - int64_t s64; - uint64_t u64; - int32_t s32[2]; - uint32_t u32[2]; - int16_t s16[4]; - uint16_t u16[4]; - int8_t s8[8]; - uint8_t u8[8]; -} Union64; - -/** Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - int64_t *s64ptr; - uint64_t *u64ptr; - int32_t *s32ptr; - uint32_t *u32ptr; - int16_t *s16ptr; - uint16_t *u16ptr; - int8_t *s8ptr; - uint8_t *u8ptr; -} UnionPtr; - -/** Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - volatile int64_t *s64ptr; - volatile uint64_t *u64ptr; - volatile int32_t *s32ptr; - volatile uint32_t *u32ptr; - volatile int16_t *s16ptr; - volatile uint16_t *u16ptr; - volatile int8_t *s8ptr; - volatile uint8_t *u8ptr; -} UnionVPtr; - -/** Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - const int64_t *s64ptr; - const uint64_t *u64ptr; - const int32_t *s32ptr; - const uint32_t *u32ptr; - const int16_t *s16ptr; - const uint16_t *u16ptr; - const int8_t *s8ptr; - const uint8_t *u8ptr; -} UnionCPtr; - -/** Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef union -{ - const volatile int64_t *s64ptr; - const volatile uint64_t *u64ptr; - const volatile int32_t *s32ptr; - const volatile uint32_t *u32ptr; - const volatile int16_t *s16ptr; - const volatile uint16_t *u16ptr; - const volatile int8_t *s8ptr; - const volatile uint8_t *u8ptr; -} UnionCVPtr; - -/** Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - int64_t *s64ptr; - uint64_t *u64ptr; - int32_t *s32ptr; - uint32_t *u32ptr; - int16_t *s16ptr; - uint16_t *u16ptr; - int8_t *s8ptr; - uint8_t *u8ptr; -} StructPtr; - -/** Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - volatile int64_t *s64ptr; - volatile uint64_t *u64ptr; - volatile int32_t *s32ptr; - volatile uint32_t *u32ptr; - volatile int16_t *s16ptr; - volatile uint16_t *u16ptr; - volatile int8_t *s8ptr; - volatile uint8_t *u8ptr; -} StructVPtr; - -/** Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - const int64_t *s64ptr; - const uint64_t *u64ptr; - const int32_t *s32ptr; - const uint32_t *u32ptr; - const int16_t *s16ptr; - const uint16_t *u16ptr; - const int8_t *s8ptr; - const uint8_t *u8ptr; -} StructCPtr; - -/** Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers. */ -typedef struct -{ - const volatile int64_t *s64ptr; - const volatile uint64_t *u64ptr; - const volatile int32_t *s32ptr; - const volatile uint32_t *u32ptr; - const volatile int16_t *s16ptr; - const volatile uint16_t *u16ptr; - const volatile int8_t *s8ptr; - const volatile uint8_t *u8ptr; -} StructCVPtr; - -/** @} */ - -#endif /* #ifndef __ASSEMBLY__ */ - -/** \name Usual Constants - * @{ */ -#define DISABLE 0 -#define ENABLE 1 - -#ifndef __cplusplus -# if !defined(__bool_true_false_are_defined) -# define false 0 -# define true 1 -# endif -#endif -/** @} */ - -#ifndef __ASSEMBLY__ - -/** \name Optimization Control - * @{ */ - -/** - * \def likely(exp) - * \brief The expression \a exp is likely to be true - */ -#if !defined(likely) || defined(__DOXYGEN__) -# define likely(exp) (exp) -#endif - -/** - * \def unlikely(exp) - * \brief The expression \a exp is unlikely to be true - */ -#if !defined(unlikely) || defined(__DOXYGEN__) -# define unlikely(exp) (exp) -#endif - -/** - * \def is_constant(exp) - * \brief Determine if an expression evaluates to a constant value. - * - * \param[in] exp Any expression - * - * \return true if \a exp is constant, false otherwise. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define is_constant(exp) __builtin_constant_p(exp) -#else -# define is_constant(exp) (0) -#endif - -/** @} */ - -/** \name Bit-Field Handling - * @{ */ - -/** \brief Reads the bits of a value specified by a given bit-mask. - * - * \param[in] value Value to read bits from. - * \param[in] mask Bit-mask indicating bits to read. - * - * \return Read bits. - */ -#define Rd_bits( value, mask) ((value) & (mask)) - -/** \brief Writes the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue to write bits to. - * \param[in] mask Bit-mask indicating bits to write. - * \param[in] bits Bits to write. - * - * \return Resulting value with written bits. - */ -#define Wr_bits(lvalue, mask, bits) ((lvalue) = ((lvalue) & ~(mask)) |\ - ((bits ) & (mask))) - -/** \brief Tests the bits of a value specified by a given bit-mask. - * - * \param[in] value Value of which to test bits. - * \param[in] mask Bit-mask indicating bits to test. - * - * \return \c 1 if at least one of the tested bits is set, else \c 0. - */ -#define Tst_bits( value, mask) (Rd_bits(value, mask) != 0) - -/** \brief Clears the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue of which to clear bits. - * \param[in] mask Bit-mask indicating bits to clear. - * - * \return Resulting value with cleared bits. - */ -#define Clr_bits(lvalue, mask) ((lvalue) &= ~(mask)) - -/** \brief Sets the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue of which to set bits. - * \param[in] mask Bit-mask indicating bits to set. - * - * \return Resulting value with set bits. - */ -#define Set_bits(lvalue, mask) ((lvalue) |= (mask)) - -/** \brief Toggles the bits of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue of which to toggle bits. - * \param[in] mask Bit-mask indicating bits to toggle. - * - * \return Resulting value with toggled bits. - */ -#define Tgl_bits(lvalue, mask) ((lvalue) ^= (mask)) - -/** \brief Reads the bit-field of a value specified by a given bit-mask. - * - * \param[in] value Value to read a bit-field from. - * \param[in] mask Bit-mask indicating the bit-field to read. - * - * \return Read bit-field. - */ -#define Rd_bitfield( value, mask) (Rd_bits( value, mask) >> ctz(mask)) - -/** \brief Writes the bit-field of a C lvalue specified by a given bit-mask. - * - * \param[in] lvalue C lvalue to write a bit-field to. - * \param[in] mask Bit-mask indicating the bit-field to write. - * \param[in] bitfield Bit-field to write. - * - * \return Resulting value with written bit-field. - */ -#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (uint32_t)(bitfield) << ctz(mask))) - -/** @} */ - - -/** \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - * - * @{ */ - -/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define clz(u) __builtin_clz(u) -#else -# define clz(u) (((u) == 0) ? 32 : \ - ((u) & (1ul << 31)) ? 0 : \ - ((u) & (1ul << 30)) ? 1 : \ - ((u) & (1ul << 29)) ? 2 : \ - ((u) & (1ul << 28)) ? 3 : \ - ((u) & (1ul << 27)) ? 4 : \ - ((u) & (1ul << 26)) ? 5 : \ - ((u) & (1ul << 25)) ? 6 : \ - ((u) & (1ul << 24)) ? 7 : \ - ((u) & (1ul << 23)) ? 8 : \ - ((u) & (1ul << 22)) ? 9 : \ - ((u) & (1ul << 21)) ? 10 : \ - ((u) & (1ul << 20)) ? 11 : \ - ((u) & (1ul << 19)) ? 12 : \ - ((u) & (1ul << 18)) ? 13 : \ - ((u) & (1ul << 17)) ? 14 : \ - ((u) & (1ul << 16)) ? 15 : \ - ((u) & (1ul << 15)) ? 16 : \ - ((u) & (1ul << 14)) ? 17 : \ - ((u) & (1ul << 13)) ? 18 : \ - ((u) & (1ul << 12)) ? 19 : \ - ((u) & (1ul << 11)) ? 20 : \ - ((u) & (1ul << 10)) ? 21 : \ - ((u) & (1ul << 9)) ? 22 : \ - ((u) & (1ul << 8)) ? 23 : \ - ((u) & (1ul << 7)) ? 24 : \ - ((u) & (1ul << 6)) ? 25 : \ - ((u) & (1ul << 5)) ? 26 : \ - ((u) & (1ul << 4)) ? 27 : \ - ((u) & (1ul << 3)) ? 28 : \ - ((u) & (1ul << 2)) ? 29 : \ - ((u) & (1ul << 1)) ? 30 : \ - 31) -#endif - -/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -# define ctz(u) ((u) ? __builtin_ctz(u) : 32) -#else -# define ctz(u) ((u) & (1ul << 0) ? 0 : \ - (u) & (1ul << 1) ? 1 : \ - (u) & (1ul << 2) ? 2 : \ - (u) & (1ul << 3) ? 3 : \ - (u) & (1ul << 4) ? 4 : \ - (u) & (1ul << 5) ? 5 : \ - (u) & (1ul << 6) ? 6 : \ - (u) & (1ul << 7) ? 7 : \ - (u) & (1ul << 8) ? 8 : \ - (u) & (1ul << 9) ? 9 : \ - (u) & (1ul << 10) ? 10 : \ - (u) & (1ul << 11) ? 11 : \ - (u) & (1ul << 12) ? 12 : \ - (u) & (1ul << 13) ? 13 : \ - (u) & (1ul << 14) ? 14 : \ - (u) & (1ul << 15) ? 15 : \ - (u) & (1ul << 16) ? 16 : \ - (u) & (1ul << 17) ? 17 : \ - (u) & (1ul << 18) ? 18 : \ - (u) & (1ul << 19) ? 19 : \ - (u) & (1ul << 20) ? 20 : \ - (u) & (1ul << 21) ? 21 : \ - (u) & (1ul << 22) ? 22 : \ - (u) & (1ul << 23) ? 23 : \ - (u) & (1ul << 24) ? 24 : \ - (u) & (1ul << 25) ? 25 : \ - (u) & (1ul << 26) ? 26 : \ - (u) & (1ul << 27) ? 27 : \ - (u) & (1ul << 28) ? 28 : \ - (u) & (1ul << 29) ? 29 : \ - (u) & (1ul << 30) ? 30 : \ - (u) & (1ul << 31) ? 31 : \ - 32) -#endif - -/** @} */ - - -/** \name Bit Reversing - * @{ */ - -/** \brief Reverses the bits of \a u8. - * - * \param[in] u8 U8 of which to reverse the bits. - * - * \return Value resulting from \a u8 with reversed bits. - */ -#define bit_reverse8(u8) ((U8)(bit_reverse32((U8)(u8)) >> 24)) - -/** \brief Reverses the bits of \a u16. - * - * \param[in] u16 U16 of which to reverse the bits. - * - * \return Value resulting from \a u16 with reversed bits. - */ -#define bit_reverse16(u16) ((uint16_t)(bit_reverse32((uint16_t)(u16)) >> 16)) - -/** \brief Reverses the bits of \a u32. - * - * \param[in] u32 U32 of which to reverse the bits. - * - * \return Value resulting from \a u32 with reversed bits. - */ -#define bit_reverse32(u32) __RBIT(u32) - -/** \brief Reverses the bits of \a u64. - * - * \param[in] u64 U64 of which to reverse the bits. - * - * \return Value resulting from \a u64 with reversed bits. - */ -#define bit_reverse64(u64) ((uint64_t)(((uint64_t)bit_reverse32((uint64_t)(u64) >> 32)) |\ - ((uint64_t)bit_reverse32((uint64_t)(u64)) << 32))) - -/** @} */ - - -/** \name Alignment - * @{ */ - -/** \brief Tests alignment of the number \a val with the \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0. - */ -#define Test_align(val, n) (!Tst_bits( val, (n) - 1 ) ) - -/** \brief Gets alignment of the number \a val with respect to the \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return Alignment of the number \a val with respect to the \a n boundary. - */ -#define Get_align(val, n) ( Rd_bits( val, (n) - 1 ) ) - -/** \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary. - * - * \param[in] lval Input/output lvalue. - * \param[in] n Boundary. - * \param[in] alg Alignment. - * - * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary. - */ -#define Set_align(lval, n, alg) ( Wr_bits(lval, (n) - 1, alg) ) - -/** \brief Aligns the number \a val with the upper \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return Value resulting from the number \a val aligned with the upper \a n boundary. - */ -#define Align_up( val, n) (((val) + ((n) - 1)) & ~((n) - 1)) - -/** \brief Aligns the number \a val with the lower \a n boundary. - * - * \param[in] val Input value. - * \param[in] n Boundary. - * - * \return Value resulting from the number \a val aligned with the lower \a n boundary. - */ -#define Align_down(val, n) ( (val) & ~((n) - 1)) - -/** @} */ - - -/** \name Mathematics - * - * The same considerations as for clz and ctz apply here but GCC does not - * provide built-in functions to access the assembly instructions abs, min and - * max and it does not produce them by itself in most cases, so two sets of - * macros are defined here: - * - Abs, Min and Max to apply to constant expressions (values known at - * compile time); - * - abs, min and max to apply to non-constant expressions (values unknown at - * compile time), abs is found in stdlib.h. - * - * @{ */ - -/** \brief Takes the absolute value of \a a. - * - * \param[in] a Input value. - * - * \return Absolute value of \a a. - * - * \note More optimized if only used with values known at compile time. - */ -#define Abs(a) (((a) < 0 ) ? -(a) : (a)) - -#ifndef __cplusplus -/** \brief Takes the minimal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Min(a, b) (((a) < (b)) ? (a) : (b)) - -/** \brief Takes the maximal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values known at compile time. - */ -#define Max(a, b) (((a) > (b)) ? (a) : (b)) - -/** \brief Takes the minimal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Minimal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define min(a, b) Min(a, b) - -/** \brief Takes the maximal value of \a a and \a b. - * - * \param[in] a Input value. - * \param[in] b Input value. - * - * \return Maximal value of \a a and \a b. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define max(a, b) Max(a, b) -#endif - -/** @} */ - - -/** \brief Calls the routine at address \a addr. - * - * It generates a long call opcode. - * - * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if - * it is invoked from the CPU supervisor mode. - * - * \param[in] addr Address of the routine to call. - * - * \note It may be used as a long jump opcode in some special cases. - */ -#define Long_call(addr) ((*(void (*)(void))(addr))()) - - -/** \name MCU Endianism Handling - * ARM is MCU little endian. - * - * @{ */ -#define BE16(x) swap16(x) -#define LE16(x) (x) - -#define le16_to_cpu(x) (x) -#define cpu_to_le16(x) (x) -#define LE16_TO_CPU(x) (x) -#define CPU_TO_LE16(x) (x) - -#define be16_to_cpu(x) swap16(x) -#define cpu_to_be16(x) swap16(x) -#define BE16_TO_CPU(x) swap16(x) -#define CPU_TO_BE16(x) swap16(x) - -#define le32_to_cpu(x) (x) -#define cpu_to_le32(x) (x) -#define LE32_TO_CPU(x) (x) -#define CPU_TO_LE32(x) (x) - -#define be32_to_cpu(x) swap32(x) -#define cpu_to_be32(x) swap32(x) -#define BE32_TO_CPU(x) swap32(x) -#define CPU_TO_BE32(x) swap32(x) -/** @} */ - - -/** \name Endianism Conversion - * - * The same considerations as for clz and ctz apply here but GCC's - * __builtin_bswap_32 and __builtin_bswap_64 do not behave like macros when - * applied to constant expressions, so two sets of macros are defined here: - * - Swap16, Swap32 and Swap64 to apply to constant expressions (values known - * at compile time); - * - swap16, swap32 and swap64 to apply to non-constant expressions (values - * unknown at compile time). - * - * @{ */ - -/** \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param[in] u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) |\ - ((uint16_t)(u16) << 8))) - -/** \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param[in] u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap32(u32) ((uint32_t)(((uint32_t)Swap16((uint32_t)(u32) >> 16)) |\ - ((uint32_t)Swap16((uint32_t)(u32)) << 16))) - -/** \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param[in] u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define Swap64(u64) ((uint64_t)(((uint64_t)Swap32((uint64_t)(u64) >> 32)) |\ - ((uint64_t)Swap32((uint64_t)(u64)) << 32))) - -/** \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param[in] u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#define swap16(u16) Swap16(u16) - -/** \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param[in] u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap32(u32) ((uint32_t)__builtin_bswap32((uint32_t)(u32))) -#else -# define swap32(u32) Swap32(u32) -#endif - -/** \brief Toggles the endianism of \a u64 (by swapping its bytes). - * - * \param[in] u64 U64 of which to toggle the endianism. - * - * \return Value resulting from \a u64 with toggled endianism. - * - * \note More optimized if only used with values unknown at compile time. - */ -#if (defined __GNUC__) -# define swap64(u64) ((uint64_t)__builtin_bswap64((uint64_t)(u64))) -#else -# define swap64(u64) ((uint64_t)(((uint64_t)swap32((uint64_t)(u64) >> 32)) |\ - ((uint64_t)swap32((uint64_t)(u64)) << 32))) -#endif - -/** @} */ - - -/** \name Target Abstraction - * - * @{ */ - -#define _GLOBEXT_ extern /**< extern storage-class specifier. */ -#define _CONST_TYPE_ const /**< const type qualifier. */ -#define _MEM_TYPE_SLOW_ /**< Slow memory type. */ -#define _MEM_TYPE_MEDFAST_ /**< Fairly fast memory type. */ -#define _MEM_TYPE_FAST_ /**< Fast memory type. */ - -#define memcmp_ram2ram memcmp /**< Target-specific memcmp of RAM to RAM. */ -#define memcmp_code2ram memcmp /**< Target-specific memcmp of RAM to NVRAM. */ -#define memcpy_ram2ram memcpy /**< Target-specific memcpy from RAM to RAM. */ -#define memcpy_code2ram memcpy /**< Target-specific memcpy from NVRAM to RAM. */ - -/** @} */ - -/** - * \brief Calculate \f$ \left\lceil \frac{a}{b} \right\rceil \f$ using - * integer arithmetic. - * - * \param[in] a An integer - * \param[in] b Another integer - * - * \return (\a a / \a b) rounded up to the nearest integer. - */ -#define div_ceil(a, b) (((a) + (b) - 1) / (b)) - -#endif /* #ifndef __ASSEMBLY__ */ -#ifdef __ICCARM__ -/** \name Compiler Keywords - * - * Port of some keywords from GCC to IAR Embedded Workbench. - * - * @{ */ - -#define __asm__ asm -#define __inline__ inline -#define __volatile__ - -/** @} */ - -#endif - -#define FUNC_PTR void * -/** - * \def unused - * \brief Marking \a v as a unused parameter or value. - */ -#define unused(v) do { (void)(v); } while(0) - -/* Define RAMFUNC attribute */ -#if defined ( __CC_ARM ) /* Keil uVision 4 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define RAMFUNC __ramfunc -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define RAMFUNC __attribute__ ((section(".ramfunc"))) -#endif - -/* Define OPTIMIZE_HIGH attribute */ -#if defined ( __CC_ARM ) /* Keil uVision 4 */ -# define OPTIMIZE_HIGH _Pragma("O3") -#elif defined ( __ICCARM__ ) /* IAR Ewarm 5.41+ */ -# define OPTIMIZE_HIGH _Pragma("optimize=high") -#elif defined ( __GNUC__ ) /* GCC CS3 2009q3-68 */ -# define OPTIMIZE_HIGH __attribute__((optimize("s"))) -#endif -#define PASS 0 -#define FAIL 1 -#define LOW 0 -#define HIGH 1 - -typedef int8_t S8 ; //!< 8-bit signed integer. -typedef uint8_t U8 ; //!< 8-bit unsigned integer. -typedef int16_t S16; //!< 16-bit signed integer. -typedef uint16_t U16; //!< 16-bit unsigned integer. -typedef int32_t S32; //!< 32-bit signed integer. -typedef uint32_t U32; //!< 32-bit unsigned integer. -typedef int64_t S64; //!< 64-bit signed integer. -typedef uint64_t U64; //!< 64-bit unsigned integer. -typedef float F32; //!< 32-bit floating-point number. -typedef double F64; //!< 64-bit floating-point number. - -#define MSB(u16) (((U8 *)&(u16))[1]) //!< Most significant byte of \a u16. -#define LSB(u16) (((U8 *)&(u16))[0]) //!< Least significant byte of \a u16. - -#define MSH(u32) (((U16 *)&(u32))[1]) //!< Most significant half-word of \a u32. -#define LSH(u32) (((U16 *)&(u32))[0]) //!< Least significant half-word of \a u32. -#define MSB0W(u32) (((U8 *)&(u32))[3]) //!< Most significant byte of 1st rank of \a u32. -#define MSB1W(u32) (((U8 *)&(u32))[2]) //!< Most significant byte of 2nd rank of \a u32. -#define MSB2W(u32) (((U8 *)&(u32))[1]) //!< Most significant byte of 3rd rank of \a u32. -#define MSB3W(u32) (((U8 *)&(u32))[0]) //!< Most significant byte of 4th rank of \a u32. -#define LSB3W(u32) MSB0W(u32) //!< Least significant byte of 4th rank of \a u32. -#define LSB2W(u32) MSB1W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB1W(u32) MSB2W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB0W(u32) MSB3W(u32) //!< Least significant byte of 1st rank of \a u32. - -#define MSW(u64) (((U32 *)&(u64))[1]) //!< Most significant word of \a u64. -#define LSW(u64) (((U32 *)&(u64))[0]) //!< Least significant word of \a u64. -#define MSH0(u64) (((U16 *)&(u64))[3]) //!< Most significant half-word of 1st rank of \a u64. -#define MSH1(u64) (((U16 *)&(u64))[2]) //!< Most significant half-word of 2nd rank of \a u64. -#define MSH2(u64) (((U16 *)&(u64))[1]) //!< Most significant half-word of 3rd rank of \a u64. -#define MSH3(u64) (((U16 *)&(u64))[0]) //!< Most significant half-word of 4th rank of \a u64. -#define LSH3(u64) MSH0(u64) //!< Least significant half-word of 4th rank of \a u64. -#define LSH2(u64) MSH1(u64) //!< Least significant half-word of 3rd rank of \a u64. -#define LSH1(u64) MSH2(u64) //!< Least significant half-word of 2nd rank of \a u64. -#define LSH0(u64) MSH3(u64) //!< Least significant half-word of 1st rank of \a u64. -#define MSB0D(u64) (((U8 *)&(u64))[7]) //!< Most significant byte of 1st rank of \a u64. -#define MSB1D(u64) (((U8 *)&(u64))[6]) //!< Most significant byte of 2nd rank of \a u64. -#define MSB2D(u64) (((U8 *)&(u64))[5]) //!< Most significant byte of 3rd rank of \a u64. -#define MSB3D(u64) (((U8 *)&(u64))[4]) //!< Most significant byte of 4th rank of \a u64. -#define MSB4D(u64) (((U8 *)&(u64))[3]) //!< Most significant byte of 5th rank of \a u64. -#define MSB5D(u64) (((U8 *)&(u64))[2]) //!< Most significant byte of 6th rank of \a u64. -#define MSB6D(u64) (((U8 *)&(u64))[1]) //!< Most significant byte of 7th rank of \a u64. -#define MSB7D(u64) (((U8 *)&(u64))[0]) //!< Most significant byte of 8th rank of \a u64. -#define LSB7D(u64) MSB0D(u64) //!< Least significant byte of 8th rank of \a u64. -#define LSB6D(u64) MSB1D(u64) //!< Least significant byte of 7th rank of \a u64. -#define LSB5D(u64) MSB2D(u64) //!< Least significant byte of 6th rank of \a u64. -#define LSB4D(u64) MSB3D(u64) //!< Least significant byte of 5th rank of \a u64. -#define LSB3D(u64) MSB4D(u64) //!< Least significant byte of 4th rank of \a u64. -#define LSB2D(u64) MSB5D(u64) //!< Least significant byte of 3rd rank of \a u64. -#define LSB1D(u64) MSB6D(u64) //!< Least significant byte of 2nd rank of \a u64. -#define LSB0D(u64) MSB7D(u64) //!< Least significant byte of 1st rank of \a u64. - -#define LSB0(u32) LSB0W(u32) //!< Least significant byte of 1st rank of \a u32. -#define LSB1(u32) LSB1W(u32) //!< Least significant byte of 2nd rank of \a u32. -#define LSB2(u32) LSB2W(u32) //!< Least significant byte of 3rd rank of \a u32. -#define LSB3(u32) LSB3W(u32) //!< Least significant byte of 4th rank of \a u32. -#define MSB3(u32) MSB3W(u32) //!< Most significant byte of 4th rank of \a u32. -#define MSB2(u32) MSB2W(u32) //!< Most significant byte of 3rd rank of \a u32. -#define MSB1(u32) MSB1W(u32) //!< Most significant byte of 2nd rank of \a u32. -#define MSB0(u32) MSB0W(u32) //!< Most significant byte of 1st rank of \a u32. - -#if defined(__ICCARM__) -#define SHORTENUM __packed -#elif defined(__GNUC__) -#define SHORTENUM __attribute__((packed)) -#endif - -/* No operation */ -#if defined(__ICCARM__) -#define nop() __no_operation() -#elif defined(__GNUC__) -#define nop() (__NOP()) -#endif - -#define FLASH_DECLARE(x) const x -#define FLASH_EXTERN(x) extern const x -#define PGM_READ_BYTE(x) *(x) -#define PGM_READ_WORD(x) *(x) -#define MEMCPY_ENDIAN memcpy -#define PGM_READ_BLOCK(dst, src, len) memcpy((dst), (src), (len)) - -/*Defines the Flash Storage for the request and response of MAC*/ -#define CMD_ID_OCTET (0) - -/* Converting of values from CPU endian to little endian. */ -#define CPU_ENDIAN_TO_LE16(x) (x) -#define CPU_ENDIAN_TO_LE32(x) (x) -#define CPU_ENDIAN_TO_LE64(x) (x) - -/* Converting of values from little endian to CPU endian. */ -#define LE16_TO_CPU_ENDIAN(x) (x) -#define LE32_TO_CPU_ENDIAN(x) (x) -#define LE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from little endian to CPU endian. */ -#define CLE16_TO_CPU_ENDIAN(x) (x) -#define CLE32_TO_CPU_ENDIAN(x) (x) -#define CLE64_TO_CPU_ENDIAN(x) (x) - -/* Converting of constants from CPU endian to little endian. */ -#define CCPU_ENDIAN_TO_LE16(x) (x) -#define CCPU_ENDIAN_TO_LE32(x) (x) -#define CCPU_ENDIAN_TO_LE64(x) (x) - -#define ADDR_COPY_DST_SRC_16(dst, src) ((dst) = (src)) -#define ADDR_COPY_DST_SRC_64(dst, src) ((dst) = (src)) - -/** - * @brief Converts a 64-Bit value into a 8 Byte array - * - * @param[in] value 64-Bit value - * @param[out] data Pointer to the 8 Byte array to be updated with 64-Bit value - * @ingroup apiPalApi - */ -static inline void convert_64_bit_to_byte_array(uint64_t value, uint8_t *data) -{ - uint8_t index = 0; - - while (index < 8) - { - data[index++] = value & 0xFF; - value = value >> 8; - } -} - -/** - * @brief Converts a 16-Bit value into a 2 Byte array - * - * @param[in] value 16-Bit value - * @param[out] data Pointer to the 2 Byte array to be updated with 16-Bit value - * @ingroup apiPalApi - */ -static inline void convert_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_spec_16_bit_to_byte_array(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* Converts a 16-Bit value into a 2 Byte array */ -static inline void convert_16_bit_to_byte_address(uint16_t value, uint8_t *data) -{ - data[0] = value & 0xFF; - data[1] = (value >> 8) & 0xFF; -} - -/* - * @brief Converts a 2 Byte array into a 16-Bit value - * - * @param data Specifies the pointer to the 2 Byte array - * - * @return 16-Bit value - * @ingroup apiPalApi - */ -static inline uint16_t convert_byte_array_to_16_bit(uint8_t *data) -{ - return (data[0] | ((uint16_t)data[1] << 8)); -} - -/* Converts a 4 Byte array into a 32-Bit value */ -static inline uint32_t convert_byte_array_to_32_bit(uint8_t *data) -{ - union - { - uint32_t u32; - uint8_t u8[4]; - }long_addr; - uint8_t index; - for (index = 0; index < 4; index++) - { - long_addr.u8[index] = *data++; - } - return long_addr.u32; -} - -/** - * @brief Converts a 8 Byte array into a 64-Bit value - * - * @param data Specifies the pointer to the 8 Byte array - * - * @return 64-Bit value - * @ingroup apiPalApi - */ -static inline uint64_t convert_byte_array_to_64_bit(uint8_t *data) -{ - union - { - uint64_t u64; - uint8_t u8[8]; - } long_addr; - - uint8_t index; - - for (index = 0; index < 8; index++) - { - long_addr.u8[index] = *data++; - } - - return long_addr.u64; -} - -/** @} */ - -#endif /* UTILS_COMPILER_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/utils/header_files/io.h b/atmel-samd/asf/sam0/utils/header_files/io.h deleted file mode 100644 index a1164456658f4..0000000000000 --- a/atmel-samd/asf/sam0/utils/header_files/io.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Arch file for SAM0. - * - * This file defines common SAM0 series. - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _SAM_IO_ -#define _SAM_IO_ - -#include -#include -#include - -/* SAM D20 family */ -#if (SAMD20) -# include "samd20.h" -#endif - -#if (SAMD21) -# include "samd21.h" -#endif - -#if (SAMR21) -# include "samr21.h" -#endif - -#if (SAMD09) -# include "samd09.h" -#endif - -#if (SAMD10) -# include "samd10.h" -#endif - -#if (SAMD11) -# include "samd11.h" -#endif - -#if (SAML21) -# include "saml21.h" -#endif - -#if (SAMR30) -# include "samr30.h" -#endif - -#if (SAML22) -# include "saml22.h" -#endif - -#if (SAMDA1) -# include "samda1.h" -#endif - -#if (SAMC20) -# include "samc20.h" -#endif - -#if (SAMC21) -# include "samc21.h" -#endif - -#if (SAMB11) -# include "samb11.h" -#endif - -#endif /* _SAM_IO_ */ diff --git a/atmel-samd/asf/sam0/utils/make/Makefile.sam.in b/atmel-samd/asf/sam0/utils/make/Makefile.sam.in deleted file mode 100644 index d07e471899bd8..0000000000000 --- a/atmel-samd/asf/sam0/utils/make/Makefile.sam.in +++ /dev/null @@ -1,502 +0,0 @@ -# List of available make goals: -# -# all Default target, builds the project -# clean Clean up the project -# rebuild Rebuild the project -# debug_flash Builds the project and debug in flash -# debug_sram Builds the project and debug in sram -# -# doc Build the documentation -# cleandoc Clean up the documentation -# rebuilddoc Rebuild the documentation -# -# \file -# -# Copyright (c) 2011 - 2014 Atmel Corporation. All rights reserved. -# -# \asf_license_start -# -# \page License -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# 3. The name of Atmel may not be used to endorse or promote products derived -# from this software without specific prior written permission. -# -# 4. This software may only be redistributed and used in connection with an -# Atmel microcontroller product. -# -# THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -# EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. -# -# \asf_license_stop -# - -# Include the config.mk file from the current working path, e.g., where the -# user called make. -include config.mk - -# Tool to use to generate documentation from the source code -DOCGEN ?= doxygen - -# Look for source files relative to the top-level source directory -VPATH := $(PRJ_PATH) - -# Output target file -project_type := $(PROJECT_TYPE) - -# Output target file -ifeq ($(project_type),flash) -target := $(TARGET_FLASH) -linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_FLASH) -debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_FLASH) -else -target := $(TARGET_SRAM) -linker_script := $(PRJ_PATH)/$(LINKER_SCRIPT_SRAM) -debug_script := $(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM) -endif - -# Output project name (target name minus suffix) -project := $(basename $(target)) - -# Output target file (typically ELF or static library) -ifeq ($(suffix $(target)),.a) -target_type := lib -else -ifeq ($(suffix $(target)),.elf) -target_type := elf -else -$(error "Target type $(target_type) is not supported") -endif -endif - -# Allow override of operating system detection. The user can add OS=Linux or -# OS=Windows on the command line to explicit set the host OS. -# -# This allows to work around broken uname utility on certain systems. -ifdef OS - ifeq ($(strip $(OS)), Linux) - os_type := Linux - endif - ifeq ($(strip $(OS)), Windows) - os_type := windows32_64 - endif -endif - -os_type ?= $(strip $(shell uname)) - -ifeq ($(os_type),windows32) -os := Windows -else -ifeq ($(os_type),windows64) -os := Windows -else -ifeq ($(os_type),windows32_64) -os ?= Windows -else -ifeq ($(os_type),) -os := Windows -else -# Default to Linux style operating system. Both Cygwin and mingw are fully -# compatible (for this Makefile) with Linux. -os := Linux -endif -endif -endif -endif - -# Output documentation directory and configuration file. -docdir := ../doxygen/html -doccfg := ../doxygen/doxyfile.doxygen - -CROSS ?= arm-none-eabi- -AR := $(CROSS)ar -AS := $(CROSS)as -CC := $(CROSS)gcc -CPP := $(CROSS)gcc -E -CXX := $(CROSS)g++ -LD := $(CROSS)g++ -NM := $(CROSS)nm -OBJCOPY := $(CROSS)objcopy -OBJDUMP := $(CROSS)objdump -SIZE := $(CROSS)size -GDB := $(CROSS)gdb - -RM := rm -ifeq ($(os),Windows) -RMDIR := rmdir /S /Q -else -RMDIR := rmdir -p --ignore-fail-on-non-empty -endif - -# On Windows, we need to override the shell to force the use of cmd.exe -ifeq ($(os),Windows) -SHELL := cmd -endif - -# Strings for beautifying output -MSG_CLEAN_FILES = "RM *.o *.d" -MSG_CLEAN_DIRS = "RMDIR $(strip $(clean-dirs))" -MSG_CLEAN_DOC = "RMDIR $(docdir)" -MSG_MKDIR = "MKDIR $(dir $@)" - -MSG_INFO = "INFO " -MSG_PREBUILD = "PREBUILD $(PREBUILD_CMD)" -MSG_POSTBUILD = "POSTBUILD $(POSTBUILD_CMD)" - -MSG_ARCHIVING = "AR $@" -MSG_ASSEMBLING = "AS $@" -MSG_BINARY_IMAGE = "OBJCOPY $@" -MSG_COMPILING = "CC $@" -MSG_COMPILING_CXX = "CXX $@" -MSG_EXTENDED_LISTING = "OBJDUMP $@" -MSG_IHEX_IMAGE = "OBJCOPY $@" -MSG_LINKING = "LN $@" -MSG_PREPROCESSING = "CPP $@" -MSG_SIZE = "SIZE $@" -MSG_SYMBOL_TABLE = "NM $@" - -MSG_GENERATING_DOC = "DOXYGEN $(docdir)" - -# Don't use make's built-in rules and variables -MAKEFLAGS += -rR - -# Don't print 'Entering directory ...' -MAKEFLAGS += --no-print-directory - -# Function for reversing the order of a list -reverse = $(if $(1),$(call reverse,$(wordlist 2,$(words $(1)),$(1)))) $(firstword $(1)) - -# Hide command output by default, but allow the user to override this -# by adding V=1 on the command line. -# -# This is inspired by the Kbuild system used by the Linux kernel. -ifdef V - ifeq ("$(origin V)", "command line") - VERBOSE = $(V) - endif -endif -ifndef VERBOSE - VERBOSE = 0 -endif - -ifeq ($(VERBOSE), 1) - Q = -else - Q = @ -endif - -arflags-gnu-y := $(ARFLAGS) -asflags-gnu-y := $(ASFLAGS) -cflags-gnu-y := $(CFLAGS) -cxxflags-gnu-y := $(CXXFLAGS) -cppflags-gnu-y := $(CPPFLAGS) -cpuflags-gnu-y := -dbgflags-gnu-y := $(DBGFLAGS) -libflags-gnu-y := $(foreach LIB,$(LIBS),-l$(LIB)) -ldflags-gnu-y := $(LDFLAGS) -flashflags-gnu-y := -clean-files := -clean-dirs := - -clean-files += $(wildcard $(target) $(project).map) -clean-files += $(wildcard $(project).hex $(project).bin) -clean-files += $(wildcard $(project).lss $(project).sym) -clean-files += $(wildcard $(build)) - -# Use pipes instead of temporary files for communication between processes -cflags-gnu-y += -pipe -asflags-gnu-y += -pipe -ldflags-gnu-y += -pipe - -# Archiver flags. -arflags-gnu-y += rcs - -# Always enable warnings. And be very careful about implicit -# declarations. -cflags-gnu-y += -Wall -Wstrict-prototypes -Wmissing-prototypes -cflags-gnu-y += -Werror-implicit-function-declaration -cxxflags-gnu-y += -Wall -# IAR doesn't allow arithmetic on void pointers, so warn about that. -cflags-gnu-y += -Wpointer-arith -cxxflags-gnu-y += -Wpointer-arith - -# Preprocessor flags. -cppflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),-I$(INC)) -asflags-gnu-y += $(foreach INC,$(addprefix $(PRJ_PATH)/,$(INC_PATH)),'-Wa,-I$(INC)') - -# CPU specific flags. -cpuflags-gnu-y += -mcpu=$(ARCH) -mthumb -D=__$(PART)__ - -# Dependency file flags. -depflags = -MD -MP -MQ $@ - -# Debug specific flags. -ifdef BUILD_DEBUG_LEVEL -dbgflags-gnu-y += -g$(BUILD_DEBUG_LEVEL) -else -dbgflags-gnu-y += -g3 -endif - -# Optimization specific flags. -ifdef BUILD_OPTIMIZATION -optflags-gnu-y = -O$(BUILD_OPTIMIZATION) -else -optflags-gnu-y = $(OPTIMIZATION) -endif - -# Always preprocess assembler files. -asflags-gnu-y += -x assembler-with-cpp -# Compile C files using the GNU99 standard. -cflags-gnu-y += -std=gnu99 -# Compile C++ files using the GNU++98 standard. -cxxflags-gnu-y += -std=gnu++98 - -# Don't use strict aliasing (very common in embedded applications). -cflags-gnu-y += -fno-strict-aliasing -cxxflags-gnu-y += -fno-strict-aliasing - -# Separate each function and data into its own separate section to allow -# garbage collection of unused sections. -cflags-gnu-y += -ffunction-sections -fdata-sections -cxxflags-gnu-y += -ffunction-sections -fdata-sections - -# Various cflags. -cflags-gnu-y += -Wchar-subscripts -Wcomment -Wformat=2 -Wimplicit-int -cflags-gnu-y += -Wmain -Wparentheses -cflags-gnu-y += -Wsequence-point -Wreturn-type -Wswitch -Wtrigraphs -Wunused -cflags-gnu-y += -Wuninitialized -Wunknown-pragmas -Wfloat-equal -Wundef -cflags-gnu-y += -Wshadow -Wbad-function-cast -Wwrite-strings -cflags-gnu-y += -Wsign-compare -Waggregate-return -cflags-gnu-y += -Wmissing-declarations -cflags-gnu-y += -Wformat -Wmissing-format-attribute -Wno-deprecated-declarations -cflags-gnu-y += -Wpacked -Wredundant-decls -Wnested-externs -Wlong-long -cflags-gnu-y += -Wunreachable-code -cflags-gnu-y += -Wcast-align -cflags-gnu-y += --param max-inline-insns-single=500 - -# To reduce application size use only integer printf function. -cflags-gnu-y += -Dprintf=iprintf - -# Use newlib-nano to reduce application size -ldflags-gnu-y += --specs=nano.specs - -# Garbage collect unreferred sections when linking. -ldflags-gnu-y += -Wl,--gc-sections - -# Use the linker script if provided by the project. -ifneq ($(strip $(linker_script)),) -ldflags-gnu-y += -Wl,-T $(linker_script) -endif - -# Output a link map file and a cross reference table -ldflags-gnu-y += -Wl,-Map=$(project).map,--cref - -# Add library search paths relative to the top level directory. -ldflags-gnu-y += $(foreach _LIB_PATH,$(addprefix $(PRJ_PATH)/,$(LIB_PATH)),-L$(_LIB_PATH)) - -a_flags = $(cpuflags-gnu-y) $(depflags) $(cppflags-gnu-y) $(asflags-gnu-y) -D__ASSEMBLY__ -c_flags = $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cflags-gnu-y) -cxx_flags= $(cpuflags-gnu-y) $(dbgflags-gnu-y) $(depflags) $(optflags-gnu-y) $(cppflags-gnu-y) $(cxxflags-gnu-y) -l_flags = -Wl,--entry=Reset_Handler -Wl,--cref $(cpuflags-gnu-y) $(optflags-gnu-y) $(ldflags-gnu-y) -ar_flags = $(arflags-gnu-y) - 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-# Debug the project in sram. -.PHONY: debug_sram -debug_sram: all - $(GDB) -x "$(PRJ_PATH)/$(DEBUG_SCRIPT_SRAM)" -ex "reset" -readnow -se $(TARGET_SRAM) - -.PHONY: objfiles -objfiles: $(obj-y) - -# Create object files from C source files. -$(build-dir)%.o: %.c $(MAKEFILE_PATH) config.mk - $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) -ifeq ($(os),Windows) - $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) -else - $(Q)test -d $(dir $@) || mkdir -p $(dir $@) -endif - @echo $(MSG_COMPILING) - $(Q)$(CC) $(c_flags) -c $< -o $@ - -# Create object files from C++ source files. -$(build-dir)%.o: %.cpp $(MAKEFILE_PATH) config.mk - $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) -ifeq ($(os),Windows) - $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) -else - $(Q)test -d $(dir $@) || mkdir -p $(dir $@) -endif - @echo $(MSG_COMPILING_CXX) - $(Q)$(CXX) $(cxx_flags) -c $< -o $@ - -# Preprocess and assemble: create object files from assembler source files. -$(build-dir)%.o: %.S $(MAKEFILE_PATH) config.mk - $(Q)test -d $(dir $@) || echo $(MSG_MKDIR) -ifeq ($(os),Windows) - $(Q)test -d $(patsubst %/,%,$(dir $@)) || mkdir $(subst /,\,$(dir $@)) -else - $(Q)test -d $(dir $@) || mkdir -p $(dir $@) -endif - @echo $(MSG_ASSEMBLING) - $(Q)$(CC) $(a_flags) -c $< -o $@ - -# Include all dependency files to add depedency to all header files in use. -include $(dep-files) - -ifeq ($(target_type),lib) -# Archive object files into an archive -$(target): $(MAKEFILE_PATH) config.mk $(obj-y) - @echo $(MSG_ARCHIVING) - $(Q)$(AR) $(ar_flags) $@ $(obj-y) - @echo $(MSG_SIZE) - $(Q)$(SIZE) -Bxt $@ -else -ifeq ($(target_type),elf) -# Link the object files into an ELF file. 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All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _MRECURSION_H_ -#define _MRECURSION_H_ - -/** - * \defgroup group_sam0_utils_mrecursion Preprocessor - Macro Recursion - * - * \ingroup group_sam0_utils - * - * @{ - */ - -#include "preprocessor.h" - -#define DEC_256 255 -#define DEC_255 254 -#define DEC_254 253 -#define DEC_253 252 -#define DEC_252 251 -#define DEC_251 250 -#define DEC_250 249 -#define DEC_249 248 -#define DEC_248 247 -#define DEC_247 246 -#define DEC_246 245 -#define DEC_245 244 -#define DEC_244 243 -#define DEC_243 242 -#define DEC_242 241 -#define DEC_241 240 -#define DEC_240 239 -#define DEC_239 238 -#define DEC_238 237 -#define DEC_237 236 -#define DEC_236 235 -#define DEC_235 234 -#define DEC_234 233 -#define DEC_233 232 -#define DEC_232 231 -#define DEC_231 230 -#define DEC_230 229 -#define DEC_229 228 -#define DEC_228 227 -#define DEC_227 226 -#define DEC_226 225 -#define DEC_225 224 -#define DEC_224 223 -#define DEC_223 222 -#define DEC_222 221 -#define DEC_221 220 -#define DEC_220 219 -#define DEC_219 218 -#define DEC_218 217 -#define DEC_217 216 -#define DEC_216 215 -#define DEC_215 214 -#define DEC_214 213 -#define DEC_213 212 -#define DEC_212 211 -#define DEC_211 210 -#define DEC_210 209 -#define DEC_209 208 -#define DEC_208 207 -#define DEC_207 206 -#define DEC_206 205 -#define DEC_205 204 -#define DEC_204 203 -#define DEC_203 202 -#define DEC_202 201 -#define DEC_201 200 -#define DEC_200 199 -#define DEC_199 198 -#define DEC_198 197 -#define DEC_197 196 -#define DEC_196 195 -#define DEC_195 194 -#define DEC_194 193 -#define DEC_193 192 -#define DEC_192 191 -#define DEC_191 190 -#define DEC_190 189 -#define DEC_189 188 -#define DEC_188 187 -#define DEC_187 186 -#define DEC_186 185 -#define DEC_185 184 -#define DEC_184 183 -#define DEC_183 182 -#define DEC_182 181 -#define DEC_181 180 -#define DEC_180 179 -#define DEC_179 178 -#define DEC_178 177 -#define DEC_177 176 -#define DEC_176 175 -#define DEC_175 174 -#define DEC_174 173 -#define DEC_173 172 -#define DEC_172 171 -#define DEC_171 170 -#define DEC_170 169 -#define DEC_169 168 -#define DEC_168 167 -#define DEC_167 166 -#define DEC_166 165 -#define DEC_165 164 -#define DEC_164 163 -#define DEC_163 162 -#define DEC_162 161 -#define DEC_161 160 -#define DEC_160 159 -#define DEC_159 158 -#define DEC_158 157 -#define DEC_157 156 -#define DEC_156 155 -#define DEC_155 154 -#define DEC_154 153 -#define DEC_153 152 -#define DEC_152 151 -#define DEC_151 150 -#define DEC_150 149 -#define DEC_149 148 -#define DEC_148 147 -#define DEC_147 146 -#define DEC_146 145 -#define DEC_145 144 -#define DEC_144 143 -#define DEC_143 142 -#define DEC_142 141 -#define DEC_141 140 -#define DEC_140 139 -#define DEC_139 138 -#define DEC_138 137 -#define DEC_137 136 -#define DEC_136 135 -#define DEC_135 134 -#define DEC_134 133 -#define DEC_133 132 -#define DEC_132 131 -#define DEC_131 130 -#define DEC_130 129 -#define DEC_129 128 -#define DEC_128 127 -#define DEC_127 126 -#define DEC_126 125 -#define DEC_125 124 -#define DEC_124 123 -#define DEC_123 122 -#define DEC_122 121 -#define DEC_121 120 -#define DEC_120 119 -#define DEC_119 118 -#define DEC_118 117 -#define DEC_117 116 -#define DEC_116 115 -#define DEC_115 114 -#define DEC_114 113 -#define DEC_113 112 -#define DEC_112 111 -#define DEC_111 110 -#define DEC_110 109 -#define DEC_109 108 -#define DEC_108 107 -#define DEC_107 106 -#define DEC_106 105 -#define DEC_105 104 -#define DEC_104 103 -#define DEC_103 102 -#define DEC_102 101 -#define DEC_101 100 -#define DEC_100 99 -#define DEC_99 98 -#define DEC_98 97 -#define DEC_97 96 -#define DEC_96 95 -#define DEC_95 94 -#define DEC_94 93 -#define DEC_93 92 -#define DEC_92 91 -#define DEC_91 90 -#define DEC_90 89 -#define DEC_89 88 -#define DEC_88 87 -#define DEC_87 86 -#define DEC_86 85 -#define DEC_85 84 -#define DEC_84 83 -#define DEC_83 82 -#define DEC_82 81 -#define DEC_81 80 -#define DEC_80 79 -#define DEC_79 78 -#define DEC_78 77 -#define DEC_77 76 -#define DEC_76 75 -#define DEC_75 74 -#define DEC_74 73 -#define DEC_73 72 -#define DEC_72 71 -#define DEC_71 70 -#define DEC_70 69 -#define DEC_69 68 -#define DEC_68 67 -#define DEC_67 66 -#define DEC_66 65 -#define DEC_65 64 -#define DEC_64 63 -#define DEC_63 62 -#define DEC_62 61 -#define DEC_61 60 -#define DEC_60 59 -#define DEC_59 58 -#define DEC_58 57 -#define DEC_57 56 -#define DEC_56 55 -#define DEC_55 54 -#define DEC_54 53 -#define DEC_53 52 -#define DEC_52 51 -#define DEC_51 50 -#define DEC_50 49 -#define DEC_49 48 -#define DEC_48 47 -#define DEC_47 46 -#define DEC_46 45 -#define DEC_45 44 -#define DEC_44 43 -#define DEC_43 42 -#define DEC_42 41 -#define DEC_41 40 -#define DEC_40 39 -#define DEC_39 38 -#define DEC_38 37 -#define DEC_37 36 -#define DEC_36 35 -#define DEC_35 34 -#define DEC_34 33 -#define DEC_33 32 -#define DEC_32 31 -#define DEC_31 30 -#define DEC_30 29 -#define DEC_29 28 -#define DEC_28 27 -#define DEC_27 26 -#define DEC_26 25 -#define DEC_25 24 -#define DEC_24 23 -#define DEC_23 22 -#define DEC_22 21 -#define DEC_21 20 -#define DEC_20 19 -#define DEC_19 18 -#define DEC_18 17 -#define DEC_17 16 -#define DEC_16 15 -#define DEC_15 14 -#define DEC_14 13 -#define DEC_13 12 -#define DEC_12 11 -#define DEC_11 10 -#define DEC_10 9 -#define DEC_9 8 -#define DEC_8 7 -#define DEC_7 6 -#define DEC_6 5 -#define DEC_5 4 -#define DEC_4 3 -#define DEC_3 2 -#define DEC_2 1 -#define DEC_1 0 -#define DEC_(n) DEC_##n - - -/** Maximal number of repetitions supported by MRECURSION. */ -#define MRECURSION_LIMIT 256 - -/** \brief Macro recursion. - * - * This macro represents a horizontal repetition construct. - * - * \param[in] count The number of repetitious calls to macro. Valid values - * range from 0 to MRECURSION_LIMIT. - * \param[in] macro A binary operation of the form macro(data, n). This macro - * is expanded by MRECURSION with the current repetition number - * and the auxiliary data argument. - * \param[in] data A recursive threshold, building on this to decline by times - * defined with param count. - * - * \return macro(data-count+1,0) macro(data-count+2,1)...macro(data,count-1) - */ -#define MRECURSION(count, macro, data) TPASTE2(MRECURSION, count) (macro, data) - -#define MRECURSION0( macro, data) -#define MRECURSION1( macro, data) MRECURSION0( macro, DEC_(data)) macro(data, 0) -#define MRECURSION2( macro, data) MRECURSION1( macro, DEC_(data)) macro(data, 1) -#define MRECURSION3( macro, data) MRECURSION2( macro, DEC_(data)) macro(data, 2) -#define MRECURSION4( macro, data) MRECURSION3( macro, DEC_(data)) macro(data, 3) -#define MRECURSION5( macro, data) MRECURSION4( macro, DEC_(data)) macro(data, 4) -#define MRECURSION6( macro, data) MRECURSION5( macro, DEC_(data)) macro(data, 5) -#define MRECURSION7( macro, data) MRECURSION6( macro, DEC_(data)) macro(data, 6) -#define MRECURSION8( macro, data) MRECURSION7( macro, DEC_(data)) macro(data, 7) -#define MRECURSION9( macro, data) MRECURSION8( macro, DEC_(data)) macro(data, 8) -#define MRECURSION10( macro, data) MRECURSION9( macro, DEC_(data)) macro(data, 9) -#define MRECURSION11( macro, data) MRECURSION10( macro, DEC_(data)) macro(data, 10) -#define MRECURSION12( macro, data) MRECURSION11( macro, DEC_(data)) macro(data, 11) -#define MRECURSION13( macro, data) MRECURSION12( macro, DEC_(data)) macro(data, 12) -#define MRECURSION14( macro, data) MRECURSION13( macro, DEC_(data)) macro(data, 13) -#define MRECURSION15( macro, data) MRECURSION14( macro, DEC_(data)) macro(data, 14) -#define MRECURSION16( macro, data) MRECURSION15( macro, DEC_(data)) macro(data, 15) -#define MRECURSION17( macro, data) MRECURSION16( macro, DEC_(data)) macro(data, 16) -#define MRECURSION18( macro, data) MRECURSION17( macro, DEC_(data)) macro(data, 17) -#define MRECURSION19( macro, data) MRECURSION18( macro, DEC_(data)) macro(data, 18) -#define MRECURSION20( macro, data) MRECURSION19( macro, DEC_(data)) macro(data, 19) -#define MRECURSION21( macro, data) MRECURSION20( macro, DEC_(data)) macro(data, 20) -#define MRECURSION22( macro, data) MRECURSION21( macro, DEC_(data)) macro(data, 21) -#define MRECURSION23( macro, data) MRECURSION22( macro, DEC_(data)) macro(data, 22) -#define MRECURSION24( macro, data) MRECURSION23( macro, DEC_(data)) macro(data, 23) -#define MRECURSION25( macro, data) MRECURSION24( macro, DEC_(data)) macro(data, 24) -#define MRECURSION26( macro, data) MRECURSION25( macro, DEC_(data)) macro(data, 25) -#define MRECURSION27( macro, data) MRECURSION26( macro, DEC_(data)) macro(data, 26) -#define MRECURSION28( macro, data) MRECURSION27( macro, DEC_(data)) macro(data, 27) -#define MRECURSION29( macro, data) MRECURSION28( macro, DEC_(data)) macro(data, 28) -#define MRECURSION30( macro, data) MRECURSION29( macro, DEC_(data)) macro(data, 29) -#define MRECURSION31( macro, data) MRECURSION30( macro, DEC_(data)) macro(data, 30) -#define MRECURSION32( macro, data) MRECURSION31( macro, DEC_(data)) macro(data, 31) -#define MRECURSION33( macro, data) MRECURSION32( macro, DEC_(data)) macro(data, 32) -#define MRECURSION34( macro, data) MRECURSION33( macro, DEC_(data)) macro(data, 33) -#define MRECURSION35( macro, data) MRECURSION34( macro, DEC_(data)) macro(data, 34) -#define MRECURSION36( macro, data) MRECURSION35( macro, DEC_(data)) macro(data, 35) -#define MRECURSION37( macro, data) MRECURSION36( macro, DEC_(data)) macro(data, 36) -#define MRECURSION38( macro, data) MRECURSION37( macro, DEC_(data)) macro(data, 37) -#define MRECURSION39( macro, data) MRECURSION38( macro, DEC_(data)) macro(data, 38) -#define MRECURSION40( macro, data) MRECURSION39( macro, DEC_(data)) macro(data, 39) -#define MRECURSION41( macro, data) MRECURSION40( macro, DEC_(data)) macro(data, 40) -#define MRECURSION42( macro, data) MRECURSION41( macro, DEC_(data)) macro(data, 41) -#define MRECURSION43( macro, data) MRECURSION42( macro, DEC_(data)) macro(data, 42) -#define MRECURSION44( macro, data) MRECURSION43( macro, DEC_(data)) macro(data, 43) -#define MRECURSION45( macro, data) MRECURSION44( macro, DEC_(data)) macro(data, 44) -#define MRECURSION46( macro, data) MRECURSION45( macro, DEC_(data)) macro(data, 45) -#define MRECURSION47( macro, data) MRECURSION46( macro, DEC_(data)) macro(data, 46) -#define MRECURSION48( macro, data) MRECURSION47( macro, DEC_(data)) macro(data, 47) -#define MRECURSION49( macro, data) MRECURSION48( macro, DEC_(data)) macro(data, 48) -#define MRECURSION50( macro, data) MRECURSION49( macro, DEC_(data)) macro(data, 49) -#define MRECURSION51( macro, data) MRECURSION50( macro, DEC_(data)) macro(data, 50) -#define MRECURSION52( macro, data) MRECURSION51( macro, DEC_(data)) macro(data, 51) -#define MRECURSION53( macro, data) MRECURSION52( macro, DEC_(data)) macro(data, 52) -#define MRECURSION54( macro, data) MRECURSION53( macro, DEC_(data)) macro(data, 53) -#define MRECURSION55( macro, data) MRECURSION54( macro, DEC_(data)) macro(data, 54) -#define MRECURSION56( macro, data) MRECURSION55( macro, DEC_(data)) macro(data, 55) -#define MRECURSION57( macro, data) MRECURSION56( macro, DEC_(data)) macro(data, 56) -#define MRECURSION58( macro, data) MRECURSION57( macro, DEC_(data)) macro(data, 57) -#define MRECURSION59( macro, data) MRECURSION58( macro, DEC_(data)) macro(data, 58) -#define MRECURSION60( macro, data) MRECURSION59( macro, DEC_(data)) macro(data, 59) -#define MRECURSION61( macro, data) MRECURSION60( macro, DEC_(data)) macro(data, 60) -#define MRECURSION62( macro, data) MRECURSION61( macro, DEC_(data)) macro(data, 61) -#define MRECURSION63( macro, data) MRECURSION62( macro, DEC_(data)) macro(data, 62) -#define MRECURSION64( macro, data) MRECURSION63( macro, DEC_(data)) macro(data, 63) -#define MRECURSION65( macro, data) MRECURSION64( macro, DEC_(data)) macro(data, 64) -#define MRECURSION66( macro, data) MRECURSION65( macro, DEC_(data)) macro(data, 65) -#define MRECURSION67( macro, data) MRECURSION66( macro, DEC_(data)) macro(data, 66) -#define MRECURSION68( macro, data) MRECURSION67( macro, DEC_(data)) macro(data, 67) -#define MRECURSION69( macro, data) MRECURSION68( macro, DEC_(data)) macro(data, 68) -#define MRECURSION70( macro, data) MRECURSION69( macro, DEC_(data)) macro(data, 69) -#define MRECURSION71( macro, data) MRECURSION70( macro, DEC_(data)) macro(data, 70) -#define MRECURSION72( macro, data) MRECURSION71( macro, DEC_(data)) macro(data, 71) -#define MRECURSION73( macro, data) MRECURSION72( macro, DEC_(data)) macro(data, 72) -#define MRECURSION74( macro, data) MRECURSION73( macro, DEC_(data)) macro(data, 73) -#define MRECURSION75( macro, data) MRECURSION74( macro, DEC_(data)) macro(data, 74) -#define MRECURSION76( macro, data) MRECURSION75( macro, DEC_(data)) macro(data, 75) -#define MRECURSION77( macro, data) MRECURSION76( macro, DEC_(data)) macro(data, 76) -#define MRECURSION78( macro, data) MRECURSION77( macro, DEC_(data)) macro(data, 77) -#define MRECURSION79( macro, data) MRECURSION78( macro, DEC_(data)) macro(data, 78) -#define MRECURSION80( macro, data) MRECURSION79( macro, DEC_(data)) macro(data, 79) -#define MRECURSION81( macro, data) MRECURSION80( macro, DEC_(data)) macro(data, 80) -#define MRECURSION82( macro, data) MRECURSION81( macro, DEC_(data)) macro(data, 81) -#define MRECURSION83( macro, data) MRECURSION82( macro, DEC_(data)) macro(data, 82) -#define MRECURSION84( macro, data) MRECURSION83( macro, DEC_(data)) macro(data, 83) -#define MRECURSION85( macro, data) MRECURSION84( macro, DEC_(data)) macro(data, 84) -#define MRECURSION86( macro, data) MRECURSION85( macro, DEC_(data)) macro(data, 85) -#define MRECURSION87( macro, data) MRECURSION86( macro, DEC_(data)) macro(data, 86) -#define MRECURSION88( macro, data) MRECURSION87( macro, DEC_(data)) macro(data, 87) -#define MRECURSION89( macro, data) MRECURSION88( macro, DEC_(data)) macro(data, 88) -#define MRECURSION90( macro, data) MRECURSION89( macro, DEC_(data)) macro(data, 89) -#define MRECURSION91( macro, data) MRECURSION90( macro, DEC_(data)) macro(data, 90) -#define MRECURSION92( macro, data) MRECURSION91( macro, DEC_(data)) macro(data, 91) -#define MRECURSION93( macro, data) MRECURSION92( macro, DEC_(data)) macro(data, 92) -#define MRECURSION94( macro, data) MRECURSION93( macro, DEC_(data)) macro(data, 93) -#define MRECURSION95( macro, data) MRECURSION94( macro, DEC_(data)) macro(data, 94) -#define MRECURSION96( macro, data) MRECURSION95( macro, DEC_(data)) macro(data, 95) -#define MRECURSION97( macro, data) MRECURSION96( macro, DEC_(data)) macro(data, 96) -#define MRECURSION98( macro, data) MRECURSION97( macro, DEC_(data)) macro(data, 97) -#define MRECURSION99( macro, data) MRECURSION98( macro, DEC_(data)) macro(data, 98) -#define MRECURSION100(macro, data) MRECURSION99( macro, DEC_(data)) macro(data, 99) -#define MRECURSION101(macro, data) MRECURSION100( macro, DEC_(data)) macro(data, 100) -#define MRECURSION102(macro, data) MRECURSION101( macro, DEC_(data)) macro(data, 101) -#define MRECURSION103(macro, data) MRECURSION102( macro, DEC_(data)) macro(data, 102) -#define MRECURSION104(macro, data) MRECURSION103( macro, DEC_(data)) macro(data, 103) -#define MRECURSION105(macro, data) MRECURSION104( macro, DEC_(data)) macro(data, 104) -#define MRECURSION106(macro, data) MRECURSION105( macro, DEC_(data)) macro(data, 105) -#define MRECURSION107(macro, data) MRECURSION106( macro, DEC_(data)) macro(data, 106) -#define MRECURSION108(macro, data) MRECURSION107( macro, DEC_(data)) macro(data, 107) -#define MRECURSION109(macro, data) MRECURSION108( macro, DEC_(data)) macro(data, 108) -#define MRECURSION110(macro, data) MRECURSION109( macro, DEC_(data)) macro(data, 109) -#define MRECURSION111(macro, data) MRECURSION110( macro, DEC_(data)) macro(data, 110) -#define MRECURSION112(macro, data) MRECURSION111( macro, DEC_(data)) macro(data, 111) -#define MRECURSION113(macro, data) MRECURSION112( macro, DEC_(data)) macro(data, 112) -#define MRECURSION114(macro, data) MRECURSION113( macro, DEC_(data)) macro(data, 113) -#define MRECURSION115(macro, data) MRECURSION114( macro, DEC_(data)) macro(data, 114) -#define MRECURSION116(macro, data) MRECURSION115( macro, DEC_(data)) macro(data, 115) -#define MRECURSION117(macro, data) MRECURSION116( macro, DEC_(data)) macro(data, 116) -#define MRECURSION118(macro, data) MRECURSION117( macro, DEC_(data)) macro(data, 117) -#define MRECURSION119(macro, data) MRECURSION118( macro, DEC_(data)) macro(data, 118) -#define MRECURSION120(macro, data) MRECURSION119( macro, DEC_(data)) macro(data, 119) -#define MRECURSION121(macro, data) MRECURSION120( macro, DEC_(data)) macro(data, 120) -#define MRECURSION122(macro, data) MRECURSION121( macro, DEC_(data)) macro(data, 121) -#define MRECURSION123(macro, data) MRECURSION122( macro, DEC_(data)) macro(data, 122) -#define MRECURSION124(macro, data) MRECURSION123( macro, DEC_(data)) macro(data, 123) -#define MRECURSION125(macro, data) MRECURSION124( macro, DEC_(data)) macro(data, 124) -#define MRECURSION126(macro, data) MRECURSION125( macro, DEC_(data)) macro(data, 125) -#define MRECURSION127(macro, data) MRECURSION126( macro, DEC_(data)) macro(data, 126) -#define MRECURSION128(macro, data) MRECURSION127( macro, DEC_(data)) macro(data, 127) -#define MRECURSION129(macro, data) MRECURSION128( macro, DEC_(data)) macro(data, 128) -#define MRECURSION130(macro, data) MRECURSION129( macro, DEC_(data)) macro(data, 129) -#define MRECURSION131(macro, data) MRECURSION130( macro, DEC_(data)) macro(data, 130) -#define MRECURSION132(macro, data) MRECURSION131( macro, DEC_(data)) macro(data, 131) -#define MRECURSION133(macro, data) MRECURSION132( macro, DEC_(data)) macro(data, 132) -#define MRECURSION134(macro, data) MRECURSION133( macro, DEC_(data)) macro(data, 133) -#define MRECURSION135(macro, data) MRECURSION134( macro, DEC_(data)) macro(data, 134) -#define MRECURSION136(macro, data) MRECURSION135( macro, DEC_(data)) macro(data, 135) -#define MRECURSION137(macro, data) MRECURSION136( macro, DEC_(data)) macro(data, 136) -#define MRECURSION138(macro, data) MRECURSION137( macro, DEC_(data)) macro(data, 137) -#define MRECURSION139(macro, data) MRECURSION138( macro, DEC_(data)) macro(data, 138) -#define MRECURSION140(macro, data) MRECURSION139( macro, DEC_(data)) macro(data, 139) -#define MRECURSION141(macro, data) MRECURSION140( macro, DEC_(data)) macro(data, 140) -#define MRECURSION142(macro, data) MRECURSION141( macro, DEC_(data)) macro(data, 141) -#define MRECURSION143(macro, data) MRECURSION142( macro, DEC_(data)) macro(data, 142) -#define MRECURSION144(macro, data) MRECURSION143( macro, DEC_(data)) macro(data, 143) -#define MRECURSION145(macro, data) MRECURSION144( macro, DEC_(data)) macro(data, 144) -#define MRECURSION146(macro, data) MRECURSION145( macro, DEC_(data)) macro(data, 145) -#define MRECURSION147(macro, data) MRECURSION146( macro, DEC_(data)) macro(data, 146) -#define MRECURSION148(macro, data) MRECURSION147( macro, DEC_(data)) macro(data, 147) -#define MRECURSION149(macro, data) MRECURSION148( macro, DEC_(data)) macro(data, 148) -#define MRECURSION150(macro, data) MRECURSION149( macro, DEC_(data)) macro(data, 149) -#define MRECURSION151(macro, data) MRECURSION150( macro, DEC_(data)) macro(data, 150) -#define MRECURSION152(macro, data) MRECURSION151( macro, DEC_(data)) macro(data, 151) -#define MRECURSION153(macro, data) MRECURSION152( macro, DEC_(data)) macro(data, 152) -#define MRECURSION154(macro, data) MRECURSION153( macro, DEC_(data)) macro(data, 153) -#define MRECURSION155(macro, data) MRECURSION154( macro, DEC_(data)) macro(data, 154) -#define MRECURSION156(macro, data) MRECURSION155( macro, DEC_(data)) macro(data, 155) -#define MRECURSION157(macro, data) MRECURSION156( macro, DEC_(data)) macro(data, 156) -#define MRECURSION158(macro, data) MRECURSION157( macro, DEC_(data)) macro(data, 157) -#define MRECURSION159(macro, data) MRECURSION158( macro, DEC_(data)) macro(data, 158) -#define MRECURSION160(macro, data) MRECURSION159( macro, DEC_(data)) macro(data, 159) -#define MRECURSION161(macro, data) MRECURSION160( macro, DEC_(data)) macro(data, 160) -#define MRECURSION162(macro, data) MRECURSION161( macro, DEC_(data)) macro(data, 161) -#define MRECURSION163(macro, data) MRECURSION162( macro, DEC_(data)) macro(data, 162) -#define MRECURSION164(macro, data) MRECURSION163( macro, DEC_(data)) macro(data, 163) -#define MRECURSION165(macro, data) MRECURSION164( macro, DEC_(data)) macro(data, 164) -#define MRECURSION166(macro, data) MRECURSION165( macro, DEC_(data)) macro(data, 165) -#define MRECURSION167(macro, data) MRECURSION166( macro, DEC_(data)) macro(data, 166) -#define MRECURSION168(macro, data) MRECURSION167( macro, DEC_(data)) macro(data, 167) -#define MRECURSION169(macro, data) MRECURSION168( macro, DEC_(data)) macro(data, 168) -#define MRECURSION170(macro, data) MRECURSION169( macro, DEC_(data)) macro(data, 169) -#define MRECURSION171(macro, data) MRECURSION170( macro, DEC_(data)) macro(data, 170) -#define MRECURSION172(macro, data) MRECURSION171( macro, DEC_(data)) macro(data, 171) -#define MRECURSION173(macro, data) MRECURSION172( macro, DEC_(data)) macro(data, 172) -#define MRECURSION174(macro, data) MRECURSION173( macro, DEC_(data)) macro(data, 173) -#define MRECURSION175(macro, data) MRECURSION174( macro, DEC_(data)) macro(data, 174) -#define MRECURSION176(macro, data) MRECURSION175( macro, DEC_(data)) macro(data, 175) -#define MRECURSION177(macro, data) MRECURSION176( macro, DEC_(data)) macro(data, 176) -#define MRECURSION178(macro, data) MRECURSION177( macro, DEC_(data)) macro(data, 177) -#define MRECURSION179(macro, data) MRECURSION178( macro, DEC_(data)) macro(data, 178) -#define MRECURSION180(macro, data) MRECURSION179( macro, DEC_(data)) macro(data, 179) -#define MRECURSION181(macro, data) MRECURSION180( macro, DEC_(data)) macro(data, 180) -#define MRECURSION182(macro, data) MRECURSION181( macro, DEC_(data)) macro(data, 181) -#define MRECURSION183(macro, data) MRECURSION182( macro, DEC_(data)) macro(data, 182) -#define MRECURSION184(macro, data) MRECURSION183( macro, DEC_(data)) macro(data, 183) -#define MRECURSION185(macro, data) MRECURSION184( macro, DEC_(data)) macro(data, 184) -#define MRECURSION186(macro, data) MRECURSION185( macro, DEC_(data)) macro(data, 185) -#define MRECURSION187(macro, data) MRECURSION186( macro, DEC_(data)) macro(data, 186) -#define MRECURSION188(macro, data) MRECURSION187( macro, DEC_(data)) macro(data, 187) -#define MRECURSION189(macro, data) MRECURSION188( macro, DEC_(data)) macro(data, 188) -#define MRECURSION190(macro, data) MRECURSION189( macro, DEC_(data)) macro(data, 189) -#define MRECURSION191(macro, data) MRECURSION190( macro, DEC_(data)) macro(data, 190) -#define MRECURSION192(macro, data) MRECURSION191( macro, DEC_(data)) macro(data, 191) -#define MRECURSION193(macro, data) MRECURSION192( macro, DEC_(data)) macro(data, 192) -#define MRECURSION194(macro, data) MRECURSION193( macro, DEC_(data)) macro(data, 193) -#define MRECURSION195(macro, data) MRECURSION194( macro, DEC_(data)) macro(data, 194) -#define MRECURSION196(macro, data) MRECURSION195( macro, DEC_(data)) macro(data, 195) -#define MRECURSION197(macro, data) MRECURSION196( macro, DEC_(data)) macro(data, 196) -#define MRECURSION198(macro, data) MRECURSION197( macro, DEC_(data)) macro(data, 197) -#define MRECURSION199(macro, data) MRECURSION198( macro, DEC_(data)) macro(data, 198) -#define MRECURSION200(macro, data) MRECURSION199( macro, DEC_(data)) macro(data, 199) -#define MRECURSION201(macro, data) MRECURSION200( macro, DEC_(data)) macro(data, 200) -#define MRECURSION202(macro, data) MRECURSION201( macro, DEC_(data)) macro(data, 201) -#define MRECURSION203(macro, data) MRECURSION202( macro, DEC_(data)) macro(data, 202) -#define MRECURSION204(macro, data) MRECURSION203( macro, DEC_(data)) macro(data, 203) -#define MRECURSION205(macro, data) MRECURSION204( macro, DEC_(data)) macro(data, 204) -#define MRECURSION206(macro, data) MRECURSION205( macro, DEC_(data)) macro(data, 205) -#define MRECURSION207(macro, data) MRECURSION206( macro, DEC_(data)) macro(data, 206) -#define MRECURSION208(macro, data) MRECURSION207( macro, DEC_(data)) macro(data, 207) -#define MRECURSION209(macro, data) MRECURSION208( macro, DEC_(data)) macro(data, 208) -#define MRECURSION210(macro, data) MRECURSION209( macro, DEC_(data)) macro(data, 209) -#define MRECURSION211(macro, data) MRECURSION210( macro, DEC_(data)) macro(data, 210) -#define MRECURSION212(macro, data) MRECURSION211( macro, DEC_(data)) macro(data, 211) -#define MRECURSION213(macro, data) MRECURSION212( macro, DEC_(data)) macro(data, 212) -#define MRECURSION214(macro, data) MRECURSION213( macro, DEC_(data)) macro(data, 213) -#define MRECURSION215(macro, data) MRECURSION214( macro, DEC_(data)) macro(data, 214) -#define MRECURSION216(macro, data) MRECURSION215( macro, DEC_(data)) macro(data, 215) -#define MRECURSION217(macro, data) MRECURSION216( macro, DEC_(data)) macro(data, 216) -#define MRECURSION218(macro, data) MRECURSION217( macro, DEC_(data)) macro(data, 217) -#define MRECURSION219(macro, data) MRECURSION218( macro, DEC_(data)) macro(data, 218) -#define MRECURSION220(macro, data) MRECURSION219( macro, DEC_(data)) macro(data, 219) -#define MRECURSION221(macro, data) MRECURSION220( macro, DEC_(data)) macro(data, 220) -#define MRECURSION222(macro, data) MRECURSION221( macro, DEC_(data)) macro(data, 221) -#define MRECURSION223(macro, data) MRECURSION222( macro, DEC_(data)) macro(data, 222) -#define MRECURSION224(macro, data) MRECURSION223( macro, DEC_(data)) macro(data, 223) -#define MRECURSION225(macro, data) MRECURSION224( macro, DEC_(data)) macro(data, 224) -#define MRECURSION226(macro, data) MRECURSION225( macro, DEC_(data)) macro(data, 225) -#define MRECURSION227(macro, data) MRECURSION226( macro, DEC_(data)) macro(data, 226) -#define MRECURSION228(macro, data) MRECURSION227( macro, DEC_(data)) macro(data, 227) -#define MRECURSION229(macro, data) MRECURSION228( macro, DEC_(data)) macro(data, 228) -#define MRECURSION230(macro, data) MRECURSION229( macro, DEC_(data)) macro(data, 229) -#define MRECURSION231(macro, data) MRECURSION230( macro, DEC_(data)) macro(data, 230) -#define MRECURSION232(macro, data) MRECURSION231( macro, DEC_(data)) macro(data, 231) -#define MRECURSION233(macro, data) MRECURSION232( macro, DEC_(data)) macro(data, 232) -#define MRECURSION234(macro, data) MRECURSION233( macro, DEC_(data)) macro(data, 233) -#define MRECURSION235(macro, data) MRECURSION234( macro, DEC_(data)) macro(data, 234) -#define MRECURSION236(macro, data) MRECURSION235( macro, DEC_(data)) macro(data, 235) -#define MRECURSION237(macro, data) MRECURSION236( macro, DEC_(data)) macro(data, 236) -#define MRECURSION238(macro, data) MRECURSION237( macro, DEC_(data)) macro(data, 237) -#define MRECURSION239(macro, data) MRECURSION238( macro, DEC_(data)) macro(data, 238) -#define MRECURSION240(macro, data) MRECURSION239( macro, DEC_(data)) macro(data, 239) -#define MRECURSION241(macro, data) MRECURSION240( macro, DEC_(data)) macro(data, 240) -#define MRECURSION242(macro, data) MRECURSION241( macro, DEC_(data)) macro(data, 241) -#define MRECURSION243(macro, data) MRECURSION242( macro, DEC_(data)) macro(data, 242) -#define MRECURSION244(macro, data) MRECURSION243( macro, DEC_(data)) macro(data, 243) -#define MRECURSION245(macro, data) MRECURSION244( macro, DEC_(data)) macro(data, 244) -#define MRECURSION246(macro, data) MRECURSION245( macro, DEC_(data)) macro(data, 245) -#define MRECURSION247(macro, data) MRECURSION246( macro, DEC_(data)) macro(data, 246) -#define MRECURSION248(macro, data) MRECURSION247( macro, DEC_(data)) macro(data, 247) -#define MRECURSION249(macro, data) MRECURSION248( macro, DEC_(data)) macro(data, 248) -#define MRECURSION250(macro, data) MRECURSION249( macro, DEC_(data)) macro(data, 249) -#define MRECURSION251(macro, data) MRECURSION250( macro, DEC_(data)) macro(data, 250) -#define MRECURSION252(macro, data) MRECURSION251( macro, DEC_(data)) macro(data, 251) -#define MRECURSION253(macro, data) MRECURSION252( macro, DEC_(data)) macro(data, 252) -#define MRECURSION254(macro, data) MRECURSION253( macro, DEC_(data)) macro(data, 253) -#define MRECURSION255(macro, data) MRECURSION254( macro, DEC_(data)) macro(data, 254) -#define MRECURSION256(macro, data) MRECURSION255( macro, DEC_(data)) macro(data, 255) - -/** @} */ - -#endif /* _MRECURSION_H_ */ diff --git a/atmel-samd/asf/sam0/utils/preprocessor/mrepeat.h b/atmel-samd/asf/sam0/utils/preprocessor/mrepeat.h deleted file mode 100644 index b8c08c89dc492..0000000000000 --- a/atmel-samd/asf/sam0/utils/preprocessor/mrepeat.h +++ /dev/null @@ -1,338 +0,0 @@ -/** - * \file - * - * \brief Preprocessor macro repeating utils. - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _MREPEAT_H_ -#define _MREPEAT_H_ - -/** - * \defgroup group_sam0_utils_mrepeat Preprocessor - Macro Repeat - * - * \ingroup group_sam0_utils - * - * @{ - */ - -#include "preprocessor.h" - -/** Maximal number of repetitions supported by MREPEAT. */ -#define MREPEAT_LIMIT 256 - -/** \brief Macro repeat. - * - * This macro represents a horizontal repetition construct. - * - * \param[in] count The number of repetitious calls to macro. Valid values - * range from 0 to MREPEAT_LIMIT. - * \param[in] macro A binary operation of the form macro(n, data). This macro - * is expanded by MREPEAT with the current repetition number - * and the auxiliary data argument. - * \param[in] data Auxiliary data passed to macro. - * - * \return macro(0, data) macro(1, data) ... macro(count - 1, data) - */ -#define MREPEAT(count, macro, data) TPASTE2(MREPEAT, count) (macro, data) - -#define MREPEAT0( macro, data) -#define MREPEAT1( macro, data) MREPEAT0( macro, data) macro( 0, data) -#define MREPEAT2( macro, data) MREPEAT1( macro, data) macro( 1, data) -#define MREPEAT3( macro, data) MREPEAT2( macro, data) macro( 2, data) -#define MREPEAT4( macro, data) MREPEAT3( macro, data) macro( 3, data) -#define MREPEAT5( macro, data) MREPEAT4( macro, data) macro( 4, data) -#define MREPEAT6( macro, data) MREPEAT5( macro, data) macro( 5, data) -#define MREPEAT7( macro, data) MREPEAT6( macro, data) macro( 6, data) -#define MREPEAT8( macro, data) MREPEAT7( macro, data) macro( 7, data) -#define MREPEAT9( macro, data) MREPEAT8( macro, data) macro( 8, data) -#define MREPEAT10( macro, data) MREPEAT9( macro, data) macro( 9, data) -#define MREPEAT11( macro, data) MREPEAT10( macro, data) macro( 10, data) -#define MREPEAT12( macro, data) MREPEAT11( macro, data) macro( 11, data) -#define MREPEAT13( macro, data) MREPEAT12( macro, data) macro( 12, data) -#define MREPEAT14( macro, data) MREPEAT13( macro, data) macro( 13, data) -#define MREPEAT15( macro, data) MREPEAT14( macro, data) macro( 14, data) -#define MREPEAT16( macro, data) MREPEAT15( macro, data) macro( 15, data) -#define MREPEAT17( macro, data) MREPEAT16( macro, data) macro( 16, data) -#define MREPEAT18( macro, data) MREPEAT17( macro, data) macro( 17, data) -#define MREPEAT19( macro, data) MREPEAT18( macro, data) macro( 18, data) -#define MREPEAT20( macro, data) MREPEAT19( macro, data) macro( 19, data) -#define MREPEAT21( macro, data) MREPEAT20( macro, data) macro( 20, data) -#define MREPEAT22( macro, data) MREPEAT21( macro, data) macro( 21, data) -#define MREPEAT23( macro, data) MREPEAT22( macro, data) macro( 22, data) -#define MREPEAT24( macro, data) MREPEAT23( macro, data) macro( 23, data) -#define MREPEAT25( macro, data) MREPEAT24( macro, data) macro( 24, data) -#define MREPEAT26( macro, data) MREPEAT25( macro, data) macro( 25, data) -#define MREPEAT27( macro, data) MREPEAT26( macro, data) macro( 26, data) -#define MREPEAT28( macro, data) MREPEAT27( macro, data) macro( 27, data) -#define MREPEAT29( macro, data) MREPEAT28( macro, data) macro( 28, data) -#define MREPEAT30( macro, data) MREPEAT29( macro, data) macro( 29, data) -#define MREPEAT31( macro, data) MREPEAT30( macro, data) macro( 30, data) -#define MREPEAT32( macro, data) MREPEAT31( macro, data) macro( 31, data) -#define MREPEAT33( macro, data) MREPEAT32( macro, data) macro( 32, data) -#define MREPEAT34( macro, data) MREPEAT33( macro, data) macro( 33, data) -#define MREPEAT35( macro, data) MREPEAT34( macro, data) macro( 34, data) -#define MREPEAT36( macro, data) MREPEAT35( macro, data) macro( 35, data) -#define MREPEAT37( macro, data) MREPEAT36( macro, data) macro( 36, data) -#define MREPEAT38( macro, data) MREPEAT37( macro, data) macro( 37, data) -#define MREPEAT39( macro, data) MREPEAT38( macro, data) macro( 38, data) -#define MREPEAT40( macro, data) MREPEAT39( macro, data) macro( 39, data) -#define MREPEAT41( macro, data) MREPEAT40( macro, data) macro( 40, data) -#define MREPEAT42( macro, data) MREPEAT41( macro, data) macro( 41, data) -#define MREPEAT43( macro, data) MREPEAT42( macro, data) macro( 42, data) -#define MREPEAT44( macro, data) MREPEAT43( macro, data) macro( 43, data) -#define MREPEAT45( macro, data) MREPEAT44( macro, data) macro( 44, data) -#define MREPEAT46( macro, data) MREPEAT45( macro, data) macro( 45, data) -#define MREPEAT47( macro, data) MREPEAT46( macro, data) macro( 46, data) -#define MREPEAT48( macro, data) MREPEAT47( macro, data) macro( 47, data) -#define MREPEAT49( macro, data) MREPEAT48( macro, data) macro( 48, data) -#define MREPEAT50( macro, data) MREPEAT49( macro, data) macro( 49, data) -#define MREPEAT51( macro, data) MREPEAT50( macro, data) macro( 50, data) -#define MREPEAT52( macro, data) MREPEAT51( macro, data) macro( 51, data) -#define MREPEAT53( macro, data) MREPEAT52( macro, data) macro( 52, data) -#define MREPEAT54( macro, data) MREPEAT53( macro, data) macro( 53, data) -#define MREPEAT55( macro, data) MREPEAT54( macro, data) macro( 54, data) -#define MREPEAT56( macro, data) MREPEAT55( macro, data) macro( 55, data) -#define MREPEAT57( macro, data) MREPEAT56( macro, data) macro( 56, data) -#define MREPEAT58( macro, data) MREPEAT57( macro, data) macro( 57, data) -#define MREPEAT59( macro, data) MREPEAT58( macro, data) macro( 58, data) -#define MREPEAT60( macro, data) MREPEAT59( macro, data) macro( 59, data) -#define MREPEAT61( macro, data) MREPEAT60( macro, data) macro( 60, data) -#define MREPEAT62( macro, data) MREPEAT61( macro, data) macro( 61, data) -#define MREPEAT63( macro, data) MREPEAT62( macro, data) macro( 62, data) -#define MREPEAT64( macro, data) MREPEAT63( macro, data) macro( 63, data) -#define MREPEAT65( macro, data) MREPEAT64( macro, data) macro( 64, data) -#define MREPEAT66( macro, data) MREPEAT65( macro, data) macro( 65, data) -#define MREPEAT67( macro, data) MREPEAT66( macro, data) macro( 66, data) -#define MREPEAT68( macro, data) MREPEAT67( macro, data) macro( 67, data) -#define MREPEAT69( macro, data) MREPEAT68( macro, data) macro( 68, data) -#define MREPEAT70( macro, data) MREPEAT69( macro, data) macro( 69, data) -#define MREPEAT71( macro, data) MREPEAT70( macro, data) macro( 70, data) -#define MREPEAT72( macro, data) MREPEAT71( macro, data) macro( 71, data) -#define MREPEAT73( macro, data) MREPEAT72( macro, data) macro( 72, data) -#define MREPEAT74( macro, data) MREPEAT73( macro, data) macro( 73, data) -#define MREPEAT75( macro, data) MREPEAT74( macro, data) macro( 74, data) -#define MREPEAT76( macro, data) MREPEAT75( macro, data) macro( 75, data) -#define MREPEAT77( macro, data) MREPEAT76( macro, data) macro( 76, data) -#define MREPEAT78( macro, data) MREPEAT77( macro, data) macro( 77, data) -#define MREPEAT79( macro, data) MREPEAT78( macro, data) macro( 78, data) -#define MREPEAT80( macro, data) MREPEAT79( macro, data) macro( 79, data) -#define MREPEAT81( macro, data) MREPEAT80( macro, data) macro( 80, data) -#define MREPEAT82( macro, data) MREPEAT81( macro, data) macro( 81, data) -#define MREPEAT83( macro, data) MREPEAT82( macro, data) macro( 82, data) -#define MREPEAT84( macro, data) MREPEAT83( macro, data) macro( 83, data) -#define MREPEAT85( macro, data) MREPEAT84( macro, data) macro( 84, data) -#define MREPEAT86( macro, data) MREPEAT85( macro, data) macro( 85, data) -#define MREPEAT87( macro, data) MREPEAT86( macro, data) macro( 86, data) -#define MREPEAT88( macro, data) MREPEAT87( macro, data) macro( 87, data) -#define MREPEAT89( macro, data) MREPEAT88( macro, data) macro( 88, data) -#define MREPEAT90( macro, data) MREPEAT89( macro, data) macro( 89, data) -#define MREPEAT91( macro, data) MREPEAT90( macro, data) macro( 90, data) -#define MREPEAT92( macro, data) MREPEAT91( macro, data) macro( 91, data) -#define MREPEAT93( macro, data) MREPEAT92( macro, data) macro( 92, data) -#define MREPEAT94( macro, data) MREPEAT93( macro, data) macro( 93, data) -#define MREPEAT95( macro, data) MREPEAT94( macro, data) macro( 94, data) -#define MREPEAT96( macro, data) MREPEAT95( macro, data) macro( 95, data) -#define MREPEAT97( macro, data) MREPEAT96( macro, data) macro( 96, data) -#define MREPEAT98( macro, data) MREPEAT97( macro, data) macro( 97, data) -#define MREPEAT99( macro, data) MREPEAT98( macro, data) macro( 98, data) -#define MREPEAT100(macro, data) MREPEAT99( macro, data) macro( 99, data) -#define MREPEAT101(macro, data) MREPEAT100(macro, data) macro(100, data) -#define MREPEAT102(macro, data) MREPEAT101(macro, data) macro(101, data) -#define MREPEAT103(macro, data) MREPEAT102(macro, data) macro(102, data) -#define MREPEAT104(macro, data) MREPEAT103(macro, data) macro(103, data) -#define MREPEAT105(macro, data) MREPEAT104(macro, data) macro(104, data) -#define MREPEAT106(macro, data) MREPEAT105(macro, data) macro(105, data) -#define MREPEAT107(macro, data) MREPEAT106(macro, data) macro(106, data) -#define MREPEAT108(macro, data) MREPEAT107(macro, data) macro(107, data) -#define MREPEAT109(macro, data) MREPEAT108(macro, data) macro(108, data) -#define MREPEAT110(macro, data) MREPEAT109(macro, data) macro(109, data) -#define MREPEAT111(macro, data) MREPEAT110(macro, data) macro(110, data) -#define MREPEAT112(macro, data) MREPEAT111(macro, data) macro(111, data) -#define MREPEAT113(macro, data) MREPEAT112(macro, data) macro(112, data) -#define MREPEAT114(macro, data) MREPEAT113(macro, data) macro(113, data) -#define MREPEAT115(macro, data) MREPEAT114(macro, data) macro(114, data) -#define MREPEAT116(macro, data) MREPEAT115(macro, data) macro(115, data) -#define MREPEAT117(macro, data) MREPEAT116(macro, data) macro(116, data) -#define MREPEAT118(macro, data) MREPEAT117(macro, data) macro(117, data) -#define MREPEAT119(macro, data) MREPEAT118(macro, data) macro(118, data) -#define MREPEAT120(macro, data) MREPEAT119(macro, data) macro(119, data) -#define MREPEAT121(macro, data) MREPEAT120(macro, data) macro(120, data) -#define MREPEAT122(macro, data) MREPEAT121(macro, data) macro(121, data) -#define MREPEAT123(macro, data) MREPEAT122(macro, data) macro(122, data) -#define MREPEAT124(macro, data) MREPEAT123(macro, data) macro(123, data) -#define MREPEAT125(macro, data) MREPEAT124(macro, data) macro(124, data) -#define MREPEAT126(macro, data) MREPEAT125(macro, data) macro(125, data) -#define MREPEAT127(macro, data) MREPEAT126(macro, data) macro(126, data) -#define MREPEAT128(macro, data) MREPEAT127(macro, data) macro(127, data) -#define MREPEAT129(macro, data) MREPEAT128(macro, data) macro(128, data) -#define MREPEAT130(macro, data) MREPEAT129(macro, data) macro(129, data) -#define MREPEAT131(macro, data) MREPEAT130(macro, data) macro(130, data) -#define MREPEAT132(macro, data) MREPEAT131(macro, data) macro(131, data) -#define MREPEAT133(macro, data) MREPEAT132(macro, data) macro(132, data) -#define MREPEAT134(macro, data) MREPEAT133(macro, data) macro(133, data) -#define MREPEAT135(macro, data) MREPEAT134(macro, data) macro(134, data) -#define MREPEAT136(macro, data) MREPEAT135(macro, data) macro(135, data) -#define MREPEAT137(macro, data) MREPEAT136(macro, data) macro(136, data) -#define MREPEAT138(macro, data) MREPEAT137(macro, data) macro(137, data) -#define MREPEAT139(macro, data) MREPEAT138(macro, data) macro(138, data) -#define MREPEAT140(macro, data) MREPEAT139(macro, data) macro(139, data) -#define MREPEAT141(macro, data) MREPEAT140(macro, data) macro(140, data) -#define MREPEAT142(macro, data) MREPEAT141(macro, data) macro(141, data) -#define MREPEAT143(macro, data) MREPEAT142(macro, data) macro(142, data) -#define MREPEAT144(macro, data) MREPEAT143(macro, data) macro(143, data) -#define MREPEAT145(macro, data) MREPEAT144(macro, data) macro(144, data) -#define MREPEAT146(macro, data) MREPEAT145(macro, data) macro(145, data) -#define MREPEAT147(macro, data) MREPEAT146(macro, data) macro(146, data) -#define MREPEAT148(macro, data) MREPEAT147(macro, data) macro(147, data) -#define MREPEAT149(macro, data) MREPEAT148(macro, data) macro(148, data) -#define MREPEAT150(macro, data) MREPEAT149(macro, data) macro(149, data) -#define MREPEAT151(macro, data) MREPEAT150(macro, data) macro(150, data) -#define MREPEAT152(macro, data) MREPEAT151(macro, data) macro(151, data) -#define MREPEAT153(macro, data) MREPEAT152(macro, data) macro(152, data) -#define MREPEAT154(macro, data) MREPEAT153(macro, data) macro(153, data) -#define MREPEAT155(macro, data) MREPEAT154(macro, data) macro(154, data) -#define MREPEAT156(macro, data) MREPEAT155(macro, data) macro(155, data) -#define MREPEAT157(macro, data) MREPEAT156(macro, data) macro(156, data) -#define MREPEAT158(macro, data) MREPEAT157(macro, data) macro(157, data) -#define MREPEAT159(macro, data) MREPEAT158(macro, data) macro(158, data) -#define MREPEAT160(macro, data) MREPEAT159(macro, data) macro(159, data) -#define MREPEAT161(macro, data) MREPEAT160(macro, data) macro(160, data) -#define MREPEAT162(macro, data) MREPEAT161(macro, data) macro(161, data) -#define MREPEAT163(macro, data) MREPEAT162(macro, data) macro(162, data) -#define MREPEAT164(macro, data) MREPEAT163(macro, data) macro(163, data) -#define MREPEAT165(macro, data) MREPEAT164(macro, data) macro(164, data) -#define MREPEAT166(macro, data) MREPEAT165(macro, data) macro(165, data) -#define MREPEAT167(macro, data) MREPEAT166(macro, data) macro(166, data) -#define MREPEAT168(macro, data) MREPEAT167(macro, data) macro(167, data) -#define MREPEAT169(macro, data) MREPEAT168(macro, data) macro(168, data) -#define MREPEAT170(macro, data) MREPEAT169(macro, data) macro(169, data) -#define MREPEAT171(macro, data) MREPEAT170(macro, data) macro(170, data) -#define MREPEAT172(macro, data) MREPEAT171(macro, data) macro(171, data) -#define MREPEAT173(macro, data) MREPEAT172(macro, data) macro(172, data) -#define MREPEAT174(macro, data) MREPEAT173(macro, data) macro(173, data) -#define MREPEAT175(macro, data) MREPEAT174(macro, data) macro(174, data) -#define MREPEAT176(macro, data) MREPEAT175(macro, data) macro(175, data) -#define MREPEAT177(macro, data) MREPEAT176(macro, data) macro(176, data) -#define MREPEAT178(macro, data) MREPEAT177(macro, data) macro(177, data) -#define MREPEAT179(macro, data) MREPEAT178(macro, data) macro(178, data) -#define MREPEAT180(macro, data) MREPEAT179(macro, data) macro(179, data) -#define MREPEAT181(macro, data) MREPEAT180(macro, data) macro(180, data) -#define MREPEAT182(macro, data) MREPEAT181(macro, data) macro(181, data) -#define MREPEAT183(macro, data) MREPEAT182(macro, data) macro(182, data) -#define MREPEAT184(macro, data) MREPEAT183(macro, data) macro(183, data) -#define MREPEAT185(macro, data) MREPEAT184(macro, data) macro(184, data) -#define MREPEAT186(macro, data) MREPEAT185(macro, data) macro(185, data) -#define MREPEAT187(macro, data) MREPEAT186(macro, data) macro(186, data) -#define MREPEAT188(macro, data) MREPEAT187(macro, data) macro(187, data) -#define MREPEAT189(macro, data) MREPEAT188(macro, data) macro(188, data) -#define MREPEAT190(macro, data) MREPEAT189(macro, data) macro(189, data) -#define MREPEAT191(macro, data) MREPEAT190(macro, data) macro(190, data) -#define MREPEAT192(macro, data) MREPEAT191(macro, data) macro(191, data) -#define MREPEAT193(macro, data) MREPEAT192(macro, data) macro(192, data) -#define MREPEAT194(macro, data) MREPEAT193(macro, data) macro(193, data) -#define MREPEAT195(macro, data) MREPEAT194(macro, data) macro(194, data) -#define MREPEAT196(macro, data) MREPEAT195(macro, data) macro(195, data) -#define MREPEAT197(macro, data) MREPEAT196(macro, data) macro(196, data) -#define MREPEAT198(macro, data) MREPEAT197(macro, data) macro(197, data) -#define MREPEAT199(macro, data) MREPEAT198(macro, data) macro(198, data) -#define MREPEAT200(macro, data) MREPEAT199(macro, data) macro(199, data) -#define MREPEAT201(macro, data) MREPEAT200(macro, data) macro(200, data) -#define MREPEAT202(macro, data) MREPEAT201(macro, data) macro(201, data) -#define MREPEAT203(macro, data) MREPEAT202(macro, data) macro(202, data) -#define MREPEAT204(macro, data) MREPEAT203(macro, data) macro(203, data) -#define MREPEAT205(macro, data) MREPEAT204(macro, data) macro(204, data) -#define MREPEAT206(macro, data) MREPEAT205(macro, data) macro(205, data) -#define MREPEAT207(macro, data) MREPEAT206(macro, data) macro(206, data) -#define MREPEAT208(macro, data) MREPEAT207(macro, data) macro(207, data) -#define MREPEAT209(macro, data) MREPEAT208(macro, data) macro(208, data) -#define MREPEAT210(macro, data) MREPEAT209(macro, data) macro(209, data) -#define MREPEAT211(macro, data) MREPEAT210(macro, data) macro(210, data) -#define MREPEAT212(macro, data) MREPEAT211(macro, data) macro(211, data) -#define MREPEAT213(macro, data) MREPEAT212(macro, data) macro(212, data) -#define MREPEAT214(macro, data) MREPEAT213(macro, data) macro(213, data) -#define MREPEAT215(macro, data) MREPEAT214(macro, data) macro(214, data) -#define MREPEAT216(macro, data) MREPEAT215(macro, data) macro(215, data) -#define MREPEAT217(macro, data) MREPEAT216(macro, data) macro(216, data) -#define MREPEAT218(macro, data) MREPEAT217(macro, data) macro(217, data) -#define MREPEAT219(macro, data) MREPEAT218(macro, data) macro(218, data) -#define MREPEAT220(macro, data) MREPEAT219(macro, data) macro(219, data) -#define MREPEAT221(macro, data) MREPEAT220(macro, data) macro(220, data) -#define MREPEAT222(macro, data) MREPEAT221(macro, data) macro(221, data) -#define MREPEAT223(macro, data) MREPEAT222(macro, data) macro(222, data) -#define MREPEAT224(macro, data) MREPEAT223(macro, data) macro(223, data) -#define MREPEAT225(macro, data) MREPEAT224(macro, data) macro(224, data) -#define MREPEAT226(macro, data) MREPEAT225(macro, data) macro(225, data) -#define MREPEAT227(macro, data) MREPEAT226(macro, data) macro(226, data) -#define MREPEAT228(macro, data) MREPEAT227(macro, data) macro(227, data) -#define MREPEAT229(macro, data) MREPEAT228(macro, data) macro(228, data) -#define MREPEAT230(macro, data) MREPEAT229(macro, data) macro(229, data) -#define MREPEAT231(macro, data) MREPEAT230(macro, data) macro(230, data) -#define MREPEAT232(macro, data) MREPEAT231(macro, data) macro(231, data) -#define MREPEAT233(macro, data) MREPEAT232(macro, data) macro(232, data) -#define MREPEAT234(macro, data) MREPEAT233(macro, data) macro(233, data) -#define MREPEAT235(macro, data) MREPEAT234(macro, data) macro(234, data) -#define MREPEAT236(macro, data) MREPEAT235(macro, data) macro(235, data) -#define MREPEAT237(macro, data) MREPEAT236(macro, data) macro(236, data) -#define MREPEAT238(macro, data) MREPEAT237(macro, data) macro(237, data) -#define MREPEAT239(macro, data) MREPEAT238(macro, data) macro(238, data) -#define MREPEAT240(macro, data) MREPEAT239(macro, data) macro(239, data) -#define MREPEAT241(macro, data) MREPEAT240(macro, data) macro(240, data) -#define MREPEAT242(macro, data) MREPEAT241(macro, data) macro(241, data) -#define MREPEAT243(macro, data) MREPEAT242(macro, data) macro(242, data) -#define MREPEAT244(macro, data) MREPEAT243(macro, data) macro(243, data) -#define MREPEAT245(macro, data) MREPEAT244(macro, data) macro(244, data) -#define MREPEAT246(macro, data) MREPEAT245(macro, data) macro(245, data) -#define MREPEAT247(macro, data) MREPEAT246(macro, data) macro(246, data) -#define MREPEAT248(macro, data) MREPEAT247(macro, data) macro(247, data) -#define MREPEAT249(macro, data) MREPEAT248(macro, data) macro(248, data) -#define MREPEAT250(macro, data) MREPEAT249(macro, data) macro(249, data) -#define MREPEAT251(macro, data) MREPEAT250(macro, data) macro(250, data) -#define MREPEAT252(macro, data) MREPEAT251(macro, data) macro(251, data) -#define MREPEAT253(macro, data) MREPEAT252(macro, data) macro(252, data) -#define MREPEAT254(macro, data) MREPEAT253(macro, data) macro(253, data) -#define MREPEAT255(macro, data) MREPEAT254(macro, data) macro(254, data) -#define MREPEAT256(macro, data) MREPEAT255(macro, data) macro(255, data) - -/** @} */ - -#endif /* _MREPEAT_H_ */ diff --git a/atmel-samd/asf/sam0/utils/preprocessor/preprocessor.h b/atmel-samd/asf/sam0/utils/preprocessor/preprocessor.h deleted file mode 100644 index 8576e1e47353e..0000000000000 --- a/atmel-samd/asf/sam0/utils/preprocessor/preprocessor.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Preprocessor utils. - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _PREPROCESSOR_H_ -#define _PREPROCESSOR_H_ - -#include "tpaste.h" -#include "stringz.h" -#include "mrepeat.h" -#include "mrecursion.h" - -#endif // _PREPROCESSOR_H_ diff --git a/atmel-samd/asf/sam0/utils/preprocessor/stringz.h b/atmel-samd/asf/sam0/utils/preprocessor/stringz.h deleted file mode 100644 index 3406048440514..0000000000000 --- a/atmel-samd/asf/sam0/utils/preprocessor/stringz.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \file - * - * \brief Preprocessor stringizing utils. - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _STRINGZ_H_ -#define _STRINGZ_H_ - -/** - * \defgroup group_sam0_utils_stringz Preprocessor - Stringize - * - * \ingroup group_sam0_utils - * - * @{ - */ - -/** \brief Stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * May be used only within macros with the token passed as an argument if the - * token is \#defined. - * - * For example, writing STRINGZ(PIN) within a macro \#defined by PIN_NAME(PIN) - * and invoked as PIN_NAME(PIN0) with PIN0 \#defined as A0 is equivalent to - * writing "A0". - */ -#define STRINGZ(x) #x - -/** \brief Absolute stringize. - * - * Stringize a preprocessing token, this token being allowed to be \#defined. - * - * No restriction of use if the token is \#defined. - * - * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 \#defined as A0 is - * equivalent to writing "A0". - */ -#define ASTRINGZ(x) STRINGZ(x) - -/** @} */ - -#endif // _STRINGZ_H_ diff --git a/atmel-samd/asf/sam0/utils/preprocessor/tpaste.h b/atmel-samd/asf/sam0/utils/preprocessor/tpaste.h deleted file mode 100644 index b1c77c623d7b0..0000000000000 --- a/atmel-samd/asf/sam0/utils/preprocessor/tpaste.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * \file - * - * \brief Preprocessor token pasting utils. - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _TPASTE_H_ -#define _TPASTE_H_ - -/** - * \defgroup group_sam0_utils_tpaste Preprocessor - Token Paste - * - * \ingroup group_sam0_utils - * - * @{ - */ - -/** \name Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. - * - * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by - * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is - * equivalent to writing U32. - * - * @{ */ -#define TPASTE2( a, b) a##b -#define TPASTE3( a, b, c) a##b##c -#define TPASTE4( a, b, c, d) a##b##c##d -#define TPASTE5( a, b, c, d, e) a##b##c##d##e -#define TPASTE6( a, b, c, d, e, f) a##b##c##d##e##f -#define TPASTE7( a, b, c, d, e, f, g) a##b##c##d##e##f##g -#define TPASTE8( a, b, c, d, e, f, g, h) a##b##c##d##e##f##g##h -#define TPASTE9( a, b, c, d, e, f, g, h, i) a##b##c##d##e##f##g##h##i -#define TPASTE10(a, b, c, d, e, f, g, h, i, j) a##b##c##d##e##f##g##h##i##j -/** @} */ - -/** \name Absolute Token Paste - * - * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. - * - * No restriction of use if the tokens are \#defined. - * - * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined - * as 32 is equivalent to writing U32. - * - * @{ */ -#define ATPASTE2( a, b) TPASTE2( a, b) -#define ATPASTE3( a, b, c) TPASTE3( a, b, c) -#define ATPASTE4( a, b, c, d) TPASTE4( a, b, c, d) -#define ATPASTE5( a, b, c, d, e) TPASTE5( a, b, c, d, e) -#define ATPASTE6( a, b, c, d, e, f) TPASTE6( a, b, c, d, e, f) -#define ATPASTE7( a, b, c, d, e, f, g) TPASTE7( a, b, c, d, e, f, g) -#define ATPASTE8( a, b, c, d, e, f, g, h) TPASTE8( a, b, c, d, e, f, g, h) -#define ATPASTE9( a, b, c, d, e, f, g, h, i) TPASTE9( a, b, c, d, e, f, g, h, i) -#define ATPASTE10(a, b, c, d, e, f, g, h, i, j) TPASTE10(a, b, c, d, e, f, g, h, i, j) -/** @} */ - -/** @} */ - -#endif // _TPASTE_H_ diff --git a/atmel-samd/asf/sam0/utils/status_codes.h b/atmel-samd/asf/sam0/utils/status_codes.h deleted file mode 100644 index 6501e7e474ec4..0000000000000 --- a/atmel-samd/asf/sam0/utils/status_codes.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - * \file - * - * \brief Status code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (C) 2012-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef STATUS_CODES_H_INCLUDED -#define STATUS_CODES_H_INCLUDED - -#include - -/** - * \defgroup group_sam0_utils_status_codes Status Codes - * - * \ingroup group_sam0_utils - * - * @{ - */ - -/** Mask to retrieve the error category of a status code. */ -#define STATUS_CATEGORY_MASK 0xF0 - -/** Mask to retrieve the error code within the category of a status code. */ -#define STATUS_ERROR_MASK 0x0F - -/** Status code error categories. */ -enum status_categories { - STATUS_CATEGORY_OK = 0x00, - STATUS_CATEGORY_COMMON = 0x10, - STATUS_CATEGORY_ANALOG = 0x30, - STATUS_CATEGORY_COM = 0x40, - STATUS_CATEGORY_IO = 0x50, -}; - -/** - * Status code that may be returned by shell commands and protocol - * implementations. - * - * \note Any change to these status codes and the corresponding - * message strings is strictly forbidden. New codes can be added, - * however, but make sure that any message string tables are updated - * at the same time. - */ -enum status_code { - STATUS_OK = STATUS_CATEGORY_OK | 0x00, - STATUS_VALID_DATA = STATUS_CATEGORY_OK | 0x01, - STATUS_NO_CHANGE = STATUS_CATEGORY_OK | 0x02, - STATUS_ABORTED = STATUS_CATEGORY_OK | 0x04, - STATUS_BUSY = STATUS_CATEGORY_OK | 0x05, - STATUS_SUSPEND = STATUS_CATEGORY_OK | 0x06, - - STATUS_ERR_IO = STATUS_CATEGORY_COMMON | 0x00, - STATUS_ERR_REQ_FLUSHED = STATUS_CATEGORY_COMMON | 0x01, - STATUS_ERR_TIMEOUT = STATUS_CATEGORY_COMMON | 0x02, - STATUS_ERR_BAD_DATA = STATUS_CATEGORY_COMMON | 0x03, - STATUS_ERR_NOT_FOUND = STATUS_CATEGORY_COMMON | 0x04, - STATUS_ERR_UNSUPPORTED_DEV = STATUS_CATEGORY_COMMON | 0x05, - STATUS_ERR_NO_MEMORY = STATUS_CATEGORY_COMMON | 0x06, - STATUS_ERR_INVALID_ARG = STATUS_CATEGORY_COMMON | 0x07, - STATUS_ERR_BAD_ADDRESS = STATUS_CATEGORY_COMMON | 0x08, - STATUS_ERR_BAD_FORMAT = STATUS_CATEGORY_COMMON | 0x0A, - STATUS_ERR_BAD_FRQ = STATUS_CATEGORY_COMMON | 0x0B, - STATUS_ERR_DENIED = STATUS_CATEGORY_COMMON | 0x0c, - STATUS_ERR_ALREADY_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0d, - STATUS_ERR_OVERFLOW = STATUS_CATEGORY_COMMON | 0x0e, - STATUS_ERR_NOT_INITIALIZED = STATUS_CATEGORY_COMMON | 0x0f, - - STATUS_ERR_SAMPLERATE_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x00, - STATUS_ERR_RESOLUTION_UNAVAILABLE = STATUS_CATEGORY_ANALOG | 0x01, - - STATUS_ERR_BAUDRATE_UNAVAILABLE = STATUS_CATEGORY_COM | 0x00, - STATUS_ERR_PACKET_COLLISION = STATUS_CATEGORY_COM | 0x01, - STATUS_ERR_PROTOCOL = STATUS_CATEGORY_COM | 0x02, - - STATUS_ERR_PIN_MUX_INVALID = STATUS_CATEGORY_IO | 0x00, -}; -typedef enum status_code status_code_genare_t; - -/** - Status codes used by MAC stack. - */ -enum status_code_wireless { - //STATUS_OK = 0, //!< Success - ERR_IO_ERROR = -1, //!< I/O error - ERR_FLUSHED = -2, //!< Request flushed from queue - ERR_TIMEOUT = -3, //!< Operation timed out - ERR_BAD_DATA = -4, //!< Data integrity check failed - ERR_PROTOCOL = -5, //!< Protocol error - ERR_UNSUPPORTED_DEV = -6, //!< Unsupported device - ERR_NO_MEMORY = -7, //!< Insufficient memory - ERR_INVALID_ARG = -8, //!< Invalid argument - ERR_BAD_ADDRESS = -9, //!< Bad address - ERR_BUSY = -10, //!< Resource is busy - ERR_BAD_FORMAT = -11, //!< Data format not recognized - ERR_NO_TIMER = -12, //!< No timer available - ERR_TIMER_ALREADY_RUNNING = -13, //!< Timer already running - ERR_TIMER_NOT_RUNNING = -14, //!< Timer not running - - /** - * \brief Operation in progress - * - * This status code is for driver-internal use when an operation - * is currently being performed. - * - * \note Drivers should never return this status code to any - * callers. It is strictly for internal use. - */ - OPERATION_IN_PROGRESS = -128, -}; - -typedef enum status_code_wireless status_code_t; - -/** @} */ - -#endif /* STATUS_CODES_H_INCLUDED */ diff --git a/atmel-samd/asf/sam0/utils/stdio/doxygen/sam0.utils.stdio/doxyfile.doxygen b/atmel-samd/asf/sam0/utils/stdio/doxygen/sam0.utils.stdio/doxyfile.doxygen deleted file mode 100644 index 33f6a30a9474f..0000000000000 --- a/atmel-samd/asf/sam0/utils/stdio/doxygen/sam0.utils.stdio/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or a sequence of words surrounded -# by quotes) that should identify the project. - -PROJECT_NAME = "Standard I/O (stdio) Interface" - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = . - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrilic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. 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The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful is your file systems -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = YES - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 4 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. 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This also make the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = NO - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen to replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penality. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will rougly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = NO - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespace are hidden. - -EXTRACT_ANON_NSPACES = NO - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = YES - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = NO - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = YES - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or define consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and defines in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = NO - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../read.c ../../write.c - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = YES - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = YES - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# in the INCLUDE_PATH (see below) will be search if a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. To prevent a macro definition from being -# undefined via #undef or recursively expanded use the := operator -# instead of the = operator. - -PREDEFINED = __DOXYGEN__ __AVR32_ABI_COMPILER__ __attribute__()= __GNUC__=4 - -# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then -# this tag can be used to specify a list of macro names that should be expanded. -# The macro definition that is found in the sources will be used. -# Use the PREDEFINED tag if you want to use a different macro definition. - -EXPAND_AS_DEFINED = - -# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then -# doxygen's preprocessor will remove all function-like macros that are alone -# on a line, have an all uppercase name, and do not end with a semicolon. Such -# function macros are typically used for boiler-plate code, and will confuse -# the parser if not removed. - -SKIP_FUNCTION_MACROS = YES - -#--------------------------------------------------------------------------- -# Configuration::additions related to external references -#--------------------------------------------------------------------------- - -# The TAGFILES option can be used to specify one or more tagfiles. -# Optionally an initial location of the external documentation -# can be added for each tagfile. The format of a tag file without -# this location is as follows: -# -# TAGFILES = file1 file2 ... -# Adding location for the tag files is done as follows: -# -# TAGFILES = file1=loc1 "file2 = loc2" ... -# where "loc1" and "loc2" can be relative or absolute paths or -# URLs. If a location is present for each tag, the installdox tool -# does not have to be run to correct the links. -# Note that each tag file must have a unique name -# (where the name does NOT include the path) -# If a tag file is not located in the directory in which doxygen -# is run, you must also specify the path to the tagfile here. - -TAGFILES = - -# When a file name is specified after GENERATE_TAGFILE, doxygen will create -# a tag file that is based on the input files it reads. - -GENERATE_TAGFILE = - -# If the ALLEXTERNALS tag is set to YES all external classes will be listed -# in the class index. If set to NO only the inherited external classes -# will be listed. - -ALLEXTERNALS = NO - -# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed -# in the modules index. If set to NO, only the current project's groups will -# be listed. - -EXTERNAL_GROUPS = YES - -# The PERL_PATH should be the absolute path and name of the perl script -# interpreter (i.e. the result of `which perl'). - -PERL_PATH = /usr/bin/perl - -#--------------------------------------------------------------------------- -# Configuration options related to the dot tool -#--------------------------------------------------------------------------- - -# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will -# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base -# or super classes. Setting the tag to NO turns the diagrams off. Note that -# this option is superseded by the HAVE_DOT option below. This is only a -# fallback. It is recommended to install and use dot, since it yields more -# powerful graphs. - -CLASS_DIAGRAMS = YES - -# You can define message sequence charts within doxygen comments using the \msc -# command. Doxygen will then run the mscgen tool (see -# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the -# documentation. The MSCGEN_PATH tag allows you to specify the directory where -# the mscgen tool resides. If left empty the tool is assumed to be found in the -# default search path. - -MSCGEN_PATH = - -# If set to YES, the inheritance and collaboration graphs will hide -# inheritance and usage relations if the target is undocumented -# or is not a class. - -HIDE_UNDOC_RELATIONS = YES - -# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is -# available from the path. This tool is part of Graphviz, a graph visualization -# toolkit from AT&T and Lucent Bell Labs. The other options in this section -# have no effect if this option is set to NO (the default) - -HAVE_DOT = YES - -# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is -# allowed to run in parallel. When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/sam0/utils/stdio/doxygen/sam0.utils.stdio/doxygen_module_mainpage.h b/atmel-samd/asf/sam0/utils/stdio/doxygen/sam0.utils.stdio/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/sam0/utils/stdio/doxygen/sam0.utils.stdio/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. 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- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/sam0/utils/stdio/read.c b/atmel-samd/asf/sam0/utils/stdio/read.c deleted file mode 100644 index 77c7cbd63dfef..0000000000000 --- a/atmel-samd/asf/sam0/utils/stdio/read.c +++ /dev/null @@ -1,156 +0,0 @@ -/** - * \file - * - * \brief System-specific implementation of the \ref _read function used by - * the standard library. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "compiler.h" - -/** - * \defgroup group_common_utils_stdio Standard I/O (stdio) - * - * Common standard I/O driver that implements the stdio - * read and write functions on AVR and SAM devices. - * - * \{ - */ - -extern volatile void *volatile stdio_base; -void (*ptr_get)(void volatile*, char*); - - -// IAR common implementation -#if ( defined(__ICCARM__) ) - -#include - -_STD_BEGIN - -#pragma module_name = "?__read" - -/*! \brief Reads a number of bytes, at most \a size, into the memory area - * pointed to by \a buffer. - * - * \param handle File handle to read from. - * \param buffer Pointer to buffer to write read bytes to. - * \param size Number of bytes to read. - * - * \return The number of bytes read, \c 0 at the end of the file, or - * \c _LLIO_ERROR on failure. - */ -size_t __read(int handle, unsigned char *buffer, size_t size) -{ - int nChars = 0; - // This implementation only reads from stdin. - // For all other file handles, it returns failure. - if (handle != _LLIO_STDIN) { - return _LLIO_ERROR; - } - for (; size > 0; --size) { - ptr_get(stdio_base, (char*)buffer); - buffer++; - nChars++; - } - return nChars; -} - -/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 - * the implementation is empty to be compatible with old IAR version. - */ -int __close(int handle) -{ - UNUSED(handle); - return 0; -} - -/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 - * the implementation is empty to be compatible with old IAR version. - */ -int remove(const char* val) -{ - UNUSED(val); - return 0; -} - -/*! \brief This routine is required by IAR DLIB library since EWAVR V6.10 - * the implementation is empty to be compatible with old IAR version. - */ -long __lseek(int handle, long val, int val2) -{ - UNUSED(handle); - UNUSED(val2); - return val; -} - -_STD_END - -// GCC implementation -#elif (defined(__GNUC__)) - -int __attribute__((weak)) -_read (int file, char * ptr, int len); // Remove GCC compiler warning - -int __attribute__((weak)) -_read (int file, char * ptr, int len) -{ - int nChars = 0; - - if (file != 0) { - return -1; - } - - for (; len > 0; --len) { - ptr_get(stdio_base, ptr); - ptr++; - nChars++; - } - return nChars; -} - -#endif - -/** - * \} - */ - diff --git a/atmel-samd/asf/sam0/utils/stdio/stdio_serial/doxygen/sam0.utils.stdio.stdio_serial/doxyfile.doxygen b/atmel-samd/asf/sam0/utils/stdio/stdio_serial/doxygen/sam0.utils.stdio.stdio_serial/doxyfile.doxygen deleted file mode 100644 index cf93a90d67c73..0000000000000 --- a/atmel-samd/asf/sam0/utils/stdio/stdio_serial/doxygen/sam0.utils.stdio.stdio_serial/doxyfile.doxygen +++ /dev/null @@ -1,1645 +0,0 @@ -# Doxyfile 1.7.1 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project -# -# All text after a hash (#) is considered a comment and will be ignored -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" ") - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. 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The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = YES - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# This WARN_NO_PARAMDOC option can be abled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "[WARNING]$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen_module_mainpage.h ../../stdio_serial.h - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh *.hxx -# *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.py *.f90 - -FILE_PATTERNS = *.c \ - *.h \ - *.s \ - *.S - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix filesystem feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = ./ - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty, INPUT_FILTER -# is applied to all files. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = YES - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = NO - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.doxygen.Project - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.doxygen.Publisher - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Publisher - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# This tag can be used to set the number of enum values (range [1..20]) -# that doxygen will group on one line in the generated HTML documentation. - -ENUM_VALUES_PER_LINE = 1 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = NO - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see -# http://www.mathjax.org) which uses client side Javascript for the rendering -# instead of using prerendered bitmaps. Use this if you do not have LaTeX -# installed or if you want to formulas look prettier in the HTML output. When -# enabled you may also need to install MathJax separately and configure the path -# to it using the MATHJAX_RELPATH option. -# The default value is: NO. -# This tag requires that the tag GENERATE_HTML is set to YES. - -USE_MATHJAX = NO - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvances is that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, a4wide, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4wide - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = NO - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = NO - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = RTF - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = YES - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. 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Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. 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When set to 0 (the default) doxygen will -# base this on the number of processors available in the system. You can set it -# explicitly to a value larger than 0 to get control over the balance -# between CPU load and processing speed. - -DOT_NUM_THREADS = 0 - -# By default doxygen will write a font called FreeSans.ttf to the output -# directory and reference it in all dot files that doxygen generates. This -# font does not include all possible unicode characters however, so when you need -# these (or just want a differently looking font) you can specify the font name -# using DOT_FONTNAME. You need need to make sure dot is able to find the font, -# which can be done by putting it in a standard location or by setting the -# DOTFONTPATH environment variable or by setting DOT_FONTPATH to the directory -# containing the font. - -DOT_FONTNAME = FreeSans - -# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. -# The default size is 10pt. - -DOT_FONTSIZE = 10 - -# By default doxygen will tell dot to use the output directory to look for the -# FreeSans.ttf font (which doxygen will put there itself). If you specify a -# different font using DOT_FONTNAME you can set the path where dot -# can find it using this tag. - -DOT_FONTPATH = - -# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect inheritance relations. Setting this tag to YES will force the -# the CLASS_DIAGRAMS tag to NO. - -CLASS_GRAPH = YES - -# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for each documented class showing the direct and -# indirect implementation dependencies (inheritance, containment, and -# class references variables) of the class with other documented classes. - -COLLABORATION_GRAPH = YES - -# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen -# will generate a graph for groups, showing the direct groups dependencies - -GROUP_GRAPHS = YES - -# If the UML_LOOK tag is set to YES doxygen will generate inheritance and -# collaboration diagrams in a style similar to the OMG's Unified Modeling -# Language. - -UML_LOOK = YES - -# If set to YES, the inheritance and collaboration graphs will show the -# relations between templates and their instances. - -TEMPLATE_RELATIONS = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT -# tags are set to YES then doxygen will generate a graph for each documented -# file showing the direct and indirect include dependencies of the file with -# other documented files. - -INCLUDE_GRAPH = YES - -# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and -# HAVE_DOT tags are set to YES then doxygen will generate a graph for each -# documented header file showing the documented files that directly or -# indirectly include this file. - -INCLUDED_BY_GRAPH = YES - -# If the CALL_GRAPH and HAVE_DOT options are set to YES then -# doxygen will generate a call dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable call graphs -# for selected functions only using the \callgraph command. - -CALL_GRAPH = YES - -# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then -# doxygen will generate a caller dependency graph for every global function -# or class method. Note that enabling this option will significantly increase -# the time of a run. So in most cases it will be better to enable caller -# graphs for selected functions only using the \callergraph command. - -CALLER_GRAPH = NO - -# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen -# will graphical hierarchy of all classes instead of a textual one. - -GRAPHICAL_HIERARCHY = YES - -# If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES -# then doxygen will show the dependencies a directory has on other directories -# in a graphical way. The dependency relations are determined by the #include -# relations between the files in the directories. - -DIRECTORY_GRAPH = YES - -# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images -# generated by dot. Possible values are png, jpg, or gif -# If left blank png will be used. - -DOT_IMAGE_FORMAT = gif - -# The tag DOT_PATH can be used to specify the path where the dot tool can be -# found. If left blank, it is assumed the dot tool can be found in the path. - -DOT_PATH = - -# The DOTFILE_DIRS tag can be used to specify one or more directories that -# contain dot files that are included in the documentation (see the -# \dotfile command). - -DOTFILE_DIRS = - -# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of -# nodes that will be shown in the graph. If the number of nodes in a graph -# becomes larger than this value, doxygen will truncate the graph, which is -# visualized by representing a node as a red box. Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = YES - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/atmel-samd/asf/sam0/utils/stdio/stdio_serial/doxygen/sam0.utils.stdio.stdio_serial/doxygen_module_mainpage.h b/atmel-samd/asf/sam0/utils/stdio/stdio_serial/doxygen/sam0.utils.stdio.stdio_serial/doxygen_module_mainpage.h deleted file mode 100644 index 26566747f8e73..0000000000000 --- a/atmel-samd/asf/sam0/utils/stdio/stdio_serial/doxygen/sam0.utils.stdio.stdio_serial/doxygen_module_mainpage.h +++ /dev/null @@ -1,58 +0,0 @@ - -/** - * Copyright (c) 2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - * \mainpage - * - * \section intro Introduction - * This documentation has been automatically generated, and documents the source - * code found in the Atmel Software Framework (ASF).

- * Use the above menu to navigate in the documentation, or use the links below:
- *

- * - * \section main_licence License - *
    - *
  • \ref License - *
- * \section contactinfo Contact Information - * For further information, visit Atmel.\n - * - */ diff --git a/atmel-samd/asf/sam0/utils/stdio/stdio_serial/stdio_serial.h b/atmel-samd/asf/sam0/utils/stdio/stdio_serial/stdio_serial.h deleted file mode 100644 index bf8c4f5eee5e8..0000000000000 --- a/atmel-samd/asf/sam0/utils/stdio/stdio_serial/stdio_serial.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - * - * \file - * - * \brief Common Standard I/O Serial Management. - * - * This file defines a useful set of functions for the Stdio Serial interface on - * SAM0 devices. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - ******************************************************************************/ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef STDIO_SERIAL_H_INCLUDED -#define STDIO_SERIAL_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \defgroup group_common_utils_stdio_stdio_serial Standard serial I/O (stdio) - * \ingroup group_common_utils_stdio - * - * Common standard serial I/O management driver that - * implements a stdio serial interface on AVR and SAM devices. - * - * @{ - */ - -#include -#include -#include - -/** Pointer to the base of the USART module instance to use for stdio. */ -extern volatile void *volatile stdio_base; - -/** Pointer to the external low level write function. */ -extern int (*ptr_put)(void volatile*, char); - -/** Pointer to the external low level read function. */ -extern void (*ptr_get)(void volatile*, char*); - -#if SAM0 -/** \brief Initializes the stdio in Serial Mode. - * - * \param module Software USART instance to associate with the hardware. - * \param hw Base address of the USART hardware instance. - * \param config USART configuration parameters for the STDIO stream. - * - */ -static inline void stdio_serial_init( - struct usart_module *const module, - usart_inst_t const hw, - const struct usart_config *const config) -{ - stdio_base = (void *)module; - ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar; - ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar; - - usart_serial_init(module, hw, config); -# if defined(__GNUC__) - // Specify that stdout and stdin should not be buffered. - setbuf(stdout, NULL); - setbuf(stdin, NULL); - // Note: Already the case in IAR's Normal DLIB default configuration - // and AVR GCC library: - // - printf() emits one character at a time. - // - getchar() requests only 1 byte to exit. -# endif -} -#endif - -#if SAMB -/** \brief Initializes the stdio in Serial Mode. - * - * \param module Software UART instance to associate with the hardware. - * \param hw Base address of the UART hardware instance. - * \param config UART configuration parameters for the STDIO stream. - * - */ -static inline void stdio_serial_init( - struct uart_module *const module, - Uart * const hw, - const struct uart_config *const config) -{ - stdio_base = (void *)module; - ptr_put = (int (*)(void volatile*,char))&usart_serial_putchar; - ptr_get = (void (*)(void volatile*,char*))&usart_serial_getchar; - - usart_serial_init(module, hw, config); -# if defined(__GNUC__) - // Specify that stdout and stdin should not be buffered. - setbuf(stdout, NULL); - setbuf(stdin, NULL); - // Note: Already the case in IAR's Normal DLIB default configuration - // and AVR GCC library: - // - printf() emits one character at a time. - // - getchar() requests only 1 byte to exit. -# endif -} -#endif - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif // _STDIO_SERIAL_H_ diff --git a/atmel-samd/asf/sam0/utils/stdio/write.c b/atmel-samd/asf/sam0/utils/stdio/write.c deleted file mode 100644 index 9ef442a423441..0000000000000 --- a/atmel-samd/asf/sam0/utils/stdio/write.c +++ /dev/null @@ -1,136 +0,0 @@ -/** - * \file - * - * \brief System-specific implementation of the \ref _write function used by - * the standard library. - * - * Copyright (c) 2009-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include "compiler.h" - -/** - * \addtogroup group_common_utils_stdio - * - * \{ - */ - -volatile void *volatile stdio_base; -int (*ptr_put)(void volatile*, char); - - -#if ( defined(__ICCARM__)) - -#include - -_STD_BEGIN - -#pragma module_name = "?__write" - -/*! \brief Writes a number of bytes, at most \a size, from the memory area - * pointed to by \a buffer. - * - * If \a buffer is zero then \ref __write performs flushing of internal buffers, - * if any. In this case, \a handle can be \c -1 to indicate that all handles - * should be flushed. - * - * \param handle File handle to write to. - * \param buffer Pointer to buffer to read bytes to write from. - * \param size Number of bytes to write. - * - * \return The number of bytes written, or \c _LLIO_ERROR on failure. - */ -size_t __write(int handle, const unsigned char *buffer, size_t size) -{ - size_t nChars = 0; - - if (buffer == 0) { - // This means that we should flush internal buffers. - return 0; - } - - // This implementation only writes to stdout and stderr. - // For all other file handles, it returns failure. - if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { - return _LLIO_ERROR; - } - - for (; size != 0; --size) { - if (ptr_put(stdio_base, *buffer++) < 0) { - return _LLIO_ERROR; - } - ++nChars; - } - return nChars; -} - -_STD_END - - -#elif (defined(__GNUC__)) - -int __attribute__((weak)) -_write (int file, char * ptr, int len); - -int __attribute__((weak)) -_write (int file, char * ptr, int len) -{ - int nChars = 0; - - if ((file != 1) && (file != 2) && (file!=3)) { - return -1; - } - - for (; len != 0; --len) { - if (ptr_put(stdio_base, *ptr++) < 0) { - return -1; - } - ++nChars; - } - return nChars; -} - -#endif - -/** - * \} - */ - diff --git a/atmel-samd/asf/sam0/utils/syscalls/gcc/syscalls.c b/atmel-samd/asf/sam0/utils/syscalls/gcc/syscalls.c deleted file mode 100644 index 45859e8628a2d..0000000000000 --- a/atmel-samd/asf/sam0/utils/syscalls/gcc/syscalls.c +++ /dev/null @@ -1,129 +0,0 @@ -/** - * \file - * - * \brief Syscalls for SAM0 (GCC). - * - * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#undef errno -extern int errno; -extern int _end; - -extern caddr_t _sbrk(int incr); -extern int link(char *old, char *new); -extern int _close(int file); -extern int _fstat(int file, struct stat *st); -extern int _isatty(int file); -extern int _lseek(int file, int ptr, int dir); -extern void _exit(int status); -extern void _kill(int pid, int sig); -extern int _getpid(void); - -extern caddr_t _sbrk(int incr) -{ - static unsigned char *heap = NULL; - unsigned char *prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_end; - } - prev_heap = heap; - - heap += incr; - - return (caddr_t) prev_heap; -} - -extern int link(char *old, char *new) -{ - return -1; -} - -extern int _close(int file) -{ - return -1; -} - -extern int _fstat(int file, struct stat *st) -{ - st->st_mode = S_IFCHR; - - return 0; -} - -extern int _isatty(int file) -{ - return 1; -} - -extern int _lseek(int file, int ptr, int dir) -{ - return 0; -} - -// extern void _exit(int status) -// { -// asm("BKPT #0"); -// } - -extern void _kill(int pid, int sig) -{ - return; -} - -extern int _getpid(void) -{ - return -1; -} - -#ifdef __cplusplus -} -#endif diff --git a/atmel-samd/asf/thirdparty/CMSIS/ATMEL-disclaimer.txt b/atmel-samd/asf/thirdparty/CMSIS/ATMEL-disclaimer.txt deleted file mode 100644 index 422f7fe86a902..0000000000000 --- a/atmel-samd/asf/thirdparty/CMSIS/ATMEL-disclaimer.txt +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Only the CMSIS required parts for ASF are included here, go to the below - * address for the full package: - * http://www.arm.com/products/processors/cortex-m/cortex-microcontroller-software-interface-standard.php - * - * The library file thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math_softfp.a was generated by ATMEL, which - * is support -mfloat-abi=softfp compiler flag, and this is also the default selection for device that - * have FPU module and enabled. - * If customer want to use -mfloat-abi=hard compiler flag, the project compile/link flag and link library - * should be manual modified. The library thirdparty/CMSIS/Lib/GCC/libarm_cortexM4lf_math.a is used for - * -mfloat-abi=hard configration. - * - * __CORTEX_SC is not defined for cortex-m0+, and may cause compiler warning, so the include file - * thirdparty/CMSIS/Include/core_cmInstr.h was modified to void such warning. - * Modified from: - * #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - * to: - * #if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) - * - */ diff --git a/atmel-samd/asf/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf b/atmel-samd/asf/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf deleted file mode 100644 index a828509a4d6bb..0000000000000 Binary files a/atmel-samd/asf/thirdparty/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.pdf and /dev/null differ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/arm_math.h b/atmel-samd/asf/thirdparty/CMSIS/Include/arm_math.h deleted file mode 100644 index f06a0713eb80a..0000000000000 --- a/atmel-samd/asf/thirdparty/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7538 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 12. March 2014 -* $Revision: V1.4.4 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvproj - * - * - * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2014 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - *
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- * 
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - *
- *     pData[i*numCols + j]
- * 
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - *
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- * 
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - *
- *     ARM_MATH_SIZE_MISMATCH
- * 
- * Otherwise the functions return - *
- *     ARM_MATH_SUCCESS
- * 
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - *
- *     ARM_MATH_MATRIX_CHECK
- * 
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY - #elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - *
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd  
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - *
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   * 
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - *
-   *      x1 = x0 - f(x0)/f'(x0)
-   * 
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - *
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   * 
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - *
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   * 
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - *
-   *     XF = floor(x)
-   *     YF = floor(y)
-   * 
- * \par - * The interpolated output point is computed as: - *
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   * 
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -//SMMLAR -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//SMMLA -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -//SMMLS -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) //Keil - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) // Cosmic - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cm7.h b/atmel-samd/asf/thirdparty/CMSIS/Include/core_cm7.h deleted file mode 100644 index e21e9e29fc4e6..0000000000000 --- a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2221 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 01. September 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000 - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0 - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0 - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0 - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1]; - __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93]; - __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15]; - __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1]; - __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1]; - __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6]; - __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1]; - __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/* Cache Level ID register */ -#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* Cache Type register */ -#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ - -/* Cache Size ID Register */ -#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ - -/* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register */ -#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ - -/* Instruction Tightly-Coupled Memory Control Register*/ -#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (0x1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (0x1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (0x1UL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Registers */ -#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register */ -#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register */ -#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ - -/* AHBS control register */ -#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register */ -#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## Cache functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) - - -/** \brief Enable I-Cache - - The function turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; // invalidate I-Cache - SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable I-Cache - - The function turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0; // invalidate I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate I-Cache - - The function invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; - __DSB(); - __ISB(); - #endif -} - - -/** \brief Enable D-Cache - - The function turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - __DSB(); - - SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable D-Cache - - The function turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate D-Cache - - The function invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean D-Cache - - The function cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCSW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean & Invalidate D-Cache - - The function cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cmInstr.h b/atmel-samd/asf/thirdparty/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index 2e3bb0eabb931..0000000000000 --- a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,880 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) || ((defined(__CORTEX_SC)) && (__CORTEX_SC >= 300)) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a b/atmel-samd/asf/thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a deleted file mode 100644 index c91de9d8c2561..0000000000000 Binary files a/atmel-samd/asf/thirdparty/CMSIS/Lib/GCC/libarm_cortexM0l_math.a and /dev/null differ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Lib/license.txt b/atmel-samd/asf/thirdparty/CMSIS/Lib/license.txt deleted file mode 100644 index 139c1ff8d4db3..0000000000000 --- a/atmel-samd/asf/thirdparty/CMSIS/Lib/license.txt +++ /dev/null @@ -1,28 +0,0 @@ -All pre-build libraries contained in the folders "ARM" and "GCC" -are guided by the following license: - -Copyright (C) 2009-2014 ARM Limited. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -POSSIBILITY OF SUCH DAMAGE. diff --git a/atmel-samd/asf/thirdparty/CMSIS/README.txt b/atmel-samd/asf/thirdparty/CMSIS/README.txt deleted file mode 100644 index e42a543342a12..0000000000000 --- a/atmel-samd/asf/thirdparty/CMSIS/README.txt +++ /dev/null @@ -1,42 +0,0 @@ -* ------------------------------------------------------------------- -* Copyright (C) 2011-2014 ARM Limited. All rights reserved. -* -* Date: 17 February 2014 -* Revision: V4.00 -* -* Project: Cortex Microcontroller Software Interface Standard (CMSIS) -* Title: Release Note for CMSIS -* -* ------------------------------------------------------------------- - - -NOTE - Open the index.html file to access CMSIS documentation - - -The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all -Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects -and reduces time-to-market for new embedded applications. - -CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf"). -Any user of the software package is bound to the terms and conditions of the end user license agreement. - - -You will find the following sub-directories: - -Documentation - Contains CMSIS documentation. - -DSP_Lib - MDK project files, Examples and source files etc.. to build the - CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors. - -Include - CMSIS Core Support and CMSIS DSP Include Files. - -Lib - CMSIS DSP Libraries. - -RTOS - CMSIS RTOS API template header file. - -Driver - CMSIS Peripheral Driver Interface. - -Pack - CMSIS Software Packs. - Mechanism to install software, device support, APIs, and example projects. - -SVD - CMSIS SVD Schema files and Conversion Utility. diff --git a/atmel-samd/asf/thirdparty/CMSIS/license.txt b/atmel-samd/asf/thirdparty/CMSIS/license.txt deleted file mode 100644 index dbf08a6dbf0c6..0000000000000 --- a/atmel-samd/asf/thirdparty/CMSIS/license.txt +++ /dev/null @@ -1,111 +0,0 @@ -END USER LICENCE AGREEMENT FOR THE CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS) DELIVERABLES - -THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE CMSIS DELIVERABLES. ARM IS ONLY WILLING TO LICENSE THE CMSIS DELIVERABLES TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE CMSIS DELIVERABLES YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE OF THE CMSIS DELIVERABLES AND YOU MAY NOT INSTALL, USE OR COPY THE CMSIS DELIVERABLES. - -“CMSIS Deliverables†means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD . - -“CMSIS-CORE†means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores. - -â€CMSIS-DRIVER†means the specification defining a generic peripheral driver application programming interface, naming and coding conventions. - -“CMSIS-DSP†means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation. - -“CMSIS-PACK†means the specification defining a software pack file format, verification utility, and the associated XML schema file. - -“CMSIS-RTOS API†means the real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system. - -Notwithstanding the foregoing, the CMSIS Deliverables shall not include: (i) the implementation of other published specifications referenced in the CMSIS Deliverables ; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof that complies with the CMSIS Deliverables, but are not themselves expressly set forth in the CMSIS Deliverables (e.g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs. - -“CMSIS-SVD†means the specification defining the System View Description (SVD), verification utility, and associated XML schema files. - -“Separate Files†means the components in the CMSIS reference implementation identified in the Schedule that demonstrate the usage of the CMSIS-CORE, CMSIS-DRIVER, CMSIS-DSP, CMSIS-PACK and CMSIS-RTOS API, for microprocessors or device specific software applications that are for use with microprocessors. - -1. LICENCE GRANTS. - -1.1 CMSIS DELIVERABLES - -ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable licence, to use and copy the CMSIS Deliverables for the purpose of: - -(i) subject to clause 1.2, developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the CMSIS Deliverables; and - -(ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-Deliverables unmodified, with the products you have developed under Clause 1.1 (i) provided you preserve any copyright notices which are included with the CMSIS Deliverables. - -1.2 CONDITIONS ON REDISTRIBUTION. - -If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant to Clauses 1.1 (i) you agree: (a) not to use ARM’s name, logo or trademarks to market any or all of the products created under Clause 1.1 (i); (b) to preserve any copyright notices included in the CMSIS Deliverables; and (c) to ensure your customers and authorised distributors comply with this Clause 1.2. - -2. RESTRICTIONS ON USE OF THE CMSIS DELIVERABLES. - -PERMITTED USERS: The CMSIS Deliverables shall be used only by you (either a single individual, or single legal entity) your employees, or by your on-site bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM for to the same extent as you are for your employees, and provided always that such sub-contractors: (i) are contractually obligated to use the CMSIS Deliverables only for your benefit; and (ii) agree to assign all their work product and -any rights they create therein in the supply of such work to you. - -COPYRIGHT AND RESERVATION OF RIGHTS: The CMSIS Deliverables are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The CMSIS Deliverables are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the CMSIS Deliverables or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the CMSIS Deliverables. - -3. SUPPORT. - -ARM is not obligated to support the CMSIS Deliverables but may do so entirely at ARM's discretion. - -4. NO WARRANTY. - -YOU AGREE THAT THE CMSIS DELIVERABLES ARE LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLAIMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE. THE CMSIS DELIVERABLES MAY CONTAIN ERRORS. - -5. LIMITATION OF LIABILITY. - -THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT, TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED THE GREATER OF (I) THE TOTAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE AND (II) US$10.00. THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW. - -6. THIRD PARTY RIGHTS. - -The Separate Files are delivered subject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and they are not included in the term “CMSIS Deliverables†under this Licence. You agree to comply with all terms and conditions imposed on you in respect of such Separate Files including those identified in the Schedule (“Third Party Termsâ€). - -ARM HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODEâ€), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE. - -NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF -THE POSSIBILITY OF SUCH DAMAGES. - -7. U.S. GOVERNMENT END USERS. - -US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence. - -8. TERM AND TERMINATION. - -8.1 This Licence shall remain in force until terminated in accordance with the terms of Clause 8.2 or Clause 8.3 below. - -8.2 Without prejudice to any of its other rights if you are in breach of any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you. You may terminate this Licence at any time. - -8.3 This Licence shall immediately terminate and shall be unavailable to you if you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the CMSIS Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) patent is Necessary to implement the CMSIS Deliverables. In this Licence: (i) "affiliate" means any entity controlling, controlled by or under -common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" shall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, or proceedings before any other competent trade, arbitral or international authority; and (iii) “Necessary†means with respect to any claims of any patent, those claims which, without the appropriate permission of the patent owner, will be -infringed when implementing the CMSIS Deliverables because no alternative, commercially reasonable, non-infringing way of implementing the CMSIS Deliverables is known. - -8.4 Upon termination of this Licence, you shall stop using the CMSIS Deliverables and destroy all copies of the CMSIS Deliverables in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence. - -9. GENERAL. - -This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the CMSIS Deliverables and it may only be modified by written agreement between you and ARM. Except as expressly agreed in writing, this Licence may not be modified by purchase orders, advertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be -illegal or unenforceable the remaining provisions of this Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence in the future. This Licence may not be assigned without the prior written consent of ARM. - -SCHEDULE - -Separate Files - -The package also includes the components contained in the following directories: -(a) ./CMSIS/DSP_Lib - DSP Library sources and examples; -(b) ./CMSIS/Include - Header files; -(c) ./CMSIS/Lib - DSP Library build for various toolchains; -(d) ./CMSIS/RTOS - Header file template for CMSIS-RTOS implementation; and -(e) ./Device - Template files and implementations for Cortex-M class processors. - -All of the above components (a– e) are licensed to you under the terms of the BSD licence, which is incorporated within or alongside the above components. -(f) ./CMSIS/Driver – CMSIS-Driver header files -(g) ./CMSIS/Pack – Example Device Family Pack - -The above components (f – g) are licensed to you under the terms of the zlib licence, which is incorporated within or alongside the above components. - - - - -ARM contract reference LEC-PRE-00489- v3.0 -1 June 2014 -CONFIDENTIAL -LEC-PRE-00489 -SP-Version: 3.0 - diff --git a/atmel-samd/asf/version.h b/atmel-samd/asf/version.h deleted file mode 100644 index de93d07ac2388..0000000000000 --- a/atmel-samd/asf/version.h +++ /dev/null @@ -1,3 +0,0 @@ -// Update this when the library is updated. Its not included by default. - -#define ASF_VERSION "3.32.0" diff --git a/atmel-samd/asf4/samd21/CMSIS/Documentation/Core/html/index.html b/atmel-samd/asf4/samd21/CMSIS/Documentation/Core/html/index.html new file mode 100644 index 0000000000000..3e7503ea95596 --- /dev/null +++ b/atmel-samd/asf4/samd21/CMSIS/Documentation/Core/html/index.html @@ -0,0 +1,241 @@ + + + + + +CMSIS-CORE: Overview + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CMSIS-CORE +  Version 4.00 +
+
CMSIS-CORE support for Cortex-M processor-based devices
+
+
+ +
+ +
+ + + +
+
+ +
+
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+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
  • +
  • System exception names to interface to system exceptions without having compatibility issues.
  • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
  • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
  • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
  • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
  • +
+
+

This chapter provides details about the CMSIS-CORE and contains the following sections:

+ +
+

CMSIS-CORE in ARM::CMSIS Pack

+

Files relevant to CMSIS-CORE are present in the following ARM::CMSIS directories:

+ + + + + + + + + + + +
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Include CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device ARM reference implementations of Cortex-M devices
Device\_Template_Vendor Template Files for extension by silicon vendors
+
+

+Cortex-M Reference Manuals

+

The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

+ +
Todo:
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+
+

+Tested and Verified Toolchains

+

The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

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  • ARM: MDK-ARM Version 5.12
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  • GNU: GNU Tools ARM Embedded 4.8 2014.q3
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  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
  • +
+
+

Revision History of CMSIS-CORE

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Version Description
V4.00 Added: Cortex-M7 support.
+ Added: intrinsic functions for __RRX, __LDRBT, __LDRHT, __LDRT, __STRBT, __STRHT, and __STRT
+
V3.40 Corrected: C++ include guard settings.
+
V3.30 Added: COSMIC tool chain support.
+ Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.
+ Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.
+ Corrected: GCC/CLang warnings.
+
V3.20 Added: __BKPT instruction intrinsic.
+ Added: __SMMLA instruction intrinsic for Cortex-M4.
+ Corrected: ITM_SendChar.
+ Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
+ Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.
+
V3.01 Added support for Cortex-M0+ processor.
+
V3.00 Added support for GNU GCC ARM Embedded Compiler.
+ Added function __ROR.
+ Added Register Mapping for TPIU, DWT.
+ Added support for SC000 and SC300 processors.
+ Corrected ITM_SendChar function.
+ Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
+ Documentation restructured.
V2.10 Updated documentation.
+ Updated CMSIS core include files.
+ Changed CMSIS/Device folder structure.
+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
+ Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
+ Added additional Debug Functionality.
+ Changed folder structure.
+ Added doxygen comments.
+ Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.
+
+
+ + + + diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/arm_common_tables.h b/atmel-samd/asf4/samd21/CMSIS/Include/arm_common_tables.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/arm_common_tables.h rename to atmel-samd/asf4/samd21/CMSIS/Include/arm_common_tables.h diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/arm_const_structs.h b/atmel-samd/asf4/samd21/CMSIS/Include/arm_const_structs.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/arm_const_structs.h rename to atmel-samd/asf4/samd21/CMSIS/Include/arm_const_structs.h diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h b/atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000000..49e23ee669353 --- /dev/null +++ b/atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h @@ -0,0 +1,7544 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
+ *     pData[i*numCols + j]
+ * 
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
+ *     ARM_MATH_SIZE_MISMATCH
+ * 
+ * Otherwise the functions return + *
+ *     ARM_MATH_SUCCESS
+ * 
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ *     ARM_MATH_MATRIX_CHECK
+ * 
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cm0.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_cm0.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_cm0.h diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cm0plus.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0plus.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_cm0plus.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_cm0plus.h diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cm3.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm3.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_cm3.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_cm3.h diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cm4.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm4.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_cm4.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_cm4.h diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000000..242540f8b1187 --- /dev/null +++ b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h @@ -0,0 +1,2221 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cmFunc.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmFunc.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_cmFunc.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_cmFunc.h diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000000..842be65ed3cca --- /dev/null +++ b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_cmSimd.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmSimd.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_cmSimd.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_cmSimd.h diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_sc000.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_sc000.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_sc000.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_sc000.h diff --git a/atmel-samd/asf/thirdparty/CMSIS/Include/core_sc300.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_sc300.h similarity index 100% rename from atmel-samd/asf/thirdparty/CMSIS/Include/core_sc300.h rename to atmel-samd/asf4/samd21/CMSIS/Include/core_sc300.h diff --git a/atmel-samd/asf4/samd21/armcc/Makefile b/atmel-samd/asf4/samd21/armcc/Makefile new file mode 100644 index 0000000000000..fe17feaff24f6 --- /dev/null +++ b/atmel-samd/asf4/samd21/armcc/Makefile @@ -0,0 +1,269 @@ + +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif +endif + +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/adc \ +hal/src \ +samd21a/armcc/Device/SAMD21/Source/ARM \ +examples \ +hpl/systick \ +hpl/tc \ +usb \ +hpl/dmac \ +usb/class/cdc/device \ +hal/utils/src \ +hpl/rtc \ +usb/class/hid/device \ +hpl/usb \ +hpl/pm \ +hpl/sysctrl \ +hpl/gclk \ +usb/device \ +hpl/dac \ +samd21a/armcc/Device/SAMD21/Source \ +hpl/sercom \ +hpl/nvmctrl \ +hpl/core + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hpl/systick/hpl_systick.o \ +usb/usb_protocol.o \ +usb/class/hid/device/hiddf_generic.o \ +usb/class/cdc/device/cdcdf_acm.o \ +hpl/nvmctrl/hpl_nvmctrl.o \ +hal/src/hal_spi_m_sync.o \ +hal/src/hal_timer.o \ +hal/src/hal_pwm.o \ +hpl/usb/hpl_usb.o \ +hal/src/hal_i2c_m_sync.o \ +hal/src/hal_delay.o \ +hpl/sysctrl/hpl_sysctrl.o \ +hpl/core/hpl_init.o \ +hal/utils/src/utils_list.o \ +hpl/core/hpl_core_m0plus_base.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/pm/hpl_pm.o \ +usb/class/hid/device/hiddf_keyboard.o \ +hal/src/hal_usart_sync.o \ +hpl/dac/hpl_dac.o \ +hpl/gclk/hpl_gclk.o \ +hal/src/hal_flash.o \ +hal/src/hal_init.o \ +samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o \ +hal/src/hal_usb_device.o \ +main.o \ +hpl/rtc/hpl_rtc.o \ +examples/driver_examples.o \ +driver_init.o \ +samd21a/armcc/Device/SAMD21/Source/system_samd21.o \ +hal/src/hal_adc_sync.o \ +hal/src/hal_dac_sync.o \ +hpl/sercom/hpl_sercom.o \ +hal/src/hal_gpio.o \ +usb/class/hid/device/hiddf_mouse.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +usb_start.o \ +atmel_start.o \ +usb/device/usbdc.o \ +hpl/tc/hpl_tc.o \ +hal/src/hal_atomic.o \ +hpl/adc/hpl_adc.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hpl/systick/hpl_systick.o" \ +"usb/usb_protocol.o" \ +"usb/class/hid/device/hiddf_generic.o" \ +"usb/class/cdc/device/cdcdf_acm.o" \ +"hpl/nvmctrl/hpl_nvmctrl.o" \ +"hal/src/hal_spi_m_sync.o" \ +"hal/src/hal_timer.o" \ +"hal/src/hal_pwm.o" \ +"hpl/usb/hpl_usb.o" \ +"hal/src/hal_i2c_m_sync.o" \ +"hal/src/hal_delay.o" \ +"hpl/sysctrl/hpl_sysctrl.o" \ +"hpl/core/hpl_init.o" \ +"hal/utils/src/utils_list.o" \ +"hpl/core/hpl_core_m0plus_base.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/pm/hpl_pm.o" \ +"usb/class/hid/device/hiddf_keyboard.o" \ +"hal/src/hal_usart_sync.o" \ +"hpl/dac/hpl_dac.o" \ +"hpl/gclk/hpl_gclk.o" \ +"hal/src/hal_flash.o" \ +"hal/src/hal_init.o" \ +"samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o" \ +"hal/src/hal_usb_device.o" \ +"main.o" \ +"hpl/rtc/hpl_rtc.o" \ +"examples/driver_examples.o" \ +"driver_init.o" \ +"samd21a/armcc/Device/SAMD21/Source/system_samd21.o" \ +"hal/src/hal_adc_sync.o" \ +"hal/src/hal_dac_sync.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hal/src/hal_gpio.o" \ +"usb/class/hid/device/hiddf_mouse.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"usb_start.o" \ +"atmel_start.o" \ +"usb/device/usbdc.o" \ +"hpl/tc/hpl_tc.o" \ +"hal/src/hal_atomic.o" \ +"hpl/adc/hpl_adc.o" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"usb/usb_protocol.d" \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"hpl/systick/hpl_systick.d" \ +"usb/class/hid/device/hiddf_generic.d" \ +"usb/class/cdc/device/cdcdf_acm.d" \ +"usb/class/hid/device/hiddf_mouse.d" \ +"samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.d" \ +"hal/src/hal_i2c_m_sync.d" \ +"hpl/usb/hpl_usb.d" \ +"samd21a/armcc/Device/SAMD21/Source/system_samd21.d" \ +"hpl/nvmctrl/hpl_nvmctrl.d" \ +"hal/src/hal_pwm.d" \ +"hal/src/hal_timer.d" \ +"hal/src/hal_spi_m_sync.d" \ +"hpl/core/hpl_core_m0plus_base.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/sysctrl/hpl_sysctrl.d" \ +"hal/src/hal_flash.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hal/src/hal_usb_device.d" \ +"usb_start.d" \ +"hal/src/hal_init.d" \ +"hal/src/hal_usart_sync.d" \ +"usb/class/hid/device/hiddf_keyboard.d" \ +"hpl/dac/hpl_dac.d" \ +"driver_init.d" \ +"hal/src/hal_adc_sync.d" \ +"main.d" \ +"examples/driver_examples.d" \ +"hpl/rtc/hpl_rtc.d" \ +"hal/src/hal_sleep.d" \ +"hpl/sercom/hpl_sercom.d" \ +"hal/src/hal_dac_sync.d" \ +"hal/src/hal_gpio.d" \ +"hal/src/hal_atomic.d" \ +"hpl/tc/hpl_tc.d" \ +"usb/device/usbdc.d" \ +"hpl/pm/hpl_pm.d" \ +"hpl/adc/hpl_adc.d" \ +"atmel_start.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARMCC Linker + $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ +--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ +--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ +-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M0+ \ +$(OBJS_AS_ARGS) + + @echo Finished building target: $@ + +# Compiler target(s) + + + + +%.o: %.c + @echo Building file: $< + @echo ARMCC Compiler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARMCC Assembler + $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M0+ --pd "D__SAMD21G18A__ SETA 1" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +--depend "$(@:%.o=%.d)" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARMCC Preprocessing Assembler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/atmel-samd/asf4/samd21/atmel_start.c b/atmel-samd/asf4/samd21/atmel_start.c new file mode 100644 index 0000000000000..a075fcfa62c5d --- /dev/null +++ b/atmel-samd/asf4/samd21/atmel_start.c @@ -0,0 +1,10 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project +**/ +void atmel_start_init(void) +{ + system_init(); + usb_init(); +} diff --git a/atmel-samd/asf4/samd21/atmel_start.h b/atmel-samd/asf4/samd21/atmel_start.h new file mode 100644 index 0000000000000..71d54c217bc51 --- /dev/null +++ b/atmel-samd/asf4/samd21/atmel_start.h @@ -0,0 +1,19 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" +#include "usb_start.h" + +/** + * Initializes MCU, drivers and middleware in the project +**/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/atmel-samd/asf4/samd21/atmel_start_config.atstart b/atmel-samd/asf4/samd21/atmel_start_config.atstart new file mode 100644 index 0000000000000..92e7419383af7 --- /dev/null +++ b/atmel-samd/asf4/samd21/atmel_start_config.atstart @@ -0,0 +1,1114 @@ +format_version: '2' +name: My Project +board: + identifier: CustomBoard + device: SAMD21G18A-MF +details: null +application: null +middlewares: + USB_CHAPTER_9: + user_label: USB_CHAPTER_9 + configuration: {} + definition: Atmel:USB:0.0.1::USB_Chapter_9 + functionality: USB_Chapter_9 + api: USB:Protocol:Core + dependencies: {} + USB_CLASS_HUB: + user_label: USB_CLASS_HUB + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_HUB + functionality: USB_Class_HUB + api: USB:Protocol:HUB + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_HID: + user_label: USB_CLASS_HID + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_HID + functionality: USB_Class_HID + api: USB:Protocol:HID + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_CDC: + user_label: USB_CLASS_CDC + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_CDC + functionality: USB_Class_CDC + api: USB:Protocol:CDC + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_MSC: + user_label: USB_CLASS_MSC + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_MSC + functionality: USB_Class_Mass_Storage_(MSC) + api: USB:Protocol:MSC + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_VENDOR: + user_label: USB_CLASS_VENDOR + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_VENDOR + functionality: USB_Class_VENDOR + api: USB:Protocol:VENDOR + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_DEVICE_STACK_CORE_INSTANCE: + user_label: USB_DEVICE_STACK_CORE_INSTANCE + configuration: {} + definition: Atmel:USB:0.0.1::USB_Device_Core + functionality: USB_Device_Core + api: USB:Device:Core + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB Device instance: USB_0 + USB_DEVICE_COMPOSITE_0: + user_label: USB_DEVICE_COMPOSITE_0 + configuration: + usb_composite_bcddevice: 256 + usb_composite_bcdusb: USB 2.0 version + usb_composite_bconfigval: 1 + usb_composite_bmattri: Bus power supply, not support for remote wakeup + usb_composite_bmaxpksz0: 64 bytes + usb_composite_bmaxpower: 50 + usb_composite_bnumconfig: 1 + usb_composite_cdc_acm_comm_int_maxpksz: 64 bytes + usb_composite_cdc_acm_data_buckout_maxpksz: 64 bytes + usb_composite_cdc_acm_data_builin_maxpksz: 64 bytes + usb_composite_cdc_acm_data_bulkin_epaddr: EndpointAddress = 0x81 + usb_composite_cdc_acm_data_bulkout_epaddr: EndpointAddress = 0x01 + usb_composite_cdc_acm_epaddr: EndpointAddress = 0x82 + usb_composite_cdc_acm_support: true + usb_composite_hid_generic_intin_epaddr: EndpointAddress = 0x85 + usb_composite_hid_generic_intin_maxpksz: 64 bytes + usb_composite_hid_generic_intout_epaddr: EndpointAddress = 0x03 + usb_composite_hid_generic_intout_maxpksz: 64 bytes + usb_composite_hid_generic_support: false + usb_composite_hid_keyboard_intin_epaddr: EndpointAddress = 0x84 + usb_composite_hid_keyboard_intin_maxpksz: 8 bytes + usb_composite_hid_keyboard_intout_epaddr: EndpointAddress = 0x02 + usb_composite_hid_keyboard_intout_maxpksz: 8 bytes + usb_composite_hid_keyboard_support: false + usb_composite_hid_mouse_intin_epaddr: EndpointAddress = 0x83 + usb_composite_hid_mouse_intin_maxpksz: 8 bytes + usb_composite_hid_mouse_support: false + usb_composite_iconfig: 0 + usb_composite_idproduct: 9249 + usb_composite_idvender: 1003 + usb_composite_imanufact: 0 + usb_composite_iproduct: 0 + usb_composite_iserialnum: 0 + definition: Atmel:USB:0.0.1::USB_Device_Composite + functionality: USB_Device_COMPOSITE + api: USB:Device:COMPOSITE + dependencies: + USB Class MSC: USB_CLASS_MSC + USB Class CDC: USB_CLASS_CDC + USB Device Stack Core Instance: USB_DEVICE_STACK_CORE_INSTANCE + USB Class VENDOR: USB_CLASS_VENDOR + USB Class HID: USB_CLASS_HID + USB Class HUB: USB_CLASS_HUB +drivers: + ADC_0: + user_label: ADC_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync + functionality: ADC + api: HAL:Driver:ADC_Sync + configuration: + adc_advanced_settings: false + adc_arch_adjres: 0 + adc_arch_corren: false + adc_arch_dbgrun: false + adc_arch_event_settings: false + adc_arch_gain: 1x + adc_arch_gaincorr: 0 + adc_arch_inputoffset: 0 + adc_arch_inputscan: 0 + adc_arch_leftadj: false + adc_arch_offsetcorr: 0 + adc_arch_refcomp: false + adc_arch_resrdyeo: false + adc_arch_runstdby: false + adc_arch_samplen: 0 + adc_arch_samplenum: 1 sample + adc_arch_startei: false + adc_arch_syncei: false + adc_arch_winlt: 0 + adc_arch_winmode: No window mode + adc_arch_winmoneo: false + adc_arch_winut: 0 + adc_differential_mode: false + adc_freerunning_mode: false + adc_pinmux_negative: ADC AIN0 pin + adc_pinmux_positive: ADC AIN0 pin + adc_prescaler: Peripheral clock divided by 4 + adc_reference: 1.0V voltage reference + adc_resolution: 12-bit + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: ADC + input: Generic clock generator 0 + configuration: + adc_gclk_selection: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + enable_gclk_gen_0: true + enable_gclk_gen_1: false + enable_gclk_gen_2: false + enable_gclk_gen_3: false + enable_gclk_gen_4: false + enable_gclk_gen_5: false + enable_gclk_gen_6: false + enable_gclk_gen_7: false + gclk_arch_gen_0_RUNSTDBY: false + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_1_RUNSTDBY: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_2_RUNSTDBY: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_3_RUNSTDBY: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_4_RUNSTDBY: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_5_RUNSTDBY: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_6_RUNSTDBY: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_7_RUNSTDBY: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: 8MHz Internal Oscillator (OSC8M) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: false + gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) + optional_signals: [] + variant: null + clocks: + domain_group: null + FLASH_0: + user_label: FLASH_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::NVMCTRL::driver_config_definition::Flash::HAL:Driver:FLASH + functionality: Flash + api: HAL:Driver:FLASH + configuration: + nvm_arch_cache: false + nvm_arch_read_mode: No Miss Penalty + nvm_arch_sleepprm: Wake On Access + optional_signals: [] + variant: null + clocks: + domain_group: null + PM: + user_label: PM + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::PM::driver_config_definition::PM::HAL:HPL:PM + functionality: System + api: HAL:HPL:PM + configuration: + apba_div: '1' + apbb_div: '1' + apbc_div: '1' + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + nvm_wait_states: '0' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + configuration: {} + SPI_0: + user_label: SPI_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SERCOM0::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync + functionality: SPI + api: HAL:Driver:SPI_Master_Sync + configuration: + spi_master_advanced: false + spi_master_arch_cpha: Sample input on leading edge + spi_master_arch_cpol: SCK is low when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: In data stream + spi_master_arch_runstdby: false + spi_master_baud_rate: 50000 + spi_master_character_size: 8 bits + spi_master_dummybyte: 511 + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=2 + required_signals: + - name: SERCOM0/PAD/0 + pad: PA04 + label: MOSI + - name: SERCOM0/PAD/1 + pad: PA05 + label: SCK + - name: SERCOM0/PAD/2 + pad: PA06 + label: MISO + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + - name: Slow + input: Generic clock generator 3 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM1/PAD/0 + pad: PA16 + label: SDA + - name: SERCOM1/PAD/1 + pad: PA17 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + - name: Slow + input: Generic clock generator 3 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + USART_0: + user_label: USART_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 9600 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM2/PAD/0 + pad: PA08 + label: TX + - name: SERCOM2/PAD/1 + pad: PA09 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + - name: Slow + input: Generic clock generator 3 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + DELAY_0: + user_label: DELAY_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay + functionality: Delay + api: HAL:Driver:Delay + configuration: + systick_arch_tickint: false + optional_signals: [] + variant: null + clocks: + domain_group: null + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::RTC::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + rtc_arch_comp_val: 1024 + rtc_arch_prescaler: Peripheral clock divided by 1 + rtc_cmpeo0: false + rtc_event_control: false + rtc_ovfeo: false + rtc_pereo0: false + rtc_pereo1: false + rtc_pereo2: false + rtc_pereo3: false + rtc_pereo4: false + rtc_pereo5: false + rtc_pereo6: false + rtc_pereo7: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: RTC + input: Generic clock generator 0 + configuration: + rtc_clk_selection: Generic clock generator 0 + PWM_0: + user_label: PWM_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::TC3::driver_config_definition::PWM::HAL:Driver:PWM + functionality: PWM + api: HAL:Driver:PWM + configuration: + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_mode: Counter in 16-bit mode + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tceinv: false + tc_arch_wave_duty_val: 500 + tc_arch_wave_per_val: 1000 + tc_per: 50 + tc_prescaler: Divide by 8 + timer_event_control: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + configuration: + tc_gclk_selection: Generic clock generator 0 + DAC_0: + user_label: DAC_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::DAC::driver_config_definition::DAC::HAL:Driver:DAC.Sync + functionality: DAC + api: HAL:Driver:DAC_Sync + configuration: + dac_advanced_settings: false + dac_arch_bdwp: false + dac_arch_emptyeo: false + dac_arch_eoen: true + dac_arch_ioen: false + dac_arch_leftadj: false + dac_arch_refsel: Internal 1.0v reference + dac_arch_runstdby: false + dac_arch_startei: false + dac_arch_vpd: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: DAC + input: Generic clock generator 0 + configuration: + dac_gclk_selection: Generic clock generator 0 + DMAC: + user_label: DMAC + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_1_settings: false + dmac_channel_2_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_2: false + dmac_dstinc_3: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_enable_0: false + dmac_enable_1: false + dmac_enable_10: false + dmac_enable_11: false + dmac_enable_12: false + dmac_enable_13: false + dmac_enable_14: false + dmac_enable_15: false + dmac_enable_2: false + dmac_enable_3: false + dmac_enable_4: false + dmac_enable_5: false + dmac_enable_6: false + dmac_enable_7: false + dmac_enable_8: false + dmac_enable_9: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_2: No action + dmac_evact_3: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_2: false + dmac_evie_3: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_2: false + dmac_evoe_3: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: false + dmac_lvlen1: false + dmac_lvlen2: false + dmac_lvlen3: false + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_2: false + dmac_srcinc_3: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + SYSCTRL: + user_label: SYSCTRL + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SYSCTRL::driver_config_definition::SYSCTRL::HAL:HPL:SYSCTRL + functionality: System + api: HAL:HPL:SYSCTRL + configuration: + dfll48m_arch_bplckc: false + dfll48m_arch_calibration: true + dfll48m_arch_ccdis: false + dfll48m_arch_coarse: 10 + dfll48m_arch_enable: false + dfll48m_arch_fine: 512 + dfll48m_arch_llaw: false + dfll48m_arch_ondemand: true + dfll48m_arch_qldis: false + dfll48m_arch_runstdby: false + dfll48m_arch_stable: false + dfll48m_arch_usbcrm: true + dfll48m_arch_waitlock: false + dfll48m_mode: Closed Loop Mode + dfll48m_mul: 0 + dfll48m_ref_clock: Generic clock generator 4 + dfll_arch_cstep: 1 + dfll_arch_fstep: 1 + enable_dfll48m: false + enable_fdpll96m: false + enable_osc32k: false + enable_osc8m: true + enable_osculp32k: true + enable_xosc: false + enable_xosc32k: false + fdpll96m_arch_enable: false + fdpll96m_arch_lbypass: false + fdpll96m_arch_ondemand: true + fdpll96m_arch_runstdby: false + fdpll96m_clock_div: 0 + fdpll96m_ldr: 1463 + fdpll96m_ldrfrac: 13 + fdpll96m_ref_clock: Generic clock generator 3 + osc32k_arch_calib: 0 + osc32k_arch_en1k: false + osc32k_arch_en32k: false + osc32k_arch_enable: false + osc32k_arch_ondemand: true + osc32k_arch_overwrite_calibration: false + osc32k_arch_runstdby: false + osc32k_arch_startup: 3 Clock Cycles (92us) + osc32k_arch_wrtlock: false + osc8m_arch_calib: 0 + osc8m_arch_enable: true + osc8m_arch_ondemand: true + osc8m_arch_overwrite_calibration: false + osc8m_arch_runstdby: false + osc8m_presc: '8' + osculp32k_arch_calib: 0 + osculp32k_arch_overwrite_calibration: false + osculp32k_arch_wrtlock: false + xosc32k_arch_aampen: false + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 122 us + xosc32k_arch_wrtlock: false + xosc32k_arch_xtalen: false + xosc_arch_ampgc: false + xosc_arch_enable: false + xosc_arch_gain: 2Mhz + xosc_arch_ondemand: true + xosc_arch_runstdby: false + xosc_arch_startup: 31 us + xosc_arch_xtalen: false + xosc_frequency: 400000 + optional_signals: [] + variant: null + clocks: + domain_group: null + USB_0: + user_label: USB_0 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device + functionality: USB + api: HAL:Driver:USB_Device + configuration: + usb_arch_ep0_cache: Cached by 64 bytes buffer + usb_arch_ep1_cache: Cached by 64 bytes buffer + usb_arch_ep2_cache: Cached by 64 bytes buffer + usb_arch_ep3_cache: Cached by 64 bytes buffer + usb_arch_ep4_cache: Cached by 64 bytes buffer + usb_arch_ep5_cache: Cached by 64 bytes buffer + usb_arch_ep6_cache: Cached by 64 bytes buffer + usb_arch_ep7_cache: Cached by 64 bytes buffer + usb_ep1_I_CACHE: No cache + usb_ep2_I_CACHE: No cache + usb_ep3_I_CACHE: No cache + usb_ep4_I_CACHE: No cache + usb_ep5_I_CACHE: No cache + usb_ep6_I_CACHE: No cache + usb_ep7_I_CACHE: No cache + usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02) + usbd_arch_speed: Full speed + usbd_num_ep_sp: 4 (EP0 + 3 endpoints) + optional_signals: [] + variant: + specification: default + required_signals: + - name: USB/DM + pad: PA24 + label: Data- + - name: USB/DP + pad: PA25 + label: Data+ + clocks: + domain_group: + nodes: + - name: USB + input: Generic clock generator 0 + configuration: + usb_gclk_selection: Generic clock generator 0 +pads: + PA00: + name: PA00 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA00 + mode: Digital input + user_label: PA00 + configuration: null + PA01: + name: PA01 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA01 + mode: Digital input + user_label: PA01 + configuration: null + PA02: + name: PA02 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA02 + mode: Digital input + user_label: PA02 + configuration: null + PA03: + name: PA03 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA03 + mode: Digital input + user_label: PA03 + configuration: null + PB08: + name: PB08 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB08 + mode: Digital input + user_label: PB08 + configuration: null + PB09: + name: PB09 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB09 + mode: Digital input + user_label: PB09 + configuration: null + PA04: + name: PA04 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA04 + mode: Digital output + user_label: PA04 + configuration: null + PA05: + name: PA05 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA05 + mode: Digital output + user_label: PA05 + configuration: null + PA06: + name: PA06 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA06 + mode: Digital input + user_label: PA06 + configuration: null + PA07: + name: PA07 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA07 + mode: Digital input + user_label: PA07 + configuration: null + PA08: + name: PA08 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA08 + mode: Peripheral IO + user_label: PA08 + configuration: null + PA09: + name: PA09 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA09 + mode: Peripheral IO + user_label: PA09 + configuration: null + PA10: + name: PA10 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA10 + mode: Digital input + user_label: PA10 + configuration: null + PA11: + name: PA11 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA11 + mode: Digital input + user_label: PA11 + configuration: null + PB10: + name: PB10 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB10 + mode: Digital input + user_label: PB10 + configuration: null + PB11: + name: PB11 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB11 + mode: Digital input + user_label: PB11 + configuration: null + PA12: + name: PA12 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA12 + mode: Digital input + user_label: PA12 + configuration: null + PA13: + name: PA13 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA13 + mode: Digital input + user_label: PA13 + configuration: null + PA14: + name: PA14 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA14 + mode: Digital input + user_label: PA14 + configuration: null + PA15: + name: PA15 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA15 + mode: Digital input + user_label: PA15 + configuration: null + PA16: + name: PA16 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA16 + mode: I2C + user_label: PA16 + configuration: null + PA17: + name: PA17 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA17 + mode: I2C + user_label: PA17 + configuration: null + PA18: + name: PA18 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA18 + mode: Digital input + user_label: PA18 + configuration: null + PA19: + name: PA19 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA19 + mode: Digital input + user_label: PA19 + configuration: null + PA20: + name: PA20 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA20 + mode: Digital input + user_label: PA20 + configuration: null + PA21: + name: PA21 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA21 + mode: Digital input + user_label: PA21 + configuration: null + PA22: + name: PA22 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA22 + mode: Digital input + user_label: PA22 + configuration: null + PA23: + name: PA23 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA23 + mode: Digital input + user_label: PA23 + configuration: null + PA24: + name: PA24 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA24 + mode: Advanced + user_label: PA24 + configuration: null + PA25: + name: PA25 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA25 + mode: Advanced + user_label: PA25 + configuration: null + PB22: + name: PB22 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB22 + mode: Digital input + user_label: PB22 + configuration: null + PB23: + name: PB23 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB23 + mode: Digital input + user_label: PB23 + configuration: null + PA27: + name: PA27 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA27 + mode: Digital input + user_label: PA27 + configuration: null + PA28: + name: PA28 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA28 + mode: Digital input + user_label: PA28 + configuration: null + PA30: + name: PA30 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA30 + mode: Digital input + user_label: PA30 + configuration: null + PA31: + name: PA31 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA31 + mode: Digital input + user_label: PA31 + configuration: null + PB02: + name: PB02 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB02 + mode: Digital input + user_label: PB02 + configuration: null + PB03: + name: PB03 + definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB03 + mode: Digital input + user_label: PB03 + configuration: null +toolchain_options: [] diff --git a/atmel-samd/asf4/samd21/atmel_start_pins.h b/atmel-samd/asf4/samd21/atmel_start_pins.h new file mode 100644 index 0000000000000..f8d0bd3503cfc --- /dev/null +++ b/atmel-samd/asf4/samd21/atmel_start_pins.h @@ -0,0 +1,63 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAMD21 has 8 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 + +#define PA00 GPIO(GPIO_PORTA, 0) +#define PA01 GPIO(GPIO_PORTA, 1) +#define PA02 GPIO(GPIO_PORTA, 2) +#define PA03 GPIO(GPIO_PORTA, 3) +#define PA04 GPIO(GPIO_PORTA, 4) +#define PA05 GPIO(GPIO_PORTA, 5) +#define PA06 GPIO(GPIO_PORTA, 6) +#define PA07 GPIO(GPIO_PORTA, 7) +#define PA08 GPIO(GPIO_PORTA, 8) +#define PA09 GPIO(GPIO_PORTA, 9) +#define PA10 GPIO(GPIO_PORTA, 10) +#define PA11 GPIO(GPIO_PORTA, 11) +#define PA12 GPIO(GPIO_PORTA, 12) +#define PA13 GPIO(GPIO_PORTA, 13) +#define PA14 GPIO(GPIO_PORTA, 14) +#define PA15 GPIO(GPIO_PORTA, 15) +#define PA16 GPIO(GPIO_PORTA, 16) +#define PA17 GPIO(GPIO_PORTA, 17) +#define PA18 GPIO(GPIO_PORTA, 18) +#define PA19 GPIO(GPIO_PORTA, 19) +#define PA20 GPIO(GPIO_PORTA, 20) +#define PA21 GPIO(GPIO_PORTA, 21) +#define PA22 GPIO(GPIO_PORTA, 22) +#define PA23 GPIO(GPIO_PORTA, 23) +#define PA24 GPIO(GPIO_PORTA, 24) +#define PA25 GPIO(GPIO_PORTA, 25) +#define PA27 GPIO(GPIO_PORTA, 27) +#define PA28 GPIO(GPIO_PORTA, 28) +#define PA30 GPIO(GPIO_PORTA, 30) +#define PA31 GPIO(GPIO_PORTA, 31) +#define PB02 GPIO(GPIO_PORTB, 2) +#define PB03 GPIO(GPIO_PORTB, 3) +#define PB08 GPIO(GPIO_PORTB, 8) +#define PB09 GPIO(GPIO_PORTB, 9) +#define PB10 GPIO(GPIO_PORTB, 10) +#define PB11 GPIO(GPIO_PORTB, 11) +#define PB22 GPIO(GPIO_PORTB, 22) +#define PB23 GPIO(GPIO_PORTB, 23) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/atmel-samd/asf4/samd21/config/hpl_adc_config.h b/atmel-samd/asf4/samd21/config/hpl_adc_config.h new file mode 100644 index 0000000000000..ea69d4a698b63 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_adc_config.h @@ -0,0 +1,296 @@ +/* Auto-generated config file hpl_adc_config.h */ +#ifndef HPL_ADC_CONFIG_H +#define HPL_ADC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_ADC_0_ENABLE +#define CONF_ADC_0_ENABLE 1 +#endif + +// Basic Configuration + +// Conversion resolution +// <0x0=>12-bit +// <0x1=>16-bit (averaging must be enabled) +// <0x2=>10-bit +// <0x3=>8-bit +// Defines the bit resolution for the ADC sample values (RESSEL) +// adc_resolution +#ifndef CONF_ADC_0_RESSEL +#define CONF_ADC_0_RESSEL 0x0 +#endif + +// Reference Selection +// <0x0=>1.0V voltage reference +// <0x1=>1/1.48 VDDANA +// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) +// <0x3=>External reference A +// <0x4=>External reference B +// Select the reference for the ADC (REFSEL) +// adc_reference +#ifndef CONF_ADC_0_REFSEL +#define CONF_ADC_0_REFSEL 0x0 +#endif + +// Prescaler configuration +// <0x0=>Peripheral clock divided by 4 +// <0x1=>Peripheral clock divided by 8 +// <0x2=>Peripheral clock divided by 16 +// <0x3=>Peripheral clock divided by 32 +// <0x4=>Peripheral clock divided by 64 +// <0x5=>Peripheral clock divided by 128 +// <0x6=>Peripheral clock divided by 256 +// <0x7=>Peripheral clock divided by 512 +// These bits define the ADC clock relative to the peripheral clock (PRESCALER) +// adc_prescaler +#ifndef CONF_ADC_0_PRESCALER +#define CONF_ADC_0_PRESCALER 0x0 +#endif + +// Free Running Mode +// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) +// adc_freerunning_mode +#ifndef CONF_ADC_0_FREERUN +#define CONF_ADC_0_FREERUN 0 +#endif + +// Differential Mode +// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) +// adc_differential_mode +#ifndef CONF_ADC_0_DIFFMODE +#define CONF_ADC_0_DIFFMODE 0 +#endif + +// Positive Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x08=>ADC AIN8 pin +// <0x09=>ADC AIN9 pin +// <0x0A=>ADC AIN10 pin +// <0x0B=>ADC AIN11 pin +// <0x0C=>ADC AIN12 pin +// <0x0D=>ADC AIN13 pin +// <0x0E=>ADC AIN14 pin +// <0x0F=>ADC AIN15 pin +// <0x10=>ADC AIN16 pin +// <0x11=>ADC AIN17 pin +// <0x12=>ADC AIN18 pin +// <0x13=>ADC AIN19 pin +// <0x18=>Temperature reference +// <0x19=>Bandgap voltage +// <0x1A=>1/4 scaled core supply +// <0x1B=>1/4 scaled I/O supply +// <0x1C=>DAC output +// These bits define the Mux selection for the positive ADC input. (MUXPOS) +// adc_pinmux_positive +#ifndef CONF_ADC_0_MUXPOS +#define CONF_ADC_0_MUXPOS 0x0 +#endif + +// Negative Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x18=>Internal ground +// <0x19=>I/O ground +// These bits define the Mux selection for the negative ADC input. (MUXNEG) +// adc_pinmux_negative +#ifndef CONF_ADC_0_MUXNEG +#define CONF_ADC_0_MUXNEG 0x0 +#endif + +// + +// Advanced Configuration +// adc_advanced_settings +#ifndef CONF_ADC_0_ADVANCED_CONFIG +#define CONF_ADC_0_ADVANCED_CONFIG 0 +#endif + +// Run in standby +// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) +// adc_arch_runstdby +#ifndef CONF_ADC_0_RUNSTDBY +#define CONF_ADC_0_RUNSTDBY 0 +#endif + +// Debug Run +// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) +// adc_arch_dbgrun +#ifndef CONF_ADC_0_DBGRUN +#define CONF_ADC_0_DBGRUN 0 +#endif + +// Left-Adjusted Result +// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) +// adc_arch_leftadj +#ifndef CONF_ADC_0_LEFTADJ +#define CONF_ADC_0_LEFTADJ 0 +#endif + +// Reference Buffer Offset Compensation Enable +// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) +// adc_arch_refcomp +#ifndef CONF_ADC_0_REFCOMP +#define CONF_ADC_0_REFCOMP 0 +#endif + +// Digital Correction Logic Enabled +// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) +// adc_arch_corren +#ifndef CONF_ADC_0_CORREN +#define CONF_ADC_0_CORREN 0 +#endif + +// Offset Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) +// adc_arch_offsetcorr +#ifndef CONF_ADC_0_OFFSETCORR +#define CONF_ADC_0_OFFSETCORR 0 +#endif + +// Gain Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) +// adc_arch_gaincorr +#ifndef CONF_ADC_0_GAINCORR +#define CONF_ADC_0_GAINCORR 0 +#endif + +// Gain Factor Selection +// <0x0=>1x +// <0x1=>2x +// <0x2=>4x +// <0x3=>8x +// <0x4=>16x +// <0xF=>1/2x +// These bits set the gain factor of the ADC gain stage. (GAIN) +// adc_arch_gain +#ifndef CONF_ADC_0_GAIN +#define CONF_ADC_0_GAIN 0x0 +#endif + +// Adjusting Result / Division Coefficient <0-7> +// These bits define the division coefficient in 2n steps. (ADJRES) +// adc_arch_adjres +#ifndef CONF_ADC_0_ADJRES +#define CONF_ADC_0_ADJRES 0x0 +#endif + +// Number of Samples to be Collected +// <0x0=>1 sample +// <0x1=>2 samples +// <0x2=>4 samples +// <0x3=>8 samples +// <0x4=>16 samples +// <0x5=>32 samples +// <0x6=>64 samples +// <0x7=>128 samples +// <0x8=>256 samples +// <0x9=>512 samples +// <0xA=>1024 samples +// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) +// adc_arch_samplenum +#ifndef CONF_ADC_0_SAMPLENUM +#define CONF_ADC_0_SAMPLENUM 0x0 +#endif + +// Sampling Time Length <0-63> +// These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) +// adc_arch_samplen +#ifndef CONF_ADC_0_SAMPLEN +#define CONF_ADC_0_SAMPLEN 0 +#endif + +// Window Monitor Mode +// <0x0=>No window mode +// <0x1=>Mode 1: RESULT above lower threshold +// <0x2=>Mode 2: RESULT beneath upper threshold +// <0x3=>Mode 3: RESULT inside lower and upper threshold +// <0x4=>Mode 4: RESULT outside lower and upper threshold +// These bits enable and define the window monitor mode. (WINMODE) +// adc_arch_winmode +#ifndef CONF_ADC_0_WINMODE +#define CONF_ADC_0_WINMODE 0x0 +#endif + +// Window Monitor Lower Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINLT) +// adc_arch_winlt +#ifndef CONF_ADC_0_WINLT +#define CONF_ADC_0_WINLT 0 +#endif + +// Window Monitor Upper Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINUT) +// adc_arch_winut +#ifndef CONF_ADC_0_WINUT +#define CONF_ADC_0_WINUT 0 +#endif + +// Number of Input Channels Included in Scan <0-15> +// This register gives the number of input sources included in pin scan. The number of input sources included is INPUTSCAN + 1. 0 disables the input scan feature. (INPUTSCAN) +// adc_arch_inputscan +#ifndef CONF_ADC_0_INPUTSCAN +#define CONF_ADC_0_INPUTSCAN 0 +#endif + +// Positive Mux Setting Offset <0-15> +// When inputscan is enabled this value define the pin offset, which means that the actual input pin sampled is the muxpos pin + input offset. (INPUTOFFSET) +// adc_arch_inputoffset +#ifndef CONF_ADC_0_INPUTOFFSET +#define CONF_ADC_0_INPUTOFFSET 0 +#endif + +// + +// Event Control +// adc_arch_event_settings +#ifndef CONF_ADC_0_EVENT_CONFIG +#define CONF_ADC_0_EVENT_CONFIG 0 +#endif + +// Window Monitor Event Out +// Enables event output on window event (WINMONEO) +// adc_arch_winmoneo +#ifndef CONF_ADC_0_WINMONEO +#define CONF_ADC_0_WINMONEO 0 +#endif + +// Result Ready Event Out +// Enables event output on result ready event (RESRDEO) +// adc_arch_resrdyeo +#ifndef CONF_ADC_0_RESRDYEO +#define CONF_ADC_0_RESRDYEO 0 +#endif + +// Trigger Synchronization On Event +// Trigger a flush operation and a new conversion on event in (SYNCEI) +// adc_arch_syncei +#ifndef CONF_ADC_0_SYNCEI +#define CONF_ADC_0_SYNCEI 0 +#endif + +// Trigger Conversion On Event +// Trigger a conversion on event. (STARTEI) +// adc_arch_startei +#ifndef CONF_ADC_0_STARTEI +#define CONF_ADC_0_STARTEI 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_ADC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_dac_config.h b/atmel-samd/asf4/samd21/config/hpl_dac_config.h new file mode 100644 index 0000000000000..4b1b152fb5416 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_dac_config.h @@ -0,0 +1,86 @@ +/* Auto-generated config file hpl_dac_config.h */ +#ifndef HPL_DAC_CONFIG_H +#define HPL_DAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic configuration +// Reference Selection +// <0x00=> Internal 1.0v reference +// <0x01=> AVCC +// <0x02=> External reference +// dac_arch_refsel +#ifndef CONF_DAC_REFSEL +#define CONF_DAC_REFSEL 0 +#endif +// + +// Advanced Configuration +// dac_advanced_settings +#ifndef CONF_DAC_ADVANCED_CONFIG +#define CONF_DAC_ADVANCED_CONFIG 0 +#endif + +// Run in standby +// Indicates whether the DAC will continue running in standby sleep mode or not +// dac_arch_runstdby +#ifndef CONF_DAC_RUNSTDBY +#define CONF_DAC_RUNSTDBY 0 +#endif + +// Bypass DATABUF Write Protection +// Indicate whether DATABUF write protection is bypass +// dac_arch_bdwp +#ifndef CONF_DAC_BDWP +#define CONF_DAC_BDWP 0 +#endif + +// Voltage Pump Disable +// Indicate whether voltage pump is disable or not +// dac_arch_vpd +#ifndef CONF_DAC_VPD +#define CONF_DAC_VPD 0 +#endif + +// Left Adjusted Data +// Indicate how the data is adjusted in the Data and Data Buffer register +// dac_arch_leftadj +#ifndef CONF_DAC_LEFTADJ +#define CONF_DAC_LEFTADJ 0 +#endif + +// Internal Output Enable +// Indicate whether internal output is enable or not +// dac_arch_ioen +#ifndef CONF_DAC_IOEN +#define CONF_DAC_IOEN 0 +#endif + +// External Output Enable +// Indicate whether external output is enable or not +// dac_arch_eoen +#ifndef CONF_DAC_EOEN +#define CONF_DAC_EOEN 1 +#endif + +// + +// Event configuration +// Data Buffer Empty Event Output +// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// dac_arch_emptyeo +#ifndef CONF_DAC_EMPTYEO +#define CONF_DAC_EMPTYEO 0 +#endif + +// Start Conversion on Event Input +// Indicate whether Start Conversion is enabled and data are loaded from the Data Buffer register to the Data register upon event reception or not +// dac_arch_startei +#ifndef CONF_DAC_STARTEI +#define CONF_DAC_STARTEI 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_DAC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_dmac_config.h b/atmel-samd/asf4/samd21/config/hpl_dmac_config.h new file mode 100644 index 0000000000000..3667e873ba303 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_dmac_config.h @@ -0,0 +1,3057 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_gclk_config.h b/atmel-samd/asf4/samd21/config/hpl_gclk_config.h new file mode 100644 index 0000000000000..790aa293aee2d --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_gclk_config.h @@ -0,0 +1,618 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_RUNSTDBY +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif + +// Generic clock generator 0 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SRC +#define CONF_GCLK_GEN_0_SRC GCLK_GENCTRL_SRC_OSC8M +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif + +// +// // Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_RUNSTDBY +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif + +// Generic clock generator 1 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SRC +#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif + +// +// // Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_RUNSTDBY +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif + +// Generic clock generator 2 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SRC +#define CONF_GCLK_GEN_2_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif + +// +// // Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_RUNSTDBY +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif + +// Generic clock generator 3 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SRC +#define CONF_GCLK_GEN_3_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif + +// +// // Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_RUNSTDBY +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif + +// Generic clock generator 4 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SRC +#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif + +// +// // Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_RUNSTDBY +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif + +// Generic clock generator 5 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SRC +#define CONF_GCLK_GEN_5_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif + +// +// // Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_RUNSTDBY +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif + +// Generic clock generator 6 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SRC +#define CONF_GCLK_GEN_6_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif + +// +// // Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_RUNSTDBY +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif + +// Generic clock generator 7 source +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz High Accuracy Internal Oscillator (OSC32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// 8MHz Internal Oscillator (OSC8M) +// Digital Frequency Locked Loop (DFLL48M) +// Fractional Digital Phase Locked Loop (FDPLL96M) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SRC +#define CONF_GCLK_GEN_7_SRC GCLK_GENCTRL_SRC_XOSC +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h b/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h new file mode 100644 index 0000000000000..88d6bb93ff414 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h @@ -0,0 +1,38 @@ +/* Auto-generated config file hpl_nvmctrl_config.h */ +#ifndef HPL_NVMCTRL_CONFIG_H +#define HPL_NVMCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings + +// Read Mode Selection +// <0x00=> No Miss Penalty +// <0x01=> Low Power +// <0x02=> Deterministic +// nvm_arch_read_mode +#ifndef CONF_NVM_READ_MODE +#define CONF_NVM_READ_MODE 0 +#endif + +// Power Reduction Mode During Sleep +// <0x00=> Wake On Access +// <0x01=> Wake Up Instant +// <0x03=> Disabled +// nvm_arch_sleepprm +#ifndef CONF_NVM_SLEEPPRM +#define CONF_NVM_SLEEPPRM 0 +#endif + +// Cache Disable +// Indicate whether cache is disable or not +// nvm_arch_cache +#ifndef CONF_NVM_CACHE +#define CONF_NVM_CACHE 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_NVMCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_pm_config.h b/atmel-samd/asf4/samd21/config/hpl_pm_config.h new file mode 100644 index 0000000000000..b4c704d128e7c --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_pm_config.h @@ -0,0 +1,134 @@ +/* Auto-generated config file hpl_pm_config.h */ +#ifndef HPL_PM_CONFIG_H +#define HPL_PM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// CPU Clock Settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// CPU clock Prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for Main CPU clock +// cpu_div +#ifndef CONF_CPU_DIV +#define CONF_CPU_DIV PM_CPUSEL_CPUDIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// APBA Clock Select +// APBA clock prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// APBA clock prescalar +// apba_div +#ifndef CONF_APBA_DIV +#define CONF_APBA_DIV PM_APBASEL_APBADIV_DIV1 +#endif +// + +#if CONF_APBA_DIV < CONF_CPU_DIV +#warning APBA DIV cannot less than CPU DIV +#endif + +// APBB Clock Select +// APBB clock prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// APBB clock prescalar +// apbb_div +#ifndef CONF_APBB_DIV +#define CONF_APBB_DIV PM_APBBSEL_APBBDIV_DIV1 +#endif +// + +#if CONF_APBB_DIV < CONF_CPU_DIV +#warning APBB DIV cannot less than CPU DIV +#endif + +// APBC Clock Select +// APBC clock prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// APBC clock prescalar +// apbc_div +#ifndef CONF_APBC_DIV +#define CONF_APBC_DIV PM_APBCSEL_APBCDIV_DIV1 +#endif +// + +#if CONF_APBC_DIV < CONF_CPU_DIV +#warning APBC DIV cannot less than CPU DIV +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_PM_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_rtc_config.h b/atmel-samd/asf4/samd21/config/hpl_rtc_config.h new file mode 100644 index 0000000000000..929c70c8c67ea --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_rtc_config.h @@ -0,0 +1,117 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// Prescaler configuration +// <0x0=>Peripheral clock divided by 1 +// <0x1=>Peripheral clock divided by 2 +// <0x2=>Peripheral clock divided by 4 +// <0x3=>Peripheral clock divided by 8 +// <0x4=>Peripheral clock divided by 16 +// <0x5=>Peripheral clock divided by 32 +// <0x6=>Peripheral clock divided by 64 +// <0x7=>Peripheral clock divided by 128 +// <0x8=>Peripheral clock divided by 256 +// <0x9=>Peripheral clock divided by 512 +// <0xA=>Peripheral clock divided by 1024 +// These bits define the RTC clock relative to the peripheral clock +// rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0x0 + +#endif + +// Compare Value <1-4294967295> +// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// by default 1M clock input, 1 prescaler, 1024 compare value, the ticks period equals to 1ms. +// rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL +#define CONF_RTC_COMP_VAL 1024 + +#endif + +// Event control +// rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// Periodic Interval 0 Event Output +// This bit indicates whether Periodic interval 0 event is enabled and will be generated +// rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// Periodic Interval 1 Event Output +// This bit indicates whether Periodic interval 1 event is enabled and will be generated +// rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// Periodic Interval 2 Event Output +// This bit indicates whether Periodic interval 2 event is enabled and will be generated +// rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// Periodic Interval 3 Event Output +// This bit indicates whether Periodic interval 3 event is enabled and will be generated +// rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// Periodic Interval 4 Event Output +// This bit indicates whether Periodic interval 4 event is enabled and will be generated +// rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// Periodic Interval 5 Event Output +// This bit indicates whether Periodic interval 5 event is enabled and will be generated +// rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// Periodic Interval 6 Event Output +// This bit indicates whether Periodic interval 6 event is enabled and will be generated +// rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// Periodic Interval 7 Event Output +// This bit indicates whether Periodic interval 7 event is enabled and will be generated +// rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// Compare 0 Event Output +// This bit indicates whether Compare O event is enabled and will be generated +// rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// Overflow Event Output +// This bit indicates whether Overflow event is enabled and will be generated +// rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_sercom_config.h b/atmel-samd/asf4/samd21/config/hpl_sercom_config.h new file mode 100644 index 0000000000000..50515745d3242 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_sercom_config.h @@ -0,0 +1,534 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_0_SPI_MODE +#define CONF_SERCOM_0_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_0_SPI_RXEN +#define CONF_SERCOM_0_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_0_SPI_CHSIZE +#define CONF_SERCOM_0_SPI_CHSIZE 0x0 +#endif + +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_0_SPI_BAUD +#define CONF_SERCOM_0_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_0_SPI_ADVANCED +#define CONF_SERCOM_0_SPI_ADVANCED 0 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE +#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_0_SPI_DORD +#define CONF_SERCOM_0_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_0_SPI_CPOL +#define CONF_SERCOM_0_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_0_SPI_CPHA +#define CONF_SERCOM_0_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_0_SPI_IBON +#define CONF_SERCOM_0_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_0_SPI_RUNSTDBY +#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_0_SPI_DBGSTOP +#define CONF_SERCOM_0_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_0_SPI_AMODE_EN +#define CONF_SERCOM_0_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_AMODE +#define CONF_SERCOM_0_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDR +#define CONF_SERCOM_0_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDRMASK +#define CONF_SERCOM_0_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_SSDE +#define CONF_SERCOM_0_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_MSSEN +#define CONF_SERCOM_0_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_0_SPI_PLOADEN +#define CONF_SERCOM_0_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_0_SPI_RXPO +#define CONF_SERCOM_0_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_0_SPI_TXPO +#define CONF_SERCOM_0_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_0_SPI_BAUD_RATE +#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 +#endif + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_1_I2CM_BAUD +#define CONF_SERCOM_1_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN +#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN +#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_1_I2CM_LOWTOUT +#define CONF_SERCOM_1_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_1_I2CM_INACTOUT +#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_1_I2CM_SDAHOLD +#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY +#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_1_I2CM_SPEED +#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_1_I2CM_TRISE +#define CONF_SERCOM_1_I2CM_TRISE 215 +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ + - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_1_I2CM_BAUD * 10)) +#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE +#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_1_I2CM_BAUD_RATE \ + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include + +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_2_USART_RXEN +#define CONF_SERCOM_2_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_2_USART_TXEN +#define CONF_SERCOM_2_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_2_USART_PARITY +#define CONF_SERCOM_2_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_2_USART_CHSIZE +#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_2_USART_SBMODE +#define CONF_SERCOM_2_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_2_USART_BAUD +#define CONF_SERCOM_2_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG +#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_2_USART_RUNSTDBY +#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_2_USART_IBON +#define CONF_SERCOM_2_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_2_USART_SFDE +#define CONF_SERCOM_2_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_2_USART_CLODEN +#define CONF_SERCOM_2_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_2_USART_MODE +#define CONF_SERCOM_2_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x3=>3x +// How many over-sampling bits used when samling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_2_USART_SAMPR +#define CONF_SERCOM_2_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_2_USART_SAMPA +#define CONF_SERCOM_2_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_2_USART_FRACTIONAL +#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_2_USART_DORD +#define CONF_SERCOM_2_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_2_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_2_USART_ENC +#define CONF_SERCOM_2_USART_ENC 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_2_USART_CMODE +#define CONF_SERCOM_2_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_2_USART_RXPO +#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA09 */ +#endif + +#ifndef CONF_SERCOM_2_USART_TXPO +#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA08 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_2_USART_PARITY == 0 +#define CONF_SERCOM_2_USART_PMODE 0 +#define CONF_SERCOM_2_USART_FORM 0 +#else +#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 +#define CONF_SERCOM_2_USART_FORM 1 +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_2_USART_SAMPR == 0 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 1 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 2 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 3 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_2_USART_SAMPR == 4 +#ifndef CONF_SERCOM_2_USART_BAUD_RATE +#define CONF_SERCOM_2_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h b/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h new file mode 100644 index 0000000000000..ab4c48d528bcd --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h @@ -0,0 +1,678 @@ +/* Auto-generated config file hpl_sysctrl_config.h */ +#ifndef HPL_SYSCTRL_CONFIG_H +#define HPL_SYSCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_DFLL_OPEN_LOOP_MODE 0 +#define CONF_DFLL_CLOSED_LOOP_MODE 1 + +#define CONF_XOSC_STARTUP_TIME_31MCS 0 +#define CONF_XOSC_STARTUP_TIME_61MCS 1 +#define CONF_XOSC_STARTUP_TIME_122MCS 2 +#define CONF_XOSC_STARTUP_TIME_244MCS 3 +#define CONF_XOSC_STARTUP_TIME_488MCS 4 +#define CONF_XOSC_STARTUP_TIME_977MCS 5 +#define CONF_XOSC_STARTUP_TIME_1953MCS 6 +#define CONF_XOSC_STARTUP_TIME_3906MCS 7 +#define CONF_XOSC_STARTUP_TIME_7813MCS 8 +#define CONF_XOSC_STARTUP_TIME_15625MCS 9 +#define CONF_XOSC_STARTUP_TIME_31250MCS 10 +#define CONF_XOSC_STARTUP_TIME_62500MCS 11 +#define CONF_XOSC_STARTUP_TIME_125000MCS 12 +#define CONF_XOSC_STARTUP_TIME_250000MCS 13 +#define CONF_XOSC_STARTUP_TIME_500000MCS 14 +#define CONF_XOSC_STARTUP_TIME_1000000MCS 15 + +#define CONF_OSC_STARTUP_TIME_92MCS 0 +#define CONF_OSC_STARTUP_TIME_122MCS 1 +#define CONF_OSC_STARTUP_TIME_183MCS 2 +#define CONF_OSC_STARTUP_TIME_305MCS 3 +#define CONF_OSC_STARTUP_TIME_549MCS 4 +#define CONF_OSC_STARTUP_TIME_1038MCS 5 +#define CONF_OSC_STARTUP_TIME_2014MCS 6 +#define CONF_OSC_STARTUP_TIME_3967MCS 7 + +#define CONF_XOSC32K_STARTUP_TIME_122MCS 0 +#define CONF_XOSC32K_STARTUP_TIME_1068MCS 1 +#define CONF_XOSC32K_STARTUP_TIME_65592MCS 2 +#define CONF_XOSC32K_STARTUP_TIME_125092MCS 3 +#define CONF_XOSC32K_STARTUP_TIME_500092MCS 4 +#define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5 +#define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6 +#define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7 + +// 8MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC8M is enabled or not +// enable_osc8m +#ifndef CONF_OSC8M_CONFIG +#define CONF_OSC8M_CONFIG 1 +#endif + +// 8MHz Internal Oscillator (OSC8M) Control +// Internal 8M Oscillator Enable +// Indicates whether Internal 8 Mhz Oscillator is enabled or not +// osc8m_arch_enable +#ifndef CONF_OSC8M_ENABLE +#define CONF_OSC8M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not. +// If enabled, the oscillator will only be running when requested by a peripheral. +// If disabled, the oscillator will always be running when enabled. +// osc8m_arch_ondemand +#ifndef CONF_OSC8M_ONDEMAND +#define CONF_OSC8M_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// osc8m_arch_runstdby +#ifndef CONF_OSC8M_RUNSTDBY +#define CONF_OSC8M_RUNSTDBY 0 +#endif + +// Prescaler +// 1 +// 2 +// 4 +// 8 +// Prescaler for Internal 8Mhz OSC +// Default: No Prescaling +// osc8m_presc +#ifndef CONF_OSC8M_PRESC +#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val +#endif + +// Overwrite Default Osc Calibration +// Overwrite Default Osc Calibration +// osc8m_arch_overwrite_calibration +#ifndef CONF_OSC8M_OVERWRITE_CALIBRATION +#define CONF_OSC8M_OVERWRITE_CALIBRATION 0 +#endif + +// Osc Calibration Value <0-65535> +// Set the Oscillator Calibration Value +// Default: 1 +// osc8m_arch_calib +#ifndef CONF_OSC8M_CALIB +#define CONF_OSC8M_CALIB 0 +#endif + +// +// + +// 32kHz Internal Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// 32kHz Internal Oscillator (OSC32K) Control +// Internal 32K Oscillator Enable +// Indicates whether Internal 32K Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// On Demand Control +// Enable On Demand +// If this bit is 0: The oscillator is always on, if enabled. +// If this bit is 1, the oscillator will only be running when requested by a peripheral. +// osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// Enable 32Khz Output +// Enable 32 Khz Output +// osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif + +// Enable 1K +// Enable 1K +// osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// Write Lock +// Write Lock +// osc32k_arch_wrtlock +#ifndef CONF_OSC32K_WRTLOCK +#define CONF_OSC32K_WRTLOCK 0 +#endif + +// Start up time for the 32K Oscillator +// 3 Clock Cycles (92us) +// 4 Clock Cycles (122us) +// 6 Clock Cycles (183us) +// 10 Clock Cycles (305us) +// 18 Clock Cycles (549us) +// 34 Clock Cycles (1038us) +// 66 Clock Cycles (2014us) +// 130 Clock Cycles (3967us) +// Start Up Time for the 32K Oscillator +// Default: 10 Clock Cycles (305us) +// osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS +#endif + +// Overwrite Default Osc Calibration +// Overwrite Default Osc Calibration +// osc32k_arch_overwrite_calibration +#ifndef CONF_OSC32K_OVERWRITE_CALIBRATION +#define CONF_OSC32K_OVERWRITE_CALIBRATION 0 +#endif + +// Osc Calibration Value <0-65535> +// Set the Oscillator Calibration Value +// Default: 0 +// osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0 +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator (XOSC32K) Control +// External 32K Oscillator Enable +// Indicates whether External 32K Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// On Demand +// Enable On Demand. +// If this bit is 0: The oscillator is always on, if enabled. +// If this bit is 1: the oscillator will only be running when requested by a peripheral. +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// Enable 1K +// Enable 1K +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// Enable 32Khz Output +// Enable 32 Khz Output +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Enable XTAL +// Enable XTAL +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 0 +#endif + +// Write Lock +// Write Lock +// xosc32k_arch_wrtlock +#ifndef CONF_XOSC32K_WRTLOCK +#define CONF_XOSC32K_WRTLOCK 0 +#endif + +// Automatic Amplitude Control Enable +// Indicates whether Automatic Amplitude Control is Enabled or not +// xosc32k_arch_aampen +#ifndef CONF_XOSC32K_AAMPEN +#define CONF_XOSC32K_AAMPEN 0 +#endif + +// Start up time for the 32K Oscillator +// 122 us +// 1068 us +// 62592 us +// 1125092 us +// 500092 us +// 1000092 us +// 2000092 us +// 4000092 us +// Start Up Time for the 32K Oscillator +// Default: 122 us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS +#endif + +// +// + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for External Multipurpose Osc is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator (XOSC) Control +// Enable +// Indicates whether External Multipurpose Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// On Demand +// Enable On Demand +// If this bit is 0: The oscillator is always on, if enabled. +// If this bit is 1: the oscillator will only be running when requested by a peripheral. +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Enable XTAL +// Enable XTAL +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif + +// Automatic Amplitude Control Enable +// Indicates whether Automatic Amplitude Control is Enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// Gain of the Oscillator +// 2Mhz +// 4Mhz +// 8Mhz +// 16Mhz +// 30Mhz +// Select the Gain of the oscillator +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val +#endif + +// Start up time for the External Oscillator +// 31 us +// 61 us +// 122 us +// 244 us +// 488 us +// 977 us +// 1953 us +// 3906 us +// 7813 us +// 15625 us +// 31250 us +// 62500 us +// 125000 us +// 250000 us +// 500000 us +// 1000000 us +// Start Up Time for the External Oscillator +// Default: 31 us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control +// Write Lock +// Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration +// osculp32k_arch_wrtlock +#ifndef CONF_OSCULP32K_WRTLOCK +#define CONF_OSCULP32K_WRTLOCK 0 +#endif + +// Overwrite Default Osc Calibration +// Overwrite Default Osc Calibration +// osculp32k_arch_overwrite_calibration +#ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION +#define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0 +#endif + +// Osc Calibration Value <0-255> +// Set the Oscillator Calibration Value +// Default: 0 +// osculp32k_arch_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0 +#endif + +// +// + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll48m +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// dfll48m_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK4_Val +#endif + +// DFLL Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll48m_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is Enables or not +// dfll48m_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 0 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass coarse lock is enabled or not +// dfll48m_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Quick Lock Disable +// dfll48m_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Chill Cycle Disable +// dfll48m_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// On Demand +// Enable On Demand +// If this bit is 0: The DFLL is always on, if enabled. +// If this bit is 1: the DFLL will only be running when requested by a peripheral. +// dfll48m_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The DFLL is disabled in standby sleep mode. +// If this bit is 1: The DFLL is not stopped in standby sleep mode. +// dfll48m_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// USB Clock Recovery Mode +// dfll48m_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 1 +#endif + +#if CONF_DFLL_USBCRM == 1 +#if CONF_DFLL_QLDIS == 1 +#warning QLDIS must be cleared to speed up the lock phase +#endif +#if CONF_DFLL_CCDIS == 0 +#warning CCDIS should be set to speed up the lock phase +#endif +#endif + +// Lose Lock After Wake +// Lose Lock After Wake +// dfll48m_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Stable DFLL Frequency +// If 0: FINE calibration tracks changes in output frequency. +// If 1: FINE calibration register value will be fixed after a fine lock. +// dfll48m_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// Open Loop Mode +// Closed Loop Mode +// Mode +// dfll48m_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE CONF_DFLL_CLOSED_LOOP_MODE +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 1 +#endif + +// Fine Maximum Step <0x0-0x3FF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 1 +#endif + +// DFLL Multiply Factor<0-65535> +// Set the DFLL Multiply Factor +// Default: 0 +// dfll48m_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll48m_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 1 +#endif + +// Coarse Value <0x0-0x3F> +// dfll48m_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0xa) +#endif + +// Fine Value <0x0-0x3FF> +// dfll48m_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x200) +#endif + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 +#define CONF_DEFAULT_CORASE \ + ((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos) + +#define CONF_DFLLVAL \ + SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \ + | SYSCTRL_DFLLVAL_FINE(512) + +#else +#define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE) + +#endif +// + +// +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_GCLK +#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +#if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K) +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val +#elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC) +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val +#else +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val +#endif + +// DPLL Control +// ON Demand +// Enable On Demand +// If this bit is 0: The DFLL is always on, if enabled. +// If this bit is 1: the DFLL will only be running when requested by a peripheral. +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The DFLL is disabled in standby sleep mode. +// If this bit is 1: The DFLL is not stopped in standby sleep mode. +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// DPLL Enable +// Indicates whether DPLL is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// Lock ByPass +// Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Clock Divider <0-2047> +// Clock Division Factor (Applicable if reference clock is XOSC) +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// DPLL LDRFRAC<0-15> +// Set the fractional part of the frequency multiplier. +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 13 +#endif + +// DPLL LDR <0-4095> +// Set the integer part of the frequency multiplier. +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 1463 +#endif + +// +// + +#define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val +#define CONF_DPLL_WUF 0 +#define CONF_DPLL_LPEN 0 +#define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val + +// <<< end of configuration section >>> + +#endif // HPL_SYSCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_systick_config.h b/atmel-samd/asf4/samd21/config/hpl_systick_config.h new file mode 100644 index 0000000000000..a7f2f36208fa7 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_tc_config.h b/atmel-samd/asf4/samd21/config/hpl_tc_config.h new file mode 100644 index 0000000000000..90e9b07357475 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_tc_config.h @@ -0,0 +1,181 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 1 +#endif + +// Basic settings + +// Prescaler +// No division +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 64 +// Divide by 256 +// Divide by 1024 +// This defines the prescaler value +// tc_prescaler +#ifndef CONF_TC3_PRESCALER +#define CONF_TC3_PRESCALER TC_CTRLA_PRESCALER_DIV8_Val +#endif + +// Period Value <0x00000000-0xFFFFFFFF> +// tc_per +#ifndef CONF_TC3_PER +#define CONF_TC3_PER 0x32 +#endif +// + +// PWM Waveform Output settings +// Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tc_arch_wave_per_val +#ifndef CONF_TC3_WAVE_PER_VAL +#define CONF_TC3_WAVE_PER_VAL 0x3e8 +#endif + +// Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tc_arch_wave_duty_val +#ifndef CONF_TC3_WAVE_DUTY_VAL +#define CONF_TC3_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC3_CC0 \ + ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) +#endif + +// + +// Advanced settings +// Mode +// Counter in 16-bit mode +// Counter in 32-bit mode +// These bits mode +// tc_arch_mode +#ifndef CONF_TC3_MODE +#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val +#endif +// + +// Advanced settings +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +// Run in standby +// Indicates whether the will continue running in standby sleep mode or not +// tc_arch_runstdby +#ifndef CONF_TC3_RUNSTDBY +#define CONF_TC3_RUNSTDBY 0 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC3_PRESCSYNC +#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_DIR 0 +//#define CONF_TC3_ONESHOT 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_INVEN0 0 +//#define CONF_TC3_INVEN1 0 +//#define CONF_TC3_CPTEN0 0 +//#define CONF_TC3_CPTEN1 0 + +// Debug Running Mode +// Indicates whether the Debug Running Mode is enabled or not +// tc_arch_dbgrun +#ifndef CONF_TC3_DBGRUN +#define CONF_TC3_DBGRUN 0 +#endif + +// + +// Event control +// timer_event_control +#ifndef CONF_TC3_EVENT_CONTROL_ENABLE +#define CONF_TC3_EVENT_CONTROL_ENABLE 0 +#endif + +// Overflow/Underflow Event Output +// Generates event for counter overflows/underflows +// tc_arch_ovfeo +#ifndef CONF_TC3_OVFEO +#define CONF_TC3_OVFEO 0 +#endif + +// TC Event Asynchronous input +// Enables Asynchronous input events to the TC +// tc_arch_tcei +#ifndef CONF_TC3_TCEI +#define CONF_TC3_TCEI 0 +#endif + +// TC Inverted Event Input Polarity +// Used to invert the asynchronous input event source +// tc_arch_tceinv +#ifndef CONF_TC3_TCINV +#define CONF_TC3_TCINV 0 +#endif + +// Event Action +// Defines the event action the TC will perform on an event +// Event action disabled +// Start, restart or retrigger TC on event +// Count on event +// Start TC on event +// Period captured in CC0, pulse width in CC1 +// Period captured in CC1, pulse width in CC0 +// tc_arch_evact +#ifndef CONF_TC3_EVACT +#define CONF_TC3_EVACT TC_EVCTRL_EVACT_OFF_Val +#endif + +// Match/Capture channel 0 Event +// Enables the generation of an event for every match or capture on channel 0 +// tc_arch_mceo0 +#ifndef CONF_TC3_MCEO0 +#define CONF_TC3_MCEO0 0 +#endif +// Match/Capture channel 1 Event +// Enables the generation of an event for every match or capture on channel 1 +// tc_arch_mceo1 +#ifndef CONF_TC3_MCEO1 +#define CONF_TC3_MCEO1 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_usb_config.h b/atmel-samd/asf4/samd21/config/hpl_usb_config.h new file mode 100644 index 0000000000000..73a9fea442158 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/hpl_usb_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// USB Device HAL Configuration + +// Max number of endpoints supported +// Limits the number of endpoints (described by EP address) can be used in app. +// 1 (EP0 only) +// 2 (EP0 + 1 endpoint) +// 3 (EP0 + 2 endpoints) +// 4 (EP0 + 3 endpoints) +// 5 (EP0 + 4 endpoints) +// 6 (EP0 + 5 endpoints) +// 7 (EP0 + 6 endpoints) +// 8 (EP0 + 7 endpoints) +// Max possible (by "Max Endpoint Number" config) +// usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 +#endif + +// + +// Max Endpoint Number supported +// Limits the max endpoint number. +// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// Reduce the value according to specific device design, to cut-off memory usage. +// 0 (only EP0) +// 1 (EP 0x81 or 0x01) +// 2 (EP 0x82 or 0x02) +// 3 (EP 0x83 or 0x03) +// 4 (EP 0x84 or 0x04) +// 5 (EP 0x85 or 0x05) +// 6 (EP 0x86 or 0x06) +// 7 (EP 0x87 or 0x07) +// Max possible (by HW) +// The number of physical endpoints - 1 +// usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 +#endif + +// USB Speed Limit +// Limits the working speed of the device. +// Full speed +// Low Speed +// usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// Cache buffer size for EP0 +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// Cache configuration EP1 +// Cache buffer size for EP1 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 64 +#endif + +// Cache buffer size for EP1 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 0 +#endif +// + +// Cache configuration EP2 +// Cache buffer size for EP2 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 64 +#endif + +// Cache buffer size for EP2 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// + +// Cache configuration EP3 +// Cache buffer size for EP3 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 64 +#endif + +// Cache buffer size for EP3 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// + +// Cache configuration EP4 +// Cache buffer size for EP4 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 64 +#endif + +// Cache buffer size for EP4 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// + +// Cache configuration EP5 +// Cache buffer size for EP5 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 64 +#endif + +// Cache buffer size for EP5 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// + +// Cache configuration EP6 +// Cache buffer size for EP6 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 64 +#endif + +// Cache buffer size for EP6 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// + +// Cache configuration EP7 +// Cache buffer size for EP7 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 64 +#endif + +// Cache buffer size for EP7 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/peripheral_clk_config.h b/atmel-samd/asf4/samd21/config/peripheral_clk_config.h new file mode 100644 index 0000000000000..f3bb927f9eb57 --- /dev/null +++ b/atmel-samd/asf4/samd21/config/peripheral_clk_config.h @@ -0,0 +1,369 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ADC Clock Source +// adc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for ADC. +#ifndef CONF_GCLK_ADC_SRC +#define CONF_GCLK_ADC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_ADC_FREQUENCY + * \brief ADC's Clock frequency + */ +#ifndef CONF_GCLK_ADC_FREQUENCY +#define CONF_GCLK_ADC_FREQUENCY 1000000 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000 +#endif + +// RTC Clock Source +// rtc_clk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1000000 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC3_SRC +#define CONF_GCLK_TC3_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC3_FREQUENCY + * \brief TC3's Clock frequency + */ +#ifndef CONF_GCLK_TC3_FREQUENCY +#define CONF_GCLK_TC3_FREQUENCY 1000000 +#endif + +// DAC Clock Source +// dac_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 1000000 +#endif + +// USB Clock Source +// usb_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 1000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/documentation/usb_device_composite.rst b/atmel-samd/asf4/samd21/documentation/usb_device_composite.rst new file mode 100644 index 0000000000000..1d6151cc2333f --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_device_composite.rst @@ -0,0 +1,32 @@ +==================== +USB Device Composite +==================== + +USB Device Composite is a part of the USB Device Stack library. It provides the support for +combining different USB classes into one USB device application. For more detailed features +or use cases introduction, user can refer to the related class documents. + + +Features +-------- +* Combination of different USB classes. + + +Applications +------------ + +* An USB device which is composed by CDC ACM, HID Keyboard,etc. + +Dependencies +------------ + +* USB Device Driver +* USB Device Stack Core +* USB Device CDC +* USB Device HID + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_device_core.rst b/atmel-samd/asf4/samd21/documentation/usb_device_core.rst new file mode 100644 index 0000000000000..fc70186258c2e --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_device_core.rst @@ -0,0 +1,41 @@ +=============== +USB Device Core +=============== + +USB Device Core is a part of the USB Device Stack library. It handles all the requests +during USB Enumeration process and helps upper class driver to be installed successfully +if only the descriptor configuration is correct. For more detailed description about Bus +Enumeration, user can refer to Chapter 9 (USB Device Framework) in Universal Serial Bus +Specification. + +Features +-------- +* Initialization/de-initialization +* Enabling/disabling USB device class components +* Data Transfer +* Attaching/detaching control +* Waking up by USB host +* Callbacks management on: + + * SOF event + * USB Device state change + * USB Device request handler + + +Applications +------------ + +N/A + +Dependencies +------------ + +* USB Device Driver +* USB Protocol Core + + +Limitations +----------- + +* It is recommended that at least one device class should run above the USB + device core. diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_cdc.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_cdc.rst new file mode 100644 index 0000000000000..3cf414b92a7a9 --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_protocol_cdc.rst @@ -0,0 +1,24 @@ +================ +USB CDC Protocol +================ + +USB CDC Protocol is a part of the USB Device Stack library. It provides basic +macro definitions and data structures which are compliant with CDC(Communications +Device Class) Specification version 1.2. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_core.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_core.rst new file mode 100644 index 0000000000000..4d5e01bbf392e --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_protocol_core.rst @@ -0,0 +1,40 @@ +================= +USB Protocol Core +================= + +USB Protocol Core is a part of the USB Device Stack library. It provides basic +macro definitions, data structures and API functions which are compliant with +USB specification version 2.0.0/2.0.1 for user. + +In addition, it provides interfaces of USB descriptor searching for the upper +layer to use, which is especially helpful in the USB enumeration process. + +Features +-------- +* Packaging USB device, configuration, interface, endpoint descriptors. +* Getting the descriptor length or type from an assigned USB descriptor. +* Getting VID, PID value from an assigned USB descriptor. +* Getting the total length of an USB configuration descriptor. +* Finding the next valid descriptor in a given USB descriptor. +* Finding an endpoint descriptor in a given USB descriptor. +* Finding a specific descriptor by an assigned descriptor type. +* Finding a configure descriptor by an assigned configure value. +* Finding a string descriptor by an assigned string index. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A + diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_hid.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_hid.rst new file mode 100644 index 0000000000000..613c22cec84cc --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_protocol_hid.rst @@ -0,0 +1,24 @@ +================ +USB HID Protocol +================ + +USB HID Protocol is a part of the USB Device Stack library. It provides basic +macro definitions and data structures which are compliant with HID(Human Interface +Device) Specification version 1.11. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_hub.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_hub.rst new file mode 100644 index 0000000000000..d60b0bbfd4268 --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_protocol_hub.rst @@ -0,0 +1,32 @@ +====================== +USB Protocol Hub Class +====================== + +USB Protocol Hub Class is a part of the USB Device Stack library. It provides +basic macro definitions, data structures and API functions which are compliant +with Hub part of USB specification version 2.0.0/2.0.1 for user. + +In addition, it provides interfaces of USB requests filling and input data +analyzing for the upper layer to use. + +Features +-------- +* Hub requests filling +* Hub change bitmap analyzing + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A + diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_msc.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_msc.rst new file mode 100644 index 0000000000000..6c7df54507dde --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_protocol_msc.rst @@ -0,0 +1,25 @@ +================ +USB MSC Protocol +================ + +USB MSC Protocol is a part of the USB Device Stack library. It provides basic +macro definitions and data structures which are compliant with Mass Storage +Control/Bulk/Interrupt (CBI) Specification 1.1 and Mass Storage UFI Command +Specification 1.0. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_vendor.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_vendor.rst new file mode 100644 index 0000000000000..e244675a67a59 --- /dev/null +++ b/atmel-samd/asf4/samd21/documentation/usb_protocol_vendor.rst @@ -0,0 +1,24 @@ +=================== +USB Vendor Protocol +=================== + +USB Vendor Protocol is a part of the USB Device Stack library. It provides basic +macro definitions which are compliant with Universal Serial Bus Specification +Revision 2.0. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd21/driver_init.c b/atmel-samd/asf4/samd21/driver_init.c new file mode 100644 index 0000000000000..806b89415e44e --- /dev/null +++ b/atmel-samd/asf4/samd21/driver_init.c @@ -0,0 +1,788 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include +#include +#include +#include +#include + +struct spi_m_sync_descriptor SPI_0; +struct timer_descriptor TIMER_0; + +struct adc_sync_descriptor ADC_0; + +struct flash_descriptor FLASH_0; + +struct i2c_m_sync_desc I2C_0; + +struct usart_sync_descriptor USART_0; + +struct pwm_descriptor PWM_0; + +struct dac_sync_descriptor DAC_0; + +void ADC_0_PORT_init(void) +{ +} + +void ADC_0_CLOCK_init(void) +{ + _pm_enable_bus_clock(PM_BUS_APBC, ADC); + _gclk_enable_channel(ADC_GCLK_ID, CONF_GCLK_ADC_SRC); +} + +void ADC_0_init(void) +{ + ADC_0_CLOCK_init(); + ADC_0_PORT_init(); + adc_sync_init(&ADC_0, ADC, (void *)NULL); +} + +void FLASH_0_CLOCK_init(void) +{ + + _pm_enable_bus_clock(PM_BUS_APBB, NVMCTRL); +} + +void FLASH_0_init(void) +{ + FLASH_0_CLOCK_init(); + flash_init(&FLASH_0, NVMCTRL); +} + +void SPI_0_PORT_init(void) +{ + + // Set pin direction to output + gpio_set_pin_direction(PA04, GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA04, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0); + + // Set pin direction to output + gpio_set_pin_direction(PA05, GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA05, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1); + + // Set pin direction to input + gpio_set_pin_direction(PA06, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA06, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA06, PINMUX_PA06D_SERCOM0_PAD2); +} + +void SPI_0_CLOCK_init(void) +{ + _pm_enable_bus_clock(PM_BUS_APBC, SERCOM0); + _gclk_enable_channel(SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC); +} + +void SPI_0_init(void) +{ + SPI_0_CLOCK_init(); + spi_m_sync_init(&SPI_0, SERCOM0); + SPI_0_PORT_init(); +} + +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_pull_mode(PA16, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA16, PINMUX_PA16C_SERCOM1_PAD0); + + gpio_set_pin_pull_mode(PA17, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA17, PINMUX_PA17C_SERCOM1_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + _pm_enable_bus_clock(PM_BUS_APBC, SERCOM1); + _gclk_enable_channel(SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC); + _gclk_enable_channel(SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM1); + I2C_0_PORT_init(); +} + +void USART_0_PORT_init(void) +{ + + gpio_set_pin_function(PA08, PINMUX_PA08D_SERCOM2_PAD0); + + gpio_set_pin_function(PA09, PINMUX_PA09D_SERCOM2_PAD1); +} + +void USART_0_CLOCK_init(void) +{ + _pm_enable_bus_clock(PM_BUS_APBC, SERCOM2); + _gclk_enable_channel(SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC); +} + +void USART_0_init(void) +{ + USART_0_CLOCK_init(); + usart_sync_init(&USART_0, SERCOM2, (void *)NULL); + USART_0_PORT_init(); +} + +void delay_driver_init(void) +{ + delay_init(SysTick); +} + +/** + * \brief Timer initialization function + * + * Enables Timer peripheral, clocks and initializes Timer driver + */ +static void TIMER_0_init(void) +{ + _pm_enable_bus_clock(PM_BUS_APBA, RTC); + _gclk_enable_channel(RTC_GCLK_ID, CONF_GCLK_RTC_SRC); + timer_init(&TIMER_0, RTC, _rtc_get_timer()); +} + +void PWM_0_PORT_init(void) +{ +} + +void PWM_0_CLOCK_init(void) +{ + _pm_enable_bus_clock(PM_BUS_APBC, TC3); + _gclk_enable_channel(TC3_GCLK_ID, CONF_GCLK_TC3_SRC); +} + +void PWM_0_init(void) +{ + PWM_0_CLOCK_init(); + PWM_0_PORT_init(); + pwm_init(&PWM_0, TC3, _tc_get_pwm()); +} + +void DAC_0_PORT_init(void) +{ +} + +void DAC_0_CLOCK_init(void) +{ + + _pm_enable_bus_clock(PM_BUS_APBC, DAC); + _gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC); +} + +void DAC_0_init(void) +{ + DAC_0_CLOCK_init(); + dac_sync_init(&DAC_0, DAC); + DAC_0_PORT_init(); +} + +void USB_0_PORT_init(void) +{ + + gpio_set_pin_direction(PA24, + // Pin direction + // pad_direction + // Off + // In + // Out + GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA24, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_pull_mode(PA24, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA24, + // Pin function + // pad_function + // Auto : use driver pinmux if signal is imported by driver, else turn off function + // Auto + // Off + // A + // B + // C + // D + // E + // F + // G + // H + PINMUX_PA24G_USB_DM); + + gpio_set_pin_direction(PA25, + // Pin direction + // pad_direction + // Off + // In + // Out + GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA25, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_pull_mode(PA25, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA25, + // Pin function + // pad_function + // Auto : use driver pinmux if signal is imported by driver, else turn off function + // Auto + // Off + // A + // B + // C + // D + // E + // F + // G + // H + PINMUX_PA25G_USB_DP); +} + +/* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock + * for low speed and full speed operation. */ +#if (CONF_GCLK_USB_FREQUENCY > (48000000 + 48000000 / 400)) || (CONF_GCLK_USB_FREQUENCY < (48000000 - 48000000 / 400)) +#warning USB clock should be 48MHz ~ 0.25% clock, check your configuration! +#endif + +void USB_0_CLOCK_init(void) +{ + + _pm_enable_bus_clock(PM_BUS_APBB, USB); + _pm_enable_bus_clock(PM_BUS_AHB, USB); + _gclk_enable_channel(USB_GCLK_ID, CONF_GCLK_USB_SRC); +} + +void USB_0_init(void) +{ + USB_0_CLOCK_init(); + usb_d_init(); + USB_0_PORT_init(); +} + +void system_init(void) +{ + init_mcu(); + + // GPIO on PA00 + + // Set pin direction to input + gpio_set_pin_direction(PA00, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA00, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA00, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA01 + + // Set pin direction to input + gpio_set_pin_direction(PA01, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA01, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA01, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA02 + + // Set pin direction to input + gpio_set_pin_direction(PA02, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA02, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA02, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA03 + + // Set pin direction to input + gpio_set_pin_direction(PA03, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA03, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA03, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA07 + + // Set pin direction to input + gpio_set_pin_direction(PA07, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA07, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA07, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA10 + + // Set pin direction to input + gpio_set_pin_direction(PA10, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA10, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA10, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA11 + + // Set pin direction to input + gpio_set_pin_direction(PA11, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA11, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA11, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA12 + + // Set pin direction to input + gpio_set_pin_direction(PA12, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA12, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA12, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA13 + + // Set pin direction to input + gpio_set_pin_direction(PA13, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA13, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA13, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA14 + + // Set pin direction to input + gpio_set_pin_direction(PA14, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA14, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA14, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA15 + + // Set pin direction to input + gpio_set_pin_direction(PA15, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA15, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA15, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA18 + + // Set pin direction to input + gpio_set_pin_direction(PA18, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA18, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA18, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA19 + + // Set pin direction to input + gpio_set_pin_direction(PA19, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA19, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA19, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA20 + + // Set pin direction to input + gpio_set_pin_direction(PA20, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA20, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA20, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA21 + + // Set pin direction to input + gpio_set_pin_direction(PA21, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA21, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA21, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA22 + + // Set pin direction to input + gpio_set_pin_direction(PA22, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA22, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA22, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA23 + + // Set pin direction to input + gpio_set_pin_direction(PA23, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA23, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA23, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA27 + + // Set pin direction to input + gpio_set_pin_direction(PA27, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA27, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA27, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA28 + + // Set pin direction to input + gpio_set_pin_direction(PA28, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA28, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA28, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA30 + + // Set pin direction to input + // gpio_set_pin_direction(PA30, GPIO_DIRECTION_IN); + // + // gpio_set_pin_pull_mode(PA30, + // // Pull configuration + // // pad_pull_config + // // Off + // // Pull-up + // // Pull-down + // GPIO_PULL_OFF); + // + // gpio_set_pin_function(PA30, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PA31 + + // Set pin direction to input + // gpio_set_pin_direction(PA31, GPIO_DIRECTION_IN); + // + // gpio_set_pin_pull_mode(PA31, + // // Pull configuration + // // pad_pull_config + // // Off + // // Pull-up + // // Pull-down + // GPIO_PULL_OFF); + // + // gpio_set_pin_function(PA31, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB02 + + // Set pin direction to input + gpio_set_pin_direction(PB02, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB02, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB02, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB03 + + // Set pin direction to input + gpio_set_pin_direction(PB03, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB03, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB03, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB08 + + // Set pin direction to input + gpio_set_pin_direction(PB08, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB08, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB08, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB09 + + // Set pin direction to input + gpio_set_pin_direction(PB09, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB09, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB09, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB10 + + // Set pin direction to input + gpio_set_pin_direction(PB10, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB10, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB10, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB11 + + // Set pin direction to input + gpio_set_pin_direction(PB11, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB11, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB11, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB22 + + // Set pin direction to input + gpio_set_pin_direction(PB22, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB22, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB22, GPIO_PIN_FUNCTION_OFF); + + // GPIO on PB23 + + // Set pin direction to input + gpio_set_pin_direction(PB23, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PB23, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PB23, GPIO_PIN_FUNCTION_OFF); + + ADC_0_init(); + + FLASH_0_init(); + + SPI_0_init(); + + I2C_0_init(); + + USART_0_init(); + + delay_driver_init(); + + TIMER_0_init(); + + PWM_0_init(); + + DAC_0_init(); + + USB_0_init(); +} diff --git a/atmel-samd/asf4/samd21/driver_init.h b/atmel-samd/asf4/samd21/driver_init.h new file mode 100644 index 0000000000000..da65d4ff0eacb --- /dev/null +++ b/atmel-samd/asf4/samd21/driver_init.h @@ -0,0 +1,99 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include + +#include + +#include +#include +#include +#include + +#include + +#include "hal_usb_device.h" + +extern struct adc_sync_descriptor ADC_0; + +extern struct flash_descriptor FLASH_0; +extern struct spi_m_sync_descriptor SPI_0; + +extern struct i2c_m_sync_desc I2C_0; + +extern struct usart_sync_descriptor USART_0; + +extern struct timer_descriptor TIMER_0; + +extern struct pwm_descriptor PWM_0; + +extern struct dac_sync_descriptor DAC_0; + +void ADC_0_PORT_init(void); +void ADC_0_CLOCK_init(void); +void ADC_0_init(void); + +void FLASH_0_init(void); +void FLASH_0_CLOCK_init(void); + +void SPI_0_PORT_init(void); +void SPI_0_CLOCK_init(void); +void SPI_0_init(void); + +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + +void USART_0_PORT_init(void); +void USART_0_CLOCK_init(void); +void USART_0_init(void); + +void delay_driver_init(void); + +void PWM_0_PORT_init(void); +void PWM_0_CLOCK_init(void); +void PWM_0_init(void); + +void DAC_0_PORT_init(void); +void DAC_0_CLOCK_init(void); +void DAC_0_init(void); + +void USB_0_CLOCK_init(void); +void USB_0_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/atmel-samd/asf4/samd21/examples/driver_examples.c b/atmel-samd/asf4/samd21/examples/driver_examples.c new file mode 100644 index 0000000000000..9fb93dc3e6fba --- /dev/null +++ b/atmel-samd/asf4/samd21/examples/driver_examples.c @@ -0,0 +1,140 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using ADC_0 to generate waveform. + */ +void ADC_0_example(void) +{ + uint8_t buffer[2]; + + adc_sync_enable_channel(&ADC_0, 0); + + while (1) { + adc_sync_read_channel(&ADC_0, 0, buffer, 2); + } +} + +static uint8_t src_data[128]; +static uint8_t chk_data[128]; +/** + * Example of using FLASH_0 to read and write buffer. + */ +void FLASH_0_example(void) +{ + uint32_t page_size; + uint16_t i; + + /* Init source data */ + page_size = flash_get_page_size(&FLASH_0); + + for (i = 0; i < page_size; i++) { + src_data[i] = i; + } + + /* Write data to flash */ + flash_write(&FLASH_0, 0x3200, src_data, page_size); + + /* Read data from flash */ + flash_read(&FLASH_0, 0x3200, chk_data, page_size); +} + +/** + * Example of using SPI_0 to write "Hello World" using the IO abstraction. + */ +static uint8_t example_SPI_0[12] = "Hello World!"; + +void SPI_0_example(void) +{ + struct io_descriptor *io; + spi_m_sync_get_io_descriptor(&SPI_0, &io); + + spi_m_sync_enable(&SPI_0); + io_write(io, example_SPI_0, 12); +} + +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + +/** + * Example of using USART_0 to write "Hello World" using the IO abstraction. + */ +void USART_0_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&USART_0, &io); + usart_sync_enable(&USART_0); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +void delay_example(void) +{ + delay_ms(5000); +} + +static struct timer_task TIMER_0_task1, TIMER_0_task2; +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + TIMER_0_task2.interval = 200; + TIMER_0_task2.cb = TIMER_0_task2_cb; + TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_add_task(&TIMER_0, &TIMER_0_task2); + timer_start(&TIMER_0); +} + +/** + * Example of using PWM_0. + */ +void PWM_0_example(void) +{ + pwm_set_parameters(&PWM_0, 10000, 5000); + pwm_enable(&PWM_0); +} + +/** + * Example of using DAC_0 to generate waveform. + */ +void DAC_0_example(void) +{ + uint16_t i = 0; + + dac_sync_enable_channel(&DAC_0, 0); + + for (;;) { + dac_sync_write(&DAC_0, 0, &i, 1); + i = (i + 1) % 1024; + } +} diff --git a/atmel-samd/asf4/samd21/examples/driver_examples.h b/atmel-samd/asf4/samd21/examples/driver_examples.h new file mode 100644 index 0000000000000..7a4353b982f26 --- /dev/null +++ b/atmel-samd/asf4/samd21/examples/driver_examples.h @@ -0,0 +1,32 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void ADC_0_example(void); + +void FLASH_0_example(void); + +void I2C_0_example(void); + +void USART_0_example(void); + +void delay_example(void); + +void PWM_0_example(void); + +void DAC_0_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/atmel-samd/asf4/samd21/gcc/Makefile b/atmel-samd/asf4/samd21/gcc/Makefile new file mode 100644 index 0000000000000..8e31a0231a68a --- /dev/null +++ b/atmel-samd/asf4/samd21/gcc/Makefile @@ -0,0 +1,282 @@ + +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif +endif + +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/adc \ +hal/src \ +examples \ +hpl/systick \ +hpl/tc \ +usb \ +hpl/dmac \ +usb/class/cdc/device \ +hal/utils/src \ +hpl/rtc \ +usb/class/hid/device \ +hpl/usb \ +samd21a/gcc/gcc \ +hpl/pm \ +hpl/sysctrl \ +hpl/gclk \ +usb/device \ +hpl/dac \ +samd21a/gcc \ +hpl/sercom \ +hpl/nvmctrl \ +hpl/core + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hpl/systick/hpl_systick.o \ +samd21a/gcc/gcc/startup_samd21.o \ +usb/usb_protocol.o \ +usb/class/hid/device/hiddf_generic.o \ +usb/class/cdc/device/cdcdf_acm.o \ +hal/utils/src/utils_syscalls.o \ +hpl/nvmctrl/hpl_nvmctrl.o \ +hal/src/hal_spi_m_sync.o \ +hal/src/hal_timer.o \ +hal/src/hal_pwm.o \ +hpl/usb/hpl_usb.o \ +hal/src/hal_i2c_m_sync.o \ +hal/src/hal_delay.o \ +hpl/sysctrl/hpl_sysctrl.o \ +hpl/core/hpl_init.o \ +hal/utils/src/utils_list.o \ +hpl/core/hpl_core_m0plus_base.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/pm/hpl_pm.o \ +usb/class/hid/device/hiddf_keyboard.o \ +hal/src/hal_usart_sync.o \ +hpl/dac/hpl_dac.o \ +hpl/gclk/hpl_gclk.o \ +hal/src/hal_flash.o \ +hal/src/hal_init.o \ +hal/src/hal_usb_device.o \ +main.o \ +samd21a/gcc/system_samd21.o \ +hpl/rtc/hpl_rtc.o \ +examples/driver_examples.o \ +driver_init.o \ +hal/src/hal_adc_sync.o \ +hal/src/hal_dac_sync.o \ +hpl/sercom/hpl_sercom.o \ +hal/src/hal_gpio.o \ +usb/class/hid/device/hiddf_mouse.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +usb_start.o \ +atmel_start.o \ +usb/device/usbdc.o \ +hpl/tc/hpl_tc.o \ +hal/src/hal_atomic.o \ +hpl/adc/hpl_adc.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hpl/systick/hpl_systick.o" \ +"samd21a/gcc/gcc/startup_samd21.o" \ +"usb/usb_protocol.o" \ +"usb/class/hid/device/hiddf_generic.o" \ +"usb/class/cdc/device/cdcdf_acm.o" \ +"hal/utils/src/utils_syscalls.o" \ +"hpl/nvmctrl/hpl_nvmctrl.o" \ +"hal/src/hal_spi_m_sync.o" \ +"hal/src/hal_timer.o" \ +"hal/src/hal_pwm.o" \ +"hpl/usb/hpl_usb.o" \ +"hal/src/hal_i2c_m_sync.o" \ +"hal/src/hal_delay.o" \ +"hpl/sysctrl/hpl_sysctrl.o" \ +"hpl/core/hpl_init.o" \ +"hal/utils/src/utils_list.o" \ +"hpl/core/hpl_core_m0plus_base.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/pm/hpl_pm.o" \ +"usb/class/hid/device/hiddf_keyboard.o" \ +"hal/src/hal_usart_sync.o" \ +"hpl/dac/hpl_dac.o" \ +"hpl/gclk/hpl_gclk.o" \ +"hal/src/hal_flash.o" \ +"hal/src/hal_init.o" \ +"hal/src/hal_usb_device.o" \ +"main.o" \ +"samd21a/gcc/system_samd21.o" \ +"hpl/rtc/hpl_rtc.o" \ +"examples/driver_examples.o" \ +"driver_init.o" \ +"hal/src/hal_adc_sync.o" \ +"hal/src/hal_dac_sync.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hal/src/hal_gpio.o" \ +"usb/class/hid/device/hiddf_mouse.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"usb_start.o" \ +"atmel_start.o" \ +"usb/device/usbdc.o" \ +"hpl/tc/hpl_tc.o" \ +"hal/src/hal_atomic.o" \ +"hpl/adc/hpl_adc.o" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"usb/usb_protocol.d" \ +"samd21a/gcc/gcc/startup_samd21.d" \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"hpl/systick/hpl_systick.d" \ +"usb/class/hid/device/hiddf_generic.d" \ +"hal/utils/src/utils_syscalls.d" \ +"usb/class/cdc/device/cdcdf_acm.d" \ +"usb/class/hid/device/hiddf_mouse.d" \ +"hal/src/hal_i2c_m_sync.d" \ +"hpl/usb/hpl_usb.d" \ +"hpl/nvmctrl/hpl_nvmctrl.d" \ +"hal/src/hal_pwm.d" \ +"hal/src/hal_timer.d" \ +"hal/src/hal_spi_m_sync.d" \ +"hpl/core/hpl_core_m0plus_base.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/sysctrl/hpl_sysctrl.d" \ +"hal/src/hal_flash.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hal/src/hal_usb_device.d" \ +"usb_start.d" \ +"hal/src/hal_init.d" \ +"hal/src/hal_usart_sync.d" \ +"usb/class/hid/device/hiddf_keyboard.d" \ +"hpl/dac/hpl_dac.d" \ +"driver_init.d" \ +"hal/src/hal_adc_sync.d" \ +"samd21a/gcc/system_samd21.d" \ +"main.d" \ +"examples/driver_examples.d" \ +"hpl/rtc/hpl_rtc.d" \ +"hal/src/hal_sleep.d" \ +"hpl/sercom/hpl_sercom.d" \ +"hal/src/hal_dac_sync.d" \ +"hal/src/hal_gpio.d" \ +"hal/src/hal_atomic.d" \ +"hpl/tc/hpl_tc.d" \ +"usb/device/usbdc.d" \ +"hpl/pm/hpl_pm.d" \ +"hpl/adc/hpl_adc.d" \ +"atmel_start.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARM/GNU Linker + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ +-Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m0plus \ + \ + \ +-T"../samd21a/gcc/gcc/samd21g18a_flash.ld" \ +-L"../samd21a/gcc/gcc" + @echo Finished building target: $@ + + "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin" + "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \ + "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex" + "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \ + .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \ + "$(OUTPUT_FILE_NAME).eep" || exit 0 + "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss" + "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf" + +# Compiler targets + + +%.o: %.c + @echo Building file: $< + @echo ARM/GNU C Compiler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAMD21G18A__ -mcpu=cortex-m0plus \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARM/GNU Assembler + $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAMD21G18A__ -mcpu=cortex-m0plus \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARM/GNU Preprocessing Assembler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAMD21G18A__ -mcpu=cortex-m0plus \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ + $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ + $(OUTPUT_FILE_NAME).srec diff --git a/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld b/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld new file mode 100644 index 0000000000000..2c94a53bafe4e --- /dev/null +++ b/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld b/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld new file mode 100644 index 0000000000000..f0462a22da82d --- /dev/null +++ b/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld @@ -0,0 +1,141 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c b/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c new file mode 100644 index 0000000000000..ddc0580d728db --- /dev/null +++ b/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c @@ -0,0 +1,265 @@ +/** + * \file + * + * \brief gcc starttup file for SAMD21 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NMI_Handler(void) __attribute__((weak, alias("Guilty_Handler"))); +void HardFault_Handler(void) __attribute__((weak, alias("Guilty_Handler"))); +void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SYSCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void EIC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void NVMCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_USB +void USB_Handler(void) __attribute__((weak, alias("Guilty_Handler"))); +#endif +void EVSYS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TCC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TCC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_TC6 +void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_ADC +void ADC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__((section(".vectors"), used)) const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void *)(&_estack), + + .pfnReset_Handler = (void *)Reset_Handler, + .pfnNMI_Handler = (void *)NMI_Handler, + .pfnHardFault_Handler = (void *)HardFault_Handler, + .pvReservedM12 = (void *)(0UL), /* Reserved */ + .pvReservedM11 = (void *)(0UL), /* Reserved */ + .pvReservedM10 = (void *)(0UL), /* Reserved */ + .pvReservedM9 = (void *)(0UL), /* Reserved */ + .pvReservedM8 = (void *)(0UL), /* Reserved */ + .pvReservedM7 = (void *)(0UL), /* Reserved */ + .pvReservedM6 = (void *)(0UL), /* Reserved */ + .pfnSVC_Handler = (void *)SVC_Handler, + .pvReservedM4 = (void *)(0UL), /* Reserved */ + .pvReservedM3 = (void *)(0UL), /* Reserved */ + .pfnPendSV_Handler = (void *)PendSV_Handler, + .pfnSysTick_Handler = (void *)SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ + .pfnSYSCTRL_Handler = (void *)SYSCTRL_Handler, /* 1 System Control */ + .pfnWDT_Handler = (void *)WDT_Handler, /* 2 Watchdog Timer */ + .pfnRTC_Handler = (void *)RTC_Handler, /* 3 Real-Time Counter */ + .pfnEIC_Handler = (void *)EIC_Handler, /* 4 External Interrupt Controller */ + .pfnNVMCTRL_Handler = (void *)NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void *)DMAC_Handler, /* 6 Direct Memory Access Controller */ +#ifdef ID_USB + .pfnUSB_Handler = (void *)USB_Handler, /* 7 Universal Serial Bus */ +#else + .pvReserved7 = (void *)(0UL), /* 7 Reserved */ +#endif + .pfnEVSYS_Handler = (void *)EVSYS_Handler, /* 8 Event System Interface */ + .pfnSERCOM0_Handler = (void *)SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void *)SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void *)SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + .pfnSERCOM3_Handler = (void *)SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void *)SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ +#else + .pvReserved13 = (void *)(0UL), /* 13 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void *)SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ +#else + .pvReserved14 = (void *)(0UL), /* 14 Reserved */ +#endif + .pfnTCC0_Handler = (void *)TCC0_Handler, /* 15 Timer Counter Control 0 */ + .pfnTCC1_Handler = (void *)TCC1_Handler, /* 16 Timer Counter Control 1 */ + .pfnTCC2_Handler = (void *)TCC2_Handler, /* 17 Timer Counter Control 2 */ + .pfnTC3_Handler = (void *)TC3_Handler, /* 18 Basic Timer Counter 0 */ + .pfnTC4_Handler = (void *)TC4_Handler, /* 19 Basic Timer Counter 1 */ + .pfnTC5_Handler = (void *)TC5_Handler, /* 20 Basic Timer Counter 2 */ +#ifdef ID_TC6 + .pfnTC6_Handler = (void *)TC6_Handler, /* 21 Basic Timer Counter 3 */ +#else + .pvReserved21 = (void *)(0UL), /* 21 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void *)TC7_Handler, /* 22 Basic Timer Counter 4 */ +#else + .pvReserved22 = (void *)(0UL), /* 22 Reserved */ +#endif +#ifdef ID_ADC + .pfnADC_Handler = (void *)ADC_Handler, /* 23 Analog Digital Converter */ +#else + .pvReserved23 = (void *)(0UL), /* 23 Reserved */ +#endif +#ifdef ID_AC + .pfnAC_Handler = (void *)AC_Handler, /* 24 Analog Comparators */ +#else + .pvReserved24 = (void *)(0UL), /* 24 Reserved */ +#endif +#ifdef ID_DAC + .pfnDAC_Handler = (void *)DAC_Handler, /* 25 Digital Analog Converter */ +#else + .pvReserved25 = (void *)(0UL), /* 25 Reserved */ +#endif +#ifdef ID_PTC + .pfnPTC_Handler = (void *)PTC_Handler, /* 26 Peripheral Touch Controller */ +#else + .pvReserved26 = (void *)(0UL), /* 26 Reserved */ +#endif + .pfnI2S_Handler = (void *)I2S_Handler, /* 27 Inter-IC Sound Interface */ + .pvReserved28 = (void *)(0UL) /* 28 Reserved */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *)&_sfixed; + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Change default QOS values to have the best performance and correct USB behaviour */ + SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; +#if defined(ID_USB) + USB->DEVICE.QOSCTRL.bit.CQOS = 2; + USB->DEVICE.QOSCTRL.bit.DQOS = 2; +#endif + DMAC->QOSCTRL.bit.DQOS = 2; + DMAC->QOSCTRL.bit.FQOS = 2; + DMAC->QOSCTRL.bit.WRBQOS = 2; + + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; + + /* Initialize the C library */ + // __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1) + ; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +__attribute__((used)) void Dummy_Handler(void) +{ + while (1) { + asm(""); + } +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Guilty_Handler(void) +{ + while (1) { + asm(""); + } +} diff --git a/atmel-samd/asf4/samd21/gcc/system_samd21.c b/atmel-samd/asf4/samd21/gcc/system_samd21.c new file mode 100644 index 0000000000000..274ecccb83ef6 --- /dev/null +++ b/atmel-samd/asf4/samd21/gcc/system_samd21.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (1000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/atmel-samd/asf4/samd21/hal/documentation/adc_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/adc_sync.rst new file mode 100644 index 0000000000000..d189565ad8c73 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/adc_sync.rst @@ -0,0 +1,74 @@ +====================== +ADC Synchronous driver +====================== + +An ADC (Analog-to-Digital Converter) converts analog signals to digital values. +A reference signal with a known voltage level is quantified into equally +sized chunks, each representing a digital value from 0 to the highest number +possible with the bit resolution supported by the ADC. The input voltage +measured by the ADC is compared against these chunks and the chunk with the +closest voltage level defines the digital value that can be used to represent +the analog input voltage level. + +Usually an ADC can operate in either differential or single-ended mode. +In differential mode two signals (V+ and V-) are compared against each other +and the resulting digital value represents the relative voltage level between +V+ and V-. This means that if the input voltage level on V+ is lower than on +V- the digital value is negative, which also means that in differential +mode one bit is lost to the sign. In single-ended mode only V+ is compared +against the reference voltage, and the resulting digital value can only be +positive, but the full bit-range of the ADC can be used. + +Usually multiple resolutions are supported by the ADC, lower resolution can +reduce the conversion time, but lose accuracy. + +Some ADCs has a gain stage on the input lines which can be used to increase the +dynamic range. The default gain value is usually x1, which means that the +conversion range is from 0V to the reference voltage. +Applications can change the gain stage, to increase or reduce the conversion +range. + +The window mode allows the conversion result to be compared to a set of +predefined threshold values. Applications can use callback function to monitor +if the conversion result exceeds predefined threshold value. + +Usually multiple reference voltages are supported by the ADC, both internal and +external with difference voltage levels. The reference voltage have an impact +on the accuracy, and should be selected to cover the full range of the analog +input signal and never less than the expected maximum input voltage. + +There are two conversion modes supported by ADC, single shot and free running. +In single shot mode the ADC only make one conversion when triggered by the +application, in free running mode it continues to make conversion from it +is triggered until it is stopped by the application. When window monitoring, +the ADC should be set to free running mode. + +Features +-------- +* Initialization and de-initialization +* Support multiple Conversion Mode, Single or Free run +* Start ADC Conversion +* Read Conversion Result + +Applications +------------ +* Measurement of internal sensor. E.g., MCU internal temperature sensor value. +* Measurement of external sensor. E.g., Temperature, humidity sensor value. +* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave. + +Dependencies +------------ +* ADC hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/atmel-samd/asf4/samd21/hal/documentation/dac_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/dac_sync.rst new file mode 100644 index 0000000000000..b3f3229290b5f --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/dac_sync.rst @@ -0,0 +1,41 @@ +====================== +DAC Synchronous driver +====================== + +A DAC (Digital-to-Analog Converter) converts digital value to an analog voltage. +The digital value from 0 to the highest represent the output voltage value. +The digital highest value possible with the bit resolution supported by the +DAC. For example a 10 bit resolution DAC hardware, the highest value is 1024. +The highest output voltage possible with the reference voltage. + +The driver can convert a serials digital value. The pre-defined data should +be an data array. Application can invoke dac_sync_write to start the conversation. + +Features +-------- +* Initialization and de-initialization +* Enabling and disabling +* Support for DACs with channels +* Writing buffers with multiple samples to DAC + +Applications +------------ +* Generate audio signals by connecting the DAC output to a speaker +* Generate a reference voltage + +Dependencies +------------ +* DAC hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/atmel-samd/asf4/samd21/hal/documentation/flash.rst b/atmel-samd/asf4/samd21/hal/documentation/flash.rst new file mode 100644 index 0000000000000..fcc86e63f8fd6 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/flash.rst @@ -0,0 +1,52 @@ +The Flash Driver +================ + +Flash is a re-programmable memory that retains program and data +storage even with power off. + +User can write or read several bytes from any valid address in a flash. + +As to the erase/lock/unlock command, the input parameter of address should +be a bytes address aligned with the page start, otherwise, the command will fail +to be executed. At the meantime, the number of pages that can be locked or unlocked +at once depends on region size of the flash. User can get the real number +from the function return value which could be different for the different devices. + +Features +-------- + +* Initialization/de-initialization +* Writing/Reading bytes +* Locking/Unlocking/Erasing pages +* Notifications about errors or being ready for a new command + +Applications +------------ + +* Mini disk which can retain program and data storage +* Boot loader +* Non volatile storage + +Dependencies +------------ + +The peripheral which controls a re-programmable flash memory. + +Concurrency +----------- + +N/A + +Limitations +----------- + +User should pay attention to set a proper stack size in their application, +since the driver manages a temporary buffer in stack to cache unchanged data +when calling flash write and erase function. +Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21, +write operation erazes row content before each write. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/atmel-samd/asf4/samd21/hal/documentation/i2c_master_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/i2c_master_sync.rst new file mode 100644 index 0000000000000..77b4f6e9c4f29 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/i2c_master_sync.rst @@ -0,0 +1,87 @@ +============================= +I2C Master synchronous driver +============================= + +I2C (Inter-Integrated Circuit) is a two wire serial interface usually used +for on-board low-speed bi-directional communication between controllers and +peripherals. The master device is responsible for initiating and controlling +all transfers on the I2C bus. Only one master device can be active on the I2C +bus at the time, but the master role can be transferred between devices on the +same I2C bus. I2C uses only two bidirectional open-drain lines, usually +designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up +resistors. + +The stop condition is automatically controlled by the driver if the I/O write and +read functions are used, but can be manually controlled by using the +i2c_m_sync_transfer function. + +Often a master accesses different information in the slave by accessing +different registers in the slave. This is done by first sending a message to +the target slave containing the register address, followed by a repeated start +condition (no stop condition between) ending with transferring register data. +This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read +function, but limited to 8-bit register addresses. + +I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in +Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to +stick within the SCL clock frequency range supported by the selected mode. +The requested SCL clock frequency is not validated by the +i2c_m_sync_set_baudrate function against the selected I2C mode. + +Features +-------- + + * I2C Master support + * Initialization and de-initialization + * Enabling and disabling + * Run-time bus speed configuration + * Write and read I2C messages + * Slave register access functions (limited to 8-bit address) + * Manual or automatic stop condition generation + * 10- and 7- bit addressing + * I2C Modes supported + +----------------------+-------------------+ + |* Standard/Fast mode | (SCL: 1 - 400kHz) | + +----------------------+-------------------+ + |* Fastmode+ | (SCL: 1 - 1000kHz)| + +----------------------+-------------------+ + |* Highspeed mode | (SCL: 1 - 3400kHz)| + +----------------------+-------------------+ + +Applications +------------ + +* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals +* Data communication between micro controllers +* Controlling displays + +Dependencies +------------ + +* I2C Master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +General +^^^^^^^ + + * System Managmenet Bus (SMBus) not supported. + * Power Management Bus (PMBus) not supported. + +Clock considerations +^^^^^^^^^^^^^^^^^^^^ + +The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. + +Known issues and workarounds +---------------------------- + +N/A + + diff --git a/atmel-samd/asf4/samd21/hal/documentation/pwm.rst b/atmel-samd/asf4/samd21/hal/documentation/pwm.rst new file mode 100644 index 0000000000000..71785c634c13d --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/pwm.rst @@ -0,0 +1,53 @@ +The PWM Driver(bare-bone) +========================= + +Pulse-width modulation (PWM) is used to create an analog behavior +digitally by controlling the amount of power transferred to the +connected peripheral. This is achieved by controlling the high period +(duty-cycle) of a periodic signal. + +User can change the period or duty cycle whenever PWM is running. The +function pwm_set_parameters is used to configure these two parameters. +Note these are raw register values and the parameter duty_cycle means +the period of first half during one cycle, which should be not beyond +total period value. + +In addition, user can also get multi PWM channels output from different +peripherals at the same time, which is implemented more flexible by the +function pointers. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Run-time control of PWM duty-cycle and period +* Notifications about errors and one PWM cycle is done + +Applications +------------ + +Motor control, ballast, LED, H-bridge, power converters, and +other types of power control applications. + +Dependencies +------------ + +The peripheral which can perform waveform generation like frequency +generation and pulse-width modulation, such as Timer/Counter. + +Concurrency +----------- + +N/A + +Limitations +----------- + +The current driver doesn't support the features like recoverable, +non-recoverable faults, dithering, dead-time insertion. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/atmel-samd/asf4/samd21/hal/documentation/spi_master_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/spi_master_sync.rst new file mode 100644 index 0000000000000..4fbe45e29c3db --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/spi_master_sync.rst @@ -0,0 +1,51 @@ +The SPI Master Synchronous Driver +================================= + +The serial peripheral interface (SPI) is a synchronous serial communication +interface. + +SPI devices communicate in full duplex mode using a master-slave +architecture with a single master. The master device originates the frame for +reading and writing. Multiple slave devices are supported through selection +with individual slave select (SS) lines. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * SPI mode + * Character size + * Data order +* Data transfer: transmission, reception and full-duplex + +Applications +------------ + +Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, +LCD controller, etc. + +Dependencies +------------ + +SPI master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +The slave select (SS) is not automatically inserted during read/write/transfer, +user must use I/O to control the devices' SS. + +Known issues and workarounds +---------------------------- + +N/A + diff --git a/atmel-samd/asf4/samd21/hal/documentation/timer.rst b/atmel-samd/asf4/samd21/hal/documentation/timer.rst new file mode 100644 index 0000000000000..c5ca63d127957 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/timer.rst @@ -0,0 +1,52 @@ +============================ +The Timer driver (bare-bone) +============================ + +The Timer driver provides means for delayed and periodical function invocation. + +A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has +been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a +configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically +changes execution delays and periods for all tasks in the timers task queue. + +A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue +and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on +the period set in the task configuration. +In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to +reuse the memory of expired task in the callback. + +Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. + +Features +-------- +* Initialization and de-initialization +* Starting and stopping +* Timer tasks - periodical invocation of functions +* Changing and obtaining of the period of a timer + +Applications +------------ +* Delayed and periodical function execution for middle-ware stacks and applications. + +Dependencies +------------ +* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. + +Concurrency +----------- +The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during +the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed +until the task adding or removing is complete. + +The task queue is not protected from the access by interrupts not used by the driver. Due to this +it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes +the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. + +Limitations +----------- +* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. +* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. + +Knows issues and workarounds +---------------------------- +Not applicable diff --git a/atmel-samd/asf4/samd21/hal/documentation/usart_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/usart_sync.rst new file mode 100644 index 0000000000000..73f76b749d1d9 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. +And the SCK pin can't be set directly. Application can use a GCLK output PIN +to generate SCK. For example to communicate with a SMARTCARD with ISO7816 +(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be +config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/atmel-samd/asf4/samd21/hal/documentation/usb_device_async.rst b/atmel-samd/asf4/samd21/hal/documentation/usb_device_async.rst new file mode 100644 index 0000000000000..647eec071bebe --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/documentation/usb_device_async.rst @@ -0,0 +1,195 @@ +The USB Device Asynchronous Driver +================================== + +Universal Serial Bus (USB) is an industry standard that defines the cables, +connectors and communication protocols used in a bus for connection, +communication, and power supply between computers and electronic devices. + +The USB device driver provides necessary APIs to support USB Device states and +USB data flow. So that the USB Device enumeration, class and vendor support can +be implemented base on it. The driver is asynchronous, which means that all USB +data processing is done in callbacks.. + +To be recognized by a host, a USB device must handle a subset of the USB events. +The USB device should build up control communication to report its descriptors +to the host and accept host's requests. An application or upper stack that uses +the USB device driver should have its descriptors prepared, catch the callbacks, +monitor the control requests and handle them correctly. +Usually, a USB device application that can be enumerated may use the following +sequence: + +* Initialize +* Register callback and handle Reset event, where: + + * Initialize endpoint 0 + * Register callbacks for endpoint 0, where some of the standard requests + defined in Chapter 9, USB specification + (see `USB 2.0 Documents `_) + are handled + + * Setup request handling callback + + * On *GetDeviceDescriptor* request, sends device descriptor + * On *GetConfigurationDescriptor* request, sends configuration descriptors + * On *SetAddress* request sends no data, just goes to status phase + * On *SetConfigure* request initialize and enable other endpoints, sends + no data, just goes to status phase + * Transfer done handling callback + + * On *SetAddress* request apply the new address + * On *SetConfigure* request a global variable can be set to indicates + that the host driver is loaded and device is ready to work + * Enable endpoint 0 +* Enable +* Attach device + +To support USB transfer on endpoints, endpoints information is stored +by the driver internally, including control request data, endpoint status, +callbacks and transfer data pointers. The number of endpoints that the driver +can support is defined through configuration. To optimize RAM usage, the +number of endpoints the driver needs to support should be minimized. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* USB device attachment/detachment +* USB device address control +* USB working speed status +* USB device frame number and micro frame number status +* Sending remote wakeup to host +* Callback management for following USB events: + + * Start of Frame (SOF) + * Other USB events: + + * VBus change + * Reset + * Wakeup + * Linked Power Management (LPM) Suspend + * Suspend + * Error +* Endpoints management: + + * Endpoint initialization/de-initialization + * Endpoint enabling/disabling + * Control endpoint setup request packet + * Data transfer and abort + * Endpoint halt state control + * Endpoint status, including: + + * Endpoint address + * Last transfer result status code + * Last error status code + * Current transfer state + * Transfer size and done count + * Endpoint callback management for endpoint and its transfer events: + + * In case a setup request received on control endpoint + * In case transfer finished with/without error + +Applications +------------ + +USB Device stack, to monitor USB events, handle control requests and process +data. + +Dependencies +------------ + +* USB device capable hardware +* 48MHz clock for low-speed and full-speed and 480MHz clock for high-speed + +Concurrency +----------- + +N/A + +Limitations +----------- + +* When a buffer is used by a USB endpoint to transfer data, it must be kept + unchanged while the transfer is in progress. +* After receiving a request that has no data expected, the transfer function + must be called with data length zero to complete control status phase. + +Known issues and workarounds +---------------------------- + +N/A + +Considerations for D21 USB +-------------------------- + +Clocks +^^^^^^ + +DFLL must be used to generate 48MHz clock for USB device with either of the +following mode: + +* USB Clock Recovery Mode + + * Set "DFLL Enable", "Bypass Coarse Lock", "Chill Cycle Disable", + "USB Clock Recovery Mode", "Stable DFLL Frequency" + * Clear "Wait Lock" + * Leave "Operating Mode Selection" to "Closed Loop Mode" + +* Closed Loop Mode + + * Set "DFLL Enable" + * Clear "USB Clock Recovery Mode", "Stable DFLL Frequency" + * Select "Closed Loop Mode" of "Operating Mode Selection" + * Set "DFLL Multiply Factor" to 1464 or 1465 (48000000/32768) + * Select "Reference Clock Source" to use 32768Hz source, e.g., use GCLK1 and + for GCLK1 settings: + + * Set "Generic Clock Generator Enable" + * Select "XOSC32K" of "Generic clock generator 1 source", and for XOSC32K + settings: + + * Set "External 32K Oscillator Enable", "Enable 32KHz Output", + "Enable XTAL" + * Set a right value for "Startup time for the 32K Oscillator", e.g., + 1125092 us + +Endpoints +^^^^^^^^^ + +Each USB device endpoint number supports two endpoint addresses, corresponding +to IN and OUT endpoint. E.g., for endpoint 1, the endpoint IN has address 0x81 +and endpoint OUT has address 0x01. Thus, the possible supported endpoint +addresses are almost two times of max endpoint number (endpoint 0 must be used +as control endpoint instead of dedicated IN and OUT endpoints). + +Buffering and RAM usage optimization +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +When transferring data through USB device endpoints, buffer pointers can be +used to let endpoint get access to the buffer, but there are some limits: + +* For control endpoint there must always be a buffer available to put received + setup packet. +* For IN endpoint (transmit to host) the data must in RAM. +* For OUT endpoint (receive from host) the data pointer must be aligned, and + the data size must be aligned by max endpoint size and not zero. + +The driver has option for each endpoint to allocate internal static buffer as +cache to buffer input/output data, to remove upper limits. The configuration +affects the parameter check of transfer functions, and the RAM usage. + +* For control endpoints, cache buffer must be enabled to fill setup packet. + In addition, to support unaligned OUT packet and IN packet inside flash, the + buffer size must be equal to or larger than max endpoint size. +* For OUT endpoints, if the cache is allocated, it's possible to pass unaligned + buffer address and buffer size to transfer function. Else the transfer + function only accepts aligned buffer with it's size multiple of endpoint + packet size. +* For IN endpoints, if the cache is allocated, it's possible to pass buffer + pointer to internal flash or other memory part other than RAM to the transfer + function. + +To optimize the RAM usage, the configuration of max endpoint number, max number +of endpoints supported and the buffer usage of used input and/or output +endpoints can be adjusted. + diff --git a/atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h new file mode 100644 index 0000000000000..fb4604aa578b8 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h @@ -0,0 +1,287 @@ +/** + * \file + * + * \brief ADC functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ADC_SYNC_H_INCLUDED +#define _HAL_ADC_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_adc_sync + * + * @{ + */ + +/** + * \brief ADC descriptor + * + * The ADC descriptor forward declaration. + */ +struct adc_sync_descriptor; + +/** + * \brief ADC descriptor + */ +struct adc_sync_descriptor { + /** ADC device */ + struct _adc_sync_device device; +}; + +/** + * \brief Initialize ADC + * + * This function initializes the given ADC descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr An ADC descriptor to initialize + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to a set of functions pointers + * + * \return Initialization status. + */ +int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize ADC + * + * This function deinitializes the given ADC descriptor. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr An ADC descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr); + +/** + * \brief Enable ADC + * + * Use this function to set the ADC peripheral to enabled state. + * + * \param[in] descr Pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return Operation status + * + */ +int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Disable ADC + * + * Use this function to set the ADC peripheral to disabled state. + * + * \param[in] descr Pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return Operation status + * + */ +int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Read data from ADC + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, + const uint16_t length); + +/** + * \brief Set ADC reference source + * + * This function sets ADC reference source. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] reference A reference source to set + * + * \return Status of the ADC reference source setting. + */ +int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference); + +/** + * \brief Set ADC resolution + * + * This function sets ADC resolution. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] resolution A resolution to set + * + * \return Status of the ADC resolution setting. + */ +int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * This function sets ADC positive and negative input sources. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + * + * \return Status of the ADC channels setting. + */ +int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set ADC conversion mode + * + * This function sets ADC conversion mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] mode A conversion mode to set + * + * \return Status of the ADC conversion mode setting. + */ +int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode); + +/** + * \brief Set ADC differential mode + * + * This function sets ADC differential mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + * + * \return Status of the ADC differential mode setting. + */ +int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set ADC channel gain + * + * This function sets ADC channel gain. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] gain A gain to set + * + * \return Status of the ADC gain setting. + */ +int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, + const adc_gain_t gain); + +/** + * \brief Set ADC window mode + * + * This function sets ADC window mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] mode A window mode to set + * + * \return Status of the ADC window mode setting. + */ +int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode); + +/** + * \brief Set ADC thresholds + * + * This function sets ADC positive and negative thresholds. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] low_threshold A lower thresholds to set + * \param[in] up_threshold An upper thresholds to set + * + * \return Status of the ADC thresholds setting. + */ +int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * This function retrieves ADC threshold state. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[out] state The threshold state + * + * \return The state of ADC thresholds state retrieving. + */ +int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, + adc_threshold_status_t *const state); + +/** + * \brief Check if conversion is complete + * + * This function checks if the ADC has finished the conversion. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return The status of ADC conversion completion checking. + * \retval 1 The conversion is complete + * \retval 0 The conversion is not complete + */ +int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t adc_sync_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#include + +#endif /* _HAL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_atomic.h b/atmel-samd/asf4/samd21/hal/include/hal_atomic.h new file mode 100644 index 0000000000000..8a51b2a968f81 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_atomic.h @@ -0,0 +1,137 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Some critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h new file mode 100644 index 0000000000000..79c68b2cb09ac --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief DAC functionality declaration. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_SYNC_DAC_H_INCLUDED +#define HAL_SYNC_DAC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_dac_sync + * + *@{ + */ + +/** + * \brief DAC synchronous descriptor. + * + * The DAC descriptor forward declaration. + */ +struct dac_sync_descriptor; + +/** + * \brief DAC synchronous channel descriptor. + * + */ +struct dac_sync_channel { + /** Pointer to buffer what to be converted */ + uint16_t *buffer; + /** The length of buffer */ + uint32_t length; +}; + +/** + * \brief DAC synchronous descriptor + */ +struct dac_sync_descriptor { + /** DAC device */ + struct _dac_sync_device device; + /** DAC selected channel */ + struct dac_sync_channel sel_ch[CHANNEL_NUM]; +}; + +/** \brief Initialize the DAC HAL instance and hardware. + * \param[out] descr A DAC descriptor to initialize + * \param[in] hw The pointer to hardware instance + * \return Operation status. + */ +int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw); + +/** \brief Deinitialize the DAC HAL instance and hardware. + * \param[in] descr Pointer to the HAL DAC descriptor + * \return Operation status. + */ +int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr); + +/** \brief Enable DAC channel. + * \param[in] descr Pointer to the HAL DAC descriptor + * \param[in] ch Channel number + * \return Operation status. + */ +int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); + +/** \brief Disable DAC channel. + * \param[in] descr Pointer to the HAL DAC descriptor + * \param[in] ch Channel number + * \return Operation status. + */ +int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); + +/** \brief DAC converts digital data to analog output. + * \param[in] descr Pointer to the HAL DAC descriptor + * \param[in] ch the Channel selected to output + * \param[in] buffer Pointer to digital data or buffer + * \param[in] length The number of elements in the buffer + * \return Operation status. + */ +int32_t dac_sync_write(struct dac_sync_descriptor *const descr, const uint8_t ch, uint16_t *buffer, uint32_t length); + +/** \brief Get DAC driver version + * + * \return Current driver version. + */ +uint32_t dac_sync_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_delay.h b/atmel-samd/asf4/samd21/hal/include/hal_delay.h new file mode 100644 index 0000000000000..48fee826f3373 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_delay.h @@ -0,0 +1,99 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_flash.h b/atmel-samd/asf4/samd21/hal/include/hal_flash.h new file mode 100644 index 0000000000000..2e6286389f253 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_flash.h @@ -0,0 +1,219 @@ +/** + * \file + * + * \brief Flash related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_FLASH_H_INCLUDED +#define _HAL_FLASH_H_INCLUDED + +#include + +/** + * \addtogroup doc_driver_hal_flash + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Forward declaration of flash_descriptor. */ +struct flash_descriptor; + +/** The callback types */ +enum flash_cb_type { + /** Callback type for ready to accept a new command */ + FLASH_CB_READY, + /** Callback type for error */ + FLASH_CB_ERROR, + FLASH_CB_N +}; + +/** \brief Prototype of callback on FLASH + * + */ +typedef void (*flash_cb_t)(struct flash_descriptor *const descr); + +/** \brief FLASH HAL callbacks + * + */ +struct flash_callbacks { + /** Callback invoked when ready to accept a new command */ + flash_cb_t cb_ready; + /** Callback invoked when error occurs */ + flash_cb_t cb_error; +}; + +/** \brief FLASH HAL driver struct for asynchronous access + */ +struct flash_descriptor { + /** Pointer to FLASH device instance */ + struct _flash_device dev; + /** Callbacks for asynchronous transfer */ + struct flash_callbacks callbacks; +}; + +/** \brief Initialize the FLASH HAL instance and hardware for callback mode + * + * Initialize FLASH HAL with interrupt mode (uses callbacks). + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] hw Pointer to the hardware base. + * \return Initialize status. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw); + +/** \brief Deinitialize the FLASH HAL instance + * + * Abort transfer, disable and reset FLASH, and deinitialize software. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \return Deinitialze status. + */ +int32_t flash_deinit(struct flash_descriptor *flash); + +/** \brief Writes a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to a buffer where the content + * will be written to the flash + * \param[in] length Number of bytes to write + * \return Write status. + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Appends a number of bytes to a page in the internal Flash + * + * This functions never erases the flash before writing. + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address to write to flash + * \param[in] buffer Pointer to a buffer with data to write to flash + * \param[in] length Number of bytes to append + * \return Append status. + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Reads a number of bytes to a page in the internal Flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read pages will be stored + * \param[in] length Number of bytes to read + * \return Read status. + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** \brief Register a function as FLASH transfer completion callback + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] type Callback type (\ref flash_cb_type). + * \param[in] func Pointer to callback function. + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func); + +/** \brief Execute lock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** \brief Execute erase in the internal flash + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + * \retval 0 Success + * \retval -1 Error + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); + +/** + * \brief Get the flash page size + * + * \param[in, out] flash Pointer to the HAL FLASH instance + * + * \return The flash page size + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash); + +/** + * \brief Get the number of flash page + * + * \param[in, out] flash Pointer to the HAL FLASH instance. + * + * \return The flash total page numbers + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t flash_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* ifndef _HAL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_gpio.h b/atmel-samd/asf4/samd21/hal/include/hal_gpio.h new file mode 100644 index 0000000000000..f0e8af8d777fc --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_gpio.h @@ -0,0 +1,212 @@ +/** + * \file + * + * \brief Port + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin high with internal + * resistor + * GPIO_PULL_UP = Pull pin low with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hal_i2c_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_i2c_m_sync.h new file mode 100644 index 0000000000000..65741831a7c49 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_i2c_m_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_I2C_M_SYNC_H_INCLUDED +#define _HAL_I2C_M_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_i2c_master_sync + * + * @{ + */ + +#define I2C_M_MAX_RETRY 1 + +/** + * \brief I2C descriptor structure, embed i2c_device & i2c_interface + */ +struct i2c_m_sync_desc { + struct _i2c_m_sync_device device; + struct io_descriptor io; + uint16_t slave_addr; +}; + +/** + * \brief Initialize synchronous I2C interface + * + * This function initializes the given I/O descriptor to be used as a + * synchronous I2C interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + * \retval -1 The passed parameters were invalid or the interface is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); + +/** + * \brief Deinitialize I2C interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Uninitialization status. + * \retval -1 The passed parameters were invalid or the interface is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); + +/** + * \brief Set the slave device address + * + * This function sets the next transfer target slave I2C device address. + * It takes no effect to any already started access. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] addr The slave address to access + * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN + * + * \return Masked slave address. The mask is a maximum 10-bit address, and 10th + * bit is set if a 10-bit address is used + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); + +/** + * \brief Set baudrate + * + * This function sets the I2C device to the specified baudrate. + * It only takes effect when the hardware is disabled. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] clkrate Unused parameter. Should always be 0 + * \param[in] baudrate The baudrate value set to master + * + * \return Whether successfully set the baudrate + * \retval -1 The passed parameters were invalid or the device is already enabled + * \retval 0 The baudrate set is completed successfully + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Sync version of enable hardware + * + * This function enables the I2C device, and then waits for this enabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully enable the device + * \retval -1 The passed parameters were invalid or the device enable failed + * \retval 0 The hardware enabling is completed successfully + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of disable hardware + * + * This function disables the I2C device and then waits for this disabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully disable the device + * \retval -1 The passed parameters were invalid or the device disable failed + * \retval 0 The hardware disabling is completed successfully + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of write command to I2C slave + * + * This function will write the value to a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer holding data to write to the I2C slave device + * \param[in] length The length (in bytes) to write to the I2C slave device + * + * \return Whether successfully write to the device + * \retval <0 The passed parameters were invalid or write fail + * \retval 0 Writing to register is completed successfully + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of read register value from I2C slave + * + * This function will read a byte value from a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer to hold the read data from the I2C slave device + * \param[in] length The length (in bytes) to read from the I2C slave device + * + * \return Whether successfully read from the device + * \retval <0 The passed parameters were invalid or read fail + * \retval 0 Reading from register is completed successfully + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of transfer message to/from the I2C slave + * + * This function will transfer a message between the I2C slave and the master. This function will wait for the operation + * to be done. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] msg An i2c_m_msg struct + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); + +/** + * \brief Sync version of send stop condition on the i2c bus + * + * This function will create a stop condition on the i2c bus to release the bus + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); + +/** + * \brief Return I/O descriptor for this I2C instance + * + * This function will return a I/O instance for this I2C driver instance + * + * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C + * \param[in] io_descriptor A pointer to an I/O descriptor pointer type + * + * \return Error code + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t i2c_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hal_init.h b/atmel-samd/asf4/samd21/hal/include/hal_init.h new file mode 100644 index 0000000000000..a970943eb27a7 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_init.h @@ -0,0 +1,82 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_io.h b/atmel-samd/asf4/samd21/hal/include/hal_io.h new file mode 100644 index 0000000000000..e8005e3db3e18 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_io.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_pwm.h b/atmel-samd/asf4/samd21/hal/include/hal_pwm.h new file mode 100644 index 0000000000000..29efc4bc40308 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_pwm.h @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief PWM functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_PWM_H_INCLUDED +#define HAL_PWM_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_pwm_async + * + *@{ + */ + +/** + * \brief PWM descriptor + * + * The PWM descriptor forward declaration. + */ +struct pwm_descriptor; + +/** + * \brief PWM callback type + */ +typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr); + +/** + * \brief PWM callback types + */ +enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB }; + +/** + * \brief PWM callbacks + */ +struct pwm_callbacks { + pwm_cb_t period; + pwm_cb_t error; +}; + +/** \brief PWM descriptor + */ +struct pwm_descriptor { + /** PWM device */ + struct _pwm_device device; + /** PWM callback structure */ + struct pwm_callbacks pwm_cb; +}; + +/** \brief Initialize the PWM HAL instance and hardware + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to a set of functions pointers + * + * \return Operation status. + */ +int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func); + +/** \brief Deinitialize the PWM HAL instance and hardware + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_deinit(struct pwm_descriptor *const descr); + +/** \brief PWM output start + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_enable(struct pwm_descriptor *const descr); + +/** \brief PWM output stop + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_disable(struct pwm_descriptor *const descr); + +/** \brief Register PWM callback + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] type Callback type + * \param[in] cb A callback function, passing NULL de-registers callback + * + * \return Operation status. + * \retval 0 Success + * \retval -1 Error + */ +int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb); + +/** \brief Change PWM parameter + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] period Total period of one PWM cycle + * \param[in] duty_cycle Period of PWM first half during one cycle + * + * \return Operation status. + */ +int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, + const pwm_period_t duty_cycle); + +/** \brief Get PWM driver version + * + * \return Current driver version. + */ +uint32_t pwm_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_PWM;_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_sleep.h b/atmel-samd/asf4/samd21/hal/include/hal_sleep.h new file mode 100644 index 0000000000000..0a11856b1ea49 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_sleep.h @@ -0,0 +1,84 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_spi_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_spi_m_sync.h new file mode 100644 index 0000000000000..2c630ff09a2ce --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_spi_m_sync.h @@ -0,0 +1,220 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SPI_M_SYNC_H_INCLUDED +#define _HAL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup doc_driver_hal_spi_master_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief SPI HAL driver struct for polling mode + * + */ +struct spi_m_sync_descriptor { + /** SPI device instance */ + struct _spi_sync_dev dev; + /** I/O read/write */ + struct io_descriptor io; + /** Flags for HAL driver */ + uint16_t flags; +}; + +/** \brief Initialize SPI HAL instance and hardware for polling mode + * + * Initialize SPI HAL with polling mode. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] hw Pointer to the hardware base. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_INVALID_DATA Error, initialized. + */ +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); + +/** \brief Deinitialize the SPI HAL instance and hardware + * + * Abort transfer, disable and reset SPI, deinit software. + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); + +/** \brief Enable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); + +/** \brief Disable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); + +/** \brief Set SPI baudrate + * + * Works if SPI is initialized as master, it sets the baudrate. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] baud_val The target baudrate value + * (see "baudrate calculation" for calculating the value). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The baudrate is not supported. + */ +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); + +/** \brief Set SPI mode + * + * Set the SPI transfer mode (\ref spi_transfer_mode), + * which controls the clock polarity and clock phase: + * - Mode 0: leading edge is rising edge, data sample on leading edge. + * - Mode 1: leading edge is rising edge, data sample on trailing edge. + * - Mode 2: leading edge is falling edge, data sample on leading edge. + * - Mode 3: leading edge is falling edge, data sample on trailing edge. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] mode The mode (0~3). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The mode is not supported. + */ +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); + +/** \brief Set SPI transfer character size in number of bits + * + * The character size (\ref spi_char_size) influence the way the data is + * sent/received. + * For char size <= 8-bit, data is stored byte by byte. + * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. + * Note that the default and recommended char size is 8-bit since it's + * supported by all system. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] char_size The char size (~16, recommended 8). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The char size is not supported. + */ +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); + +/** \brief Set SPI transfer data order + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] dord The data order: send LSB/MSB first. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The data order is not supported. + */ +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); + +/** \brief Perform the SPI data transfer (TX and RX) in polling way + * + * Activate CS, do TX and RX and deactivate CS. It blocks. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). + * + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + * \retval ERR_BUSY SPI is busy + */ +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); + +/** + * \brief Return the I/O descriptor for this SPI instance + * + * This function will return an I/O instance for this SPI driver instance. + * + * \param[in] spi An SPI master descriptor, which is used to communicate through + * SPI + * \param[in, out] io A pointer to an I/O descriptor pointer type + * + * \retval ERR_NONE + */ +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t spi_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_timer.h b/atmel-samd/asf4/samd21/hal/include/hal_timer.h new file mode 100644 index 0000000000000..b5c8f60821a3d --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_timer.h @@ -0,0 +1,216 @@ +/** + * \file + * + * \brief Timer task functionality declaration. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_TIMER_H_INCLUDED +#define _HAL_TIMER_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_timer + * + * @{ + */ + +/** + * \brief Timer mode type + */ +enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; + +/** + * \brief Timer task descriptor + * + * The timer task descriptor forward declaration. + */ +struct timer_task; + +/** + * \brief Timer task callback function type + */ +typedef void (*timer_cb_t)(const struct timer_task *const timer_task); + +/** + * \brief Timer task structure + */ +struct timer_task { + struct list_element elem; /*! List element. */ + uint32_t time_label; /*! Absolute timer start time. */ + + uint32_t interval; /*! Number of timer ticks before calling the task. */ + timer_cb_t cb; /*! Function pointer to the task. */ + enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ +}; + +/** + * \brief Timer structure + */ +struct timer_descriptor { + struct _timer_device device; + uint32_t time; + struct list_descriptor tasks; /*! Timer tasks list. */ + volatile uint8_t flags; +}; + +/** + * \brief Initialize timer + * + * This function initializes the given timer. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A timer descriptor to initialize + * \param[in] hw The pointer to the hardware instance + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); + +/** + * \brief Deinitialize timer + * + * This function deinitializes the given timer. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr A timer descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t timer_deinit(struct timer_descriptor *const descr); + +/** + * \brief Start timer + * + * This function starts the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to start + * + * \return Timer starting status. + */ +int32_t timer_start(struct timer_descriptor *const descr); + +/** + * \brief Stop timer + * + * This function stops the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * + * \return Timer stopping status. + */ +int32_t timer_stop(struct timer_descriptor *const descr); + +/** + * \brief Set amount of clock cycles per timer tick + * + * This function sets the amount of clock cycles per timer tick for the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * \param[in] clock_cycles The amount of clock cycles per tick to set + * + * \return Setting clock cycles amount status. + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); + +/** + * \brief Retrieve the amount of clock cycles in a tick + * + * This function retrieves how many clock cycles there are in a single timer tick. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to convert ticks to + * clock cycles + * \param[out] cycles The amount of clock cycles + * + * \return The status of clock cycles retrieving. + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); + +/** + * \brief Add timer task + * + * This function adds the given timer task to the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to add task to + * \param[in] task A task to add + * + * \return Timer's task adding status. + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); + +/** + * \brief Remove timer task + * + * This function removes the given timer task from the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to remove task from + * \param[in] task A task to remove + * + * \return Timer's task removing status. + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t timer_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_usart_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_usart_sync.h new file mode 100644 index 0000000000000..e2aef748d3e6a --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_usart_sync.h @@ -0,0 +1,257 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_usb_device.h b/atmel-samd/asf4/samd21/hal/include/hal_usb_device.h new file mode 100644 index 0000000000000..8b7bd5ec79159 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hal_usb_device.h @@ -0,0 +1,305 @@ +/** + * \file + * + * \brief SAM USB device HAL + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_USB_DEVICE_H_INCLUDED +#define _HAL_USB_DEVICE_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_usb_device + * + * @{ + */ + +/** USB device endpoint status structure. */ +struct usb_d_ep_status { + /** Endpoint address, including direction. */ + uint8_t ep; + /** Endpoint transfer status code that triggers the callback. + * \ref usb_xfer_code. */ + uint8_t code; + /** Endpoint error, if \c code is \ref USB_TRANS_ERROR. */ + uint8_t error; + /** Transfer state, \ref usb_ep_state. */ + uint8_t state; + /** Transfer count. */ + uint32_t count; + /** Transfer size. */ + uint32_t size; +}; + +/** Prototype function for callback that is invoked on USB device SOF. */ +typedef void (*usb_d_sof_cb_t)(void); + +/** Prototype function for callback that is invoked on USB device events. */ +typedef void (*usb_d_event_cb_t)(const enum usb_event event, const uint32_t param); + +/** USB device callbacks. */ +struct usb_d_callbacks { + /** Callback that is invoked on SOF. */ + usb_d_sof_cb_t sof; + /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ + usb_d_event_cb_t event; +}; + +/** Callback that is invoked when setup packet is received. + * Return \c true if request has been handled, or control endpoint will + * stall IN/OUT transactions. + */ +typedef bool (*usb_d_ep_cb_setup_t)(const uint8_t ep, const uint8_t *req); + +/** Callback that is invoked when buffer is done without error, but last packet + * is full size packet without ZLP. + * Return \c true if more data has been requested. + */ +typedef bool (*usb_d_ep_cb_more_t)(const uint8_t ep, const uint32_t count); + +/** Callback that is invoked when all data is finished, including background + * transfer, or error happens. + * In control transfer data stage, return value is checked, + * return \c false if no error happens. + */ +typedef bool (*usb_d_ep_cb_xfer_t)(const uint8_t ep, const enum usb_xfer_code code, void *param); + +/** + * \brief Initialize the USB device driver + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_init(void); + +/** + * \brief Deinitialize the USB device driver + */ +void usb_d_deinit(void); + +/** + * \brief Register the USB device callback + * \param[in] type The callback type to register. + * \param[in] func The callback function, NULL to disable callback. + */ +void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); + +/** + * \brief Enable the USB device driver + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_enable(void); + +/** + * \brief Disable the USB device driver + */ +void usb_d_disable(void); + +/** + * \brief Attach the USB device + */ +void usb_d_attach(void); + +/** + * \brief Detach the USB device + */ +void usb_d_detach(void); + +/** + * \brief Retrieve current USB working speed. + * \return USB Speed. See \ref usb_speed. + */ +enum usb_speed usb_d_get_speed(void); + +/** + * \brief Retrieve current USB frame number. + * \return Frame number. + */ +uint16_t usb_d_get_frame_num(void); + +/** + * \brief Retrieve current USB micro frame number. + * \return Micro frame number inside a frame (0~7). + * 0 if not available (not HS). + */ +uint8_t usb_d_get_uframe_num(void); + +/** + * \brief Set the USB address that is used. + * \param[in] addr The address to set. + */ +void usb_d_set_address(const uint8_t addr); + +/** + * \brief Send remote wakeup to host + * \return Operation status. + */ +void usb_d_send_remotewakeup(void); + +/** + * \brief Initialize the endpoint 0. + * + * Note that endpoint 0 must be initialized as control endpoint. + * + * \param[in] max_pkt_size Max. packet size of EP0. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep0_init(const uint8_t max_pkt_size); + +/** + * \brief Initialize the endpoint. + * + * \param[in] ep The endpoint address. + * \param[in] attr The endpoint attributes. + * \param[in] max_pkt_size Max. packet size of EP0. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size); + +/** + * \brief Disable and deinitialize the endpoint. + * \param[in] ep The endpoint address to deinitialize. + */ +void usb_d_ep_deinit(const uint8_t ep); + +/** + * \brief Register the USB device endpoint callback on initialized endpoint. + * + * \param[in] ep The endpoint address. + * \param[in] type The callback type to register. + * \param[in] func The callback function, NULL to disable callback. + */ +void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func); + +/** + * \brief Enabled the initialized endpoint. + * + * Setup request will be monitored after enabling a control endpoint. + * + * \param[in] ep The endpoint address. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep_enable(const uint8_t ep); + +/** + * \brief Disable the initialized endpoint. + * \param[in] ep The endpoint address. + */ +void usb_d_ep_disable(const uint8_t ep); + +/** + * \brief Get request data pointer to access received setup request packet + * \param[in] ep The endpoint address. + * \return Pointer to the request data. + * \retval NULL The endpoint is not a control endpoint. + */ +uint8_t *usb_d_ep_get_req(const uint8_t ep); + +/** + * \brief Endpoint transfer. + * + * For control endpoints, start the transfer according to the direction in the bmRequest + * type, and finish with STATUS stage. + * For non-control endpoints, the transfer will be unique direction. Defined by + * bit 8 of the endpoint address. + * + * \param[in] xfer Pointer to the transfer description. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer); + +/** + * \brief Abort an on-going transfer on a specific endpoint. + * + * \param[in] ep The endpoint address. + */ +void usb_d_ep_abort(const uint8_t ep); + +/** + * \brief Retrieve the endpoint status. + * + * \param[in] ep The endpoint address. + * \param[out] stat Pointer to the buffer to fill the status description. + * + * \return Endpoint status. + * \retval 1 Busy. + * \retval 0 Idle. + * \retval <0 Error code. + */ +int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat); + +/** + * \brief Endpoint halt control. + * + * \param[in] ep The endpoint address. + * \param[in] ctrl Control code (SET/CLEAR/GET). + * + * \return Operation status or HALT state (if \c ctrl is \ref USB_EP_HALT_GET). + */ +int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usb_d_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h new file mode 100644 index 0000000000000..31612be00e42a --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h @@ -0,0 +1,274 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_ASYNC_H_INCLUDED +#define _HPL_ADC_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL ADC + * + * \section hpl_async_adc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_adc_sync.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief ADC device structure + * + * The ADC device structure forward declaration. + */ +struct _adc_async_device; + +/** + * \brief ADC callback types + */ +enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB }; + +/** + * \brief ADC interrupt callbacks + */ +struct _adc_async_callbacks { + void (*window_cb)(struct _adc_async_device *device, const uint8_t channel); + void (*error_cb)(struct _adc_async_device *device, const uint8_t channel); +}; + +/** + * \brief ADC channel interrupt callbacks + */ +struct _adc_async_ch_callbacks { + void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data); +}; + +/** + * \brief ADC descriptor device structure + */ +struct _adc_async_device { + struct _adc_async_callbacks adc_async_cb; + struct _adc_async_ch_callbacks adc_async_ch_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous ADC + * + * This function does low level ADC configuration. + * + * param[in] device The pointer to ADC device instance + * param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw); + +/** + * \brief Deinitialize ADC + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_async_deinit(struct _adc_async_device *const device); + +/** + * \brief Enable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Disable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Retrieve ADC conversion data size + * + * \param[in] device The pointer to ADC device instance + * + * \return The data size in bytes + */ +uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device); + +/** + * \brief Check if conversion is done + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * \return The status of conversion + * \retval true The conversion is done + * \retval false The conversion is not done + */ +bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Make conversion + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_async_convert(struct _adc_async_device *const device); + +/** + * \brief Retrieve the conversion result + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * The result value + */ +uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Set reference source + * + * \param[in] device The pointer to ADC device instance + * \param[in] reference A reference source to set + */ +void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference); + +/** + * \brief Set resolution + * + * \param[in] device The pointer to ADC device instance + * \param[in] resolution A resolution to set + */ +void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * \param[in] device The pointer to ADC device instance + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + */ +void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set conversion mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A conversion mode to set + */ +void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode); + +/** + * \brief Set differential mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + */ +void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set gain + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] gain A gain to set + */ +void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain); + +/** + * \brief Set window mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A mode to set + */ +void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode); + +/** + * \brief Set lower threshold + * + * \param[in] device The pointer to ADC device instance + * \param[in] low_threshold A lower threshold to set + * \param[in] up_threshold An upper thresholds to set + */ +void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * \param[in] device The pointer to ADC device instance + * \param[out] state The threshold state + */ +void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state); + +/** + * \brief Enable/disable ADC channel interrupt + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, + const enum _adc_async_callback_type type, const bool state); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_ADC_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h new file mode 100644 index 0000000000000..40ff158d23a90 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h @@ -0,0 +1,253 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_DMA_H_INCLUDED +#define _HPL_ADC_DMA_H_INCLUDED + +/** + * \addtogroup HPL ADC + * + * \section hpl_dma_adc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief ADC device structure + * + * The ADC device structure forward declaration. + */ +struct _adc_dma_device; + +/** + * \brief ADC callback types + */ +enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB }; + +/** + * \brief ADC interrupt callbacks + */ +struct _adc_dma_callbacks { + void (*complete)(struct _adc_dma_device *device, const uint16_t data); + void (*error)(struct _adc_dma_device *device); +}; + +/** + * \brief ADC descriptor device structure + */ +struct _adc_dma_device { + struct _adc_dma_callbacks adc_dma_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous ADC + * + * This function does low level ADC configuration. + * + * param[in] device The pointer to ADC device instance + * param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw); + +/** + * \brief Deinitialize ADC + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_dma_deinit(struct _adc_dma_device *const device); + +/** + * \brief Enable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel); + +/** + * \brief Disable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel); + +/** + * \brief Return address of ADC DMA source + * + * \param[in] device The pointer to ADC device instance + * + * \return ADC DMA source address + */ +uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device); + +/** + * \brief Retrieve ADC conversion data size + * + * \param[in] device The pointer to ADC device instance + * + * \return The data size in bytes + */ +uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device); + +/** + * \brief Check if conversion is done + * + * \param[in] device The pointer to ADC device instance + * + * \return The status of conversion + * \retval true The conversion is done + * \retval false The conversion is not done + */ +bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device); + +/** + * \brief Make conversion + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_dma_convert(struct _adc_dma_device *const device); + +/** + * \brief Set reference source + * + * \param[in] device The pointer to ADC device instance + * \param[in] reference A reference source to set + */ +void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference); + +/** + * \brief Set resolution + * + * \param[in] device The pointer to ADC device instance + * \param[in] resolution A resolution to set + */ +void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * \param[in] device The pointer to ADC device instance + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + */ +void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set conversion mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A conversion mode to set + */ +void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode); + +/** + * \brief Set differential mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + */ +void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set gain + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] gain A gain to set + */ +void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain); + +/** + * \brief Set window mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A mode to set + */ +void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode); + +/** + * \brief Set thresholds + * + * \param[in] device The pointer to ADC device instance + * \param[in] low_threshold A lower thresholds to set + * \param[in] up_threshold An upper thresholds to set + */ +void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * \param[in] device The pointer to ADC device instance + * \param[out] state The threshold state + */ +void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_ADC_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h new file mode 100644 index 0000000000000..84ab01ab32295 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h @@ -0,0 +1,281 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_SYNC_H_INCLUDED +#define _HPL_ADC_SYNC_H_INCLUDED + +/** + * \addtogroup HPL ADC + * + * \section hpl_adc_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief ADC reference source + */ +typedef uint8_t adc_reference_t; + +/** + * \brief ADC resolution + */ +typedef uint8_t adc_resolution_t; + +/** + * \brief ADC positive input for channel + */ +typedef uint8_t adc_pos_input_t; + +/** + * \brief ADC negative input for channel + */ +typedef uint8_t adc_neg_input_t; + +/** + * \brief ADC threshold + */ +typedef uint16_t adc_threshold_t; + +/** + * \brief ADC gain + */ +typedef uint8_t adc_gain_t; + +/** + * \brief ADC conversion mode + */ +enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN }; + +/** + * \brief ADC differential mode + */ +enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL }; + +/** + * \brief ADC window mode + */ +typedef uint8_t adc_window_mode_t; + +/** + * \brief ADC threshold status + */ +typedef bool adc_threshold_status_t; + +/** + * \brief ADC sync descriptor device structure + */ +struct _adc_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous ADC + * + * This function does low level ADC configuration. + * + * param[in] device The pointer to ADC device instance + * param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize ADC + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_sync_deinit(struct _adc_sync_device *const device); + +/** + * \brief Enable ADC + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Disable ADC + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Retrieve ADC conversion data size + * + * \param[in] device The pointer to ADC device instance + * + * \return The data size in bytes + */ +uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device); + +/** + * \brief Check if conversion is done + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * \return The status of conversion + * \retval true The conversion is done + * \retval false The conversion is not done + */ +bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Make conversion + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_sync_convert(struct _adc_sync_device *const device); + +/** + * \brief Retrieve the conversion result + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * \return The result value of channel + */ +uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Set reference source + * + * \param[in] device The pointer to ADC device instance + * \param[in] reference A reference source to set + */ +void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference); + +/** + * \brief Set resolution + * + * \param[in] device The pointer to ADC device instance + * \param[in] resolution A resolution to set + */ +void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * \param[in] device The pointer to ADC device instance + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + */ +void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set conversion mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A conversion mode to set + */ +void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode); + +/** + * \brief Set differential mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + */ +void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set gain + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] gain A gain to set + */ +void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain); + +/** + * \brief Set window mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A mode to set + */ +void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode); + +/** + * \brief Set threshold + * + * \param[in] device The pointer to ADC device instance + * \param[in] low_threshold A lower threshold to set + * \param[in] up_threshold An upper thresholds to set + */ +void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * \param[in] device The pointer to ADC device instance + * \param[out] state The threshold state + */ +void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_calendar.h b/atmel-samd/asf4/samd21/hal/include/hpl_calendar.h new file mode 100644 index 0000000000000..9b9002c2523b3 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_calendar.h @@ -0,0 +1,252 @@ +/** + * \file + * + * \brief Generic CALENDAR functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_CALENDER_H_INCLUDED +#define _HPL_CALENDER_H_INCLUDED + +#include +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Calendar structure + * + * The Calendar structure forward declaration. + */ +struct calendar_dev; + +/** + * \brief Available mask options for alarms. + * + * Available mask options for alarms. + */ +enum calendar_alarm_option { + /** Alarm disabled. */ + CALENDAR_ALARM_MATCH_DISABLED = 0, + /** Alarm match on second. */ + CALENDAR_ALARM_MATCH_SEC, + /** Alarm match on second and minute. */ + CALENDAR_ALARM_MATCH_MIN, + /** Alarm match on second, minute, and hour. */ + CALENDAR_ALARM_MATCH_HOUR, + /** Alarm match on second, minute, hour, and day. */ + CALENDAR_ALARM_MATCH_DAY, + /** Alarm match on second, minute, hour, day, and month. */ + CALENDAR_ALARM_MATCH_MONTH, + /** Alarm match on second, minute, hour, day, month and year. */ + CALENDAR_ALARM_MATCH_YEAR +}; + +/** + * \brief Available mode for alarms. + */ +enum calendar_alarm_mode { ONESHOT = 1, REPEAT }; +/** + * \brief Prototype of callback on alarm match + */ +typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev); + +/** + * \brief Structure of Calendar instance + */ +struct calendar_dev { + /** Pointer to the hardware base */ + void *hw; + /** Alarm match callback */ + calendar_drv_cb_alarm_t callback; + /** IRQ struct */ + struct _irq_descriptor irq; +}; + +/** + * \brief Time struct for calendar + */ +struct calendar_time { + /*range from 0 to 59*/ + uint8_t sec; + /*range from 0 to 59*/ + uint8_t min; + /*range from 0 to 23*/ + uint8_t hour; +}; + +/** + * \brief Time struct for calendar + */ +struct calendar_date { + /*range from 1 to 28/29/30/31*/ + uint8_t day; + /*range from 1 to 12*/ + uint8_t month; + /*absolute year>= 1970(such as 2000)*/ + uint16_t year; +}; + +/** \brief Calendar driver struct + * + */ +struct calendar_descriptor { + struct calendar_dev device; + struct list_descriptor alarms; + /*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/ + uint32_t base_year; + uint8_t flags; +}; + +/** \brief Date&Time struct for calendar + */ +struct calendar_date_time { + struct calendar_time time; + struct calendar_date date; +}; + +/** \brief struct for alarm time + */ +struct _calendar_alarm { + struct calendar_date_time datetime; + uint32_t timestamp; + enum calendar_alarm_option option; + enum calendar_alarm_mode mode; +}; + +/** + * \brief Initialize Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_init(struct calendar_dev *const dev); + +/** + * \brief Deinitialize Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_deinit(struct calendar_dev *const dev); + +/** + * \brief Enable Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_enable(struct calendar_dev *const dev); + +/** + * \brief Disable Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_disable(struct calendar_dev *const dev); +/** + * \brief Set time for calendar + * + * \param[in] dev The pointer to calendar device struct + * \param[in] p_calendar_time Pointer to the time configuration + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_set_time(struct calendar_dev *const dev, struct calendar_time *const p_calendar_time); + +/** + * \brief Set date for calendar + * + * \param[in] dev The pointer to calendar device struct + * \param[in] p_calendar_date Pointer to the date configuration + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_set_date(struct calendar_dev *const dev, struct calendar_date *const p_calendar_date); + +/** + * \brief Get the time for calendar HAL instance and hardware + * Retrieve the time from calendar instance. + * + * \param[in] dev The pointer to calendar device struct + * \param[in] date_time Pointer to value that will be filled with current time + * + * \return Return current counter value + */ +uint32_t _calendar_get_date_time(struct calendar_dev *const dev, struct calendar_date_time *const date_time); + +/** + * \brief Set compare value for calendar + * + * \param[in] dev The pointer to calendar device struct + * \param[in] alarm Pointer to the configuration + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_set_alarm(struct calendar_dev *const dev, struct _calendar_alarm *const alarm); + +/** + * \brief Register callback for calendar alarm + * + * \param[in] dev The pointer to calendar device struct + * \param[in] callback The pointer to callback function + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback); + +/** + * \brief Set calendar IRQ + * + * \param[in] dev The pointer to calendar device struct + */ +void _calendar_set_irq(struct calendar_dev *const dev); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RTC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_core.h b/atmel-samd/asf4/samd21/hal/include/hpl_core.h new file mode 100644 index 0000000000000..db448a16ac253 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_core.h @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h new file mode 100644 index 0000000000000..fe55e601587dc --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief DAC related functionality declaration. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_DAC_H_INCLUDED +#define _HPL_DAC_H_INCLUDED + +/** + * \addtogroup hpl__dac__group DAC HPL APIs + * See interface description here: \ref hpl__dac__doc + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * DAC hardware Channel Number + */ + +#ifndef CHANNEL_NUM +#define CHANNEL_NUM 1 +#endif + +/** + * \brief DAC callback types + */ +enum _dac_callback_type { DAC_DEVICE_CONVERSION_DONE_CB, DAC_DEVICE_ERROR_CB }; + +/** + * \brief DAC device structure + * + * The DAC device structure forward declaration. + */ +struct _dac_async_device; + +/** + * \brief DAC interrupt handlers structure + */ +struct _dac_callback { + /** Transmit ready(Data Buffer empty) handler */ + void (*tx_ready_cb)(struct _dac_async_device *device, const uint8_t ch); + /** Error handler */ + void (*tx_error_cb)(struct _dac_async_device *device, const uint8_t ch); +}; + +/** + * \brief DAC descriptor device structure. + */ +struct _dac_async_device { + struct _dac_callback dac_cb; /*!< Interrupt handers */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize asynchronous DAC. + * + * This function does low level DAC configuration. + * + * \param[in] device The pointer to DAC device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw); + +/** + * \brief Deinitialize DAC. + * + * \param[in] device The pointer to DAC device instance + */ +void _dac_async_deinit(struct _dac_async_device *const device); + +/** + * \brief Enable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch); + +/** + * \brief Disable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch); + +/** + * \brief Checks if DAC channel is enabled + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + * + * \return true channel is enabled, false otherwise + */ +bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch); + +/** + * \brief Write DAC data for output. + * + * \param[in] device The pointer to DAC device instance + * \param[in] data Digital data which to be converted + * \param[in] ch The channel selected to output + */ +void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch); + +/** + * \brief Enable/disable DAC interrupt + * + * param[in] device The pointer to DAC device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +/** + * \page hpl__dac__doc DAC HPL Interface Driver + * + * \section hpl__dac__desc DAC HPL Description + * + * The following device can use this HPL driver + * - Atmel | SMART SAM D21 + * + * \section hpl__dac__imple DAC HPL Implements + * - \subpage hpl__dac__hw_module1__doc + */ + +#endif /* _HPL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h new file mode 100644 index 0000000000000..49a7222bf4d16 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h @@ -0,0 +1,148 @@ +/** + * \file + * + * \brief DAC related functionality declaration. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_DAC_SYNC_H_INCLUDED +#define _HPL_DAC_SYNC_H_INCLUDED + +/** + * \addtogroup hpl__dac__group DAC HPL APIs + * See interface description here: \ref hpl__dac__doc + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * DAC hardware Channel Number + */ + +#ifndef CHANNEL_NUM +#define CHANNEL_NUM 1 +#endif + +/** + * \brief DAC sync descriptor device structure. + */ +struct _dac_sync_device { + void *hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize synchronous DAC. + * + * This function does low level DAC configuration. + * + * \param[in] device The pointer to DAC device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize DAC. + * + * \param[in] device The pointer to DAC device instance + */ +void _dac_sync_deinit(struct _dac_sync_device *const device); + +/** + * \brief Enable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch); + +/** + * \brief Disable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch); + +/** + * \brief Checks if DAC channel is enabled + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + * + * \return true channel is enabled, false otherwise + */ +bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch); + +/** + * \brief Write synchronous DAC data for output. + * + * \param[in] device The pointer to DAC device instance + * \param[in] data Digital data which to be converted + * \param[in] ch The channel selected to output + */ +void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +/** + * \page hpl__dac__doc DAC HPL Interface Driver + * + * \section hpl__dac__desc DAC HPL Description + * + * The following device can use this HPL driver + * - Atmel | SMART SAM D21 + * + * \section hpl__dac__imple DAC HPL Implements + * - \subpage hpl__dac__hw_module1__doc + */ + +#endif /* _HPL_DAC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_delay.h b/atmel-samd/asf4/samd21/hal/include/hpl_delay.h new file mode 100644 index 0000000000000..7d2a6f90bf863 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_delay.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_dma.h new file mode 100644 index 0000000000000..f8c8cce42392c --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_dma.h @@ -0,0 +1,167 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_flash.h b/atmel-samd/asf4/samd21/hal/include/hpl_flash.h new file mode 100644 index 0000000000000..774bb5e0b2faf --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_flash.h @@ -0,0 +1,228 @@ +/** + * \file + * + * \brief FLASH related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_FLASH_H_INCLUDED +#define _HPL_FLASH_H_INCLUDED + +/** + * \addtogroup hpl__flash__group FLASH HPL APIs + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief FLASH device structure + * + * The FLASH device structure forward declaration. + */ +struct _flash_device; + +/** The callback types */ +enum _flash_cb_type { FLASH_DEVICE_CB_READY, FLASH_DEVICE_CB_ERROR, FLASH_DEVICE_CB_N }; + +/** + * \brief FLASH interrupt handlers structure + */ +struct _flash_callback { + /** Ready to accept new command handler */ + void (*ready_cb)(struct _flash_device *device); + /** Error handler */ + void (*error_cb)(struct _flash_device *device); +}; + +/** + * \brief FLASH descriptor device structure. + */ +struct _flash_device { + struct _flash_callback flash_cb; /*!< Interrupt handers */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize FLASH. + * + * This function does low level FLASH configuration. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialize status. + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw); + +/** + * \brief Deinitialize FLASH. + * + * \param[in] device The pointer to FLASH device instance + */ +void _flash_deinit(struct _flash_device *const device); + +/** + * \brief Reads a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] src_addr Source bytes address to read from flash + * \param[out] buffer Pointer to a buffer where the content + * of the read page will be stored + * \param[in] length Number of bytes to read + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Writes a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] length Number of bytes to write + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** + * \brief Appends a number of bytes in the internal Flash. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to write into flash + * \param[in] buffer Pointer to buffer with data to write to flash + * \param[in] length Number of bytes to write + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); + +/** \brief Execute lock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be locked + * \param[in] page_nums Number of pages to be locked + * + * \return Real locked numbers of pages. + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief Execute unlock in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be unlocked + * \param[in] page_nums Number of pages to be unlocked + * + * \return Real unlocked numbers of pages. + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** \brief check whether the region which is pointed by address + * is locked + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address to check + * + * \return The lock status of assigned address. + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr); + +/** \brief Execute erase in the internal flash + * \param[in] device The pointer to FLASH device instance + * \param[in] dst_addr Destination bytes address aligned with page + * start to be erased + * \param[in] page_nums Number of pages to be erased + */ +void _flash_erase(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); + +/** + * \brief Get the flash page size. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash page size + */ +uint32_t _flash_get_page_size(struct _flash_device *const device); + +/** + * \brief Get the numbers of flash page. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The flash total page numbers + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device); + +/** + * \brief Get the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * + * \return The number of wait states for read and write operations + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device); + +/** + * \brief Set the number of wait states for read and write operations. + * + * \param[in] device The pointer to FLASH device instance + * \param[in] state The number of wait states + * + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state); + +/** + * \brief Enable/disable Flash interrupt + * + * param[in] device The pointer to Flash device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +#endif /* _HPL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_gpio.h b/atmel-samd/asf4/samd21/hal/include/hpl_gpio.h new file mode 100644 index 0000000000000..e1de9c58ef117 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_gpio.h @@ -0,0 +1,195 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_async.h new file mode 100644 index 0000000000000..c00d7e733e0fc --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,215 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 0000000000000..4a643ee6567c8 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,195 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_async.h new file mode 100644 index 0000000000000..b240478f73f26 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,194 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 0000000000000..a0f4fa4652e5f --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_init.h b/atmel-samd/asf4/samd21/hal/include/hpl_init.h new file mode 100644 index 0000000000000..be54600c02693 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_init.h @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_irq.h b/atmel-samd/asf4/samd21/hal/include/hpl_irq.h new file mode 100644 index 0000000000000..7325b5711959f --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_irq.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_missing_features.h b/atmel-samd/asf4/samd21/hal/include/hpl_missing_features.h new file mode 100644 index 0000000000000..90fa16be4bc73 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_missing_features.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_pwm.h b/atmel-samd/asf4/samd21/hal/include/hpl_pwm.h new file mode 100644 index 0000000000000..8deb54cc02090 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_pwm.h @@ -0,0 +1,203 @@ +/** + * \file + * + * \brief PWM related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_PWM_H_INCLUDED +#define _HPL_PWM_H_INCLUDED + +/** + * \addtogroup HPL PWM + * + * \section hpl_pwm_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief PWM callback types + */ +enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; + +/** + * \brief PWM pulse-width period + */ +typedef uint32_t pwm_period_t; + +/** + * \brief PWM device structure + * + * The PWM device structure forward declaration. + */ +struct _pwm_device; + +/** + * \brief PWM interrupt callbacks + */ +struct _pwm_callback { + void (*pwm_period_cb)(struct _pwm_device *device); + void (*pwm_error_cb)(struct _pwm_device *device); +}; + +/** + * \brief PWM descriptor device structure + */ +struct _pwm_device { + struct _pwm_callback callback; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief PWM functions, pointers to low-level functions + */ +struct _pwm_hpl_interface { + int32_t (*init)(struct _pwm_device *const device, void *const hw); + void (*deinit)(struct _pwm_device *const device); + void (*start_pwm)(struct _pwm_device *const device); + void (*stop_pwm)(struct _pwm_device *const device); + void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + bool (*is_pwm_enabled)(const struct _pwm_device *const device); + pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); + uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); + void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); +}; +/** + * \brief Initialize TC + * + * This function does low level TC configuration. + * + * \param[in] device The pointer to PWM device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw); + +/** + * \brief Deinitialize TC + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_deinit(struct _pwm_device *const device); + +/** + * \brief Retrieve offset of the given tc hardware instance + * + * \param[in] device The pointer to PWM device instance + * + * \return The offset of the given tc hardware instance + */ +uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); + +/** + * \brief Start hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_enable(struct _pwm_device *const device); + +/** + * \brief Stop hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_disable(struct _pwm_device *const device); + +/** + * \brief Set pwm parameter + * + * \param[in] device The pointer to PWM device instance + * \param[in] period Total period of one PWM cycle. + * \param[in] duty_cycle Period of PWM first half during one cycle. + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + +/** + * \brief Check if pwm is working + * + * \param[in] device The pointer to PWM device instance + * + * \return Check status. + * \retval true The given pwm is working + * \retval false The given pwm is not working + */ +bool _pwm_is_enabled(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform period value + * + * \param[in] device The pointer to PWM device instance + * + * \return Period value. + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform duty cycle value + * + * \param[in] device The pointer to PWM device instance + * + * \return Duty cycle value + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device); + +/** + * \brief Enable/disable PWM interrupt + * + * param[in] device The pointer to PWM device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_reset.h b/atmel-samd/asf4/samd21/hal/include/hpl_reset.h new file mode 100644 index 0000000000000..868591ee68105 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_reset.h @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_EXT = 8, + RESET_REASON_WDT = 16, + RESET_REASON_SYST = 32, + RESET_REASON_BACKUP = 64 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_sleep.h b/atmel-samd/asf4/samd21/hal/include/hpl_sleep.h new file mode 100644 index 0000000000000..3bd6a1cb2018a --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_sleep.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi.h new file mode 100644 index 0000000000000..14177642f729f --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi.h @@ -0,0 +1,173 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2014 - 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_async.h new file mode 100644 index 0000000000000..b81ef12aff59b --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_async.h @@ -0,0 +1,137 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer complete. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_complete_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_complete_t complete; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_dma.h new file mode 100644 index 0000000000000..3f2088c05e14e --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_dma.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Common SPI DMA related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_DMA_H_INCLUDED +#define _HPL_SPI_DMA_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** The callback types */ +enum _spi_dma_dev_cb_type { + /** Callback type for DMA transmit. */ + SPI_DEV_CB_DMA_TX, + /** Callback type for DMA receive. */ + SPI_DEV_CB_DMA_RX, + /** Callback type for DMA error. */ + SPI_DEV_CB_DMA_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_DMA_N +}; + +struct _spi_dma_dev; + +/** + * \brief The prototype for callback on SPI DMA. + */ +typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_dma_dev_callbacks { + _spi_dma_cb_t tx; + _spi_dma_cb_t rx; + _spi_dma_cb_t error; +}; + +/** SPI driver to support DMA HAL */ +struct _spi_dma_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Pointer to callback functions */ + struct _spi_dma_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; + /** DMA resource */ + struct _dma_resource *resource; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_async.h new file mode 100644 index 0000000000000..f2d330495504a --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_async.h @@ -0,0 +1,248 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_complete_t _spi_async_dev_cb_complete_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_ss_detect(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_dma.h new file mode 100644 index 0000000000000..5e676fdc51001 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,187 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_sync.h new file mode 100644 index 0000000000000..fff1db4f2beb4 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,171 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_async.h new file mode 100644 index 0000000000000..aec3c0a6f1717 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_async.h @@ -0,0 +1,227 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_s_async_dev_cb_complete_t _spi_async_dev_cb_complete_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_sync.h new file mode 100644 index 0000000000000..d4236869714d6 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,237 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_sync.h new file mode 100644 index 0000000000000..a231a0bb5cdb2 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_spi_sync.h @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_time_measure.h b/atmel-samd/asf4/samd21/hal/include/hpl_time_measure.h new file mode 100644 index 0000000000000..7502a59107db6 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_time_measure.h @@ -0,0 +1,104 @@ +/** + * \file + * + * \brief Time measure related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIME_MEASURE_H_INCLUDED +#define _HPL_TIME_MEASURE_H_INCLUDED + +/** + * \addtogroup HPL Time measure + * + * \section hpl_time_measure_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief System time type + */ +typedef uint32_t system_time_t; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_init(void *const hw); + +/** + * \brief Deinitialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_deinit(void *const hw); + +/** + * \brief Get system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get(const void *const hw); + +/** + * \brief Get maximum possible system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get_max_time_value(const void *const hw); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_timer.h b/atmel-samd/asf4/samd21/hal/include/hpl_timer.h new file mode 100644 index 0000000000000..d2434e8c40f93 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_timer.h @@ -0,0 +1,170 @@ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usart.h b/atmel-samd/asf4/samd21/hal/include/hpl_usart.h new file mode 100644 index 0000000000000..f6235de93ac8e --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_usart.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usart_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_usart_async.h new file mode 100644 index 0000000000000..1bcb3da440126 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_usart_async.h @@ -0,0 +1,280 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usart_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_usart_sync.h new file mode 100644 index 0000000000000..c7881583cc225 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_usart_sync.h @@ -0,0 +1,253 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usb.h b/atmel-samd/asf4/samd21/hal/include/hpl_usb.h new file mode 100644 index 0000000000000..d31bd978559f6 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_usb.h @@ -0,0 +1,281 @@ +/** + * \file + * + * \brief SAM USB HPL + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USB_H_INCLUDED +#define _HPL_USB_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \name USB Spec definitions */ +/*@{*/ + +/** Return 8-bit unsigned USB data. */ +#define USB_GET_U8(addr, offset) (((uint8_t *)(addr))[(offset)]) + +/** Return 16-bit unsigned USB data. */ +#define USB_GET_U16(addr, offset) ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8)) + +/** Return 32-bit unsigned USB data. */ +#define USB_GET_U32(addr, offset) \ + ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8) \ + + (((uint8_t *)(addr))[(offset) + 2] << 16) \ + + (((uint8_t *)(addr))[(offset) + 3] << 32)) + +/** Offset of bmRequestType in USB request buffer. */ +#define USB_bmRequestType_Offset 0 + +/** Offset of bRequest in USB request buffer. */ +#define USB_bRequest_Offset 1 + +/** Offset of wValue in USB request buffer. */ +#define USB_wValue_Offset 2 + +/** Offset of wIndex in USB request buffer. */ +#define USB_wIndex_Offset 4 + +/** Offset of wLength in USB request buffer. */ +#define USB_wLength_Offset 6 + +/** Get value of bmRequestType from USB request. */ +#define USB_GET_bmRequestType(req) USB_GET_U8((req), USB_bmRequestType_Offset) + +/** Get value of bRequest from USB request. */ +#define USB_GET_bRequest(req) USB_GET_U8((req), USB_bRequest_Offset) + +/** Get value of wValue from USB request. */ +#define USB_GET_wValue(req) USB_GET_U16((req), USB_wValue_Offset) + +/** Get value of wIndex from USB request. */ +#define USB_GET_wIndex(req) USB_GET_U16((req), USB_wIndex_Offset) + +/** Get value of wLength from USB request. */ +#define USB_GET_wLength(req) USB_GET_U16((req), USB_wLength_Offset) + +/** USB request IN indication of bmRequestType. */ +#define USB_REQ_TYPE_IN 0x80u + +/** USB endpoint number mask of bEndpointAddress. */ +#define USB_EP_N_MASK 0x0Fu + +/** USB endpoint direction bit of bEndpointAddress. */ +#define USB_EP_DIR 0x80u + +/** Get USB endpoint direction from endpoint address. */ +#define USB_EP_GET_DIR(ep_addr) ((ep_addr)&USB_EP_DIR) + +/** Get USB endpoint number from endpoint address. */ +#define USB_EP_GET_N(ep_addr) ((ep_addr)&USB_EP_N_MASK) + +/** Transfer type in EP descriptor bmAttributes: Control. */ +#define USB_EP_XTYPE_CTRL 0x0 + +/** Transfer type in EP descriptor bmAttributes: Isochronous. */ +#define USB_EP_XTYPE_ISOCH 0x1 + +/** Transfer type in EP descriptor bmAttributes: Bulk. */ +#define USB_EP_XTYPE_BULK 0x2 + +/** Transfer type in EP descriptor bmAttributes: Interrupt. */ +#define USB_EP_XTYPE_INTERRUPT 0x3 + +/** Transfer type mask in EP descriptor bmAttributes. */ +#define USB_EP_XTYPE_MASK 0x3u + +/*@}*/ + +/** \name USB status codes + *@{ + */ +/** USB operation is done successfully. */ +#define USB_OK 0 +/** USB (endpoint) is busy. */ +#define USB_BUSY 1 +/** USB (endpoint) is halted. */ +#define USB_HALTED 2 + +/** General error. */ +#define USB_ERROR 0x10 +/** Operation is denied by hardware (e.g., syncing). */ +#define USB_ERR_DENIED 0x11 +/** Input parameter error. */ +#define USB_ERR_PARAM 0x12 +/** Functionality is not supported (e.g., initialize endpoint without cache to be control). */ +#define USB_ERR_FUNC 0x13 +/** Re-initialize, re-enable ... */ +#define USB_ERR_REDO 0x14 +/** Not enough resource (memory, endpoints ...). */ +#define USB_ERR_ALLOC_FAIL 0x15 +/*@}*/ + +/** USB speed. */ +enum usb_speed { + /** USB Low Speed. */ + USB_SPEED_LS, + /** USB Full Speed. */ + USB_SPEED_FS, + /** USB High Speed. */ + USB_SPEED_HS, + /** USB Super Speed. */ + USB_SPEED_SS +}; + +/** USB transaction type. */ +enum usb_trans_type { + /** USB SETUP transaction. */ + USB_TRANS_SETUP, + /** USB IN transaction. */ + USB_TRANS_IN, + /** USB OUT transaction. */ + USB_TRANS_OUT +}; + +/** USB events that generates the device callbacks. */ +enum usb_event { + /** USB VBus changed, with parameter as present/not present. */ + USB_EV_VBUS, + /** USB RESET detected on bus. */ + USB_EV_RESET, + /** USB wakeup. */ + USB_EV_WAKEUP, + /** USB LPM suspend, with parameter as \ref usb_lpm_attributes. */ + USB_EV_LPM_SUSPEND, + /** USB suspend. */ + USB_EV_SUSPEND, + /** USB error, with parameter as error code. */ + USB_EV_ERROR, + /** Number of USB event types. */ + USB_EV_N +}; + +/** Control action for USB device endpoint stall. */ +enum usb_ep_stall_ctrl { + /** Clear stall of the endpoint. */ + USB_EP_STALL_CLR, + /** Stall the endpoint. */ + USB_EP_STALL_SET, + /** Return the stall status. */ + USB_EP_STALL_GET +}; + +/** Control action for USB device endpoint halt. */ +enum usb_ep_halt_ctrl { + /** Clear halt of the endpoint. */ + USB_EP_HALT_CLR = USB_EP_STALL_CLR, + /** Stall the endpoint. */ + USB_EP_HALT_SET = USB_EP_STALL_SET, + /** Return the halt status. */ + USB_EP_HALT_GET = USB_EP_STALL_GET +}; + +/** USB transactions status codes. */ +enum usb_trans_code { + /** TX or RX has been done without error. */ + USB_TRANS_DONE, + /** The endpoint is stalled. */ + USB_TRANS_STALL, + /** The endpoint transactions are aborted (cancel, control setup/status). */ + USB_TRANS_ABORT, + /** The endpoint transactions are aborted by reset/disable. */ + USB_TRANS_RESET, + /** Error is reported on the endpoint. */ + USB_TRANS_ERROR +}; + +/** Transfer status codes. */ +enum usb_xfer_code { + /** Transfer is done without error, for ctrl it means status packet done. */ + USB_XFER_DONE, + /** For control transfer only, data stage is done without error. */ + USB_XFER_DATA, + /** Endpoint stall is set. */ + USB_XFER_HALT, + /** Endpoint stall is cleared. */ + USB_XFER_UNHALT, + /** Transfer is aborted. */ + USB_XFER_ABORT, + /** Transfer is aborted because endpoint reset/disable. */ + USB_XFER_RESET, + /** There was an error. */ + USB_XFER_ERROR +}; + +/** USB endpoint errors. */ +enum usb_ep_error { + /** No error. */ + USB_EP_NO_ERROR, + /** CRC error. */ + USB_EP_ERR_CRC, + /** Endpoint transfer overflow. */ + USB_EP_ERR_OVERFLOW, + /** Other endpoint errors. */ + USB_EP_ERR_GENERAL +}; + +/** Endpoint transfer state. */ +enum usb_ep_state { + /** Endpoint is disabled. */ + USB_EP_S_DISABLED, + /** Endpoint is not busy. */ + USB_EP_S_IDLE, + /** Control transfer only, endpoint is transferring setup packet. */ + USB_EP_S_X_SETUP, + /** Endpoint is transferring data. */ + USB_EP_S_X_DATA, + /** Control transfer only, endpoint is in status stage. */ + USB_EP_S_X_STATUS, + /** Endpoint is halted. */ + USB_EP_S_HALTED, + /** Endpoint error. */ + USB_EP_S_ERROR +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USB_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usb_device.h b/atmel-samd/asf4/samd21/hal/include/hpl_usb_device.h new file mode 100644 index 0000000000000..640833f457694 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_usb_device.h @@ -0,0 +1,387 @@ +/** + * \file + * + * \brief SAM USB HPL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USB_DEVICE_H_INCLUDED +#define _HPL_USB_DEVICE_H_INCLUDED + +#include +#include "hpl_usb_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** USB Device callback type. */ +enum usb_d_cb_type { + /** USB device SOF callback. */ + USB_D_CB_SOF, + /** USB device events callbacks. */ + USB_D_CB_EVENT, + /** Number of types of USB device callback types. */ + USB_D_CB_N +}; + +/** USB Device endpoint callback type. */ +enum usb_d_ep_cb_type { + /** USB device endpoint setup callback. */ + USB_D_EP_CB_SETUP, + /** USB device endpoint more data callback. */ + USB_D_EP_CB_MORE, + /** USB device endpoint transaction done or error callback. */ + USB_D_EP_CB_XFER, + /** Number of types of USB device endpoint callback types. */ + USB_D_EP_CB_N +}; + +/** Control action for USB device LPM handshake. */ +enum usb_d_lpm_ctrl { + /** No LPM handshake, not supported. */ + USB_D_LPM_DISABLE, + /** ACK the LPM transaction. */ + USB_D_LPM_ACK, + /** NYET the LPM transaction. */ + USB_D_LPM_NYET +}; + +/** + * USB device transfer descriptor. + */ +struct usb_d_transfer { + /** Pointer to data buffer to transfer. + * Note that it's recommended that the buffer is 32-bit aligned since + * some of USB peripheral require this. + */ + uint8_t *buf; + /** Transfer size, in number of bytes. + * Note that it's recommended that the buffer size is 32-bit aligned + * (modeled by 4) since some of USB peripheral require this. + */ + uint32_t size; + /** Endpoint address. */ + uint8_t ep; + /** Append ZLP for IN transfer, wait ZLP for OUT transfer. */ + uint8_t zlp; +}; + +/** USB device transactions status structure. */ +struct usb_d_trans_status { + /** Total data size. */ + uint32_t size; + /** Total transfered data count. */ + uint32_t count; + /** Endpoint address. */ + uint8_t ep; + /** Endpoint type - CTRL/ISO/INT/BULK. */ + uint8_t xtype : 2; + /** Transactions state, busy or not. */ + uint8_t busy : 1; + /** Transactions state, setup received or not. */ + uint8_t setup : 1; + /** Transactions state, stall or not. */ + uint8_t stall : 1; + /** Transactions direction. */ + uint8_t dir : 1; +}; + +/** Prototype function for callback that is invoked on USB device SOF. */ +typedef void (*_usb_d_dev_sof_cb_t)(void); + +/** Prototype function for callback that is invoked on USB device events. */ +typedef void (*_usb_d_dev_event_cb_t)(const enum usb_event, const uint32_t param); + +/** HPL USB device callbacks. */ +struct _usb_d_dev_callbacks { + /** Callback that is invoked on SOF. */ + _usb_d_dev_sof_cb_t sof; + /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ + _usb_d_dev_event_cb_t event; +}; + +/** USB device endpoint callbacks. */ +enum usb_d_dev_ep_cb_type { + /** Setup packet is received. */ + USB_D_DEV_EP_CB_SETUP, + /** Try to require more data. */ + USB_D_DEV_EP_CB_MORE, + /** Transaction done OK/ERROR. */ + USB_D_DEV_EP_CB_DONE, + /** Number of device endpoint callbacks. */ + USB_D_DEV_EP_CB_N +}; + +/** + * Callback that is invoked when control SETUP packet has bee received. + * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and allow + * IN/OUT transactions on control endpoint. + */ +typedef void (*_usb_d_dev_ep_cb_setup_t)(const uint8_t ep); + +/** Callback that is invoked when buffer is done, but last packet is full size + * packet without ZLP. Return \c true if more data has been requested. */ +typedef bool (*_usb_d_dev_ep_cb_more_t)(const uint8_t ep, const uint32_t transfered); + +/** Callback that is invoked when all data is finished, including background + * transfer, or error happens. */ +typedef void (*_usb_d_dev_ep_cb_done_t)(const uint8_t ep, const int32_t code, const uint32_t transfered); + +/** Callbacks for HPL USB device endpoint. */ +struct _usb_d_dev_ep_callbacks { + /** Callback that is invoked when SETUP packet is received. + * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and + * allow IN/OUT transactions on control endpoint. + */ + _usb_d_dev_ep_cb_setup_t setup; + /** Callback that is invoked to check if buffer is NULL and more data is + * required. + * It's called when last packet is full size packet, without + * auto ZLP enabled. + * It could be called when background transfer is still in progress. + */ + _usb_d_dev_ep_cb_more_t more; + /** Callback that is invoked when transaction is done, including background + * transfer, or error occurs. + */ + _usb_d_dev_ep_cb_done_t done; +}; + +/** + * \brief Initialize the USB device instance + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_init(void); + +/** + * \brief Deinitialize the USB device instance + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +void _usb_d_dev_deinit(void); + +/** + * \brief Register callback to handle USB device events + * \param[in] type Callback type. See \ref usb_d_cb_type. + * \param[in] func Pointer to callback function. + * Refer to \ref _usb_d_dev_callbacks for the prototypes. + */ +void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); + +/** + * \brief Register callback to handle USB device endpoint events + * \param[in] type Callback type. See \ref usb_d_dev_ep_cb_type. + * \param[in] func Pointer to callback function. + * Refer to \ref _usb_d_dev_ep_callbacks for the prototypes. + */ +void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func); + +/** + * \brief Enable the USB device + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_enable(void); + +/** + * \brief Disable the USB device + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_disable(void); + +/** + * \brief Attach the USB device + */ +void _usb_d_dev_attach(void); + +/** + * \brief Detach the USB device + */ +void _usb_d_dev_detach(void); + +/** + * \brief Send the USB device remote wakeup to host + */ +void _usb_d_dev_send_remotewakeup(void); + +/** + * \brief Get the USB device working speed + * \return USB speed. See \ref usb_speed. + */ +enum usb_speed _usb_d_dev_get_speed(void); + +/** + * \brief Set the USB device address + * \param[in] addr Address to be used. + */ +void _usb_d_dev_set_address(const uint8_t addr); + +/** + * \brief Get the USB device address + * \return Address that is used. + */ +uint8_t _usb_d_dev_get_address(void); + +/** + * \brief Get the USB device frame number + * \return The frame number. + */ +uint16_t _usb_d_dev_get_frame_n(void); + +/** + * \brief Get the USB device micro frame number + * \return The micro frame number inside one frame (0~7). + */ +uint8_t _usb_d_dev_get_uframe_n(void); + +/** + * \brief Initialize and enable the USB device default endpoint 0 + * \param[in] max_pkt_siz Max endpoint size. + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz); + +/** + * \brief Initialize and enable the USB device endpoint + * \param[in] ep Endpoint address, + * see endpoint descriptor details in USB spec. + * \param[in] attr Endpoint attributes, + * see endpoint descriptor details in USB spec. + * \param[in] max_pkt_siz Endpoint size, + * see endpoint descriptor details in USB spec. + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, uint16_t max_pkt_siz); + +/** + * \brief Disable and deinitialize the USB device endpoint + + * \param[in] ep The endpoint to deinitialize. + */ +void _usb_d_dev_ep_deinit(const uint8_t ep); + +/** + * \brief Enable the endpoint + * \param[in] ep The endpoint to enable. + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_enable(const uint8_t ep); + +/** + * \brief Disable the endpoint + * \param[in] ep The endpoint to disable. + */ +void _usb_d_dev_ep_disable(const uint8_t ep); + +/** + * \brief Set/Clear/Get USB device endpoint stall status + * \param[in] ep Endpoint address. + * \param[in] ctrl Operation selector. See \ref usb_ep_stall_ctrl. + * \return Operation result or stall status. + * \retval 0 Success or not stall. + * \retval 1 Endpoint is stalled. + * \retval -1 error. + */ +int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl); + +/** + * \brief Read setup request data from specific endpoint + * \param[in] ep Endpoint address. + * \param[out] req_buf Pointer to buffer to locate the setup packet. + * \return Number of bytes or error code. + * \retval <0 error code. + * \retval 0 No setup packet ready for read. + * \retval >0 Size of bytes read, and ready to start IN/OUT. Note that if + * this number is over 8, only first 8 bytes will be copied. + */ +int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf); + +/** + * \brief Start USB device transfer + * + * On different USB peripheral hardware the transaction buffer address and size + * may have different constraints. E.g., some hardware may require input address + * 32-bit aligned, and input size 32-bit aligned. Refer to the corresponding + * hardware usage reference documents. + * The constraints are checked in implementation, with error code returned. + * + * \param[in] trans Pointer to the transaction description. + * \return Operation result status. + * \retval 1 Busy. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans); + +/** + * \brief Abort pending USB device transaction on specific endpoint + * \param[in] ep Endpoint address to abort. + */ +void _usb_d_dev_ep_abort(const uint8_t ep); + +/** + * \brief Retrieve endpoint status. + * \param[in] ep Endpoint address. + * \param[out] stat Pointer to buffer to fill status description. + * \return Status. + * \retval 2 Packet writing. + * \retval 1 Busy. + * \retval 0 Ready. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usb_host.h b/atmel-samd/asf4/samd21/hal/include/hpl_usb_host.h new file mode 100644 index 0000000000000..ee48ecc3a094b --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_usb_host.h @@ -0,0 +1,628 @@ +/** + * \file + * + * \brief SAM USB host HPL + * + * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USB_HOST_H_INCLUDED +#define _HPL_USB_HOST_H_INCLUDED + +#include +#include +#include "hpl_usb_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Driver version */ +#define USB_H_VERSION 0x00000001 + +/** + * @brief USB HCD callback types + */ +enum usb_h_cb_type { + /** SOF generated */ + USB_H_CB_SOF, + /** Root Hub change detected */ + USB_H_CB_ROOTHUB_CHANGE, + /** Number of USB HCD callback types */ + USB_H_CB_N +}; + +/** + * @brief USB HCD resource strategy + */ +enum usb_h_rsc_strategy { + /** Normal resource allocation, e.g., + * 1 bank for interrupt endpoint, + * 2 bank for bulk endpoint and normal iso endpoint, + * 3 bank for iso high bandwidth endpoint. + */ + USB_H_RSC_NORMAL = false, + /** Minimal resource allocation, e.g., only 1 bank for bulk endpoints */ + USB_H_RSC_MINIMAL = true +}; + +/** + * @brief USB HCD pipe states + */ +enum usb_h_pipe_state { + /** Pipe is free to allocate */ + USB_H_PIPE_S_FREE = 0x00, + /** Pipe is in configuration */ + USB_H_PIPE_S_CFG = 0x01, + /** Pipe is allocated and idle */ + USB_H_PIPE_S_IDLE = 0x02, + /** Pipe in control setup stage */ + USB_H_PIPE_S_SETUP = 0x03, + /** Pipe in data IN stage */ + USB_H_PIPE_S_DATI = 0x05, + /** Pipe in data OUT stage */ + USB_H_PIPE_S_DATO = 0x06, + /** Pipe in data IN ZLP stage */ + USB_H_PIPE_S_ZLPI = 0x07, + /** Pipe in data OUT ZLP stage */ + USB_H_PIPE_S_ZLPO = 0x08, + /** Pipe in control status IN stage */ + USB_H_PIPE_S_STATI = 0x09, + /** Pipe in control status OUT stage */ + USB_H_PIPE_S_STATO = 0x0A, + /** Taken by physical pipe (in process) */ + USB_H_PIPE_S_TAKEN = 0x10 +}; + +/** + * @brief USB HCD status code + */ +enum usb_h_status { + /** OK */ + USB_H_OK = ERR_NONE, + /** Busy */ + USB_H_BUSY = ERR_BUSY, + /** Denied */ + USB_H_DENIED = ERR_DENIED, + /** Timeout */ + USB_H_TIMEOUT = ERR_TIMEOUT, + /** Abort */ + USB_H_ABORT = ERR_ABORTED, + /** Stall protocol */ + USB_H_STALL = ERR_PROTOCOL, + /** Transfer reset by pipe re-configure */ + USB_H_RESET = ERR_REQ_FLUSHED, + /** Argument error */ + USB_H_ERR_ARG = ERR_INVALID_ARG, + /** Operation not supported */ + USB_H_ERR_UNSP_OP = ERR_UNSUPPORTED_OP, + /** No resource */ + USB_H_ERR_NO_RSC = ERR_NO_RESOURCE, + /** Not initialized */ + USB_H_ERR_NOT_INIT = ERR_NOT_INITIALIZED, + /** Some general error */ + USB_H_ERR = ERR_IO +}; + +/** Forward declare for pipe structure */ +struct usb_h_pipe; + +/** Forward declare for driver descriptor structure */ +struct usb_h_desc; + +/** + * \brief Prototyping USB HCD callback of SOF + */ +typedef void (*usb_h_cb_sof_t)(struct usb_h_desc *drv); + +/** + * \brief Prototyping USB HCD callback of root hub changing. + * According to the bitmap size, max port number is 31. + */ +typedef void (*usb_h_cb_roothub_t)(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); + +/** + * Prototyping USB HCD callback of pipe transfer done. + * For control pipe, it's forced to call even if there is no transfer + * in progress, since the pipe size could be changed at run time. + */ +typedef void (*usb_h_pipe_cb_xfer_t)(struct usb_h_pipe *pipe); + +/** Access to max packet size of a pipe */ +#define usb_h_pipe_max_pkt_size(p) (p->max_pkt_size) + +/** Access to device address of a pipe */ +#define usb_h_pipe_dev_addr(p) (p->dev) + +/** Access to endpoint address of a pipe */ +#define usb_h_pipe_ep_addr(p) (p->ep) + +/** Access to state of a pipe */ +#define usb_h_pipe_state(p) (p->x.general.state) + +/** Access to status of a pipe */ +#define usb_h_pipe_status(p) (p->x.general.status) + +/** + * @brief USB Host Controller device structure + */ +struct usb_h_desc { + /** Pointer to hardware base */ + void *hw; + /** Pointer to private data for Host Controller driver */ + void *prvt; + /** Interrupt handling descriptor */ + struct _irq_descriptor irq; + /** Callback of SOF */ + usb_h_cb_sof_t sof_cb; + /** Callback of root hub change */ + usb_h_cb_roothub_t rh_cb; +#if CONF_USB_H_INST_OWNER_SP + /** Extension for the driver owner (upper layer user) */ + void *owner; +#endif +}; + +/** + * @brief Transfer descriptor for control transfer + * + * Timing in USB 2.0 spec.: + * - 9.2.6.1 : USB sets an upper limit of 5 seconds as the upper limit for any + * command to be processed. + * - 9.2.6.3 : if a device receives a SetAddress() request, the device must be + * able to complete processing of the request and be able to + * successfully complete the Status stage of the request within + * 50 ms. + * After successful completion of the Status stage, the device is + * allowed a SetAddress() recovery interval of 2 ms. At the end of + * this interval, the device must be able to accept Setup packets + * addressed to the new address. + * - 9.2.6.4 : For standard device requests that require no Data stage, a device + * must be able to complete the request and be able to successfully + * complete the Status stage of the request within 50 ms of receipt + * of the request. This limitation applies to requests to the + * device, interface, or endpoint. + * For standard device requests that require data stage transfer to + * the host, the device must be able to return the first data packet + * to the host within 500 ms of receipt of the request. For + * subsequent data packets, if any, the device must be able to + * return them within 500 ms of successful completion of the + * transmission of the previous packet. The device must then be + * able to successfully complete the status stage within 50 ms after + * returning the last data packet. + * For standard device requests that require a data stage transfer + * to the device, the 5-second limit applies. + * - 9.2.6.5 : Unless specifically exempted in the class document, all + * class-specific requests must meet the timing limitations for + * standard device requests. + * + * Conclusion: + * 1. Whole request with data: 5 seconds + * 2. Whole request without data: 50 ms + * 3. Data packets: 500 ms + */ +struct usb_h_ctrl_xfer { + /** Pointer to transfer data */ + uint8_t *data; + /** Pointer to setup packet */ + uint8_t *setup; + /** Expected transfer size */ + uint16_t size; + /** Transfer count */ + uint16_t count; + /** Timeout for request, -1 if disable timeout */ + int16_t req_timeout; + /** Timeout between packets + * (500ms for data and 50ms for status), -1 if disabled */ + int16_t pkt_timeout; + /** Packet size during transfer (<= allocate max packet size) */ + uint16_t pkt_size; + + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief Transfer descriptor for bulk / interrupt / iso transfer + */ +struct usb_h_bulk_int_iso_xfer { + /** Expected transfer size */ + uint32_t size; + /** Transfer count */ + uint32_t count; + /** Pointer to transfer data */ + uint8_t *data; + /** Reserved */ + uint16_t reserved[3]; + + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief Transfer descriptor for periodic high bandwidth transfer + */ +struct usb_h_high_bw_xfer { + /** Expected transfer size */ + uint32_t size; + /** Transfer count */ + uint32_t count; + /** Pointer to transfer data */ + uint8_t *data; + /** Micro frame packet sizes */ + uint16_t pkt_size[3]; + + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief General transfer descriptor + */ +struct usb_h_xfer { + /** Reserved for different transfer */ + union { + uint16_t u16[9]; + uint8_t u8[18]; + } reserved; + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief USB Host Controller Driver Pipe structure + */ +struct usb_h_pipe { + /** Pointer to the USB Host Controller Driver */ + struct usb_h_desc *hcd; + /** Pointer to the callback for transfer done */ + usb_h_pipe_cb_xfer_t done; +#if CONF_USB_H_INST_OWNER_SP + /** Pointer to the pipe owner */ + void *owner; +#endif + + /** Endpoint max packet size (bits 10..0) */ + uint16_t max_pkt_size; + /** Device address */ + uint8_t dev; + /** Endpoint address */ + uint8_t ep; + + /** Endpoint interval */ + uint8_t interval; + /** Endpoint type: Control, Isochronous, Bulk or Interrupt */ + uint8_t type; + /** Current toggle (driver dependent) */ + uint8_t toggle; + /** Endpoint number of banks (HW dependent) */ + uint8_t bank : 2; + /** Transfer speed (HW dependent) */ + uint8_t speed : 2; + /** High bandwidth periodic out */ + uint8_t high_bw_out : 1; + /** Uses DMA (on transfer) */ + uint8_t dma : 1; + /** Transfer ZLP support */ + uint8_t zlp : 1; + /** Transfer periodic */ + uint8_t periodic_start : 1; + + /** Transfer status */ + union { + /** General transfer info */ + struct usb_h_xfer general; + /** Control transfer status */ + struct usb_h_ctrl_xfer ctrl; + /** Bulk interrupt iso transfer status */ + struct usb_h_bulk_int_iso_xfer bii; + /** Periodic high bandwidth transfer status */ + struct usb_h_high_bw_xfer hbw; + } x; +}; + +/** + * @brief USB HCD Initialization + * + * @param drv Pointer to the HCD driver instance + * @param[in] hw Pointer to hardware base + * @param[in] prvt The private driver data (implement specific) + * + * @return Operation result status + * @retval ERR_DENIED Hardware has been enabled + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_init(struct usb_h_desc *drv, void *hw, void *prvt); + +/** + * @brief USB HCD de-initialization + * + * @param drv The driver + */ +void _usb_h_deinit(struct usb_h_desc *drv); + +/** + * @brief USB HCD enable + * + * @param drv The driver + */ +void _usb_h_enable(struct usb_h_desc *drv); + +/** + * @brief USB HCD disable + * + * @param drv The driver + */ +void _usb_h_disable(struct usb_h_desc *drv); + +/** + * @brief Register callbacks for USB HCD + * + * @param drv The driver + * @param[in] type The callback type + * @param[in] cb The callback function entry + * + * @return Operation result status + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_register_callback(struct usb_h_desc *drv, enum usb_h_cb_type type, FUNC_PTR cb); + +/** + * @brief Return current frame number + * + * @param drv The driver + * + * @return current frame number + */ +uint16_t _usb_h_get_frame_n(struct usb_h_desc *drv); + +/** + * @brief Return current micro frame number + * + * @param drv The driver + * + * @return current micro frame number + */ +uint8_t _usb_h_get_microframe_n(struct usb_h_desc *drv); + +/** + * @brief Suspend the USB bus + * + * @param drv The driver + */ +void _usb_h_suspend(struct usb_h_desc *drv); + +/** + * @brief Resume the USB bus + * + * @param drv The driver + */ +void _usb_h_resume(struct usb_h_desc *drv); + +/* Root hub related APIs */ + +/** + * \brief Reset the root hub port + * + * \param[in,out] drv Pointer to the USB HCD driver + * \param[in] port Root hub port, ignored if there is only one port + */ +void _usb_h_rh_reset(struct usb_h_desc *drv, uint8_t port); + +/** + * \brief Suspend the root hub port + * + * \param[in,out] drv Pointer to the USB HCD driver + * \param[in] port Root hub port, ignored if there is only one port + */ +void _usb_h_rh_suspend(struct usb_h_desc *drv, uint8_t port); + +/** + * \brief Resume the root hub port + * + * \param[in,out] drv Pointer to the USB HCD driver + * \param[in] port Root hub port, ignored if there is only one port + */ +void _usb_h_rh_resume(struct usb_h_desc *drv, uint8_t port); + +/** + * \brief Root hub or port feature status check + * + * Check USB Spec. for hub status and feature selectors. + * + * \param[in] drv Pointer to the USB HCD driver + * \param[in] port Set to 0 to get hub status, otherwise to get port status + * \param[in] ftr Hub feature/status selector + * (0: connection, 2: suspend, 4: reset, 9: LS, 10: HS) + * + * \return \c true if the status bit is 1 + */ +bool _usb_h_rh_check_status(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); + +/* Pipe transfer functions */ + +/** + * @brief Allocate a pipe for USB host communication + * + * @param drv The USB HCD driver + * @param[in] dev The device address + * @param[in] ep The endpoint address + * @param[in] max_pkt_size The endpoint maximum packet size + * @param[in] attr The endpoint attribute + * @param[in] interval The endpoint interval + * (bInterval of USB Endpoint Descriptor) + * @param[in] speed The transfer speed of the endpoint + * @param[in] minimum_rsc Minimum the resource usage, \sa usb_h_rsc_strategy + * + * @return Pointer to allocated pipe structure instance + * @retval NULL allocation fail + */ +struct usb_h_pipe *_usb_h_pipe_allocate(struct usb_h_desc *drv, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, + uint8_t attr, uint8_t interval, uint8_t speed, bool minimum_rsc); + +/** + * @brief Free an allocated pipe + * + * @param pipe The pipe + * + * @return Operation result status + * @retval ERR_BUSY Pipe is busy, use \ref _usb_h_pipe_abort to abort + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_pipe_free(struct usb_h_pipe *pipe); + +/** + * @brief Modify parameters of an allocated control pipe + * + * @param pipe The pipe + * @param[in] dev The device address + * @param[in] ep The endpoint address + * @param[in] max_pkt_size The maximum packet size, must be equal or + * less than allocated size + * @param[in] speed The working speed + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_pipe_set_control_param(struct usb_h_pipe *pipe, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, + uint8_t speed); + +/** + * @brief Register transfer callback on a pipe + * + * @param pipe The pipe + * @param[in] cb Transfer callback function + * + * @return Operation result status + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_pipe_register_callback(struct usb_h_pipe *pipe, usb_h_pipe_cb_xfer_t cb); + +/** + * @brief Issue a control transfer (request) on a pipe + * + * \note When there is data stage, timeout between data packets is 500ms, the + * timeout between last data packet and the status packet is 50ms. + * + * @param pipe The pipe + * @param[in] setup Pointer to the setup packet + * @param[in,out] data Pointer to the data buffer + * @param[in] length The data length + * @param[in] timeout Timeout for whole request in ms + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_control_xfer(struct usb_h_pipe *pipe, uint8_t *setup, uint8_t *data, uint16_t length, int16_t timeout); + +/** + * @brief Issue a bulk / interrupt / iso transfer on a pipe + * + * @param pipe The pipe + * @param[in,out] data Pointer to the data buffer + * @param[in] length The data length + * @param[in] auto_zlp Auto append ZLP for OUT + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is control pipe + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_bulk_int_iso_xfer(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, bool auto_zlp); + +/** + * @brief Issue a periodic high bandwidth output on a pipe + * + * @param pipe The pipe + * @param[in,out] data Pointer to the data buffer + * @param[in] length The data length + * @param[in] trans_pkt_size The transaction packet sizes in a micro frame, + * 0 to use endpoint max packet size + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is not high bandwidth periodic pipe, or + * DMA feature not enabled, or + * high bandwidth not enabled + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_high_bw_out(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, uint16_t trans_pkt_size[3]); + +/** + * @brief Check if pipe is busy transferring + * + * @param pipe The pipe + * + * @return \c true if pipe is busy + */ +bool _usb_h_pipe_is_busy(struct usb_h_pipe *pipe); + +/** + * @brief Abort pending transfer on a pipe + * + * @param pipe The pipe + */ +void _usb_h_pipe_abort(struct usb_h_pipe *pipe); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USB_HOST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_user_area.h b/atmel-samd/asf4/samd21/hal/include/hpl_user_area.h new file mode 100644 index 0000000000000..b5c419bff9115 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/include/hpl_user_area.h @@ -0,0 +1,133 @@ +/** + * \file + * + * \brief Special user data area access + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USER_DATA_H_INCLUDED +#define _HPL_USER_DATA_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Read data from user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * \param[in] base The base address of the user area + * \param[in] offset The byte offset of the data to be read inside the area + * \param[out] buf Pointer to buffer to place the read data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes read. + * \retval ERR_NONE Data read successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, const uint32_t size); + +/** + * \brief Read no more than 32 bits data from user data area + * + * When reading bits, the bitfield can cross 32-bis boundaries. + * + * \param[in] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] n_bits Number of bits to read + * \return data read, assert if anything wrong (address not in user area + * offset, size error, etc.). + */ +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits); + +/** + * \brief Write data to user data area + * + * The user data area could be the area that stores user data that is not erased + * with the flash contents, e.g., + * - NVM Software Calibration Area of SAM D/L/C family + * - User Signature of SAM E/S/V 70 + * + * When assigned offset and size exceeds the data area, error is reported. + * + * \param[out] base The base address of the user area + * \param[in] offset The offset of the data to be written inside the area + * \param[in] buf Pointer to buffer to place the written data + * \param[in] size Size of data in number of bytes + * + * \return Operation status or bytes writting. + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size); + +/** + * \brief Write no more than 32 bits data to user data area + * + * When writting bits, the bitfield can cross 32-bis boundaries. + * + * \param[out] base The base address of the user area + * \param[in] bit_offset Offset in number of bits + * \param[in] bits The data content + * \param[in] n_bits Number of bits to write + * \return Operation result + * \retval ERR_NONE Data written successfully + * \retval ERR_UNSUPPORTED_OP base address not in any supported user area + * \retval ERR_DENIED Security bit is set + * \retval ERR_BAD_ADDRESS offset not in right area + * \retval ERR_INVALID_ARG offset and size exceeds the right area + */ +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USER_DATA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/src/hal_adc_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_adc_sync.c new file mode 100644 index 0000000000000..9c7c3ab528811 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_adc_sync.c @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief ADC functionality implementation. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \brief Indicates HAL being compiled. Must be defined before including. + */ +#define _COMPILING_HAL + +#include "hal_adc_sync.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Maximum amount of ADC interface instances + */ +#define MAX_ADC_AMOUNT ADC_INST_NUM + +/** + * \brief Initialize ADC + */ +int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func) +{ + ASSERT(descr && hw); + + return _adc_sync_init(&descr->device, hw); +} + +/** + * \brief Deinitialize ADC + */ +int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr) +{ + ASSERT(descr); + _adc_sync_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Enable ADC + */ +int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_enable_channel(&descr->device, channel); + + return ERR_NONE; +} + +/** + * \brief Disable ADC + */ +int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_disable_channel(&descr->device, channel); + return ERR_NONE; +} + +/* + * \brief Read data from ADC + */ +int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, + const uint16_t length) +{ + uint8_t data_size; + uint16_t offset = 0; + + ASSERT(descr && buffer && length); + data_size = _adc_sync_get_data_size(&descr->device); + ASSERT(!(length % data_size)); + + do { + uint16_t result; + _adc_sync_convert(&descr->device); + + while (!_adc_sync_is_channel_conversion_done(&descr->device, channel)) + ; + + result = _adc_sync_read_channel_data(&descr->device, channel); + buffer[offset] = result; + if (1 < data_size) { + buffer[offset + 1] = result >> 8; + } + offset += data_size; + } while (offset < length); + + return offset; +} + +/** + * \brief Set ADC reference source + */ +int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference) +{ + ASSERT(descr); + _adc_sync_set_reference_source(&descr->device, reference); + + return ERR_NONE; +} + +/** + * \brief Set ADC resolution + */ +int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution) +{ + ASSERT(descr); + _adc_sync_set_resolution(&descr->device, resolution); + + return ERR_NONE; +} + +/** + * \brief Set ADC input source of a channel + */ +int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel); + + return ERR_NONE; +} + +/** + * \brief Set ADC thresholds + */ +int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + ASSERT(descr); + _adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold); + + return ERR_NONE; +} + +/** + * \brief Set ADC gain + */ +int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain) +{ + ASSERT(descr); + _adc_sync_set_channel_gain(&descr->device, channel, gain); + + return ERR_NONE; +} + +/** + * \brief Set ADC conversion mode + */ +int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode) +{ + ASSERT(descr); + _adc_sync_set_conversion_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set ADC differential mode + */ +int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, + const enum adc_differential_mode mode) +{ + ASSERT(descr); + _adc_sync_set_channel_differential_mode(&descr->device, channel, mode); + + return ERR_NONE; +} + +/** + * \brief Set ADC window mode + */ +int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode) +{ + ASSERT(descr); + _adc_sync_set_window_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Retrieve threshold state + */ +int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state) +{ + ASSERT(descr && state); + _adc_sync_get_threshold_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Check if conversion is complete + */ +int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + return _adc_sync_is_channel_conversion_done(&descr->device, channel); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t adc_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +//@} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_atomic.c b/atmel-samd/asf4/samd21/hal/src/hal_atomic.c new file mode 100644 index 0000000000000..82a11e2bdf580 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_atomic.c @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_dac_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_dac_sync.c new file mode 100644 index 0000000000000..a56e6aef77918 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_dac_sync.c @@ -0,0 +1,141 @@ +/** + * \file + * + * \brief DAC functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_dac_sync.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Initialize the DAC HAL instance and hardware. + */ +int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw) +{ + uint8_t i; + int32_t rc; + + ASSERT(descr && hw); + + rc = _dac_sync_init(&descr->device, hw); + if (rc) { + return rc; + } + + for (i = 0; i < CHANNEL_NUM; i++) { + descr->sel_ch[i].buffer = NULL; + descr->sel_ch[i].length = 0; + } + + return ERR_NONE; +} + +/** + * \brief Deinitialize the DAC HAL instance and hardware + */ +int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr) +{ + ASSERT(descr); + + _dac_sync_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Enable DAC channel + */ +int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) +{ + ASSERT(descr && (ch < CHANNEL_NUM)); + + _dac_sync_enable_channel(&descr->device, ch); + + return ERR_NONE; +} + +/** + * \brief Disable DAC channel + */ +int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) +{ + ASSERT(descr && (ch < CHANNEL_NUM)); + + _dac_sync_disable_channel(&descr->device, ch); + + return ERR_NONE; +} + +/** + * \brief DAC convert digital data to analog output + */ +int32_t dac_sync_write(struct dac_sync_descriptor *descr, const uint8_t ch, uint16_t *buffer, uint32_t length) +{ + ASSERT(descr && (ch < CHANNEL_NUM) && buffer && length); + + /* check whether channel is enable */ + if (!_dac_sync_is_channel_enable(&descr->device, ch)) { + return ERR_NOT_READY; + } + + descr->sel_ch[ch].buffer = buffer; + descr->sel_ch[ch].length = length; + + while (descr->sel_ch[ch].length) { + _dac_sync_write_data(&descr->device, *(descr->sel_ch[ch].buffer), ch); + descr->sel_ch[ch].buffer++; + descr->sel_ch[ch].length--; + } + + return ERR_NONE; +} + +/** + * \brief Get DAC driver version + */ +uint32_t dac_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_delay.c b/atmel-samd/asf4/samd21/hal/src/hal_delay.c new file mode 100644 index 0000000000000..ce963db009e88 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_delay.c @@ -0,0 +1,90 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_flash.c b/atmel-samd/asf4/samd21/hal/src/hal_flash.c new file mode 100644 index 0000000000000..f3cc4bbfe0b03 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_flash.c @@ -0,0 +1,324 @@ +/** + * \file + * + * \brief Flash functionality implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_flash.h" +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static void flash_ready(struct _flash_device *device); +static void flash_error(struct _flash_device *device); + +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr); + +/** + * \brief Initialize the FLASH HAL instance and hardware for callback mode. + */ +int32_t flash_init(struct flash_descriptor *flash, void *const hw) +{ + int32_t rc; + + ASSERT(flash && hw); + + rc = _flash_init(&flash->dev, hw); + if (rc) { + return rc; + } + + flash->dev.flash_cb.ready_cb = flash_ready; + flash->dev.flash_cb.error_cb = flash_error; + + return ERR_NONE; +} + +/** + * \brief Deinitialize the FLASH HAL instance. + */ +int32_t flash_deinit(struct flash_descriptor *flash) +{ + ASSERT(flash); + + _flash_deinit(&flash->dev); + + return ERR_NONE; +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash + */ +int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + _flash_read(&flash->dev, src_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Updates several bytes to the internal Flash + */ +int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_write(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Appends a number of bytes to a page in the internal Flash + */ +int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + ASSERT(flash && buffer && length); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + + /* Check if the address is valid */ + if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { + return ERR_BAD_ADDRESS; + } + + if (_flash_is_locked(&flash->dev, dst_addr)) { + return ERR_DENIED; + } + + _flash_append(&flash->dev, dst_addr, buffer, length); + + return ERR_NONE; +} + +/** + * \brief Execute erase in the internal flash + */ +int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + _flash_erase(&flash->dev, dst_addr, page_nums); + + return ERR_NONE; +} + +/** + * \brief Register a function as FLASH transfer completion callback + */ +int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func) +{ + ASSERT(flash); + + switch (type) { + case FLASH_CB_READY: + flash->callbacks.cb_ready = func; + break; + + case FLASH_CB_ERROR: + flash->callbacks.cb_error = func; + break; + + default: + return ERR_INVALID_ARG; + } + + _flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func); + + return ERR_NONE; +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_lock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) +{ + ASSERT(flash && page_nums); + uint32_t page_size = _flash_get_page_size(&flash->dev); + uint32_t total_pages = _flash_get_total_pages(&flash->dev); + int32_t rc; + + rc = flash_is_address_aligned(flash, dst_addr); + if (rc) { + return rc; + } + + if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { + return ERR_INVALID_ARG; + } + + return _flash_unlock(&flash->dev, dst_addr, page_nums); +} + +/** + * \brief Get the flash page size. + */ +uint32_t flash_get_page_size(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_page_size(&flash->dev); +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t flash_get_total_pages(struct flash_descriptor *flash) +{ + ASSERT(flash); + return _flash_get_total_pages(&flash->dev); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t flash_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal check the address whether it is aligned + * \param[in, out] flash Pointer to the HAL FLASH instance. + * \param[in] flash_addr address to be check in flash + * + * \return whether it is valid + * \retval 0 Valid. + * \retval -1 Error, invalid. + */ +static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr) +{ + ASSERT(flash); + + uint32_t page_size = _flash_get_page_size(&flash->dev); + + /* Check if the read address not aligned to the start of a page */ + if (flash_addr & (page_size - 1)) { + return ERR_BAD_ADDRESS; + } + return ERR_NONE; +} + +/** + * \internal Ready for a new flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_ready(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_ready) { + descr->callbacks.cb_ready(descr); + } +} + +/** + * \internal Error occurs in flash command + * + * \param[in] device The pointer to flash device structure + */ +static void flash_error(struct _flash_device *device) +{ + struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); + if (descr->callbacks.cb_error) { + descr->callbacks.cb_error(descr); + } +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_gpio.c b/atmel-samd/asf4/samd21/hal/src/hal_gpio.c new file mode 100644 index 0000000000000..319726290226c --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_gpio.c @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Port + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c new file mode 100644 index 0000000000000..c72fe2758aec0 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c @@ -0,0 +1,260 @@ +/** + * \file + * + * \brief I/O I2C related functionality implementation. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Sync version of I2C I/O read + */ +static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; +} + +/** + * \brief Sync version of I2C I/O write + */ +static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP; + msg.buffer = (uint8_t *)buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; +} + +/** + * \brief Sync version of i2c initialize + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) +{ + int32_t init_status; + ASSERT(i2c); + + init_status = _i2c_m_sync_init(&i2c->device, hw); + if (init_status) { + return init_status; + } + + /* Init I/O */ + i2c->io.read = i2c_m_sync_read; + i2c->io.write = i2c_m_sync_write; + + return ERR_NONE; +} + +/** + * \brief deinitialize + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) +{ + int32_t status; + ASSERT(i2c); + + status = _i2c_m_sync_deinit(&i2c->device); + if (status) { + return status; + } + + i2c->io.read = NULL; + i2c->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c enable + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_enable(&i2c->device); +} + +/** + * \brief Sync version of i2c disable + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_disable(&i2c->device); +} + +/** + * \brief Sync version of i2c set slave address + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) +{ + return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); +} + +/** + * \brief Sync version of i2c set baudrate + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) +{ + return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); +} + +/** + * \brief Sync version of i2c write command + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c read command + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c transfer command + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) +{ + return _i2c_m_sync_transfer(&i2c->device, msg); +} + +/** + * \brief Sync version of i2c send stop condition command + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) +{ + return _i2c_m_sync_send_stop(&i2c->device); +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) +{ + *io = &i2c->io; + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t i2c_m_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_init.c b/atmel-samd/asf4/samd21/hal/src/hal_init.c new file mode 100644 index 0000000000000..bdcf2a4098541 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_init.c @@ -0,0 +1,57 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_io.c b/atmel-samd/asf4/samd21/hal/src/hal_io.c new file mode 100644 index 0000000000000..52638d9b05768 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_io.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_pwm.c b/atmel-samd/asf4/samd21/hal/src/hal_pwm.c new file mode 100644 index 0000000000000..2b9d2606fd1fe --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_pwm.c @@ -0,0 +1,169 @@ +/** + * \file + * + * \brief PWM functionality implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_pwm.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static void pwm_period_expired(struct _pwm_device *device); +static void pwm_detect_fault(struct _pwm_device *device); + +/** + * \brief Initialize pwm + */ +int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func) +{ + ASSERT(descr && hw); + _pwm_init(&descr->device, hw); + descr->device.callback.pwm_period_cb = pwm_period_expired; + descr->device.callback.pwm_error_cb = pwm_detect_fault; + return ERR_NONE; +} + +/** + * \brief Deinitialize pwm + */ +int32_t pwm_deinit(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + _pwm_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start pwm + */ +int32_t pwm_enable(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + if (_pwm_is_enabled(&descr->device)) { + return ERR_DENIED; + } + _pwm_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop pwm + */ +int32_t pwm_disable(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + if (!_pwm_is_enabled(&descr->device)) { + return ERR_DENIED; + } + _pwm_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Register PWM callback + */ +int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb) +{ + switch (type) { + case PWM_PERIOD_CB: + descr->pwm_cb.period = cb; + break; + + case PWM_ERROR_CB: + descr->pwm_cb.error = cb; + break; + + default: + return ERR_INVALID_ARG; + } + ASSERT(descr); + _pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb); + return ERR_NONE; +} + +/** + * \brief Change PWM parameter + */ +int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle) +{ + ASSERT(descr); + _pwm_set_param(&descr->device, period, duty_cycle); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t pwm_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Process interrupts caused by period experied + */ +static void pwm_period_expired(struct _pwm_device *device) +{ + struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); + + if (descr->pwm_cb.period) { + descr->pwm_cb.period(descr); + } +} + +/** + * \internal Process interrupts caused by pwm fault + */ +static void pwm_detect_fault(struct _pwm_device *device) +{ + struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); + + if (descr->pwm_cb.error) { + descr->pwm_cb.error(descr); + } +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_sleep.c b/atmel-samd/asf4/samd21/hal/src/hal_sleep.c new file mode 100644 index 0000000000000..2d1aadd67e6c2 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_sleep.c @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_spi_m_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_spi_m_sync.c new file mode 100644 index 0000000000000..8ceaa9a4aa60f --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_spi_m_sync.c @@ -0,0 +1,212 @@ +/** + * \file + * + * \brief I/O SPI related functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_spi_m_sync.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Driver version + */ +#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u + +#define SPI_DEACTIVATE_NEXT 0x8000 + +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); +static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); + +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) +{ + int32_t rc = 0; + + ASSERT(spi && hw); + + spi->dev.prvt = (void *)hw; + + rc = _spi_m_sync_init(&spi->dev, hw); + if (rc < 0) { + return rc; + } + + spi->flags = SPI_DEACTIVATE_NEXT; + spi->io.read = _spi_m_sync_io_read; + spi->io.write = _spi_m_sync_io_write; + + return ERR_NONE; +} + +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + + _spi_m_sync_deinit(&spi->dev); +} + +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + + _spi_m_sync_enable(&spi->dev); +} + +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + + _spi_m_sync_disable(&spi->dev); +} + +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) +{ + ASSERT(spi); + + return _spi_m_sync_set_baudrate(&spi->dev, baud_val); +} + +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) +{ + ASSERT(spi); + + return _spi_m_sync_set_mode(&spi->dev, mode); +} + +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) +{ + ASSERT(spi); + + return _spi_m_sync_set_char_size(&spi->dev, char_size); +} + +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) +{ + ASSERT(spi); + + return _spi_m_sync_set_data_order(&spi->dev, dord); +} + +/** \brief Do SPI read in polling way + * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. + * + * It blocks until all data read or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[out] buf Pointer to the buffer to store read data. + * \param[in] size Size of the data in number of characters. + * \return Operation status. + * \retval size Success. + * \retval >=0 Time out, with number of characters read. + */ +static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = buf; + xfer.txbuf = 0; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +/** \brief Do SPI data write in polling way + * For SPI master, activate CS, do buffer send and deactivate CS. The data back + * is discarded. + * + * The data read back is discarded. + * + * It blocks until all data sent or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). + * \return Operation status. + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + */ +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = 0; + xfer.txbuf = (uint8_t *)buf; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) +{ + struct spi_msg msg; + + ASSERT(spi && p_xfer); + + msg.txbuf = p_xfer->txbuf; + msg.rxbuf = p_xfer->rxbuf; + msg.size = p_xfer->size; + + return _spi_m_sync_trans(&spi->dev, &msg); +} + +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) +{ + ASSERT(spi && io); + *io = &spi->io; + return 0; +} + +uint32_t spi_m_sync_get_version(void) +{ + return SPI_M_SYNC_DRIVER_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/atmel-samd/asf4/samd21/hal/src/hal_timer.c b/atmel-samd/asf4/samd21/hal/src/hal_timer.c new file mode 100644 index 0000000000000..08e096a1b7402 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_timer.c @@ -0,0 +1,263 @@ +/** + * \file + * + * \brief Timer functionality implementation. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_timer.h" +#include +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Timer flags + */ +#define TIMER_FLAG_QUEUE_IS_TAKEN 1 +#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 + +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); +static void timer_process_counted(struct _timer_device *device); + +/** + * \brief Initialize timer + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) +{ + ASSERT(descr && hw); + _timer_init(&descr->device, hw); + descr->time = 0; + descr->device.timer_cb.period_expired = timer_process_counted; + + return ERR_NONE; +} + +/** + * \brief Deinitialize timer + */ +int32_t timer_deinit(struct timer_descriptor *const descr) +{ + ASSERT(descr); + _timer_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start timer + */ +int32_t timer_start(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_start(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop timer + */ +int32_t timer_stop(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (!_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_stop(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Set amount of clock cycler per timer tick + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) +{ + ASSERT(descr); + _timer_set_period(&descr->device, clock_cycles); + + return ERR_NONE; +} + +/** + * \brief Add timer task + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_ALREADY_INITIALIZED; + } + task->time_label = descr->time; + timer_add_timer_task(&descr->tasks, task, descr->time); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Remove timer task + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (!is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_NOT_FOUND; + } + list_delete_element(&descr->tasks, task); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Retrieve the amount of clock cycles in a tick + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) +{ + ASSERT(descr && cycles); + *cycles = _timer_get_period(&descr->device); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t timer_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Insert a timer task into sorted timer's list + * + * \param[in] head The pointer to the head of timer task list + * \param[in] task The pointer to task to add + * \param[in] time Current timer time + */ +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) +{ + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + + if (!head) { + list_insert_as_head(list, new_task); + return; + } + + for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { + uint32_t time_left; + + if (it->time_label <= time) { + time_left = it->interval - (time - it->time_label); + } else { + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + } + if (time_left >= new_task->interval) + break; + prev = it; + } + + if (it == head) { + list_insert_as_head(list, new_task); + } else { + list_insert_after(prev, new_task); + } +} + +/** + * \internal Process interrupts + */ +static void timer_process_counted(struct _timer_device *device) +{ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wcast-align" + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); + #pragma GCC diagnostic pop + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; + + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; + return; + } + + while (it && ((time - it->time_label) >= it->interval)) { + struct timer_task *tmp = it; + + list_remove_head(&timer->tasks); + if (TIMER_TASK_REPEAT == tmp->mode) { + tmp->time_label = time; + timer_add_timer_task(&timer->tasks, tmp, time); + } + it = (struct timer_task *)list_get_head(&timer->tasks); + + tmp->cb(tmp); + } +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_usart_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_usart_sync.c new file mode 100644 index 0000000000000..ccc832db85836 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_usart_sync.c @@ -0,0 +1,285 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_sent(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_byte_sent(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_byte_sent(&descr->device)) + ; + } while (++offset < length); + + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c b/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c new file mode 100644 index 0000000000000..f0efd9ff5047c --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c @@ -0,0 +1,602 @@ +/** + * \file + * + * \brief SAM USB device HAL + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_usb_device.h" +#include "hal_atomic.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** USB device HAL driver version. */ +#define USB_D_VERSION 0x00000001u + +/** + * Endpoint callbacks for data transfer. + */ +struct usb_d_ep_callbacks { + /** Callback that is invoked when setup packet is received. */ + usb_d_ep_cb_setup_t req; + /** Callback invoked when buffer is done, but last packet is full size + * packet without ZLP. Return \c true if new transfer has been submitted. + */ + usb_d_ep_cb_more_t more; + /** Callback invoked when transfer is finished/halted/aborted or error + * occurs. + */ + usb_d_ep_cb_xfer_t xfer; +}; + +/** + * Endpoint transfer descriptor header. + */ +struct usb_ep_xfer_hdr { + /** Transfer type, reuse \ref usb_ep_type. */ + uint8_t type; + /** Endpoint address. */ + uint8_t ep; + /** Endpoint state. */ + uint8_t state; + /** Last status code. */ + uint8_t status; +}; + +/** + * Transfer descriptor. + */ +struct usb_ep_xfer { + /** General transfer descriptor. */ + struct usb_ep_xfer_hdr hdr; + /** Pointer to data buffer. */ + uint8_t *buf; + /** Transfer size. */ + uint32_t size; + /** Control request packet. */ + uint8_t req[8]; +}; + +/** + * USB device endpoint descriptor. + */ +struct usb_d_ep { + /** On-going transfer on the endpoint. */ + struct usb_ep_xfer xfer; + /** Endpoint callbacks. */ + struct usb_d_ep_callbacks callbacks; +}; + +/** + * USB device HAL driver descriptor. + */ +struct usb_d_descriptor { + /** USB device endpoints. */ + struct usb_d_ep ep[CONF_USB_D_NUM_EP_SP]; +}; + +/** The USB HAL driver descriptor instance. */ +static struct usb_d_descriptor usb_d_inst; + +/** \brief Find the endpoint. + * \param[in] ep Endpoint address. + * \return Index of endpoint descriptor. + * \retval >=0 The index. + * \retval <0 Not found (endpoint is not initialized). + */ +static int8_t _usb_d_find_ep(const uint8_t ep) +{ + int8_t i; + for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { + if (usb_d_inst.ep[i].xfer.hdr.ep == ep) { + return i; + } + if (usb_d_inst.ep[i].xfer.hdr.type == USB_EP_XTYPE_CTRL + && (ep & USB_EP_N_MASK) == usb_d_inst.ep[i].xfer.hdr.ep) { + return i; + } + } + return -1; +} + +/** + * \brief Start transactions + * \param[in] ep Endpoint address. + * \param[in] dir Endpoint transfer direction. + * \param[in] buf Pointer to transfer buffer. + * \param[in] size Transfer size. + * \param[in] zlp Auto append ZLP for IN, or wait ZLP for OUT. + */ +static inline int32_t _usb_d_trans(const uint8_t ep, const bool dir, const uint8_t *buf, const uint32_t size, + const uint8_t zlp) +{ + struct usb_d_transfer trans + = {(uint8_t *)buf, size, dir ? (uint8_t)(ep | USB_EP_DIR) : (uint8_t)(ep & USB_EP_N_MASK), zlp}; + + return _usb_d_dev_ep_trans(&trans); +} + +/** + * \brief Dummy callback that returns false + * \param[in] unused0 Unused parameter. + * \param[in] unused1 Unused parameter. + * \param[in] unused2 Unused parameter. + * \return Always \c false. + */ +static bool usb_d_dummy_cb_false(uint32_t unused0, uint32_t unused1, uint32_t unused2) +{ + (void)unused0; + (void)unused1; + (void)unused2; + return false; +} + +/** + * \brief Callback invoked when SETUP packet is ready + * \param[in] ep Endpoint number with transfer direction on bit 8. + */ +static void usb_d_cb_trans_setup(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + uint8_t * req = ept->xfer.req; + + uint8_t n = _usb_d_dev_ep_read_req(ep, req); + if (n != 8) { + _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); + _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); + return; + } + + _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); + _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_CLR); + ept->xfer.hdr.state = USB_EP_S_IDLE; + if (!ept->callbacks.req(ep, req)) { + ept->xfer.hdr.state = USB_EP_S_HALTED; + _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); + _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); + } +} + +/** + * \brief Callback invoked when request more data + * \param[in] ep Endpoint number with transfer direction on bit 8. + * \param[in] transfered Number of bytes transfered. + */ +static bool usb_d_cb_trans_more(const uint8_t ep, const uint32_t transfered) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ept->xfer.hdr.state == USB_EP_S_X_DATA) { + return ept->callbacks.more(ep, transfered); + } + return false; +} + +/** + * \brief Handles the case that control endpoint transactions are done + * \param[in,out] ept Pointer to endpoint information. + */ +static inline void usb_d_ctrl_trans_done(struct usb_d_ep *ept) +{ + uint8_t state = ept->xfer.hdr.state; + bool req_dir = USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN; + + if (state == USB_EP_S_X_DATA) { + /* Data stage -> Status stage */ + bool err = ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DATA, ept->xfer.req); + if (err) { + ept->xfer.hdr.state = USB_EP_S_HALTED; + ept->xfer.hdr.status = USB_XFER_HALT; + _usb_d_dev_ep_stall(req_dir ? ept->xfer.hdr.ep : (ept->xfer.hdr.ep | USB_EP_DIR), USB_EP_STALL_SET); + } else { + ept->xfer.hdr.state = USB_EP_S_X_STATUS; + _usb_d_trans(ept->xfer.hdr.ep, !req_dir, NULL, 0, 1); + } + } else { + /* Status stage done */ + ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DONE, ept->xfer.req); + ept->xfer.hdr.state = USB_EP_S_X_SETUP; + } +} + +/** + * Callback when USB transactions are finished. + */ +static void _usb_d_cb_trans_done(const uint8_t ep, const int32_t code, const uint32_t transferred) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + + if (code == USB_TRANS_DONE) { + ept->xfer.hdr.status = USB_XFER_DONE; + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + usb_d_ctrl_trans_done(ept); + return; + } + ept->xfer.hdr.state = USB_EP_S_IDLE; + } else if (code == USB_TRANS_STALL) { + ept->xfer.hdr.status = USB_XFER_HALT; + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + ept->xfer.hdr.state = USB_EP_S_X_SETUP; + _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); + } else { + ept->xfer.hdr.state = USB_EP_S_HALTED; + } + } else if (code == USB_TRANS_ABORT) { + ept->xfer.hdr.status = USB_XFER_ABORT; + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + ept->xfer.hdr.state = USB_EP_S_X_SETUP; + return; + } + ept->xfer.hdr.state = USB_EP_S_IDLE; + } else if (code == USB_TRANS_RESET) { + ept->xfer.hdr.state = USB_EP_S_DISABLED; + ept->xfer.hdr.status = USB_XFER_RESET; + } else { + ept->xfer.hdr.state = USB_EP_S_ERROR; + ept->xfer.hdr.status = USB_XFER_ERROR; + } + + ept->callbacks.xfer(ep, (enum usb_xfer_code)ept->xfer.hdr.status, (void *)transferred); +} + +int32_t usb_d_init(void) +{ + int32_t rc = _usb_d_dev_init(); + uint8_t i; + if (rc < 0) { + return rc; + } + memset(usb_d_inst.ep, 0x00, sizeof(struct usb_d_ep) * CONF_USB_D_NUM_EP_SP); + for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { + usb_d_inst.ep[i].xfer.hdr.ep = 0xFF; + usb_d_inst.ep[i].callbacks.req = (usb_d_ep_cb_setup_t)usb_d_dummy_cb_false; + usb_d_inst.ep[i].callbacks.more = (usb_d_ep_cb_more_t)usb_d_dummy_cb_false; + usb_d_inst.ep[i].callbacks.xfer = (usb_d_ep_cb_xfer_t)usb_d_dummy_cb_false; + } + /* Handles device driver endpoint callbacks to build transfer. */ + _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_SETUP, (FUNC_PTR)usb_d_cb_trans_setup); + _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_MORE, (FUNC_PTR)usb_d_cb_trans_more); + _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_DONE, (FUNC_PTR)_usb_d_cb_trans_done); + return ERR_NONE; +} + +void usb_d_deinit(void) +{ + _usb_d_dev_deinit(); +} + +void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) +{ + /* Directly uses device driver callback. */ + _usb_d_dev_register_callback(type, func); +} + +int32_t usb_d_enable(void) +{ + return _usb_d_dev_enable(); +} + +void usb_d_disable(void) +{ + _usb_d_dev_disable(); +} + +void usb_d_attach(void) +{ + _usb_d_dev_attach(); +} + +void usb_d_detach(void) +{ + _usb_d_dev_detach(); +} + +enum usb_speed usb_d_get_speed(void) +{ + return _usb_d_dev_get_speed(); +} + +uint16_t usb_d_get_frame_num(void) +{ + return _usb_d_dev_get_frame_n(); +} + +uint8_t usb_d_get_uframe_num(void) +{ + return _usb_d_dev_get_uframe_n(); +} + +void usb_d_set_address(const uint8_t addr) +{ + _usb_d_dev_set_address(addr); +} + +void usb_d_send_remotewakeup(void) +{ + _usb_d_dev_send_remotewakeup(); +} + +int32_t usb_d_ep0_init(const uint8_t max_pkt_size) +{ + return usb_d_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_size); +} + +int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size) +{ + int32_t rc; + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index >= 0) { + return -USB_ERR_REDO; + } else { + ep_index = _usb_d_find_ep(0xFF); + if (ep_index < 0) { + return -USB_ERR_ALLOC_FAIL; + } + ept = &usb_d_inst.ep[ep_index]; + } + rc = _usb_d_dev_ep_init(ep, attr, max_pkt_size); + if (rc < 0) { + return rc; + } + ept->xfer.hdr.ep = ep; + ept->xfer.hdr.type = attr & USB_EP_XTYPE_MASK; + return ERR_NONE; +} + +void usb_d_ep_deinit(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index < 0) { + return; + } + _usb_d_dev_ep_deinit(ep); + ept->xfer.hdr.ep = 0xFF; +} + +int32_t usb_d_ep_enable(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + int32_t rc; + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + ept->xfer.hdr.state = (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) ? USB_EP_S_X_SETUP : USB_EP_S_IDLE; + rc = _usb_d_dev_ep_enable(ep); + if (rc < 0) { + ept->xfer.hdr.state = USB_EP_S_DISABLED; + } + return rc; +} + +void usb_d_ep_disable(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index < 0) { + return; + } + _usb_d_dev_ep_disable(ep); + ept->xfer.hdr.state = USB_EP_S_DISABLED; +} + +uint8_t *usb_d_ep_get_req(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + if (ep_index < 0) { + return NULL; + } + return usb_d_inst.ep[ep_index].xfer.req; +} + +int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer) +{ + int8_t ep_index = _usb_d_find_ep(xfer->ep); + struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; + bool dir = USB_EP_GET_DIR(xfer->ep), zlp = xfer->zlp; + uint32_t len = xfer->size; + int32_t rc; + volatile uint8_t state; + volatile hal_atomic_t flags; + + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + + atomic_enter_critical(&flags); + state = ept->xfer.hdr.state; + if (state == USB_EP_S_IDLE) { + ept->xfer.hdr.state = USB_EP_S_X_DATA; + atomic_leave_critical(&flags); + } else { + atomic_leave_critical(&flags); + switch (state) { + case USB_EP_S_HALTED: + return USB_HALTED; + case USB_EP_S_ERROR: + return -USB_ERROR; + case USB_EP_S_DISABLED: + return -USB_ERR_FUNC + 1; + default: /* USB_EP_S_X_xxxx */ + return USB_BUSY; + } + } + + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + uint16_t req_len = USB_GET_wLength(ept->xfer.req); + /* SETUP without data: ZLP IN as status. */ + if (req_len == 0) { + dir = true; + len = 0; + zlp = true; + ept->xfer.hdr.state = USB_EP_S_X_STATUS; + } else { + dir = (USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN); + /* Data length not exceed requested. */ + if (len > req_len) { + len = req_len; + } + if (dir) { + /* Setup -> In */ + zlp = (req_len > len); + } else { + zlp = false; + } + } + } + + rc = _usb_d_trans(xfer->ep, dir, xfer->buf, len, zlp); + return rc; +} + +void usb_d_ep_abort(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index < 0) { + return; + } + _usb_d_dev_ep_abort(ep); + ept->xfer.hdr.state = USB_EP_S_IDLE; + ept->xfer.hdr.status = USB_XFER_ABORT; +} + +int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; + struct usb_d_trans_status tmp; + uint8_t state = ept->xfer.hdr.state; + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + if (stat) { + /* Check transaction status if transferring data. */ + _usb_d_dev_ep_get_status(ep, &tmp); + stat->ep = ep; + stat->state = state; + stat->code = ept->xfer.hdr.status; + stat->count = tmp.count; + stat->size = tmp.size; + } + switch (state) { + case USB_EP_S_IDLE: + return USB_OK; + case USB_EP_S_HALTED: + return USB_HALTED; + case USB_EP_S_ERROR: + return -USB_ERROR; + case USB_EP_S_DISABLED: + return -USB_ERR_FUNC; + default: + /* Busy */ + return USB_BUSY; + } +} + +static inline int32_t _usb_d_ep_halt_clr(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + int32_t rc; + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + if (ept->xfer.hdr.state == USB_EP_S_HALTED) { + rc = _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); + if (rc < 0) { + return rc; + } + ept->xfer.hdr.state = USB_EP_S_IDLE; + ept->xfer.hdr.status = USB_XFER_UNHALT; + ept->callbacks.xfer(ep, USB_XFER_UNHALT, NULL); + } + return ERR_NONE; +} + +int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl) +{ + if (ctrl == USB_EP_HALT_CLR) { + return _usb_d_ep_halt_clr(ep); + } else if (ctrl == USB_EP_HALT_SET) { + return _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); + } else { + return _usb_d_dev_ep_stall(ep, USB_EP_STALL_GET); + } +} + +void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + FUNC_PTR f = func ? (FUNC_PTR)func : (FUNC_PTR)usb_d_dummy_cb_false; + if (ep_index < 0) { + return; + } + switch (type) { + case USB_D_EP_CB_SETUP: + ept->callbacks.req = (usb_d_ep_cb_setup_t)f; + break; + case USB_D_EP_CB_MORE: + ept->callbacks.more = (usb_d_ep_cb_more_t)f; + break; + case USB_D_EP_CB_XFER: + ept->callbacks.xfer = (usb_d_ep_cb_xfer_t)f; + break; + default: + break; + } +} + +uint32_t usb_d_get_version(void) +{ + return USB_D_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/atmel-samd/asf4/samd21/hal/utils/include/compiler.h b/atmel-samd/asf4/samd21/hal/utils/include/compiler.h new file mode 100644 index 0000000000000..3cd654f5372b6 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/compiler.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin +******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/err_codes.h b/atmel-samd/asf4/samd21/hal/utils/include/err_codes.h new file mode 100644 index 0000000000000..ebc80e58b2c38 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/err_codes.h @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/atmel-samd/asf4/samd21/hal/utils/include/events.h b/atmel-samd/asf4/samd21/hal/utils/include/events.h new file mode 100644 index 0000000000000..13c1d62db066b --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/events.h @@ -0,0 +1,64 @@ +/** +* \file +* +* \brief Events declaration. +* +* Copyright (C) 2015 Atmel Corporation. All rights reserved. +* +* \asf_license_start +* +* \page License +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of Atmel may not be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* 4. This software may only be redistributed and used in connection with an +* Atmel microcontroller product. +* +* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +* \asf_license_stop +* +*/ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/parts.h b/atmel-samd/asf4/samd21/hal/utils/include/parts.h new file mode 100644 index 0000000000000..4ba71d65ea32d --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/parts.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "samd21.h" + +#include "hri_d21.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils.h b/atmel-samd/asf4/samd21/hal/utils/include/utils.h new file mode 100644 index 0000000000000..1cc588ad7de61 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils.h @@ -0,0 +1,364 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + (((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) ? 0 : ((u) & (1ul << 30)) ? 1 : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) ? 6 \ + : ((u) & (1ul << 24)) ? 7 : ((u) & (1ul << 23)) ? 8 : ((u) & (1ul << 22)) ? 9 : ((u) & (1ul << 21)) ? 10 : ((u) & (1ul << 20)) ? 11 : (( \ + u) \ + & (1ul \ + << 19)) \ + ? 12 \ + : ((u) \ + & (1ul \ + << 18)) \ + ? 13 \ + : ( \ + (u) \ + & (1ul \ + << 17)) \ + ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) \ + & (1ul \ + << 15)) \ + ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 : ((u) & (1ul << 12)) ? 19 : ((u) & (1ul << 11)) ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) & (1ul << 9)) ? 22 \ + : ((u) & (1ul << 8)) ? 23 : ((u) \ + & (1ul \ + << 7)) \ + ? 24 \ + : ((u) & (1ul << 6)) ? 25 : ((u) & (1ul << 5)) ? 26 : ((u) & (1ul << 4)) ? 27 : ((u) & (1ul << 3)) ? 28 : ((u) \ + & (1ul \ + << 2)) \ + ? 29 \ + : ((u) & (1ul << 1)) ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul \ + << 14) \ + ? 14 \ + : (u) & (1ul \ + << 15) \ + ? 15 \ + : (u) & (1ul << 16) ? 16 : (u) & (1ul << 17) ? 17 : (u) & (1ul << 18) ? 18 : (u) & (1ul << 19) ? 19 : (u) & (1ul << 20) ? 20 : (u) \ + & (1ul \ + << 21) \ + ? 21 \ + : (u) & (1ul << 22) ? 22 : (u) \ + & (1ul << 23) \ + ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 : (u) & (1ul \ + << 27) \ + ? 27 \ + : (u) & (1ul \ + << 28) \ + ? 28 \ + : (u) & (1ul << 29) ? 29 \ + : (u) & (1ul << 30) ? 30 : ( \ + u) & (1ul << 31) \ + ? 31 \ + : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_assert.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_assert.h new file mode 100644 index 0000000000000..ae679e7a35691 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils_assert.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void asf_assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_decrement_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_decrement_macro.h new file mode 100644 index 0000000000000..b53c5da8c73c7 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils_decrement_macro.h @@ -0,0 +1,319 @@ +/** + * \file + * + * \brief Decrement macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_DECREMENT_MACRO_H +#define _UTILS_DECREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time decrement, result value is entire integer literal + * + * \param[in] val - value to be decremented + */ +#define DEC_VALUE(val) DEC_##val + +// Preprocessor increment implementation +#define DEC_256 255 +#define DEC_255 254 +#define DEC_254 253 +#define DEC_253 252 +#define DEC_252 251 +#define DEC_251 250 +#define DEC_250 249 +#define DEC_249 248 +#define DEC_248 247 +#define DEC_247 246 +#define DEC_246 245 +#define DEC_245 244 +#define DEC_244 243 +#define DEC_243 242 +#define DEC_242 241 +#define DEC_241 240 +#define DEC_240 239 +#define DEC_239 238 +#define DEC_238 237 +#define DEC_237 236 +#define DEC_236 235 +#define DEC_235 234 +#define DEC_234 233 +#define DEC_233 232 +#define DEC_232 231 +#define DEC_231 230 +#define DEC_230 229 +#define DEC_229 228 +#define DEC_228 227 +#define DEC_227 226 +#define DEC_226 225 +#define DEC_225 224 +#define DEC_224 223 +#define DEC_223 222 +#define DEC_222 221 +#define DEC_221 220 +#define DEC_220 219 +#define DEC_219 218 +#define DEC_218 217 +#define DEC_217 216 +#define DEC_216 215 +#define DEC_215 214 +#define DEC_214 213 +#define DEC_213 212 +#define DEC_212 211 +#define DEC_211 210 +#define DEC_210 209 +#define DEC_209 208 +#define DEC_208 207 +#define DEC_207 206 +#define DEC_206 205 +#define DEC_205 204 +#define DEC_204 203 +#define DEC_203 202 +#define DEC_202 201 +#define DEC_201 200 +#define DEC_200 199 +#define DEC_199 198 +#define DEC_198 197 +#define DEC_197 196 +#define DEC_196 195 +#define DEC_195 194 +#define DEC_194 193 +#define DEC_193 192 +#define DEC_192 191 +#define DEC_191 190 +#define DEC_190 189 +#define DEC_189 188 +#define DEC_188 187 +#define DEC_187 186 +#define DEC_186 185 +#define DEC_185 184 +#define DEC_184 183 +#define DEC_183 182 +#define DEC_182 181 +#define DEC_181 180 +#define DEC_180 179 +#define DEC_179 178 +#define DEC_178 177 +#define DEC_177 176 +#define DEC_176 175 +#define DEC_175 174 +#define DEC_174 173 +#define DEC_173 172 +#define DEC_172 171 +#define DEC_171 170 +#define DEC_170 169 +#define DEC_169 168 +#define DEC_168 167 +#define DEC_167 166 +#define DEC_166 165 +#define DEC_165 164 +#define DEC_164 163 +#define DEC_163 162 +#define DEC_162 161 +#define DEC_161 160 +#define DEC_160 159 +#define DEC_159 158 +#define DEC_158 157 +#define DEC_157 156 +#define DEC_156 155 +#define DEC_155 154 +#define DEC_154 153 +#define DEC_153 152 +#define DEC_152 151 +#define DEC_151 150 +#define DEC_150 149 +#define DEC_149 148 +#define DEC_148 147 +#define DEC_147 146 +#define DEC_146 145 +#define DEC_145 144 +#define DEC_144 143 +#define DEC_143 142 +#define DEC_142 141 +#define DEC_141 140 +#define DEC_140 139 +#define DEC_139 138 +#define DEC_138 137 +#define DEC_137 136 +#define DEC_136 135 +#define DEC_135 134 +#define DEC_134 133 +#define DEC_133 132 +#define DEC_132 131 +#define DEC_131 130 +#define DEC_130 129 +#define DEC_129 128 +#define DEC_128 127 +#define DEC_127 126 +#define DEC_126 125 +#define DEC_125 124 +#define DEC_124 123 +#define DEC_123 122 +#define DEC_122 121 +#define DEC_121 120 +#define DEC_120 119 +#define DEC_119 118 +#define DEC_118 117 +#define DEC_117 116 +#define DEC_116 115 +#define DEC_115 114 +#define DEC_114 113 +#define DEC_113 112 +#define DEC_112 111 +#define DEC_111 110 +#define DEC_110 109 +#define DEC_109 108 +#define DEC_108 107 +#define DEC_107 106 +#define DEC_106 105 +#define DEC_105 104 +#define DEC_104 103 +#define DEC_103 102 +#define DEC_102 101 +#define DEC_101 100 +#define DEC_100 99 +#define DEC_99 98 +#define DEC_98 97 +#define DEC_97 96 +#define DEC_96 95 +#define DEC_95 94 +#define DEC_94 93 +#define DEC_93 92 +#define DEC_92 91 +#define DEC_91 90 +#define DEC_90 89 +#define DEC_89 88 +#define DEC_88 87 +#define DEC_87 86 +#define DEC_86 85 +#define DEC_85 84 +#define DEC_84 83 +#define DEC_83 82 +#define DEC_82 81 +#define DEC_81 80 +#define DEC_80 79 +#define DEC_79 78 +#define DEC_78 77 +#define DEC_77 76 +#define DEC_76 75 +#define DEC_75 74 +#define DEC_74 73 +#define DEC_73 72 +#define DEC_72 71 +#define DEC_71 70 +#define DEC_70 69 +#define DEC_69 68 +#define DEC_68 67 +#define DEC_67 66 +#define DEC_66 65 +#define DEC_65 64 +#define DEC_64 63 +#define DEC_63 62 +#define DEC_62 61 +#define DEC_61 60 +#define DEC_60 59 +#define DEC_59 58 +#define DEC_58 57 +#define DEC_57 56 +#define DEC_56 55 +#define DEC_55 54 +#define DEC_54 53 +#define DEC_53 52 +#define DEC_52 51 +#define DEC_51 50 +#define DEC_50 49 +#define DEC_49 48 +#define DEC_48 47 +#define DEC_47 46 +#define DEC_46 45 +#define DEC_45 44 +#define DEC_44 43 +#define DEC_43 42 +#define DEC_42 41 +#define DEC_41 40 +#define DEC_40 39 +#define DEC_39 38 +#define DEC_38 37 +#define DEC_37 36 +#define DEC_36 35 +#define DEC_35 34 +#define DEC_34 33 +#define DEC_33 32 +#define DEC_32 31 +#define DEC_31 30 +#define DEC_30 29 +#define DEC_29 28 +#define DEC_28 27 +#define DEC_27 26 +#define DEC_26 25 +#define DEC_25 24 +#define DEC_24 23 +#define DEC_23 22 +#define DEC_22 21 +#define DEC_21 20 +#define DEC_20 19 +#define DEC_19 18 +#define DEC_18 17 +#define DEC_17 16 +#define DEC_16 15 +#define DEC_15 14 +#define DEC_14 13 +#define DEC_13 12 +#define DEC_12 11 +#define DEC_11 10 +#define DEC_10 9 +#define DEC_9 8 +#define DEC_8 7 +#define DEC_7 6 +#define DEC_6 5 +#define DEC_5 4 +#define DEC_4 3 +#define DEC_3 2 +#define DEC_2 1 +#define DEC_1 0 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_DECREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_event.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_event.h new file mode 100644 index 0000000000000..48d9c88d5dc79 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils_event.h @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_increment_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_increment_macro.h new file mode 100644 index 0000000000000..9bbc63ff34a0e --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,318 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_list.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_list.h new file mode 100644 index 0000000000000..8d049ff1bcd29 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils_list.h @@ -0,0 +1,174 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_recursion_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_recursion_macro.h new file mode 100644 index 0000000000000..fcc625cd95a18 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils_recursion_macro.h @@ -0,0 +1,79 @@ +/** + * \file + * + * \brief Recursion macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_RECURSION_MACRO_H +#define _UTILS_RECURSION_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Macro recursion + * + * \param[in] macro Macro to be repeated recursively + * \param[in] arg A recursive threshold, building on this to decline by times + * defined with parameter n + * \param[in] n The number of repetitious calls to macro + */ +#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg) + +#define RECURSION0(macro, arg) +#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0) +#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1) +#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2) +#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3) +#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_RECURSION_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_repeat_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 0000000000000..aeed75d5c3cf6 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,332 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_assert.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_assert.c new file mode 100644 index 0000000000000..9fe56827cc909 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/src/utils_assert.c @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUFDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_event.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_event.c new file mode 100644 index 0000000000000..ab4e9eb3fa5fe --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/src/utils_event.c @@ -0,0 +1,135 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_list.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_list.c new file mode 100644 index 0000000000000..eaf5f3410e1bb --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/src/utils_list.c @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_syscalls.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_syscalls.c new file mode 100644 index 0000000000000..7adad249ab4a5 --- /dev/null +++ b/atmel-samd/asf4/samd21/hal/utils/src/utils_syscalls.c @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/atmel-samd/asf4/samd21/hpl/adc/hpl_adc.c b/atmel-samd/asf4/samd21/hpl/adc/hpl_adc.c new file mode 100644 index 0000000000000..7f2e9fca1b48e --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/adc/hpl_adc.c @@ -0,0 +1,761 @@ +/** + * \file + * + * \brief SAM Analog Digital Converter + * + * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#define ADC_CONFIGURATION(n) \ + { \ + (n), (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ENABLE << ADC_CTRLA_ENABLE_Pos), \ + (CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL), \ + ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM), \ + ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN), \ + ADC_CTRLB_PRESCALER(CONF_ADC_##n##_PRESCALER) | (CONF_ADC_##n##_RESSEL << ADC_CTRLB_RESSEL_Pos) \ + | (CONF_ADC_##n##_CORREN << ADC_CTRLB_CORREN_Pos) | (CONF_ADC_##n##_FREERUN << ADC_CTRLB_FREERUN_Pos) \ + | (CONF_ADC_##n##_LEFTADJ << ADC_CTRLB_LEFTADJ_Pos) \ + | (CONF_ADC_##n##_DIFFMODE << ADC_CTRLB_DIFFMODE_Pos), \ + CONF_ADC_##n##_WINMODE, \ + ADC_INPUTCTRL_GAIN(CONF_ADC_##n##_GAIN) | ADC_INPUTCTRL_INPUTOFFSET(CONF_ADC_##n##_INPUTOFFSET) \ + | ADC_INPUTCTRL_INPUTSCAN(CONF_ADC_##n##_INPUTSCAN) \ + | (CONF_ADC_##n##_MUXNEG << ADC_INPUTCTRL_MUXNEG_Pos) \ + | (CONF_ADC_##n##_MUXPOS << ADC_INPUTCTRL_MUXPOS_Pos), \ + (CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos) \ + | (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos) \ + | (CONF_ADC_##n##_SYNCEI << ADC_EVCTRL_SYNCEI_Pos) \ + | (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos), \ + CONF_ADC_##n##_WINLT, CONF_ADC_##n##_WINUT, ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), \ + ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR), (CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos), \ + } + +/** + * \brief ADC configuration type + */ +struct adc_configuration { + uint8_t number; + hri_adc_ctrla_reg_t ctrl_a; + hri_adc_refctrl_reg_t ref_ctrl; + hri_adc_avgctrl_reg_t avg_ctrl; + hri_adc_sampctrl_reg_t samp_ctrl; + hri_adc_ctrlb_reg_t ctrl_b; + hri_adc_winctrl_reg_t win_ctrl; + hri_adc_inputctrl_reg_t input_ctrl; + hri_adc_evctrl_reg_t ev_ctrl; + hri_adc_winlt_reg_t win_lt; + hri_adc_winut_reg_t win_ut; + hri_adc_gaincorr_reg_t gain_corr; + hri_adc_offsetcorr_reg_t offset_corr; + hri_adc_dbgctrl_reg_t dbg_ctrl; +}; + +#define ADC_AMOUNT (CONF_ADC_0_ENABLE) + +/** + * \brief Array of ADC configurations + */ +static struct adc_configuration _adcs[] = { +#if CONF_ADC_0_ENABLE == 1 + ADC_CONFIGURATION(0), +#endif +}; + +/*!< Pointer to hpl device */ +static struct _adc_async_device *_adc_dev = NULL; + +static void _adc_set_resolution(void *const hw, const adc_resolution_t resolution); +static void _adc_set_conversion_mode(void *const hw, const enum adc_conversion_mode mode); +static void _adc_set_channel_differential_mode(void *const hw, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Retrieve ordinal number of the given adc hardware instance + */ +static uint8_t _adc_get_hardware_index(const void *const hw) +{ + (void)hw; + return 0; +} + +/** \brief Return the pointer to register settings of specific ADC + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific ADC. + */ +static uint8_t _adc_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _adc_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) { + if (_adcs[i].number == n) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device) +{ + (void)device; + return ADC_IRQn; +} + +/** + * \brief Initialize ADC + * + * \param[in] hw The pointer to hardware instance + * \param[in] i The number of hardware instance + */ +static int32_t _adc_init(void *const hw, const uint8_t i) +{ + ASSERT(hw == ADC); + + hri_adc_wait_for_sync(hw); + if (hri_adc_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_adc_set_CTRLA_SWRST_bit(hw); + hri_adc_wait_for_sync(hw); + + hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl); + hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl); + hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl); + hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl); + hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr); + hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr); + hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl); + hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b); + hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl); + hri_adc_write_WINCTRL_reg(hw, _adcs[i].win_ctrl); + hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt); + hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut); + hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a); + + return ERR_NONE; +} + +/** + * \brief De-initialize ADC + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _adc_deinit(void *const hw) +{ + hri_adc_clear_CTRLA_ENABLE_bit(hw); + hri_adc_set_CTRLA_SWRST_bit(hw); +} + +/** + * \brief Initialize ADC + */ +int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _adc_init(hw, _adc_get_regs((uint32_t)hw)); +} + +/** + * \brief Initialize ADC + */ +int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw)); + if (init_status) { + return init_status; + } + device->hw = hw; + _adc_dev = device; + + NVIC_DisableIRQ(ADC_IRQn); + NVIC_ClearPendingIRQ(ADC_IRQn); + NVIC_EnableIRQ(ADC_IRQn); + + return ERR_NONE; +} + +/** + * \brief Initialize ADC + */ +int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _adc_init(hw, _adc_get_regs((uint32_t)hw)); +} + +/** + * \brief De-initialize ADC + */ +void _adc_sync_deinit(struct _adc_sync_device *const device) +{ + _adc_deinit(device->hw); +} + +/** + * \brief De-initialize ADC + */ +void _adc_async_deinit(struct _adc_async_device *const device) +{ + NVIC_DisableIRQ(_adc_get_irq_num(device)); + NVIC_ClearPendingIRQ(_adc_get_irq_num(device)); + + _adc_deinit(device->hw); +} + +/** + * \brief De-initialize ADC + */ +void _adc_dma_deinit(struct _adc_dma_device *const device) +{ + _adc_deinit(device->hw); +} + +/** + * \brief Enable ADC + */ +void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable ADC + */ +void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable ADC + */ +void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable ADC + */ +void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable ADC + */ +void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable ADC + */ +void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Return address of ADC DMA source + */ +uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device) +{ + return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg); +} + +/** + * \brief Retrieve ADC conversion data size + */ +uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device) +{ + return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; +} + +/** + * \brief Retrieve ADC conversion data size + */ +uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device) +{ + return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; +} + +/** + * \brief Retrieve ADC conversion data size + */ +uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device) +{ + return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; +} + +/** + * \brief Check if conversion is done + */ +bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_get_interrupt_RESRDY_bit(device->hw); +} + +/** + * \brief Check if conversion is done + */ +bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_get_interrupt_RESRDY_bit(device->hw); +} + +/** + * \brief Check if conversion is done + */ +bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device) +{ + return hri_adc_get_interrupt_RESRDY_bit(device->hw); +} + +/** + * \brief Make conversion + */ +void _adc_sync_convert(struct _adc_sync_device *const device) +{ + hri_adc_set_SWTRIG_START_bit(device->hw); +} + +/** + * \brief Make conversion + */ +void _adc_async_convert(struct _adc_async_device *const device) +{ + hri_adc_set_SWTRIG_START_bit(device->hw); +} + +/** + * \brief Make conversion + */ +void _adc_dma_convert(struct _adc_dma_device *const device) +{ + hri_adc_set_SWTRIG_START_bit(device->hw); +} + +/** + * \brief Retrieve the conversion result + */ +uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_read_RESULT_reg(device->hw); +} + +/** + * \brief Retrieve the conversion result + */ +uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_read_RESULT_reg(device->hw); +} + +/** + * \brief Set reference source + */ +void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference) +{ + hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference); +} + +/** + * \brief Set reference source + */ +void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference) +{ + hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference); +} + +/** + * \brief Set reference source + */ +void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference) +{ + hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference); +} + +/** + * \brief Set resolution + */ +void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution) +{ + _adc_set_resolution(device->hw, resolution); +} + +/** + * \brief Set resolution + */ +void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution) +{ + _adc_set_resolution(device->hw, resolution); +} + +/** + * \brief Set resolution + */ +void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution) +{ + hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); +} + +/** + * \brief Set channels input sources + */ +void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); + hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); +} + +/** + * \brief Set channels input sources + */ +void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); + hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); +} + +/** + * \brief Set channels input source + */ +void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); + hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); +} + +/** + * \brief Set thresholds + */ +void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + hri_adc_write_WINLT_reg(device->hw, low_threshold); + hri_adc_write_WINUT_reg(device->hw, up_threshold); +} + +/** + * \brief Set threshold + */ +void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + hri_adc_write_WINLT_reg(device->hw, low_threshold); + hri_adc_write_WINUT_reg(device->hw, up_threshold); +} + +/** + * \brief Set thresholds + */ +void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + hri_adc_write_WINLT_reg(device->hw, low_threshold); + hri_adc_write_WINUT_reg(device->hw, up_threshold); +} + +/** + * \brief Set gain + */ +void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain); +} + +/** + * \brief Set gain + */ +void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain); +} + +/** + * \brief Set gain + */ +void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain); +} + +/** + * \brief Set conversion mode + */ +void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode) +{ + _adc_set_conversion_mode(device->hw, mode); +} + +/** + * \brief Set conversion mode + */ +void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode) +{ + _adc_set_conversion_mode(device->hw, mode); +} + +/** + * \brief Set conversion mode + */ +void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode) +{ + _adc_set_conversion_mode(device->hw, mode); +} + +/** + * \brief Set differential mode + */ +void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, + const enum adc_differential_mode mode) +{ + _adc_set_channel_differential_mode(device->hw, channel, mode); +} + +/** + * \brief Set differential mode + */ +void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, + const enum adc_differential_mode mode) +{ + _adc_set_channel_differential_mode(device->hw, channel, mode); +} + +/** + * \brief Set differential mode + */ +void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, + const enum adc_differential_mode mode) +{ + (void)channel; + + _adc_set_channel_differential_mode(device->hw, channel, mode); +} + +/** + * \brief Set window mode + */ +void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode) +{ + hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode); +} + +/** + * \brief Set window mode + */ +void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode) +{ + hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode); +} + +/** + * \brief Set window mode + */ +void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode) +{ + hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode); +} + +/** + * \brief Retrieve threshold state + */ +void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state) +{ + *state = hri_adc_get_interrupt_WINMON_bit(device->hw); +} + +/** + * \brief Retrieve threshold state + */ +void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state) +{ + *state = hri_adc_get_interrupt_WINMON_bit(device->hw); +} + +/** + * \brief Retrieve threshold state + */ +void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state) +{ + *state = hri_adc_get_interrupt_WINMON_bit(device->hw); +} + +/** + * \brief Enable/disable ADC interrupt + * + * param[in] device The pointer to ADC device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, + const enum _adc_async_callback_type type, const bool state) +{ + (void)channel; + + void *const hw = device->hw; + + if (ADC_ASYNC_DEVICE_MONITOR_CB == type) { + hri_adc_write_INTEN_WINMON_bit(hw, state); + } else if (ADC_ASYNC_DEVICE_ERROR_CB == type) { + hri_adc_write_INTEN_OVERRUN_bit(hw, state); + } else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) { + hri_adc_write_INTEN_RESRDY_bit(hw, state); + } +} + +/** + * \brief SetADC resolution + * + * \param[in] hw The pointer to hardware instance + * \param[in] resolution The resolution to set + */ +static void _adc_set_resolution(void *const hw, const adc_resolution_t resolution) +{ + bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); + + hri_adc_clear_CTRLA_ENABLE_bit(hw); + hri_adc_write_CTRLB_RESSEL_bf(hw, resolution); + + if (enabled) { + hri_adc_set_CTRLA_ENABLE_bit(hw); + } +} + +/** + * \brief SetADC resolution + * + * \param[in] hw The pointer to hardware instance + * \param[in] mode The mode to set + */ +static void _adc_set_conversion_mode(void *const hw, const enum adc_conversion_mode mode) +{ + bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); + + hri_adc_clear_CTRLA_ENABLE_bit(hw); + hri_adc_clear_CTRLB_FREERUN_bit(hw); + if (ADC_CONVERSION_MODE_FREERUN == mode) { + hri_adc_set_CTRLB_FREERUN_bit(hw); + } + + if (enabled) { + hri_adc_set_CTRLA_ENABLE_bit(hw); + } +} + +/** + * \brief SetADC resolution + * + * \param[in] hw The pointer to hardware instance + * \param[in] mode The mode to set + */ +static void _adc_set_channel_differential_mode(void *const hw, const uint8_t channel, + const enum adc_differential_mode mode) +{ + (void)channel; + bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); + + hri_adc_clear_CTRLA_ENABLE_bit(hw); + hri_adc_clear_CTRLB_DIFFMODE_bit(hw); + if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { + hri_adc_set_CTRLB_DIFFMODE_bit(hw); + } + + if (enabled) { + hri_adc_set_CTRLA_ENABLE_bit(hw); + } +} diff --git a/atmel-samd/asf4/samd21/hpl/adc/hpl_adc_base.h b/atmel-samd/asf4/samd21/hpl/adc/hpl_adc_base.h new file mode 100644 index 0000000000000..2f9a333c90829 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/adc/hpl_adc_base.h @@ -0,0 +1,82 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_ADC_H_INCLUDED +#define _HPL_ADC_ADC_H_INCLUDED + +#include +#include + +/** + * \addtogroup HPL ADC + * + * \section hpl_adc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve ADC helper functions + * + * \return A pointer to set of ADC helper functions + */ +void *_adc_get_adc_sync(void); +void *_adc_get_adc_async(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_UART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/core/hpl_core_m0plus_base.c b/atmel-samd/asf4/samd21/hpl/core/hpl_core_m0plus_base.c new file mode 100644 index 0000000000000..8b2ecbff36ade --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/core/hpl_core_m0plus_base.c @@ -0,0 +1,210 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (us * (freq / 100000) - 1) / 10 + 1; + case 7: + return (us * (freq / 10000) - 1) / 100 + 1; + case 6: + return (us * (freq / 1000) - 1) / 1000 + 1; + case 5: + return (us * (freq / 100) - 1) / 10000 + 1; + case 4: + return (us * (freq / 10) - 1) / 100000 + 1; + default: + return (us * freq - 1) / 1000000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 8: + return (ms * (freq / 100000)) * 100; + case 7: + return (ms * (freq / 10000)) * 10; + case 6: + return (ms * (freq / 1000)); + case 5: + return (ms * (freq / 100) - 1) / 10 + 1; + case 4: + return (ms * (freq / 10) - 1) / 100 + 1; + default: + return (ms * freq - 1) / 1000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} diff --git a/atmel-samd/asf4/samd21/hpl/core/hpl_core_port.h b/atmel-samd/asf4/samd21/hpl/core/hpl_core_port.h new file mode 100644 index 0000000000000..b068af8397c49 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/core/hpl_core_port.h @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (C) 2015 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/core/hpl_init.c b/atmel-samd/asf4/samd21/hpl/core/hpl_init.c new file mode 100644 index 0000000000000..e567b5d2273a3 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/core/hpl_init.c @@ -0,0 +1,69 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _pm_init(); + _sysctrl_init_sources(); + _gclk_init_generators(); + _sysctrl_init_referenced_generators(); + +#if CONF_DMAC_ENABLE + _pm_enable_bus_clock(PM_BUS_AHB, DMAC); + _pm_enable_bus_clock(PM_BUS_APBB, DMAC); + _dma_init(); +#endif +} diff --git a/atmel-samd/asf4/samd21/hpl/dac/hpl_dac.c b/atmel-samd/asf4/samd21/hpl/dac/hpl_dac.c new file mode 100644 index 0000000000000..2896b0eeec635 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/dac/hpl_dac.c @@ -0,0 +1,248 @@ + +/** +* \file +* +* \brief SAM Digital to Analog Converter +* +* Copyright (C) 2016 -2017 Atmel Corporation. All rights reserved. +* +* \asf_license_start +* +* \page License +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of Atmel may not be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* 4. This software may only be redistributed and used in connection with an +* Atmel microcontroller product. +* +* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +* \asf_license_stop +* +*/ + +#include +#include +#include +#include + +/** \conf INTERNAL */ +static int32_t _dac_init(void *const hw); +static inline void _dac_deinit(void *const hw); +/** \endcond */ + +/** + * \brief DAC configuration type + */ +struct dac_configuration { + hri_dac_ctrla_reg_t ctrla; /*!< Control A Register */ + hri_dac_ctrlb_reg_t ctrlb; /*!< Control B Register */ + hri_dac_evctrl_reg_t ev_ctrl; /*!< Event Control Register */ +}; + +/** + * \brief Array of DAC configurations + */ +static struct dac_configuration _dac = { + (CONF_DAC_RUNSTDBY << DAC_CTRLA_RUNSTDBY_Pos), + (CONF_DAC_REFSEL << DAC_CTRLB_REFSEL_Pos) | (CONF_DAC_BDWP << DAC_CTRLB_BDWP_Pos) + | (CONF_DAC_VPD << DAC_CTRLB_VPD_Pos) + | (CONF_DAC_LEFTADJ << DAC_CTRLB_LEFTADJ_Pos) + | (CONF_DAC_IOEN << DAC_CTRLB_IOEN_Pos) + | (CONF_DAC_EOEN << DAC_CTRLB_EOEN_Pos), + (CONF_DAC_EMPTYEO << DAC_EVCTRL_EMPTYEO_Pos) | (CONF_DAC_STARTEI << DAC_EVCTRL_STARTEI_Pos), +}; + +/*!< Pointer to hpl device */ +static struct _dac_async_device *_dac_dev = NULL; + +/** + * \brief Initialize synchronous DAC + */ +int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _dac_init(device->hw); +} + +/** + * \brief Initialize DAC + * + * param[in] hw The pointer to DAC hardware instance + */ +static int32_t _dac_init(void *const hw) +{ + hri_dac_wait_for_sync(hw); + + if (hri_dac_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_dac_set_CTRLA_SWRST_bit(hw); + hri_dac_wait_for_sync(hw); + + hri_dac_write_EVCTRL_reg(hw, _dac.ev_ctrl); + hri_dac_write_CTRLB_reg(hw, _dac.ctrlb); + hri_dac_write_CTRLA_reg(hw, _dac.ctrla); + return ERR_NONE; +} + +/** + * \brief De-initialize DAC + * + * param[in] hw The pointer to DAC hardware instance + */ +static inline void _dac_deinit(void *const hw) +{ + hri_dac_clear_CTRLA_ENABLE_bit(hw); + hri_dac_set_CTRLA_SWRST_bit(hw); +} + +/** + * \brief Initialize DAC + */ +int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _dac_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + + _dac_dev = device; + NVIC_DisableIRQ(DAC_IRQn); + NVIC_ClearPendingIRQ(DAC_IRQn); + NVIC_EnableIRQ(DAC_IRQn); + + return ERR_NONE; +} + +/** + * \brief De-initialize DAC + */ +void _dac_sync_deinit(struct _dac_sync_device *const device) +{ + _dac_deinit(device->hw); +} + +/** + * \brief De-initialize DAC + */ +void _dac_async_deinit(struct _dac_async_device *const device) +{ + NVIC_DisableIRQ(DAC_IRQn); + + _dac_deinit(device->hw); +} + +/** + * \brief Enable DAC Channel + */ +void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch) +{ + (void)ch; + hri_dac_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable DAC Channel + */ +void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch) +{ + (void)ch; + hri_dac_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable DAC Channel + */ +void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch) +{ + (void)ch; + hri_dac_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable DAC Channel + */ +void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch) +{ + (void)ch; + hri_dac_clear_CTRLA_ENABLE_bit(device->hw); +} + +bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch) +{ + (void)ch; + return hri_dac_get_CTRLA_ENABLE_bit(device->hw); +} + +bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch) +{ + (void)ch; + return hri_dac_get_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief write synchronous DAC data for output + */ +void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch) +{ + (void)ch; + hri_dac_write_DATA_reg(device->hw, data); +} + +/** + * \brief write DAC data for output + */ +void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch) +{ + (void)ch; + hri_dac_write_DATABUF_reg(device->hw, data); +} + +/** + * \brief Enable/disable DAC interrupt + * + * param[in] device The pointer to DAC device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, + const bool state) +{ + void *hw = device->hw; + + if (DAC_DEVICE_CONVERSION_DONE_CB == type) { + hri_dac_write_INTEN_EMPTY_bit(hw, state); + } else if (DAC_DEVICE_ERROR_CB == type) { + hri_dac_write_INTEN_UNDERRUN_bit(hw, state); + } +} diff --git a/atmel-samd/asf4/samd21/hpl/dmac/hpl_dmac.c b/atmel-samd/asf4/samd21/hpl/dmac/hpl_dmac.c new file mode 100644 index 0000000000000..5af9abaf37150 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/dmac/hpl_dmac.c @@ -0,0 +1,226 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE + +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +static DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +static DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ + DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ + | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) \ + | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ + | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) \ + | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) \ + | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) \ + | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint8_t ctrla; + uint32_t ctrlb; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i = 0; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); + hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_PRICTRL0_reg(DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) + | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) + | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) + | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHID_reg(DMAC, i); + + hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + } + + NVIC_DisableIRQ(DMAC_IRQn); + NVIC_ClearPendingIRQ(DMAC_IRQn); + NVIC_EnableIRQ(DMAC_IRQn); + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmac_write_CHID_reg(DMAC, channel); + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +/** + * \internal DMAC interrupt handler + */ +void DMAC_Handler(void) +{ + uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); + struct _dma_resource *tmp_resource = &_resources[channel]; + + hri_dmac_write_CHID_reg(DMAC, channel); + + if (hri_dmac_get_CHINTFLAG_TERR_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); + tmp_resource->dma_cb.error(tmp_resource); + } else if (hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk.c b/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk.c new file mode 100644 index 0000000000000..1012da0a2752d --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk.c @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Generic Clock Controller v210 related functionality. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + + */ +void _gclk_init_generators(void) +{ +#if CONF_GCLK_GEN_0_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_0_DIV) | GCLK_GENDIV_ID(0)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_0_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_0_SRC + | GCLK_GENCTRL_ID(0)); +#endif +#if CONF_GCLK_GEN_1_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_1_DIV) | GCLK_GENDIV_ID(1)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_1_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_1_SRC + | GCLK_GENCTRL_ID(1)); +#endif +#if CONF_GCLK_GEN_2_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_2_DIV) | GCLK_GENDIV_ID(2)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_2_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_2_SRC + | GCLK_GENCTRL_ID(2)); +#endif +#if CONF_GCLK_GEN_3_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_3_DIV) | GCLK_GENDIV_ID(3)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_3_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_3_SRC + | GCLK_GENCTRL_ID(3)); +#endif +#if CONF_GCLK_GEN_4_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_4_DIV) | GCLK_GENDIV_ID(4)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_4_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_4_SRC + | GCLK_GENCTRL_ID(4)); +#endif +#if CONF_GCLK_GEN_5_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_5_DIV) | GCLK_GENDIV_ID(5)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_5_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_5_SRC + | GCLK_GENCTRL_ID(5)); +#endif +#if CONF_GCLK_GEN_6_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_6_DIV) | GCLK_GENDIV_ID(6)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_6_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_6_SRC + | GCLK_GENCTRL_ID(6)); +#endif +#if CONF_GCLK_GEN_7_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_7_DIV) | GCLK_GENDIV_ID(7)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_7_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_7_SRC + | GCLK_GENCTRL_ID(7)); +#endif +#if defined(CONF_GCLK_GEN_8_GENEN) && CONF_GCLK_GEN_8_GENEN == 1 + hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_8_DIV) | GCLK_GENDIV_ID(8)); + hri_gclk_write_GENCTRL_reg(GCLK, + (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_8_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_8_SRC + | GCLK_GENCTRL_ID(8)); +#endif +} diff --git a/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk_base.h b/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 0000000000000..6451647f56136 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,91 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_CLKCTRL_reg(GCLK, + GCLK_CLKCTRL_ID(channel) | GCLK_CLKCTRL_GEN(source) | (1 << GCLK_CLKCTRL_CLKEN_Pos)); +} + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/nvmctrl/hpl_nvmctrl.c b/atmel-samd/asf4/samd21/hpl/nvmctrl/hpl_nvmctrl.c new file mode 100644 index 0000000000000..2c9131a1a89e5 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/nvmctrl/hpl_nvmctrl.c @@ -0,0 +1,684 @@ + +/** +* \file +* +* \brief Non-Volatile Memory Controller +* +* Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. +* +* \asf_license_start +* +* \page License +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of Atmel may not be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* 4. This software may only be redistributed and used in connection with an +* Atmel microcontroller product. +* +* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +* \asf_license_stop +* +*/ + +#include +#include +#include +#include +#include +#include + +#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR) + +/** + * \brief NVM configuration type + */ +struct nvm_configuration { + hri_nvmctrl_ctrlb_reg_t ctrlb; /*!< Control B Register */ +}; + +/** + * \brief Array of NVM configurations + */ +static struct nvm_configuration _nvm + = {(CONF_NVM_CACHE << NVMCTRL_CTRLB_CACHEDIS_Pos) | (CONF_NVM_READ_MODE << NVMCTRL_CTRLB_READMODE_Pos) + | (CONF_NVM_SLEEPPRM << NVMCTRL_CTRLB_SLEEPPRM_Pos)}; + +/*!< Pointer to hpl device */ +static struct _flash_device *_nvm_dev = NULL; + +static void _flash_erase_row(void *const hw, const uint32_t dst_addr); +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size); + +/** + * \brief Initialize NVM + */ +int32_t _flash_init(struct _flash_device *const device, void *const hw) +{ + ASSERT(device && (hw == NVMCTRL)); + uint32_t ctrlb; + + device->hw = hw; + ctrlb = _nvm.ctrlb & ~(NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); + ctrlb |= hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); + hri_nvmctrl_write_CTRLB_reg(device->hw, ctrlb); + + _nvm_dev = device; + NVIC_DisableIRQ(NVMCTRL_IRQn); + NVIC_ClearPendingIRQ(NVMCTRL_IRQn); + NVIC_EnableIRQ(NVMCTRL_IRQn); + return ERR_NONE; +} + +/** + * \brief De-initialize NVM + */ +void _flash_deinit(struct _flash_device *const device) +{ + device->hw = NULL; + NVIC_DisableIRQ(NVMCTRL_IRQn); +} + +/** + * \brief Get the flash page size. + */ +uint32_t _flash_get_page_size(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)NVMCTRL_PAGE_SIZE; +} + +/** + * \brief Get the numbers of flash page. + */ +uint32_t _flash_get_total_pages(struct _flash_device *const device) +{ + (void)device; + return (uint32_t)FLASH_NB_OF_PAGES; +} + +/** + * \brief Get the number of wait states for read and write operations. + */ +uint8_t _flash_get_wait_state(struct _flash_device *const device) +{ + return hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk); +} + +/** + * \brief Set the number of wait states for read and write operations. + */ +void _flash_set_wait_state(struct _flash_device *const device, uint8_t state) +{ + hri_nvmctrl_write_CTRLB_RWS_bf(device->hw, state); +} + +/** + * \brief Reads a number of bytes to a page in the internal Flash. + */ +void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) +{ + uint32_t nvm_address = src_addr / 2; + uint32_t i; + uint16_t data; + + /* Check if the module is busy */ + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + /* Check whether byte address is word-aligned*/ + if (src_addr % 2) { + data = NVM_MEMORY[nvm_address++]; + buffer[0] = data >> 8; + i = 1; + } else { + i = 0; + } + + /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy + * to ensure alignment */ + while (i < length) { + data = NVM_MEMORY[nvm_address++]; + buffer[i] = (data & 0xFF); + if (i < (length - 1)) { + buffer[i + 1] = (data >> 8); + } + i += 2; + } +} + +/** + * \brief Writes a number of bytes to a page in the internal Flash. + */ +void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr, row_end_addr; + uint32_t i, j, k; + uint32_t wr_start_addr = dst_addr; + + do { + row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; + + /* store the erase data into temp buffer before write */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + + /* temp buffer update */ + j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; + k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; + while ((wr_start_addr <= row_end_addr) && (length > 0)) { + tmp_buffer[j][k] = *buffer; + k = (k + 1) % NVMCTRL_PAGE_SIZE; + if (0 == k) { + j++; + } + wr_start_addr++; + buffer++; + length--; + } + + /* erase row before write */ + _flash_erase_row(device->hw, row_start_addr); + + /* write buffer to flash */ + for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { + _flash_program(device->hw, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); + } + + } while (row_end_addr < (wr_start_addr + length - 1)); +} + +/** + * \brief Appends a number of bytes in the internal Flash. + */ +void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) +{ + uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); + uint32_t size; + uint32_t offset = 0; + + if (dst_addr != page_start_addr) { + /* Need to write some data to the end of a page */ + size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr)); + _flash_program(device->hw, dst_addr, buffer, size); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } + + while (offset < length) { + size = min(length - offset, NVMCTRL_PAGE_SIZE); + _flash_program(device->hw, page_start_addr, buffer + offset, size); + page_start_addr += NVMCTRL_PAGE_SIZE; + offset += size; + } +} + +/** + * \brief Execute erase in the internal flash + */ +void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums) +{ + uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE]; + uint32_t row_start_addr; + uint32_t i; + + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE); + + /* when address is not aligned with row start address */ + if (dst_addr != row_start_addr) { + row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; + for (i = 0; i < NVMCTRL_ROW_PAGES - 1; i++) { + _flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + if (--page_nums == 0) { + return; + } + dst_addr += NVMCTRL_PAGE_SIZE; + if (dst_addr == row_start_addr) { + break; + } + } + } + + while (page_nums >= NVMCTRL_ROW_PAGES) { + _flash_erase_row(device->hw, row_start_addr); + row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; + page_nums -= NVMCTRL_ROW_PAGES; + } + + if (page_nums != 0) { + for (i = 0; i < page_nums; i++) { + _flash_write(device, row_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); + row_start_addr += NVMCTRL_PAGE_SIZE; + } + } +} + +/** + * \brief Execute lock in the internal flash + */ +int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t row_start_addr; + + region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_LR | NVMCTRL_CTRLA_CMDEX_KEY); + + return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief Execute unlock in the internal flash + */ +int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) +{ + uint32_t region_pages; + uint32_t row_start_addr; + + region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); + row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); + + if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { + return ERR_INVALID_ARG; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); + + hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_UR | NVMCTRL_CTRLA_CMDEX_KEY); + + return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); +} + +/** + * \brief check whether the region which is pointed by address + */ +bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr) +{ + uint16_t region_id; + + /* Get region for given page */ + region_id = dst_addr / (NVMCTRL_FLASH_SIZE / 16); + + return !(hri_nvmctrl_get_LOCK_reg(device->hw, 1 << region_id)); +} + +/** + * \brief Enable/disable Flash interrupt + */ +void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state) +{ + ASSERT(device); + + if (FLASH_DEVICE_CB_READY == type) { + hri_nvmctrl_write_INTEN_READY_bit(device->hw, state); + } else if (FLASH_DEVICE_CB_ERROR == type) { + hri_nvmctrl_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal erase a row in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to erase + */ +static void _flash_erase_row(void *const hw, const uint32_t dst_addr) +{ + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + + /* Set address and command */ + hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY); +} + +/** + * \internal write a page in flash + * \param[in] hw The pointer to hardware instance + * \param[in] dst_addr Destination page address to write + * \param[in] buffer Pointer to buffer where the data to + * write is stored + * \param[in] size The size of data to write to a page + */ +static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size) +{ + ASSERT(!(dst_addr % 2)); + + uint32_t nvm_address = dst_addr / 2; + uint16_t i, data; + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + /* Clear flags */ + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + + for (i = 0; i < size; i += 2) { + data = buffer[i]; + if (i < NVMCTRL_PAGE_SIZE - 1) { + data |= (buffer[i + 1] << 8); + } + NVM_MEMORY[nvm_address++] = data; + } + + while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { + /* Wait until this module isn't busy */ + } + + hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WP | NVMCTRL_CTRLA_CMDEX_KEY); +} + +/** + * \internal NVM interrupt handler + */ +void NVMCTRL_Handler(void) +{ + void *const hw = _nvm_dev->hw; + + if (hri_nvmctrl_get_interrupt_READY_bit(hw)) { + hri_nvmctrl_clear_interrupt_READY_bit(hw); + if (NULL != _nvm_dev->flash_cb.ready_cb) { + _nvm_dev->flash_cb.ready_cb(_nvm_dev); + } + } else if (hri_nvmctrl_get_interrupt_ERROR_bit(hw)) { + hri_nvmctrl_clear_interrupt_ERROR_bit(hw); + if (NULL != _nvm_dev->flash_cb.error_cb) { + _nvm_dev->flash_cb.error_cb(_nvm_dev); + } + } +} + +/* +The NVM User Row contains calibration data that are automatically read at device +power on. +The NVM User Row can be read at address 0x804000. +*/ +#ifndef _NVM_USER_ROW_BASE +#define _NVM_USER_ROW_BASE 0x804000 +#endif +#define _NVM_USER_ROW_N_BITS 64 +#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8) +#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1) +#define _IS_NVM_USER_ROW(b) \ + (((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END))) +#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END)) + +/* +The NVM Software Calibration Area can be read at address 0x806020. +The NVM Software Calibration Area can not be written. +*/ +#ifndef _NVM_SW_CALIB_AREA_BASE +#define _NVM_SW_CALIB_AREA_BASE 0x806020 +#endif +#define _NVM_SW_CALIB_AREA_N_BITS 128 +#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8) +#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1) +#define _IS_NVM_SW_CALIB_AREA(b) \ + (((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END)) +#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END)) + +/** + * \internal Read left aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return base[bit_offset >> 5] & ((1 << n_bits) - 1); +} + +/** + * \internal Read right aligned data bits + * \param[in] base Base address for the data + * \param[in] bit_offset Offset for the bitfield start + * \param[in] n_bits Number of bits in the bitfield + */ +static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset, + const uint8_t n_bits) +{ + return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1); +} + +int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size) +{ + ASSERT(buf); + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } + /* Cut off if request too many bytes */ + if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + if (!_IN_NVM_SW_CALIB_AREA(base, offset)) { + return ERR_BAD_ADDRESS; + } + /* Cut off if request too many bytes */ + if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Copy data */ + memcpy(buf, ((uint8_t *)base) + offset, size); + return ERR_NONE; +} + +uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits) +{ + volatile uint32_t *mem_base = (volatile uint32_t *)base; + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)); + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3) + && _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3)); + } else { + ASSERT(false); + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are read from 32-bit aligned address + * and then combined together. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + return _user_area_read_r32_bits(mem_base, bit_offset, l_bits) + + (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits); +} + +/** \internal Write 64-bit user row + * \param[in] _row Pointer to 64-bit user row data. + */ +static int32_t _user_row_write_exec(const uint32_t *_row) +{ + Nvmctrl *hw = NVMCTRL; + uint32_t ctrlb = hri_nvmctrl_read_CTRLB_reg(NVMCTRL); + + /* Denie if Security Bit is set */ + if (hri_nvmctrl_get_STATUS_reg(hw, NVMCTRL_STATUS_SB)) { + return ERR_DENIED; + } + + /* Do Save */ + + /* - Prepare. */ + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); + hri_nvmctrl_set_CTRLB_MANW_bit(hw); + + /* - Erase AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_EAR | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + + /* - Page buffer clear & write. */ + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = _row[0]; + *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = _row[1]; + + /* - Write AUX row. */ + hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); + hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WAP | NVMCTRL_CTRLA_CMDEX_KEY); + while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { + /* Wait until this module isn't busy */ + } + + /* Restore CTRLB */ + hri_nvmctrl_write_CTRLB_reg(NVMCTRL, ctrlb); + + return ERR_NONE; +} + +int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size) +{ + uint32_t _row[2]; /* Copy of user row. */ + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, offset)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + memcpy(_row, base, 8); /* Store previous data. */ + memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */ + + return _user_row_write_exec(_row); +} + +int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits) +{ + uint32_t _row[2]; /* Copy of user row. */ + uint32_t l_off, l_bits; + uint32_t r_off, r_bits; + + /** Parameter check. */ + if (_IS_NVM_USER_ROW(base)) { + if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) { + return ERR_BAD_ADDRESS; + } else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) { + return ERR_INVALID_ARG; + } + } else if (_IS_NVM_SW_CALIB_AREA(base)) { + return ERR_DENIED; + } else { + return ERR_UNSUPPORTED_OP; + } + + /* Since the bitfield can cross 32-bits boundaries, + * left and right bits are splitted for 32-bit aligned address + * and then saved. */ + l_off = bit_offset & (~(32 - 1)); + r_off = l_off + 32; + l_bits = 32 - (bit_offset & (32 - 1)); + if (n_bits > l_bits) { + r_bits = n_bits - l_bits; + } else { + l_bits = n_bits; + r_bits = 0; + } + + memcpy(_row, base, 8); /* Store previous data. */ + if (l_bits) { + uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1)); + _row[bit_offset >> 5] &= ~l_mask; + _row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask; + } + if (r_bits) { + uint32_t r_mask = (1 << r_bits) - 1; + _row[r_off >> 5] &= ~r_mask; + _row[r_off >> 5] |= bits >> l_bits; + } + return _user_row_write_exec(_row); +} diff --git a/atmel-samd/asf4/samd21/hpl/pm/hpl_pm.c b/atmel-samd/asf4/samd21/hpl/pm/hpl_pm.c new file mode 100644 index 0000000000000..2df1169d0193c --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/pm/hpl_pm.c @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include + +/** + * \brief Retrieve the reset reason + */ +enum reset_reason _get_reset_reason(void) +{ + return (enum reset_reason)hri_pm_read_RCAUSE_reg(PM); +} + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 0: + case 1: + case 2: + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + PM->SLEEP.reg = mode; + return ERR_NONE; + case 3: + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + return ERR_NONE; + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Power Manager Init + */ +void _pm_init(void) +{ + hri_pm_set_CPUSEL_CPUDIV_bf(PM, CONF_CPU_DIV); + hri_pm_set_APBASEL_APBADIV_bf(PM, CONF_APBA_DIV); + hri_pm_set_APBBSEL_APBBDIV_bf(PM, CONF_APBB_DIV); + hri_pm_set_APBCSEL_APBCDIV_bf(PM, CONF_APBC_DIV); +} diff --git a/atmel-samd/asf4/samd21/hpl/pm/hpl_pm_base.h b/atmel-samd/asf4/samd21/hpl/pm/hpl_pm_base.h new file mode 100644 index 0000000000000..3f308b4269a39 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/pm/hpl_pm_base.h @@ -0,0 +1,213 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distributionn. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \addtogroup pm_group PM Low Level Driver Helpers + * + * \section pm_helpers_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \brief Power Manager buses + */ +enum _pm_bus { PM_BUS_AHB, PM_BUS_APBA, PM_BUS_APBB, PM_BUS_APBC }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve AHB index + * + * \param[in] module Module to get index for + * + * \return index of the given module if succeeds, ERR_INVALID_ARG otherwise + */ +static inline int32_t _pm_get_ahb_index(const void *const module) +{ + if ((uint32_t)module == (uint32_t)PM_BUS_APBA) { + return 0; + } else if ((uint32_t)module == (uint32_t)PM_BUS_APBB) { + return 1; + } else if ((uint32_t)module == (uint32_t)PM_BUS_APBC) { + return 2; + } + if ((uint32_t)module == (uint32_t)DSU) { + return 3; + } else if ((uint32_t)module == (uint32_t)NVMCTRL) { + return 4; + } else if ((uint32_t)module == (uint32_t)DMAC) { + return 5; + } +#ifdef USB + else if ((uint32_t)module == (uint32_t)USB) { + return 6; + } +#endif + + return ERR_INVALID_ARG; +} + +/** + * \brief Retrieve APBB index + * + * \param[in] module Module to get index for + * + * \return index of the given module if succeeds, ERR_INVALID_ARG otherwise + */ +static inline int32_t _pm_get_apbb_index(const void *const module) +{ + if ((uint32_t)module == (uint32_t)PAC1) { + return 0; + } else if ((uint32_t)module == (uint32_t)DSU) { + return 1; + } else if ((uint32_t)module == (uint32_t)NVMCTRL) { + return 2; + } + if ((uint32_t)module == (uint32_t)PORT) { + return 3; + } else if ((uint32_t)module == (uint32_t)DMAC) { + return 4; + } +#ifdef USB + else if ((uint32_t)module == (uint32_t)USB) { + return 5; + } +#endif + + return ERR_INVALID_ARG; +} + +/** + * \brief Enable clock on the given bus for the given hardware module + * + * This function enables clock on the given bus for the given hardware module. + * For an overview of available buses and hardware modules see datasheet. + * + * \param[in] bus A bus to enable clock on + * \param[in] module A hardware module to enable clock for + */ +static inline void _pm_enable_bus_clock(const enum _pm_bus bus, const void *const module) +{ + uint32_t peripheral = ((uint32_t)module & 0x0000ff00) >> 10; + + switch (bus) { + case PM_BUS_AHB: + if (_pm_get_ahb_index(module) >= 0) { + peripheral = (uint32_t)_pm_get_ahb_index(module); + PM->AHBMASK.reg |= 1 << peripheral; + } + break; + case PM_BUS_APBA: + PM->APBAMASK.reg |= 1 << peripheral; + break; + case PM_BUS_APBB: + if (_pm_get_apbb_index(module) >= 0) { + peripheral = (uint32_t)_pm_get_apbb_index(module); + PM->APBBMASK.reg |= 1 << peripheral; + } + break; + case PM_BUS_APBC: + PM->APBCMASK.reg |= 1 << peripheral; + break; + default: + ASSERT(false); + break; + } +} + +/** + * \brief Disable clock on the given bus for the given hardware module + * + * This function disables clock on the given bus for the given hardware module. + * For an overview of available buses and hardware modules see datasheet. + * + * \param[in] bus A bus to disable clock on + * \param[in] module A hardware module to disable clock for + */ +static inline void _pm_disable_bus_clock(const enum _pm_bus bus, const void *const module) +{ + uint32_t peripheral = ((uint32_t)module & 0x0000ff00) >> 10; + + switch (bus) { + case PM_BUS_AHB: + if (_pm_get_ahb_index(module) >= 0) { + peripheral = (uint32_t)_pm_get_ahb_index(module); + PM->AHBMASK.reg &= ~(1 << peripheral); + } + break; + case PM_BUS_APBA: + PM->APBAMASK.reg &= ~(1 << peripheral); + break; + case PM_BUS_APBB: + if (_pm_get_apbb_index(module) >= 0) { + peripheral = (uint32_t)_pm_get_apbb_index(module); + PM->APBBMASK.reg &= ~(1 << peripheral); + } + break; + case PM_BUS_APBC: + PM->APBCMASK.reg &= ~(1 << peripheral); + break; + default: + ASSERT(false); + break; + } +} + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/port/hpl_gpio_base.h b/atmel-samd/asf4/samd21/hpl/port/hpl_gpio_base.h new file mode 100644 index 0000000000000..6ff4dcaa98f36 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/port/hpl_gpio_base.h @@ -0,0 +1,172 @@ +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT_IOBUS, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT_IOBUS, port, mask); + } else { + hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} diff --git a/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc.c b/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc.c new file mode 100644 index 0000000000000..80fca2b5bd377 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc.c @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief RTC Driver (Calendar Mode) + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hpl_calendar.h" +#include "hpl_timer.h" +#include +#include + +/*!< Pointer to hpl device */ + +static struct _timer_device *_rtc_dev = NULL; + +/** + * \brief Initialize Timer + */ +int32_t _timer_init(struct _timer_device *const dev, void *const hw) +{ + ASSERT(dev); + + uint16_t register_value; + dev->hw = hw; + + hri_rtcmode0_write_CTRL_reg(dev->hw, RTC_MODE0_CTRL_SWRST); + hri_rtcmode0_wait_for_sync(dev->hw); + + /* Set mode 0 */ + register_value = RTC_MODE0_CTRL_MODE(0); + + /* Set prescaler */ + register_value |= RTC_MODE0_CTRL_PRESCALER(CONF_RTC_PRESCALER); + + /* clear counter on compare/timer match */ + register_value |= RTC_MODE0_CTRL_MATCHCLR; + + hri_rtcmode0_write_CTRL_reg(dev->hw, register_value); + + hri_rtcmode0_write_COMP_COMP_bf(dev->hw, 0, CONF_RTC_COMP_VAL); + hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw); + +/* set event control */ +#if CONF_RTC_EVENT_CONTROL_ENABLE == 1 + hri_rtcmode0_write_EVCTRL_reg(dev->hw, + (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos) + | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos) + | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos) + | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos) + | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) + | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos) + | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) + | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos) + | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) + | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos)); +#endif + + _rtc_dev = dev; + + return ERR_NONE; +} + +/** + * \brief De-initialize Timer + */ +void _timer_deinit(struct _timer_device *const dev) +{ + ASSERT(dev && dev->hw); + + NVIC_DisableIRQ(RTC_IRQn); + + hri_rtcmode0_write_CTRL_reg(dev->hw, RTC_MODE0_CTRL_SWRST); +} + +/** + * \brief Start hardware timer + */ +void _timer_start(struct _timer_device *const dev) +{ + ASSERT(dev && dev->hw); + + NVIC_EnableIRQ(RTC_IRQn); + hri_rtcmode0_write_COUNT_COUNT_bf(dev->hw, 0); + hri_rtcmode0_wait_for_sync(dev->hw); + hri_rtcmode0_set_CTRL_ENABLE_bit(dev->hw); +} + +/** + * \brief Stop hardware timer + */ +void _timer_stop(struct _timer_device *const dev) +{ + ASSERT(dev && dev->hw); + + hri_rtcmode0_clear_CTRL_ENABLE_bit(dev->hw); +} + +/** + * \brief Set timer period + */ +void _timer_set_period(struct _timer_device *const dev, const uint32_t clock_cycles) +{ + hri_rtcmode0_write_COMP_COMP_bf(dev->hw, 0, clock_cycles); +} + +/** + * \brief Retrieve timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const dev) +{ + return hri_rtcmode0_read_COMP_COMP_bf(dev->hw, 0); +} + +/** + * \brief Check if timer is running + */ +bool _timer_is_started(const struct _timer_device *const dev) +{ + return hri_rtcmode0_get_CTRL_ENABLE_bit(dev->hw); +} + +/** + * \brief Set timer IRQ + */ +void _timer_set_irq(struct _timer_device *const dev) +{ + (void)dev; +} + +/** + * \brief RTC Timer interrupt handler + * + * \param[in] p The pointer to calendar device struct + */ +static void _rtc_timer_interrupt_handler(struct _timer_device *dev) +{ + /* Read and mask interrupt flag register */ + uint16_t flag = hri_rtcmode0_read_INTFLAG_reg(dev->hw); + + if (flag & RTC_MODE0_INTFLAG_CMP0) { + if (dev->timer_cb.period_expired) { + dev->timer_cb.period_expired(dev); + } + + /* Clear interrupt flag */ + hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw); + } +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_rtc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Rtc interrupt handler + */ +void RTC_Handler(void) +{ + _rtc_timer_interrupt_handler(_rtc_dev); +} diff --git a/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc_base.h b/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc_base.h new file mode 100644 index 0000000000000..bbcf242b9a078 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc_base.h @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief RTC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distributionn. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HPL_RTC2_V200_H_INCLUDED +#define _HPL_RTC2_V200_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_rtc_get_timer(void); + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_RTC2_V200_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c b/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c new file mode 100644 index 0000000000000..baec8a2b4ca9b --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c @@ -0,0 +1,2897 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE \ + + CONF_SERCOM_5_USART_ENABLE \ + + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ +#ifdef _UNIT_TEST_ + return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); +#endif + +#if defined __SAML21E18B__ || defined __ATSAML21E18B__ || defined __SAML21G18B__ || defined __ATSAML21G18B__ \ + || defined __SAML21J18B__ || defined __ATSAML21J18B__ || defined __ATSAMR30G18A__ || defined __ATSAMR30E18A__ + if ((uint32_t)SERCOM5 == (uint32_t)hw) { + return 5; + } +#endif + + return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + if (hri_sercomusart_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomusart_set_CTRLA_SWRST_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + +/* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE \ + + CONF_SERCOM_5_I2CM_ENABLE \ + + CONF_SERCOM_6_I2CM_ENABLE \ + + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline void _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_IRQn + _sercom_get_hardware_index(hw); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline void _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + /* Check if module is enabled. */ + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomi2cm_set_CTRLA_SWRST_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + +/* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE \ + + CONF_SERCOM_5_I2CS_ENABLE \ + + CONF_SERCOM_6_I2CS_ENABLE \ + + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); + if (hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + +/* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + ((CONF_SERCOM_##n##_SPI_DORD) | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) \ + | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE \ + + CONF_SERCOM_5_SPI_ENABLE \ + + CONF_SERCOM_6_SPI_ENABLE \ + + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + NVIC_EnableIRQ(_sercom_get_irq_num(hw)); + NVIC_EnableIRQ(_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + NVIC_DisableIRQ(_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + if (hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_ss_detect(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_ss_detect(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_COMPLETE == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} diff --git a/atmel-samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c b/atmel-samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c new file mode 100644 index 0000000000000..fb01560827d94 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c @@ -0,0 +1,265 @@ +/** + * \file + * + * \brief SAM System Controller. + * + * Copyright (C) 2015 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes clock generators + * + * All GCLK generators are running when this function returns. + */ +void _sysctrl_init_sources(void) +{ + void * hw = (void *)SYSCTRL; + uint16_t calib; + +#if CONF_XOSC32K_CONFIG == 1 + hri_sysctrl_write_XOSC32K_reg(hw, + (CONF_XOSC32K_WRTLOCK << SYSCTRL_XOSC32K_WRTLOCK_Pos) + | SYSCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) + | (CONF_XOSC32K_RUNSTDBY << SYSCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_AAMPEN << SYSCTRL_XOSC32K_AAMPEN_Pos) + | (CONF_XOSC32K_EN1K << SYSCTRL_XOSC32K_EN1K_Pos) + | (CONF_XOSC32K_EN32K << SYSCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << SYSCTRL_XOSC32K_XTALEN_Pos) + | (CONF_XOSC32K_ENABLE << SYSCTRL_XOSC32K_ENABLE_Pos)); +#endif + +#if CONF_XOSC_CONFIG == 1 + hri_sysctrl_write_XOSC_reg(hw, + SYSCTRL_XOSC_STARTUP(CONF_XOSC_STARTUP) | (CONF_XOSC_AMPGC << SYSCTRL_XOSC_AMPGC_Pos) + | SYSCTRL_XOSC_GAIN(CONF_XOSC_GAIN) + | (CONF_XOSC_RUNSTDBY << SYSCTRL_XOSC_RUNSTDBY_Pos) + | (CONF_XOSC_XTALEN << SYSCTRL_XOSC_XTALEN_Pos) + | (CONF_XOSC_ENABLE << SYSCTRL_XOSC_ENABLE_Pos)); +#endif + +#if CONF_OSC8M_CONFIG == 1 + calib = hri_sysctrl_read_OSC8M_CALIB_bf(hw); + + hri_sysctrl_write_OSC8M_reg(hw, + SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) | +#if CONF_OSC8M_OVERWRITE_CALIBRATION == 1 + SYSCTRL_OSC8M_CALIB(CONF_OSC8M_CALIB) | +#else + SYSCTRL_OSC8M_CALIB(calib) | +#endif + SYSCTRL_OSC8M_PRESC(CONF_OSC8M_PRESC) + | (CONF_OSC8M_RUNSTDBY << SYSCTRL_OSC8M_RUNSTDBY_Pos) + | (CONF_OSC8M_ENABLE << SYSCTRL_OSC8M_ENABLE_Pos)); +#endif + +#if CONF_OSC32K_CONFIG == 1 + /* OSC32K calibration value at bit 44:38 of memory 0x00806020 */ + calib = (*((uint32_t *)0x00806024) & 0x0001FC0) >> 6; + + hri_sysctrl_write_OSC32K_reg(hw, +#if CONF_OSC32K_OVERWRITE_CALIBRATION == 1 + SYSCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) | +#else + SYSCTRL_OSC32K_CALIB(calib) | +#endif + (CONF_OSC32K_WRTLOCK << SYSCTRL_OSC32K_WRTLOCK_Pos) + | SYSCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP) + | (CONF_OSC32K_RUNSTDBY << SYSCTRL_OSC32K_RUNSTDBY_Pos) + | (CONF_OSC32K_EN1K << SYSCTRL_OSC32K_EN1K_Pos) + | (CONF_OSC32K_EN32K << SYSCTRL_OSC32K_EN32K_Pos) + | (1 << SYSCTRL_OSC32K_ENABLE_Pos)); +#else + /* Enable OSC32K anyway since GCLK configuration may need it to sync */ + hri_sysctrl_set_OSC32K_ENABLE_bit(hw); +#endif + +#if CONF_OSCULP32K_CONFIG == 1 + hri_sysctrl_write_OSCULP32K_reg(hw, +#if CONF_OSC32K_OVERWRITE_CALIBRATION == 1 + SYSCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) | +#else + SYSCTRL_OSCULP32K_CALIB(calib) | +#endif + (CONF_OSC32K_WRTLOCK << SYSCTRL_OSCULP32K_WRTLOCK_Pos)); +#endif + +#if CONF_XOSC32K_CONFIG == 1 +#if CONF_XOSC32K_ENABLE == 1 + while (!hri_sysctrl_get_PCLKSR_XOSC32KRDY_bit(hw)) + ; +#endif +#if CONF_XOSC32K_ONDEMAND == 1 + hri_sysctrl_set_XOSC32K_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_XOSC_CONFIG == 1 +#if CONF_XOSC_ENABLE == 1 + while (!hri_sysctrl_get_PCLKSR_XOSCRDY_bit(hw)) + ; +#endif +#if CONF_XOSC_ONDEMAND == 1 + hri_sysctrl_set_XOSC_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_OSC32K_CONFIG == 1 +#if CONF_OSC32K_ENABLE == 1 + while (!hri_sysctrl_get_PCLKSR_OSC32KRDY_bit(hw)) + ; +#endif +#if CONF_OSC32K_ONDEMAND == 1 + hri_sysctrl_set_OSC32K_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_OSC8M_CONFIG == 1 +#if CONF_OSC8M_ENABLE == 1 + while (!hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(hw)) + ; +#endif +#if CONF_OSC8M_ONDEMAND == 1 + hri_sysctrl_set_OSC8M_ONDEMAND_bit(hw); +#endif +#endif + + (void)calib, (void)hw; +} + +void _sysctrl_init_referenced_generators(void) +{ + void *hw = (void *)SYSCTRL; + +#if CONF_DFLL_CONFIG == 1 + +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != CONF_DFLL_OPEN_LOOP_MODE + hri_gclk_write_CLKCTRL_reg(GCLK, + GCLK_CLKCTRL_ID(0) | GCLK_CLKCTRL_GEN(CONF_DFLL_GCLK) | (1 << GCLK_CLKCTRL_CLKEN_Pos)); +#endif + + hri_sysctrl_write_DFLLCTRL_reg(hw, SYSCTRL_DFLLCTRL_ENABLE); + while (!hri_sysctrl_get_PCLKSR_DFLLRDY_bit(hw)) + ; + + hri_sysctrl_write_DFLLMUL_reg(hw, + SYSCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | SYSCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | SYSCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + hri_sysctrl_write_DFLLVAL_reg(hw, CONF_DFLLVAL); + + hri_sysctrl_dfllctrl_reg_t tmp = + + (CONF_DFLL_WAITLOCK << SYSCTRL_DFLLCTRL_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << SYSCTRL_DFLLCTRL_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << SYSCTRL_DFLLCTRL_QLDIS_Pos) | (CONF_DFLL_CCDIS << SYSCTRL_DFLLCTRL_CCDIS_Pos) + | (CONF_DFLL_RUNSTDBY << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos) | (CONF_DFLL_USBCRM << SYSCTRL_DFLLCTRL_USBCRM_Pos) + | (CONF_DFLL_LLAW << SYSCTRL_DFLLCTRL_LLAW_Pos) | (CONF_DFLL_STABLE << SYSCTRL_DFLLCTRL_STABLE_Pos) + | (CONF_DFLL_MODE << SYSCTRL_DFLLCTRL_MODE_Pos) | (CONF_DFLL_ENABLE << SYSCTRL_DFLLCTRL_ENABLE_Pos); + + hri_sysctrl_write_DFLLCTRL_reg(hw, tmp); +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_REFCLK == SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val + hri_gclk_write_CLKCTRL_reg(GCLK, + GCLK_CLKCTRL_ID(1) | GCLK_CLKCTRL_GEN(CONF_DPLL_GCLK) | (1 << GCLK_CLKCTRL_CLKEN_Pos)); +#endif + + hri_sysctrl_write_DPLLCTRLA_reg(hw, + (CONF_DPLL_RUNSTDBY << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_DPLL_ENABLE << SYSCTRL_DPLLCTRLA_ENABLE_Pos)); + hri_sysctrl_write_DPLLRATIO_reg( + hw, SYSCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | SYSCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); + hri_sysctrl_write_DPLLCTRLB_reg(hw, + SYSCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) + | (CONF_DPLL_LBYPASS << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) + | SYSCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) + | SYSCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) + | (CONF_DPLL_WUF << SYSCTRL_DPLLCTRLB_WUF_Pos) + | (CONF_DPLL_LPEN << SYSCTRL_DPLLCTRLB_LPEN_Pos) + | SYSCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); +#endif + +#if CONF_DFLL_CONFIG == 1 +#if CONF_DFLL_ENABLE == 1 + if (hri_sysctrl_get_DFLLCTRL_MODE_bit(hw)) { + +#if CONF_DFLL_USBCRM == 0 + hri_sysctrl_pclksr_reg_t status_mask + = SYSCTRL_PCLKSR_DFLLRDY | SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC; +#else + hri_sysctrl_pclksr_reg_t status_mask = SYSCTRL_PCLKSR_DFLLRDY; +#endif + + while (hri_sysctrl_get_PCLKSR_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_sysctrl_get_PCLKSR_DFLLRDY_bit(hw)) + ; + } +#endif +#if CONF_DFLL_ONDEMAND == 1 + hri_sysctrl_set_DFLLCTRL_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DPLL_CONFIG == 1 +#if CONF_DPLL_ENABLE == 1 + while (!(hri_sysctrl_get_DPLLSTATUS_ENABLE_bit(hw) || hri_sysctrl_get_DPLLSTATUS_LOCK_bit(hw) + || hri_sysctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) + ; +#endif +#if CONF_DPLL_ONDEMAND == 1 + hri_sysctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_get_STATUS_SYNCBUSY_bit(GCLK)) + ; +#endif + +#if CONF_OSC32K_CONFIG == 0 || CONF_OSC32K_ENABLE == 0 + /* Disable after all possible configurations needs sync written. */ + hri_sysctrl_clear_OSC32K_ENABLE_bit(hw); +#endif + + (void)hw; +} diff --git a/atmel-samd/asf4/samd21/hpl/systick/hpl_systick.c b/atmel-samd/asf4/samd21/hpl/systick/hpl_systick.c new file mode 100644 index 0000000000000..783f306e063df --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/systick/hpl_systick.c @@ -0,0 +1,113 @@ + +/** + * \file + * + * \brief SysTick related functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize system time module + */ +void _system_time_init(void *const hw) +{ + (void)hw; + SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); + SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) + | (1 << SysTick_CTRL_CLKSOURCE_Pos); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + _system_time_init(hw); +} + +/** + * \brief De-initialize system time module + */ +void _system_time_deinit(void *const hw) +{ + (void)hw; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +/** + * \brief Get system time + */ +system_time_t _system_time_get(const void *const hw) +{ + (void)hw; + return (system_time_t)SysTick->VAL; +} + +/** + * \brief Get maximum possible system time + */ +system_time_t _system_time_get_max_time_value(const void *const hw) +{ + (void)hw; + return 0xFFFFFF; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ + (void)hw; + uint8_t n = cycles >> 24; + uint32_t buf = cycles; + + while (n--) { + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0xFFFFFF; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; + buf -= 0xFFFFFF; + } + + SysTick->LOAD = buf; + SysTick->VAL = buf; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; +} diff --git a/atmel-samd/asf4/samd21/hpl/tc/hpl_tc.c b/atmel-samd/asf4/samd21/hpl/tc/hpl_tc.c new file mode 100644 index 0000000000000..9344729da8004 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/tc/hpl_tc.c @@ -0,0 +1,369 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 0 +#endif +#ifndef CONF_TC4_ENABLE +#define CONF_TC4_ENABLE 0 +#endif +#ifndef CONF_TC5_ENABLE +#define CONF_TC5_ENABLE 0 +#endif +#ifndef CONF_TC6_ENABLE +#define CONF_TC6_ENABLE 0 +#endif +#ifndef CONF_TC7_ENABLE +#define CONF_TC7_ENABLE 0 +#endif + +/** + * \brief TC IRQ base index + */ +#define TC_IRQ_BASE_INDEX ((uint8_t)TC3_IRQn) + +/** + * \brief TC base address + */ +#define TC_HW_BASE_ADDR ((uint32_t)TC3) + +/** + * \brief TC number offset + */ +#define TC_NUMBER_OFFSET 3 + +/** + * \brief Macro is used to fill usart configuration structure based on its + * number + * + * \param[in] n The number of structures + */ +#define TC_CONFIGURATION(n) \ + { \ + (n), TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_WAVEGEN(TC_CTRLA_WAVEGEN_MPWM_Val) \ + | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) \ + | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC), \ + (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), \ + (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ + | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ + | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ + CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1 \ + } +/** + * \brief TC configuration type + */ +struct tc_configuration { + uint8_t number; + hri_tc_ctrla_reg_t ctrl_a; + hri_tc_dbgctrl_reg_t dbg_ctrl; + hri_tc_evctrl_reg_t event_ctrl; + hri_tc_per_reg_t per; + hri_tc_cc32_reg_t cc0; + hri_tc_cc32_reg_t cc1; +}; + +/** + * \brief Array of TC configurations + */ +static struct tc_configuration _tcs[] = { +#if CONF_TC3_ENABLE == 1 + TC_CONFIGURATION(3), +#endif +#if CONF_TC4_ENABLE == 1 + TC_CONFIGURATION(4), +#endif +#if CONF_TC5_ENABLE == 1 + TC_CONFIGURATION(5), +#endif +#if CONF_TC6_ENABLE == 1 + TC_CONFIGURATION(6), +#endif +#if CONF_TC7_ENABLE == 1 + TC_CONFIGURATION(7), +#endif +}; + +static struct _pwm_device *_tc3_dev = NULL; + +static int8_t get_tc_index(const void *const hw); +static uint8_t tc_get_hardware_index(const void *const hw); +static void _tc_init_irq_param(const void *const hw, void *dev); +static inline uint8_t _get_hardware_offset(const void *const hw); +/** + * \brief Initialize TC for PWM mode + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw) +{ + int8_t i = get_tc_index(hw); + device->hw = hw; + + hri_tc_wait_for_sync(hw); + if (hri_tc_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_tc_set_CTRLA_SWRST_bit(hw); + hri_tc_wait_for_sync(hw); + + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); + hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { + hri_tccount16_write_CC_reg(hw, 0, (hri_tc_count16_reg_t)_tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, (hri_tc_count16_reg_t)_tcs[i].cc1); + } else { + /* 8-bit resolution is not accepted by duty cycle control */ + return ERR_INVALID_DATA; + } + + _tc_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); + NVIC_ClearPendingIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); + NVIC_EnableIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); + + return ERR_NONE; +} +/** + * \brief De-initialize TC for PWM mode + */ +void _pwm_deinit(struct _pwm_device *const device) +{ + void *const hw = device->hw; + + NVIC_DisableIRQ((IRQn_Type)(TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); + + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_set_CTRLA_SWRST_bit(hw); +} +/** + * \brief Start PWM + */ +void _pwm_enable(struct _pwm_device *const device) +{ + hri_tc_set_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Stop PWM + */ +void _pwm_disable(struct _pwm_device *const device) +{ + hri_tc_clear_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Set PWM parameter + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle) +{ + int8_t i = get_tc_index(device->hw); + void *const hw = device->hw; + _tcs[i].cc0 = period; + _tcs[i].cc1 = duty_cycle; + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + } else { + hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1); + } +} +/** + * \brief Get pwm waveform period value + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0)); + } else { + return (pwm_period_t)(hri_tccount16_read_CC_reg(hw, 0)); + } +} +/** + * \brief Get pwm waveform duty cycle + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + uint32_t per; + uint32_t duty_cycle; + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + per = hri_tccount32_read_CC_reg(hw, 0); + duty_cycle = hri_tccount32_read_CC_reg(hw, 1); + } else { + per = hri_tccount16_read_CC_reg(hw, 0); + duty_cycle = hri_tccount16_read_CC_reg(hw, 1); + } + + return ((duty_cycle * 1000) / per); +} +/** + * \brief Check if PWM is running + */ +bool _pwm_is_enabled(const struct _pwm_device *const device) +{ + return hri_tc_get_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Enable/disable PWM interrupt + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable) +{ + ASSERT(device); + + if (PWM_DEVICE_PERIOD_CB == type) { + hri_tc_write_INTEN_OVF_bit(device->hw, disable); + } else if (PWM_DEVICE_ERROR_CB == type) { + hri_tc_write_INTEN_ERR_bit(device->hw, disable); + } +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Retrieve pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void) +{ + return NULL; +} +/** + * \internal TC interrupt handler for PWM + * + * \param[in] instance TC instance number + */ +static void tc_pwm_interrupt_handler(struct _pwm_device *device) +{ + void *const hw = device->hw; + + if (hri_tc_get_interrupt_OVF_bit(hw)) { + hri_tc_clear_interrupt_OVF_bit(hw); + if (NULL != device->callback.pwm_period_cb) { + device->callback.pwm_period_cb(device); + } + } + if (hri_tc_get_INTEN_ERR_bit(hw)) { + hri_tc_clear_interrupt_ERR_bit(hw); + if (NULL != device->callback.pwm_error_cb) { + device->callback.pwm_error_cb(device); + } + } +} + +/** +* \brief TC interrupt handler +*/ +void TC3_Handler(void) +{ + tc_pwm_interrupt_handler(_tc3_dev); +} + +/** + * \internal Retrieve TC hardware index + * + * \param[in] hw The pointer to hardware instance + */ +static uint8_t tc_get_hardware_index(const void *const hw) +{ +#ifndef _UNIT_TEST_ + return ((uint32_t)hw - TC_HW_BASE_ADDR) >> 10; +#else + return ((uint32_t)hw - TC_HW_BASE_ADDR) / sizeof(Tc); +#endif +} + +/** + * \internal Retrieve TC index + * + * \param[in] hw The pointer to hardware instance + * + * \return The index of TC configuration + */ +static int8_t get_tc_index(const void *const hw) +{ + uint8_t tc_offset = tc_get_hardware_index(hw) + TC_NUMBER_OFFSET; + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_tcs); i++) { + if (_tcs[i].number == tc_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \brief Init irq param with the given tc hardware instance + */ +static void _tc_init_irq_param(const void *const hw, void *dev) +{ + if (hw == TC3) { + _tc3_dev = (struct _pwm_device *)dev; + } +} + +static inline uint8_t _get_hardware_offset(const void *const hw) +{ + return (((uint32_t)hw - TC_HW_BASE_ADDR) >> 10) + TC_NUMBER_OFFSET; +} diff --git a/atmel-samd/asf4/samd21/hpl/tc/hpl_tc_base.h b/atmel-samd/asf4/samd21/hpl/tc/hpl_tc_base.h new file mode 100644 index 0000000000000..9d7f2c72a5ec2 --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/tc/hpl_tc_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief SAM Timer/Counter + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distributionn. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HPL_TC_BASE_H_INCLUDED +#define _HPL_TC_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup tc_group TC Hardware Proxy Layer + * + * \section tc_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void); + +/** + * \brief Retrieve pwm helper functions + * + * \return A pointer to set of pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void); + +//@} +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c b/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c new file mode 100644 index 0000000000000..6a9cd6627b9fd --- /dev/null +++ b/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c @@ -0,0 +1,2051 @@ +/** + * \file + * + * \brief SAM USB HPL + * + * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +/** + * \brief Dummy callback function + * \return Always false. + */ +static bool _dummy_func_no_return(uint32_t unused0, uint32_t unused1) +{ + (void)unused0; + (void)unused1; + return false; +} + +/** + * \brief Load USB calibration value from NVM + */ +static void _usb_load_calib(void) +{ +#define NVM_USB_PAD_TRANSN_POS 45 +#define NVM_USB_PAD_TRANSN_SIZE 5 +#define NVM_USB_PAD_TRANSP_POS 50 +#define NVM_USB_PAD_TRANSP_SIZE 5 +#define NVM_USB_PAD_TRIM_POS 55 +#define NVM_USB_PAD_TRIM_SIZE 3 + Usb * hw = USB; + uint32_t pad_transn + = (*((uint32_t *)(NVMCTRL_OTP4) + (NVM_USB_PAD_TRANSN_POS / 32)) >> (NVM_USB_PAD_TRANSN_POS % 32)) + & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1); + uint32_t pad_transp + = (*((uint32_t *)(NVMCTRL_OTP4) + (NVM_USB_PAD_TRANSP_POS / 32)) >> (NVM_USB_PAD_TRANSP_POS % 32)) + & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1); + uint32_t pad_trim = (*((uint32_t *)(NVMCTRL_OTP4) + (NVM_USB_PAD_TRIM_POS / 32)) >> (NVM_USB_PAD_TRIM_POS % 32)) + & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1); + if (pad_transn == 0x1F) { + pad_transn = 5; + } + if (pad_transp == 0x1F) { + pad_transp = 29; + } + if (pad_trim == 0x7) { + pad_trim = 5; + } + + hw->DEVICE.PADCAL.reg = USB_PADCAL_TRANSN(pad_transn) | USB_PADCAL_TRANSP(pad_transp) | USB_PADCAL_TRIM(pad_trim); + + hw->DEVICE.QOSCTRL.bit.CQOS = 3; + hw->DEVICE.QOSCTRL.bit.DQOS = 3; +} + +/** \name USB clock source management */ +/*@{*/ + +/** USB clock is generated by DFLL. */ +#define USB_CLK_SRC_DFLL 0 + +/** USB clock is generated by DPLL. */ +#define USB_CLK_SRC_DPLL 1 + +/** Uses DFLL as USB clock source. */ +#define CONF_USB_D_CLK_SRC USB_CLK_SRC_DFLL + +/** Retry for USB remote wakeup sending. */ +#define CONF_USB_RMT_WKUP_RETRY 5 + +/** + * \brief Wait DPLL clock to be ready + */ +static inline void _usb_d_dev_wait_dpll_rdy(void) +{ +#define DPLL_READY_FLAG (SYSCTRL_DPLLSTATUS_ENABLE | SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK) + while (hri_sysctrl_get_DPLLSTATUS_reg(SYSCTRL, DPLL_READY_FLAG) != DPLL_READY_FLAG) + ; +} + +/** + * \brief Wait DFLL clock to be ready + */ +static inline void _usb_d_dev_wait_dfll_rdy(void) +{ +#define DFLL_READY_FLAG (SYSCTRL_PCLKSR_DFLLRDY | SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC) + /* In USB recovery mode the status is not checked */ + if (!(SYSCTRL->DFLLCTRL.reg & SYSCTRL_DFLLCTRL_USBCRM)) { + while (hri_sysctrl_get_PCLKSR_reg(SYSCTRL, DFLL_READY_FLAG) != DFLL_READY_FLAG) + ; + } else { + while (hri_sysctrl_get_PCLKSR_reg(SYSCTRL, SYSCTRL_PCLKSR_DFLLRDY) != SYSCTRL_PCLKSR_DFLLRDY) + ; + } +} + +/** + * \brief Wait USB source clock to be ready + * \param[in] clk_src Clock source, could be \ref USB_CLK_SRC_DFLL or + * \ref USB_CLK_SRC_DPLL. + */ +static inline void _usb_d_dev_wait_clk_rdy(const uint8_t clk_src) +{ + if (clk_src == USB_CLK_SRC_DFLL) { + _usb_d_dev_wait_dfll_rdy(); + } else if (clk_src == USB_CLK_SRC_DPLL) { + _usb_d_dev_wait_dpll_rdy(); + } +} + +/*@}*/ + +/** \name USB general settings */ +/*@{*/ + +/** Increase the value to be aligned. */ +#define _usb_align_up(val) (((val)&0x3) ? (((val) + 4 - ((val)&0x3))) : (val)) + +/** Check if the buffer is in RAM (can DMA), or cache needed + * \param[in] a Buffer start address. + * \param[in] s Buffer size, in number of bytes. + * \return \c true If the buffer is in RAM. + */ +#define _IN_RAM(a, s) ((0x20000000 <= (uint32_t)(a)) && (((uint32_t)(a) + (s)) < 0x20008000)) + +/** Check if the address should be placed in RAM. */ +#define _usb_is_addr4dma(addr, size) _IN_RAM((addr), (size)) + +/** Check if the address is 32-bit aligned. */ +#define _usb_is_aligned(val) (((uint32_t)(val)&0x3) == 0) +/*@}*/ + +/* Cache static configurations. + * By default, all OUT endpoint have 64 bytes cache. */ +#ifndef CONF_USB_EP0_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP0_CACHE 64 +#endif + +#ifndef CONF_USB_EP0_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP0_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP1_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP1_CACHE 64 +#endif + +#ifndef CONF_USB_EP1_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP1_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP2_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP2_CACHE 64 +#endif + +#ifndef CONF_USB_EP2_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP2_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP3_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP3_CACHE 64 +#endif + +#ifndef CONF_USB_EP3_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP3_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP4_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP4_CACHE 64 +#endif + +#ifndef CONF_USB_EP4_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP4_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP5_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP5_CACHE 64 +#endif + +#ifndef CONF_USB_EP5_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP5_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP6_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP6_CACHE 64 +#endif + +#ifndef CONF_USB_EP6_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP6_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP7_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP7_CACHE 64 +#endif + +#ifndef CONF_USB_EP7_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP7_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP8_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP8_CACHE 64 +#endif + +#ifndef CONF_USB_EP8_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP8_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP9_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP9_CACHE 64 +#endif + +#ifndef CONF_USB_EP9_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP9_I_CACHE 0 +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP0_CACHE +static uint32_t _usb_ep0_cache[_usb_align_up(CONF_USB_EP0_CACHE) / 4]; +#else +#define _usb_ep0_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#define _usb_ep0_i_cache NULL + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 +uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; +#else +#define _usb_ep1_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1 +static uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; +#else +#define _usb_ep1_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP2_CACHE && CONF_USB_D_MAX_EP_N >= 2 +static uint32_t _usb_ep2_cache[_usb_align_up(CONF_USB_EP2_CACHE) / 4]; +#else +#define _usb_ep2_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP2_I_CACHE && CONF_USB_D_MAX_EP_N >= 2 +static uint32_t _usb_ep2_i_cache[_usb_align_up(CONF_USB_EP2_I_CACHE) / 4]; +#else +#define _usb_ep2_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP3_CACHE && CONF_USB_D_MAX_EP_N >= 3 +static uint32_t _usb_ep3_cache[_usb_align_up(CONF_USB_EP3_CACHE) / 4]; +#else +#define _usb_ep3_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP3_I_CACHE && CONF_USB_D_MAX_EP_N >= 3 +static uint32_t _usb_ep3_i_cache[_usb_align_up(CONF_USB_EP3_I_CACHE) / 4]; +#else +#define _usb_ep3_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP4_CACHE && CONF_USB_D_MAX_EP_N >= 4 +static uint32_t _usb_ep4_cache[_usb_align_up(CONF_USB_EP4_CACHE) / 4]; +#else +#define _usb_ep4_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP4_I_CACHE && CONF_USB_D_MAX_EP_N >= 4 +static uint32_t _usb_ep4_i_cache[_usb_align_up(CONF_USB_EP4_I_CACHE) / 4]; +#else +#define _usb_ep4_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP5_CACHE && CONF_USB_D_MAX_EP_N >= 5 +static uint32_t _usb_ep5_cache[_usb_align_up(CONF_USB_EP5_CACHE) / 4]; +#else +#define _usb_ep5_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP5_I_CACHE && CONF_USB_D_MAX_EP_N >= 5 +static uint32_t _usb_ep5_i_cache[_usb_align_up(CONF_USB_EP5_I_CACHE) / 4]; +#else +#define _usb_ep5_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP6_CACHE && CONF_USB_D_MAX_EP_N >= 6 +static uint32_t _usb_ep6_cache[_usb_align_up(CONF_USB_EP6_CACHE) / 4]; +#else +#define _usb_ep6_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP6_I_CACHE && CONF_USB_D_MAX_EP_N >= 6 +static uint32_t _usb_ep6_i_cache[_usb_align_up(CONF_USB_EP6_I_CACHE) / 4]; +#else +#define _usb_ep6_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP7_CACHE && CONF_USB_D_MAX_EP_N >= 7 +static uint32_t _usb_ep7_cache[_usb_align_up(CONF_USB_EP7_CACHE) / 4]; +#else +#define _usb_ep7_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP7_I_CACHE && CONF_USB_D_MAX_EP_N >= 7 +static uint32_t _usb_ep7_i_cache[_usb_align_up(CONF_USB_EP7_I_CACHE) / 4]; +#else +#define _usb_ep7_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP8_CACHE && CONF_USB_D_MAX_EP_N >= 8 +static uint32_t _usb_ep8_cache[_usb_align_up(CONF_USB_EP8_CACHE) / 4]; +#else +#define _usb_ep8_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP8_I_CACHE && CONF_USB_D_MAX_EP_N >= 8 +static uint32_t _usb_ep8_i_cache[_usb_align_up(CONF_USB_EP8_I_CACHE) / 4]; +#else +#define _usb_ep8_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP9_CACHE && CONF_USB_D_MAX_EP_N >= 9 +static uint32_t _usb_ep9_cache[_usb_align_up(CONF_USB_EP9_CACHE) / 4]; +#else +#define _usb_ep9_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP9_I_CACHE && CONF_USB_D_MAX_EP_N >= 9 +static uint32_t _usb_ep9_i_cache[_usb_align_up(CONF_USB_EP9_I_CACHE) / 4]; +#else +#define _usb_ep9_i_cache NULL +#endif + +/** Access endpoint cache buffer for OUT transactions (none-control) or + * SETUP/IN/OUT transactions (control). */ +#define _USB_EP_CACHE(n) ((void *)_usb_ep##n##_cache) + +/** Access endpoint cache buffer for IN transactions (none-control). */ +#define _USB_EP_I_CACHE(n) ((void *)_usb_ep##n##_i_cache) + +/** The configuration settings for one of the endpoint hardware. */ +struct _usb_ep_cfg_item { + /* Endpoint cache buffer for OUT transactions (none-control) or + * SETUP/IN/OUT transactions (control). */ + void *cache; + /* endpoint cache buffer for IN transactions (none-control). */ + void *i_cache; + /* Cache buffer size for OUT transactions (none-control) or + * SETUP/IN/OUT transactions (control). */ + uint16_t size; + /* Cache buffer size for IN transactions (none-control). */ + uint16_t i_size; +}; + +/** Build the endpoint configuration settings for one endpoint. */ +#define _USB_EP_CFG_ITEM(n) \ + { \ + _USB_EP_CACHE(n), _USB_EP_I_CACHE(n), CONF_USB_EP##n##_CACHE, CONF_USB_EP##n##_I_CACHE, \ + } + +/** The configuration settings for all endpoint. */ +static const struct _usb_ep_cfg_item _usb_ep_cfgs[] = {_USB_EP_CFG_ITEM(0) +#if CONF_USB_D_MAX_EP_N >= 1 + , + _USB_EP_CFG_ITEM(1) +#endif +#if CONF_USB_D_MAX_EP_N >= 2 + , + _USB_EP_CFG_ITEM(2) +#endif +#if CONF_USB_D_MAX_EP_N >= 3 + , + _USB_EP_CFG_ITEM(3) +#endif +#if CONF_USB_D_MAX_EP_N >= 4 + , + _USB_EP_CFG_ITEM(4) +#endif +#if CONF_USB_D_MAX_EP_N >= 5 + , + _USB_EP_CFG_ITEM(5) +#endif +#if CONF_USB_D_MAX_EP_N >= 6 + , + _USB_EP_CFG_ITEM(6) +#endif +#if CONF_USB_D_MAX_EP_N >= 7 + , + _USB_EP_CFG_ITEM(7) +#endif +#if CONF_USB_D_MAX_EP_N >= 8 + , + _USB_EP_CFG_ITEM(8) +#endif +#if CONF_USB_D_MAX_EP_N >= 9 + , + _USB_EP_CFG_ITEM(9) +#endif +}; + +/** \name HW specific settings and implements */ +/*@{*/ + +/** Number of endpoints supported. */ +#define USB_D_N_EP (1 + CONF_USB_D_NUM_EP_SP * 2) + +/** HPL USB device endpoint struct. */ +struct _usb_d_dev_ep { + /** Pointer to transaction buffer. */ + uint8_t *trans_buf; + /** Transaction size. */ + uint32_t trans_size; + /** Transaction transferred count. */ + uint32_t trans_count; + + /** Pointer to cache buffer, must be aligned. */ + uint8_t *cache; + + /** Endpoint size. */ + uint16_t size; + /** Endpoint address. */ + uint8_t ep; + /** Feature flags. */ + union { + /** Interpreted by bit fields. */ + struct { + /** EPCFG.ETYPE. */ + uint8_t eptype : 3; + /** Stall status. */ + uint8_t is_stalled : 1; + /** Transaction auto ZLP. */ + uint8_t need_zlp : 1; + /** Transaction with cache */ + uint8_t use_cache : 1; + /** Endpoint is busy. */ + uint8_t is_busy : 1; + /** Transaction direction. */ + uint8_t dir : 1; + } bits; + uint8_t u8; + } flags; +}; + +/** Check if the endpoint is used. */ +#define _usb_d_dev_ep_is_used(ept) ((ept)->ep != 0xFF) + +/** Check if the endpoint is busy doing transactions. */ +#define _usb_d_dev_ep_is_busy(ept) ((ept)->flags.bits.is_busy) + +/** Check if the endpoint is control endpoint. */ +#define _usb_d_dev_ep_is_ctrl(ept) ((ept)->flags.bits.eptype == USB_D_EPTYPE_CTRL) + +/** Check if the endpoint transactions are IN. */ +#define _usb_d_dev_ep_is_in(ept) ((ept)->flags.bits.dir) + +/** Interrupt flags for SETUP transaction. */ +#define USB_D_SETUP_INT_FLAGS (USB_DEVICE_EPINTFLAG_RXSTP) + +/** Interrupt flags for BANK1 transactions. */ +#define USB_D_BANK1_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT1 | USB_DEVICE_EPINTFLAG_TRFAIL1 | USB_DEVICE_EPINTFLAG_STALL1) + +/** Interrupt flags for BANK0 transactions. */ +#define USB_D_BANK0_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT0 | USB_DEVICE_EPINTFLAG_TRFAIL0 | USB_DEVICE_EPINTFLAG_STALL0) + +/** Interrupt flags for SETUP/IN/OUT transactions. */ +#define USB_D_ALL_INT_FLAGS (0x7F) + +/** Interrupt flags for WAKEUP event. */ +#define USB_D_WAKEUP_INT_FLAGS (USB_DEVICE_INTFLAG_UPRSM | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_WAKEUP) + +/** Interrupt flags for SUSPEND event. */ +#define USB_D_SUSPEND_INT_FLAGS (USB_DEVICE_INTFLAG_LPMSUSP | USB_DEVICE_INTFLAG_SUSPEND) + +/** Max data bytes for a single DMA transfer. */ +#define USB_D_DEV_TRANS_MAX 8192 /* 14-bits, uses 13-bits. */ + +/** Endpoint type setting to disable. */ +#define USB_D_EPTYPE_DISABLE 0 + +/** Endpoint type setting to work as control endpoint. */ +#define USB_D_EPTYPE_CTRL 1 + +/** Endpoint type setting to work as isochronous endpoint. */ +#define USB_D_EPTYPE_ISOCH 2 + +/** Endpoint type setting to work as interrupt endpoint. */ +#define USB_D_EPTYPE_INT 3 + +/** Endpoint type setting to work as bulk endpoint. */ +#define USB_D_EPTYPE_BULK 4 + +/** Endpoint type setting for dual bank endpoint. */ +#define USB_D_EPTYPE_DUAL 5 + +/** EPCFG register value for control endpoints. */ +#define USB_D_EPCFG_CTRL 0x11 + +/** HPL USB device struct. */ +struct _usb_d_dev { + /** Callbacks of USB device. */ + struct _usb_d_dev_callbacks callbacks; + /** Endpoint transaction callbacks. */ + struct _usb_d_dev_ep_callbacks ep_callbacks; + /** Endpoints (ep0 + others). */ + struct _usb_d_dev_ep ep[USB_D_N_EP]; +}; + +/** Private data for SAM0 USB peripheral. + */ +typedef struct _usb_d_dev_prvt { + /** USB device descriptor table for peripheral to work. */ + UsbDeviceDescriptor desc_table[CONF_USB_D_MAX_EP_N + 1]; +} usb_d_dev_prvt_t; + +/*@}*/ + +/** USB device driver instance. */ +static struct _usb_d_dev dev_inst; + +/** USB device driver private data instance. */ +static struct _usb_d_dev_prvt prvt_inst; + +static void _usb_d_dev_reset_epts(void); + +static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t status); +static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code); + +static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr); +static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr); + +static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept); + +/** \brief ACK the endpoint interrupt + * \param[in] epn Endpoint number. + * \param[in] flags Interrupt flags. + */ +static inline void _usbd_ep_int_ack(uint8_t epn, uint32_t flags) +{ + hri_usbendpoint_clear_EPINTFLAG_reg(USB, epn, flags); +} + +/** \brief Enable the endpoint interrupt + * \param[in] epn Endpoint number. + * \param[in] flags Interrupt flags. + */ +static inline void _usbd_ep_int_en(uint8_t epn, uint32_t flags) +{ + hri_usbendpoint_set_EPINTEN_reg(USB, epn, flags); +} + +/** \brief Disable the endpoint interrupt + * \param[in] epn Endpoint number. + * \param[in] flags Interrupt flags. + */ +static inline void _usbd_ep_int_dis(uint8_t epn, uint32_t flags) +{ + hri_usbendpoint_clear_EPINTEN_reg(USB, epn, flags); +} + +/** \brief Check if endpoint is control endpoint + * \param[in] epn Endpoint number. + */ +static inline bool _usbd_ep_is_ctrl(uint8_t epn) +{ + return (hri_usbendpoint_read_EPCFG_reg(USB, epn) == USB_D_EPCFG_CTRL); +} + +/** \brief Set endpoint stall + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] st Stall status. + */ +static inline void _usbd_ep_set_stall(uint8_t epn, uint8_t bank_n, bool st) +{ + if (st) { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); + } else { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); + } +} + +/** \brief Check if the endpoint is stalled + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \return \c true if it's stalled. + */ +static inline bool _usbd_ep_is_stalled(uint8_t epn, uint8_t bank_n) +{ + Usb *hw = USB; + return (hri_usbendpoint_read_EPSTATUS_reg(hw, epn) & (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); +} + +/** \brief Check if stall has been sent from the endpoint + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \return \c true if it's sent. + */ +static inline bool _usbd_ep_is_stall_sent(uint8_t epn, uint8_t bank_n) +{ + Usb *hw = USB; + return (hri_usbendpoint_read_EPINTFLAG_reg(hw, epn) & (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); +} + +/** \brief ACK endpoint STALL interrupt + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + */ +static inline void _usbd_ep_ack_stall(uint8_t epn, uint8_t bank_n) +{ + _usbd_ep_int_ack(epn, (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); +} + +/** \brief Enable/disable endpoint STALL interrupt + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] en \c true to enable, \c false to disable. + */ +static inline void _usbd_ep_int_stall_en(uint8_t epn, uint8_t bank_n, const bool en) +{ + if (en) { + _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); + } else { + _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); + } +} + +/** \brief Stop SETUP transactions + * \param[in] epn Endpoint number. + */ +static inline void _usbd_ep_stop_setup(uint8_t epn) +{ + hri_usbendpoint_clear_EPINTEN_RXSTP_bit(USB, epn); +} + +/** \brief Check if SETUP packet is ready in cache + * \param[in] epn Endpoint number. + */ +static inline bool _usbd_ep_is_setup(uint8_t epn) +{ + return hri_usbendpoint_get_EPINTFLAG_reg(USB, epn, USB_DEVICE_EPINTFLAG_RXSTP); +} + +/** \brief ACK endpoint SETUP interrupt + * \param[in] epn Endpoint number. + */ +static inline void _usbd_ep_ack_setup(uint8_t epn) +{ + _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_RXSTP); +} + +/** \brief Set endpoint toggle value + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] tgl Toggle value. + */ +static inline void _usbd_ep_set_toggle(uint8_t epn, uint8_t bank_n, uint8_t tgl) +{ + if (tgl) { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); + } else { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); + } +} + +/** \brief ACK IN/OUT complete interrupt + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + */ +static inline void _usbd_ep_ack_io_cpt(uint8_t epn, uint8_t bank_n) +{ + _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_TRCPT0 << bank_n); +} + +/** \brief Set DMA buffer used for bank data + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] addr DMA buffer address to set. + */ +static inline void _usbd_ep_set_buf(uint8_t epn, uint8_t bank_n, uint32_t addr) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->ADDR.reg = addr; +} + +/** \brief Set bank count for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] count Data count for IN. + */ +static inline void _usbd_ep_set_in_count(uint8_t epn, uint8_t bank_n, uint16_t count) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.MULTI_PACKET_SIZE = count; +} + +/** \brief Set bank size for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size for IN. + */ +static inline void _usbd_ep_set_in_size(uint8_t epn, uint8_t bank_n, uint16_t size) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.BYTE_COUNT = size; +} + +/** \brief Set bank count for OUT transaction + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] count Data count for OUT. + */ +static inline void _usbd_ep_set_out_count(uint8_t epn, uint8_t bank_n, uint16_t count) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.BYTE_COUNT = count; +} + +/** \brief Set bank size for OUT transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size for OUT. + */ +static inline void _usbd_ep_set_out_size(uint8_t epn, uint8_t bank_n, uint16_t size) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.MULTI_PACKET_SIZE = size; +} + +/** Set bank size and count for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size. + * \param[in] count Initial data count. + */ +static inline void _usbd_ep_set_in_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) +{ + _usbd_ep_set_in_size(epn, bank_n, size); + _usbd_ep_set_in_count(epn, bank_n, count); +} + +/** \brief Set bank size and count for OUT transaction + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size. + * \param[in] count Initial data count. + */ +static inline void _usbd_ep_set_out_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) +{ + _usbd_ep_set_out_size(epn, bank_n, size); + _usbd_ep_set_out_count(epn, bank_n, count); +} + +/** \brief Clear bank status + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + */ +static inline void _usbd_ep_clear_bank_status(uint8_t epn, uint8_t bank_n) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->STATUS_BK.reg = 0; +} + +/** Set IN ready for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] rdy Set to \c true to indicate IN packet ready to TX. + */ +static inline void _usbd_ep_set_in_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) +{ + if (rdy) { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } else { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } +} + +/** \brief Set bank ready for OUT transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] rdy Set to \c true to indicate OUT bank ready to RX. + */ +static inline void _usbd_ep_set_out_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) +{ + if (rdy) { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } else { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } +} + +/** + * \brief Convert USB endpoint size to HW PCKSIZE.SIZE + * \param[in] n Number of bytes of endpoint size. + */ +static inline uint8_t _usbd_ep_pcksize_size(uint16_t n) +{ + return ( + (n > 512) + ? 7 + : ((n > 256) ? 6 : ((n > 128) ? 5 : ((n > 64) ? 4 : ((n > 32) ? 3 : ((n > 16) ? 2 : ((n > 8) ? 1 : 0))))))); +} + +/** + * \brief Obtain endpoint descriptor pointer + * \param[in] epn Endpoint number. + * \param[in] dir Endpoint direction. + */ +static inline struct _usb_d_dev_ep *_usb_d_dev_ept(uint8_t epn, bool dir) +{ + uint8_t ep_index = (epn == 0) ? 0 : (dir ? (epn + CONF_USB_D_MAX_EP_N) : epn); + return &dev_inst.ep[ep_index]; +} + +/** + * \brief Handles USB SOF interrupt + */ +static inline void _usb_d_dev_sof(void) +{ + /* ACK SOF interrupt. */ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_SOF); + dev_inst.callbacks.sof(); +} + +/** + * \brief Handles USB LPM Suspend interrupt + */ +static inline void _usb_d_dev_lpmsusp(void) +{ + uint8_t i; + uint32_t lpm_variable = 0; + + /* ACK LPMSUSP interrupt. */ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); + /* Change interrupt masks */ + hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + + /* Find LPM data */ + for (i = 0; i < CONF_USB_D_MAX_EP_N; i++) { + UsbDeviceDescBank *bank = &prvt_inst.desc_table[i].DeviceDescBank[0]; + if (bank->EXTREG.bit.SUBPID == 0x3) { + /* Save LPM variable */ + lpm_variable = bank->EXTREG.bit.VARIABLE; + /* Clear */ + bank->EXTREG.reg = 0; + break; + } + } + dev_inst.callbacks.event(USB_EV_LPM_SUSPEND, lpm_variable); +} + +/** + * \brief Handles USB RAM Error interrupt + */ +static inline void _usb_d_dev_ramerr(void) +{ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_RAMACER); + dev_inst.callbacks.event(USB_EV_ERROR, 0); +} + +/** + * \brief Handles USB resume/wakeup interrupts + */ +static inline void _usb_d_dev_wakeup(void) +{ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_WAKEUP_INT_FLAGS); + hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + + _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); + dev_inst.callbacks.event(USB_EV_WAKEUP, 0); +} + +/** + * \brief Handles USB signal reset interrupt + */ +static inline void _usb_d_dev_reset(void) +{ + /* EP0 will not be reseted by USB RESET, disable manually. */ + hri_usbendpoint_write_EPCFG_reg(USB, 0, 0); + + hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_EORST); + hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + + _usb_d_dev_reset_epts(); + dev_inst.callbacks.event(USB_EV_RESET, 0); +} + +static inline void _usb_d_dev_suspend(void) +{ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); + hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + + dev_inst.callbacks.event(USB_EV_SUSPEND, 0); +} + +/** + * \brief Handles USB non-endpoint interrupt + */ +static inline bool _usb_d_dev_handle_nep(void) +{ + bool rc = true; + uint16_t flags = hri_usbdevice_read_INTFLAG_reg(USB); + flags &= hri_usbdevice_read_INTEN_reg(USB); + + if (flags & USB_DEVICE_INTFLAG_SOF) { + _usb_d_dev_sof(); + return true; + } + if (flags & USB_DEVICE_INTFLAG_LPMSUSP) { + _usb_d_dev_lpmsusp(); + } else if (flags & USB_DEVICE_INTFLAG_RAMACER) { + _usb_d_dev_ramerr(); + } else if (flags & USB_D_WAKEUP_INT_FLAGS) { + _usb_d_dev_wakeup(); + } else if (flags & USB_DEVICE_INTFLAG_EORST) { + _usb_d_dev_reset(); + } else if (flags & USB_DEVICE_INTFLAG_SUSPEND) { + _usb_d_dev_suspend(); + } else { + rc = false; + } + return rc; +} + +/** + * \brief Prepare next IN transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] isr Invoked from ISR. + */ +static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; + uint16_t trans_count = isr ? bank[1].PCKSIZE.bit.BYTE_COUNT : 0; + uint16_t trans_next; + uint16_t last_pkt = trans_count & ((ept->size == 1023) ? ept->size : (ept->size - 1)); + uint8_t inten = 0; + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + + if (isr) { + _usbd_ep_ack_io_cpt(epn, 1); + } + + ept->trans_count += trans_count; + /* Send more data. */ + if (ept->trans_count < ept->trans_size) { + trans_next = ept->trans_size - ept->trans_count; + if (ept->flags.bits.use_cache) { + if (trans_next > ept->size) { + trans_next = ept->size; + } + memcpy(ept->cache, &ept->trans_buf[ept->trans_count], trans_next); + _usbd_ep_set_buf(epn, 1, (uint32_t)ept->cache); + } else { + if (trans_next > USB_D_DEV_TRANS_MAX) { + trans_next = USB_D_DEV_TRANS_MAX; + } + _usbd_ep_set_buf(epn, 1, (uint32_t)&ept->trans_buf[ept->trans_count]); + } + _usbd_ep_set_in_trans(epn, 1, trans_next, 0); + goto _in_tx_exec; + } else if (ept->flags.bits.need_zlp) { + ept->flags.bits.need_zlp = 0; + _usbd_ep_set_in_trans(epn, 1, 0, 0); + goto _in_tx_exec; + } + /* Complete. */ + if (is_ctrl) { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRCPT0); + } else { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS); + } + + /* No ping-pong, so ask more data without background transfer. */ + if (last_pkt == ept->size) { + ept->flags.bits.is_busy = 0; + if (dev_inst.ep_callbacks.more(ept->ep, ept->trans_count)) { + /* More data added. */ + return; + } + ept->flags.bits.is_busy = 1; + } + /* Finish normally. */ + _usb_d_dev_trans_done(ept, USB_TRANS_DONE); + return; + +_in_tx_exec: + if (!isr) { + if (is_ctrl) { + /* Control endpoint: SETUP or OUT will abort IN transaction. + * SETUP: terminate the IN without any notification. Trigger + * SETUP callback. + * OUT NAK: terminate IN. + */ + inten = USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL0; + } else { + /* Initialize normal IN transaction. */ + inten = USB_D_BANK1_INT_FLAGS; + } + hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); + } + _usbd_ep_set_in_rdy(epn, 1, true); +} + +/** + * \brief Prepare next OUT transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] isr Invoked from ISR. + */ +static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; + uint16_t trans_size = isr ? bank->PCKSIZE.bit.MULTI_PACKET_SIZE : 0; + uint16_t last_trans = isr ? bank->PCKSIZE.bit.BYTE_COUNT : 0; + uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); + uint16_t last_pkt = last_trans & size_mask; + uint16_t trans_next; + uint8_t inten; + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + + if (isr) { + _usbd_ep_ack_io_cpt(epn, 0); + } + + /* If cache is used, copy data to buffer. */ + if (ept->flags.bits.use_cache && ept->trans_size) { + uint16_t buf_remain = ept->trans_size - ept->trans_count; + memcpy(&ept->trans_buf[ept->trans_count], ept->cache, (buf_remain > last_pkt) ? last_pkt : buf_remain); + } + + /* Force wait ZLP */ + if (ept->trans_size == 0 && ept->flags.bits.need_zlp) { + ept->flags.bits.need_zlp = 0; + ept->flags.bits.use_cache = 1; + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + _usbd_ep_set_out_trans(epn, 0, ept->size, 0); + goto _out_rx_exec; + } else if (isr && last_pkt < ept->size) { + /* Short packet. */ + ept->flags.bits.need_zlp = 0; + ept->trans_count += last_trans; + } else { + /* Full packets. */ + ept->trans_count += trans_size; + + /* Wait more data */ + if (ept->trans_count < ept->trans_size) { + /* Continue OUT */ + trans_next = ept->trans_size - ept->trans_count; + if (ept->flags.bits.use_cache) { + /* Expect single packet each time. */ + if (trans_next > ept->size) { + trans_next = ept->size; + } + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + } else { + /* Multiple packets each time. */ + if (trans_next > ept->size) { + if (trans_next > USB_D_DEV_TRANS_MAX) { + trans_next = USB_D_DEV_TRANS_MAX; + } else { + /* Must expect multiple of ep size. */ + trans_next -= trans_next & size_mask; + } + } else if (trans_next < ept->size) { + /* Last un-aligned packet should be cached. */ + ept->flags.bits.use_cache = 1; + } + _usbd_ep_set_buf(epn, 0, (uint32_t)&ept->trans_buf[ept->trans_count]); + } + _usbd_ep_set_out_trans(epn, 0, trans_next, 0); + goto _out_rx_exec; + } + } + /* Finish normally. */ + if (is_ctrl) { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1); + } else { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS); + } + /* Use ep0 out cache for next setup packets */ + if (0 == epn) { + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + } + _usb_d_dev_trans_done(ept, USB_TRANS_DONE); + return; + +_out_rx_exec: + if (!isr) { + if (is_ctrl) { + /* Initialize control OUT transaction. */ + + /* Control transfer: SETUP or IN request will abort the + * OUT transactions. + * SETUP: terminate OUT without any notification. + * Trigger SETUP notification. + * IN NAK: finish OUT normally. Notify data done. + */ + _usbd_ep_clear_bank_status(epn, 1); + /* Detect OUT, SETUP, NAK IN */ + inten = USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1; + } else { + /* Initialize normal OUT transaction. */ + inten = USB_D_BANK0_INT_FLAGS; + } + hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); + } + _usbd_ep_set_out_rdy(epn, 0, true); +} + +/** + * \brief Handles setup received interrupt + * \param[in] ept Pointer to endpoint information. + */ +static void _usb_d_dev_handle_setup(struct _usb_d_dev_ep *ept) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + + if (!is_ctrl) { + /* Should never be here! */ + _usbd_ep_ack_setup(epn); + _usbd_ep_stop_setup(epn); + return; + } + /* Control transfer: + * SETUP transaction will terminate IN/OUT transaction, + * and start new transaction with received SETUP packet. + */ + if (_usb_d_dev_ep_is_busy(ept)) { + ept->flags.bits.is_busy = 0; + + /* Stop transfer on either direction. */ + _usbd_ep_set_in_rdy(epn, 1, false); + _usbd_ep_set_out_rdy(epn, 0, false); + } + ept->flags.bits.is_stalled = 0; + + /* Clear status and notify SETUP */ + _usbd_ep_clear_bank_status(epn, 0); + _usbd_ep_clear_bank_status(epn, 1); + _usbd_ep_int_ack(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); + _usbd_ep_int_dis(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); + /* Invoke callback. */ + dev_inst.ep_callbacks.setup(ept->ep); +} + +/** + * \brief Handles stall sent interrupt + * \param[in] ept Pointer to endpoint information. + * \param[in] bank_n Bank number. + */ +static void _usb_d_dev_handle_stall(struct _usb_d_dev_ep *ept, const uint8_t bank_n) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + /* Clear interrupt enable. Leave status there for status check. */ + _usbd_ep_int_stall_en(epn, bank_n, false); + _usb_d_dev_trans_done(ept, USB_TRANS_STALL); +} + +/** + * \brief Handles transaction fail interrupt + * \param[in] ept Pointer to endpoint information. + * \param[in] bank_n Bank number. + */ +static void _usb_d_dev_handle_trfail(struct _usb_d_dev_ep *ept, const uint8_t bank_n) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + const uint8_t fail[2] = {USB_DEVICE_EPINTFLAG_TRFAIL0, USB_DEVICE_EPINTFLAG_TRFAIL1}; + UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; + uint8_t eptype + = bank_n ? hri_usbendpoint_read_EPCFG_EPTYPE1_bf(hw, epn) : hri_usbendpoint_read_EPCFG_EPTYPE0_bf(hw, epn); + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + USB_DEVICE_STATUS_BK_Type st; + st.reg = bank[bank_n].STATUS_BK.reg; + + if ((eptype == USB_D_EPTYPE_ISOCH) && st.bit.CRCERR) { + bank[bank_n].STATUS_BK.bit.CRCERR = 0; + hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); + _usb_d_dev_trans_stop(ept, bank_n, USB_TRANS_ERROR); + } else if (st.bit.ERRORFLOW) { + bank[bank_n].STATUS_BK.bit.ERRORFLOW = 0; + hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); + /* Abort control transfer. */ + if (is_ctrl && _usb_d_dev_ep_is_busy(ept)) { + if (bank_n != _usb_d_dev_ep_is_in(ept)) { + _usb_d_dev_trans_stop(ept, _usb_d_dev_ep_is_in(ept), USB_TRANS_DONE); + } + } + } else { + _usbd_ep_clear_bank_status(epn, bank_n); + hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); + } +} + +/** + * \brief Analyze flags for setup transaction + * \param[in] ept Pointer to endpoint information. + * \param[in] flags Endpoint interrupt flags. + */ +static inline void _usb_d_dev_trans_setup_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) +{ + /* + * SETPU is automatically ACKed by hardware + * OUT & IN should be set to NAK when checking SETUP + * No need to check OUT & IN status. + */ + if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { + _usb_d_dev_handle_setup(ept); + } else if (flags & USB_DEVICE_EPINTFLAG_STALL1) { + _usb_d_dev_handle_stall(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_STALL0) { + _usb_d_dev_handle_stall(ept, 0); + } +} + +/** + * \brief Analyze flags for IN transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] flags Endpoint interrupt flags. + */ +static inline void _usb_d_dev_trans_in_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) +{ + /* + * Check IN flags + * If control endpoint, SETUP & OUT is checked to see if abort + */ + if (flags & USB_DEVICE_EPINTFLAG_STALL1) { + _usb_d_dev_handle_stall(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { + _usb_d_dev_handle_trfail(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT1) { + _usb_d_dev_in_next(ept, true); + } else if (_usb_d_dev_ep_is_ctrl(ept)) { + /* Check OUT NAK + * Check SETUP + */ + if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { + _usb_d_dev_handle_trfail(ept, 0); + } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { + _usb_d_dev_handle_setup(ept); + } + } +} + +/** + * \brief Analyze flags for OUT transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] flags Endpoint interrupt flags. + */ +static inline void _usb_d_dev_trans_out_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) +{ + /* + * Check OUT flags. + * If control endpoint, SETUP & IN NAK is checked to see if abort + */ + if (flags & USB_DEVICE_EPINTFLAG_STALL0) { + _usb_d_dev_handle_stall(ept, 0); + } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { + _usb_d_dev_handle_trfail(ept, 0); + } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT0) { + _usb_d_dev_out_next(ept, true); + } else if (_usb_d_dev_ep_is_ctrl(ept)) { + /* Check IN NAK + * Check SETUP + */ + if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { + _usb_d_dev_handle_trfail(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { + _usb_d_dev_handle_setup(ept); + } + } +} + +/** + * \brief Handles the endpoint interrupts. + * \param[in] epint Endpoint interrupt summary (by bits). + * \param[in] ept Pointer to endpoint information. + */ +static inline void _usb_d_dev_handle_eps(uint32_t epint, struct _usb_d_dev_ep *ept) +{ + Usb *hw = USB; + + uint8_t flags, mask; + uint8_t epn = USB_EP_GET_N(ept->ep); + + if (!(epint & (1u << epn))) { + return; + } + flags = hw->DEVICE.DeviceEndpoint[epn].EPINTFLAG.reg; + mask = hw->DEVICE.DeviceEndpoint[epn].EPINTENSET.reg; + flags &= mask; + if (flags) { + if (!_usb_d_dev_ep_is_busy(ept)) { + _usb_d_dev_trans_setup_isr(ept, flags); + } else if (_usb_d_dev_ep_is_in(ept)) { + _usb_d_dev_trans_in_isr(ept, flags); + } else { + _usb_d_dev_trans_out_isr(ept, flags); + } + } +} + +/** + * \brief USB device interrupt handler + * \param[in] unused The parameter is not used + */ +static void _usb_d_dev_handler(void) +{ + Usb * hw = USB; + uint8_t i; + + uint16_t epint = hw->DEVICE.EPINTSMRY.reg; + if (0 == epint) { + if (_usb_d_dev_handle_nep()) { + return; + } + } + /* Handle endpoints */ + for (i = 0; i < USB_D_N_EP; i++) { + struct _usb_d_dev_ep *ept = &dev_inst.ep[i]; + if (ept->ep == 0xFF) { + continue; + } + _usb_d_dev_handle_eps(epint, ept); + } +} + +/** + * \brief Reset all endpoint software instances + */ +static void _usb_d_dev_reset_epts(void) +{ + uint8_t i; + for (i = 0; i < USB_D_N_EP; i++) { + _usb_d_dev_trans_done(&dev_inst.ep[i], USB_TRANS_RESET); + dev_inst.ep[i].ep = 0xFF; + dev_inst.ep[i].flags.u8 = 0; + } + memset(prvt_inst.desc_table, 0, sizeof(UsbDeviceDescriptor) * (CONF_USB_D_MAX_EP_N + 1)); +} + +int32_t _usb_d_dev_init(void) +{ + Usb * hw = USB; + uint8_t speed = CONF_USB_D_SPEED; + const uint8_t spdconf[4] = { + USB_DEVICE_CTRLB_SPDCONF(1), /* LS */ + USB_DEVICE_CTRLB_SPDCONF(0), /* FS */ + 0, + 0 /* Reserved */ + }; + + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + if (hri_usbdevice_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_usbdevice_set_CTRLA_SWRST_bit(hw); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + + dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)_dummy_func_no_return; + dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)_dummy_func_no_return; + + dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)_dummy_func_no_return; + dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)_dummy_func_no_return; + dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)_dummy_func_no_return; + + _usb_d_dev_reset_epts(); + + _usb_load_calib(); + + hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_RUNSTDBY); + hri_usbdevice_write_DESCADD_reg(hw, (uint32_t)prvt_inst.desc_table); + hri_usbdevice_write_CTRLB_reg(hw, spdconf[speed] | USB_DEVICE_CTRLB_DETACH); + + return ERR_NONE; +} + +void _usb_d_dev_deinit(void) +{ + Usb *hw = USB; + + while (_usb_d_dev_disable() < 0) + ; + + hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_SWRST); + + NVIC_DisableIRQ(USB_IRQn); + NVIC_ClearPendingIRQ(USB_IRQn); +} + +int32_t _usb_d_dev_enable(void) +{ + Usb * hw = USB; + uint8_t ctrla; + + if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { + return -USB_ERR_DENIED; + } + ctrla = hri_usbdevice_read_CTRLA_reg(hw); + if ((ctrla & USB_CTRLA_ENABLE) == 0) { + hri_usbdevice_write_CTRLA_reg(hw, ctrla | USB_CTRLA_ENABLE); + } + + NVIC_EnableIRQ(USB_IRQn); + + hri_usbdevice_set_INTEN_reg(hw, + USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER + | USB_D_SUSPEND_INT_FLAGS); + + return ERR_NONE; +} + +int32_t _usb_d_dev_disable(void) +{ + Usb * hw = USB; + uint8_t ctrla; + + if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { + return -USB_ERR_DENIED; + } + + ctrla = hri_usbdevice_read_CTRLA_reg(hw); + if (ctrla & USB_CTRLA_ENABLE) { + hri_usbdevice_write_CTRLA_reg(hw, ctrla & ~USB_CTRLA_ENABLE); + } + NVIC_DisableIRQ(USB_IRQn); + + hri_usbdevice_clear_INTEN_reg(hw, + USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER + | USB_D_SUSPEND_INT_FLAGS + | USB_D_WAKEUP_INT_FLAGS); + + return ERR_NONE; +} + +void _usb_d_dev_attach(void) +{ + hri_usbdevice_clear_CTRLB_DETACH_bit(USB); +} + +void _usb_d_dev_detach(void) +{ + hri_usbdevice_set_CTRLB_DETACH_bit(USB); +} + +#ifndef USB_FSMSTATUS_FSMSTATE_ON +#define USB_FSMSTATUS_FSMSTATE_ON USB_FSMSTATUS_FSMSTATE(2ul) +#endif +void _usb_d_dev_send_remotewakeup(void) +{ + uint32_t retry = CONF_USB_RMT_WKUP_RETRY; + _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); + while ((USB_FSMSTATUS_FSMSTATE_ON != hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(USB)) && (retry--)) { + USB->DEVICE.CTRLB.bit.UPRSM = 1; + } +} + +enum usb_speed _usb_d_dev_get_speed(void) +{ + uint8_t sp = (enum usb_speed)hri_usbdevice_read_STATUS_SPEED_bf(USB); + const enum usb_speed speed[2] = {USB_SPEED_FS, USB_SPEED_LS}; + + return speed[sp]; +} + +void _usb_d_dev_set_address(uint8_t addr) +{ + hri_usbdevice_write_DADD_reg(USB, USB_DEVICE_DADD_ADDEN | USB_DEVICE_DADD_DADD(addr)); +} + +uint8_t _usb_d_dev_get_address(void) +{ + uint8_t addr = hri_usbdevice_read_DADD_DADD_bf(USB); + return addr; +} + +uint16_t _usb_d_dev_get_frame_n(void) +{ + uint16_t fn = hri_usbdevice_read_FNUM_FNUM_bf(USB); + return fn; +} + +uint8_t _usb_d_dev_get_uframe_n(void) +{ + uint8_t ufn = hri_usbdevice_read_FNUM_MFNUM_bf(USB); + return ufn; +} + +/** + * \brief Start a setup transaction + * \param[in] ept Endpoint information. + */ +static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + _usbd_ep_set_out_trans(epn, 0, ept->size, 0); + + hri_usbendpoint_clear_EPSTATUS_reg(hw, epn, USB_DEVICE_EPSTATUS_STALLRQ(0x3) | USB_DEVICE_EPSTATUS_BK1RDY); + _usbd_ep_set_out_rdy(epn, 0, false); + + hri_usbendpoint_set_EPINTEN_reg(hw, epn, USB_D_SETUP_INT_FLAGS); +} + +int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz) +{ + return _usb_d_dev_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_siz); +} + +int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_siz) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + uint8_t ep_type = attr & USB_EP_XTYPE_MASK; + const struct _usb_ep_cfg_item *pcfg = &_usb_ep_cfgs[epn]; + + if (epn > CONF_USB_D_MAX_EP_N) { + return -USB_ERR_PARAM; + } + if (ept->ep != 0xFF) { + return -USB_ERR_REDO; + } + if (ep_type == USB_EP_XTYPE_CTRL) { + struct _usb_d_dev_ep *ept_in = _usb_d_dev_ept(epn, !dir); + if (ept_in->ep != 0xFF) { + return -USB_ERR_REDO; + } + if (pcfg->cache == NULL) { + return -USB_ERR_FUNC; + } + } + if ((dir ? pcfg->i_cache : pcfg->cache) && ((dir ? pcfg->i_size : pcfg->size) < max_pkt_siz)) { + return -USB_ERR_FUNC; + } + + /* Initialize EP n settings */ + ept->cache = (uint8_t *)(dir ? pcfg->i_cache : pcfg->cache); + ept->size = max_pkt_siz; + ept->flags.u8 = (ep_type + 1); + ept->ep = ep; + + return USB_OK; +} + +void _usb_d_dev_ep_deinit(uint8_t ep) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { + return; + } + + /* Finish pending transactions. */ + _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); + + /* Disable the endpoint. */ + if (_usb_d_dev_ep_is_ctrl(ept)) { + hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg = 0; + } else if (USB_EP_GET_DIR(ep)) { + hw->DEVICE.DeviceEndpoint[USB_EP_GET_N(ep)].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + } else { + hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + } + ept->flags.u8 = 0; + ept->ep = 0xFF; +} + +int32_t _usb_d_dev_ep_enable(const uint8_t ep) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + uint8_t epcfg = hri_usbendpoint_read_EPCFG_reg(hw, epn); + UsbDeviceDescBank * bank; + + if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { + return -USB_ERR_PARAM; + } + + bank = prvt_inst.desc_table[epn].DeviceDescBank; + if (ept->flags.bits.eptype == USB_D_EPTYPE_CTRL) { + if (epcfg & (USB_DEVICE_EPCFG_EPTYPE1_Msk | USB_DEVICE_EPCFG_EPTYPE0_Msk)) { + return -USB_ERR_REDO; + } + hri_usbendpoint_write_EPCFG_reg(hw, epn, USB_D_EPCFG_CTRL); + bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) + | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + bank[1].PCKSIZE.reg + = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + /* By default, control endpoint accept SETUP and NAK all other token. */ + _usbd_ep_set_out_rdy(epn, 0, false); + _usbd_ep_set_in_rdy(epn, 1, false); + + _usbd_ep_clear_bank_status(epn, 0); + _usbd_ep_clear_bank_status(epn, 1); + + /* Enable SETUP reception for control endpoint. */ + _usb_d_dev_trans_setup(ept); + + } else if (dir) { + if (epcfg & USB_DEVICE_EPCFG_EPTYPE1_Msk) { + return -USB_ERR_REDO; + } + epcfg |= USB_DEVICE_EPCFG_EPTYPE1(ept->flags.bits.eptype); + hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); + + bank[1].PCKSIZE.reg + = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + + /* By default, IN endpoint will NAK all token. */ + _usbd_ep_set_in_rdy(epn, 1, false); + _usbd_ep_clear_bank_status(epn, 1); + + } else { + + if (epcfg & USB_DEVICE_EPCFG_EPTYPE0_Msk) { + return -USB_ERR_REDO; + } + epcfg |= USB_DEVICE_EPCFG_EPTYPE0(ept->flags.bits.eptype); + hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); + + bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) + | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + + /* By default, OUT endpoint will NAK all token. */ + _usbd_ep_set_out_rdy(epn, 0, false); + _usbd_ep_clear_bank_status(epn, 0); + } + + return USB_OK; +} + +void _usb_d_dev_ep_disable(const uint8_t ep) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); + if (_usb_d_dev_ep_is_ctrl(ept)) { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_ALL_INT_FLAGS); + } +} + +/** + * \brief Get endpoint stall status + * \param[in] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \return Stall status. + * \retval \c true Endpoint is stalled. + * \retval \c false Endpoint is not stalled. + */ +static inline int32_t _usb_d_dev_ep_stall_get(struct _usb_d_dev_ep *ept, bool dir) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + return _usbd_ep_is_stalled(epn, dir); +} + +/** + * \brief Set endpoint stall + * \param[in, out] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \return Always 0, success. + */ +static inline int32_t _usb_d_dev_ep_stall_set(struct _usb_d_dev_ep *ept, bool dir) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + _usbd_ep_set_stall(epn, dir, true); + _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); + ept->flags.bits.is_stalled = 1; + /* In stall interrupt abort the transfer. */ + return ERR_NONE; +} + +/** + * \brief Clear endpoint stall + * \param[in, out] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \return Always 0, success. + */ +static inline int32_t _usb_d_dev_ep_stall_clr(struct _usb_d_dev_ep *ept, bool dir) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + bool is_stalled = _usbd_ep_is_stalled(epn, dir); + if (!is_stalled) { + return ERR_NONE; + } + _usbd_ep_set_stall(epn, dir, false); + _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); + if (_usbd_ep_is_stall_sent(epn, dir)) { + _usbd_ep_ack_stall(epn, dir); + _usbd_ep_set_toggle(epn, dir, 0); + } + if (_usb_d_dev_ep_is_ctrl(ept)) { + if ((hri_usbendpoint_read_EPSTATUS_reg(USB, epn) & USB_DEVICE_EPSTATUS_STALLRQ_Msk) == 0) { + ept->flags.bits.is_stalled = 0; + } + } else { + ept->flags.bits.is_stalled = 0; + } + return ERR_NONE; +} + +int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + int32_t rc; + + if (epn > CONF_USB_D_MAX_EP_N) { + return -USB_ERR_PARAM; + } + + if (USB_EP_STALL_SET == ctrl) { + rc = _usb_d_dev_ep_stall_set(ept, dir); + } else if (USB_EP_STALL_CLR == ctrl) { + rc = _usb_d_dev_ep_stall_clr(ept, dir); + } else { + rc = _usb_d_dev_ep_stall_get(ept, dir); + } + return rc; +} + +/** + * \brief Finish the transaction and invoke callback + * \param[in, out] ept Pointer to endpoint information. + * \param[in] code Information code passed. + */ +static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t code) +{ + if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { + return; + } + ept->flags.bits.is_busy = 0; + dev_inst.ep_callbacks.done(ept->ep, code, ept->trans_count); +} + +/** + * \brief Terminate the transaction with specific status code + * \param[in, out] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \param[in] code Information code passed. + */ +static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + ; + const uint8_t intflags[2] = {USB_D_BANK0_INT_FLAGS, USB_D_BANK1_INT_FLAGS}; + if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { + return; + } + /* Stop transfer */ + if (dir) { + /* NAK IN */ + _usbd_ep_set_in_rdy(epn, 1, false); + } else { + /* NAK OUT */ + _usbd_ep_set_out_rdy(epn, 0, false); + } + _usbd_ep_int_ack(epn, intflags[dir]); + _usbd_ep_int_dis(epn, intflags[dir]); + _usb_d_dev_trans_done(ept, code); +} + +int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf) +{ + uint8_t epn = USB_EP_GET_N(ep); + UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; + uint32_t addr = bank[0].ADDR.reg; + uint16_t bytes = bank[0].PCKSIZE.bit.BYTE_COUNT; + + if (epn > CONF_USB_D_MAX_EP_N || !req_buf) { + return -USB_ERR_PARAM; + } + if (!_usbd_ep_is_ctrl(epn)) { + return -USB_ERR_FUNC; + } + if (!_usbd_ep_is_setup(epn)) { + return ERR_NONE; + } + memcpy(req_buf, (void *)addr, 8); + _usbd_ep_ack_setup(epn); + + return bytes; +} + +int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans) +{ + uint8_t epn = USB_EP_GET_N(trans->ep); + bool dir = USB_EP_GET_DIR(trans->ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); + bool size_n_aligned = (trans->size & size_mask); + + bool use_cache = false; + + volatile hal_atomic_t flags; + + if (epn > CONF_USB_D_MAX_EP_N) { + return -USB_ERR_PARAM; + } + + /* Cases that needs cache: + * 1. Buffer not in RAM (cache all). + * 2. IN/OUT with unaligned buffer (cache all). + * 3. OUT with unaligned packet size (cache last packet). + * 4. OUT size < 8 (sub-case for 3). + */ + if (!_usb_is_addr4dma(trans->buf, trans->size) || (!_usb_is_aligned(trans->buf)) + || (!dir && (trans->size < ept->size))) { + if (!ept->cache) { + return -USB_ERR_FUNC; + } + /* Use cache all the time. */ + use_cache = true; + } + if (!dir && size_n_aligned) { + if (!ept->cache) { + return -USB_ERR_PARAM; + } + /* Set 'use_cache' on last packet. */ + } + + /* Check halt */ + if (ept->flags.bits.is_stalled) { + return USB_HALTED; + } + + /* Try to start transactions. */ + + atomic_enter_critical(&flags); + if (_usb_d_dev_ep_is_busy(ept)) { + atomic_leave_critical(&flags); + return USB_BUSY; + } + ept->flags.bits.is_busy = 1; + atomic_leave_critical(&flags); + + /* Copy transaction information. */ + ept->trans_buf = trans->buf; + ept->trans_size = trans->size; + ept->trans_count = 0; + + ept->flags.bits.dir = dir; + ept->flags.bits.use_cache = use_cache; + ept->flags.bits.need_zlp = (trans->zlp && (!size_n_aligned)); + + if (dir) { + _usb_d_dev_in_next(ept, false); + } else { + _usb_d_dev_out_next(ept, false); + } + + return ERR_NONE; +} + +void _usb_d_dev_ep_abort(const uint8_t ep) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + if (epn > CONF_USB_D_MAX_EP_N) { + return; + } + _usb_d_dev_trans_stop(ept, dir, USB_TRANS_ABORT); +} + +int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + bool busy, stall; + + if (epn > CONF_USB_D_MAX_EP_N) { + return USB_ERR_PARAM; + } + busy = ept->flags.bits.is_busy; + stall = ept->flags.bits.is_stalled; + if (stat) { + stat->stall = stall; + stat->busy = busy; + stat->setup = USB->DEVICE.DeviceEndpoint[epn].EPINTFLAG.bit.RXSTP; + stat->dir = ept->flags.bits.dir; + stat->size = ept->trans_size; + stat->count = ept->trans_count; + stat->ep = ep; + stat->xtype = ept->flags.bits.eptype - 1; + } + if (stall) { + return USB_HALTED; + } + if (busy) { + return USB_BUSY; + } + return USB_OK; +} + +void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) +{ + FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; + if (type == USB_D_CB_EVENT) { + dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)f; + } else if (type == USB_D_CB_SOF) { + dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)f; + } +} + +void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func) +{ + FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; + if (type == USB_D_DEV_EP_CB_SETUP) { + dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)f; + } else if (type == USB_D_DEV_EP_CB_MORE) { + dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)f; + } else if (type == USB_D_DEV_EP_CB_DONE) { + dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)f; + } +} + +/** +* \brief USB interrupt handler +*/ +void USB_Handler(void) +{ + + _usb_d_dev_handler(); +} diff --git a/atmel-samd/asf4/samd21/hri/hri_ac_d21.h b/atmel-samd/asf4/samd21/hri/hri_ac_d21.h new file mode 100644 index 0000000000000..3efd86b22749b --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_ac_d21.h @@ -0,0 +1,1586 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_AC_COMPONENT_ +#ifndef _HRI_AC_D21_H_INCLUDED_ +#define _HRI_AC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_statusc_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw) +{ + while (((const Ac *)hw)->STATUSB.bit.SYNCBUSY) + ; +} + +static inline bool hri_ac_is_syncing(const void *const hw) +{ + return ((const Ac *)hw)->STATUSB.bit.SYNCBUSY; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_RUNSTDBY_Msk; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_RUNSTDBY_Msk) >> AC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_RUNSTDBY_Msk; + tmp |= value << AC_CTRLA_RUNSTDBY_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_RUNSTDBY_Msk; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_RUNSTDBY_Msk; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_LPMUX_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_LPMUX; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_LPMUX_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_LPMUX) >> AC_CTRLA_LPMUX_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_LPMUX_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_LPMUX; + tmp |= value << AC_CTRLA_LPMUX_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_LPMUX_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_LPMUX; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_LPMUX_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_LPMUX; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST) >> AC_COMPCTRL_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST; + tmp |= value << AC_COMPCTRL_HYST_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline bool hri_ac_get_STATUSB_SYNCBUSY_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_SYNCBUSY) >> AC_STATUSB_SYNCBUSY_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_STATUSC_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_STATE0) >> AC_STATUSC_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSC_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_STATE1) >> AC_STATUSC_STATE1_Pos; +} + +static inline hri_ac_statusc_reg_t hri_ac_get_STATUSC_WSTATE0_bf(const void *const hw, hri_ac_statusc_reg_t mask) +{ + return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_WSTATE0(mask)) >> AC_STATUSC_WSTATE0_Pos; +} + +static inline hri_ac_statusc_reg_t hri_ac_read_STATUSC_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_WSTATE0_Msk) >> AC_STATUSC_WSTATE0_Pos; +} + +static inline hri_ac_statusc_reg_t hri_ac_get_STATUSC_reg(const void *const hw, hri_ac_statusc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusc_reg_t hri_ac_read_STATUSC_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_D21_H_INCLUDED */ +#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_adc_d21.h b/atmel-samd/asf4/samd21/hri/hri_adc_d21.h new file mode 100644 index 0000000000000..f511c59f4df15 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_adc_d21.h @@ -0,0 +1,2513 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_ADC_COMPONENT_ +#ifndef _HRI_ADC_D21_H_INCLUDED_ +#define _HRI_ADC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrlb_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_inputctrl_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_ctrla_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_status_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; +typedef uint8_t hri_adc_winctrl_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw) +{ + while (((const Adc *)hw)->STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_adc_is_syncing(const void *const hw) +{ + return ((const Adc *)hw)->STATUS.bit.SYNCBUSY; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_SYNCRDY; +} + +static inline bool hri_adc_get_INTEN_SYNCRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_SYNCRDY) >> ADC_INTENSET_SYNCRDY_Pos; +} + +static inline void hri_adc_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_SYNCRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_SYNCRDY; + } +} + +static inline void hri_adc_clear_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_SYNCRDY; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_SYNCRDY) >> ADC_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_SYNCRDY; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_SYNCRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_SYNCRDY) >> ADC_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_SYNCRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_SYNCRDY; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_CTRLB_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_DIFFMODE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_DIFFMODE) >> ADC_CTRLB_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_DIFFMODE; + tmp |= value << ADC_CTRLB_DIFFMODE_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_DIFFMODE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_DIFFMODE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_LEFTADJ; + tmp |= value << ADC_CTRLB_LEFTADJ_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_FREERUN; + tmp |= value << ADC_CTRLB_FREERUN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_CORREN; + tmp |= value << ADC_CTRLB_CORREN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_RESSEL_Msk; + tmp |= ADC_CTRLB_RESSEL(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_PRESCALER_Msk; + tmp |= ADC_CTRLB_PRESCALER(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINCTRL.reg |= ADC_WINCTRL_WINMODE(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winctrl_reg_t hri_adc_get_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINCTRL.reg; + tmp = (tmp & ADC_WINCTRL_WINMODE(mask)) >> ADC_WINCTRL_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINCTRL.reg; + tmp &= ~ADC_WINCTRL_WINMODE_Msk; + tmp |= ADC_WINCTRL_WINMODE(data); + ((Adc *)hw)->WINCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINCTRL.reg &= ~ADC_WINCTRL_WINMODE(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINCTRL.reg ^= ADC_WINCTRL_WINMODE(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winctrl_reg_t hri_adc_read_WINCTRL_WINMODE_bf(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINCTRL.reg; + tmp = (tmp & ADC_WINCTRL_WINMODE_Msk) >> ADC_WINCTRL_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winctrl_reg_t hri_adc_get_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winctrl_reg_t hri_adc_read_WINCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->WINCTRL.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_INPUTSCAN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_INPUTSCAN_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_INPUTSCAN(mask)) >> ADC_INPUTCTRL_INPUTSCAN_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_INPUTSCAN_Msk; + tmp |= ADC_INPUTCTRL_INPUTSCAN(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_INPUTSCAN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_INPUTSCAN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_INPUTSCAN_bf(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_INPUTSCAN_Msk) >> ADC_INPUTCTRL_INPUTSCAN_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_INPUTOFFSET(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_INPUTOFFSET(mask)) >> ADC_INPUTCTRL_INPUTOFFSET_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_INPUTOFFSET_Msk; + tmp |= ADC_INPUTCTRL_INPUTOFFSET(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_INPUTOFFSET(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_INPUTOFFSET(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_INPUTOFFSET_bf(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_INPUTOFFSET_Msk) >> ADC_INPUTCTRL_INPUTOFFSET_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_GAIN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_GAIN(mask)) >> ADC_INPUTCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_GAIN_Msk; + tmp |= ADC_INPUTCTRL_GAIN(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_GAIN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_GAIN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_GAIN_bf(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_GAIN_Msk) >> ADC_INPUTCTRL_GAIN_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_SYNCEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_SYNCEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_SYNCEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_SYNCEI) >> ADC_EVCTRL_SYNCEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_SYNCEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_SYNCEI; + tmp |= value << ADC_EVCTRL_SYNCEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_SYNCEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_SYNCEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_SYNCEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_SYNCEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_LINEARITY_CAL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_LINEARITY_CAL(mask)) >> ADC_CALIB_LINEARITY_CAL_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_LINEARITY_CAL_Msk; + tmp |= ADC_CALIB_LINEARITY_CAL(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_LINEARITY_CAL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_LINEARITY_CAL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_LINEARITY_CAL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_LINEARITY_CAL_Msk) >> ADC_CALIB_LINEARITY_CAL_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIAS_CAL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIAS_CAL(mask)) >> ADC_CALIB_BIAS_CAL_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIAS_CAL_Msk; + tmp |= ADC_CALIB_BIAS_CAL(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIAS_CAL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIAS_CAL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIAS_CAL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIAS_CAL_Msk) >> ADC_CALIB_BIAS_CAL_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline bool hri_adc_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_SYNCBUSY) >> ADC_STATUS_SYNCBUSY_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->STATUS.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + hri_adc_wait_for_sync(hw); + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + hri_adc_wait_for_sync(hw); + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_D21_H_INCLUDED */ +#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_d21.h b/atmel-samd/asf4/samd21/hri/hri_d21.h new file mode 100644 index 0000000000000..adaf36067119f --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_d21.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief SAM D21 HRI top-level header file + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HRI_D21_H_INCLUDED_ +#define _HRI_D21_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_D21_H_INCLUDED_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_dac_d21.h b/atmel-samd/asf4/samd21/hri/hri_dac_d21.h new file mode 100644 index 0000000000000..f4444bf1112fc --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_dac_d21.h @@ -0,0 +1,1033 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_DAC_COMPONENT_ +#ifndef _HRI_DAC_D21_H_INCLUDED_ +#define _HRI_DAC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw) +{ + while (((const Dac *)hw)->STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_dac_is_syncing(const void *const hw) +{ + return ((const Dac *)hw)->STATUS.bit.SYNCBUSY; +} + +static inline void hri_dac_set_INTEN_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN) >> DAC_INTENSET_UNDERRUN_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; +} + +static inline void hri_dac_set_INTEN_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; +} + +static inline bool hri_dac_get_INTEN_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY) >> DAC_INTENSET_EMPTY_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; +} + +static inline void hri_dac_set_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_SYNCRDY; +} + +static inline bool hri_dac_get_INTEN_SYNCRDY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_SYNCRDY) >> DAC_INTENSET_SYNCRDY_Pos; +} + +static inline void hri_dac_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_SYNCRDY; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_SYNCRDY; + } +} + +static inline void hri_dac_clear_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_SYNCRDY; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; +} + +static inline bool hri_dac_get_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_SYNCRDY) >> DAC_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_dac_clear_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_SYNCRDY; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; +} + +static inline bool hri_dac_get_interrupt_EMPTY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; +} + +static inline bool hri_dac_get_interrupt_SYNCRDY_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_SYNCRDY) >> DAC_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_dac_clear_interrupt_SYNCRDY_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_SYNCRDY; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_RUNSTDBY; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_RUNSTDBY) >> DAC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_RUNSTDBY; + tmp |= value << DAC_CTRLA_RUNSTDBY_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_RUNSTDBY; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_RUNSTDBY; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_EOEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_EOEN) >> DAC_CTRLB_EOEN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_EOEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_EOEN; + tmp |= value << DAC_CTRLB_EOEN_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_EOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_EOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_IOEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_IOEN) >> DAC_CTRLB_IOEN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_IOEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_IOEN; + tmp |= value << DAC_CTRLB_IOEN_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_IOEN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_IOEN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_LEFTADJ) >> DAC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_LEFTADJ; + tmp |= value << DAC_CTRLB_LEFTADJ_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_VPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_VPD) >> DAC_CTRLB_VPD_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_VPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_VPD; + tmp |= value << DAC_CTRLB_VPD_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_VPD_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_VPD; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_BDWP_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_BDWP; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_BDWP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_BDWP) >> DAC_CTRLB_BDWP_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_BDWP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_BDWP; + tmp |= value << DAC_CTRLB_BDWP_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_BDWP_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_BDWP; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_BDWP_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_BDWP; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI) >> DAC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI; + tmp |= value << DAC_EVCTRL_STARTEI_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO) >> DAC_EVCTRL_EMPTYEO_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO; + tmp |= value << DAC_EVCTRL_EMPTYEO_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->DATA.reg |= DAC_DATA_DATA(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_data_reg_t hri_dac_get_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->DATA.reg; + tmp = (tmp & DAC_DATA_DATA(mask)) >> DAC_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dac_write_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->DATA.reg; + tmp &= ~DAC_DATA_DATA_Msk; + tmp |= DAC_DATA_DATA(data); + ((Dac *)hw)->DATA.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->DATA.reg &= ~DAC_DATA_DATA(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->DATA.reg ^= DAC_DATA_DATA(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_data_reg_t hri_dac_read_DATA_DATA_bf(const void *const hw) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->DATA.reg; + tmp = (tmp & DAC_DATA_DATA_Msk) >> DAC_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dac_set_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_data_reg_t hri_dac_get_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_data_reg_t hri_dac_read_DATA_reg(const void *const hw) +{ + return ((Dac *)hw)->DATA.reg; +} + +static inline void hri_dac_set_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->DATABUF.reg |= DAC_DATABUF_DATABUF(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_databuf_reg_t hri_dac_get_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->DATABUF.reg; + tmp = (tmp & DAC_DATABUF_DATABUF(mask)) >> DAC_DATABUF_DATABUF_Pos; + return tmp; +} + +static inline void hri_dac_write_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->DATABUF.reg; + tmp &= ~DAC_DATABUF_DATABUF_Msk; + tmp |= DAC_DATABUF_DATABUF(data); + ((Dac *)hw)->DATABUF.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->DATABUF.reg &= ~DAC_DATABUF_DATABUF(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw); + ((Dac *)hw)->DATABUF.reg ^= DAC_DATABUF_DATABUF(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_databuf_reg_t hri_dac_read_DATABUF_DATABUF_bf(const void *const hw) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw); + tmp = ((Dac *)hw)->DATABUF.reg; + tmp = (tmp & DAC_DATABUF_DATABUF_Msk) >> DAC_DATABUF_DATABUF_Pos; + return tmp; +} + +static inline void hri_dac_set_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_databuf_reg_t hri_dac_get_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DATABUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_databuf_reg_t hri_dac_read_DATABUF_reg(const void *const hw) +{ + return ((Dac *)hw)->DATABUF.reg; +} + +static inline bool hri_dac_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + hri_dac_wait_for_sync(hw); + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_SYNCBUSY) >> DAC_STATUS_SYNCBUSY_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_D21_H_INCLUDED */ +#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h b/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h new file mode 100644 index 0000000000000..2290917013663 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h @@ -0,0 +1,4308 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_D21_H_INCLUDED_ +#define _HRI_DMAC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrlb_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrla_reg_t; +typedef uint8_t hri_dmac_chid_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmac_qosctrl_reg_t; + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->CHINTENSET.reg = data; + ((Dmac *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_CRCENABLE; + tmp |= value << DMAC_CTRL_CRCENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; + tmp |= DMAC_QOSCTRL_WRBQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_FQOS_Msk; + tmp |= DMAC_QOSCTRL_FQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= ~DMAC_QOSCTRL_DQOS_Msk; + tmp |= DMAC_QOSCTRL_DQOS(data); + ((Dmac *)hw)->QOSCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->QOSCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->QOSCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= ~DMAC_CHID_ID_Msk; + tmp |= DMAC_CHID_ID(data); + ((Dmac *)hw)->CHID.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHID.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHID.reg; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVIE; + tmp |= value << DMAC_CHCTRLB_EVIE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVOE; + tmp |= value << DMAC_CHCTRLB_EVOE_Pos; + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_EVACT_Msk; + tmp |= DMAC_CHCTRLB_EVACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_LVL_Msk; + tmp |= DMAC_CHCTRLB_LVL(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLB_TRIGSRC(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; + tmp |= DMAC_CHCTRLB_TRIGACT(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHCTRLB.reg; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CHSTATUS.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_D21_H_INCLUDED */ +#endif /* _SAMD21_DMAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h b/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h new file mode 100644 index 0000000000000..cd001e0a77b9e --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h @@ -0,0 +1,979 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_DSU_COMPONENT_ +#ifndef _HRI_DSU_D21_H_INCLUDED_ +#define _HRI_DSU_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY_EPRES_bit(const void *const hw, uint8_t index) +{ + return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_EPRES) >> DSU_ENTRY_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY_FMT_bit(const void *const hw, uint8_t index) +{ + return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_FMT) >> DSU_ENTRY_FMT_Pos; +} + +static inline hri_dsu_entry_reg_t hri_dsu_get_ENTRY_ADDOFF_bf(const void *const hw, uint8_t index, + hri_dsu_entry_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_ADDOFF(mask)) >> DSU_ENTRY_ADDOFF_Pos; +} + +static inline hri_dsu_entry_reg_t hri_dsu_read_ENTRY_ADDOFF_bf(const void *const hw, uint8_t index) +{ + return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_ADDOFF_Msk) >> DSU_ENTRY_ADDOFF_Pos; +} + +static inline hri_dsu_entry_reg_t hri_dsu_get_ENTRY_reg(const void *const hw, uint8_t index, hri_dsu_entry_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry_reg_t hri_dsu_read_ENTRY_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->ENTRY[index].reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_D21_H_INCLUDED */ +#endif /* _SAMD21_DSU_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_eic_d21.h b/atmel-samd/asf4/samd21/hri/hri_eic_d21.h new file mode 100644 index 0000000000000..89919db6e26ab --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_eic_d21.h @@ -0,0 +1,3233 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_EIC_COMPONENT_ +#ifndef _HRI_EIC_D21_H_INCLUDED_ +#define _HRI_EIC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_wakeup_reg_t; +typedef uint8_t hri_eic_ctrl_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; +typedef uint8_t hri_eic_nmiflag_reg_t; +typedef uint8_t hri_eic_status_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw) +{ + while (((const Eic *)hw)->STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_eic_is_syncing(const void *const hw) +{ + return ((const Eic *)hw)->STATUS.bit.SYNCBUSY; +} + +static inline void hri_eic_set_INTEN_EXTINT0_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT0; +} + +static inline bool hri_eic_get_INTEN_EXTINT0_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT0) >> EIC_INTENSET_EXTINT0_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT0; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT0; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT0_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT0; +} + +static inline void hri_eic_set_INTEN_EXTINT1_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT1; +} + +static inline bool hri_eic_get_INTEN_EXTINT1_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT1) >> EIC_INTENSET_EXTINT1_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT1; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT1; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT1_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT1; +} + +static inline void hri_eic_set_INTEN_EXTINT2_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT2; +} + +static inline bool hri_eic_get_INTEN_EXTINT2_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT2) >> EIC_INTENSET_EXTINT2_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT2; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT2; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT2_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT2; +} + +static inline void hri_eic_set_INTEN_EXTINT3_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT3; +} + +static inline bool hri_eic_get_INTEN_EXTINT3_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT3) >> EIC_INTENSET_EXTINT3_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT3; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT3; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT3_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT3; +} + +static inline void hri_eic_set_INTEN_EXTINT4_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT4; +} + +static inline bool hri_eic_get_INTEN_EXTINT4_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT4) >> EIC_INTENSET_EXTINT4_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT4; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT4; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT4_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT4; +} + +static inline void hri_eic_set_INTEN_EXTINT5_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT5; +} + +static inline bool hri_eic_get_INTEN_EXTINT5_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT5) >> EIC_INTENSET_EXTINT5_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT5; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT5; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT5_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT5; +} + +static inline void hri_eic_set_INTEN_EXTINT6_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT6; +} + +static inline bool hri_eic_get_INTEN_EXTINT6_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT6) >> EIC_INTENSET_EXTINT6_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT6; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT6; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT6_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT6; +} + +static inline void hri_eic_set_INTEN_EXTINT7_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT7; +} + +static inline bool hri_eic_get_INTEN_EXTINT7_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT7) >> EIC_INTENSET_EXTINT7_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT7; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT7; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT7_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT7; +} + +static inline void hri_eic_set_INTEN_EXTINT8_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT8; +} + +static inline bool hri_eic_get_INTEN_EXTINT8_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT8) >> EIC_INTENSET_EXTINT8_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT8; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT8; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT8_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT8; +} + +static inline void hri_eic_set_INTEN_EXTINT9_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT9; +} + +static inline bool hri_eic_get_INTEN_EXTINT9_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT9) >> EIC_INTENSET_EXTINT9_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT9; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT9; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT9_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT9; +} + +static inline void hri_eic_set_INTEN_EXTINT10_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT10; +} + +static inline bool hri_eic_get_INTEN_EXTINT10_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT10) >> EIC_INTENSET_EXTINT10_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT10; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT10; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT10_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT10; +} + +static inline void hri_eic_set_INTEN_EXTINT11_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT11; +} + +static inline bool hri_eic_get_INTEN_EXTINT11_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT11) >> EIC_INTENSET_EXTINT11_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT11; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT11; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT11_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT11; +} + +static inline void hri_eic_set_INTEN_EXTINT12_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT12; +} + +static inline bool hri_eic_get_INTEN_EXTINT12_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT12) >> EIC_INTENSET_EXTINT12_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT12_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT12; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT12; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT12_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT12; +} + +static inline void hri_eic_set_INTEN_EXTINT13_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT13; +} + +static inline bool hri_eic_get_INTEN_EXTINT13_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT13) >> EIC_INTENSET_EXTINT13_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT13_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT13; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT13; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT13_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT13; +} + +static inline void hri_eic_set_INTEN_EXTINT14_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT14; +} + +static inline bool hri_eic_get_INTEN_EXTINT14_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT14) >> EIC_INTENSET_EXTINT14_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT14_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT14; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT14; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT14_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT14; +} + +static inline void hri_eic_set_INTEN_EXTINT15_bit(const void *const hw) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT15; +} + +static inline bool hri_eic_get_INTEN_EXTINT15_bit(const void *const hw) +{ + return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT15) >> EIC_INTENSET_EXTINT15_Pos; +} + +static inline void hri_eic_write_INTEN_EXTINT15_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT15; + } else { + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT15; + } +} + +static inline void hri_eic_clear_INTEN_EXTINT15_bit(const void *const hw) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT15; +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT0_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT0) >> EIC_INTFLAG_EXTINT0_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT0_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT0; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT1_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT1) >> EIC_INTFLAG_EXTINT1_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT1_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT1; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT2_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT2) >> EIC_INTFLAG_EXTINT2_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT2_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT2; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT3_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT3) >> EIC_INTFLAG_EXTINT3_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT3_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT3; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT4_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT4) >> EIC_INTFLAG_EXTINT4_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT4_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT4; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT5_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT5) >> EIC_INTFLAG_EXTINT5_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT5_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT5; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT6_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT6) >> EIC_INTFLAG_EXTINT6_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT6_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT6; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT7_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT7) >> EIC_INTFLAG_EXTINT7_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT7_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT7; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT8_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT8) >> EIC_INTFLAG_EXTINT8_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT8_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT8; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT9_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT9) >> EIC_INTFLAG_EXTINT9_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT9_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT9; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT10_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT10) >> EIC_INTFLAG_EXTINT10_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT10_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT10; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT11_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT11) >> EIC_INTFLAG_EXTINT11_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT11_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT11; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT12_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT12) >> EIC_INTFLAG_EXTINT12_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT12_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT12; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT13_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT13) >> EIC_INTFLAG_EXTINT13_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT13_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT13; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT14_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT14) >> EIC_INTFLAG_EXTINT14_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT14_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT14; +} + +static inline bool hri_eic_get_INTFLAG_EXTINT15_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT15) >> EIC_INTFLAG_EXTINT15_Pos; +} + +static inline void hri_eic_clear_INTFLAG_EXTINT15_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT15; +} + +static inline bool hri_eic_get_interrupt_EXTINT0_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT0) >> EIC_INTFLAG_EXTINT0_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT0_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT0; +} + +static inline bool hri_eic_get_interrupt_EXTINT1_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT1) >> EIC_INTFLAG_EXTINT1_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT1_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT1; +} + +static inline bool hri_eic_get_interrupt_EXTINT2_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT2) >> EIC_INTFLAG_EXTINT2_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT2_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT2; +} + +static inline bool hri_eic_get_interrupt_EXTINT3_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT3) >> EIC_INTFLAG_EXTINT3_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT3_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT3; +} + +static inline bool hri_eic_get_interrupt_EXTINT4_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT4) >> EIC_INTFLAG_EXTINT4_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT4_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT4; +} + +static inline bool hri_eic_get_interrupt_EXTINT5_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT5) >> EIC_INTFLAG_EXTINT5_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT5_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT5; +} + +static inline bool hri_eic_get_interrupt_EXTINT6_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT6) >> EIC_INTFLAG_EXTINT6_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT6_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT6; +} + +static inline bool hri_eic_get_interrupt_EXTINT7_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT7) >> EIC_INTFLAG_EXTINT7_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT7_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT7; +} + +static inline bool hri_eic_get_interrupt_EXTINT8_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT8) >> EIC_INTFLAG_EXTINT8_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT8_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT8; +} + +static inline bool hri_eic_get_interrupt_EXTINT9_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT9) >> EIC_INTFLAG_EXTINT9_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT9_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT9; +} + +static inline bool hri_eic_get_interrupt_EXTINT10_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT10) >> EIC_INTFLAG_EXTINT10_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT10_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT10; +} + +static inline bool hri_eic_get_interrupt_EXTINT11_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT11) >> EIC_INTFLAG_EXTINT11_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT11_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT11; +} + +static inline bool hri_eic_get_interrupt_EXTINT12_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT12) >> EIC_INTFLAG_EXTINT12_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT12_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT12; +} + +static inline bool hri_eic_get_interrupt_EXTINT13_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT13) >> EIC_INTFLAG_EXTINT13_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT13_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT13; +} + +static inline bool hri_eic_get_interrupt_EXTINT14_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT14) >> EIC_INTFLAG_EXTINT14_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT14_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT14; +} + +static inline bool hri_eic_get_interrupt_EXTINT15_bit(const void *const hw) +{ + return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT15) >> EIC_INTFLAG_EXTINT15_Pos; +} + +static inline void hri_eic_clear_interrupt_EXTINT15_bit(const void *const hw) +{ + ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT15; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_CTRL_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw); + ((Eic *)hw)->CTRL.reg |= EIC_CTRL_SWRST; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw); + tmp = ((Eic *)hw)->CTRL.reg; + tmp = (tmp & EIC_CTRL_SWRST) >> EIC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRL_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw); + ((Eic *)hw)->CTRL.reg |= EIC_CTRL_ENABLE; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw); + tmp = ((Eic *)hw)->CTRL.reg; + tmp = (tmp & EIC_CTRL_ENABLE) >> EIC_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw); + tmp = ((Eic *)hw)->CTRL.reg; + tmp &= ~EIC_CTRL_ENABLE; + tmp |= value << EIC_CTRL_ENABLE_Pos; + ((Eic *)hw)->CTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRL_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw); + ((Eic *)hw)->CTRL.reg &= ~EIC_CTRL_ENABLE; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw); + ((Eic *)hw)->CTRL.reg ^= EIC_CTRL_ENABLE; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrl_reg_t hri_eic_get_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrl_reg_t hri_eic_read_CTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->CTRL.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO0) >> EIC_EVCTRL_EXTINTEO0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO0; + tmp |= value << EIC_EVCTRL_EXTINTEO0_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO1) >> EIC_EVCTRL_EXTINTEO1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO1; + tmp |= value << EIC_EVCTRL_EXTINTEO1_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO2_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO2) >> EIC_EVCTRL_EXTINTEO2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO2; + tmp |= value << EIC_EVCTRL_EXTINTEO2_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO2_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO2_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO3_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO3) >> EIC_EVCTRL_EXTINTEO3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO3; + tmp |= value << EIC_EVCTRL_EXTINTEO3_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO3_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO3_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO4_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO4) >> EIC_EVCTRL_EXTINTEO4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO4; + tmp |= value << EIC_EVCTRL_EXTINTEO4_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO4_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO4_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO5_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO5) >> EIC_EVCTRL_EXTINTEO5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO5; + tmp |= value << EIC_EVCTRL_EXTINTEO5_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO5_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO5_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO6_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO6) >> EIC_EVCTRL_EXTINTEO6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO6; + tmp |= value << EIC_EVCTRL_EXTINTEO6_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO6_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO6_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO7_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO7) >> EIC_EVCTRL_EXTINTEO7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO7; + tmp |= value << EIC_EVCTRL_EXTINTEO7_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO7_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO7_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO8_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO8; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO8) >> EIC_EVCTRL_EXTINTEO8_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO8; + tmp |= value << EIC_EVCTRL_EXTINTEO8_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO8_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO8; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO8_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO8; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO9_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO9; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO9) >> EIC_EVCTRL_EXTINTEO9_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO9; + tmp |= value << EIC_EVCTRL_EXTINTEO9_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO9_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO9; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO9_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO9; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO10_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO10; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO10) >> EIC_EVCTRL_EXTINTEO10_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO10; + tmp |= value << EIC_EVCTRL_EXTINTEO10_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO10_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO10; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO10_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO10; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO11_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO11; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO11) >> EIC_EVCTRL_EXTINTEO11_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO11; + tmp |= value << EIC_EVCTRL_EXTINTEO11_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO11_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO11; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO11_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO11; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO12_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO12; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO12) >> EIC_EVCTRL_EXTINTEO12_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO12; + tmp |= value << EIC_EVCTRL_EXTINTEO12_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO12_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO12; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO12_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO12; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO13_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO13; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO13) >> EIC_EVCTRL_EXTINTEO13_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO13; + tmp |= value << EIC_EVCTRL_EXTINTEO13_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO13_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO13; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO13_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO13; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO14_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO14; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO14) >> EIC_EVCTRL_EXTINTEO14_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO14; + tmp |= value << EIC_EVCTRL_EXTINTEO14_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO14_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO14; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO14_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO14; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO15_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO15; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_EVCTRL_EXTINTEO15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO15) >> EIC_EVCTRL_EXTINTEO15_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO15; + tmp |= value << EIC_EVCTRL_EXTINTEO15_Pos; + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO15_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO15; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO15_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO15; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN0) >> EIC_WAKEUP_WAKEUPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN0; + tmp |= value << EIC_WAKEUP_WAKEUPEN0_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN1) >> EIC_WAKEUP_WAKEUPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN1; + tmp |= value << EIC_WAKEUP_WAKEUPEN1_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN2_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN2) >> EIC_WAKEUP_WAKEUPEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN2; + tmp |= value << EIC_WAKEUP_WAKEUPEN2_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN2_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN2_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN3_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN3) >> EIC_WAKEUP_WAKEUPEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN3; + tmp |= value << EIC_WAKEUP_WAKEUPEN3_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN3_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN3_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN4_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN4) >> EIC_WAKEUP_WAKEUPEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN4; + tmp |= value << EIC_WAKEUP_WAKEUPEN4_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN4_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN4_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN5_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN5) >> EIC_WAKEUP_WAKEUPEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN5; + tmp |= value << EIC_WAKEUP_WAKEUPEN5_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN5_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN5_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN6_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN6) >> EIC_WAKEUP_WAKEUPEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN6; + tmp |= value << EIC_WAKEUP_WAKEUPEN6_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN6_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN6_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN7_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN7) >> EIC_WAKEUP_WAKEUPEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN7; + tmp |= value << EIC_WAKEUP_WAKEUPEN7_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN7_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN7_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN8_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN8; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN8) >> EIC_WAKEUP_WAKEUPEN8_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN8; + tmp |= value << EIC_WAKEUP_WAKEUPEN8_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN8_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN8; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN8_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN8; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN9_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN9; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN9) >> EIC_WAKEUP_WAKEUPEN9_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN9; + tmp |= value << EIC_WAKEUP_WAKEUPEN9_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN9_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN9; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN9_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN9; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN10_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN10; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN10) >> EIC_WAKEUP_WAKEUPEN10_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN10; + tmp |= value << EIC_WAKEUP_WAKEUPEN10_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN10_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN10; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN10_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN10; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN11_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN11; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN11) >> EIC_WAKEUP_WAKEUPEN11_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN11; + tmp |= value << EIC_WAKEUP_WAKEUPEN11_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN11_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN11; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN11_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN11; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN12_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN12; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN12) >> EIC_WAKEUP_WAKEUPEN12_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN12; + tmp |= value << EIC_WAKEUP_WAKEUPEN12_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN12_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN12; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN12_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN12; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN13_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN13; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN13) >> EIC_WAKEUP_WAKEUPEN13_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN13; + tmp |= value << EIC_WAKEUP_WAKEUPEN13_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN13_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN13; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN13_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN13; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN14_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN14; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN14) >> EIC_WAKEUP_WAKEUPEN14_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN14; + tmp |= value << EIC_WAKEUP_WAKEUPEN14_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN14_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN14; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN14_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN14; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_WAKEUPEN15_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN15; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_WAKEUP_WAKEUPEN15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp = (tmp & EIC_WAKEUP_WAKEUPEN15) >> EIC_WAKEUP_WAKEUPEN15_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_WAKEUP_WAKEUPEN15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= ~EIC_WAKEUP_WAKEUPEN15; + tmp |= value << EIC_WAKEUP_WAKEUPEN15_Pos; + ((Eic *)hw)->WAKEUP.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_WAKEUPEN15_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN15; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_WAKEUPEN15_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN15; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_wakeup_reg_t hri_eic_get_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->WAKEUP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->WAKEUP.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_wakeup_reg_t hri_eic_read_WAKEUP_reg(const void *const hw) +{ + return ((Eic *)hw)->WAKEUP.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +static inline bool hri_eic_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Eic *)hw)->STATUS.reg & EIC_STATUS_SYNCBUSY) >> EIC_STATUS_SYNCBUSY_Pos; +} + +static inline hri_eic_status_reg_t hri_eic_get_STATUS_reg(const void *const hw, hri_eic_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_status_reg_t hri_eic_read_STATUS_reg(const void *const hw) +{ + return ((Eic *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_D21_H_INCLUDED */ +#endif /* _SAMD21_EIC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h b/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h new file mode 100644 index 0000000000000..a624728b77e33 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h @@ -0,0 +1,1729 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_D21_H_INCLUDED_ +#define _HRI_EVSYS_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_evsys_user_reg_t; +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_chstatus_reg_t; +typedef uint32_t hri_evsys_intenset_reg_t; +typedef uint32_t hri_evsys_intflag_reg_t; +typedef uint8_t hri_evsys_ctrl_reg_t; + +static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; +} + +static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; + } +} + +static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; +} + +static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; +} + +static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; + } +} + +static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; +} + +static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; +} + +static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; + } +} + +static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; +} + +static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; +} + +static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; + } +} + +static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; +} + +static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; +} + +static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; + } +} + +static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; +} + +static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; +} + +static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; + } +} + +static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; +} + +static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; +} + +static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; + } +} + +static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; +} + +static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; +} + +static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; + } +} + +static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; +} + +static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; +} + +static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; + } +} + +static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; +} + +static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; +} + +static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; + } +} + +static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; +} + +static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; +} + +static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; + } +} + +static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; +} + +static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; +} + +static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; + } +} + +static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; +} + +static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; +} + +static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; + } +} + +static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; +} + +static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; +} + +static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; + } +} + +static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; +} + +static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; +} + +static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; + } +} + +static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; +} + +static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; +} + +static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; + } +} + +static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; +} + +static inline void hri_evsys_set_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; +} + +static inline bool hri_evsys_get_INTEN_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR8) >> EVSYS_INTENSET_OVR8_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; + } +} + +static inline void hri_evsys_clear_INTEN_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; +} + +static inline void hri_evsys_set_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; +} + +static inline bool hri_evsys_get_INTEN_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR9) >> EVSYS_INTENSET_OVR9_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; + } +} + +static inline void hri_evsys_clear_INTEN_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; +} + +static inline void hri_evsys_set_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; +} + +static inline bool hri_evsys_get_INTEN_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR10) >> EVSYS_INTENSET_OVR10_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; + } +} + +static inline void hri_evsys_clear_INTEN_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; +} + +static inline void hri_evsys_set_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; +} + +static inline bool hri_evsys_get_INTEN_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR11) >> EVSYS_INTENSET_OVR11_Pos; +} + +static inline void hri_evsys_write_INTEN_OVR11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; + } +} + +static inline void hri_evsys_clear_INTEN_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; +} + +static inline void hri_evsys_set_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; +} + +static inline bool hri_evsys_get_INTEN_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD8) >> EVSYS_INTENSET_EVD8_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD8_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; + } +} + +static inline void hri_evsys_clear_INTEN_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; +} + +static inline void hri_evsys_set_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; +} + +static inline bool hri_evsys_get_INTEN_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD9) >> EVSYS_INTENSET_EVD9_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD9_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; + } +} + +static inline void hri_evsys_clear_INTEN_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; +} + +static inline void hri_evsys_set_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; +} + +static inline bool hri_evsys_get_INTEN_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD10) >> EVSYS_INTENSET_EVD10_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD10_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; + } +} + +static inline void hri_evsys_clear_INTEN_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; +} + +static inline void hri_evsys_set_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; +} + +static inline bool hri_evsys_get_INTEN_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD11) >> EVSYS_INTENSET_EVD11_Pos; +} + +static inline void hri_evsys_write_INTEN_EVD11_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; + } else { + ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; + } +} + +static inline void hri_evsys_clear_INTEN_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; +} + +static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENSET.reg = mask; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTENSET.reg; +} + +static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) +{ + ((Evsys *)hw)->INTENSET.reg = data; + ((Evsys *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) +{ + ((Evsys *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_INTFLAG_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_INTFLAG_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_INTFLAG_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_INTFLAG_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_INTFLAG_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_INTFLAG_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_INTFLAG_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_INTFLAG_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_INTFLAG_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; +} + +static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; +} + +static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; +} + +static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; +} + +static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; +} + +static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; +} + +static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; +} + +static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; +} + +static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; +} + +static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; +} + +static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; +} + +static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; +} + +static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; +} + +static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; +} + +static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; +} + +static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; +} + +static inline bool hri_evsys_get_interrupt_OVR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; +} + +static inline bool hri_evsys_get_interrupt_OVR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; +} + +static inline bool hri_evsys_get_interrupt_OVR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; +} + +static inline bool hri_evsys_get_interrupt_OVR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; +} + +static inline bool hri_evsys_get_interrupt_EVD8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD8_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; +} + +static inline bool hri_evsys_get_interrupt_EVD9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD9_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; +} + +static inline bool hri_evsys_get_interrupt_EVD10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD10_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; +} + +static inline bool hri_evsys_get_interrupt_EVD11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD11_bit(const void *const hw) +{ + ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTFLAG.reg; +} + +static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) +{ + ((Evsys *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_evsys_write_CTRL_reg(const void *const hw, hri_evsys_ctrl_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_SWEVT_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_SWEVT; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_SWEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_SWEVT) >> EVSYS_CHANNEL_SWEVT_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_SWEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_SWEVT; + tmp |= value << EVSYS_CHANNEL_SWEVT_Pos; + ((Evsys *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_SWEVT_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_SWEVT; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_SWEVT_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_SWEVT; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_CHANNEL_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_CHANNEL(mask)) >> EVSYS_CHANNEL_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_CHANNEL_Msk; + tmp |= EVSYS_CHANNEL_CHANNEL(data); + ((Evsys *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_CHANNEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_CHANNEL_Msk) >> EVSYS_CHANNEL_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw) +{ + return ((Evsys *)hw)->CHANNEL.reg; +} + +static inline void hri_evsys_set_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg |= EVSYS_USER_USER(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->USER.reg; + tmp = (tmp & EVSYS_USER_USER(mask)) >> EVSYS_USER_USER_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t data) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER.reg; + tmp &= ~EVSYS_USER_USER_Msk; + tmp |= EVSYS_USER_USER(data); + ((Evsys *)hw)->USER.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg &= ~EVSYS_USER_USER(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg ^= EVSYS_USER_USER(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_USER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->USER.reg; + tmp = (tmp & EVSYS_USER_USER_Msk) >> EVSYS_USER_USER_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->USER.reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t data) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER.reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->USER.reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->USER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw) +{ + return ((Evsys *)hw)->USER.reg; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY8) >> EVSYS_CHSTATUS_USRRDY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY9) >> EVSYS_CHSTATUS_USRRDY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY10) >> EVSYS_CHSTATUS_USRRDY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_USRRDY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY11) >> EVSYS_CHSTATUS_USRRDY11_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY8_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY8) >> EVSYS_CHSTATUS_CHBUSY8_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY9_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY9) >> EVSYS_CHSTATUS_CHBUSY9_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY10_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY10) >> EVSYS_CHSTATUS_CHBUSY10_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_CHBUSY11_bit(const void *const hw) +{ + return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY11) >> EVSYS_CHSTATUS_CHBUSY11_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->CHSTATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_D21_H_INCLUDED */ +#endif /* _SAMD21_EVSYS_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h b/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h new file mode 100644 index 0000000000000..39aa44eab144d --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h @@ -0,0 +1,933 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_D21_H_INCLUDED_ +#define _HRI_GCLK_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_gclk_clkctrl_reg_t; +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_gendiv_reg_t; +typedef uint8_t hri_gclk_ctrl_reg_t; +typedef uint8_t hri_gclk_status_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw) +{ + while (((const Gclk *)hw)->STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_gclk_is_syncing(const void *const hw) +{ + return ((const Gclk *)hw)->STATUS.bit.SYNCBUSY; +} + +static inline void hri_gclk_set_CTRL_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->CTRL.reg |= GCLK_CTRL_SWRST; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->CTRL.reg; + tmp = (tmp & GCLK_CTRL_SWRST) >> GCLK_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRL.reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrl_reg_t hri_gclk_get_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Gclk *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRL.reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRL.reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRL.reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrl_reg_t hri_gclk_read_CTRL_reg(const void *const hw) +{ + return ((Gclk *)hw)->CTRL.reg; +} + +static inline void hri_gclk_set_CLKCTRL_CLKEN_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CLKCTRL_CLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp = (tmp & GCLK_CLKCTRL_CLKEN) >> GCLK_CLKCTRL_CLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_CLKCTRL_CLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp &= ~GCLK_CLKCTRL_CLKEN; + tmp |= value << GCLK_CLKCTRL_CLKEN_Pos; + ((Gclk *)hw)->CLKCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CLKCTRL_CLKEN_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CLKCTRL_CLKEN_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_CLKEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_CLKCTRL_WRTLOCK_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CLKCTRL_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp = (tmp & GCLK_CLKCTRL_WRTLOCK) >> GCLK_CLKCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_CLKCTRL_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp &= ~GCLK_CLKCTRL_WRTLOCK; + tmp |= value << GCLK_CLKCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->CLKCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CLKCTRL_WRTLOCK_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CLKCTRL_WRTLOCK_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp = (tmp & GCLK_CLKCTRL_ID(mask)) >> GCLK_CLKCTRL_ID_Pos; + return tmp; +} + +static inline void hri_gclk_write_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t data) +{ + uint16_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp &= ~GCLK_CLKCTRL_ID_Msk; + tmp |= GCLK_CLKCTRL_ID(data); + ((Gclk *)hw)->CLKCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp = (tmp & GCLK_CLKCTRL_ID_Msk) >> GCLK_CLKCTRL_ID_Pos; + return tmp; +} + +static inline void hri_gclk_set_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp = (tmp & GCLK_CLKCTRL_GEN(mask)) >> GCLK_CLKCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t data) +{ + uint16_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp &= ~GCLK_CLKCTRL_GEN_Msk; + tmp |= GCLK_CLKCTRL_GEN(data); + ((Gclk *)hw)->CLKCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_GEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp = (tmp & GCLK_CLKCTRL_GEN_Msk) >> GCLK_CLKCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Gclk *)hw)->CLKCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CLKCTRL.reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_reg(const void *const hw) +{ + return ((Gclk *)hw)->CLKCTRL.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_GENEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_GENEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_IDC; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_IDC; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_IDC; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_OOV; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_OOV; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_OOV; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_OE; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_OE; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_OE; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_DIVSEL; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_DIVSEL; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_DIVSEL; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_RUNSTDBY; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_RUNSTDBY; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_RUNSTDBY; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_ID(mask)) >> GCLK_GENCTRL_ID_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_ID_Msk; + tmp |= GCLK_GENCTRL_ID(data); + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_ID_bf(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_ID_Msk) >> GCLK_GENCTRL_ID_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_SRC(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_SRC(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw); + ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_SRC(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw); + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL.reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL.reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL.reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL.reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw) +{ + return ((Gclk *)hw)->GENCTRL.reg; +} + +static inline void hri_gclk_set_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg |= GCLK_GENDIV_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENDIV.reg; + tmp = (tmp & GCLK_GENDIV_ID(mask)) >> GCLK_GENDIV_ID_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENDIV.reg; + tmp &= ~GCLK_GENDIV_ID_Msk; + tmp |= GCLK_GENDIV_ID(data); + ((Gclk *)hw)->GENDIV.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg &= ~GCLK_GENDIV_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg ^= GCLK_GENDIV_ID(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_ID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENDIV.reg; + tmp = (tmp & GCLK_GENDIV_ID_Msk) >> GCLK_GENDIV_ID_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg |= GCLK_GENDIV_DIV(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENDIV.reg; + tmp = (tmp & GCLK_GENDIV_DIV(mask)) >> GCLK_GENDIV_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENDIV.reg; + tmp &= ~GCLK_GENDIV_DIV_Msk; + tmp |= GCLK_GENDIV_DIV(data); + ((Gclk *)hw)->GENDIV.reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg &= ~GCLK_GENDIV_DIV(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg ^= GCLK_GENDIV_DIV(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENDIV.reg; + tmp = (tmp & GCLK_GENDIV_DIV_Msk) >> GCLK_GENDIV_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENDIV.reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_reg(const void *const hw) +{ + return ((Gclk *)hw)->GENDIV.reg; +} + +static inline bool hri_gclk_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Gclk *)hw)->STATUS.reg & GCLK_STATUS_SYNCBUSY) >> GCLK_STATUS_SYNCBUSY_Pos; +} + +static inline hri_gclk_status_reg_t hri_gclk_get_STATUS_reg(const void *const hw, hri_gclk_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Gclk *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_status_reg_t hri_gclk_read_STATUS_reg(const void *const hw) +{ + return ((Gclk *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_D21_H_INCLUDED */ +#endif /* _SAMD21_GCLK_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h b/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h new file mode 100644 index 0000000000000..d9c59868744ab --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h @@ -0,0 +1,289 @@ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_D21_H_INCLUDED_ +#define _HRI_HMATRIXB_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixb_sfr_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixb_set_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_get_SFR_reg(const void *const hw, uint8_t index, + hri_hmatrixb_sfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->SFR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->SFR[index].reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_read_SFR_reg(const void *const hw, uint8_t index) +{ + return ((Hmatrixb *)hw)->SFR[index].reg; +} + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_D21_H_INCLUDED */ +#endif /* _SAMD21_HMATRIXB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h b/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h new file mode 100644 index 0000000000000..5ab2f76c01e8e --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h @@ -0,0 +1,2516 @@ +/** + * \file + * + * \brief SAM I2S + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_I2S_COMPONENT_ +#ifndef _HRI_I2S_D21_H_INCLUDED_ +#define _HRI_I2S_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_I2S_CRITICAL_SECTIONS) +#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define I2S_CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_i2s_intenset_reg_t; +typedef uint16_t hri_i2s_intflag_reg_t; +typedef uint16_t hri_i2s_syncbusy_reg_t; +typedef uint32_t hri_i2s_clkctrl_reg_t; +typedef uint32_t hri_i2s_data_reg_t; +typedef uint32_t hri_i2s_serctrl_reg_t; +typedef uint8_t hri_i2s_ctrla_reg_t; + +static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + while (((I2s *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + return ((I2s *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; +} + +static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; +} + +static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; +} + +static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; +} + +static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; +} + +static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; +} + +static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; +} + +static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; +} + +static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; +} + +static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; +} + +static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; +} + +static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; +} + +static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; +} + +static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; +} + +static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; +} + +static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; +} + +static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENSET.reg = mask; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) +{ + return ((I2s *)hw)->INTENSET.reg; +} + +static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) +{ + ((I2s *)hw)->INTENSET.reg = data; + ((I2s *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) +{ + return ((I2s *)hw)->INTFLAG.reg; +} + +static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + ((I2s *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_ENABLE; + tmp |= value << I2S_CTRLA_ENABLE_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN0; + tmp |= value << I2S_CTRLA_CKEN0_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN1; + tmp |= value << I2S_CTRLA_CKEN1_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_SEREN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SEREN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SEREN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SEREN0) >> I2S_CTRLA_SEREN0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_SEREN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_SEREN0; + tmp |= value << I2S_CTRLA_SEREN0_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_SEREN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_SEREN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_SEREN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_SEREN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_SEREN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SEREN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SEREN1_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SEREN1) >> I2S_CTRLA_SEREN1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_SEREN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_SEREN1; + tmp |= value << I2S_CTRLA_SEREN1_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_SEREN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_SEREN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_SEREN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_SEREN0 + | I2S_SYNCBUSY_SEREN1); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_SEREN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) +{ + return ((I2s *)hw)->CTRLA.reg; +} + +static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_BITDELAY; + tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSSEL; + tmp |= value << I2S_CLKCTRL_FSSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSINV; + tmp |= value << I2S_CLKCTRL_FSINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKSEL; + tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKSEL; + tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKEN; + tmp |= value << I2S_CLKCTRL_MCKEN_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSOUTINV; + tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKOUTINV; + tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTINV; + tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; + tmp |= I2S_CLKCTRL_SLOTSIZE(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; + tmp |= I2S_CLKCTRL_NBSLOTS(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; + tmp |= I2S_CLKCTRL_FSWIDTH(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; + tmp |= I2S_CLKCTRL_MCKDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; + tmp |= I2S_CLKCTRL_MCKOUTDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->CLKCTRL[index].reg; +} + +static inline void hri_i2s_set_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_TXSAME) >> I2S_SERCTRL_TXSAME_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_TXSAME; + tmp |= value << I2S_SERCTRL_TXSAME_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_CLKSEL) >> I2S_SERCTRL_CLKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_CLKSEL; + tmp |= value << I2S_SERCTRL_CLKSEL_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTADJ) >> I2S_SERCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTADJ; + tmp |= value << I2S_SERCTRL_SLOTADJ_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_WORDADJ) >> I2S_SERCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_WORDADJ; + tmp |= value << I2S_SERCTRL_WORDADJ_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_BITREV) >> I2S_SERCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_BITREV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_BITREV; + tmp |= value << I2S_SERCTRL_BITREV_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS0) >> I2S_SERCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS0; + tmp |= value << I2S_SERCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS1) >> I2S_SERCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS1; + tmp |= value << I2S_SERCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS2) >> I2S_SERCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS2; + tmp |= value << I2S_SERCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS3) >> I2S_SERCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS3; + tmp |= value << I2S_SERCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS4) >> I2S_SERCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS4; + tmp |= value << I2S_SERCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS5) >> I2S_SERCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS5; + tmp |= value << I2S_SERCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS6) >> I2S_SERCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS6; + tmp |= value << I2S_SERCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SLOTDIS7) >> I2S_SERCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SLOTDIS7; + tmp |= value << I2S_SERCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_MONO_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_MONO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_MONO) >> I2S_SERCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_MONO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_MONO; + tmp |= value << I2S_SERCTRL_MONO_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_MONO_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_MONO_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_DMA_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_DMA_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_DMA) >> I2S_SERCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_DMA_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_DMA; + tmp |= value << I2S_SERCTRL_DMA_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_DMA_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_DMA_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_RXLOOP) >> I2S_SERCTRL_RXLOOP_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_RXLOOP; + tmp |= value << I2S_SERCTRL_RXLOOP_Pos; + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, + hri_i2s_serctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SERMODE(mask)) >> I2S_SERCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_write_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_SERMODE_Msk; + tmp |= I2S_SERCTRL_SERMODE(data); + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_SERMODE_Msk) >> I2S_SERCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_set_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, + hri_i2s_serctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_TXDEFAULT(mask)) >> I2S_SERCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_write_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_TXDEFAULT_Msk; + tmp |= I2S_SERCTRL_TXDEFAULT(data); + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_TXDEFAULT_Msk) >> I2S_SERCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_set_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, + hri_i2s_serctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_DATASIZE(mask)) >> I2S_SERCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_DATASIZE_Msk; + tmp |= I2S_SERCTRL_DATASIZE(data); + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_DATASIZE_Msk) >> I2S_SERCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, + hri_i2s_serctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_EXTEND(mask)) >> I2S_SERCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= ~I2S_SERCTRL_EXTEND_Msk; + tmp |= I2S_SERCTRL_EXTEND(data); + ((I2s *)hw)->SERCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp = (tmp & I2S_SERCTRL_EXTEND_Msk) >> I2S_SERCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_reg(const void *const hw, uint8_t index, + hri_i2s_serctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->SERCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->SERCTRL[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->SERCTRL[index].reg; +} + +static inline void hri_i2s_set_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + ((I2s *)hw)->DATA[index].reg |= I2S_DATA_DATA(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_data_reg_t hri_i2s_get_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + uint32_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->DATA[index].reg; + tmp = (tmp & I2S_DATA_DATA(mask)) >> I2S_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_i2s_write_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->DATA[index].reg; + tmp &= ~I2S_DATA_DATA_Msk; + tmp |= I2S_DATA_DATA(data); + ((I2s *)hw)->DATA[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + ((I2s *)hw)->DATA[index].reg &= ~I2S_DATA_DATA(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + ((I2s *)hw)->DATA[index].reg ^= I2S_DATA_DATA(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_data_reg_t hri_i2s_read_DATA_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->DATA[index].reg; + tmp = (tmp & I2S_DATA_DATA_Msk) >> I2S_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_i2s_set_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->DATA[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_data_reg_t hri_i2s_get_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->DATA[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->DATA[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->DATA[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->DATA[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_data_reg_t hri_i2s_read_DATA_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->DATA[index].reg; +} + +static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_SEREN0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SEREN0) >> I2S_SYNCBUSY_SEREN0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_SEREN1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SEREN1) >> I2S_SYNCBUSY_SEREN1_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_DATA0) >> I2S_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_DATA1) >> I2S_SYNCBUSY_DATA1_Pos; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) +{ + return ((I2s *)hw)->SYNCBUSY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_I2S_D21_H_INCLUDED */ +#endif /* _SAMD21_I2S_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h b/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h new file mode 100644 index 0000000000000..09f5f66d65871 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h @@ -0,0 +1,560 @@ +/** + * \file + * + * \brief SAM MTB + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_MTB_COMPONENT_ +#ifndef _HRI_MTB_D21_H_INCLUDED_ +#define _HRI_MTB_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MTB_CRITICAL_SECTIONS) +#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MTB_CRITICAL_SECTION_ENTER() +#define MTB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mtb_authstatus_reg_t; +typedef uint32_t hri_mtb_base_reg_t; +typedef uint32_t hri_mtb_cid0_reg_t; +typedef uint32_t hri_mtb_cid1_reg_t; +typedef uint32_t hri_mtb_cid2_reg_t; +typedef uint32_t hri_mtb_cid3_reg_t; +typedef uint32_t hri_mtb_claimset_reg_t; +typedef uint32_t hri_mtb_devarch_reg_t; +typedef uint32_t hri_mtb_devid_reg_t; +typedef uint32_t hri_mtb_devtype_reg_t; +typedef uint32_t hri_mtb_flow_reg_t; +typedef uint32_t hri_mtb_itctrl_reg_t; +typedef uint32_t hri_mtb_lockaccess_reg_t; +typedef uint32_t hri_mtb_lockstatus_reg_t; +typedef uint32_t hri_mtb_master_reg_t; +typedef uint32_t hri_mtb_pid0_reg_t; +typedef uint32_t hri_mtb_pid1_reg_t; +typedef uint32_t hri_mtb_pid2_reg_t; +typedef uint32_t hri_mtb_pid3_reg_t; +typedef uint32_t hri_mtb_pid4_reg_t; +typedef uint32_t hri_mtb_pid5_reg_t; +typedef uint32_t hri_mtb_pid6_reg_t; +typedef uint32_t hri_mtb_pid7_reg_t; +typedef uint32_t hri_mtb_position_reg_t; + +static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMSET.reg = mask; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CLAIMSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) +{ + return ((Mtb *)hw)->CLAIMSET.reg; +} + +static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) +{ + ((Mtb *)hw)->CLAIMSET.reg = data; + ((Mtb *)hw)->CLAIMCLR.reg = ~data; +} + +static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) +{ + ((Mtb *)hw)->CLAIMCLR.reg = mask; +} + +static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->POSITION.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->POSITION.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) +{ + return ((Mtb *)hw)->POSITION.reg; +} + +static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->MASTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->MASTER.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) +{ + return ((Mtb *)hw)->MASTER.reg; +} + +static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->FLOW.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->FLOW.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) +{ + return ((Mtb *)hw)->FLOW.reg; +} + +static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->ITCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->ITCTRL.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) +{ + return ((Mtb *)hw)->ITCTRL.reg; +} + +static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg |= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKACCESS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg = data; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) +{ + MTB_CRITICAL_SECTION_ENTER(); + ((Mtb *)hw)->LOCKACCESS.reg ^= mask; + MTB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKACCESS.reg; +} + +static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->BASE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) +{ + return ((Mtb *)hw)->BASE.reg; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->LOCKSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->LOCKSTATUS.reg; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->AUTHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) +{ + return ((Mtb *)hw)->AUTHSTATUS.reg; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVARCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVARCH.reg; +} + +static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVID.reg; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->DEVTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) +{ + return ((Mtb *)hw)->DEVTYPE.reg; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID4.reg; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID5.reg; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID6.reg; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID7.reg; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID0.reg; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID1.reg; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID2.reg; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->PID3.reg; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID0.reg; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID1.reg; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID2.reg; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mtb *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) +{ + return ((Mtb *)hw)->CID3.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MTB_D21_H_INCLUDED */ +#endif /* _SAMD21_MTB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h b/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h new file mode 100644 index 0000000000000..366387209467f --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h @@ -0,0 +1,2304 @@ +/** + * \file + * + * \brief SAM NVIC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_NVIC_COMPONENT_ +#ifndef _HRI_NVIC_D21_H_INCLUDED_ +#define _HRI_NVIC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) +#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVIC_CRITICAL_SECTION_ENTER() +#define NVIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_nvic_nvicicer_reg_t; +typedef uint32_t hri_nvic_nvicicpr_reg_t; +typedef uint32_t hri_nvic_nvicipr0_reg_t; +typedef uint32_t hri_nvic_nvicipr1_reg_t; +typedef uint32_t hri_nvic_nvicipr2_reg_t; +typedef uint32_t hri_nvic_nvicipr3_reg_t; +typedef uint32_t hri_nvic_nvicipr4_reg_t; +typedef uint32_t hri_nvic_nvicipr5_reg_t; +typedef uint32_t hri_nvic_nvicipr6_reg_t; +typedef uint32_t hri_nvic_nvicipr7_reg_t; +typedef uint32_t hri_nvic_nviciser_reg_t; +typedef uint32_t hri_nvic_nvicispr_reg_t; + +static inline void hri_nvic_set_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISER.reg |= NVIC_NVICISER_SETENA(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nviciser_reg_t hri_nvic_get_NVICISER_SETENA_bf(const void *const hw, + hri_nvic_nviciser_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICISER.reg; + tmp = (tmp & NVIC_NVICISER_SETENA(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICISER.reg; + tmp &= ~NVIC_NVICISER_SETENA_Msk; + tmp |= NVIC_NVICISER_SETENA(data); + ((Nvic *)hw)->NVICISER.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISER.reg &= ~NVIC_NVICISER_SETENA(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISER.reg ^= NVIC_NVICISER_SETENA(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nviciser_reg_t hri_nvic_read_NVICISER_SETENA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICISER.reg; + tmp = (tmp & NVIC_NVICISER_SETENA_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nviciser_reg_t hri_nvic_get_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICISER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nviciser_reg_t hri_nvic_read_NVICISER_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICISER.reg; +} + +static inline void hri_nvic_set_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICER.reg |= NVIC_NVICICER_CLRENA(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicer_reg_t hri_nvic_get_NVICICER_CLRENA_bf(const void *const hw, + hri_nvic_nvicicer_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICICER.reg; + tmp = (tmp & NVIC_NVICICER_CLRENA(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICICER.reg; + tmp &= ~NVIC_NVICICER_CLRENA_Msk; + tmp |= NVIC_NVICICER_CLRENA(data); + ((Nvic *)hw)->NVICICER.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICER.reg &= ~NVIC_NVICICER_CLRENA(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICER.reg ^= NVIC_NVICICER_CLRENA(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicer_reg_t hri_nvic_read_NVICICER_CLRENA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICICER.reg; + tmp = (tmp & NVIC_NVICICER_CLRENA_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICER.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicer_reg_t hri_nvic_get_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICICER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICER.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICER.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICER.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicer_reg_t hri_nvic_read_NVICICER_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICICER.reg; +} + +static inline void hri_nvic_set_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISPR.reg |= NVIC_NVICISPR_SETPEND(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicispr_reg_t hri_nvic_get_NVICISPR_SETPEND_bf(const void *const hw, + hri_nvic_nvicispr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICISPR.reg; + tmp = (tmp & NVIC_NVICISPR_SETPEND(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICISPR.reg; + tmp &= ~NVIC_NVICISPR_SETPEND_Msk; + tmp |= NVIC_NVICISPR_SETPEND(data); + ((Nvic *)hw)->NVICISPR.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISPR.reg &= ~NVIC_NVICISPR_SETPEND(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISPR.reg ^= NVIC_NVICISPR_SETPEND(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicispr_reg_t hri_nvic_read_NVICISPR_SETPEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICISPR.reg; + tmp = (tmp & NVIC_NVICISPR_SETPEND_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicispr_reg_t hri_nvic_get_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICISPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICISPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicispr_reg_t hri_nvic_read_NVICISPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICISPR.reg; +} + +static inline void hri_nvic_set_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICPR.reg |= NVIC_NVICICPR_CLRPEND(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicpr_reg_t hri_nvic_get_NVICICPR_CLRPEND_bf(const void *const hw, + hri_nvic_nvicicpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICICPR.reg; + tmp = (tmp & NVIC_NVICICPR_CLRPEND(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICICPR.reg; + tmp &= ~NVIC_NVICICPR_CLRPEND_Msk; + tmp |= NVIC_NVICICPR_CLRPEND(data); + ((Nvic *)hw)->NVICICPR.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICPR.reg &= ~NVIC_NVICICPR_CLRPEND(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICPR.reg ^= NVIC_NVICICPR_CLRPEND(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicpr_reg_t hri_nvic_read_NVICICPR_CLRPEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICICPR.reg; + tmp = (tmp & NVIC_NVICICPR_CLRPEND_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICPR.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicpr_reg_t hri_nvic_get_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICICPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICPR.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICPR.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICICPR.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicicpr_reg_t hri_nvic_read_NVICICPR_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICICPR.reg; +} + +static inline void hri_nvic_set_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI0(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI0(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp &= ~NVIC_NVICIPR0_PRI0_Msk; + tmp |= NVIC_NVICIPR0_PRI0(data); + ((Nvic *)hw)->NVICIPR0.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI0(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI0(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI0_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI1(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI1(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp &= ~NVIC_NVICIPR0_PRI1_Msk; + tmp |= NVIC_NVICIPR0_PRI1(data); + ((Nvic *)hw)->NVICIPR0.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI1(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI1(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI1_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI2(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI2(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp &= ~NVIC_NVICIPR0_PRI2_Msk; + tmp |= NVIC_NVICIPR0_PRI2(data); + ((Nvic *)hw)->NVICIPR0.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI2(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI2(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI2_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI3(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI3(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp &= ~NVIC_NVICIPR0_PRI3_Msk; + tmp |= NVIC_NVICIPR0_PRI3(data); + ((Nvic *)hw)->NVICIPR0.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI3(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI3(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp = (tmp & NVIC_NVICIPR0_PRI3_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR0.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR0.reg; +} + +static inline void hri_nvic_set_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI4(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI4(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp &= ~NVIC_NVICIPR1_PRI4_Msk; + tmp |= NVIC_NVICIPR1_PRI4(data); + ((Nvic *)hw)->NVICIPR1.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI4(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI4(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI4_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI4_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI5(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI5(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp &= ~NVIC_NVICIPR1_PRI5_Msk; + tmp |= NVIC_NVICIPR1_PRI5(data); + ((Nvic *)hw)->NVICIPR1.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI5(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI5(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI5_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI5_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI6(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI6(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp &= ~NVIC_NVICIPR1_PRI6_Msk; + tmp |= NVIC_NVICIPR1_PRI6(data); + ((Nvic *)hw)->NVICIPR1.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI6(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI6(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI6_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI6_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI7(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI7(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp &= ~NVIC_NVICIPR1_PRI7_Msk; + tmp |= NVIC_NVICIPR1_PRI7(data); + ((Nvic *)hw)->NVICIPR1.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI7(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI7(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI7_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp = (tmp & NVIC_NVICIPR1_PRI7_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR1.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR1.reg; +} + +static inline void hri_nvic_set_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI8(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI8(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp &= ~NVIC_NVICIPR2_PRI8_Msk; + tmp |= NVIC_NVICIPR2_PRI8(data); + ((Nvic *)hw)->NVICIPR2.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI8(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI8(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI8_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI8_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI9(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI9(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp &= ~NVIC_NVICIPR2_PRI9_Msk; + tmp |= NVIC_NVICIPR2_PRI9(data); + ((Nvic *)hw)->NVICIPR2.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI9(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI9(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI9_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI9_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI10(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI10(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp &= ~NVIC_NVICIPR2_PRI10_Msk; + tmp |= NVIC_NVICIPR2_PRI10(data); + ((Nvic *)hw)->NVICIPR2.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI10(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI10(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI10_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI10_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI11(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI11(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp &= ~NVIC_NVICIPR2_PRI11_Msk; + tmp |= NVIC_NVICIPR2_PRI11(data); + ((Nvic *)hw)->NVICIPR2.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI11(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI11(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI11_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp = (tmp & NVIC_NVICIPR2_PRI11_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR2.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR2.reg; +} + +static inline void hri_nvic_set_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI12(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI12(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp &= ~NVIC_NVICIPR3_PRI12_Msk; + tmp |= NVIC_NVICIPR3_PRI12(data); + ((Nvic *)hw)->NVICIPR3.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI12(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI12(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI12_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI12_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI13(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI13(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp &= ~NVIC_NVICIPR3_PRI13_Msk; + tmp |= NVIC_NVICIPR3_PRI13(data); + ((Nvic *)hw)->NVICIPR3.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI13(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI13(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI13_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI13_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI14(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI14(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp &= ~NVIC_NVICIPR3_PRI14_Msk; + tmp |= NVIC_NVICIPR3_PRI14(data); + ((Nvic *)hw)->NVICIPR3.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI14(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI14(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI14_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI14_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI15(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI15(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp &= ~NVIC_NVICIPR3_PRI15_Msk; + tmp |= NVIC_NVICIPR3_PRI15(data); + ((Nvic *)hw)->NVICIPR3.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI15(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI15(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI15_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp = (tmp & NVIC_NVICIPR3_PRI15_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR3.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR3.reg; +} + +static inline void hri_nvic_set_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI16(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI16(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp &= ~NVIC_NVICIPR4_PRI16_Msk; + tmp |= NVIC_NVICIPR4_PRI16(data); + ((Nvic *)hw)->NVICIPR4.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI16(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI16(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI16_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI16_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI17(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI17(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp &= ~NVIC_NVICIPR4_PRI17_Msk; + tmp |= NVIC_NVICIPR4_PRI17(data); + ((Nvic *)hw)->NVICIPR4.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI17(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI17(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI17_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI17_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI18(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI18(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp &= ~NVIC_NVICIPR4_PRI18_Msk; + tmp |= NVIC_NVICIPR4_PRI18(data); + ((Nvic *)hw)->NVICIPR4.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI18(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI18(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI18_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI18_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI19(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI19(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp &= ~NVIC_NVICIPR4_PRI19_Msk; + tmp |= NVIC_NVICIPR4_PRI19(data); + ((Nvic *)hw)->NVICIPR4.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI19(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI19(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI19_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp = (tmp & NVIC_NVICIPR4_PRI19_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR4.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR4.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR4.reg; +} + +static inline void hri_nvic_set_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI20(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI20(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp &= ~NVIC_NVICIPR5_PRI20_Msk; + tmp |= NVIC_NVICIPR5_PRI20(data); + ((Nvic *)hw)->NVICIPR5.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI20(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI20(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI20_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI20_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI21(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI21(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp &= ~NVIC_NVICIPR5_PRI21_Msk; + tmp |= NVIC_NVICIPR5_PRI21(data); + ((Nvic *)hw)->NVICIPR5.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI21(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI21(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI21_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI21_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI22(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI22(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp &= ~NVIC_NVICIPR5_PRI22_Msk; + tmp |= NVIC_NVICIPR5_PRI22(data); + ((Nvic *)hw)->NVICIPR5.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI22(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI22(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI22_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI22_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI23(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI23(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp &= ~NVIC_NVICIPR5_PRI23_Msk; + tmp |= NVIC_NVICIPR5_PRI23(data); + ((Nvic *)hw)->NVICIPR5.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI23(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI23(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI23_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp = (tmp & NVIC_NVICIPR5_PRI23_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR5.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR5.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR5.reg; +} + +static inline void hri_nvic_set_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI24(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI24(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp &= ~NVIC_NVICIPR6_PRI24_Msk; + tmp |= NVIC_NVICIPR6_PRI24(data); + ((Nvic *)hw)->NVICIPR6.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI24(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI24(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI24_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI24_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI25(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI25(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp &= ~NVIC_NVICIPR6_PRI25_Msk; + tmp |= NVIC_NVICIPR6_PRI25(data); + ((Nvic *)hw)->NVICIPR6.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI25(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI25(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI25_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI25_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI26(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI26(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp &= ~NVIC_NVICIPR6_PRI26_Msk; + tmp |= NVIC_NVICIPR6_PRI26(data); + ((Nvic *)hw)->NVICIPR6.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI26(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI26(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI26_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI26_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI27(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI27(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp &= ~NVIC_NVICIPR6_PRI27_Msk; + tmp |= NVIC_NVICIPR6_PRI27(data); + ((Nvic *)hw)->NVICIPR6.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI27(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI27(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI27_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp = (tmp & NVIC_NVICIPR6_PRI27_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR6.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR6.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR6.reg; +} + +static inline void hri_nvic_set_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI28(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI28(mask)) >> 0; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp &= ~NVIC_NVICIPR7_PRI28_Msk; + tmp |= NVIC_NVICIPR7_PRI28(data); + ((Nvic *)hw)->NVICIPR7.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI28(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI28(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI28_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI28_Msk) >> 0; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI29(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI29(mask)) >> 8; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp &= ~NVIC_NVICIPR7_PRI29_Msk; + tmp |= NVIC_NVICIPR7_PRI29(data); + ((Nvic *)hw)->NVICIPR7.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI29(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI29(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI29_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI29_Msk) >> 8; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI30(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI30(mask)) >> 16; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp &= ~NVIC_NVICIPR7_PRI30_Msk; + tmp |= NVIC_NVICIPR7_PRI30(data); + ((Nvic *)hw)->NVICIPR7.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI30(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI30(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI30_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI30_Msk) >> 16; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI31(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI31(mask)) >> 24; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) +{ + uint32_t tmp; + NVIC_CRITICAL_SECTION_ENTER(); + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp &= ~NVIC_NVICIPR7_PRI31_Msk; + tmp |= NVIC_NVICIPR7_PRI31(data); + ((Nvic *)hw)->NVICIPR7.reg = tmp; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI31(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI31(mask); + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI31_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp = (tmp & NVIC_NVICIPR7_PRI31_Msk) >> 24; + return tmp; +} + +static inline void hri_nvic_set_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg |= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvic *)hw)->NVICIPR7.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvic_write_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t data) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg = data; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_clear_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg &= ~mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvic_toggle_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) +{ + NVIC_CRITICAL_SECTION_ENTER(); + ((Nvic *)hw)->NVICIPR7.reg ^= mask; + NVIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_reg(const void *const hw) +{ + return ((Nvic *)hw)->NVICIPR7.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVIC_D21_H_INCLUDED */ +#endif /* _SAMD21_NVIC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h b/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h new file mode 100644 index 0000000000000..dcf781f985eae --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h @@ -0,0 +1,1024 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_D21_H_INCLUDED_ +#define _HRI_NVMCTRL_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_lock_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_ctrlb_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint8_t hri_nvmctrl_intenset_reg_t; +typedef uint8_t hri_nvmctrl_intflag_reg_t; + +static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; +} + +static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; + } +} + +static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; +} + +static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; +} + +static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMD_Msk; + tmp |= NVMCTRL_CTRLA_CMD(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; + tmp |= NVMCTRL_CTRLA_CMDEX(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_MANW; + tmp |= value << NVMCTRL_CTRLB_MANW_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_CACHEDIS; + tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos; + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_RWS_Msk; + tmp |= NVMCTRL_CTRLB_RWS(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; + tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, + hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; + tmp |= NVMCTRL_CTRLB_READMODE(data); + ((Nvmctrl *)hw)->CTRLB.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLB.reg; +} + +static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_NVMP_Msk; + tmp |= NVMCTRL_PARAM_NVMP(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= ~NVMCTRL_PARAM_PSZ_Msk; + tmp |= NVMCTRL_PARAM_PSZ(data); + ((Nvmctrl *)hw)->PARAM.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->PARAM.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= ~NVMCTRL_LOCK_LOCK_Msk; + tmp |= NVMCTRL_LOCK_LOCK(data); + ((Nvmctrl *)hw)->LOCK.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->LOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->LOCK.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->LOCK.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; +} + +static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->STATUS.reg = mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_D21_H_INCLUDED */ +#endif /* _SAMD21_NVMCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_pac_d21.h b/atmel-samd/asf4/samd21/hri/hri_pac_d21.h new file mode 100644 index 0000000000000..fbd75c46ca5db --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_pac_d21.h @@ -0,0 +1,130 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_PAC_COMPONENT_ +#ifndef _HRI_PAC_D21_H_INCLUDED_ +#define _HRI_PAC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_wpset_reg_t; + +static inline void hri_pac_set_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask) +{ + ((Pac *)hw)->WPSET.reg = PAC_WPSET_WP(mask); +} + +static inline hri_pac_wpset_reg_t hri_pac_get_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WPSET.reg; + tmp = (tmp & PAC_WPSET_WP(mask)) >> PAC_WPSET_WP_Pos; + return tmp; +} + +static inline hri_pac_wpset_reg_t hri_pac_read_WP_WP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WPSET.reg; + tmp = (tmp & PAC_WPSET_WP_Msk) >> PAC_WPSET_WP_Pos; + return tmp; +} + +static inline void hri_pac_write_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t data) +{ + ((Pac *)hw)->WPSET.reg = PAC_WPSET_WP(data); + ((Pac *)hw)->WPCLR.reg = ~PAC_WPSET_WP(data); +} + +static inline void hri_pac_clear_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask) +{ + ((Pac *)hw)->WPCLR.reg = PAC_WPSET_WP(mask); +} + +static inline void hri_pac_set_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask) +{ + ((Pac *)hw)->WPSET.reg = mask; +} + +static inline hri_pac_wpset_reg_t hri_pac_get_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WPSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_wpset_reg_t hri_pac_read_WP_reg(const void *const hw) +{ + return ((Pac *)hw)->WPSET.reg; +} + +static inline void hri_pac_write_WP_reg(const void *const hw, hri_pac_wpset_reg_t data) +{ + ((Pac *)hw)->WPSET.reg = data; + ((Pac *)hw)->WPCLR.reg = ~data; +} + +static inline void hri_pac_clear_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask) +{ + ((Pac *)hw)->WPCLR.reg = mask; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_D21_H_INCLUDED */ +#endif /* _SAMD21_PAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_pm_d21.h b/atmel-samd/asf4/samd21/hri/hri_pm_d21.h new file mode 100644 index 0000000000000..41f84b5ea9924 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_pm_d21.h @@ -0,0 +1,2545 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_PM_COMPONENT_ +#ifndef _HRI_PM_D21_H_INCLUDED_ +#define _HRI_PM_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pm_ahbmask_reg_t; +typedef uint32_t hri_pm_apbamask_reg_t; +typedef uint32_t hri_pm_apbbmask_reg_t; +typedef uint32_t hri_pm_apbcmask_reg_t; +typedef uint8_t hri_pm_apbasel_reg_t; +typedef uint8_t hri_pm_apbbsel_reg_t; +typedef uint8_t hri_pm_apbcsel_reg_t; +typedef uint8_t hri_pm_cpusel_reg_t; +typedef uint8_t hri_pm_ctrl_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_rcause_reg_t; +typedef uint8_t hri_pm_sleep_reg_t; + +static inline void hri_pm_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_CKRDY; +} + +static inline bool hri_pm_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_CKRDY) >> PM_INTENSET_CKRDY_Pos; +} + +static inline void hri_pm_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_CKRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_CKRDY; + } +} + +static inline void hri_pm_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_CKRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pm_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_CKRDY) >> PM_INTFLAG_CKRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_CKRDY; +} + +static inline bool hri_pm_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_CKRDY) >> PM_INTFLAG_CKRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_CKRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRL.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrl_reg_t hri_pm_get_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRL.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRL.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRL.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrl_reg_t hri_pm_read_CTRL_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRL.reg; +} + +static inline void hri_pm_set_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEP.reg |= PM_SLEEP_IDLE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleep_reg_t hri_pm_get_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEP.reg; + tmp = (tmp & PM_SLEEP_IDLE(mask)) >> PM_SLEEP_IDLE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEP.reg; + tmp &= ~PM_SLEEP_IDLE_Msk; + tmp |= PM_SLEEP_IDLE(data); + ((Pm *)hw)->SLEEP.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEP.reg &= ~PM_SLEEP_IDLE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEP.reg ^= PM_SLEEP_IDLE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleep_reg_t hri_pm_read_SLEEP_IDLE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEP.reg; + tmp = (tmp & PM_SLEEP_IDLE_Msk) >> PM_SLEEP_IDLE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEP.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleep_reg_t hri_pm_get_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEP.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEP.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEP.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleep_reg_t hri_pm_read_SLEEP_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEP.reg; +} + +static inline void hri_pm_set_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CPUSEL.reg |= PM_CPUSEL_CPUDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_cpusel_reg_t hri_pm_get_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CPUSEL.reg; + tmp = (tmp & PM_CPUSEL_CPUDIV(mask)) >> PM_CPUSEL_CPUDIV_Pos; + return tmp; +} + +static inline void hri_pm_write_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CPUSEL.reg; + tmp &= ~PM_CPUSEL_CPUDIV_Msk; + tmp |= PM_CPUSEL_CPUDIV(data); + ((Pm *)hw)->CPUSEL.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CPUSEL.reg &= ~PM_CPUSEL_CPUDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CPUSEL.reg ^= PM_CPUSEL_CPUDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_cpusel_reg_t hri_pm_read_CPUSEL_CPUDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CPUSEL.reg; + tmp = (tmp & PM_CPUSEL_CPUDIV_Msk) >> PM_CPUSEL_CPUDIV_Pos; + return tmp; +} + +static inline void hri_pm_set_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CPUSEL.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_cpusel_reg_t hri_pm_get_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CPUSEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CPUSEL.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CPUSEL.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CPUSEL.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_cpusel_reg_t hri_pm_read_CPUSEL_reg(const void *const hw) +{ + return ((Pm *)hw)->CPUSEL.reg; +} + +static inline void hri_pm_set_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBASEL.reg |= PM_APBASEL_APBADIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbasel_reg_t hri_pm_get_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBASEL.reg; + tmp = (tmp & PM_APBASEL_APBADIV(mask)) >> PM_APBASEL_APBADIV_Pos; + return tmp; +} + +static inline void hri_pm_write_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBASEL.reg; + tmp &= ~PM_APBASEL_APBADIV_Msk; + tmp |= PM_APBASEL_APBADIV(data); + ((Pm *)hw)->APBASEL.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBASEL.reg &= ~PM_APBASEL_APBADIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBASEL.reg ^= PM_APBASEL_APBADIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbasel_reg_t hri_pm_read_APBASEL_APBADIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBASEL.reg; + tmp = (tmp & PM_APBASEL_APBADIV_Msk) >> PM_APBASEL_APBADIV_Pos; + return tmp; +} + +static inline void hri_pm_set_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBASEL.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbasel_reg_t hri_pm_get_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBASEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBASEL.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBASEL.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBASEL.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbasel_reg_t hri_pm_read_APBASEL_reg(const void *const hw) +{ + return ((Pm *)hw)->APBASEL.reg; +} + +static inline void hri_pm_set_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBSEL.reg |= PM_APBBSEL_APBBDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbbsel_reg_t hri_pm_get_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBBSEL.reg; + tmp = (tmp & PM_APBBSEL_APBBDIV(mask)) >> PM_APBBSEL_APBBDIV_Pos; + return tmp; +} + +static inline void hri_pm_write_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBSEL.reg; + tmp &= ~PM_APBBSEL_APBBDIV_Msk; + tmp |= PM_APBBSEL_APBBDIV(data); + ((Pm *)hw)->APBBSEL.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBSEL.reg &= ~PM_APBBSEL_APBBDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBSEL.reg ^= PM_APBBSEL_APBBDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbbsel_reg_t hri_pm_read_APBBSEL_APBBDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBBSEL.reg; + tmp = (tmp & PM_APBBSEL_APBBDIV_Msk) >> PM_APBBSEL_APBBDIV_Pos; + return tmp; +} + +static inline void hri_pm_set_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBSEL.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbbsel_reg_t hri_pm_get_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBBSEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBSEL.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBSEL.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBSEL.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbbsel_reg_t hri_pm_read_APBBSEL_reg(const void *const hw) +{ + return ((Pm *)hw)->APBBSEL.reg; +} + +static inline void hri_pm_set_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCSEL.reg |= PM_APBCSEL_APBCDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbcsel_reg_t hri_pm_get_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBCSEL.reg; + tmp = (tmp & PM_APBCSEL_APBCDIV(mask)) >> PM_APBCSEL_APBCDIV_Pos; + return tmp; +} + +static inline void hri_pm_write_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCSEL.reg; + tmp &= ~PM_APBCSEL_APBCDIV_Msk; + tmp |= PM_APBCSEL_APBCDIV(data); + ((Pm *)hw)->APBCSEL.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCSEL.reg &= ~PM_APBCSEL_APBCDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCSEL.reg ^= PM_APBCSEL_APBCDIV(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbcsel_reg_t hri_pm_read_APBCSEL_APBCDIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBCSEL.reg; + tmp = (tmp & PM_APBCSEL_APBCDIV_Msk) >> PM_APBCSEL_APBCDIV_Pos; + return tmp; +} + +static inline void hri_pm_set_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCSEL.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbcsel_reg_t hri_pm_get_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->APBCSEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCSEL.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCSEL.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCSEL.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbcsel_reg_t hri_pm_read_APBCSEL_reg(const void *const hw) +{ + return ((Pm *)hw)->APBCSEL.reg; +} + +static inline void hri_pm_set_AHBMASK_HPB0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp = (tmp & PM_AHBMASK_HPB0) >> PM_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= ~PM_AHBMASK_HPB0; + tmp |= value << PM_AHBMASK_HPB0_Pos; + ((Pm *)hw)->AHBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_AHBMASK_HPB1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp = (tmp & PM_AHBMASK_HPB1) >> PM_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= ~PM_AHBMASK_HPB1; + tmp |= value << PM_AHBMASK_HPB1_Pos; + ((Pm *)hw)->AHBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_AHBMASK_HPB2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp = (tmp & PM_AHBMASK_HPB2) >> PM_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= ~PM_AHBMASK_HPB2; + tmp |= value << PM_AHBMASK_HPB2_Pos; + ((Pm *)hw)->AHBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_AHBMASK_DSU_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_DSU; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp = (tmp & PM_AHBMASK_DSU) >> PM_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= ~PM_AHBMASK_DSU; + tmp |= value << PM_AHBMASK_DSU_Pos; + ((Pm *)hw)->AHBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_DSU_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_DSU; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_DSU; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_NVMCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp = (tmp & PM_AHBMASK_NVMCTRL) >> PM_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= ~PM_AHBMASK_NVMCTRL; + tmp |= value << PM_AHBMASK_NVMCTRL_Pos; + ((Pm *)hw)->AHBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_NVMCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_NVMCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_AHBMASK_DMAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_DMAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp = (tmp & PM_AHBMASK_DMAC) >> PM_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= ~PM_AHBMASK_DMAC; + tmp |= value << PM_AHBMASK_DMAC_Pos; + ((Pm *)hw)->AHBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_DMAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_DMAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_AHBMASK_USB_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_USB; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp = (tmp & PM_AHBMASK_USB) >> PM_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= ~PM_AHBMASK_USB; + tmp |= value << PM_AHBMASK_USB_Pos; + ((Pm *)hw)->AHBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_USB_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_USB; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_USB_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_USB; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ahbmask_reg_t hri_pm_get_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->AHBMASK.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ahbmask_reg_t hri_pm_read_AHBMASK_reg(const void *const hw) +{ + return ((Pm *)hw)->AHBMASK.reg; +} + +static inline void hri_pm_set_APBAMASK_PAC0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_PAC0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBAMASK_PAC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp = (tmp & PM_APBAMASK_PAC0) >> PM_APBAMASK_PAC0_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBAMASK_PAC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= ~PM_APBAMASK_PAC0; + tmp |= value << PM_APBAMASK_PAC0_Pos; + ((Pm *)hw)->APBAMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_PAC0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_PAC0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_PAC0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_PAC0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBAMASK_PM_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_PM; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp = (tmp & PM_APBAMASK_PM) >> PM_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= ~PM_APBAMASK_PM; + tmp |= value << PM_APBAMASK_PM_Pos; + ((Pm *)hw)->APBAMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_PM_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_PM; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_PM_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_PM; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBAMASK_SYSCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_SYSCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBAMASK_SYSCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp = (tmp & PM_APBAMASK_SYSCTRL) >> PM_APBAMASK_SYSCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBAMASK_SYSCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= ~PM_APBAMASK_SYSCTRL; + tmp |= value << PM_APBAMASK_SYSCTRL_Pos; + ((Pm *)hw)->APBAMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_SYSCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_SYSCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_SYSCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_SYSCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBAMASK_GCLK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_GCLK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp = (tmp & PM_APBAMASK_GCLK) >> PM_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= ~PM_APBAMASK_GCLK; + tmp |= value << PM_APBAMASK_GCLK_Pos; + ((Pm *)hw)->APBAMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_GCLK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_GCLK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBAMASK_WDT_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_WDT; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp = (tmp & PM_APBAMASK_WDT) >> PM_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= ~PM_APBAMASK_WDT; + tmp |= value << PM_APBAMASK_WDT_Pos; + ((Pm *)hw)->APBAMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_WDT_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_WDT; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_WDT; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBAMASK_RTC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_RTC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp = (tmp & PM_APBAMASK_RTC) >> PM_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= ~PM_APBAMASK_RTC; + tmp |= value << PM_APBAMASK_RTC_Pos; + ((Pm *)hw)->APBAMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_RTC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_RTC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_RTC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBAMASK_EIC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_EIC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp = (tmp & PM_APBAMASK_EIC) >> PM_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= ~PM_APBAMASK_EIC; + tmp |= value << PM_APBAMASK_EIC_Pos; + ((Pm *)hw)->APBAMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_EIC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_EIC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_EIC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbamask_reg_t hri_pm_get_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBAMASK.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbamask_reg_t hri_pm_read_APBAMASK_reg(const void *const hw) +{ + return ((Pm *)hw)->APBAMASK.reg; +} + +static inline void hri_pm_set_APBBMASK_PAC1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_PAC1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBBMASK_PAC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp = (tmp & PM_APBBMASK_PAC1) >> PM_APBBMASK_PAC1_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBBMASK_PAC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= ~PM_APBBMASK_PAC1; + tmp |= value << PM_APBBMASK_PAC1_Pos; + ((Pm *)hw)->APBBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_PAC1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_PAC1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_PAC1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_PAC1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBBMASK_DSU_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_DSU; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp = (tmp & PM_APBBMASK_DSU) >> PM_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= ~PM_APBBMASK_DSU; + tmp |= value << PM_APBBMASK_DSU_Pos; + ((Pm *)hw)->APBBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_DSU_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_DSU; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_DSU; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_NVMCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp = (tmp & PM_APBBMASK_NVMCTRL) >> PM_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= ~PM_APBBMASK_NVMCTRL; + tmp |= value << PM_APBBMASK_NVMCTRL_Pos; + ((Pm *)hw)->APBBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_NVMCTRL; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBBMASK_PORT_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_PORT; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp = (tmp & PM_APBBMASK_PORT) >> PM_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= ~PM_APBBMASK_PORT; + tmp |= value << PM_APBBMASK_PORT_Pos; + ((Pm *)hw)->APBBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_PORT_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_PORT; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_PORT; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBBMASK_DMAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_DMAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp = (tmp & PM_APBBMASK_DMAC) >> PM_APBBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= ~PM_APBBMASK_DMAC; + tmp |= value << PM_APBBMASK_DMAC_Pos; + ((Pm *)hw)->APBBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_DMAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_DMAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_DMAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_DMAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBBMASK_USB_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_USB; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp = (tmp & PM_APBBMASK_USB) >> PM_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= ~PM_APBBMASK_USB; + tmp |= value << PM_APBBMASK_USB_Pos; + ((Pm *)hw)->APBBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_USB_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_USB; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_USB_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_USB; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBBMASK_HMATRIX_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_HMATRIX; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp = (tmp & PM_APBBMASK_HMATRIX) >> PM_APBBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= ~PM_APBBMASK_HMATRIX; + tmp |= value << PM_APBBMASK_HMATRIX_Pos; + ((Pm *)hw)->APBBMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_HMATRIX_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_HMATRIX; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_HMATRIX_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_HMATRIX; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbbmask_reg_t hri_pm_get_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBBMASK.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbbmask_reg_t hri_pm_read_APBBMASK_reg(const void *const hw) +{ + return ((Pm *)hw)->APBBMASK.reg; +} + +static inline void hri_pm_set_APBCMASK_PAC2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_PAC2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_PAC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_PAC2) >> PM_APBCMASK_PAC2_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_PAC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_PAC2; + tmp |= value << PM_APBCMASK_PAC2_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_PAC2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_PAC2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_PAC2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_PAC2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_EVSYS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_EVSYS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_EVSYS) >> PM_APBCMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_EVSYS; + tmp |= value << PM_APBCMASK_EVSYS_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_EVSYS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_EVSYS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_EVSYS_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_EVSYS; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_SERCOM0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_SERCOM0) >> PM_APBCMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_SERCOM0; + tmp |= value << PM_APBCMASK_SERCOM0_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_SERCOM0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_SERCOM0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_SERCOM1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_SERCOM1) >> PM_APBCMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_SERCOM1; + tmp |= value << PM_APBCMASK_SERCOM1_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_SERCOM1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_SERCOM1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_SERCOM2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_SERCOM2) >> PM_APBCMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_SERCOM2; + tmp |= value << PM_APBCMASK_SERCOM2_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_SERCOM2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_SERCOM2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_SERCOM3_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM3; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_SERCOM3) >> PM_APBCMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_SERCOM3; + tmp |= value << PM_APBCMASK_SERCOM3_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_SERCOM3_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM3; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_SERCOM3_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM3; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_SERCOM4_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM4; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_SERCOM4) >> PM_APBCMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_SERCOM4; + tmp |= value << PM_APBCMASK_SERCOM4_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_SERCOM4_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM4; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_SERCOM4_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM4; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_SERCOM5_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM5; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_SERCOM5) >> PM_APBCMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_SERCOM5; + tmp |= value << PM_APBCMASK_SERCOM5_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_SERCOM5_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM5; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_SERCOM5_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM5; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TCC0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TCC0) >> PM_APBCMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TCC0; + tmp |= value << PM_APBCMASK_TCC0_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TCC0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TCC0_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC0; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TCC1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TCC1) >> PM_APBCMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TCC1; + tmp |= value << PM_APBCMASK_TCC1_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TCC1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TCC1_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC1; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TCC2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TCC2) >> PM_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TCC2; + tmp |= value << PM_APBCMASK_TCC2_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC2; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TC3_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC3; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TC3) >> PM_APBCMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TC3; + tmp |= value << PM_APBCMASK_TC3_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TC3_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC3; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TC3_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC3; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TC4_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC4; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TC4) >> PM_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TC4; + tmp |= value << PM_APBCMASK_TC4_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TC4_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC4; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC4; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TC5_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC5; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TC5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TC5) >> PM_APBCMASK_TC5_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TC5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TC5; + tmp |= value << PM_APBCMASK_TC5_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TC5_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC5; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TC5_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC5; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TC6_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC6; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TC6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TC6) >> PM_APBCMASK_TC6_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TC6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TC6; + tmp |= value << PM_APBCMASK_TC6_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TC6_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC6; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TC6_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC6; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_TC7_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC7; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_TC7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_TC7) >> PM_APBCMASK_TC7_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_TC7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_TC7; + tmp |= value << PM_APBCMASK_TC7_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_TC7_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC7; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_TC7_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC7; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_ADC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_ADC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_ADC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_ADC) >> PM_APBCMASK_ADC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_ADC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_ADC; + tmp |= value << PM_APBCMASK_ADC_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_ADC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_ADC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_ADC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_ADC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_AC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_AC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_AC) >> PM_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_AC; + tmp |= value << PM_APBCMASK_AC_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_AC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_AC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_AC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_AC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_DAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_DAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_DAC) >> PM_APBCMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_DAC; + tmp |= value << PM_APBCMASK_DAC_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_DAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_DAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_DAC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_DAC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_PTC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_PTC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_PTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_PTC) >> PM_APBCMASK_PTC_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_PTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_PTC; + tmp |= value << PM_APBCMASK_PTC_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_PTC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_PTC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_PTC_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_PTC; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_I2S_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_I2S; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_APBCMASK_I2S_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp = (tmp & PM_APBCMASK_I2S) >> PM_APBCMASK_I2S_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_APBCMASK_I2S_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= ~PM_APBCMASK_I2S; + tmp |= value << PM_APBCMASK_I2S_Pos; + ((Pm *)hw)->APBCMASK.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_I2S_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_I2S; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_I2S_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_I2S; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbcmask_reg_t hri_pm_get_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pm *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->APBCMASK.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_apbcmask_reg_t hri_pm_read_APBCMASK_reg(const void *const hw) +{ + return ((Pm *)hw)->APBCMASK.reg; +} + +static inline bool hri_pm_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_POR) >> PM_RCAUSE_POR_Pos; +} + +static inline bool hri_pm_get_RCAUSE_BOD12_bit(const void *const hw) +{ + return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_BOD12) >> PM_RCAUSE_BOD12_Pos; +} + +static inline bool hri_pm_get_RCAUSE_BOD33_bit(const void *const hw) +{ + return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_BOD33) >> PM_RCAUSE_BOD33_Pos; +} + +static inline bool hri_pm_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_EXT) >> PM_RCAUSE_EXT_Pos; +} + +static inline bool hri_pm_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_WDT) >> PM_RCAUSE_WDT_Pos; +} + +static inline bool hri_pm_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_SYST) >> PM_RCAUSE_SYST_Pos; +} + +static inline hri_pm_rcause_reg_t hri_pm_get_RCAUSE_reg(const void *const hw, hri_pm_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_rcause_reg_t hri_pm_read_RCAUSE_reg(const void *const hw) +{ + return ((Pm *)hw)->RCAUSE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_D21_H_INCLUDED */ +#endif /* _SAMD21_PM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_port_d21.h b/atmel-samd/asf4/samd21/hri/hri_port_d21.h new file mode 100644 index 0000000000000..cf37b2a40ac20 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_port_d21.h @@ -0,0 +1,1324 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_PORT_COMPONENT_ +#ifndef _HRI_PORT_D21_H_INCLUDED_ +#define _HRI_PORT_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_D21_H_INCLUDED */ +#endif /* _SAMD21_PORT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h b/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h new file mode 100644 index 0000000000000..49808d60a0c76 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h @@ -0,0 +1,5921 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_RTC_COMPONENT_ +#ifndef _HRI_RTC_D21_H_INCLUDED_ +#define _HRI_RTC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrl_reg_t; +typedef uint16_t hri_rtcmode0_evctrl_reg_t; +typedef uint16_t hri_rtcmode0_readreq_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrl_reg_t; +typedef uint16_t hri_rtcmode1_evctrl_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode1_readreq_reg_t; +typedef uint16_t hri_rtcmode2_ctrl_reg_t; +typedef uint16_t hri_rtcmode2_evctrl_reg_t; +typedef uint16_t hri_rtcmode2_readreq_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode0_dbgctrl_reg_t; +typedef uint8_t hri_rtcmode0_freqcorr_reg_t; +typedef uint8_t hri_rtcmode0_intenset_reg_t; +typedef uint8_t hri_rtcmode0_intflag_reg_t; +typedef uint8_t hri_rtcmode0_status_reg_t; +typedef uint8_t hri_rtcmode1_dbgctrl_reg_t; +typedef uint8_t hri_rtcmode1_freqcorr_reg_t; +typedef uint8_t hri_rtcmode1_intenset_reg_t; +typedef uint8_t hri_rtcmode1_intflag_reg_t; +typedef uint8_t hri_rtcmode1_status_reg_t; +typedef uint8_t hri_rtcmode2_dbgctrl_reg_t; +typedef uint8_t hri_rtcmode2_freqcorr_reg_t; +typedef uint8_t hri_rtcmode2_intenset_reg_t; +typedef uint8_t hri_rtcmode2_intflag_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; +typedef uint8_t hri_rtcmode2_status_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw) +{ + while (((const Rtc *)hw)->MODE0.STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw) +{ + return ((const Rtc *)hw)->MODE0.STATUS.bit.SYNCBUSY; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw) +{ + while (((const Rtc *)hw)->MODE1.STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw) +{ + return ((const Rtc *)hw)->MODE1.STATUS.bit.SYNCBUSY; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw) +{ + while (((const Rtc *)hw)->MODE2.STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw) +{ + return ((const Rtc *)hw)->MODE2.STATUS.bit.SYNCBUSY; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_SYNCRDY; +} + +static inline bool hri_rtcmode2_get_INTEN_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_SYNCRDY) >> RTC_MODE2_INTENSET_SYNCRDY_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_SYNCRDY; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_SYNCRDY; + } +} + +static inline void hri_rtcmode2_clear_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_SYNCRDY; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_SYNCRDY) >> RTC_MODE2_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_SYNCRDY; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_SYNCRDY) >> RTC_MODE2_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_SYNCRDY; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode2_set_CTRL_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_SWRST) >> RTC_MODE2_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_ENABLE) >> RTC_MODE2_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp &= ~RTC_MODE2_CTRL_ENABLE; + tmp |= value << RTC_MODE2_CTRL_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRL_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_CLKREP; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRL_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_CLKREP) >> RTC_MODE2_CTRL_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRL_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp &= ~RTC_MODE2_CTRL_CLKREP; + tmp |= value << RTC_MODE2_CTRL_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRL_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_CLKREP; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRL_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRL_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRL_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_MATCHCLR) >> RTC_MODE2_CTRL_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRL_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp &= ~RTC_MODE2_CTRL_MATCHCLR; + tmp |= value << RTC_MODE2_CTRL_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRL_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRL_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_MODE(mask)) >> RTC_MODE2_CTRL_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp &= ~RTC_MODE2_CTRL_MODE_Msk; + tmp |= RTC_MODE2_CTRL_MODE(data); + ((Rtc *)hw)->MODE2.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_MODE_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_MODE_Msk) >> RTC_MODE2_CTRL_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrl_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_PRESCALER(mask)) >> RTC_MODE2_CTRL_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp &= ~RTC_MODE2_CTRL_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRL_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp = (tmp & RTC_MODE2_CTRL_PRESCALER_Msk) >> RTC_MODE2_CTRL_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRL.reg; +} + +static inline void hri_rtcmode2_set_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_READREQ_RCONT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_READREQ_RCONT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp &= ~RTC_READREQ_RCONT; + tmp |= value << RTC_READREQ_RCONT_Pos; + ((Rtc *)hw)->MODE2.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_READREQ_RREQ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_READREQ_RREQ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp &= ~RTC_READREQ_RREQ; + tmp |= value << RTC_READREQ_RREQ_Pos; + ((Rtc *)hw)->MODE2.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_get_READREQ_ADDR_bf(const void *const hw, + hri_rtcmode2_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp &= ~RTC_READREQ_ADDR_Msk; + tmp |= RTC_READREQ_ADDR(data); + ((Rtc *)hw)->MODE2.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_read_READREQ_ADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_get_READREQ_reg(const void *const hw, + hri_rtcmode2_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.READREQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.READREQ.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_read_READREQ_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.READREQ.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE2.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_get_DBGCTRL_reg(const void *const hw, + hri_rtcmode2_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.DBGCTRL.reg; +} + +static inline void hri_rtcmode2_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_VALUE_bf(const void *const hw, + hri_rtcmode2_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_reg(const void *const hw, + hri_rtcmode2_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.FREQCORR.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline bool hri_rtcmode2_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos; +} + +static inline void hri_rtcmode2_clear_STATUS_SYNCBUSY_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.STATUS.reg = RTC_STATUS_SYNCBUSY; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_status_reg_t hri_rtcmode2_get_STATUS_reg(const void *const hw, + hri_rtcmode2_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_clear_STATUS_reg(const void *const hw, hri_rtcmode2_status_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.STATUS.reg = mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_status_reg_t hri_rtcmode2_read_STATUS_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.STATUS.reg; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_SYNCRDY; +} + +static inline bool hri_rtcmode0_get_INTEN_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_SYNCRDY) >> RTC_MODE0_INTENSET_SYNCRDY_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_SYNCRDY; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_SYNCRDY; + } +} + +static inline void hri_rtcmode0_clear_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_SYNCRDY; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_SYNCRDY) >> RTC_MODE0_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_SYNCRDY; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_SYNCRDY) >> RTC_MODE0_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_SYNCRDY; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_CTRL_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp = (tmp & RTC_MODE0_CTRL_SWRST) >> RTC_MODE0_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp = (tmp & RTC_MODE0_CTRL_ENABLE) >> RTC_MODE0_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp &= ~RTC_MODE0_CTRL_ENABLE; + tmp |= value << RTC_MODE0_CTRL_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRL_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRL_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp = (tmp & RTC_MODE0_CTRL_MATCHCLR) >> RTC_MODE0_CTRL_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRL_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp &= ~RTC_MODE0_CTRL_MATCHCLR; + tmp |= value << RTC_MODE0_CTRL_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRL_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRL_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp = (tmp & RTC_MODE0_CTRL_MODE(mask)) >> RTC_MODE0_CTRL_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp &= ~RTC_MODE0_CTRL_MODE_Msk; + tmp |= RTC_MODE0_CTRL_MODE(data); + ((Rtc *)hw)->MODE0.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_MODE_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp = (tmp & RTC_MODE0_CTRL_MODE_Msk) >> RTC_MODE0_CTRL_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrl_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp = (tmp & RTC_MODE0_CTRL_PRESCALER(mask)) >> RTC_MODE0_CTRL_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp &= ~RTC_MODE0_CTRL_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRL_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp = (tmp & RTC_MODE0_CTRL_PRESCALER_Msk) >> RTC_MODE0_CTRL_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRL.reg; +} + +static inline void hri_rtcmode0_set_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_READREQ_RCONT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_READREQ_RCONT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp &= ~RTC_READREQ_RCONT; + tmp |= value << RTC_READREQ_RCONT_Pos; + ((Rtc *)hw)->MODE0.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_READREQ_RREQ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_READREQ_RREQ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp &= ~RTC_READREQ_RREQ; + tmp |= value << RTC_READREQ_RREQ_Pos; + ((Rtc *)hw)->MODE0.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_get_READREQ_ADDR_bf(const void *const hw, + hri_rtcmode0_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp &= ~RTC_READREQ_ADDR_Msk; + tmp |= RTC_READREQ_ADDR(data); + ((Rtc *)hw)->MODE0.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_read_READREQ_ADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_get_READREQ_reg(const void *const hw, + hri_rtcmode0_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.READREQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.READREQ.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_read_READREQ_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.READREQ.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_get_DBGCTRL_reg(const void *const hw, + hri_rtcmode0_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtcmode0_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_VALUE_bf(const void *const hw, + hri_rtcmode0_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_reg(const void *const hw, + hri_rtcmode0_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline bool hri_rtcmode0_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos; +} + +static inline void hri_rtcmode0_clear_STATUS_SYNCBUSY_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.STATUS.reg = RTC_STATUS_SYNCBUSY; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_status_reg_t hri_rtcmode0_get_STATUS_reg(const void *const hw, + hri_rtcmode0_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_clear_STATUS_reg(const void *const hw, hri_rtcmode0_status_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.STATUS.reg = mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_status_reg_t hri_rtcmode0_read_STATUS_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.STATUS.reg; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_SYNCRDY; +} + +static inline bool hri_rtcmode1_get_INTEN_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_SYNCRDY) >> RTC_MODE1_INTENSET_SYNCRDY_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_SYNCRDY; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_SYNCRDY; + } +} + +static inline void hri_rtcmode1_clear_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_SYNCRDY; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_SYNCRDY) >> RTC_MODE1_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_SYNCRDY; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_SYNCRDY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_SYNCRDY) >> RTC_MODE1_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_SYNCRDY_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_SYNCRDY; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode1_set_CTRL_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_SWRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp = (tmp & RTC_MODE1_CTRL_SWRST) >> RTC_MODE1_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp = (tmp & RTC_MODE1_CTRL_ENABLE) >> RTC_MODE1_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp &= ~RTC_MODE1_CTRL_ENABLE; + tmp |= value << RTC_MODE1_CTRL_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp = (tmp & RTC_MODE1_CTRL_MODE(mask)) >> RTC_MODE1_CTRL_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp &= ~RTC_MODE1_CTRL_MODE_Msk; + tmp |= RTC_MODE1_CTRL_MODE(data); + ((Rtc *)hw)->MODE1.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_MODE_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp = (tmp & RTC_MODE1_CTRL_MODE_Msk) >> RTC_MODE1_CTRL_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrl_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp = (tmp & RTC_MODE1_CTRL_PRESCALER(mask)) >> RTC_MODE1_CTRL_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp &= ~RTC_MODE1_CTRL_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRL_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp = (tmp & RTC_MODE1_CTRL_PRESCALER_Msk) >> RTC_MODE1_CTRL_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRL.reg; +} + +static inline void hri_rtcmode1_set_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_READREQ_RCONT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_READREQ_RCONT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp &= ~RTC_READREQ_RCONT; + tmp |= value << RTC_READREQ_RCONT_Pos; + ((Rtc *)hw)->MODE1.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_READREQ_RCONT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_RCONT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_READREQ_RREQ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_READREQ_RREQ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp &= ~RTC_READREQ_RREQ; + tmp |= value << RTC_READREQ_RREQ_Pos; + ((Rtc *)hw)->MODE1.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_READREQ_RREQ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_RREQ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_get_READREQ_ADDR_bf(const void *const hw, + hri_rtcmode1_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp &= ~RTC_READREQ_ADDR_Msk; + tmp |= RTC_READREQ_ADDR(data); + ((Rtc *)hw)->MODE1.READREQ.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_ADDR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_read_READREQ_ADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_get_READREQ_reg(const void *const hw, + hri_rtcmode1_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.READREQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.READREQ.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_read_READREQ_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.READREQ.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE1.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_get_DBGCTRL_reg(const void *const hw, + hri_rtcmode1_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.DBGCTRL.reg; +} + +static inline void hri_rtcmode1_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_VALUE_bf(const void *const hw, + hri_rtcmode1_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_reg(const void *const hw, + hri_rtcmode1_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.FREQCORR.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline bool hri_rtcmode1_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos; +} + +static inline void hri_rtcmode1_clear_STATUS_SYNCBUSY_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.STATUS.reg = RTC_STATUS_SYNCBUSY; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_status_reg_t hri_rtcmode1_get_STATUS_reg(const void *const hw, + hri_rtcmode1_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_clear_STATUS_reg(const void *const hw, hri_rtcmode1_status_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.STATUS.reg = mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_status_reg_t hri_rtcmode1_read_STATUS_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_D21_H_INCLUDED */ +#endif /* _SAMD21_RTC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h b/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h new file mode 100644 index 0000000000000..52b72b7ba7de0 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h @@ -0,0 +1,7188 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_D21_H_INCLUDED_ +#define _HRI_SERCOM_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_data_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_data_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_data_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD(mask)) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD_Msk) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD(mask)) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD_Msk) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_USARTFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD(mask)) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_USARTFP_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_USARTFP_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_USARTFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_USARTFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD_Msk) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_D21_H_INCLUDED */ +#endif /* _SAMD21_SERCOM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h b/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h new file mode 100644 index 0000000000000..879a2f9395a69 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h @@ -0,0 +1,4760 @@ +/** + * \file + * + * \brief SAM SYSCTRL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_SYSCTRL_COMPONENT_ +#ifndef _HRI_SYSCTRL_D21_H_INCLUDED_ +#define _HRI_SYSCTRL_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SYSCTRL_CRITICAL_SECTIONS) +#define SYSCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SYSCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SYSCTRL_CRITICAL_SECTION_ENTER() +#define SYSCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sysctrl_dfllctrl_reg_t; +typedef uint16_t hri_sysctrl_vreg_reg_t; +typedef uint16_t hri_sysctrl_xosc32k_reg_t; +typedef uint16_t hri_sysctrl_xosc_reg_t; +typedef uint32_t hri_sysctrl_bod33_reg_t; +typedef uint32_t hri_sysctrl_dfllmul_reg_t; +typedef uint32_t hri_sysctrl_dfllval_reg_t; +typedef uint32_t hri_sysctrl_dpllctrlb_reg_t; +typedef uint32_t hri_sysctrl_dpllratio_reg_t; +typedef uint32_t hri_sysctrl_intenset_reg_t; +typedef uint32_t hri_sysctrl_intflag_reg_t; +typedef uint32_t hri_sysctrl_osc32k_reg_t; +typedef uint32_t hri_sysctrl_osc8m_reg_t; +typedef uint32_t hri_sysctrl_pclksr_reg_t; +typedef uint32_t hri_sysctrl_vref_reg_t; +typedef uint8_t hri_sysctrl_dfllsync_reg_t; +typedef uint8_t hri_sysctrl_dpllctrla_reg_t; +typedef uint8_t hri_sysctrl_dpllstatus_reg_t; +typedef uint8_t hri_sysctrl_osculp32k_reg_t; + +static inline void hri_sysctrl_set_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSCRDY; +} + +static inline bool hri_sysctrl_get_INTEN_XOSCRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_XOSCRDY) >> SYSCTRL_INTENSET_XOSCRDY_Pos; +} + +static inline void hri_sysctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSCRDY; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSCRDY; + } +} + +static inline void hri_sysctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSCRDY; +} + +static inline void hri_sysctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_sysctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_XOSC32KRDY) >> SYSCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_sysctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSC32KRDY; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_sysctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_sysctrl_set_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC32KRDY; +} + +static inline bool hri_sysctrl_get_INTEN_OSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_OSC32KRDY) >> SYSCTRL_INTENSET_OSC32KRDY_Pos; +} + +static inline void hri_sysctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC32KRDY; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC32KRDY; + } +} + +static inline void hri_sysctrl_clear_INTEN_OSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC32KRDY; +} + +static inline void hri_sysctrl_set_INTEN_OSC8MRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC8MRDY; +} + +static inline bool hri_sysctrl_get_INTEN_OSC8MRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_OSC8MRDY) >> SYSCTRL_INTENSET_OSC8MRDY_Pos; +} + +static inline void hri_sysctrl_write_INTEN_OSC8MRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC8MRDY; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC8MRDY; + } +} + +static inline void hri_sysctrl_clear_INTEN_OSC8MRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC8MRDY; +} + +static inline void hri_sysctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_sysctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLRDY) >> SYSCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRDY; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_sysctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_sysctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_sysctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLOOB) >> SYSCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLOOB; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_sysctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_sysctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_sysctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLLCKF) >> SYSCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKF; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_sysctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_sysctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_sysctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLLCKC) >> SYSCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKC; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_sysctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_sysctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_sysctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLRCS) >> SYSCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRCS; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_sysctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_sysctrl_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33RDY; +} + +static inline bool hri_sysctrl_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_BOD33RDY) >> SYSCTRL_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_sysctrl_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33RDY; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33RDY; + } +} + +static inline void hri_sysctrl_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33RDY; +} + +static inline void hri_sysctrl_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33DET; +} + +static inline bool hri_sysctrl_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_BOD33DET) >> SYSCTRL_INTENSET_BOD33DET_Pos; +} + +static inline void hri_sysctrl_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33DET; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33DET; + } +} + +static inline void hri_sysctrl_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33DET; +} + +static inline void hri_sysctrl_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_B33SRDY; +} + +static inline bool hri_sysctrl_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_B33SRDY) >> SYSCTRL_INTENSET_B33SRDY_Pos; +} + +static inline void hri_sysctrl_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_B33SRDY; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_B33SRDY; + } +} + +static inline void hri_sysctrl_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_B33SRDY; +} + +static inline void hri_sysctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKR; +} + +static inline bool hri_sysctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLCKR) >> SYSCTRL_INTENSET_DPLLLCKR_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKR; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKR; + } +} + +static inline void hri_sysctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKR; +} + +static inline void hri_sysctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKF; +} + +static inline bool hri_sysctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLCKF) >> SYSCTRL_INTENSET_DPLLLCKF_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKF; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKF; + } +} + +static inline void hri_sysctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKF; +} + +static inline void hri_sysctrl_set_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLTO; +} + +static inline bool hri_sysctrl_get_INTEN_DPLLLTO_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLTO) >> SYSCTRL_INTENSET_DPLLLTO_Pos; +} + +static inline void hri_sysctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLTO; + } else { + ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLTO; + } +} + +static inline void hri_sysctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLTO; +} + +static inline void hri_sysctrl_set_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t mask) +{ + ((Sysctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_sysctrl_intenset_reg_t hri_sysctrl_get_INTEN_reg(const void *const hw, + hri_sysctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sysctrl_intenset_reg_t hri_sysctrl_read_INTEN_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->INTENSET.reg; +} + +static inline void hri_sysctrl_write_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t data) +{ + ((Sysctrl *)hw)->INTENSET.reg = data; + ((Sysctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_sysctrl_clear_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t mask) +{ + ((Sysctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_sysctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSCRDY) >> SYSCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_sysctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSC32KRDY) >> SYSCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_sysctrl_get_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC32KRDY) >> SYSCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_OSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_sysctrl_get_INTFLAG_OSC8MRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC8MRDY) >> SYSCTRL_INTFLAG_OSC8MRDY_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_OSC8MRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC8MRDY; +} + +static inline bool hri_sysctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRDY) >> SYSCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_sysctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLOOB) >> SYSCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_sysctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKF) >> SYSCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_sysctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKC) >> SYSCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_sysctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRCS) >> SYSCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_sysctrl_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33RDY) >> SYSCTRL_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY; +} + +static inline bool hri_sysctrl_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33DET) >> SYSCTRL_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET; +} + +static inline bool hri_sysctrl_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_B33SRDY) >> SYSCTRL_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_B33SRDY; +} + +static inline bool hri_sysctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKR) >> SYSCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_sysctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKF) >> SYSCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_sysctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLTO) >> SYSCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_sysctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLTO; +} + +static inline bool hri_sysctrl_get_interrupt_XOSCRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSCRDY) >> SYSCTRL_INTFLAG_XOSCRDY_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSCRDY; +} + +static inline bool hri_sysctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSC32KRDY) >> SYSCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_sysctrl_get_interrupt_OSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC32KRDY) >> SYSCTRL_INTFLAG_OSC32KRDY_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_OSC32KRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC32KRDY; +} + +static inline bool hri_sysctrl_get_interrupt_OSC8MRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC8MRDY) >> SYSCTRL_INTFLAG_OSC8MRDY_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_OSC8MRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC8MRDY; +} + +static inline bool hri_sysctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRDY) >> SYSCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_sysctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLOOB) >> SYSCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_sysctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKF) >> SYSCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_sysctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKC) >> SYSCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_sysctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRCS) >> SYSCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_sysctrl_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33RDY) >> SYSCTRL_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY; +} + +static inline bool hri_sysctrl_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33DET) >> SYSCTRL_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET; +} + +static inline bool hri_sysctrl_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_B33SRDY) >> SYSCTRL_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_B33SRDY; +} + +static inline bool hri_sysctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKR) >> SYSCTRL_INTFLAG_DPLLLCKR_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKR; +} + +static inline bool hri_sysctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKF) >> SYSCTRL_INTFLAG_DPLLLCKF_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKF; +} + +static inline bool hri_sysctrl_get_interrupt_DPLLLTO_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLTO) >> SYSCTRL_INTFLAG_DPLLLTO_Pos; +} + +static inline void hri_sysctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) +{ + ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLTO; +} + +static inline hri_sysctrl_intflag_reg_t hri_sysctrl_get_INTFLAG_reg(const void *const hw, + hri_sysctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sysctrl_intflag_reg_t hri_sysctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_sysctrl_clear_INTFLAG_reg(const void *const hw, hri_sysctrl_intflag_reg_t mask) +{ + ((Sysctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_sysctrl_set_XOSC_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_ENABLE) >> SYSCTRL_XOSC_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= ~SYSCTRL_XOSC_ENABLE; + tmp |= value << SYSCTRL_XOSC_ENABLE_Pos; + ((Sysctrl *)hw)->XOSC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC_XTALEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_XTALEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_XTALEN) >> SYSCTRL_XOSC_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= ~SYSCTRL_XOSC_XTALEN; + tmp |= value << SYSCTRL_XOSC_XTALEN_Pos; + ((Sysctrl *)hw)->XOSC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_XTALEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_XTALEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_XTALEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_XTALEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_RUNSTDBY) >> SYSCTRL_XOSC_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= ~SYSCTRL_XOSC_RUNSTDBY; + tmp |= value << SYSCTRL_XOSC_RUNSTDBY_Pos; + ((Sysctrl *)hw)->XOSC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_ONDEMAND) >> SYSCTRL_XOSC_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= ~SYSCTRL_XOSC_ONDEMAND; + tmp |= value << SYSCTRL_XOSC_ONDEMAND_Pos; + ((Sysctrl *)hw)->XOSC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC_AMPGC_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_AMPGC; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC_AMPGC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_AMPGC) >> SYSCTRL_XOSC_AMPGC_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC_AMPGC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= ~SYSCTRL_XOSC_AMPGC; + tmp |= value << SYSCTRL_XOSC_AMPGC_Pos; + ((Sysctrl *)hw)->XOSC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_AMPGC_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_AMPGC; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_AMPGC_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_AMPGC; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_GAIN(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_GAIN(mask)) >> SYSCTRL_XOSC_GAIN_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t data) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= ~SYSCTRL_XOSC_GAIN_Msk; + tmp |= SYSCTRL_XOSC_GAIN(data); + ((Sysctrl *)hw)->XOSC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_GAIN(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_GAIN(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_GAIN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_GAIN_Msk) >> SYSCTRL_XOSC_GAIN_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_STARTUP(mask)) >> SYSCTRL_XOSC_STARTUP_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t data) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= ~SYSCTRL_XOSC_STARTUP_Msk; + tmp |= SYSCTRL_XOSC_STARTUP(data); + ((Sysctrl *)hw)->XOSC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp = (tmp & SYSCTRL_XOSC_STARTUP_Msk) >> SYSCTRL_XOSC_STARTUP_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->XOSC.reg; +} + +static inline void hri_sysctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_ENABLE) >> SYSCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_ENABLE; + tmp |= value << SYSCTRL_XOSC32K_ENABLE_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_XTALEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_XTALEN) >> SYSCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_XTALEN; + tmp |= value << SYSCTRL_XOSC32K_XTALEN_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_XTALEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_XTALEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_EN32K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_EN32K) >> SYSCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_EN32K; + tmp |= value << SYSCTRL_XOSC32K_EN32K_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_EN32K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_EN32K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_EN1K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_EN1K) >> SYSCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_EN1K; + tmp |= value << SYSCTRL_XOSC32K_EN1K_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_EN1K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_EN1K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_AAMPEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_AAMPEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_AAMPEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_AAMPEN) >> SYSCTRL_XOSC32K_AAMPEN_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_AAMPEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_AAMPEN; + tmp |= value << SYSCTRL_XOSC32K_AAMPEN_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_AAMPEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_AAMPEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_AAMPEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_AAMPEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_RUNSTDBY) >> SYSCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_RUNSTDBY; + tmp |= value << SYSCTRL_XOSC32K_RUNSTDBY_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_ONDEMAND) >> SYSCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_ONDEMAND; + tmp |= value << SYSCTRL_XOSC32K_ONDEMAND_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_WRTLOCK) >> SYSCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_WRTLOCK; + tmp |= value << SYSCTRL_XOSC32K_WRTLOCK_Pos; + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_sysctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_STARTUP(mask)) >> SYSCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= ~SYSCTRL_XOSC32K_STARTUP_Msk; + tmp |= SYSCTRL_XOSC32K_STARTUP(data); + ((Sysctrl *)hw)->XOSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp = (tmp & SYSCTRL_XOSC32K_STARTUP_Msk) >> SYSCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_get_XOSC32K_reg(const void *const hw, + hri_sysctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->XOSC32K.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_sysctrl_set_OSC32K_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC32K_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_ENABLE) >> SYSCTRL_OSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_ENABLE; + tmp |= value << SYSCTRL_OSC32K_ENABLE_Pos; + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC32K_EN32K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_EN32K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_EN32K) >> SYSCTRL_OSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_EN32K; + tmp |= value << SYSCTRL_OSC32K_EN32K_Pos; + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_EN32K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_EN32K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_EN32K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_EN32K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC32K_EN1K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_EN1K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_EN1K) >> SYSCTRL_OSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_EN1K; + tmp |= value << SYSCTRL_OSC32K_EN1K_Pos; + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_EN1K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_EN1K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_EN1K_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_EN1K; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_RUNSTDBY) >> SYSCTRL_OSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_RUNSTDBY; + tmp |= value << SYSCTRL_OSC32K_RUNSTDBY_Pos; + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC32K_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC32K_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_ONDEMAND) >> SYSCTRL_OSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_ONDEMAND; + tmp |= value << SYSCTRL_OSC32K_ONDEMAND_Pos; + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_WRTLOCK) >> SYSCTRL_OSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_WRTLOCK; + tmp |= value << SYSCTRL_OSC32K_WRTLOCK_Pos; + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_STARTUP_bf(const void *const hw, + hri_sysctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_STARTUP(mask)) >> SYSCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_STARTUP_Msk; + tmp |= SYSCTRL_OSC32K_STARTUP(data); + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_STARTUP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_STARTUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_STARTUP_Msk) >> SYSCTRL_OSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_CALIB_bf(const void *const hw, + hri_sysctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_CALIB(mask)) >> SYSCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= ~SYSCTRL_OSC32K_CALIB_Msk; + tmp |= SYSCTRL_OSC32K_CALIB(data); + ((Sysctrl *)hw)->OSC32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp = (tmp & SYSCTRL_OSC32K_CALIB_Msk) >> SYSCTRL_OSC32K_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC32K.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->OSC32K.reg; +} + +static inline void hri_sysctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg |= SYSCTRL_OSCULP32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & SYSCTRL_OSCULP32K_WRTLOCK) >> SYSCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSCULP32K.reg; + tmp &= ~SYSCTRL_OSCULP32K_WRTLOCK; + tmp |= value << SYSCTRL_OSCULP32K_WRTLOCK_Pos; + ((Sysctrl *)hw)->OSCULP32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg &= ~SYSCTRL_OSCULP32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg ^= SYSCTRL_OSCULP32K_WRTLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg |= SYSCTRL_OSCULP32K_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_sysctrl_osculp32k_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & SYSCTRL_OSCULP32K_CALIB(mask)) >> SYSCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t data) +{ + uint8_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSCULP32K.reg; + tmp &= ~SYSCTRL_OSCULP32K_CALIB_Msk; + tmp |= SYSCTRL_OSCULP32K_CALIB(data); + ((Sysctrl *)hw)->OSCULP32K.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg &= ~SYSCTRL_OSCULP32K_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg ^= SYSCTRL_OSCULP32K_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_get_OSCULP32K_reg(const void *const hw, + hri_sysctrl_osculp32k_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSCULP32K.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->OSCULP32K.reg; +} + +static inline void hri_sysctrl_set_OSC8M_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC8M_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_ENABLE) >> SYSCTRL_OSC8M_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC8M_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp &= ~SYSCTRL_OSC8M_ENABLE; + tmp |= value << SYSCTRL_OSC8M_ENABLE_Pos; + ((Sysctrl *)hw)->OSC8M.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC8M_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC8M_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC8M_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC8M_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_RUNSTDBY) >> SYSCTRL_OSC8M_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC8M_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp &= ~SYSCTRL_OSC8M_RUNSTDBY; + tmp |= value << SYSCTRL_OSC8M_RUNSTDBY_Pos; + ((Sysctrl *)hw)->OSC8M.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC8M_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC8M_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC8M_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_OSC8M_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_ONDEMAND) >> SYSCTRL_OSC8M_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_OSC8M_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp &= ~SYSCTRL_OSC8M_ONDEMAND; + tmp |= value << SYSCTRL_OSC8M_ONDEMAND_Pos; + ((Sysctrl *)hw)->OSC8M.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC8M_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC8M_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_PRESC(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_PRESC(mask)) >> SYSCTRL_OSC8M_PRESC_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp &= ~SYSCTRL_OSC8M_PRESC_Msk; + tmp |= SYSCTRL_OSC8M_PRESC(data); + ((Sysctrl *)hw)->OSC8M.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_PRESC(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_PRESC(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_PRESC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_PRESC_Msk) >> SYSCTRL_OSC8M_PRESC_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_CALIB(mask)) >> SYSCTRL_OSC8M_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp &= ~SYSCTRL_OSC8M_CALIB_Msk; + tmp |= SYSCTRL_OSC8M_CALIB(data); + ((Sysctrl *)hw)->OSC8M.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_CALIB_Msk) >> SYSCTRL_OSC8M_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_FRANGE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_FRANGE_bf(const void *const hw, + hri_sysctrl_osc8m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_FRANGE(mask)) >> SYSCTRL_OSC8M_FRANGE_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp &= ~SYSCTRL_OSC8M_FRANGE_Msk; + tmp |= SYSCTRL_OSC8M_FRANGE(data); + ((Sysctrl *)hw)->OSC8M.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_FRANGE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_FRANGE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_FRANGE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp = (tmp & SYSCTRL_OSC8M_FRANGE_Msk) >> SYSCTRL_OSC8M_FRANGE_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->OSC8M.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->OSC8M.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->OSC8M.reg; +} + +static inline void hri_sysctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_ENABLE) >> SYSCTRL_DFLLCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_ENABLE; + tmp |= value << SYSCTRL_DFLLCTRL_ENABLE_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_MODE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_MODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_MODE) >> SYSCTRL_DFLLCTRL_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_MODE; + tmp |= value << SYSCTRL_DFLLCTRL_MODE_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_MODE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_MODE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_MODE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_STABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_STABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_STABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_STABLE) >> SYSCTRL_DFLLCTRL_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_STABLE; + tmp |= value << SYSCTRL_DFLLCTRL_STABLE_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_STABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_STABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_LLAW_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_LLAW; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_LLAW_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_LLAW) >> SYSCTRL_DFLLCTRL_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_LLAW; + tmp |= value << SYSCTRL_DFLLCTRL_LLAW_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_LLAW; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_LLAW; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_USBCRM; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_USBCRM) >> SYSCTRL_DFLLCTRL_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_USBCRM; + tmp |= value << SYSCTRL_DFLLCTRL_USBCRM_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_USBCRM; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_USBCRM; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_RUNSTDBY) >> SYSCTRL_DFLLCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_RUNSTDBY; + tmp |= value << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_ONDEMAND) >> SYSCTRL_DFLLCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_ONDEMAND; + tmp |= value << SYSCTRL_DFLLCTRL_ONDEMAND_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_CCDIS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_CCDIS) >> SYSCTRL_DFLLCTRL_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_CCDIS; + tmp |= value << SYSCTRL_DFLLCTRL_CCDIS_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_CCDIS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_CCDIS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_QLDIS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_QLDIS) >> SYSCTRL_DFLLCTRL_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_QLDIS; + tmp |= value << SYSCTRL_DFLLCTRL_QLDIS_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_QLDIS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_QLDIS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_BPLCKC; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_BPLCKC) >> SYSCTRL_DFLLCTRL_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_BPLCKC; + tmp |= value << SYSCTRL_DFLLCTRL_BPLCKC_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_BPLCKC; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_BPLCKC; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_WAITLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp = (tmp & SYSCTRL_DFLLCTRL_WAITLOCK) >> SYSCTRL_DFLLCTRL_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= ~SYSCTRL_DFLLCTRL_WAITLOCK; + tmp |= value << SYSCTRL_DFLLCTRL_WAITLOCK_Pos; + ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_WAITLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_WAITLOCK; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllctrl_reg_t hri_sysctrl_get_DFLLCTRL_reg(const void *const hw, + hri_sysctrl_dfllctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLCTRL.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllctrl_reg_t hri_sysctrl_read_DFLLCTRL_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DFLLCTRL.reg; +} + +static inline void hri_sysctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_FINE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_sysctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & SYSCTRL_DFLLVAL_FINE(mask)) >> SYSCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp &= ~SYSCTRL_DFLLVAL_FINE_Msk; + tmp |= SYSCTRL_DFLLVAL_FINE(data); + ((Sysctrl *)hw)->DFLLVAL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_FINE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_FINE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & SYSCTRL_DFLLVAL_FINE_Msk) >> SYSCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_COARSE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_sysctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & SYSCTRL_DFLLVAL_COARSE(mask)) >> SYSCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp &= ~SYSCTRL_DFLLVAL_COARSE_Msk; + tmp |= SYSCTRL_DFLLVAL_COARSE(data); + ((Sysctrl *)hw)->DFLLVAL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_COARSE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_COARSE(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & SYSCTRL_DFLLVAL_COARSE_Msk) >> SYSCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_DIFF(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_sysctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & SYSCTRL_DFLLVAL_DIFF(mask)) >> SYSCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp &= ~SYSCTRL_DFLLVAL_DIFF_Msk; + tmp |= SYSCTRL_DFLLVAL_DIFF(data); + ((Sysctrl *)hw)->DFLLVAL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_DIFF(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_DIFF(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & SYSCTRL_DFLLVAL_DIFF_Msk) >> SYSCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_reg(const void *const hw, + hri_sysctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLVAL.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_sysctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_MUL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_sysctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & SYSCTRL_DFLLMUL_MUL(mask)) >> SYSCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp &= ~SYSCTRL_DFLLMUL_MUL_Msk; + tmp |= SYSCTRL_DFLLMUL_MUL(data); + ((Sysctrl *)hw)->DFLLMUL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_MUL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_MUL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & SYSCTRL_DFLLMUL_MUL_Msk) >> SYSCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_FSTEP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_sysctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & SYSCTRL_DFLLMUL_FSTEP(mask)) >> SYSCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp &= ~SYSCTRL_DFLLMUL_FSTEP_Msk; + tmp |= SYSCTRL_DFLLMUL_FSTEP(data); + ((Sysctrl *)hw)->DFLLMUL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_FSTEP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_FSTEP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & SYSCTRL_DFLLMUL_FSTEP_Msk) >> SYSCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_CSTEP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_sysctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & SYSCTRL_DFLLMUL_CSTEP(mask)) >> SYSCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp &= ~SYSCTRL_DFLLMUL_CSTEP_Msk; + tmp |= SYSCTRL_DFLLMUL_CSTEP(data); + ((Sysctrl *)hw)->DFLLMUL.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_CSTEP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_CSTEP(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & SYSCTRL_DFLLMUL_CSTEP_Msk) >> SYSCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_reg(const void *const hw, + hri_sysctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLMUL.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_sysctrl_set_DFLLSYNC_READREQ_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLSYNC.reg |= SYSCTRL_DFLLSYNC_READREQ; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DFLLSYNC_READREQ_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & SYSCTRL_DFLLSYNC_READREQ) >> SYSCTRL_DFLLSYNC_READREQ_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DFLLSYNC.reg; + tmp &= ~SYSCTRL_DFLLSYNC_READREQ; + tmp |= value << SYSCTRL_DFLLSYNC_READREQ_Pos; + ((Sysctrl *)hw)->DFLLSYNC.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLSYNC.reg &= ~SYSCTRL_DFLLSYNC_READREQ; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLSYNC.reg ^= SYSCTRL_DFLLSYNC_READREQ; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLSYNC.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllsync_reg_t hri_sysctrl_get_DFLLSYNC_reg(const void *const hw, + hri_sysctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLSYNC.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLSYNC.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DFLLSYNC.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dfllsync_reg_t hri_sysctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DFLLSYNC.reg; +} + +static inline void hri_sysctrl_set_BOD33_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_ENABLE) >> SYSCTRL_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_ENABLE; + tmp |= value << SYSCTRL_BOD33_ENABLE_Pos; + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_BOD33_HYST_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_HYST; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_BOD33_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_HYST) >> SYSCTRL_BOD33_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_BOD33_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_HYST; + tmp |= value << SYSCTRL_BOD33_HYST_Pos; + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_HYST_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_HYST; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_HYST_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_HYST; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_RUNSTDBY) >> SYSCTRL_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_RUNSTDBY; + tmp |= value << SYSCTRL_BOD33_RUNSTDBY_Pos; + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_BOD33_MODE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_MODE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_BOD33_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_MODE) >> SYSCTRL_BOD33_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_BOD33_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_MODE; + tmp |= value << SYSCTRL_BOD33_MODE_Pos; + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_MODE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_MODE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_MODE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_MODE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_BOD33_CEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_CEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_BOD33_CEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_CEN) >> SYSCTRL_BOD33_CEN_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_BOD33_CEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_CEN; + tmp |= value << SYSCTRL_BOD33_CEN_Pos; + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_CEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_CEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_CEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_CEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_ACTION(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_ACTION_bf(const void *const hw, + hri_sysctrl_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_ACTION(mask)) >> SYSCTRL_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_ACTION_Msk; + tmp |= SYSCTRL_BOD33_ACTION(data); + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_ACTION(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_ACTION(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_ACTION_Msk) >> SYSCTRL_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_PSEL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_PSEL(mask)) >> SYSCTRL_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_PSEL_Msk; + tmp |= SYSCTRL_BOD33_PSEL(data); + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_PSEL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_PSEL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_PSEL_Msk) >> SYSCTRL_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_LEVEL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_LEVEL(mask)) >> SYSCTRL_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= ~SYSCTRL_BOD33_LEVEL_Msk; + tmp |= SYSCTRL_BOD33_LEVEL(data); + ((Sysctrl *)hw)->BOD33.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_LEVEL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_LEVEL(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp = (tmp & SYSCTRL_BOD33_LEVEL_Msk) >> SYSCTRL_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->BOD33.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->BOD33.reg; +} + +static inline void hri_sysctrl_set_VREG_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg |= SYSCTRL_VREG_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_VREG_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->VREG.reg; + tmp = (tmp & SYSCTRL_VREG_RUNSTDBY) >> SYSCTRL_VREG_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->VREG.reg; + tmp &= ~SYSCTRL_VREG_RUNSTDBY; + tmp |= value << SYSCTRL_VREG_RUNSTDBY_Pos; + ((Sysctrl *)hw)->VREG.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_VREG_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg &= ~SYSCTRL_VREG_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_VREG_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg ^= SYSCTRL_VREG_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_VREG_FORCELDO_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg |= SYSCTRL_VREG_FORCELDO; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_VREG_FORCELDO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->VREG.reg; + tmp = (tmp & SYSCTRL_VREG_FORCELDO) >> SYSCTRL_VREG_FORCELDO_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_VREG_FORCELDO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->VREG.reg; + tmp &= ~SYSCTRL_VREG_FORCELDO; + tmp |= value << SYSCTRL_VREG_FORCELDO_Pos; + ((Sysctrl *)hw)->VREG.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_VREG_FORCELDO_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg &= ~SYSCTRL_VREG_FORCELDO; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_VREG_FORCELDO_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg ^= SYSCTRL_VREG_FORCELDO; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_vreg_reg_t hri_sysctrl_get_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sysctrl *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREG.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_vreg_reg_t hri_sysctrl_read_VREG_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->VREG.reg; +} + +static inline void hri_sysctrl_set_VREF_TSEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_TSEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp = (tmp & SYSCTRL_VREF_TSEN) >> SYSCTRL_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp &= ~SYSCTRL_VREF_TSEN; + tmp |= value << SYSCTRL_VREF_TSEN_Pos; + ((Sysctrl *)hw)->VREF.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_VREF_TSEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_TSEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_VREF_TSEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_TSEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_VREF_BGOUTEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_BGOUTEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_VREF_BGOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp = (tmp & SYSCTRL_VREF_BGOUTEN) >> SYSCTRL_VREF_BGOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_VREF_BGOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp &= ~SYSCTRL_VREF_BGOUTEN; + tmp |= value << SYSCTRL_VREF_BGOUTEN_Pos; + ((Sysctrl *)hw)->VREF.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_VREF_BGOUTEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_VREF_BGOUTEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_BGOUTEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_vref_reg_t hri_sysctrl_get_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp = (tmp & SYSCTRL_VREF_CALIB(mask)) >> SYSCTRL_VREF_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp &= ~SYSCTRL_VREF_CALIB_Msk; + tmp |= SYSCTRL_VREF_CALIB(data); + ((Sysctrl *)hw)->VREF.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_CALIB(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_vref_reg_t hri_sysctrl_read_VREF_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp = (tmp & SYSCTRL_VREF_CALIB_Msk) >> SYSCTRL_VREF_CALIB_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_vref_reg_t hri_sysctrl_get_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->VREF.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_vref_reg_t hri_sysctrl_read_VREF_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->VREF.reg; +} + +static inline void hri_sysctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLA_ENABLE) >> SYSCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~SYSCTRL_DPLLCTRLA_ENABLE; + tmp |= value << SYSCTRL_DPLLCTRLA_ENABLE_Pos; + ((Sysctrl *)hw)->DPLLCTRLA.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_ENABLE; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLA_RUNSTDBY) >> SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~SYSCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Sysctrl *)hw)->DPLLCTRLA.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_RUNSTDBY; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLA_ONDEMAND) >> SYSCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; + tmp &= ~SYSCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Sysctrl *)hw)->DPLLCTRLA.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_ONDEMAND; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrla_reg_t hri_sysctrl_get_DPLLCTRLA_reg(const void *const hw, + hri_sysctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLA.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrla_reg_t hri_sysctrl_read_DPLLCTRLA_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_sysctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg |= SYSCTRL_DPLLRATIO_LDR(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_sysctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & SYSCTRL_DPLLRATIO_LDR(mask)) >> SYSCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; + tmp &= ~SYSCTRL_DPLLRATIO_LDR_Msk; + tmp |= SYSCTRL_DPLLRATIO_LDR(data); + ((Sysctrl *)hw)->DPLLRATIO.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg &= ~SYSCTRL_DPLLRATIO_LDR(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg ^= SYSCTRL_DPLLRATIO_LDR(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & SYSCTRL_DPLLRATIO_LDR_Msk) >> SYSCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg |= SYSCTRL_DPLLRATIO_LDRFRAC(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_sysctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & SYSCTRL_DPLLRATIO_LDRFRAC(mask)) >> SYSCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; + tmp &= ~SYSCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= SYSCTRL_DPLLRATIO_LDRFRAC(data); + ((Sysctrl *)hw)->DPLLRATIO.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg &= ~SYSCTRL_DPLLRATIO_LDRFRAC(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg ^= SYSCTRL_DPLLRATIO_LDRFRAC(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; + tmp = (tmp & SYSCTRL_DPLLRATIO_LDRFRAC_Msk) >> SYSCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_reg(const void *const hw, + hri_sysctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLRATIO.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DPLLRATIO.reg; +} + +static inline void hri_sysctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LPEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_LPEN) >> SYSCTRL_DPLLCTRLB_LPEN_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~SYSCTRL_DPLLCTRLB_LPEN; + tmp |= value << SYSCTRL_DPLLCTRLB_LPEN_Pos; + ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LPEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LPEN; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_WUF; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_WUF) >> SYSCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~SYSCTRL_DPLLCTRLB_WUF; + tmp |= value << SYSCTRL_DPLLCTRLB_WUF_Pos; + ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_WUF; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_WUF; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LBYPASS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sysctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_LBYPASS) >> SYSCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~SYSCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << SYSCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LBYPASS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LBYPASS; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_FILTER(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_sysctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_FILTER(mask)) >> SYSCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~SYSCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= SYSCTRL_DPLLCTRLB_FILTER(data); + ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_FILTER(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_FILTER(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_FILTER_Msk) >> SYSCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_REFCLK(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_sysctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_REFCLK(mask)) >> SYSCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~SYSCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= SYSCTRL_DPLLCTRLB_REFCLK(data); + ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_REFCLK(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_REFCLK(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_REFCLK_Msk) >> SYSCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LTIME(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_sysctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_LTIME(mask)) >> SYSCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~SYSCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= SYSCTRL_DPLLCTRLB_LTIME(data); + ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LTIME(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LTIME(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_LTIME_Msk) >> SYSCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_DIV(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_sysctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_DIV(mask)) >> SYSCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + SYSCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= ~SYSCTRL_DPLLCTRLB_DIV_Msk; + tmp |= SYSCTRL_DPLLCTRLB_DIV(data); + ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_DIV(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_DIV(mask); + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp = (tmp & SYSCTRL_DPLLCTRLB_DIV_Msk) >> SYSCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_sysctrl_set_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg |= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_reg(const void *const hw, + hri_sysctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sysctrl_write_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg = data; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sysctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) +{ + SYSCTRL_CRITICAL_SECTION_ENTER(); + ((Sysctrl *)hw)->DPLLCTRLB.reg ^= mask; + SYSCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DPLLCTRLB.reg; +} + +static inline bool hri_sysctrl_get_PCLKSR_XOSCRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_XOSCRDY) >> SYSCTRL_PCLKSR_XOSCRDY_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_XOSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) >> SYSCTRL_PCLKSR_XOSC32KRDY_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_OSC32KRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY) >> SYSCTRL_PCLKSR_OSC32KRDY_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) >> SYSCTRL_PCLKSR_OSC8MRDY_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DFLLRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) >> SYSCTRL_PCLKSR_DFLLRDY_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DFLLOOB_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLOOB) >> SYSCTRL_PCLKSR_DFLLOOB_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DFLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) >> SYSCTRL_PCLKSR_DFLLLCKF_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DFLLLCKC_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) >> SYSCTRL_PCLKSR_DFLLLCKC_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DFLLRCS_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRCS) >> SYSCTRL_PCLKSR_DFLLRCS_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_BOD33RDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_BOD33RDY) >> SYSCTRL_PCLKSR_BOD33RDY_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_BOD33DET_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_BOD33DET) >> SYSCTRL_PCLKSR_BOD33DET_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_B33SRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_B33SRDY) >> SYSCTRL_PCLKSR_B33SRDY_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DPLLLCKR_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLCKR) >> SYSCTRL_PCLKSR_DPLLLCKR_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DPLLLCKF_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLCKF) >> SYSCTRL_PCLKSR_DPLLLCKF_Pos; +} + +static inline bool hri_sysctrl_get_PCLKSR_DPLLLTO_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLTO) >> SYSCTRL_PCLKSR_DPLLLTO_Pos; +} + +static inline hri_sysctrl_pclksr_reg_t hri_sysctrl_get_PCLKSR_reg(const void *const hw, hri_sysctrl_pclksr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sysctrl *)hw)->PCLKSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sysctrl_pclksr_reg_t hri_sysctrl_read_PCLKSR_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->PCLKSR.reg; +} + +static inline bool hri_sysctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_LOCK) >> SYSCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_sysctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_CLKRDY) >> SYSCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline bool hri_sysctrl_get_DPLLSTATUS_ENABLE_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE) >> SYSCTRL_DPLLSTATUS_ENABLE_Pos; +} + +static inline bool hri_sysctrl_get_DPLLSTATUS_DIV_bit(const void *const hw) +{ + return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_DIV) >> SYSCTRL_DPLLSTATUS_DIV_Pos; +} + +static inline hri_sysctrl_dpllstatus_reg_t hri_sysctrl_get_DPLLSTATUS_reg(const void *const hw, + hri_sysctrl_dpllstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sysctrl *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sysctrl_dpllstatus_reg_t hri_sysctrl_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((Sysctrl *)hw)->DPLLSTATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SYSCTRL_D21_H_INCLUDED */ +#endif /* _SAMD21_SYSCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h b/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h new file mode 100644 index 0000000000000..5969d32bf42e1 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h @@ -0,0 +1,1477 @@ +/** + * \file + * + * \brief SAM SystemControl + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_SystemControl_COMPONENT_ +#ifndef _HRI_SystemControl_D21_H_INCLUDED_ +#define _HRI_SystemControl_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) +#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SystemControl_CRITICAL_SECTION_ENTER() +#define SystemControl_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systemcontrol_aircr_reg_t; +typedef uint32_t hri_systemcontrol_ccr_reg_t; +typedef uint32_t hri_systemcontrol_cpuid_reg_t; +typedef uint32_t hri_systemcontrol_icsr_reg_t; +typedef uint32_t hri_systemcontrol_scr_reg_t; +typedef uint32_t hri_systemcontrol_shpr2_reg_t; +typedef uint32_t hri_systemcontrol_shpr3_reg_t; +typedef uint32_t hri_systemcontrol_vtor_reg_t; + +static inline void hri_systemcontrol_set_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_REVISION(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_REVISION(mask)) >> 0; + return tmp; +} + +static inline void hri_systemcontrol_write_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= ~SystemControl_CPUID_REVISION_Msk; + tmp |= SystemControl_CPUID_REVISION(data); + ((Systemcontrol *)hw)->CPUID.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_REVISION(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_REVISION(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_REVISION_Msk) >> 0; + return tmp; +} + +static inline void hri_systemcontrol_set_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_PARTNO(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_PARTNO(mask)) >> 4; + return tmp; +} + +static inline void hri_systemcontrol_write_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= ~SystemControl_CPUID_PARTNO_Msk; + tmp |= SystemControl_CPUID_PARTNO(data); + ((Systemcontrol *)hw)->CPUID.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_PARTNO(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_PARTNO(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_PARTNO_Msk) >> 4; + return tmp; +} + +static inline void hri_systemcontrol_set_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_ARCHITECTURE(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; + return tmp; +} + +static inline void hri_systemcontrol_write_CPUID_ARCHITECTURE_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= ~SystemControl_CPUID_ARCHITECTURE_Msk; + tmp |= SystemControl_CPUID_ARCHITECTURE(data); + ((Systemcontrol *)hw)->CPUID.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CPUID_ARCHITECTURE_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_ARCHITECTURE(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CPUID_ARCHITECTURE_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_ARCHITECTURE(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; + return tmp; +} + +static inline void hri_systemcontrol_set_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_VARIANT(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_VARIANT(mask)) >> 20; + return tmp; +} + +static inline void hri_systemcontrol_write_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= ~SystemControl_CPUID_VARIANT_Msk; + tmp |= SystemControl_CPUID_VARIANT(data); + ((Systemcontrol *)hw)->CPUID.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_VARIANT(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_VARIANT(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_VARIANT_Msk) >> 20; + return tmp; +} + +static inline void hri_systemcontrol_set_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_IMPLEMENTER(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t +hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; + return tmp; +} + +static inline void hri_systemcontrol_write_CPUID_IMPLEMENTER_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= ~SystemControl_CPUID_IMPLEMENTER_Msk; + tmp |= SystemControl_CPUID_IMPLEMENTER(data); + ((Systemcontrol *)hw)->CPUID.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CPUID_IMPLEMENTER_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_IMPLEMENTER(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CPUID_IMPLEMENTER_bf(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_IMPLEMENTER(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp = (tmp & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; + return tmp; +} + +static inline void hri_systemcontrol_set_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, + hri_systemcontrol_cpuid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CPUID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CPUID.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CPUID.reg; +} + +static inline void hri_systemcontrol_set_ICSR_PENDSTCLR_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTCLR; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_ICSR_PENDSTCLR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp = (tmp & SystemControl_ICSR_PENDSTCLR) >> 25; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_ICSR_PENDSTCLR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= ~SystemControl_ICSR_PENDSTCLR; + tmp |= value << 25; + ((Systemcontrol *)hw)->ICSR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_PENDSTCLR_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTCLR; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_PENDSTCLR_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTCLR; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_ICSR_PENDSTSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_ICSR_PENDSTSET_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp = (tmp & SystemControl_ICSR_PENDSTSET) >> 26; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_ICSR_PENDSTSET_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= ~SystemControl_ICSR_PENDSTSET; + tmp |= value << 26; + ((Systemcontrol *)hw)->ICSR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_PENDSTSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_PENDSTSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_ICSR_PENDSVCLR_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVCLR; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_ICSR_PENDSVCLR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp = (tmp & SystemControl_ICSR_PENDSVCLR) >> 27; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_ICSR_PENDSVCLR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= ~SystemControl_ICSR_PENDSVCLR; + tmp |= value << 27; + ((Systemcontrol *)hw)->ICSR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_PENDSVCLR_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVCLR; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_PENDSVCLR_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVCLR; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_ICSR_PENDSVSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_ICSR_PENDSVSET_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp = (tmp & SystemControl_ICSR_PENDSVSET) >> 28; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_ICSR_PENDSVSET_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= ~SystemControl_ICSR_PENDSVSET; + tmp |= value << 28; + ((Systemcontrol *)hw)->ICSR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_PENDSVSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_PENDSVSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_ICSR_NMIPENDSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_NMIPENDSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_ICSR_NMIPENDSET_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp = (tmp & SystemControl_ICSR_NMIPENDSET) >> 31; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_ICSR_NMIPENDSET_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= ~SystemControl_ICSR_NMIPENDSET; + tmp |= value << 31; + ((Systemcontrol *)hw)->ICSR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_NMIPENDSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_NMIPENDSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_NMIPENDSET_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_NMIPENDSET; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_VECTPENDING(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_VECTPENDING_bf(const void *const hw, + hri_systemcontrol_icsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp = (tmp & SystemControl_ICSR_VECTPENDING(mask)) >> 12; + return tmp; +} + +static inline void hri_systemcontrol_write_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= ~SystemControl_ICSR_VECTPENDING_Msk; + tmp |= SystemControl_ICSR_VECTPENDING(data); + ((Systemcontrol *)hw)->ICSR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_VECTPENDING(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_VECTPENDING(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_VECTPENDING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp = (tmp & SystemControl_ICSR_VECTPENDING_Msk) >> 12; + return tmp; +} + +static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, + hri_systemcontrol_icsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->ICSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->ICSR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->ICSR.reg; +} + +static inline void hri_systemcontrol_set_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg |= SystemControl_VTOR_TBLOFF(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_TBLOFF_bf(const void *const hw, + hri_systemcontrol_vtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp = (tmp & SystemControl_VTOR_TBLOFF(mask)) >> 7; + return tmp; +} + +static inline void hri_systemcontrol_write_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp &= ~SystemControl_VTOR_TBLOFF_Msk; + tmp |= SystemControl_VTOR_TBLOFF(data); + ((Systemcontrol *)hw)->VTOR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg &= ~SystemControl_VTOR_TBLOFF(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg ^= SystemControl_VTOR_TBLOFF(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_TBLOFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp = (tmp & SystemControl_VTOR_TBLOFF_Msk) >> 7; + return tmp; +} + +static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, + hri_systemcontrol_vtor_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->VTOR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->VTOR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->VTOR.reg; +} + +static inline void hri_systemcontrol_set_AIRCR_VECTCLRACTIVE_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTCLRACTIVE; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_AIRCR_VECTCLRACTIVE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp = (tmp & SystemControl_AIRCR_VECTCLRACTIVE) >> 1; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_VECTCLRACTIVE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= ~SystemControl_AIRCR_VECTCLRACTIVE; + tmp |= value << 1; + ((Systemcontrol *)hw)->AIRCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_VECTCLRACTIVE_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTCLRACTIVE; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_VECTCLRACTIVE_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTCLRACTIVE; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_AIRCR_SYSRESETREQ_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_SYSRESETREQ; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_AIRCR_SYSRESETREQ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp = (tmp & SystemControl_AIRCR_SYSRESETREQ) >> 2; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_SYSRESETREQ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= ~SystemControl_AIRCR_SYSRESETREQ; + tmp |= value << 2; + ((Systemcontrol *)hw)->AIRCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_SYSRESETREQ_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_SYSRESETREQ; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_SYSRESETREQ_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_SYSRESETREQ; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_AIRCR_ENDIANNESS_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_ENDIANNESS; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_AIRCR_ENDIANNESS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp = (tmp & SystemControl_AIRCR_ENDIANNESS) >> 15; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_ENDIANNESS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= ~SystemControl_AIRCR_ENDIANNESS; + tmp |= value << 15; + ((Systemcontrol *)hw)->AIRCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_ENDIANNESS_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_ENDIANNESS; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_ENDIANNESS_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_ENDIANNESS; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTKEY(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_VECTKEY_bf(const void *const hw, + hri_systemcontrol_aircr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp = (tmp & SystemControl_AIRCR_VECTKEY(mask)) >> 16; + return tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= ~SystemControl_AIRCR_VECTKEY_Msk; + tmp |= SystemControl_AIRCR_VECTKEY(data); + ((Systemcontrol *)hw)->AIRCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTKEY(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTKEY(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_VECTKEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp = (tmp & SystemControl_AIRCR_VECTKEY_Msk) >> 16; + return tmp; +} + +static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, + hri_systemcontrol_aircr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->AIRCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->AIRCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->AIRCR.reg; +} + +static inline void hri_systemcontrol_set_SCR_SLEEPONEXIT_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPONEXIT; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_SCR_SLEEPONEXIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp = (tmp & SystemControl_SCR_SLEEPONEXIT) >> 1; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_SCR_SLEEPONEXIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= ~SystemControl_SCR_SLEEPONEXIT; + tmp |= value << 1; + ((Systemcontrol *)hw)->SCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_SLEEPONEXIT_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPONEXIT; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_SLEEPONEXIT_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPONEXIT; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_SCR_SLEEPDEEP_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPDEEP; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_SCR_SLEEPDEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp = (tmp & SystemControl_SCR_SLEEPDEEP) >> 2; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_SCR_SLEEPDEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= ~SystemControl_SCR_SLEEPDEEP; + tmp |= value << 2; + ((Systemcontrol *)hw)->SCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_SLEEPDEEP_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPDEEP; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_SLEEPDEEP_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPDEEP; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_SCR_SEVONPEND_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SEVONPEND; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_SCR_SEVONPEND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp = (tmp & SystemControl_SCR_SEVONPEND) >> 4; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_SCR_SEVONPEND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= ~SystemControl_SCR_SEVONPEND; + tmp |= value << 4; + ((Systemcontrol *)hw)->SCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_SEVONPEND_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SEVONPEND; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_SEVONPEND_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SEVONPEND; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, + hri_systemcontrol_scr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SCR.reg; +} + +static inline void hri_systemcontrol_set_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_UNALIGN_TRP; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp = (tmp & SystemControl_CCR_UNALIGN_TRP) >> 3; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_CCR_UNALIGN_TRP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= ~SystemControl_CCR_UNALIGN_TRP; + tmp |= value << 3; + ((Systemcontrol *)hw)->CCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_UNALIGN_TRP; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CCR_UNALIGN_TRP_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_UNALIGN_TRP; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_CCR_STKALIGN_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_STKALIGN; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp = (tmp & SystemControl_CCR_STKALIGN) >> 9; + return (bool)tmp; +} + +static inline void hri_systemcontrol_write_CCR_STKALIGN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= ~SystemControl_CCR_STKALIGN; + tmp |= value << 9; + ((Systemcontrol *)hw)->CCR.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CCR_STKALIGN_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_STKALIGN; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CCR_STKALIGN_bit(const void *const hw) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_STKALIGN; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_set_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, + hri_systemcontrol_ccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->CCR.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->CCR.reg; +} + +static inline void hri_systemcontrol_set_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg |= SystemControl_SHPR2_PRI_11(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_PRI_11_bf(const void *const hw, + hri_systemcontrol_shpr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp = (tmp & SystemControl_SHPR2_PRI_11(mask)) >> 24; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp &= ~SystemControl_SHPR2_PRI_11_Msk; + tmp |= SystemControl_SHPR2_PRI_11(data); + ((Systemcontrol *)hw)->SHPR2.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg &= ~SystemControl_SHPR2_PRI_11(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg ^= SystemControl_SHPR2_PRI_11(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_PRI_11_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp = (tmp & SystemControl_SHPR2_PRI_11_Msk) >> 24; + return tmp; +} + +static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, + hri_systemcontrol_shpr2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR2.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR2.reg; +} + +static inline void hri_systemcontrol_set_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_14(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_14_bf(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp = (tmp & SystemControl_SHPR3_PRI_14(mask)) >> 16; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= ~SystemControl_SHPR3_PRI_14_Msk; + tmp |= SystemControl_SHPR3_PRI_14(data); + ((Systemcontrol *)hw)->SHPR3.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_14(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_14(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_14_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp = (tmp & SystemControl_SHPR3_PRI_14_Msk) >> 16; + return tmp; +} + +static inline void hri_systemcontrol_set_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_15(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_15_bf(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp = (tmp & SystemControl_SHPR3_PRI_15(mask)) >> 24; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + uint32_t tmp; + SystemControl_CRITICAL_SECTION_ENTER(); + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= ~SystemControl_SHPR3_PRI_15_Msk; + tmp |= SystemControl_SHPR3_PRI_15(data); + ((Systemcontrol *)hw)->SHPR3.reg = tmp; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_15(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_15(mask); + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_15_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp = (tmp & SystemControl_SHPR3_PRI_15_Msk) >> 24; + return tmp; +} + +static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg |= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, + hri_systemcontrol_shpr3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systemcontrol *)hw)->SHPR3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg = data; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) +{ + SystemControl_CRITICAL_SECTION_ENTER(); + ((Systemcontrol *)hw)->SHPR3.reg ^= mask; + SystemControl_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) +{ + return ((Systemcontrol *)hw)->SHPR3.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SystemControl_D21_H_INCLUDED */ +#endif /* _SAMD21_SystemControl_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_systick_d21.h b/atmel-samd/asf4/samd21/hri/hri_systick_d21.h new file mode 100644 index 0000000000000..34d4558c04056 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_systick_d21.h @@ -0,0 +1,620 @@ +/** + * \file + * + * \brief SAM SysTick + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_SysTick_COMPONENT_ +#ifndef _HRI_SysTick_D21_H_INCLUDED_ +#define _HRI_SysTick_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) +#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SysTick_CRITICAL_SECTION_ENTER() +#define SysTick_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_systick_calib_reg_t; +typedef uint32_t hri_systick_csr_reg_t; +typedef uint32_t hri_systick_cvr_reg_t; +typedef uint32_t hri_systick_rvr_reg_t; + +static inline void hri_systick_set_CSR_ENABLE_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= SysTick_CSR_ENABLE; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systick_get_CSR_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp = (tmp & SysTick_CSR_ENABLE) >> 0; + return (bool)tmp; +} + +static inline void hri_systick_write_CSR_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CSR.reg; + tmp &= ~SysTick_CSR_ENABLE; + tmp |= value << 0; + ((Systick *)hw)->CSR.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_ENABLE_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_ENABLE; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_ENABLE_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= SysTick_CSR_ENABLE; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_set_CSR_TICKINT_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= SysTick_CSR_TICKINT; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systick_get_CSR_TICKINT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp = (tmp & SysTick_CSR_TICKINT) >> 1; + return (bool)tmp; +} + +static inline void hri_systick_write_CSR_TICKINT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CSR.reg; + tmp &= ~SysTick_CSR_TICKINT; + tmp |= value << 1; + ((Systick *)hw)->CSR.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_TICKINT_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_TICKINT; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_TICKINT_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= SysTick_CSR_TICKINT; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_set_CSR_CLKSOURCE_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= SysTick_CSR_CLKSOURCE; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systick_get_CSR_CLKSOURCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp = (tmp & SysTick_CSR_CLKSOURCE) >> 2; + return (bool)tmp; +} + +static inline void hri_systick_write_CSR_CLKSOURCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CSR.reg; + tmp &= ~SysTick_CSR_CLKSOURCE; + tmp |= value << 2; + ((Systick *)hw)->CSR.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_CLKSOURCE_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_CLKSOURCE; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_CLKSOURCE_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= SysTick_CSR_CLKSOURCE; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_set_CSR_COUNTFLAG_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= SysTick_CSR_COUNTFLAG; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systick_get_CSR_COUNTFLAG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp = (tmp & SysTick_CSR_COUNTFLAG) >> 16; + return (bool)tmp; +} + +static inline void hri_systick_write_CSR_COUNTFLAG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CSR.reg; + tmp &= ~SysTick_CSR_COUNTFLAG; + tmp |= value << 16; + ((Systick *)hw)->CSR.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_COUNTFLAG_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_COUNTFLAG; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_COUNTFLAG_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= SysTick_CSR_COUNTFLAG; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CSR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) +{ + return ((Systick *)hw)->CSR.reg; +} + +static inline void hri_systick_set_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg |= SysTick_RVR_RELOAD(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_get_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp = (tmp & SysTick_RVR_RELOAD(mask)) >> 0; + return tmp; +} + +static inline void hri_systick_write_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t data) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->RVR.reg; + tmp &= ~SysTick_RVR_RELOAD_Msk; + tmp |= SysTick_RVR_RELOAD(data); + ((Systick *)hw)->RVR.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg &= ~SysTick_RVR_RELOAD(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg ^= SysTick_RVR_RELOAD(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_read_RVR_RELOAD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp = (tmp & SysTick_RVR_RELOAD_Msk) >> 0; + return tmp; +} + +static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->RVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->RVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) +{ + return ((Systick *)hw)->RVR.reg; +} + +static inline void hri_systick_set_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg |= SysTick_CVR_CURRENT(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_get_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp = (tmp & SysTick_CVR_CURRENT(mask)) >> 0; + return tmp; +} + +static inline void hri_systick_write_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t data) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CVR.reg; + tmp &= ~SysTick_CVR_CURRENT_Msk; + tmp |= SysTick_CVR_CURRENT(data); + ((Systick *)hw)->CVR.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg &= ~SysTick_CVR_CURRENT(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg ^= SysTick_CVR_CURRENT(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_read_CVR_CURRENT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp = (tmp & SysTick_CVR_CURRENT_Msk) >> 0; + return tmp; +} + +static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CVR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CVR.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) +{ + return ((Systick *)hw)->CVR.reg; +} + +static inline void hri_systick_set_CALIB_SKEW_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg |= SysTick_CALIB_SKEW; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp = (tmp & SysTick_CALIB_SKEW) >> 30; + return (bool)tmp; +} + +static inline void hri_systick_write_CALIB_SKEW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= ~SysTick_CALIB_SKEW; + tmp |= value << 30; + ((Systick *)hw)->CALIB.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CALIB_SKEW_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_SKEW; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CALIB_SKEW_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_SKEW; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_set_CALIB_NOREF_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg |= SysTick_CALIB_NOREF; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp = (tmp & SysTick_CALIB_NOREF) >> 31; + return (bool)tmp; +} + +static inline void hri_systick_write_CALIB_NOREF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= ~SysTick_CALIB_NOREF; + tmp |= value << 31; + ((Systick *)hw)->CALIB.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CALIB_NOREF_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_NOREF; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CALIB_NOREF_bit(const void *const hw) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_NOREF; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_set_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg |= SysTick_CALIB_TENMS(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp = (tmp & SysTick_CALIB_TENMS(mask)) >> 0; + return tmp; +} + +static inline void hri_systick_write_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t data) +{ + uint32_t tmp; + SysTick_CRITICAL_SECTION_ENTER(); + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= ~SysTick_CALIB_TENMS_Msk; + tmp |= SysTick_CALIB_TENMS(data); + ((Systick *)hw)->CALIB.reg = tmp; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_TENMS(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_TENMS(mask); + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp = (tmp & SysTick_CALIB_TENMS_Msk) >> 0; + return tmp; +} + +static inline void hri_systick_set_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg |= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + uint32_t tmp; + tmp = ((Systick *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_systick_write_CALIB_reg(const void *const hw, hri_systick_calib_reg_t data) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg = data; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_clear_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg &= ~mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_systick_toggle_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) +{ + SysTick_CRITICAL_SECTION_ENTER(); + ((Systick *)hw)->CALIB.reg ^= mask; + SysTick_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) +{ + return ((Systick *)hw)->CALIB.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SysTick_D21_H_INCLUDED */ +#endif /* _SAMD21_SysTick_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_tc_d21.h b/atmel-samd/asf4/samd21/hri/hri_tc_d21.h new file mode 100644 index 0000000000000..08058f4f7f187 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_tc_d21.h @@ -0,0 +1,2190 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_TC_COMPONENT_ +#ifndef _HRI_TC_D21_H_INCLUDED_ +#define _HRI_TC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_cc16_reg_t; +typedef uint16_t hri_tc_count16_reg_t; +typedef uint16_t hri_tc_ctrla_reg_t; +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tc_readreq_reg_t; +typedef uint32_t hri_tc_cc32_reg_t; +typedef uint32_t hri_tc_count32_reg_t; +typedef uint8_t hri_tc_cc8_reg_t; +typedef uint8_t hri_tc_count8_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_ctrlc_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_per_reg_t; +typedef uint8_t hri_tc_status_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw) +{ + while (((const Tc *)hw)->COUNT8.STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_tc_is_syncing(const void *const hw) +{ + return ((const Tc *)hw)->COUNT8.STATUS.bit.SYNCBUSY; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tc_count16_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tc_count32_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_SYNCRDY; +} + +static inline bool hri_tc_get_INTEN_SYNCRDY_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_SYNCRDY) >> TC_INTENSET_SYNCRDY_Pos; +} + +static inline void hri_tc_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_SYNCRDY; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_SYNCRDY; + } +} + +static inline void hri_tc_clear_INTEN_SYNCRDY_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_SYNCRDY; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = data; + ((Tc *)hw)->COUNT8.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_SYNCRDY) >> TC_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_tc_clear_INTFLAG_SYNCRDY_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_SYNCRDY; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_SYNCRDY_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_SYNCRDY) >> TC_INTFLAG_SYNCRDY_Pos; +} + +static inline void hri_tc_clear_interrupt_SYNCRDY_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_SYNCRDY; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ENABLE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ENABLE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ENABLE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_MODE(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_MODE(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_WAVEGEN(mask)) >> TC_CTRLA_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_WAVEGEN_Msk; + tmp |= TC_CTRLA_WAVEGEN(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_WAVEGEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_WAVEGEN_Msk) >> TC_CTRLA_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.CTRLA.reg; +} + +static inline void hri_tc_set_READREQ_RCONT_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_RCONT; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_READREQ_RCONT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp = (tmp & TC_READREQ_RCONT) >> TC_READREQ_RCONT_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_READREQ_RCONT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp &= ~TC_READREQ_RCONT; + tmp |= value << TC_READREQ_RCONT_Pos; + ((Tc *)hw)->COUNT8.READREQ.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_READREQ_RCONT_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_RCONT; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_READREQ_RCONT_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_RCONT; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_READREQ_RREQ_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_RREQ; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_READREQ_RREQ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp = (tmp & TC_READREQ_RREQ) >> TC_READREQ_RREQ_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_READREQ_RREQ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp &= ~TC_READREQ_RREQ; + tmp |= value << TC_READREQ_RREQ_Pos; + ((Tc *)hw)->COUNT8.READREQ.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_READREQ_RREQ_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_RREQ; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_READREQ_RREQ_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_RREQ; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_ADDR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_readreq_reg_t hri_tc_get_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp = (tmp & TC_READREQ_ADDR(mask)) >> TC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_tc_write_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp &= ~TC_READREQ_ADDR_Msk; + tmp |= TC_READREQ_ADDR(data); + ((Tc *)hw)->COUNT8.READREQ.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_ADDR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_ADDR(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_readreq_reg_t hri_tc_read_READREQ_ADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp = (tmp & TC_READREQ_ADDR_Msk) >> TC_READREQ_ADDR_Pos; + return tmp; +} + +static inline void hri_tc_set_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_readreq_reg_t hri_tc_get_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.READREQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.READREQ.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_readreq_reg_t hri_tc_read_READREQ_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.READREQ.reg; +} + +static inline void hri_tc_set_CTRLC_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLC_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp = (tmp & TC_CTRLC_INVEN0) >> TC_CTRLC_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLC_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp &= ~TC_CTRLC_INVEN0; + tmp |= value << TC_CTRLC_INVEN0_Pos; + ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLC_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLC_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLC_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLC_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp = (tmp & TC_CTRLC_INVEN1) >> TC_CTRLC_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLC_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp &= ~TC_CTRLC_INVEN1; + tmp |= value << TC_CTRLC_INVEN1_Pos; + ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLC_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLC_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLC_CPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_CPTEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLC_CPTEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp = (tmp & TC_CTRLC_CPTEN0) >> TC_CTRLC_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLC_CPTEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp &= ~TC_CTRLC_CPTEN0; + tmp |= value << TC_CTRLC_CPTEN0_Pos; + ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLC_CPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_CPTEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLC_CPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_CPTEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLC_CPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_CPTEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLC_CPTEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp = (tmp & TC_CTRLC_CPTEN1) >> TC_CTRLC_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLC_CPTEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp &= ~TC_CTRLC_CPTEN1; + tmp |= value << TC_CTRLC_CPTEN1_Pos; + ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLC_CPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_CPTEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLC_CPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_CPTEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrlc_reg_t hri_tc_get_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLC.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrlc_reg_t hri_tc_read_CTRLC_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.CTRLC.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT8.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.DBGCTRL.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.EVCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tc_count8_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tc_set_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_get_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tc_write_PER_PER_bf(const void *const hw, hri_tc_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tc_set_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_get_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_PER_reg(const void *const hw, hri_tc_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_read_PER_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline bool hri_tc_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SYNCBUSY) >> TC_STATUS_SYNCBUSY_Pos; +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_D21_H_INCLUDED */ +#endif /* _SAMD21_TC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h b/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h new file mode 100644 index 0000000000000..051c8c8216865 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h @@ -0,0 +1,10318 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_TCC_COMPONENT_ +#ifndef _HRI_TCC_D21_H_INCLUDED_ +#define _HRI_TCC_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattb_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccb_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perb_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_waveb_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH4_COUNT(mask)) >> TCC_COUNT_DITH4_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_DITH4_COUNT_Msk; + tmp |= TCC_COUNT_DITH4_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH4_COUNT_Msk) >> TCC_COUNT_DITH4_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH5_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH5_COUNT(mask)) >> TCC_COUNT_DITH5_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_DITH5_COUNT_Msk; + tmp |= TCC_COUNT_DITH5_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH5_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH5_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH5_COUNT_Msk) >> TCC_COUNT_DITH5_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH6_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH6_COUNT(mask)) >> TCC_COUNT_DITH6_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_DITH6_COUNT_Msk; + tmp |= TCC_COUNT_DITH6_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH6_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH6_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH6_COUNT_Msk) >> TCC_COUNT_DITH6_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHERCY(mask)) >> TCC_PER_DITH4_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHERCY_Msk; + tmp |= TCC_PER_DITH4_DITHERCY(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHERCY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHERCY_Msk) >> TCC_PER_DITH4_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_PER(mask)) >> TCC_PER_DITH4_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_PER_Msk; + tmp |= TCC_PER_DITH4_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_PER_Msk) >> TCC_PER_DITH4_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHERCY(mask)) >> TCC_PER_DITH5_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHERCY_Msk; + tmp |= TCC_PER_DITH5_DITHERCY(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHERCY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHERCY_Msk) >> TCC_PER_DITH5_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_PER(mask)) >> TCC_PER_DITH5_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_PER_Msk; + tmp |= TCC_PER_DITH5_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_PER_Msk) >> TCC_PER_DITH5_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHERCY(mask)) >> TCC_PER_DITH6_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHERCY_Msk; + tmp |= TCC_PER_DITH6_DITHERCY(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHERCY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHERCY_Msk) >> TCC_PER_DITH6_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_PER(mask)) >> TCC_PER_DITH6_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_PER_Msk; + tmp |= TCC_PER_DITH6_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_PER_Msk) >> TCC_PER_DITH6_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHERCY(mask)) >> TCC_CC_DITH4_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHERCY_Msk; + tmp |= TCC_CC_DITH4_DITHERCY(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHERCY_Msk) >> TCC_CC_DITH4_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_CC(mask)) >> TCC_CC_DITH4_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_CC_Msk; + tmp |= TCC_CC_DITH4_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_CC_Msk) >> TCC_CC_DITH4_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHERCY(mask)) >> TCC_CC_DITH5_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHERCY_Msk; + tmp |= TCC_CC_DITH5_DITHERCY(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHERCY_Msk) >> TCC_CC_DITH5_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_CC(mask)) >> TCC_CC_DITH5_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_CC_Msk; + tmp |= TCC_CC_DITH5_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_CC_Msk) >> TCC_CC_DITH5_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHERCY(mask)) >> TCC_CC_DITH6_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHERCY_Msk; + tmp |= TCC_CC_DITH6_DITHERCY(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHERCY(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHERCY_Msk) >> TCC_CC_DITH6_DITHERCY_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_CC(mask)) >> TCC_CC_DITH6_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_CC_Msk; + tmp |= TCC_CC_DITH6_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_CC_Msk) >> TCC_CC_DITH6_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH4_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH4_DITHERCYB(mask)) >> TCC_PERB_DITH4_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= ~TCC_PERB_DITH4_DITHERCYB_Msk; + tmp |= TCC_PERB_DITH4_DITHERCYB(data); + ((Tcc *)hw)->PERB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH4_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH4_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_DITHERCYB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH4_DITHERCYB_Msk) >> TCC_PERB_DITH4_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH4_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH4_PERB(mask)) >> TCC_PERB_DITH4_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= ~TCC_PERB_DITH4_PERB_Msk; + tmp |= TCC_PERB_DITH4_PERB(data); + ((Tcc *)hw)->PERB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH4_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH4_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_PERB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH4_PERB_Msk) >> TCC_PERB_DITH4_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH5_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH5_DITHERCYB(mask)) >> TCC_PERB_DITH5_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= ~TCC_PERB_DITH5_DITHERCYB_Msk; + tmp |= TCC_PERB_DITH5_DITHERCYB(data); + ((Tcc *)hw)->PERB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH5_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH5_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_DITHERCYB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH5_DITHERCYB_Msk) >> TCC_PERB_DITH5_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH5_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH5_PERB(mask)) >> TCC_PERB_DITH5_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= ~TCC_PERB_DITH5_PERB_Msk; + tmp |= TCC_PERB_DITH5_PERB(data); + ((Tcc *)hw)->PERB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH5_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH5_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_PERB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH5_PERB_Msk) >> TCC_PERB_DITH5_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH6_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH6_DITHERCYB(mask)) >> TCC_PERB_DITH6_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= ~TCC_PERB_DITH6_DITHERCYB_Msk; + tmp |= TCC_PERB_DITH6_DITHERCYB(data); + ((Tcc *)hw)->PERB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH6_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH6_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_DITHERCYB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH6_DITHERCYB_Msk) >> TCC_PERB_DITH6_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH6_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH6_PERB(mask)) >> TCC_PERB_DITH6_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= ~TCC_PERB_DITH6_PERB_Msk; + tmp |= TCC_PERB_DITH6_PERB(data); + ((Tcc *)hw)->PERB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH6_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH6_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_PERB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_DITH6_PERB_Msk) >> TCC_PERB_DITH6_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= TCC_PERB_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_PERB(mask)) >> TCC_PERB_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= ~TCC_PERB_PERB_Msk; + tmp |= TCC_PERB_PERB(data); + ((Tcc *)hw)->PERB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= TCC_PERB_PERB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_PERB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp = (tmp & TCC_PERB_PERB_Msk) >> TCC_PERB_PERB_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERB.reg; +} + +static inline void hri_tcc_set_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERB.reg; +} + +static inline void hri_tcc_set_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERB.reg; +} + +static inline void hri_tcc_set_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERB_reg(const void *const hw, hri_tcc_perb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERB.reg; +} + +static inline void hri_tcc_set_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH4_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, + hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH4_DITHERCYB(mask)) >> TCC_CCB_DITH4_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= ~TCC_CCB_DITH4_DITHERCYB_Msk; + tmp |= TCC_CCB_DITH4_DITHERCYB(data); + ((Tcc *)hw)->CCB[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH4_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH4_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH4_DITHERCYB_Msk) >> TCC_CCB_DITH4_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH4_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, + hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH4_CCB(mask)) >> TCC_CCB_DITH4_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= ~TCC_CCB_DITH4_CCB_Msk; + tmp |= TCC_CCB_DITH4_CCB(data); + ((Tcc *)hw)->CCB[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH4_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH4_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH4_CCB_Msk) >> TCC_CCB_DITH4_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH5_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, + hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH5_DITHERCYB(mask)) >> TCC_CCB_DITH5_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= ~TCC_CCB_DITH5_DITHERCYB_Msk; + tmp |= TCC_CCB_DITH5_DITHERCYB(data); + ((Tcc *)hw)->CCB[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH5_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH5_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH5_DITHERCYB_Msk) >> TCC_CCB_DITH5_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH5_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, + hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH5_CCB(mask)) >> TCC_CCB_DITH5_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= ~TCC_CCB_DITH5_CCB_Msk; + tmp |= TCC_CCB_DITH5_CCB(data); + ((Tcc *)hw)->CCB[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH5_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH5_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH5_CCB_Msk) >> TCC_CCB_DITH5_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH6_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, + hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH6_DITHERCYB(mask)) >> TCC_CCB_DITH6_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= ~TCC_CCB_DITH6_DITHERCYB_Msk; + tmp |= TCC_CCB_DITH6_DITHERCYB(data); + ((Tcc *)hw)->CCB[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH6_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH6_DITHERCYB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH6_DITHERCYB_Msk) >> TCC_CCB_DITH6_DITHERCYB_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH6_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, + hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH6_CCB(mask)) >> TCC_CCB_DITH6_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= ~TCC_CCB_DITH6_CCB_Msk; + tmp |= TCC_CCB_DITH6_CCB(data); + ((Tcc *)hw)->CCB[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH6_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH6_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_DITH6_CCB_Msk) >> TCC_CCB_DITH6_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_CCB(mask)) >> TCC_CCB_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= ~TCC_CCB_CCB_Msk; + tmp |= TCC_CCB_CCB(data); + ((Tcc *)hw)->CCB[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_CCB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_CCB_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp = (tmp & TCC_CCB_CCB_Msk) >> TCC_CCB_CCB_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCB[index].reg; +} + +static inline void hri_tcc_set_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCB[index].reg; +} + +static inline void hri_tcc_set_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCB[index].reg; +} + +static inline void hri_tcc_set_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCB[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCB[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCB[index].reg; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PATTB_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB0) >> TCC_PATTB_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB0; + tmp |= value << TCC_PATTB_PGEB0_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB1) >> TCC_PATTB_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB1; + tmp |= value << TCC_PATTB_PGEB1_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB2) >> TCC_PATTB_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB2; + tmp |= value << TCC_PATTB_PGEB2_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB3) >> TCC_PATTB_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB3; + tmp |= value << TCC_PATTB_PGEB3_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB4) >> TCC_PATTB_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB4; + tmp |= value << TCC_PATTB_PGEB4_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB5) >> TCC_PATTB_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB5; + tmp |= value << TCC_PATTB_PGEB5_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB6) >> TCC_PATTB_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB6; + tmp |= value << TCC_PATTB_PGEB6_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGEB7) >> TCC_PATTB_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGEB7; + tmp |= value << TCC_PATTB_PGEB7_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB0) >> TCC_PATTB_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB0; + tmp |= value << TCC_PATTB_PGVB0_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB1) >> TCC_PATTB_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB1; + tmp |= value << TCC_PATTB_PGVB1_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB2) >> TCC_PATTB_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB2; + tmp |= value << TCC_PATTB_PGVB2_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB3) >> TCC_PATTB_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB3; + tmp |= value << TCC_PATTB_PGVB3_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB4) >> TCC_PATTB_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB4; + tmp |= value << TCC_PATTB_PGVB4_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB5) >> TCC_PATTB_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB5; + tmp |= value << TCC_PATTB_PGVB5_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB6) >> TCC_PATTB_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB6; + tmp |= value << TCC_PATTB_PGVB6_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTB_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp = (tmp & TCC_PATTB_PGVB7) >> TCC_PATTB_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTB_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= ~TCC_PATTB_PGVB7; + tmp |= value << TCC_PATTB_PGVB7_Pos; + ((Tcc *)hw)->PATTB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattb_reg_t hri_tcc_get_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattb_reg_t hri_tcc_read_PATTB_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTB.reg; +} + +static inline void hri_tcc_set_WAVEB_CIPERENB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CIPERENB; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_CIPERENB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_CIPERENB) >> TCC_WAVEB_CIPERENB_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_CIPERENB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_CIPERENB; + tmp |= value << TCC_WAVEB_CIPERENB_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_CIPERENB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CIPERENB; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_CIPERENB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CIPERENB; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_CICCENB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_CICCENB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_CICCENB0) >> TCC_WAVEB_CICCENB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_CICCENB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_CICCENB0; + tmp |= value << TCC_WAVEB_CICCENB0_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_CICCENB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_CICCENB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_CICCENB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_CICCENB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_CICCENB1) >> TCC_WAVEB_CICCENB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_CICCENB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_CICCENB1; + tmp |= value << TCC_WAVEB_CICCENB1_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_CICCENB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_CICCENB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_CICCENB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_CICCENB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_CICCENB2) >> TCC_WAVEB_CICCENB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_CICCENB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_CICCENB2; + tmp |= value << TCC_WAVEB_CICCENB2_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_CICCENB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_CICCENB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_CICCENB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_CICCENB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_CICCENB3) >> TCC_WAVEB_CICCENB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_CICCENB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_CICCENB3; + tmp |= value << TCC_WAVEB_CICCENB3_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_CICCENB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_CICCENB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_POLB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_POLB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_POLB0) >> TCC_WAVEB_POLB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_POLB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_POLB0; + tmp |= value << TCC_WAVEB_POLB0_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_POLB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_POLB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_POLB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_POLB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_POLB1) >> TCC_WAVEB_POLB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_POLB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_POLB1; + tmp |= value << TCC_WAVEB_POLB1_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_POLB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_POLB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_POLB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_POLB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_POLB2) >> TCC_WAVEB_POLB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_POLB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_POLB2; + tmp |= value << TCC_WAVEB_POLB2_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_POLB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_POLB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_POLB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_POLB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_POLB3) >> TCC_WAVEB_POLB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_POLB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_POLB3; + tmp |= value << TCC_WAVEB_POLB3_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_POLB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_POLB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_SWAPB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_SWAPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_SWAPB0) >> TCC_WAVEB_SWAPB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_SWAPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_SWAPB0; + tmp |= value << TCC_WAVEB_SWAPB0_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_SWAPB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_SWAPB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_SWAPB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_SWAPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_SWAPB1) >> TCC_WAVEB_SWAPB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_SWAPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_SWAPB1; + tmp |= value << TCC_WAVEB_SWAPB1_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_SWAPB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_SWAPB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_SWAPB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_SWAPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_SWAPB2) >> TCC_WAVEB_SWAPB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_SWAPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_SWAPB2; + tmp |= value << TCC_WAVEB_SWAPB2_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_SWAPB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_SWAPB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_SWAPB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVEB_SWAPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_SWAPB3) >> TCC_WAVEB_SWAPB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVEB_SWAPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_SWAPB3; + tmp |= value << TCC_WAVEB_SWAPB3_Pos; + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_SWAPB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_SWAPB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_WAVEGENB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_WAVEGENB(mask)) >> TCC_WAVEB_WAVEGENB_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_WAVEGENB_Msk; + tmp |= TCC_WAVEB_WAVEGENB(data); + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_WAVEGENB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_WAVEGENB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_WAVEGENB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_WAVEGENB_Msk) >> TCC_WAVEB_WAVEGENB_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_RAMPB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_RAMPB(mask)) >> TCC_WAVEB_RAMPB_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= ~TCC_WAVEB_RAMPB_Msk; + tmp |= TCC_WAVEB_RAMPB(data); + ((Tcc *)hw)->WAVEB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_RAMPB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_RAMPB(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_RAMPB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp = (tmp & TCC_WAVEB_RAMPB_Msk) >> TCC_WAVEB_RAMPB_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVEB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVEB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_reg(const void *const hw) +{ + return ((Tcc *)hw)->WAVEB.reg; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATTB) >> TCC_SYNCBUSY_PATTB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVEB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVEB) >> TCC_SYNCBUSY_WAVEB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PERB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PERB) >> TCC_SYNCBUSY_PERB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CCB0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB0) >> TCC_SYNCBUSY_CCB0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CCB1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB1) >> TCC_SYNCBUSY_CCB1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CCB2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB2) >> TCC_SYNCBUSY_CCB2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CCB3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB3) >> TCC_SYNCBUSY_CCB3_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBV) >> TCC_STATUS_PATTBV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBV; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_WAVEBV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_WAVEBV) >> TCC_STATUS_WAVEBV_Pos; +} + +static inline void hri_tcc_clear_STATUS_WAVEBV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_WAVEBV; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBV) >> TCC_STATUS_PERBV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBV; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV0) >> TCC_STATUS_CCBV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV1) >> TCC_STATUS_CCBV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV2) >> TCC_STATUS_CCBV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV3) >> TCC_STATUS_CCBV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + return ((Tcc *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_D21_H_INCLUDED */ +#endif /* _SAMD21_TCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_usb_d21.h b/atmel-samd/asf4/samd21/hri/hri_usb_d21.h new file mode 100644 index 0000000000000..f0aa01f37e208 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_usb_d21.h @@ -0,0 +1,9811 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_USB_COMPONENT_ +#ifndef _HRI_USB_D21_H_INCLUDED_ +#define _HRI_USB_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_descriptor_extreg_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbdevice_padcal_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_descriptor_ctrl_pipe_reg_t; +typedef uint16_t hri_usbhost_descriptor_extreg_reg_t; +typedef uint16_t hri_usbhost_descriptor_status_pipe_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_padcal_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdevice_descadd_reg_t; +typedef uint32_t hri_usbdevice_descriptor_addr_reg_t; +typedef uint32_t hri_usbdevice_descriptor_pcksize_reg_t; +typedef uint32_t hri_usbhost_descadd_reg_t; +typedef uint32_t hri_usbhost_descriptor_addr_reg_t; +typedef uint32_t hri_usbhost_descriptor_pcksize_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdevice_ctrla_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_descriptor_status_bk_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_fsmstatus_reg_t; +typedef uint8_t hri_usbdevice_qosctrl_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbdevice_syncbusy_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_ctrla_reg_t; +typedef uint8_t hri_usbhost_descriptor_status_bk_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_fsmstatus_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_qosctrl_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbhost_syncbusy_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usbdevice_wait_for_sync(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usbdevice_is_syncing(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline void hri_usbhost_wait_for_sync(const void *const hw, hri_usbhost_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->HOST.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usbhost_is_syncing(const void *const hw, hri_usbhost_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg & reg; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrla_reg_t hri_usbhost_get_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrla_reg_t hri_usbhost_read_CTRLA_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usbhost_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_CQOS_bf(const void *const hw, + hri_usbhost_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_DQOS_bf(const void *const hw, + hri_usbhost_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_set_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_reg(const void *const hw, + hri_usbhost_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usbhost_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_DESCADD_bf(const void *const hw, + hri_usbhost_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbhost_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbhost_set_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_reg(const void *const hw, + hri_usbhost_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usbhost_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSP_bf(const void *const hw, + hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSN_bf(const void *const hw, + hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRIM_bf(const void *const hw, + hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline bool hri_usbhost_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usbhost_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usbhost_syncbusy_reg_t hri_usbhost_get_SYNCBUSY_reg(const void *const hw, + hri_usbhost_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_syncbusy_reg_t hri_usbhost_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usbhost_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_reg(const void *const hw, + hri_usbhost_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_get_CTRLA_reg(const void *const hw, + hri_usbdevice_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_read_CTRLA_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLA.reg; +} + +static inline void hri_usbdevice_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_CQOS_bf(const void *const hw, + hri_usbdevice_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_DQOS_bf(const void *const hw, + hri_usbdevice_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_reg(const void *const hw, + hri_usbdevice_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbdevice_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_DESCADD_bf(const void *const hw, + hri_usbdevice_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->DEVICE.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_reg(const void *const hw, + hri_usbdevice_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DESCADD.reg; +} + +static inline void hri_usbdevice_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSP_bf(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSN_bf(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRIM_bf(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_reg(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.PADCAL.reg; +} + +static inline bool hri_usbdevice_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usbdevice_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_get_SYNCBUSY_reg(const void *const hw, + hri_usbdevice_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usbdevice_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_reg(const void *const hw, + hri_usbdevice_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_D21_H_INCLUDED */ +#endif /* _SAMD21_USB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h b/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h new file mode 100644 index 0000000000000..90c307ba659c0 --- /dev/null +++ b/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h @@ -0,0 +1,616 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD21_WDT_COMPONENT_ +#ifndef _HRI_WDT_D21_H_INCLUDED_ +#define _HRI_WDT_D21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrl_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; +typedef uint8_t hri_wdt_status_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw) +{ + while (((const Wdt *)hw)->STATUS.bit.SYNCBUSY) + ; +} + +static inline bool hri_wdt_is_syncing(const void *const hw) +{ + return ((const Wdt *)hw)->STATUS.bit.SYNCBUSY; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRL_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg |= WDT_CTRL_ENABLE; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CTRL.reg; + tmp = (tmp & WDT_CTRL_ENABLE) >> WDT_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CTRL.reg; + tmp &= ~WDT_CTRL_ENABLE; + tmp |= value << WDT_CTRL_ENABLE_Pos; + ((Wdt *)hw)->CTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRL_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_ENABLE; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_ENABLE; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRL_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg |= WDT_CTRL_WEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRL_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CTRL.reg; + tmp = (tmp & WDT_CTRL_WEN) >> WDT_CTRL_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRL_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CTRL.reg; + tmp &= ~WDT_CTRL_WEN; + tmp |= value << WDT_CTRL_WEN_Pos; + ((Wdt *)hw)->CTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRL_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_WEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRL_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_WEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRL_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg |= WDT_CTRL_ALWAYSON; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRL_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CTRL.reg; + tmp = (tmp & WDT_CTRL_ALWAYSON) >> WDT_CTRL_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRL_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CTRL.reg; + tmp &= ~WDT_CTRL_ALWAYSON; + tmp |= value << WDT_CTRL_ALWAYSON_Pos; + ((Wdt *)hw)->CTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRL_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_ALWAYSON; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRL_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_ALWAYSON; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrl_reg_t hri_wdt_get_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrl_reg_t hri_wdt_read_CTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->CTRL.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline bool hri_wdt_get_STATUS_SYNCBUSY_bit(const void *const hw) +{ + return (((Wdt *)hw)->STATUS.reg & WDT_STATUS_SYNCBUSY) >> WDT_STATUS_SYNCBUSY_Pos; +} + +static inline hri_wdt_status_reg_t hri_wdt_get_STATUS_reg(const void *const hw, hri_wdt_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_status_reg_t hri_wdt_read_STATUS_reg(const void *const hw) +{ + return ((Wdt *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_D21_H_INCLUDED */ +#endif /* _SAMD21_WDT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component-version.h b/atmel-samd/asf4/samd21/include/component-version.h new file mode 100644 index 0000000000000..dcf909bae290d --- /dev/null +++ b/atmel-samd/asf4/samd21/include/component-version.h @@ -0,0 +1,65 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 2 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION +// is at least 8 digits long. +// +#define COMPONENT_VERSION 00010002 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 276 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.2" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2017-02-07 19:08:26" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/atmel-samd/asf4/samd21/include/component/ac.h b/atmel-samd/asf4/samd21/include/component/ac.h new file mode 100644 index 0000000000000..80ea1abe1f133 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/component/ac.h @@ -0,0 +1,544 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_AC_COMPONENT_ +#define _SAMD21_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_AC Analog Comparators */ +/*@{*/ + +#define AC_U2205 +#define REV_AC 0x111 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ +#define AC_CTRLA_RUNSTDBY_Msk (_U(0x1) << AC_CTRLA_RUNSTDBY_Pos) +#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) +#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ +#define AC_CTRLA_LPMUX (_U(0x1) << AC_CTRLA_LPMUX_Pos) +#define AC_CTRLA_MASK _U(0x87) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ +#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ +#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ +#define AC_EVCTRL_COMPEI_Msk (_U(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_MASK _U(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ +#define AC_STATUSB_SYNCBUSY (_U(0x1) << AC_STATUSB_SYNCBUSY_Pos) +#define AC_STATUSB_MASK _U(0x83) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ +#define AC_STATUSC_RESETVALUE _U(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ + +#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ +#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) +#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ +#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) +#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ +#define AC_STATUSC_STATE_Msk (_U(0x3) << AC_STATUSC_STATE_Pos) +#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) +#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ +#define AC_STATUSC_WSTATE0_Msk (_U(0x3) << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) +#define AC_STATUSC_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSC) Signal is above window */ +#define AC_STATUSC_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ +#define AC_STATUSC_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSC) Signal is below window */ +#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_MASK _U(0x33) /**< \brief (AC_STATUSC) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ENABLE:1; /*!< bit: 0 Enable */ + uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ + uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 14 Reserved */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t OUT:2; /*!< bit: 16..17 Output */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val _U(0x0) /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _U(0x1) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U(0x3) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYST (_U(0x1) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_MASK _U(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ + __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ + RoReg8 Reserved2[0x1]; + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ + RoReg8 Reserved3[0x3]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved4[0x8]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component/adc.h b/atmel-samd/asf4/samd21/include/component/adc.h new file mode 100644 index 0000000000000..fe415212509e9 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/component/adc.h @@ -0,0 +1,684 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_ADC_COMPONENT_ +#define _SAMD21_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2204 +#define REV_ADC 0x120 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_MASK _U(0x07) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INT1V_Val _U(0x0) /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U(0x1) /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U(0x3) /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U(0x4) /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_MASK _U(0x3F) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ +#define ADC_CTRLB_DIFFMODE (_U(0x1) << ADC_CTRLB_DIFFMODE_Pos) +#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ +#define ADC_CTRLB_CORREN (_U(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (_U(0x7) << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV4_Val _U(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _U(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _U(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _U(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _U(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _U(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _U(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV512_Val _U(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK _U(0x073F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ +#define ADC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ + +#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ +#define ADC_WINCTRL_WINMODE_Msk (_U(0x7) << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) +#define ADC_WINCTRL_WINMODE_DISABLE_Val _U(0x0) /**< \brief (ADC_WINCTRL) No window mode (default) */ +#define ADC_WINCTRL_WINMODE_MODE1_Val _U(0x1) /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ +#define ADC_WINCTRL_WINMODE_MODE2_Val _U(0x2) /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE3_Val _U(0x3) /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE4_Val _U(0x4) /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ +#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_MASK _U(0x07) /**< \brief (ADC_WINCTRL) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ +#define ADC_SWTRIG_START (_U(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ + uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ + uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN8_Val _U(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN9_Val _U(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN10_Val _U(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN11_Val _U(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN12_Val _U(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN13_Val _U(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN14_Val _U(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN15_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN16_Val _U(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN17_Val _U(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN18_Val _U(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN19_Val _U(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Reference */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_IOGND_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) I/O Ground */ +#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ +#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos) +#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) +#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ +#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos) +#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) +#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ +#define ADC_INPUTCTRL_GAIN_Msk (_U(0xF) << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) +#define ADC_INPUTCTRL_GAIN_1X_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) 1x */ +#define ADC_INPUTCTRL_GAIN_2X_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) 2x */ +#define ADC_INPUTCTRL_GAIN_4X_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) 4x */ +#define ADC_INPUTCTRL_GAIN_8X_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) 8x */ +#define ADC_INPUTCTRL_GAIN_16X_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) 16x */ +#define ADC_INPUTCTRL_GAIN_DIV2_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) 1/2x */ +#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_MASK _U(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ + uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ +#define ADC_EVCTRL_STARTEI (_U(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ +#define ADC_EVCTRL_SYNCEI (_U(0x1) << ADC_EVCTRL_SYNCEI_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U(0x33) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ +#define ADC_INTENCLR_RESRDY (_U(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ +#define ADC_INTENCLR_OVERRUN (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ +#define ADC_INTENCLR_WINMON (_U(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define ADC_INTENCLR_SYNCRDY (_U(0x1) << ADC_INTENCLR_SYNCRDY_Pos) +#define ADC_INTENCLR_MASK _U(0x0F) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ +#define ADC_INTENSET_SYNCRDY (_U(0x1) << ADC_INTENSET_SYNCRDY_Pos) +#define ADC_INTENSET_MASK _U(0x0F) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ + __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ +#define ADC_INTFLAG_RESRDY (_U(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ +#define ADC_INTFLAG_OVERRUN (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ +#define ADC_INTFLAG_WINMON (_U(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ +#define ADC_INTFLAG_SYNCRDY (_U(0x1) << ADC_INTFLAG_SYNCRDY_Pos) +#define ADC_INTFLAG_MASK _U(0x0F) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ +#define ADC_STATUS_SYNCBUSY (_U(0x1) << ADC_STATUS_SYNCBUSY_Pos) +#define ADC_STATUS_MASK _U(0x80) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE _U(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ + uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ +#define ADC_CALIB_LINEARITY_CAL_Msk (_U(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos) +#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) +#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ +#define ADC_CALIB_BIAS_CAL_Msk (_U(0x7) << ADC_CALIB_BIAS_CAL_Pos) +#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) +#define ADC_CALIB_MASK _U(0x07FF) /**< \brief (ADC_CALIB) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ + RoReg8 Reserved1[0x2]; + __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ + RoReg8 Reserved2[0x3]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ + RoReg8 Reserved3[0x3]; + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ + RoReg8 Reserved4[0x1]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ + RoReg8 Reserved5[0x2]; + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ + RoReg8 Reserved6[0x2]; + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component/dac.h b/atmel-samd/asf4/samd21/include/component/dac.h new file mode 100644 index 0000000000000..ba84975eafa64 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/component/dac.h @@ -0,0 +1,271 @@ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DAC_COMPONENT_ +#define _SAMD21_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_DAC Digital Analog Converter */ +/*@{*/ + +#define DAC_U2214 +#define REV_DAC 0x110 + +/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ +#define DAC_CTRLA_ENABLE (_U(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ +#define DAC_CTRLA_RUNSTDBY (_U(0x1) << DAC_CTRLA_RUNSTDBY_Pos) +#define DAC_CTRLA_MASK _U(0x07) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ + uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ + uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ + uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ + uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ +#define DAC_CTRLB_EOEN (_U(0x1) << DAC_CTRLB_EOEN_Pos) +#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ +#define DAC_CTRLB_IOEN (_U(0x1) << DAC_CTRLB_IOEN_Pos) +#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ +#define DAC_CTRLB_LEFTADJ (_U(0x1) << DAC_CTRLB_LEFTADJ_Pos) +#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ +#define DAC_CTRLB_VPD (_U(0x1) << DAC_CTRLB_VPD_Pos) +#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ +#define DAC_CTRLB_BDWP (_U(0x1) << DAC_CTRLB_BDWP_Pos) +#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ +#define DAC_CTRLB_REFSEL_Msk (_U(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_INT1V_Val _U(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val _U(0x1) /**< \brief (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val _U(0x2) /**< \brief (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U(0xDF) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ + uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ +#define DAC_EVCTRL_STARTEI (_U(0x1) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ +#define DAC_EVCTRL_EMPTYEO (_U(0x1) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_MASK _U(0x03) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN (_U(0x1) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY (_U(0x1) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define DAC_INTENCLR_SYNCRDY (_U(0x1) << DAC_INTENCLR_SYNCRDY_Pos) +#define DAC_INTENCLR_MASK _U(0x07) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN (_U(0x1) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY (_U(0x1) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ +#define DAC_INTENSET_SYNCRDY (_U(0x1) << DAC_INTENSET_SYNCRDY_Pos) +#define DAC_INTENSET_MASK _U(0x07) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ + __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ + __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ +#define DAC_INTFLAG_UNDERRUN (_U(0x1) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ +#define DAC_INTFLAG_EMPTY (_U(0x1) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ +#define DAC_INTFLAG_SYNCRDY (_U(0x1) << DAC_INTFLAG_SYNCRDY_Pos) +#define DAC_INTFLAG_MASK _U(0x07) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ +#define DAC_STATUS_SYNCBUSY (_U(0x1) << DAC_STATUS_SYNCBUSY_Pos) +#define DAC_STATUS_MASK _U(0x80) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ +#define DAC_DATA_RESETVALUE _U(0x0000) /**< \brief (DAC_DATA reset_value) Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ +#define DAC_DATA_DATA_Msk (_U(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ + RoReg8 Reserved2[0x2]; + __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component/dmac.h b/atmel-samd/asf4/samd21/include/component/dmac.h new file mode 100644 index 0000000000000..1d7c8c0eaece3 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/component/dmac.h @@ -0,0 +1,1072 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DMAC_COMPONENT_ +#define _SAMD21_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2223 +#define REV_DMAC 0x100 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (_U(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ +#define DMAC_CTRL_CRCENABLE (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (_U(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK _U(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) No action */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_MASK _U(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_MASK _U(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _U(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_QOSCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ +#define DMAC_QOSCTRL_RESETVALUE _U(0x15) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ + +#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ +#define DMAC_QOSCTRL_WRBQOS_Msk (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) +#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ +#define DMAC_QOSCTRL_FQOS_Msk (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) +#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_FQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_FQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ +#define DMAC_QOSCTRL_DQOS_Msk (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) +#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_DQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_DQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_MASK _U(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK _U(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _U(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (_U(0xF) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (_U(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (_U(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (_U(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (_U(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (_U(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (_U(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _U(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (_U(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK _U(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (_U(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK _U(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (_U(0xFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK _U(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (_U(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ +#define DMAC_CHID_RESETVALUE _U(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ + +#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ +#define DMAC_CHID_ID_Msk (_U(0xF) << DMAC_CHID_ID_Pos) +#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) +#define DMAC_CHID_MASK _U(0x0F) /**< \brief (DMAC_CHID) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ +#define DMAC_CHCTRLA_RESETVALUE _U(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_MASK _U(0x03) /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ +#define DMAC_CHCTRLB_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ + +#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ +#define DMAC_CHCTRLB_EVACT_Msk (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) +#define DMAC_CHCTRLB_EVACT_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_EVACT_TRIG_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ +#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_EVACT_RESUME_Val _U(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ +#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ +#define DMAC_CHCTRLB_EVIE (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos) +#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ +#define DMAC_CHCTRLB_EVOE (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos) +#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ +#define DMAC_CHCTRLB_LVL_Msk (_U(0x3) << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) +#define DMAC_CHCTRLB_LVL_LVL0_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ +#define DMAC_CHCTRLB_LVL_LVL1_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ +#define DMAC_CHCTRLB_LVL_LVL2_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ +#define DMAC_CHCTRLB_LVL_LVL3_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ +#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ +#define DMAC_CHCTRLB_TRIGSRC_Msk (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ +#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ +#define DMAC_CHCTRLB_TRIGACT_Msk (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) +#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ +#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ +#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (_U(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _U(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (_U(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _U(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _U(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ +#define DMAC_CHSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (_U(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (_U(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_MASK _U(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (_U(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030D) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E15A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21e16a.h b/atmel-samd/asf4/samd21/include/samd21e16a.h new file mode 100644 index 0000000000000..7bb07c660bd88 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21e16a.h @@ -0,0 +1,552 @@ +/** + * \file + * + * \brief Header file for SAMD21E16A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E16A_ +#define _SAMD21E16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions + * This file defines all structures and symbols for SAMD21E16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030C) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E16A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21e17a.h b/atmel-samd/asf4/samd21/include/samd21e17a.h new file mode 100644 index 0000000000000..df037351ac653 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21e17a.h @@ -0,0 +1,552 @@ +/** + * \file + * + * \brief Header file for SAMD21E17A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E17A_ +#define _SAMD21E17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions + * This file defines all structures and symbols for SAMD21E17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030B) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E17A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21e18a.h b/atmel-samd/asf4/samd21/include/samd21e18a.h new file mode 100644 index 0000000000000..3b7a5c7a4b862 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21e18a.h @@ -0,0 +1,552 @@ +/** + * \file + * + * \brief Header file for SAMD21E18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E18A_ +#define _SAMD21E18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions + * This file defines all structures and symbols for SAMD21E18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +// #define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030A) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E18A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g15a.h b/atmel-samd/asf4/samd21/include/samd21g15a.h new file mode 100644 index 0000000000000..5131ac4c9219f --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21g15a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G15A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G15A_ +#define _SAMD21G15A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions + * This file defines all structures and symbols for SAMD21G15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010308) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G15A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g16a.h b/atmel-samd/asf4/samd21/include/samd21g16a.h new file mode 100644 index 0000000000000..102128025a730 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21g16a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G16A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G16A_ +#define _SAMD21G16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions + * This file defines all structures and symbols for SAMD21G16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010307) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G16A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g17a.h b/atmel-samd/asf4/samd21/include/samd21g17a.h new file mode 100644 index 0000000000000..dc3b161284b41 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21g17a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G17A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G17A_ +#define _SAMD21G17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions + * This file defines all structures and symbols for SAMD21G17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010306) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G17A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g17au.h b/atmel-samd/asf4/samd21/include/samd21g17au.h new file mode 100644 index 0000000000000..46225b3bfdd82 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21g17au.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21G17AU + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G17AU_ +#define _SAMD21G17AU_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions + * This file defines all structures and symbols for SAMD21G17AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g17au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010310) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G17AU_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g18a.h b/atmel-samd/asf4/samd21/include/samd21g18a.h new file mode 100644 index 0000000000000..37480349a7cfa --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21g18a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G18A_ +#define _SAMD21G18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions + * This file defines all structures and symbols for SAMD21G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010305) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G18A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g18au.h b/atmel-samd/asf4/samd21/include/samd21g18au.h new file mode 100644 index 0000000000000..82c2532b606b2 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21g18au.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21G18AU + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G18AU_ +#define _SAMD21G18AU_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions + * This file defines all structures and symbols for SAMD21G18AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g18au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030F) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G18AU_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j15a.h b/atmel-samd/asf4/samd21/include/samd21j15a.h new file mode 100644 index 0000000000000..80aba23ec0e58 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21j15a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J15A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J15A_ +#define _SAMD21J15A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions + * This file defines all structures and symbols for SAMD21J15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010303) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J15A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j16a.h b/atmel-samd/asf4/samd21/include/samd21j16a.h new file mode 100644 index 0000000000000..b054d7ed86d0a --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21j16a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J16A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J16A_ +#define _SAMD21J16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions + * This file defines all structures and symbols for SAMD21J16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010302) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J16A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j17a.h b/atmel-samd/asf4/samd21/include/samd21j17a.h new file mode 100644 index 0000000000000..bc85d9304e18f --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21j17a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J17A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J17A_ +#define _SAMD21J17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions + * This file defines all structures and symbols for SAMD21J17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010301) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J17A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j18a.h b/atmel-samd/asf4/samd21/include/samd21j18a.h new file mode 100644 index 0000000000000..ee9a8fa1e648e --- /dev/null +++ b/atmel-samd/asf4/samd21/include/samd21j18a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J18A_ +#define _SAMD21J18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions + * This file defines all structures and symbols for SAMD21J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010300) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J18A_H */ diff --git a/atmel-samd/asf4/samd21/include/system_samd21.h b/atmel-samd/asf4/samd21/include/system_samd21.h new file mode 100644 index 0000000000000..223911ce69ca6 --- /dev/null +++ b/atmel-samd/asf4/samd21/include/system_samd21.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAMD21_H_INCLUDED_ +#define _SYSTEM_SAMD21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAMD21_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/main.c b/atmel-samd/asf4/samd21/main.c new file mode 100644 index 0000000000000..4652da488fb76 --- /dev/null +++ b/atmel-samd/asf4/samd21/main.c @@ -0,0 +1,11 @@ +#include + +int main(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + + /* Replace with your application code */ + while (1) { + } +} diff --git a/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s b/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s new file mode 100644 index 0000000000000..96ef2cdbbd596 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s @@ -0,0 +1,247 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.01 +; * @date 25. March 2015 +; * +; * @note +; * Copyright (C) 2014 - 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface + DCD AC1_Handler ; 28 Analog Comparators 1 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT AC1_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler +AC1_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c b/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c new file mode 100644 index 0000000000000..a4123b4e6b1fe --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "samd21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (1000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld new file mode 100644 index 0000000000000..2c94a53bafe4e --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_flash.ld @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD21G18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_sram.ld b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_sram.ld new file mode 100644 index 0000000000000..f0462a22da82d --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/samd21g18a_sram.ld @@ -0,0 +1,141 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD21G18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/gcc/startup_samd21.c b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/startup_samd21.c new file mode 100644 index 0000000000000..b159549c83b4c --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/gcc/gcc/startup_samd21.c @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief gcc starttup file for SAMD21 + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd21.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M0+ core handlers */ +void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SYSCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void EIC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void NVMCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_USB +void USB_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void EVSYS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_SERCOM4 +void SERCOM4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SERCOM5 +void SERCOM5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void TCC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TCC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TCC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_TC6 +void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_ADC +void ADC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_AC +void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_DAC +void DAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PTC +void PTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Exception Table */ +__attribute__((section(".vectors"))) const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void *)(&_estack), + + .pfnReset_Handler = (void *)Reset_Handler, + .pfnNMI_Handler = (void *)NMI_Handler, + .pfnHardFault_Handler = (void *)HardFault_Handler, + .pvReservedM12 = (void *)(0UL), /* Reserved */ + .pvReservedM11 = (void *)(0UL), /* Reserved */ + .pvReservedM10 = (void *)(0UL), /* Reserved */ + .pvReservedM9 = (void *)(0UL), /* Reserved */ + .pvReservedM8 = (void *)(0UL), /* Reserved */ + .pvReservedM7 = (void *)(0UL), /* Reserved */ + .pvReservedM6 = (void *)(0UL), /* Reserved */ + .pfnSVC_Handler = (void *)SVC_Handler, + .pvReservedM4 = (void *)(0UL), /* Reserved */ + .pvReservedM3 = (void *)(0UL), /* Reserved */ + .pfnPendSV_Handler = (void *)PendSV_Handler, + .pfnSysTick_Handler = (void *)SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ + .pfnSYSCTRL_Handler = (void *)SYSCTRL_Handler, /* 1 System Control */ + .pfnWDT_Handler = (void *)WDT_Handler, /* 2 Watchdog Timer */ + .pfnRTC_Handler = (void *)RTC_Handler, /* 3 Real-Time Counter */ + .pfnEIC_Handler = (void *)EIC_Handler, /* 4 External Interrupt Controller */ + .pfnNVMCTRL_Handler = (void *)NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ + .pfnDMAC_Handler = (void *)DMAC_Handler, /* 6 Direct Memory Access Controller */ +#ifdef ID_USB + .pfnUSB_Handler = (void *)USB_Handler, /* 7 Universal Serial Bus */ +#else + .pvReserved7 = (void *)(0UL), /* 7 Reserved */ +#endif + .pfnEVSYS_Handler = (void *)EVSYS_Handler, /* 8 Event System Interface */ + .pfnSERCOM0_Handler = (void *)SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ + .pfnSERCOM1_Handler = (void *)SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ + .pfnSERCOM2_Handler = (void *)SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ + .pfnSERCOM3_Handler = (void *)SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_Handler = (void *)SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ +#else + .pvReserved13 = (void *)(0UL), /* 13 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_Handler = (void *)SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ +#else + .pvReserved14 = (void *)(0UL), /* 14 Reserved */ +#endif + .pfnTCC0_Handler = (void *)TCC0_Handler, /* 15 Timer Counter Control 0 */ + .pfnTCC1_Handler = (void *)TCC1_Handler, /* 16 Timer Counter Control 1 */ + .pfnTCC2_Handler = (void *)TCC2_Handler, /* 17 Timer Counter Control 2 */ + .pfnTC3_Handler = (void *)TC3_Handler, /* 18 Basic Timer Counter 0 */ + .pfnTC4_Handler = (void *)TC4_Handler, /* 19 Basic Timer Counter 1 */ + .pfnTC5_Handler = (void *)TC5_Handler, /* 20 Basic Timer Counter 2 */ +#ifdef ID_TC6 + .pfnTC6_Handler = (void *)TC6_Handler, /* 21 Basic Timer Counter 3 */ +#else + .pvReserved21 = (void *)(0UL), /* 21 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void *)TC7_Handler, /* 22 Basic Timer Counter 4 */ +#else + .pvReserved22 = (void *)(0UL), /* 22 Reserved */ +#endif +#ifdef ID_ADC + .pfnADC_Handler = (void *)ADC_Handler, /* 23 Analog Digital Converter */ +#else + .pvReserved23 = (void *)(0UL), /* 23 Reserved */ +#endif +#ifdef ID_AC + .pfnAC_Handler = (void *)AC_Handler, /* 24 Analog Comparators */ +#else + .pvReserved24 = (void *)(0UL), /* 24 Reserved */ +#endif +#ifdef ID_DAC + .pfnDAC_Handler = (void *)DAC_Handler, /* 25 Digital Analog Converter */ +#else + .pvReserved25 = (void *)(0UL), /* 25 Reserved */ +#endif +#ifdef ID_PTC + .pfnPTC_Handler = (void *)PTC_Handler, /* 26 Peripheral Touch Controller */ +#else + .pvReserved26 = (void *)(0UL), /* 26 Reserved */ +#endif + .pfnI2S_Handler = (void *)I2S_Handler, /* 27 Inter-IC Sound Interface */ + .pvReserved28 = (void *)(0UL) /* 28 Reserved */ +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *)&_sfixed; + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + + /* Change default QOS values to have the best performance and correct USB behaviour */ + SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; +#if defined(ID_USB) + USB->DEVICE.QOSCTRL.bit.CQOS = 2; + USB->DEVICE.QOSCTRL.bit.DQOS = 2; +#endif + DMAC->QOSCTRL.bit.DQOS = 2; + DMAC->QOSCTRL.bit.FQOS = 2; + DMAC->QOSCTRL.bit.WRBQOS = 2; + + /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ + NVMCTRL->CTRLB.bit.MANW = 1; + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1) + ; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/atmel-samd/asf4/samd21/samd21a/gcc/system_samd21.c b/atmel-samd/asf4/samd21/samd21a/gcc/system_samd21.c new file mode 100644 index 0000000000000..274ecccb83ef6 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/gcc/system_samd21.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (1000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/atmel-samd/asf4/samd21/samd21a/include/component-version.h b/atmel-samd/asf4/samd21/samd21a/include/component-version.h new file mode 100644 index 0000000000000..dcf909bae290d --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/component-version.h @@ -0,0 +1,65 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 2 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION +// is at least 8 digits long. +// +#define COMPONENT_VERSION 00010002 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 276 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.2" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2017-02-07 19:08:26" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/ac.h b/atmel-samd/asf4/samd21/samd21a/include/component/ac.h new file mode 100644 index 0000000000000..80ea1abe1f133 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/component/ac.h @@ -0,0 +1,544 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_AC_COMPONENT_ +#define _SAMD21_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_AC Analog Comparators */ +/*@{*/ + +#define AC_U2205 +#define REV_AC 0x111 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ +#define AC_CTRLA_RUNSTDBY_Msk (_U(0x1) << AC_CTRLA_RUNSTDBY_Pos) +#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) +#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ +#define AC_CTRLA_LPMUX (_U(0x1) << AC_CTRLA_LPMUX_Pos) +#define AC_CTRLA_MASK _U(0x87) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ +#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ +#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ +#define AC_EVCTRL_COMPEI_Msk (_U(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_MASK _U(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ +#define AC_STATUSB_SYNCBUSY (_U(0x1) << AC_STATUSB_SYNCBUSY_Pos) +#define AC_STATUSB_MASK _U(0x83) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ +#define AC_STATUSC_RESETVALUE _U(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ + +#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ +#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) +#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ +#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) +#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ +#define AC_STATUSC_STATE_Msk (_U(0x3) << AC_STATUSC_STATE_Pos) +#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) +#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ +#define AC_STATUSC_WSTATE0_Msk (_U(0x3) << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) +#define AC_STATUSC_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSC) Signal is above window */ +#define AC_STATUSC_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ +#define AC_STATUSC_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSC) Signal is below window */ +#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_MASK _U(0x33) /**< \brief (AC_STATUSC) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ENABLE:1; /*!< bit: 0 Enable */ + uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ + uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 14 Reserved */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t OUT:2; /*!< bit: 16..17 Output */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val _U(0x0) /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _U(0x1) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U(0x3) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYST (_U(0x1) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_MASK _U(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ + __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ + RoReg8 Reserved2[0x1]; + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ + RoReg8 Reserved3[0x3]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved4[0x8]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/adc.h b/atmel-samd/asf4/samd21/samd21a/include/component/adc.h new file mode 100644 index 0000000000000..fe415212509e9 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/component/adc.h @@ -0,0 +1,684 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_ADC_COMPONENT_ +#define _SAMD21_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2204 +#define REV_ADC 0x120 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_MASK _U(0x07) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INT1V_Val _U(0x0) /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U(0x1) /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U(0x3) /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U(0x4) /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_MASK _U(0x3F) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ +#define ADC_CTRLB_DIFFMODE (_U(0x1) << ADC_CTRLB_DIFFMODE_Pos) +#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ +#define ADC_CTRLB_CORREN (_U(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (_U(0x7) << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV4_Val _U(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _U(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _U(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _U(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _U(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _U(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _U(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV512_Val _U(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK _U(0x073F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ +#define ADC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ + +#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ +#define ADC_WINCTRL_WINMODE_Msk (_U(0x7) << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) +#define ADC_WINCTRL_WINMODE_DISABLE_Val _U(0x0) /**< \brief (ADC_WINCTRL) No window mode (default) */ +#define ADC_WINCTRL_WINMODE_MODE1_Val _U(0x1) /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ +#define ADC_WINCTRL_WINMODE_MODE2_Val _U(0x2) /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE3_Val _U(0x3) /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE4_Val _U(0x4) /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ +#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_MASK _U(0x07) /**< \brief (ADC_WINCTRL) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ +#define ADC_SWTRIG_START (_U(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ + uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ + uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN8_Val _U(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN9_Val _U(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN10_Val _U(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN11_Val _U(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN12_Val _U(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN13_Val _U(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN14_Val _U(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN15_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN16_Val _U(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN17_Val _U(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN18_Val _U(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN19_Val _U(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Reference */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_IOGND_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) I/O Ground */ +#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ +#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos) +#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) +#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ +#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos) +#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) +#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ +#define ADC_INPUTCTRL_GAIN_Msk (_U(0xF) << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) +#define ADC_INPUTCTRL_GAIN_1X_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) 1x */ +#define ADC_INPUTCTRL_GAIN_2X_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) 2x */ +#define ADC_INPUTCTRL_GAIN_4X_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) 4x */ +#define ADC_INPUTCTRL_GAIN_8X_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) 8x */ +#define ADC_INPUTCTRL_GAIN_16X_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) 16x */ +#define ADC_INPUTCTRL_GAIN_DIV2_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) 1/2x */ +#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_MASK _U(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ + uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ +#define ADC_EVCTRL_STARTEI (_U(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ +#define ADC_EVCTRL_SYNCEI (_U(0x1) << ADC_EVCTRL_SYNCEI_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U(0x33) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ +#define ADC_INTENCLR_RESRDY (_U(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ +#define ADC_INTENCLR_OVERRUN (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ +#define ADC_INTENCLR_WINMON (_U(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define ADC_INTENCLR_SYNCRDY (_U(0x1) << ADC_INTENCLR_SYNCRDY_Pos) +#define ADC_INTENCLR_MASK _U(0x0F) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ +#define ADC_INTENSET_SYNCRDY (_U(0x1) << ADC_INTENSET_SYNCRDY_Pos) +#define ADC_INTENSET_MASK _U(0x0F) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ + __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ +#define ADC_INTFLAG_RESRDY (_U(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ +#define ADC_INTFLAG_OVERRUN (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ +#define ADC_INTFLAG_WINMON (_U(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ +#define ADC_INTFLAG_SYNCRDY (_U(0x1) << ADC_INTFLAG_SYNCRDY_Pos) +#define ADC_INTFLAG_MASK _U(0x0F) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ +#define ADC_STATUS_SYNCBUSY (_U(0x1) << ADC_STATUS_SYNCBUSY_Pos) +#define ADC_STATUS_MASK _U(0x80) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE _U(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ + uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ +#define ADC_CALIB_LINEARITY_CAL_Msk (_U(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos) +#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) +#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ +#define ADC_CALIB_BIAS_CAL_Msk (_U(0x7) << ADC_CALIB_BIAS_CAL_Pos) +#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) +#define ADC_CALIB_MASK _U(0x07FF) /**< \brief (ADC_CALIB) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ + RoReg8 Reserved1[0x2]; + __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ + RoReg8 Reserved2[0x3]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ + RoReg8 Reserved3[0x3]; + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ + RoReg8 Reserved4[0x1]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ + RoReg8 Reserved5[0x2]; + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ + RoReg8 Reserved6[0x2]; + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/dac.h b/atmel-samd/asf4/samd21/samd21a/include/component/dac.h new file mode 100644 index 0000000000000..ba84975eafa64 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/component/dac.h @@ -0,0 +1,271 @@ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DAC_COMPONENT_ +#define _SAMD21_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_DAC Digital Analog Converter */ +/*@{*/ + +#define DAC_U2214 +#define REV_DAC 0x110 + +/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ +#define DAC_CTRLA_ENABLE (_U(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ +#define DAC_CTRLA_RUNSTDBY (_U(0x1) << DAC_CTRLA_RUNSTDBY_Pos) +#define DAC_CTRLA_MASK _U(0x07) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ + uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ + uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ + uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ + uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ +#define DAC_CTRLB_EOEN (_U(0x1) << DAC_CTRLB_EOEN_Pos) +#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ +#define DAC_CTRLB_IOEN (_U(0x1) << DAC_CTRLB_IOEN_Pos) +#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ +#define DAC_CTRLB_LEFTADJ (_U(0x1) << DAC_CTRLB_LEFTADJ_Pos) +#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ +#define DAC_CTRLB_VPD (_U(0x1) << DAC_CTRLB_VPD_Pos) +#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ +#define DAC_CTRLB_BDWP (_U(0x1) << DAC_CTRLB_BDWP_Pos) +#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ +#define DAC_CTRLB_REFSEL_Msk (_U(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_INT1V_Val _U(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val _U(0x1) /**< \brief (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val _U(0x2) /**< \brief (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U(0xDF) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ + uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ +#define DAC_EVCTRL_STARTEI (_U(0x1) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ +#define DAC_EVCTRL_EMPTYEO (_U(0x1) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_MASK _U(0x03) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN (_U(0x1) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY (_U(0x1) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define DAC_INTENCLR_SYNCRDY (_U(0x1) << DAC_INTENCLR_SYNCRDY_Pos) +#define DAC_INTENCLR_MASK _U(0x07) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN (_U(0x1) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY (_U(0x1) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ +#define DAC_INTENSET_SYNCRDY (_U(0x1) << DAC_INTENSET_SYNCRDY_Pos) +#define DAC_INTENSET_MASK _U(0x07) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ + __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ + __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ +#define DAC_INTFLAG_UNDERRUN (_U(0x1) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ +#define DAC_INTFLAG_EMPTY (_U(0x1) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ +#define DAC_INTFLAG_SYNCRDY (_U(0x1) << DAC_INTFLAG_SYNCRDY_Pos) +#define DAC_INTFLAG_MASK _U(0x07) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ +#define DAC_STATUS_SYNCBUSY (_U(0x1) << DAC_STATUS_SYNCBUSY_Pos) +#define DAC_STATUS_MASK _U(0x80) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ +#define DAC_DATA_RESETVALUE _U(0x0000) /**< \brief (DAC_DATA reset_value) Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ +#define DAC_DATA_DATA_Msk (_U(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ + RoReg8 Reserved2[0x2]; + __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/component/dmac.h b/atmel-samd/asf4/samd21/samd21a/include/component/dmac.h new file mode 100644 index 0000000000000..1d7c8c0eaece3 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/component/dmac.h @@ -0,0 +1,1072 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DMAC_COMPONENT_ +#define _SAMD21_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2223 +#define REV_DMAC 0x100 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ + uint16_t :5; /*!< bit: 3.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (_U(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ +#define DMAC_CTRL_CRCENABLE (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (_U(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK _U(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) No action */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_MASK _U(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_MASK _U(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _U(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ + uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ + uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_QOSCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ +#define DMAC_QOSCTRL_RESETVALUE _U(0x15) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ + +#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ +#define DMAC_QOSCTRL_WRBQOS_Msk (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) +#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) +#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ +#define DMAC_QOSCTRL_FQOS_Msk (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) +#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_FQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_FQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) +#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ +#define DMAC_QOSCTRL_DQOS_Msk (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) +#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ +#define DMAC_QOSCTRL_DQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ +#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ +#define DMAC_QOSCTRL_DQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ +#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) +#define DMAC_QOSCTRL_MASK _U(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK _U(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ + uint32_t :3; /*!< bit: 4.. 6 Reserved */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ + uint32_t :3; /*!< bit: 12..14 Reserved */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ + uint32_t :3; /*!< bit: 20..22 Reserved */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ + uint32_t :3; /*!< bit: 28..30 Reserved */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :2; /*!< bit: 11..12 Reserved */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _U(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (_U(0xF) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (_U(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (_U(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (_U(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (_U(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (_U(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (_U(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _U(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (_U(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK _U(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (_U(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK _U(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (_U(0xFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK _U(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (_U(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHID_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ +#define DMAC_CHID_RESETVALUE _U(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ + +#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ +#define DMAC_CHID_ID_Msk (_U(0xF) << DMAC_CHID_ID_Pos) +#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) +#define DMAC_CHID_MASK _U(0x0F) /**< \brief (DMAC_CHID) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ +#define DMAC_CHCTRLA_RESETVALUE _U(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_MASK _U(0x03) /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ + uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ + uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ + uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ + uint32_t :8; /*!< bit: 14..21 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ + uint32_t CMD:2; /*!< bit: 24..25 Software Command */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ +#define DMAC_CHCTRLB_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ + +#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ +#define DMAC_CHCTRLB_EVACT_Msk (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) +#define DMAC_CHCTRLB_EVACT_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_EVACT_TRIG_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ +#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ +#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_EVACT_RESUME_Val _U(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ +#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) +#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ +#define DMAC_CHCTRLB_EVIE (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos) +#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ +#define DMAC_CHCTRLB_EVOE (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos) +#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ +#define DMAC_CHCTRLB_LVL_Msk (_U(0x3) << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) +#define DMAC_CHCTRLB_LVL_LVL0_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ +#define DMAC_CHCTRLB_LVL_LVL1_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ +#define DMAC_CHCTRLB_LVL_LVL2_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ +#define DMAC_CHCTRLB_LVL_LVL3_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ +#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) +#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ +#define DMAC_CHCTRLB_TRIGSRC_Msk (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) +#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ +#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) +#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ +#define DMAC_CHCTRLB_TRIGACT_Msk (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) +#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ +#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ +#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) +#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (_U(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _U(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (_U(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _U(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _U(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ +#define DMAC_CHSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (_U(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (_U(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_MASK _U(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (_U(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ +#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030D) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E15A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21e16a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21e16a.h new file mode 100644 index 0000000000000..7bb07c660bd88 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21e16a.h @@ -0,0 +1,552 @@ +/** + * \file + * + * \brief Header file for SAMD21E16A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E16A_ +#define _SAMD21E16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions + * This file defines all structures and symbols for SAMD21E16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030C) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E16A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21e17a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21e17a.h new file mode 100644 index 0000000000000..df037351ac653 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21e17a.h @@ -0,0 +1,552 @@ +/** + * \file + * + * \brief Header file for SAMD21E17A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E17A_ +#define _SAMD21E17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions + * This file defines all structures and symbols for SAMD21E17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030B) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E17A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21e18a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21e18a.h new file mode 100644 index 0000000000000..8e7bcb7f48866 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21e18a.h @@ -0,0 +1,552 @@ +/** + * \file + * + * \brief Header file for SAMD21E18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E18A_ +#define _SAMD21E18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions + * This file defines all structures and symbols for SAMD21E18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21E18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030A) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E18A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g15a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g15a.h new file mode 100644 index 0000000000000..5131ac4c9219f --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21g15a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G15A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G15A_ +#define _SAMD21G15A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions + * This file defines all structures and symbols for SAMD21G15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010308) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G15A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g16a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g16a.h new file mode 100644 index 0000000000000..102128025a730 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21g16a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G16A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G16A_ +#define _SAMD21G16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions + * This file defines all structures and symbols for SAMD21G16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010307) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G16A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g17a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g17a.h new file mode 100644 index 0000000000000..dc3b161284b41 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21g17a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G17A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G17A_ +#define _SAMD21G17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions + * This file defines all structures and symbols for SAMD21G17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010306) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G17A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g17au.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g17au.h new file mode 100644 index 0000000000000..46225b3bfdd82 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21g17au.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21G17AU + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G17AU_ +#define _SAMD21G17AU_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions + * This file defines all structures and symbols for SAMD21G17AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g17au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010310) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G17AU_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g18a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g18a.h new file mode 100644 index 0000000000000..2840b6e14b05f --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21g18a.h @@ -0,0 +1,564 @@ +/** + * \file + * + * \brief Header file for SAMD21G18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G18A_ +#define _SAMD21G18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions + * This file defines all structures and symbols for SAMD21G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010305) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G18A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21g18au.h b/atmel-samd/asf4/samd21/samd21a/include/samd21g18au.h new file mode 100644 index 0000000000000..82c2532b606b2 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21g18au.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21G18AU + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G18AU_ +#define _SAMD21G18AU_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions + * This file defines all structures and symbols for SAMD21G18AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g18au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x1001030F) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G18AU_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j15a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j15a.h new file mode 100644 index 0000000000000..80aba23ec0e58 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21j15a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J15A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J15A_ +#define _SAMD21J15A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions + * This file defines all structures and symbols for SAMD21J15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J15A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010303) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J15A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j16a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j16a.h new file mode 100644 index 0000000000000..b054d7ed86d0a --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21j16a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J16A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J16A_ +#define _SAMD21J16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions + * This file defines all structures and symbols for SAMD21J16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J16A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010302) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J16A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j17a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j17a.h new file mode 100644 index 0000000000000..bc85d9304e18f --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21j17a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J17A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J17A_ +#define _SAMD21J17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions + * This file defines all structures and symbols for SAMD21J17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J17A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010301) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J17A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/samd21j18a.h b/atmel-samd/asf4/samd21/samd21a/include/samd21j18a.h new file mode 100644 index 0000000000000..ee9a8fa1e648e --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/samd21j18a.h @@ -0,0 +1,576 @@ +/** + * \file + * + * \brief Header file for SAMD21J18A + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J18A_ +#define _SAMD21J18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions + * This file defines all structures and symbols for SAMD21J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#if !defined(_UL) +#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#endif +#else +#if !defined(_UL) +#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L(x) x /**< Assembler: Long integer literal constant value */ +#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif +#endif + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ + /****** SAMD21J18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void SVC_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define LITTLE_ENDIAN 1 +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL(0x10010300) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J18A_H */ diff --git a/atmel-samd/asf4/samd21/samd21a/include/system_samd21.h b/atmel-samd/asf4/samd21/samd21a/include/system_samd21.h new file mode 100644 index 0000000000000..223911ce69ca6 --- /dev/null +++ b/atmel-samd/asf4/samd21/samd21a/include/system_samd21.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAMD21_H_INCLUDED_ +#define _SYSTEM_SAMD21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAMD21_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.c b/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.c new file mode 100644 index 0000000000000..f0a8de446e4d1 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.c @@ -0,0 +1,389 @@ +/** + * \file + * + * \brief USB Device Stack CDC ACM Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "cdcdf_acm.h" + +#define CDCDF_ACM_VERSION 0x00000001u +#define CDCDF_ACM_COMM_EP_INDEX 0 +#define CDCDF_ACM_DATA_EP_INDEX 1 + +/** USB Device CDC ACM Fucntion Specific Data */ +struct cdcdf_acm_func_data { + /** CDC Device ACM Interface information */ + uint8_t func_iface[2]; + /** CDC Device ACM IN Endpoint */ + uint8_t func_ep_in[2]; + /** CDC Device ACM OUT Endpoint */ + uint8_t func_ep_out; + /** CDC Device ACM Enable Flag */ + bool enabled; +}; + +static struct usbdf_driver _cdcdf_acm; +static struct cdcdf_acm_func_data _cdcdf_acm_funcd; +static struct usb_cdc_line_coding usbd_cdc_line_coding; + +static cdcdf_acm_notify_state_t cdcdf_acm_notify_state = NULL; +static cdcdf_acm_set_line_coding_t cdcdf_acm_set_line_coding = NULL; + +/** + * \brief Enable CDC ACM Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t cdcdf_acm_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); + + usb_ep_desc_t ep_desc; + usb_iface_desc_t ifc_desc; + uint8_t * ifc, *ep; + uint8_t i; + + ifc = desc->sod; + for (i = 0; i < 2; i++) { + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if ((CDC_CLASS_COMM == ifc_desc.bInterfaceClass) || (CDC_CLASS_DATA == ifc_desc.bInterfaceClass)) { + if (func_data->func_iface[i] == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface[i] != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface[i] = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); + while (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in[i] = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in[i]); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + } + desc->sod = ep; + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + } + ifc = usb_find_desc(usb_desc_next(desc->sod), desc->eod, USB_DT_INTERFACE); + } + // Installed + _cdcdf_acm_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable CDC ACM Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t cdcdf_acm_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + uint8_t i; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + // Check interface + if ((ifc_desc.bInterfaceClass != CDC_CLASS_COMM) && (ifc_desc.bInterfaceClass != CDC_CLASS_DATA)) { + return ERR_NOT_FOUND; + } + } + + for (i = 0; i < 2; i++) { + if (func_data->func_iface[i] == 0xFF) { + continue; + } else { + func_data->func_iface[i] = 0xFF; + if (func_data->func_ep_in[i] != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in[i]); + func_data->func_ep_in[i] = 0xFF; + } + } + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + _cdcdf_acm_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief CDC ACM Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t cdcdf_acm_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return cdcdf_acm_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return cdcdf_acm_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the CDC class set request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t cdcdf_acm_set_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + struct usb_cdc_line_coding line_coding_tmp; + uint16_t len = req->wLength; + uint8_t * ctrl_buf = usbdc_get_ctrl_buffer(); + + switch (req->bRequest) { + case USB_REQ_CDC_SET_LINE_CODING: + if (sizeof(struct usb_cdc_line_coding) != len) { + return ERR_INVALID_DATA; + } + if (USB_SETUP_STAGE == stage) { + return usbdc_xfer(ep, ctrl_buf, len, false); + } else { + memcpy(&line_coding_tmp, ctrl_buf, sizeof(struct usb_cdc_line_coding)); + if ((NULL == cdcdf_acm_set_line_coding) || (true == cdcdf_acm_set_line_coding(&line_coding_tmp))) { + usbd_cdc_line_coding = line_coding_tmp; + } + return ERR_NONE; + } + case USB_REQ_CDC_SET_CONTROL_LINE_STATE: + usbdc_xfer(0, NULL, 0, 0); + if (NULL != cdcdf_acm_notify_state) { + cdcdf_acm_notify_state(req->wValue); + } + return ERR_NONE; + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the CDC class get request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t cdcdf_acm_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + uint16_t len = req->wLength; + + if (USB_DATA_STAGE == stage) { + return ERR_NONE; + } + + switch (req->bRequest) { + case USB_REQ_CDC_GET_LINE_CODING: + if (sizeof(struct usb_cdc_line_coding) != len) { + return ERR_INVALID_DATA; + } + return usbdc_xfer(ep, (uint8_t *)&usbd_cdc_line_coding, len, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the CDC class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t cdcdf_acm_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if ((req->wIndex == _cdcdf_acm_funcd.func_iface[0]) || (req->wIndex == _cdcdf_acm_funcd.func_iface[1])) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return cdcdf_acm_get_req(ep, req, stage); + } else { + return cdcdf_acm_set_req(ep, req, stage); + } + } else { + return ERR_NOT_FOUND; + } +} + +/** USB Device CDC ACM Handler Struct */ +static struct usbdc_handler cdcdf_acm_req_h = {NULL, (FUNC_PTR)cdcdf_acm_req}; + +/** + * \brief Initialize the USB CDC ACM Function Driver + */ +int32_t cdcdf_acm_init(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _cdcdf_acm.ctrl = cdcdf_acm_ctrl; + _cdcdf_acm.func_data = &_cdcdf_acm_funcd; + + usbdc_register_function(&_cdcdf_acm); + usbdc_register_handler(USBDC_HDL_REQ, &cdcdf_acm_req_h); + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB CDC ACM Function Driver + */ +void cdcdf_acm_deinit(void) +{ + usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_COMM_EP_INDEX]); + usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); + usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_out); +} + +/** + * \brief USB CDC ACM Function Read Data + */ +int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size) +{ + if (!cdcdf_acm_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_cdcdf_acm_funcd.func_ep_out, buf, size, false); +} + +/** + * \brief USB CDC ACM Function Write Data + */ +int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size) +{ + if (!cdcdf_acm_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], buf, size, true); +} + +/** + * \brief USB CDC ACM Stop the data transfer + */ +void cdcdf_acm_stop_xfer(void) +{ + /* Stop transfer. */ + usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); + usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_out); +} + +/** + * \brief USB CDC ACM Function Register Callback + */ +int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func) +{ + switch (cb_type) { + case CDCDF_ACM_CB_READ: + usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_out, USB_D_EP_CB_XFER, func); + break; + case CDCDF_ACM_CB_WRITE: + usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], USB_D_EP_CB_XFER, func); + break; + case CDCDF_ACM_CB_LINE_CODING_C: + cdcdf_acm_set_line_coding = (cdcdf_acm_set_line_coding_t)func; + break; + case CDCDF_ACM_CB_STATE_C: + cdcdf_acm_notify_state = (cdcdf_acm_notify_state_t)func; + break; + default: + return ERR_INVALID_ARG; + } + return ERR_NONE; +} + +/** + * \brief Check whether CDC ACM Function is enabled + */ +bool cdcdf_acm_is_enabled(void) +{ + return _cdcdf_acm_funcd.enabled; +} + +/** + * \brief Return the CDC ACM line coding structure start address + */ +const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void) +{ + return (const struct usb_cdc_line_coding *)&usbd_cdc_line_coding; +} + +/** + * \brief Return version + */ +uint32_t cdcdf_acm_get_version(void) +{ + return CDCDF_ACM_VERSION; +} diff --git a/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.h b/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.h new file mode 100644 index 0000000000000..913e734be4578 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.h @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief USB Device Stack CDC ACM Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_CDC_ACM_SER_H_ +#define USBDF_CDC_ACM_SER_H_ + +#include "usbdc.h" +#include "usb_protocol_cdc.h" + +/** CDC ACM Class Callback Type */ +enum cdcdf_acm_cb_type { CDCDF_ACM_CB_READ, CDCDF_ACM_CB_WRITE, CDCDF_ACM_CB_LINE_CODING_C, CDCDF_ACM_CB_STATE_C }; + +/** CDC ACM Notify Line State Callback. */ +typedef void (*cdcdf_acm_notify_state_t)(uint16_t); + +/** CDC ACM Set Line Coding Callback. */ +typedef bool (*cdcdf_acm_set_line_coding_t)(struct usb_cdc_line_coding *); + +/** + * \brief Initialize the USB CDC ACM Function Driver + * \return Operation status. + */ +int32_t cdcdf_acm_init(void); + +/** + * \brief Deinitialize the USB CDC ACM Function Driver + * \return Operation status. + */ +void cdcdf_acm_deinit(void); + +/** + * \brief USB CDC ACM Function Read Data + * \param[in] buf Pointer to the buffer which receives data + * \param[in] size the size of data to be received + * \return Operation status. + */ +int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size); + +/** + * \brief USB CDC ACM Function Write Data + * \param[in] buf Pointer to the buffer which stores data + * \param[in] size the size of data to be sent + * \return Operation status. + */ +int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size); + +/** + * \brief USB CDC ACM Stop the currnet data transfer + */ +void cdcdf_acm_stop_xfer(void); + +/** + * \brief USB CDC ACM Function Register Callback + * \param[in] cb_type Callback type of CDC ACM Function + * \param[in] func Pointer to callback function + * \return Operation status. + */ +int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func); + +/** + * \brief Check whether CDC ACM Function is enabled + * \return Operation status. + * \return true CDC ACM Function is enabled + * \return false CDC ACM Function is disabled + */ +bool cdcdf_acm_is_enabled(void); + +/** + * \brief Return the CDC ACM line coding structure start address + * \return Pointer to USB CDC ACM line coding data. + */ +const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void); + +/** + * \brief Return version + */ +uint32_t cdcdf_acm_get_version(void); + +#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h b/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h new file mode 100644 index 0000000000000..6017864cb2755 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h @@ -0,0 +1,407 @@ +/** + * \file + * + * \brief USB Communication Device Class (CDC) protocol definitions + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef _USB_PROTOCOL_CDC_H_ +#define _USB_PROTOCOL_CDC_H_ + +#include "usb_includes.h" + +/** + * \ingroup usb_protocol_group + * \defgroup cdc_protocol_group Communication Device Class Definitions + * @{ + */ + +/** + * \name Possible values of class + */ +//@{ +#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class +#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface +#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface +//@} + +//! \name USB CDC Subclass IDs +//@{ +#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model +#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model +#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model +#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model +#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model +#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model +#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model +//@} + +//! \name USB CDC Communication Interface Protocol IDs +//@{ +#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands +//@} + +//! \name USB CDC Data Interface Protocol IDs +//@{ +#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI +#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC +#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent +#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol +#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol +#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor +#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures +#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control +#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN +#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands +#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver + /** + * \brief Describes the Protocol Unit Functional Descriptors [sic] + * on Communication Class Interface + */ +#define CDC_PROTOCOL_PUFD 0xFE +//@} + +//! \name USB CDC Functional Descriptor Types +//@{ +#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor +#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor +//@} + +//! \name USB CDC Functional Descriptor Subtypes +//@{ +#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor +#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management +#define CDC_SCS_ACM 0x02 //!< Abstract Control Management +#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor +//@} + +//! \name USB CDC Request IDs +//@{ +#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define USB_REQ_CDC_SET_COMM_FEATURE 0x02 +#define USB_REQ_CDC_GET_COMM_FEATURE 0x03 +#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04 +#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10 +#define USB_REQ_CDC_SET_HOOK_STATE 0x11 +#define USB_REQ_CDC_PULSE_SETUP 0x12 +#define USB_REQ_CDC_SEND_PULSE 0x13 +#define USB_REQ_CDC_SET_PULSE_TIME 0x14 +#define USB_REQ_CDC_RING_AUX_JACK 0x15 +#define USB_REQ_CDC_SET_LINE_CODING 0x20 +#define USB_REQ_CDC_GET_LINE_CODING 0x21 +#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22 +#define USB_REQ_CDC_SEND_BREAK 0x23 +#define USB_REQ_CDC_SET_RINGER_PARMS 0x30 +#define USB_REQ_CDC_GET_RINGER_PARMS 0x31 +#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32 +#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33 +#define USB_REQ_CDC_SET_LINE_PARMS 0x34 +#define USB_REQ_CDC_GET_LINE_PARMS 0x35 +#define USB_REQ_CDC_DIAL_DIGITS 0x36 +#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37 +#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38 +#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39 +#define USB_REQ_CDC_GET_PROFILE 0x3A +#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41 +#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42 +#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44 +#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50 +#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51 +#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52 +#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53 +// Added bNotification codes according cdc spec 1.1 chapter 6.3 +#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09 +#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20 +#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 +#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 +//@} + +/* + * Need to pack structures tightly, or the compiler might insert padding + * and violate the spec-mandated layout. + */ +COMPILER_PACK_SET(1) + +//! \name USB CDC Descriptors +//@{ + +//! CDC Header Functional Descriptor +typedef struct usb_cdc_hdr_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + le16_t bcdCDC; +} usb_cdc_hdr_desc_t; + +#define USB_CDC_HDR_DESC_LEN 5 +#define USB_CDC_HDR_DESC_BYTES(bcdCDC) \ + USB_CDC_HDR_DESC_LEN, /* bFunctionLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_SCS_HEADER, /* bDescriptorSubtype */ \ + LE_BYTE0(bcdCDC), LE_BYTE1(bcdCDC) /* bcdCDC */ + +//! CDC Call Management Functional Descriptor +typedef struct usb_cdc_call_mgmt_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} usb_cdc_call_mgmt_desc_t; + +#define USB_CDC_CALL_MGMT_DESC_LEN 5 +#define USB_CDC_CALL_MGMT_DESC_BYTES(bmCapabilities, bDataInterface) \ + USB_CDC_CALL_MGMT_DESC_LEN, /* bFunctionLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_SCS_CALL_MGMT, /* bDescriptorSubtype */ \ + bmCapabilities, bDataInterface + +//! CDC ACM Functional Descriptor +typedef struct usb_cdc_acm_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} usb_cdc_acm_desc_t; + +#define USB_CDC_ACM_DESC_LEN 4 +#define USB_CDC_ACM_DESC_BYTES(bmCapabilities) \ + USB_CDC_ACM_DESC_LEN, /* bFunctionLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_SCS_ACM, /* bDescriptorSubType */ \ + bmCapabilities + +//! CDC Union Functional Descriptor +typedef struct usb_cdc_union_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bMasterInterface; + uint8_t bSlaveInterface0; +} usb_cdc_union_desc_t; + +#define USB_CDC_UNION_DESC_LEN 5 +#define USB_CDC_UNION_DESC_BYTES(bMasterInterface, bSlaveInterface) \ + USB_CDC_UNION_DESC_LEN, CDC_CS_INTERFACE, CDC_SCS_UNION, bMasterInterface, bSlaveInterface + +//! \name USB CDC Call Management Capabilities +//@{ +//! Device handles call management itself +#define CDC_CALL_MGMT_SUPPORTED (1 << 0) +//! Device can send/receive call management info over a Data Class interface +#define CDC_CALL_MGMT_OVER_DCI (1 << 1) +//@} + +//! \name USB CDC ACM Capabilities +//@{ +//! Device supports the request combination of +//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. +#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0) +//! Device supports the request combination of +//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, +//! and the notification Serial_State. +#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1) +//! Device supports the request Send_Break +#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2) +//! Device supports the notification Network_Connection. +#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3) +//@} +//@} + +//! \name USB CDC line control +//@{ + +//! \name USB CDC line coding +//@{ + +//! Line Coding structure +typedef struct usb_cdc_line_coding { + le32_t dwDTERate; //!< Data rate, bits per second + uint8_t bCharFormat; //!< 0-1 Stop bit,1-1.5 Stop bits,2-2 Stop bits + uint8_t bParityType; //!< 0-None,1-Odd,2-Even,3-Mark,4-Space + uint8_t bDataBits; //!< 5,6,7,8 or 16 +} usb_cdc_line_coding_t; + +//! Possible values of bCharFormat +enum cdc_char_format { + CDC_STOP_BITS_1 = 0, //!< 1 stop bit + CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits + CDC_STOP_BITS_2 = 2 //!< 2 stop bits +}; + +//! Possible values of bParityType +enum cdc_parity { + CDC_PAR_NONE = 0, //!< No parity + CDC_PAR_ODD = 1, //!< Odd parity + CDC_PAR_EVEN = 2, //!< Even parity + CDC_PAR_MARK = 3, //!< Parity forced to 0 (space) + CDC_PAR_SPACE = 4 //!< Parity forced to 1 (mark) +}; +//@} + +//! \name USB CDC control signals +//! spec 1.1 chapter 6.2.14 +//@{ + +//! Control signal structure +typedef struct usb_cdc_control_signal { + union { + le16_t value; + struct { + uint8_t dte_present; + uint8_t carrier_ctrl; + } modem; + struct { + uint8_t DTR : 1; //!< Data Terminal Ready + uint8_t RTS : 1; //!< Request To Send + } rs232; + struct { + uint8_t s108_2 : 1; //!< V.24 signal 108/2 + uint8_t s105 : 1; //!< V.24 signal 105 + } v24; + }; +} usb_cdc_control_signal_t; + +//! \name Possible values in usb_cdc_control_signal_t +//@{ +//! Carrier control for half duplex modems. +//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS. +//! The device ignores the value of this bit +//! when operating in full duplex mode. +#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1) +//! Indicates to DCE if DTE is present or not. +//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. +#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0) +//@} +//@} + +//! \name USB CDC notification message +//@{ + +typedef struct usb_cdc_notify_msg { + uint8_t bmRequestType; + uint8_t bNotification; + union { + le16_t wValue; + struct { + uint8_t low; + uint8_t high; + } wValueBytes; + }; + union { + le16_t wIndex; + struct { + uint8_t low; + uint8_t high; + } wIndexBytes; + }; + union { + le16_t wLength; + struct { + uint8_t low; + uint8_t high; + } wLengthBytes; + }; +} usb_cdc_notify_msg_t; + +//! \name USB CDC serial state +//@{* + +//! UART State Bitmap (cdc spec 1.1 chapter 6.3.5) +typedef union usb_cdc_uart_state { + le16_t value; + struct { + uint8_t bRxCarrier : 1; + uint8_t bTxCarrier : 1; + uint8_t bBreak : 1; + uint8_t bRingSignal : 1; + uint8_t bFraming : 1; + uint8_t bParity : 1; + uint8_t bOverRun; + } bitmap; + struct { + uint8_t bDCD : 1; + uint8_t bDSR : 1; + uint8_t bBreak : 1; + uint8_t bRingSignal : 1; + uint8_t bFraming : 1; + uint8_t bParity : 1; + uint8_t bOverRun; + } rs232; + struct { + uint8_t bS109 : 1; //!< V.24 signal 109 + uint8_t bS106 : 1; //!< V.24 signal 106 + uint8_t bBreak : 1; + uint8_t bRingSignal : 1; + uint8_t bFraming : 1; + uint8_t bParity : 1; + uint8_t bOverRun; + } v24; +} usb_cdc_uart_state_t; + +//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5) +typedef struct usb_cdc_notify_serial_state { + usb_cdc_notify_msg_t header; + union usb_cdc_uart_state state; +} usb_cdc_notify_serial_state_t; + +//! \name Possible values in usb_cdc_notify_serial_state_t +//@{ +#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1 << 0)) +#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1 << 1)) +#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1 << 2)) +#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1 << 3)) +#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1 << 4)) +#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1 << 5)) +#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1 << 6)) +//@} +//! @} + +//! @} + +COMPILER_PACK_RESET() + +//! @} + +#endif // _USB_PROTOCOL_CDC_H_ diff --git a/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h b/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h new file mode 100644 index 0000000000000..68db57af99e98 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h @@ -0,0 +1,170 @@ +/** + * \file + * + * \brief USB Device Stack Composite Class Descriptor Setting. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_COMPOSITE_DESC_H_ +#define USBDF_COMPOSITE_DESC_H_ + +#include "usb_protocol.h" +#include "usbd_composite_config.h" + +#if CONF_USB_COMPOSITE_CDC_ACM_EN == 1 +#define CONF_CDC_ACM_IFC_LEN 66 +#define CONF_CDC_ACM_IFC_NUM 2 +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM 0 +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM 1 +#define CONF_CDC_ACM_IFC_DESC \ + USB_IAD_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x02, CDC_CLASS_DEVICE, CDC_SUBCLASS_ACM, CDC_PROTOCOL_V25TER, 0x00) \ + , \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, \ + 0x00, \ + 0x01, \ + CDC_CLASS_DEVICE, \ + CDC_SUBCLASS_ACM, \ + CDC_PROTOCOL_V25TER, \ + 0x00), \ + USB_CDC_HDR_DESC_BYTES(0x1001), USB_CDC_CALL_MGMT_DESC_BYTES(0x01, 0x00), USB_CDC_ACM_DESC_BYTES(0x02), \ + USB_CDC_UNION_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x01), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR, 3, CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ, 10), \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM, 0x00, 2, 0x0A, 0x00, 0x00, 0x00), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ, 0x00), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ, 0x00), +#else +#define CONF_CDC_ACM_IFC_LEN 0 +#define CONF_CDC_ACM_IFC_NUM 0 +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM -2 +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM -1 +#define CONF_CDC_ACM_IFC_DESC +#endif + +#if CONF_USB_COMPOSITE_HID_MOUSE_EN == 1 +#define CONF_HID_MOUSE_IFC_LEN 25 +#define CONF_HID_MOUSE_IFC_NUM 1 +#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM (CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM + 1) +#define CONF_HID_MOUSE_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM, 0x00, 0x01, 0x03, 0x01, 0x02, 0x00) \ + , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 0x34), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ, 10), +#else +#define CONF_HID_MOUSE_IFC_LEN 0 +#define CONF_HID_MOUSE_IFC_NUM 0 +#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM +#define CONF_HID_MOUSE_IFC_DESC +#endif + +#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN == 1 +#define CONF_HID_KEYBOARD_IFC_LEN 32 +#define CONF_HID_KEYBOARD_IFC_NUM 1 +#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM (CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM + 1) +#define CONF_HID_KEYBOARD_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM, 0x00, 0x02, 0x03, 0x01, 0x01, 0x00) \ + , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 59), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ, 10), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ, 10), +#else +#define CONF_HID_KEYBOARD_IFC_LEN 0 +#define CONF_HID_KEYBOARD_IFC_NUM 0 +#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM +#define CONF_HID_KEYBOARD_IFC_DESC +#endif + +#if CONF_USB_COMPOSITE_HID_GENERIC_EN == 1 +#define CONF_HID_GENERIC_IFC_LEN 32 +#define CONF_HID_GENERIC_IFC_NUM 1 +#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM (CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM + 1) +#define CONF_HID_GENERIC_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM, 0x00, 0x02, 0x03, 0x00, 0x00, 0x00) \ + , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ, 10), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ, 10), +#else +#define CONF_HID_GENERIC_IFC_LEN 0 +#define CONF_HID_GENERIC_IFC_NUM 0 +#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM +#define CONF_HID_GENERIC_IFC_DESC +#endif + +#define CONF_USB_COMPOSITE_TOTAL_LEN \ + (USB_CONFIG_DESC_LEN + CONF_CDC_ACM_IFC_LEN + CONF_HID_MOUSE_IFC_LEN + CONF_HID_KEYBOARD_IFC_LEN \ + + CONF_HID_GENERIC_IFC_LEN) + +#define CONF_USB_COMPOSITE_IFC_NUM \ + (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM) + +#define COMPOSITE_DEV_DESC \ + USB_DEV_DESC_BYTES(CONF_USB_COMPOSITE_BCDUSB, \ + 0xEF, \ + 0x02, \ + 0x01, \ + CONF_USB_COMPOSITE_BMAXPKSZ0, \ + CONF_USB_COMPOSITE_IDVENDER, \ + CONF_USB_COMPOSITE_IDPRODUCT, \ + CONF_USB_COMPOSITE_BCDDEVICE, \ + CONF_USB_COMPOSITE_IMANUFACT, \ + CONF_USB_COMPOSITE_IPRODUCT, \ + CONF_USB_COMPOSITE_ISERIALNUM, \ + CONF_USB_COMPOSITE_BNUMCONFIG) + +#define COMPOSITE_CFG_DESC \ + USB_CONFIG_DESC_BYTES(CONF_USB_COMPOSITE_TOTAL_LEN, \ + CONF_USB_COMPOSITE_IFC_NUM, \ + CONF_USB_COMPOSITE_BCONFIGVAL, \ + CONF_USB_COMPOSITE_ICONFIG, \ + CONF_USB_COMPOSITE_BMATTRI, \ + CONF_USB_COMPOSITE_BMAXPOWER) + +#define COMPOSITE_IFACE_DESCES \ + CONF_CDC_ACM_IFC_DESC \ + CONF_HID_MOUSE_IFC_DESC \ + CONF_HID_KEYBOARD_IFC_DESC \ + CONF_HID_GENERIC_IFC_DESC + +/** USB Device descriptors and configuration descriptors */ +#define COMPOSITE_DESCES_LS_FS \ + COMPOSITE_DEV_DESC, COMPOSITE_CFG_DESC, COMPOSITE_IFACE_DESCES CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC, \ + CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC, CONF_USB_COMPOSITE_PRODUCT_STR_DESC + +#endif /* USBDF_COMPOSITE_DESC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h b/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h new file mode 100644 index 0000000000000..1b29802b031f7 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file usbd_composite_config.h */ +#ifndef USBD_COMPOSITE_CONFIG_H +#define USBD_COMPOSITE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Composite Device Descriptor + +// bcdUSB +// <0x0200=> USB 2.0 version +// <0x0210=> USB 2.1 version +// usb_composite_bcdusb +#ifndef CONF_USB_COMPOSITE_BCDUSB +#define CONF_USB_COMPOSITE_BCDUSB 0x200 +#endif + +// bMaxPackeSize0 +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_bmaxpksz0 +#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 +#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 +#endif + +// idVender <0x0000-0xFFFF> +// usb_composite_idvender +#ifndef CONF_USB_COMPOSITE_IDVENDER +#define CONF_USB_COMPOSITE_IDVENDER 0x3eb +#endif + +// idProduct <0x0000-0xFFFF> +// usb_composite_idproduct +#ifndef CONF_USB_COMPOSITE_IDPRODUCT +#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 +#endif + +// bcdDevice <0x0000-0xFFFF> +// usb_composite_bcddevice +#ifndef CONF_USB_COMPOSITE_BCDDEVICE +#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 +#endif + +// iManufacturer <0x00-0xFF> +// usb_composite_imanufact +#ifndef CONF_USB_COMPOSITE_IMANUFACT +#define CONF_USB_COMPOSITE_IMANUFACT 0x0 +#endif + +#ifndef CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC +#define CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC 0x04, 0x03, 0x09, 0x04 +#endif + +#ifndef CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC +#define CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC \ + 0x14, 0x03, 0x41, 0x00, 0x54, 0x00, 0x4D, 0x00, 0x45, 0x00, 0x4C, 0x00, 0x20, 0x00, 0x41, 0x00, 0x53, 0x00, 0x46, \ + 0x00 +#endif + +// iProduct <0x00-0xFF> +// usb_composite_iproduct +#ifndef CONF_USB_COMPOSITE_IPRODUCT +#define CONF_USB_COMPOSITE_IPRODUCT 0x0 +#endif + +#ifndef CONF_USB_COMPOSITE_PRODUCT_STR_DESC +#define CONF_USB_COMPOSITE_PRODUCT_STR_DESC \ + 0x22, 0x03, 0x43, 0x00, 0x6f, 0x00, 0x6d, 0x00, 0x70, 0x00, 0x6f, 0x00, 0x73, 0x00, 0x69, 0x00, 0x74, 0x00, 0x65, \ + 0x00, 0x20, 0x00, 0x44, 0x00, 0x65, 0x00, 0x76, 0x00, 0x69, 0x00, 0x63, 0x00, 0x65, 0x00 +#endif + +// iSerialNumber <0x00-0xFF> +// usb_composite_iserialnum +#ifndef CONF_USB_COMPOSITE_ISERIALNUM +#define CONF_USB_COMPOSITE_ISERIALNUM 0x0 +#endif + +// bNumConfigurations <0x01-0xFF> +// usb_composite_bnumconfig +#ifndef CONF_USB_COMPOSITE_BNUMCONFIG +#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 +#endif +// + +// Composite Configuration Descriptor + +// bConfigurationValue <0x01-0xFF> +// usb_composite_bconfigval +#ifndef CONF_USB_COMPOSITE_BCONFIGVAL +#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 +#endif + +// iConfiguration <0x00-0xFF> +// usb_composite_iconfig +#ifndef CONF_USB_COMPOSITE_ICONFIG +#define CONF_USB_COMPOSITE_ICONFIG 0x0 +#endif + +// bmAttributes +// <0x80=> Bus power supply, not support for remote wakeup +// <0xA0=> Bus power supply, support for remote wakeup +// <0xC0=> Self powered, not support for remote wakeup +// <0xE0=> Self powered, support for remote wakeup +// usb_composite_bmattri +#ifndef CONF_USB_COMPOSITE_BMATTRI +#define CONF_USB_COMPOSITE_BMATTRI 0x80 +#endif + +// bMaxPower <0x00-0xFF> +// usb_composite_bmaxpower +#ifndef CONF_USB_COMPOSITE_BMAXPOWER +#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 +#endif +// + +// CDC ACM Support +// usb_composite_cdc_acm_support +#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN +#define CONF_USB_COMPOSITE_CDC_ACM_EN 1 +#endif + +// CDC ACM Comm Interrupt IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_cdc_acm_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 +#endif + +// CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_cdc_acm_comm_int_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_cdc_acm_data_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 +#endif + +// CDC ACM Data BULK IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_cdc_acm_data_builin_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// usb_composite_cdc_acm_data_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 +#endif + +// CDC ACM Data BULK OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_cdc_acm_data_buckout_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 +#endif +// + +// HID Mouse Support +// usb_composite_hid_mouse_support +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN +#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 +#endif + +// HID Mouse INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_hid_mouse_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 +#endif + +// HID Mouse INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_mouse_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 +#endif + +// + +// HID Keyboard Support +// usb_composite_hid_keyboard_support +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN +#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 +#endif + +// HID Keyboard INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_hid_keyboard_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 +#endif + +// HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_keyboard_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// usb_composite_hid_keyboard_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_keyboard_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 +#endif + +// + +// HID Generic Support +// usb_composite_hid_generic_support +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN +#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 +#endif + +// HID Generic INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_hid_generic_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 +#endif + +// HID Generic INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_generic_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 +#endif + +// HID Generic INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// usb_composite_hid_generic_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 +#endif + +// HID Generic INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_generic_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 +#endif + +// + +// <<< end of configuration section >>> + +#endif // USBD_COMPOSITE_CONFIG_H diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.c b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.c new file mode 100644 index 0000000000000..2c7cd35847379 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.c @@ -0,0 +1,358 @@ +/** + * \file + * + * \brief USB Device Stack HID Generic Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hiddf_generic.h" +#include + +#define HIDDF_GENERIC_VERSION 0x00000001u + +/** USB Device HID Generic Function Specific Data */ +struct hiddf_generic_func_data { + /** HID Device Generic Interface information */ + uint8_t func_iface; + /** HID Device Generic IN Endpoint */ + uint8_t func_ep_in; + /** HID Device Generic OUT Endpoint */ + uint8_t func_ep_out; + /** HID Device Generic Report Descriptor */ + const uint8_t *report_desc; + /** HID Device Generic Report Descriptor Length */ + uint32_t report_desc_len; + /** HID Device Generic Enable Flag */ + bool enabled; +}; + +/* USB Device HID Generic Function Instance */ +static struct usbdf_driver _hiddf_generic; + +/* USB Device HID Generic Function Data Instance */ +static struct hiddf_generic_func_data _hiddf_generic_funcd; + +/* USB Device HID Generic Set Report Function Callback */ +static hiddf_generic_set_report_t hiddf_generic_set_report = NULL; + +/** + * \brief Enable HID Generic Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t hid_generic_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + uint8_t * ifc, *ep, i; + usb_iface_desc_t ifc_desc; + usb_ep_desc_t ep_desc; + + struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (HID_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + for (i = 0; i < 2; i++) { + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + desc->sod = ep; + if (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + } + } else { + return ERR_NOT_FOUND; + } + } + + // Installed + _hiddf_generic_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable HID Generic Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t hid_generic_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + if (ifc_desc.bInterfaceClass != HID_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + _hiddf_generic_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief HID Generic Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t hid_generic_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return hid_generic_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return hid_generic_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class get descriptor + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_generic_get_desc(uint8_t ep, struct usb_req *req) +{ + switch (req->wValue >> 8) { + case USB_DT_HID_REPORT: + return usbdc_xfer(ep, (uint8_t *)_hiddf_generic_funcd.report_desc, _hiddf_generic_funcd.report_desc_len, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_generic_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + uint8_t *ctrl_buf = usbdc_get_ctrl_buffer(); + uint16_t len = req->wLength; + + if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_generic_funcd.func_iface)) { + return hid_generic_get_desc(ep, req); + } else { + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if (req->wIndex == _hiddf_generic_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return ERR_INVALID_ARG; + } else { + if (USB_REQ_HID_SET_REPORT == req->bRequest) { + if (USB_SETUP_STAGE == stage) { + return usbdc_xfer(ep, ctrl_buf, len, false); + } else { + if (NULL != hiddf_generic_set_report) { + hiddf_generic_set_report(ctrl_buf, len); + } + return ERR_NONE; + } + } else { + return usbdc_xfer(0, NULL, 0, 0); + } + } + } else { + return ERR_NOT_FOUND; + } + } +} + +/** USB Device HID Generic Handler Struct */ +static struct usbdc_handler hid_generic_req_h = {NULL, (FUNC_PTR)hid_generic_req}; + +/** + * \brief Initialize the USB HID Generic Function Driver + */ +int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len) +{ + if (NULL == report_desc || 0 == len) { + return ERR_INVALID_ARG; + } + + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_generic_funcd.report_desc = report_desc; + _hiddf_generic_funcd.report_desc_len = len; + _hiddf_generic.ctrl = hid_generic_ctrl; + _hiddf_generic.func_data = &_hiddf_generic_funcd; + + usbdc_register_function(&_hiddf_generic); + usbdc_register_handler(USBDC_HDL_REQ, &hid_generic_req_h); + + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB HID Generic Function Driver + */ +int32_t hiddf_generic_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_generic.ctrl = NULL; + _hiddf_generic.func_data = NULL; + + usbdc_unregister_function(&_hiddf_generic); + usbdc_unregister_handler(USBDC_HDL_REQ, &hid_generic_req_h); + return ERR_NONE; +} + +/** + * \brief Check whether HID Generic Function is enabled + */ +bool hiddf_generic_is_enabled(void) +{ + return _hiddf_generic_funcd.enabled; +} + +/** + * \brief USB HID Generic Function Read Data + */ +int32_t hiddf_generic_read(uint8_t *buf, uint32_t size) +{ + if (!hiddf_generic_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_hiddf_generic_funcd.func_ep_out, buf, size, false); +} + +/** + * \brief USB HID Generic Function Write Data + */ +int32_t hiddf_generic_write(uint8_t *buf, uint32_t size) +{ + if (!hiddf_generic_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_hiddf_generic_funcd.func_ep_in, buf, size, false); +} + +/** + * \brief USB HID Generic Function Register Callback + */ +int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func) +{ + if (!hiddf_generic_is_enabled()) { + return ERR_DENIED; + } + switch (cb_type) { + case HIDDF_GENERIC_CB_READ: + usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_out, USB_D_EP_CB_XFER, func); + break; + case HIDDF_GENERIC_CB_WRITE: + usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_in, USB_D_EP_CB_XFER, func); + break; + case HIDDF_GENERIC_CB_SET_REPORT: + hiddf_generic_set_report = (hiddf_generic_set_report_t)func; + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Return version + */ +uint32_t hiddf_generic_get_version(void) +{ + return HIDDF_GENERIC_VERSION; +} diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.h b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.h new file mode 100644 index 0000000000000..c12f1575ad86d --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.h @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief USB Device Stack HID Generic Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_HID_GENERIC_H_ +#define USBDF_HID_GENERIC_H_ + +#include "usbdc.h" +#include "usb_protocol_hid.h" + +/** HID Generic Callback Type */ +enum hiddf_generic_cb_type { HIDDF_GENERIC_CB_READ, HIDDF_GENERIC_CB_WRITE, HIDDF_GENERIC_CB_SET_REPORT }; + +/** HID Generic Set Report Callback. */ +typedef bool (*hiddf_generic_set_report_t)(uint8_t *, uint16_t); + +/** + * \brief Initialize the USB HID Generic Function Driver + * \param[in] report_desc Point to usr HID Report Descriptor + * \param[in] len length of usr HID Report Descriptor + * \return Operation status. + */ +int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len); + +/** + * \brief Deinitialize the USB HID Generic Function Driver + * \return Operation status. + */ +int32_t hiddf_generic_deinit(void); + +/** + * \brief Check whether HID Generic Function is enabled + * \return Operation status. + * \return true HID Generic Function is enabled + * \return false HID Generic Function is disabled + */ +bool hiddf_generic_is_enabled(void); + +/** + * \brief USB HID Generic Function Read Data + * \param[in] buf Pointer to the buffer which receives data + * \param[in] size the size of data to be received + * \return Operation status. + */ +int32_t hiddf_generic_read(uint8_t *buf, uint32_t size); + +/** + * \brief USB HID Generic Function Write Data + * \param[in] buf Pointer to the buffer which stores data + * \param[in] size the size of data to be sent + * \return Operation status. + */ +int32_t hiddf_generic_write(uint8_t *buf, uint32_t size); + +/** + * \brief USB HID Generic Function Register Callback + * \param[in] cb_type Callback type of HID Generic Function + * \param[in] func Pointer to callback function + * \return Operation status. + */ +int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func); + +/** + * \brief Return version + */ +uint32_t hiddf_generic_get_version(void); + +#endif /* USBDF_HID_GENERIC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.c b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.c new file mode 100644 index 0000000000000..835481e416eae --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.c @@ -0,0 +1,365 @@ +/** + * \file + * + * \brief USB Device Stack HID Keyboard Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hiddf_keyboard.h" +#include + +#define HIDDF_KEYBOARD_VERSION 0x00000001u + +#define KEYBOARD_REPORT_DESC_LEN 59 + +/** USB Device HID Keyboard Function Specific Data */ +struct hiddf_keyboard_func_data { + /* HID Device Keyboard Report */ + uint8_t kb_report[8]; + /** HID Device Keyboard Interface information */ + uint8_t func_iface; + /** HID Device Keyboard IN Endpoint */ + uint8_t func_ep_in; + /** HID Device Keyboard OUT Endpoint */ + uint8_t func_ep_out; + /** HID Device Keyboard Enable Flag */ + bool enabled; +}; + +/* HID report descriptor for standard HID keyboard */ +const uint8_t keyboard_report_desc[KEYBOARD_REPORT_DESC_LEN] = { + 0x05, 0x01, /* Usage Page (Generic Desktop) */ + 0x09, 0x06, /* Usage (Keyboard) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x05, 0x07, /* Usage Page (Keyboard) */ + 0x19, 0xE0, /* Usage Minimum (224) */ + 0x29, 0xE7, /* Usage Maximum (231) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x08, /* Report Count (8) */ + 0x81, 0x02, /* Input (Data, Variable, Absolute) */ + 0x81, 0x01, /* Input (Constant) */ + 0x19, 0x00, /* Usage Minimum (0) */ + 0x29, 0x65, /* Usage Maximum (101) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x65, /* Logical Maximum (101) */ + 0x75, 0x08, /* Report Size (8) */ + 0x95, 0x06, /* Report Count (6) */ + 0x81, 0x00, /* Input (Data, Array) */ + 0x05, 0x08, /* Usage Page (LED) */ + 0x19, 0x01, /* Usage Minimum (1) */ + 0x29, 0x05, /* Usage Maximum (5) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x05, /* Report Count (5) */ + 0x91, 0x02, /* Output (Data, Variable, Absolute) */ + 0x95, 0x03, /* Report Count (3) */ + 0x91, 0x01, /* Output (Constant) */ + 0xC0 /* End Collection */ +}; + +/* USB Device HID Keyboard Function Instance */ +static struct usbdf_driver _hiddf_keyboard; + +/* USB Device HID Keyboard Function Data Instance */ +static struct hiddf_keyboard_func_data _hiddf_keyboard_funcd; + +/** + * \brief Enable HID Keyboard Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t hid_keyboard_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + uint8_t * ifc, *ep, i; + usb_iface_desc_t ifc_desc; + usb_ep_desc_t ep_desc; + + struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (HID_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + for (i = 0; i < 2; i++) { + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + desc->sod = ep; + if (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + } + } else { + return ERR_NOT_FOUND; + } + } + + // Installed + _hiddf_keyboard_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable HID Keyboard Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t hid_keyboard_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + if (ifc_desc.bInterfaceClass != HID_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + _hiddf_keyboard_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief HID Keyboard Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t hid_keyboard_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return hid_keyboard_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return hid_keyboard_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class get descriptor + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_keyboard_get_desc(uint8_t ep, struct usb_req *req) +{ + switch (req->wValue >> 8) { + case USB_DT_HID_REPORT: + return usbdc_xfer(ep, (uint8_t *)keyboard_report_desc, KEYBOARD_REPORT_DESC_LEN, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_keyboard_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_keyboard_funcd.func_iface)) { + return hid_keyboard_get_desc(ep, req); + } else { + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if (req->wIndex == _hiddf_keyboard_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return ERR_INVALID_ARG; + } else { + return usbdc_xfer(0, NULL, 0, 0); + } + } else { + return ERR_NOT_FOUND; + } + } + (void)stage; +} + +/** USB Device HID Keyboard Handler Struct */ +static struct usbdc_handler hid_keyboard_req_h = {NULL, (FUNC_PTR)hid_keyboard_req}; + +/** + * \brief Initialize the USB HID Keyboard Function Driver + */ +int32_t hiddf_keyboard_init(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_keyboard.ctrl = hid_keyboard_ctrl; + _hiddf_keyboard.func_data = &_hiddf_keyboard_funcd; + + usbdc_register_function(&_hiddf_keyboard); + usbdc_register_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB HID Keyboard Function Driver + */ +int32_t hiddf_keyboard_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_keyboard.ctrl = NULL; + _hiddf_keyboard.func_data = NULL; + + usbdc_unregister_function(&_hiddf_keyboard); + usbdc_unregister_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); + return ERR_NONE; +} + +/** + * \brief Check whether HID Keyboard Function is enabled + */ +bool hiddf_keyboard_is_enabled(void) +{ + return _hiddf_keyboard_funcd.enabled; +} + +/** + * \brief Process the HID Keyboard key state change request + * \param keys_desc[] keys_descriptor array for state changing + * \param keys_count total keys amount for state changing + * \return Operation status. + */ +int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count) +{ + uint8_t i, j; + uint8_t modifier_keys, regular_keys; + + if (!hiddf_keyboard_is_enabled()) { + return ERR_DENIED; + } + + memset(_hiddf_keyboard_funcd.kb_report, 0x00, 8); + modifier_keys = 0; + + for (i = 0; i < keys_count; i++) { + if (true == keys_desc[i].b_modifier) { + modifier_keys++; + } + } + + regular_keys = keys_count - modifier_keys; + + if (regular_keys > 6) { + memset(&_hiddf_keyboard_funcd.kb_report[2], 0xFF, 6); + } else { + i = 2; + for (j = 0; j < keys_count; j++) { + if (HID_KB_KEY_DOWN == keys_desc[j].state) { + if (true == keys_desc[j].b_modifier) { + _hiddf_keyboard_funcd.kb_report[0] |= keys_desc[j].key_id; + } else { + _hiddf_keyboard_funcd.kb_report[i++] = keys_desc[j].key_id; + } + } + } + } + return usbdc_xfer(_hiddf_keyboard_funcd.func_ep_in, &_hiddf_keyboard_funcd.kb_report[0], 8, false); +} + +/** + * \brief Return version + */ +uint32_t hiddf_keyboard_get_version(void) +{ + return HIDDF_KEYBOARD_VERSION; +} diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.h b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.h new file mode 100644 index 0000000000000..3295d1b785a3f --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.h @@ -0,0 +1,91 @@ +/** + * \file + * + * \brief USB Device Stack HID Keyboard Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_HID_KEYBOARD_H_ +#define USBDF_HID_KEYBOARD_H_ + +#include "usbdc.h" +#include "usb_protocol_hid.h" + +/** HID Keyboard Class Key State Type */ +enum hiddf_kb_key_state { HID_KB_KEY_UP, HID_KB_KEY_DOWN }; + +/** Describes the USB HID Keyboard Key descriptors. */ +struct hiddf_kb_key_descriptors { + /* HID Key Value, defined in usb_protocol_hid.h */ + uint8_t key_id; + /* Flag whether it is a modifier key */ + bool b_modifier; + /* Key State */ + enum hiddf_kb_key_state state; +}; + +/** + * \brief Initialize the USB HID Keyboard Function Driver + * \return Operation status. + */ +int32_t hiddf_keyboard_init(void); + +/** + * \brief Deinitialize the USB HID Keyboard Function Driver + * \return Operation status. + */ +int32_t hiddf_keyboard_deinit(void); + +/** + * \brief Check whether HID Keyboard Function is enabled + * \return Operation status. + * \return true HID Keyboard Function is enabled + * \return false HID Keyboard Function is disabled + */ +bool hiddf_keyboard_is_enabled(void); + +/** + * \brief Process the HID Keyboard key state change request + * \param keys_desc[] keys_descriptor array for state changing + * \param keys_count total keys amount for state changing + * \return Operation status. + */ +int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count); + +/** + * \brief Return version + */ +uint32_t hiddf_keyboard_get_version(void); + +#endif /* USBDF_HID_KEYBOARD_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.c b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.c new file mode 100644 index 0000000000000..7a58ce66e0824 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.c @@ -0,0 +1,363 @@ +/** + * \file + * + * \brief USB Device Stack HID Mouse Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hiddf_mouse.h" + +#define HIDDF_MOUSE_VERSION 0x00000001u + +#define MOUSE_REPORT_DESC_LEN 52 + +/** USB Device HID Mouse Function Specific Data */ +struct hiddf_mouse_func_data { + /* HID Device Mouse Report */ + union { + /** Interpreted by bytes. */ + struct { + /** Button Status. */ + uint8_t button_state; + /** X Axis Variant.*/ + uint8_t x_axis_var; + /** Y Axis Variant.*/ + uint8_t y_axis_var; + /** Scroll Variant.*/ + uint8_t scroll_var; + } bytes; + uint32_t u32; + } mouse_report; + /** HID Device Mouse Interface information */ + uint8_t func_iface; + /** HID Device Mouse IN Endpoint */ + uint8_t func_ep_in; + /** HID Device Mouse Enable Flag */ + bool enabled; +}; + +/* HID report descriptor for standard HID mouse */ +const uint8_t mouse_report_desc[MOUSE_REPORT_DESC_LEN] = { + 0x05, 0x01, /* Usage Page (Generic Desktop), */ + 0x09, 0x02, /* Usage (Mouse), */ + 0xA1, 0x01, /* Collection (Application), */ + 0x09, 0x01, /* Usage (Pointer), */ + 0xA1, 0x00, /* Collection (Physical), */ + 0x05, 0x09, /* Usage Page (Buttons), */ + 0x19, 0x01, /* Usage Minimum (01), */ + 0x29, 0x03, /* Usage Maximum (03), */ + 0x15, 0x00, /* Logical Minimum (0), */ + 0x25, 0x01, /* Logical Maximum (1), */ + 0x75, 0x01, /* Report Size (1), */ + 0x95, 0x03, /* Report Count (3), */ + 0x81, 0x02, /* Input (Data, Variable, Absolute) */ + 0x75, 0x05, /* Report Size (5), */ + 0x95, 0x01, /* Report Count (1), */ + 0x81, 0x01, /* Input (Constant), */ + 0x05, 0x01, /* Usage Page (Generic Desktop), */ + 0x09, 0x30, /* Usage (X), */ + 0x09, 0x31, /* Usage (Y), */ + 0x09, 0x38, /* Usage (Scroll), */ + 0x15, 0x81, /* Logical Minimum (-127), */ + 0x25, 0x7F, /* Logical Maximum (127), */ + 0x75, 0x08, /* Report Size (8), */ + 0x95, 0x03, /* Report Count (3), */ + 0x81, 0x06, /* Input (Data, Variable, Relative) */ + 0xC0, /* End Collection, */ + 0xC0, /* End Collection */ +}; + +/* USB Device HID Mouse Function Instance */ +static struct usbdf_driver _hiddf_mouse; + +/* USB Device HID Mouse Function Data Instance */ +static struct hiddf_mouse_func_data _hiddf_mouse_funcd; + +/** + * \brief Enable HID Mouse Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t hid_mouse_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + uint8_t * ifc, *ep; + usb_iface_desc_t ifc_desc; + usb_ep_desc_t ep_desc; + + struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (HID_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + desc->sod = ep; + if (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + } else { + return ERR_INVALID_DATA; + } + } else { + return ERR_NOT_FOUND; + } + // Installed + _hiddf_mouse_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable HID Mouse Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t hid_mouse_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + if (ifc_desc.bInterfaceClass != HID_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + _hiddf_mouse_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief HID Mouse Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t hid_mouse_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return hid_mouse_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return hid_mouse_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class get descriptor + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_mouse_get_desc(uint8_t ep, struct usb_req *req) +{ + switch (req->wValue >> 8) { + case USB_DT_HID_REPORT: + return usbdc_xfer(ep, (uint8_t *)mouse_report_desc, MOUSE_REPORT_DESC_LEN, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_mouse_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_mouse_funcd.func_iface)) { + return hid_mouse_get_desc(ep, req); + } else { + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if (req->wIndex == _hiddf_mouse_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return ERR_INVALID_ARG; + } else { + return usbdc_xfer(0, NULL, 0, 0); + } + } else { + return ERR_NOT_FOUND; + } + } + (void)stage; +} + +/** USB Device HID Mouse Handler Struct */ +static struct usbdc_handler hid_mouse_req_h = {NULL, (FUNC_PTR)hid_mouse_req}; + +/** + * \brief Initialize the USB HID Mouse Function Driver + */ +int32_t hiddf_mouse_init(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_mouse.ctrl = hid_mouse_ctrl; + _hiddf_mouse.func_data = &_hiddf_mouse_funcd; + + usbdc_register_function(&_hiddf_mouse); + usbdc_register_handler(USBDC_HDL_REQ, &hid_mouse_req_h); + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB HID Mouse Function Driver + */ +int32_t hiddf_mouse_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_mouse.ctrl = NULL; + _hiddf_mouse.func_data = NULL; + + usbdc_unregister_function(&_hiddf_mouse); + usbdc_unregister_handler(USBDC_HDL_REQ, &hid_mouse_req_h); + return ERR_NONE; +} + +/** + * \brief Check whether HID Mouse Function is enabled + */ +bool hiddf_mouse_is_enabled(void) +{ + return _hiddf_mouse_funcd.enabled; +} + +/** + * \brief Move the mouse pointer + * \param pos Signed value to move + * \param type HID mouse class pointer move type + * \return Operation status. + */ +int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type) +{ + + _hiddf_mouse_funcd.mouse_report.u32 = 0; + + if (type == HID_MOUSE_X_AXIS_MV) { + _hiddf_mouse_funcd.mouse_report.bytes.x_axis_var = pos; + } else if (type == HID_MOUSE_Y_AXIS_MV) { + _hiddf_mouse_funcd.mouse_report.bytes.y_axis_var = pos; + } else if (type == HID_MOUSE_SCROLL_MV) { + _hiddf_mouse_funcd.mouse_report.bytes.scroll_var = pos; + } else { + return ERR_INVALID_ARG; + } + + return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); +} + +/** + * \brief Changes button state + * \param b_state New button state + * \param type Button type + * \return Operation status. + */ +int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type) +{ + _hiddf_mouse_funcd.mouse_report.u32 = 0; + + if (b_state == HID_MOUSE_BTN_DOWN) { + _hiddf_mouse_funcd.mouse_report.bytes.button_state = type; + } else { + _hiddf_mouse_funcd.mouse_report.bytes.button_state = 0x00; + } + + return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); +} + +/** + * \brief Return version + */ +uint32_t hiddf_mouse_get_version(void) +{ + return HIDDF_MOUSE_VERSION; +} diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.h b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.h new file mode 100644 index 0000000000000..464b1e92dfbf7 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief USB Device Stack HID Mouse Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_HID_MOUSE_H_ +#define USBDF_HID_MOUSE_H_ + +#include "usbdc.h" +#include "usb_protocol_hid.h" + +/** HID Mouse Class Button State Type */ +enum hiddf_mouse_button_state { HID_MOUSE_BTN_UP, HID_MOUSE_BTN_DOWN }; + +/* HID Mosue Class Button Type */ +enum hiddf_mouse_button_type { HID_MOUSE_LEFT_BTN = 0x01, HID_MOUSE_RIGHT_BTN = 0x02, HID_MOUSE_MIDDLE_BTN = 0x04 }; + +/* HID Mouse Class Pointer Move Type */ +enum hiddf_mouse_move_type { HID_MOUSE_X_AXIS_MV = 0x01, HID_MOUSE_Y_AXIS_MV = 0x02, HID_MOUSE_SCROLL_MV = 0x03 }; + +/** + * \brief Initialize the USB HID Mouse Function Driver + * \return Operation status. + */ +int32_t hiddf_mouse_init(void); + +/** + * \brief Deinitialize the USB HID Mouse Function Driver + * \return Operation status. + */ +int32_t hiddf_mouse_deinit(void); + +/** + * \brief Check whether HID Mouse Function is enabled + * \return Operation status. + * \return true HID Mouse Function is enabled + * \return false HID Mouse Function is disabled + */ +bool hiddf_mouse_is_enabled(void); + +/** + * \brief Move the mouse pointer + * \param pos Signed value to move + * \param type HID mouse class pointer move type + * \return Operation status. + */ +int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type); + +/** + * \brief Changes button state + * \param b_state New button state + * \param type Button type + * \return Operation status. + */ +int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type); + +/** + * \brief Return version + */ +uint32_t hiddf_mouse_get_version(void); + +#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/hid/usb_protocol_hid.h b/atmel-samd/asf4/samd21/usb/class/hid/usb_protocol_hid.h new file mode 100644 index 0000000000000..71d74e632d30f --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hid/usb_protocol_hid.h @@ -0,0 +1,597 @@ +/** + * \file + * + * \brief USB Human Interface Device (HID) protocol definitions. + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _USB_PROTOCOL_HID_H_ +#define _USB_PROTOCOL_HID_H_ + +#include "usb_includes.h" + +/** + * \ingroup usb_protocol_group + * \defgroup usb_hid_protocol USB Human Interface Device (HID) + * protocol definitions + * \brief USB Human Interface Device (HID) protocol definitions + * + * @{ + */ + +//! \name Possible Class value +//@{ +#define HID_CLASS 0x03 +//@} + +//! \name Possible SubClass value +//@{ +//! Interface subclass NO support BOOT protocol +#define HID_SUB_CLASS_NOBOOT 0x00 +//! Interface subclass support BOOT protocol +#define HID_SUB_CLASS_BOOT 0x01 +//@} + +//! \name Possible protocol value +//@{ +//! Protocol generic standard +#define HID_PROTOCOL_GENERIC 0x00 +//! Protocol keyboard standard +#define HID_PROTOCOL_KEYBOARD 0x01 +//! Protocol mouse standard +#define HID_PROTOCOL_MOUSE 0x02 +//@} + +//! \brief Hid USB requests (bRequest) + +#define USB_REQ_HID_GET_REPORT 0x01 +#define USB_REQ_HID_GET_IDLE 0x02 +#define USB_REQ_HID_GET_PROTOCOL 0x03 +#define USB_REQ_HID_SET_REPORT 0x09 +#define USB_REQ_HID_SET_IDLE 0x0A +#define USB_REQ_HID_SET_PROTOCOL 0x0B + +//! \brief HID USB descriptor types +#define USB_DT_HID 0x21 +#define USB_DT_HID_REPORT 0x22 +#define USB_DT_HID_PHYSICAL 0x23 + +//! \brief HID Type for report descriptor +#define USB_HID_ITEM_REPORT_TYPE_MAIN 0 +#define USB_HID_ITEM_REPORT_TYPE_GLOBAL 1 +#define USB_HID_ITEM_REPORT_TYPE_LOCAL 2 +#define USB_HID_ITEM_REPORT_TYPE_LONG 3 + +//! \brief HID report type +#define USB_HID_REPORT_TYPE_INPUT 1 +#define USB_HID_REPORT_TYPE_OUTPUT 2 +#define USB_HID_REPORT_TYPE_FEATURE 3 + +//! \brief HID protocol +#define USB_HID_PROCOTOL_BOOT 0 +#define USB_HID_PROCOTOL_REPORT 1 + +#define USB_HID_DESC_BYTES(bLength, bCountryCode, bNumDescriptors, bDescriptorType, bDescriptorLength) \ + bLength, 0x21, 0x10, 0x01, bCountryCode, bNumDescriptors, bDescriptorType, LE_BYTE0(bDescriptorLength), \ + LE_BYTE1(bDescriptorLength) + +COMPILER_PACK_SET(1) + +//! \brief HID Descriptor +typedef struct usb_hid_descriptor { + uint8_t bLength; //!< Size of this descriptor in bytes + uint8_t bDescriptorType; //!< HID descriptor type + le16_t bcdHID; //!< Binary Coded Decimal Spec. release + uint8_t bCountryCode; //!< Hardware target country + uint8_t bNumDescriptors; //!< Number of HID class descriptors to follow + uint8_t bRDescriptorType; //!< Report descriptor type + le16_t wDescriptorLength; //!< Total length of Report descriptor +} usb_hid_descriptor_t; + +COMPILER_PACK_RESET() + +//! \name HID Report type +//! Used by SETUP_HID_GET_REPORT & SETUP_HID_SET_REPORT +//! @{ +#define REPORT_TYPE_INPUT 0x01 +#define REPORT_TYPE_OUTPUT 0x02 +#define REPORT_TYPE_FEATURE 0x03 +//! @} + +//! \name Constants of field DESCRIPTOR_HID +//! @{ +//! Numeric expression identifying the HID Class +//! Specification release (here V1.11) +#define USB_HID_BDC_V1_11 0x0111 +//! Numeric expression specifying the number of class descriptors +//! Note: Always at least one i.e. Report descriptor. +#define USB_HID_NUM_DESC 0x01 + +//! \name Country code +//! @{ +#define USB_HID_NO_COUNTRY_CODE 0 // Not Supported +#define USB_HID_COUNTRY_ARABIC 1 // Arabic +#define USB_HID_COUNTRY_BELGIAN 2 // Belgian +#define USB_HID_COUNTRY_CANADIAN_BILINGUAL 3 // Canadian-Bilingual +#define USB_HID_COUNTRY_CANADIAN_FRENCH 4 // Canadian-French +#define USB_HID_COUNTRY_CZECH_REPUBLIC 5 // Czech Republic +#define USB_HID_COUNTRY_DANISH 6 // Danish +#define USB_HID_COUNTRY_FINNISH 7 // Finnish +#define USB_HID_COUNTRY_FRENCH 8 // French +#define USB_HID_COUNTRY_GERMAN 9 // German +#define USB_HID_COUNTRY_GREEK 10 // Greek +#define USB_HID_COUNTRY_HEBREW 11 // Hebrew +#define USB_HID_COUNTRY_HUNGARY 12 // Hungary +#define USB_HID_COUNTRY_INTERNATIONAL_ISO 13 // International (ISO) +#define USB_HID_COUNTRY_ITALIAN 14 // Italian +#define USB_HID_COUNTRY_JAPAN_KATAKANA 15 // Japan (Katakana) +#define USB_HID_COUNTRY_KOREAN 16 // Korean +#define USB_HID_COUNTRY_LATIN_AMERICAN 17 // Latin American +#define USB_HID_COUNTRY_NETHERLANDS_DUTCH 18 // Netherlands/Dutch +#define USB_HID_COUNTRY_NORWEGIAN 19 // Norwegian +#define USB_HID_COUNTRY_PERSIAN_FARSI 20 // Persian (Farsi) +#define USB_HID_COUNTRY_POLAND 21 // Poland +#define USB_HID_COUNTRY_PORTUGUESE 22 // Portuguese +#define USB_HID_COUNTRY_RUSSIA 23 // Russia +#define USB_HID_COUNTRY_SLOVAKIA 24 // Slovakia +#define USB_HID_COUNTRY_SPANISH 25 // Spanish +#define USB_HID_COUNTRY_SWEDISH 26 // Swedish +#define USB_HID_COUNTRY_SWISS_FRENCH 27 // Swiss/French +#define USB_HID_COUNTRY_SWISS_GERMAN 28 // Swiss/German +#define USB_HID_COUNTRY_SWITZERLAND 29 // Switzerland +#define USB_HID_COUNTRY_TAIWAN 30 // Taiwan +#define USB_HID_COUNTRY_TURKISH_Q 31 // Turkish-Q +#define USB_HID_COUNTRY_UK 32 // UK +#define USB_HID_COUNTRY_US 33 // US +#define USB_HID_COUNTRY_YUGOSLAVIA 34 // Yugoslavia +#define USB_HID_COUNTRY_TURKISH_F 35 // Turkish-F + //! @} + //! @} +//! @} + +//! \name HID KEYS values +//! @{ +#define HID_A 0x04 +#define HID_B 0x05 +#define HID_C 0x06 +#define HID_D 0x07 +#define HID_E 0x08 +#define HID_F 0x09 +#define HID_G 0x0A +#define HID_H 0x0B +#define HID_I 0x0C +#define HID_J 0x0D +#define HID_K 0x0E +#define HID_L 0x0F +#define HID_M 0x10 +#define HID_N 0x11 +#define HID_O 0x12 +#define HID_P 0x13 +#define HID_Q 0x14 +#define HID_R 0x15 +#define HID_S 0x16 +#define HID_T 0x17 +#define HID_U 0x18 +#define HID_V 0x19 +#define HID_W 0x1A +#define HID_X 0x1B +#define HID_Y 0x1C +#define HID_Z 0x1D +#define HID_1 30 +#define HID_2 31 +#define HID_3 32 +#define HID_4 33 +#define HID_5 34 +#define HID_6 35 +#define HID_7 36 +#define HID_8 37 +#define HID_9 38 +#define HID_0 39 +#define HID_ENTER 40 +#define HID_ESCAPE 41 +#define HID_BACKSPACE 42 +#define HID_TAB 43 +#define HID_SPACEBAR 44 +#define HID_UNDERSCORE 45 +#define HID_PLUS 46 +#define HID_OPEN_BRACKET 47 // { +#define HID_CLOSE_BRACKET 48 // } +#define HID_BACKSLASH 49 +#define HID_ASH 50 // # ~ +#define HID_COLON 51 // ; : +#define HID_QUOTE 52 // ' " +#define HID_TILDE 53 +#define HID_COMMA 54 +#define HID_DOT 55 +#define HID_SLASH 56 +#define HID_CAPS_LOCK 57 +#define HID_F1 58 +#define HID_F2 59 +#define HID_F3 60 +#define HID_F4 61 +#define HID_F5 62 +#define HID_F6 63 +#define HID_F7 64 +#define HID_F8 65 +#define HID_F9 66 +#define HID_F10 67 +#define HID_F11 68 +#define HID_F12 69 +#define HID_PRINTSCREEN 70 +#define HID_SCROLL_LOCK 71 +#define HID_PAUSE 72 +#define HID_INSERT 73 +#define HID_HOME 74 +#define HID_PAGEUP 75 +#define HID_DELETE 76 +#define HID_END 77 +#define HID_PAGEDOWN 78 +#define HID_RIGHT 79 +#define HID_LEFT 80 +#define HID_DOWN 81 +#define HID_UP 82 +#define HID_KEYPAD_NUM_LOCK 83 +#define HID_KEYPAD_DIVIDE 84 +#define HID_KEYPAD_AT 85 +#define HID_KEYPAD_MULTIPLY 85 +#define HID_KEYPAD_MINUS 86 +#define HID_KEYPAD_PLUS 87 +#define HID_KEYPAD_ENTER 88 +#define HID_KEYPAD_1 89 +#define HID_KEYPAD_2 90 +#define HID_KEYPAD_3 91 +#define HID_KEYPAD_4 92 +#define HID_KEYPAD_5 93 +#define HID_KEYPAD_6 94 +#define HID_KEYPAD_7 95 +#define HID_KEYPAD_8 96 +#define HID_KEYPAD_9 97 +#define HID_KEYPAD_0 98 + +//! \name HID modifier values +//! @{ +#define HID_MODIFIER_NONE 0x00 +#define HID_MODIFIER_LEFT_CTRL 0x01 +#define HID_MODIFIER_LEFT_SHIFT 0x02 +#define HID_MODIFIER_LEFT_ALT 0x04 +#define HID_MODIFIER_LEFT_UI 0x08 +#define HID_MODIFIER_RIGHT_CTRL 0x10 +#define HID_MODIFIER_RIGHT_SHIFT 0x20 +#define HID_MODIFIER_RIGHT_ALT 0x40 +#define HID_MODIFIER_RIGHT_UI 0x80 +//! @} +//! @} + +//! \name HID KEYS LED values +//! @{ +#define HID_LED_NUM_LOCK (1 << 0) +#define HID_LED_CAPS_LOCK (1 << 1) +#define HID_LED_SCROLL_LOCK (1 << 2) +#define HID_LED_COMPOSE (1 << 3) +#define HID_LED_KANA (1 << 4) +//! @} + +/** \name Standard HID mouse definitions from HID spec. example */ +/*@{*/ + +/** \brief Structure for standard HID keyboard modified keys */ +typedef union hid_kbd_modifier { + uint8_t byte; + struct { + uint8_t lctrl : 1; /**< Left Ctrl */ + uint8_t lshift : 1; /**< Left Shift */ + uint8_t lalt : 1; /**< Left Alt */ + uint8_t lgui : 1; /**< Left Gui */ + uint8_t rctrl : 1; /**< Right Ctrl */ + uint8_t rshift : 1; /**< Right Shift */ + uint8_t ralt : 1; /**< Right Alt */ + uint8_t rgui : 1; /**< Right Gui */ + } bm; +} hid_kbd_modifier_t; +#define HID_KBD_L_CTRL (1 << 0) /**< Left Ctrl */ +#define HID_KBD_L_SHIFT (1 << 1) /**< Left Shift */ +#define HID_KBD_L_ALT (1 << 2) /**< Left Alt */ +#define HID_KBD_L_GUI (1 << 3) /**< Left Gui */ +#define HID_KBD_R_CTRL (1 << 4) /**< Right Ctrl */ +#define HID_KBD_R_SHIFT (1 << 5) /**< Right Shift */ +#define HID_KBD_R_ALT (1 << 6) /**< Right Alt */ +#define HID_KBD_R_GUI (1 << 7) /**< Right Gui */ + +/** \brief Structure for standard HID keyboard input report */ +typedef union hid_kbd_input_report { + uint8_t byte[8]; + struct { + union hid_kbd_modifier modifier; + uint8_t reserved_oem; + uint8_t key[6]; /** < Key array */ + } field; +} hid_kbd_input_report_t; +/** Access to the modifier keys in HID keyboard report + * \param rpt Pointer to report data of bytes + */ +#define hid_kbd_modifier_keys(rpt) (rpt[0]) +/** Access to the OEM reserved in HID keyboard report + * \param rpt Pointer to report data of bytes + */ +#define hid_kbd_oem(rpt) (rpt[1]) +/** Access to the Key code in HID keyboard report + * \param rpt Pointer to report data of bytes + * \param i Index in the report key array (0~n) + */ +#define hid_kbd_keycode(rpt, i) (rpt[2 + i]) + +/** \brief Structure for standard HID keyboard output report */ +typedef union hid_kbd_output_report { + uint8_t byte; + struct { + uint8_t num_lock : 1; /**< LED of Num Lock */ + uint8_t caps_lock : 1; /**< LED of Caps Lock */ + uint8_t scroll_lock : 1; /**< LED of Scroll Lock */ + uint8_t compose : 1; /**< LED of COMPOSE LOCK */ + uint8_t kana : 1; /**< LED of KANA */ + uint8_t constant : 3; + } field; +} hid_kbd_output_report_t; +#define HID_KBD_NUM_LOCK (1 << 0) /**< LED of Num Lock */ +#define HID_KBD_CAPS_LOCK (1 << 1) /**< LED of Caps Lock */ +#define HID_KBD_SCROLL_LOCK (1 << 2) /**< LED of Scroll Lock */ +#define HID_KBD_COMPOSE (1 << 3) /**< LED of COMPOSE LOCK */ +#define HID_KBD_KANA (1 << 4) /**< LED of KANA */ + +/*@}*/ + +/** \name Standard HID mouse definitions from HID spec. example */ +/*@{*/ +/** \brief Structure for standard HID mouse report */ +typedef union hid_mouse_report { + uint8_t byte[3]; + struct { + uint8_t btn1 : 1; /**< Button 1 */ + uint8_t btn2 : 2; /**< Button 2 */ + uint8_t btn3 : 3; /**< Button 3 */ + uint8_t device_spec : 5; + int8_t x; /**< X displacement */ + int8_t y; /**< Y displacement */ + } field; + /* More bytes are optional */ +} hid_mouse_report_t; +#define HID_MOUSE_BTN1 (1 << 0) /**< Button 1 */ +#define HID_MOUSE_BTN2 (1 << 1) /**< Button 2 */ +#define HID_MOUSE_BTN3 (1 << 2) /**< Button 3 */ + +/** Access to the button state in HID mouse report + * \param rpt Pointer to report data of bytes + */ +#define hid_mouse_btn_state(rpt) (rpt[0]) +/** Check if the button is done in HID mouse report + * \param rpt Pointer to report data of bytes + * \param btn Button bitmap to check + */ +#define hid_mouse_is_btn_down(rpt, btn) (rpt[0] & (btn)) +/** Access to the relative X displacement in HID mouse report + * \param rpt Pointer to report data of bytes + */ +#define hid_mouse_x(rpt) ((int8_t)rpt[1]) +/** Access to the relative Y displacement in HID mouse report + * \param rpt Pointer to report data of bytes + */ +#define hid_mouse_y(rpt) ((int8_t)rpt[2]) + +/*@}*/ + +/** \name Standard HID joystick definitions from HID spec. example */ +/*@{*/ + +/** \brief Structure for standard HID joystick report */ +typedef union hid_joystick_report { + uint8_t byte[4]; + struct { + int8_t x; + int8_t y; + uint8_t hat_sw : 4; /**< Hat switch */ + uint8_t btn1 : 1; /**< Button 1 */ + uint8_t btn2 : 1; /**< Button 2 */ + uint8_t btn3 : 1; /**< Button 3 */ + uint8_t btn4 : 1; /**< Button 4 */ + uint8_t throttle; + } field; +} hid_joystick_report_t; +#define HID_JOYSTICK_BTN1 (1 << 4) /**< Button 1 */ +#define HID_JOYSTICK_BTN2 (1 << 5) /**< Button 2 */ +#define HID_JOYSTICK_BTN3 (1 << 6) /**< Button 3 */ +#define HID_JOYSTICK_BTN4 (1 << 7) /**< Button 4 */ + +/** Access to the absolute X position in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_x(rpt) ((int8_t)rpt[0]) +/** Access to the absolute Y position in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_y(rpt) ((int8_t)rpt[1]) +/** Access to the button state in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_btn_state(rpt) (rpt[2]) +/** Check if the button is done in HID joystick report + * \param rpt Pointer to report data of bytes + * \param btn Button bitmap to check + */ +#define hid_joystick_is_btn_down(rpt, btn) (rpt[2] & (btn)) +/** Get the Hat switch in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_hat_sw(rpt) (rpt[2] & 0xF) +/** Access to the throttle in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_throttle(rpt) (rpt[3]) + +/*@}*/ + +/** + * \brief Fill a GetHIDDescriptor request + * \param[out] req Pointer to the request to fill + * \param[in] type Descriptor type + * \param[in] index Descriptor index + * \param[in] iface Interface Number + * \param[in] len Descriptor Length + */ +static inline void usb_fill_GetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, + uint16_t len) +{ + req->bmRequestType = 0x81; + req->bRequest = USB_REQ_GET_DESC; + req->wValue = (type << 8) | index; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a SetHIDDescriptor request + * \param[out] req Pointer to the request to fill + * \param[in] type Descriptor type + * \param[in] index Descriptor index + * \param[in] iface Interface Number + * \param[in] len Descriptor Length + */ +static inline void usb_fill_SetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, + uint16_t len) +{ + req->bmRequestType = 0x01; + req->bRequest = USB_REQ_SET_DESC; + req->wValue = (type << 8) | index; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a GetReport request + * \param[out] req Pointer to the request to fill + * \param[in] type Report type + * \param[in] id Report ID + * \param[in] iface Interface Number + * \param[in] len Report Length + */ +static inline void usb_fill_GetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_HID_GET_REPORT; + req->wValue = (type << 8) | id; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a SetReport request + * \param[out] req Pointer to the request to fill + * \param[in] type Report type + * \param[in] id Report ID + * \param[in] iface Interface Number + * \param[in] len Report Length + */ +static inline void usb_fill_SetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_HID_GET_REPORT; + req->wValue = (type << 8) | id; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a GetIdle request + * \param[out] req Pointer to the request to fill + * \param[in] id Report ID + * \param[in] iface Interface Number + */ +static inline void usb_fill_GetIdle_req(struct usb_req *req, uint8_t id, uint8_t iface) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_HID_GET_IDLE; + req->wValue = id; + req->wIndex = iface; + req->wLength = 1; +} + +/** + * \brief Fill a SetIdle request + * \param[out] req Pointer to the request to fill + * \param[in] duration Duration value + * \param[in] id Report ID + * \param[in] iface Interface Number + */ +static inline void usb_fill_SetIdle_req(struct usb_req *req, uint8_t duration, uint8_t id, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_HID_SET_IDLE; + req->wValue = (duration << 8) | id; + req->wIndex = iface; + req->wLength = 0; +} + +/** + * \brief Fill a GetProtocol request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_GetProtocol_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_HID_GET_PROTOCOL; + req->wValue = 0; + req->wIndex = iface; + req->wLength = 1; +} + +/** + * \brief Fill a SetProtocol request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_SetProtocol_req(struct usb_req *req, uint8_t protocol, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_HID_SET_PROTOCOL; + req->wValue = protocol; + req->wIndex = iface; + req->wLength = 0; +} + +#endif // _USB_PROTOCOL_HID_H_ diff --git a/atmel-samd/asf4/samd21/usb/class/hub/usb_protocol_hub.h b/atmel-samd/asf4/samd21/usb/class/hub/usb_protocol_hub.h new file mode 100644 index 0000000000000..dbfc04a2cbb3a --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/hub/usb_protocol_hub.h @@ -0,0 +1,364 @@ +/** + * \file + * + * \brief USB hub protocol definitions. + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _USB_PROTOCOL_HUB_H_ +#define _USB_PROTOCOL_HUB_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \name Possible class value */ +/*@{*/ +#define HUB_CLASS 0x09 +/*@}*/ + +/** \brief Hub USB requests (bRequest) */ +enum usb_reqid_hub { + USB_REQ_HUB_GET_STATUS = 0, + /** CLEAR_FEATURE */ + USB_REQ_HUB_CLR_FTR = 1, + /** SET_FEATURE */ + USB_REQ_HUB_SET_FTR = 3, + /** GET_DESCRIPTOR */ + USB_REQ_HUB_GET_DESC = 6, + /** SET_DESCRIPTOR */ + USB_REQ_HUB_SET_DESC = 7, + /** CLEAR_TT_BUFFER */ + USB_REQ_HUB_CLR_TT_BUF = 8, + /** RESET_TT */ + USB_REQ_HUB_RESET_TT = 9, + /** GET_TT_STATE */ + USB_REQ_HUB_GET_TT_STATE = 10, + /** STOP_TT */ + USB_REQ_HUB_STOP_TT +}; + +/** \brief Hub USB descriptor type */ +enum usb_descriptor_type_hub { USB_DT_HUB = 0x29 }; + +/** \brief Hub feature selector */ +enum usb_hub_ftr_sel { + USB_HUB_FTR_C_HUB_LOCAL_POWER = 0, + USB_HUB_FTR_C_HUB_OVER_CURRENT = 1, + USB_HUB_FTR_PORT_CONNECTION = 0, + USB_HUB_FTR_PORT_ENABLE = 1, + USB_HUB_FTR_PORT_SUSPEND = 2, + USB_HUB_FTR_PORT_OVER_CURRENT = 3, + USB_HUB_FTR_PORT_RESET = 4, + USB_HUB_FTR_PORT_POWER = 8, + USB_HUB_FTR_PORT_LOW_SPEED = 9, + USB_HUB_FTR_PORT_LS = 9, + USB_HUB_FTR_PORT_HIGH_SPEED = 10, + USB_HUB_FTR_PORT_HS = 10, + USB_HUB_FTR_C_PORT_CONNECTION = 16, + USB_HUB_FTR_C_PORT_ENABLE = 17, + USB_HUB_FTR_C_PORT_SUSPEND = 18, + USB_HUB_FTR_C_PORT_OVER_CURRENT = 19, + USB_HUB_FTR_C_PORT_RESET = 20, + USB_HUB_FTR_PORT_TEST = 21, + USB_HUB_FTR_PORT_INDICATOR +}; + +COMPILER_PACK_SET(1) + +/** + * \brief General Hub Descriptor + */ +typedef struct usb_hub_descriptor { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint32_t variables[1]; +} usb_hub_descriptor_t; + +/** + * \brief Hub Descriptor with no more than 7 ports + */ +typedef struct usb_hub_descriptor_7p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[1]; + uint8_t PortPwrCtrlMask[1]; +} usb_hub_descriptor_7p_t; + +/** + * \brief Hub Descriptor with no more than 15 ports + */ +typedef struct usb_hub_descriptor_15p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[2]; + uint8_t PortPwrCtrlMask[2]; +} usb_hub_descriptor_15p_t; + +/** + * \brief Hub Descriptor with no more than 23 ports + */ +typedef struct usb_hub_descriptor_23p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[3]; + uint8_t PortPwrCtrlMask[3]; +} usb_hub_descriptor_23p_t; + +/** + * \brief Hub Descriptor with no more than 31 ports + */ +typedef struct usb_hub_descriptor_31p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[4]; + uint8_t PortPwrCtrlMask[4]; +} usb_hub_descriptor_31p_t; + +COMPILER_PACK_RESET() + +/** + * \brief Check if hub change is detected + * \param[in] bitmap Pointer to the bitmap location + * \return \c true if hub change is detected + */ +static inline bool usb_is_hub_change_detected(const uint8_t *bitmap) +{ + return (*bitmap & 0x1); +} + +/** + * \brief Check if port change is detected + * \param[in] bitmap Pointer to the bitmap location + * \param[in] port Port number ( 1 ~ n ) + * \return \c true if port change is detected + */ +static inline bool usb_is_port_change_detected(const uint8_t *bitmap, const uint8_t port) +{ + uint8_t idx = port >> 3; + uint8_t pos = port & 0x7; + return (bitmap[idx] & (1u << pos)); +} + +/** + * \brief Fill a ClearHubFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + */ +static inline void usb_fill_ClrHubFtr_req(struct usb_req *req, uint8_t ftr) +{ + req->bmRequestType = 0x20; + req->bRequest = USB_REQ_CLEAR_FTR; + req->wValue = ftr; + req->wIndex = 0; + req->wLength = 0; +} + +/** + * \brief Fill a ClearPortFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_ClrPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_CLEAR_FTR; + req->wValue = ftr; + req->wIndex = port; + req->wLength = 0; +} + +/** + * \brief Fill a ClearTTBuffer request + * \param[out] req Pointer to the request to fill + * \param[in] dev Dev_Addr + * \param[in] ep EP_Num + * \param[in] tt_port TT_port + */ +static inline void usb_fill_ClrTTBuf_req(struct usb_req *req, uint8_t dev, uint8_t ep, uint8_t tt_port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_HUB_CLR_TT_BUF; + req->wValue = (dev << 8) | ep; + req->wIndex = tt_port; + req->wLength = 0; +} + +/** + * \brief Fill a GetHubDescriptor request + * \param[out] req Pointer to the request to fill + * \param[in] len Length of available buffer for request data + */ +static inline void usb_fill_GetHubDesc_req(struct usb_req *req, uint16_t len) +{ + req->bmRequestType = 0xA0; + req->bRequest = USB_REQ_GET_DESC; + req->wValue = (USB_DT_HUB << 8) | 0; + req->wIndex = 0; + req->wLength = len; +} + +/** + * \brief Fill a GetHubStatus request + * \param[out] req Pointer to the request to fill + */ +static inline void usb_fill_GetHubStatus_req(struct usb_req *req) +{ + req->bmRequestType = 0xA0; + req->bRequest = USB_REQ_GET_STATUS; + req->wValue = 0; + req->wIndex = 0; + req->wLength = 4; +} + +/** + * \brief Fill a GetPortStatus request + * \param[out] req Pointer to the request to fill + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_GetPortStatus_req(struct usb_req *req, uint8_t port) +{ + req->bmRequestType = 0xA3; + req->bRequest = USB_REQ_GET_STATUS; + req->wValue = 0; + req->wIndex = port; + req->wLength = 4; +} + +/** + * \brief Fill a ResetTT request + * \param[out] req Pointer to the request to fill + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_ResetTT_req(struct usb_req *req, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_HUB_RESET_TT; + req->wValue = 0; + req->wIndex = port; + req->wLength = 0; +} + +/** + * \brief Fill a SetHubFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + */ +static inline void usb_fill_SetHubFtr_req(struct usb_req *req, uint8_t ftr) +{ + req->bmRequestType = 0x20; + req->bRequest = USB_REQ_SET_FTR; + req->wValue = ftr; + req->wIndex = 0; + req->wLength = 0; +} + +/** + * \brief Fill a SetPortFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_SetPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_SET_FTR; + req->wValue = ftr; + req->wIndex = port; + req->wLength = 0; +} + +/** + * \brief Fill a GetTTState request + * \param[out] req Pointer to the request to fill + * \param[in] tt_flags TT_Flags + * \param[in] port Port number ( 1 ~ n ) + * \param[in] len TT State Length + */ +static inline void usb_fill_GetTTState_req(struct usb_req *req, uint16_t tt_flags, uint8_t port, uint16_t len) +{ + req->bmRequestType = 0xA3; + req->bRequest = USB_REQ_HUB_GET_TT_STATE; + req->wValue = tt_flags; + req->wIndex = port; + req->wLength = len; +} + +/** + * \brief Fill a StopTT request + * \param[out] req Pointer to the request to fill + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_StopTT_req(struct usb_req *req, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_HUB_STOP_TT; + req->wValue = 0; + req->wIndex = port; + req->wLength = 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _USB_PROTOCOL_HUB_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/msc/sbc_protocol.h b/atmel-samd/asf4/samd21/usb/class/msc/sbc_protocol.h new file mode 100644 index 0000000000000..9259335228d0c --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/msc/sbc_protocol.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SCSI Block Commands + * + * This file contains definitions of some of the commands found in the + * SCSI SBC-2 standard. + * + * Note that the SBC specification depends on several commands defined + * by the SCSI Primary Commands (SPC) standard. Each version of the SBC + * standard is meant to be used in conjunction with a specific version + * of the SPC standard, as follows: + * - SBC depends on SPC + * - SBC-2 depends on SPC-3 + * - SBC-3 depends on SPC-4 + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _SBC_PROTOCOL_H_ +#define _SBC_PROTOCOL_H_ + +/** + * \ingroup usb_msc_protocol + * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions + * + * @{ + */ + +/** \name SCSI commands defined by SBC-2 */ +#define SBC_FORMAT_UNIT 0x04 +#define SBC_READ6 0x08 +#define SBC_WRITE6 0x0A +#define SBC_START_STOP_UNIT 0x1B +#define SBC_READ_CAPACITY10 0x25 +#define SBC_READ10 0x28 +#define SBC_WRITE10 0x2A +#define SBC_VERIFY10 0x2F + +/** \name SBC-2 Mode page definitions */ +enum scsi_sbc_mode { + SCSI_MS_MODE_RW_ERR_RECOV = 0x01, /**< Read-Write Error Recovery mode page */ + SCSI_MS_MODE_FORMAT_DEVICE = 0x03, /**< Format Device mode page */ + SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, /**< Flexible Disk mode page */ + SCSI_MS_MODE_CACHING = 0x08 +}; + +/** \name SBC-2 Device-Specific Parameter */ +#define SCSI_MS_SBC_WP 0x80 /**< Write Protected */ +#define SCSI_MS_SBC_DPOFUA 0x10 /**< DPO and FUA supported */ + +/** + * \brief SBC-2 Short LBA mode parameter block descriptor + * \note Fields are MSB first (BE) + */ +struct sbc_slba_block_desc { + be32_t nr_blocks; /**< Number of Blocks (BE32) */ + be32_t block_len; /**< Block Length (BE32) */ +#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU /**< Mask reserved bits */ +}; + +/** + * \brief SBC-2 Caching mode page + * \note Fields are MSB first (BE) + */ +struct sbc_caching_mode_page { + uint8_t page_code; + uint8_t page_length; + uint8_t flags2; +#define SBC_MP_CACHE_IC (1 << 7) /**< Initiator Control */ +#define SBC_MP_CACHE_ABPF (1 << 6) /**< Abort Pre-Fetch */ +#define SBC_MP_CACHE_CAP (1 << 5) /**< Catching Analysis Permitted */ +#define SBC_MP_CACHE_DISC (1 << 4) /**< Discontinuity */ +#define SBC_MP_CACHE_SIZE (1 << 3) /**< Size enable */ +#define SBC_MP_CACHE_WCE (1 << 2) /**< Write back Cache Enable */ +#define SBC_MP_CACHE_MF (1 << 1) /**< Multiplication Factor */ +#define SBC_MP_CACHE_RCD (1 << 0) /**< Read Cache Disable */ + uint8_t retention; + be16_t dis_pf_transfer_len; + be16_t min_prefetch; + be16_t max_prefetch; + be16_t max_prefetch_ceil; + uint8_t flags12; +#define SBC_MP_CACHE_FSW (1 << 7) /**< Force Sequential Write */ +#define SBC_MP_CACHE_LBCSS (1 << 6) /**< Logical Blk Cache Seg Sz */ +#define SBC_MP_CACHE_DRA (1 << 5) /**< Disable Read-Ahead */ +#define SBC_MP_CACHE_NV_DIS (1 << 0) /**< Non-Volatile Cache Disable */ + uint8_t nr_cache_segments; + be16_t cache_segment_size; + uint8_t reserved[4]; +}; + +/** + * \brief SBC-2 Read-Write Error Recovery mode page + * \note Fields are MSB first (BE) + */ +struct sbc_rdwr_error_recovery_mode_page { + uint8_t page_code; + uint8_t page_length; +#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A + uint8_t flags1; +#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7) +#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6) +#define SBC_MP_RW_ERR_RECOV_TB (1 << 5) +#define SBC_MP_RW_ERR_RECOV_RC (1 << 4) +#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3) +#define SBC_MP_RW_ERR_RECOV_PER (1 << 2) +#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1) +#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0) + uint8_t read_retry_count; + uint8_t correction_span; + uint8_t head_offset_count; + uint8_t data_strobe_offset_count; + uint8_t flags2; + uint8_t write_retry_count; + uint8_t flags3; + be16_t recovery_time_limit; +}; + +/** + * \brief SBC-2 READ CAPACITY (10) parameter data (8 bytes) + * \note Fields are MSB first (BE) + */ +struct sbc_read_capacity10_data { + be32_t max_lba; /**< LBA of last logical block (BE32) */ + be32_t block_len; /**< Number of bytes in the last logical block (BE32) */ +}; + +#endif /*_SBC_PROTOCOL_H_*/ diff --git a/atmel-samd/asf4/samd21/usb/class/msc/spc_protocol.h b/atmel-samd/asf4/samd21/usb/class/msc/spc_protocol.h new file mode 100644 index 0000000000000..c44cbef32bd02 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/msc/spc_protocol.h @@ -0,0 +1,340 @@ +/** + * \file + * + * \brief SCSI Primary Commands + * + * This file contains definitions of some of the commands found in the + * SPC-2 standard. + * + * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _SPC_PROTOCOL_H_ +#define _SPC_PROTOCOL_H_ + +/** + * \ingroup usb_msc_protocol + * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions + * + * + */ + +/**< \name SCSI commands defined by SPC-2 */ +#define SPC_TEST_UNIT_READY 0x00 +#define SPC_REQUEST_SENSE 0x03 +#define SPC_INQUIRY 0x12 +#define SPC_MODE_SELECT6 0x15 +#define SPC_MODE_SENSE6 0x1A +#define SPC_SEND_DIAGNOSTIC 0x1D +#define SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +#define SPC_MODE_SENSE10 0x5A +#define SPC_REPORT_LUNS 0xA0 + +/**< \brief May be set in byte 0 of the INQUIRY CDB */ +/**< Enable Vital Product Data */ +#define SCSI_INQ_REQ_EVPD 0x01 +/**< Command Support Data specified by the PAGE OR OPERATION CODE field */ +#define SCSI_INQ_REQ_CMDT 0x02 + +COMPILER_PACK_SET(1) + +/** + * \brief SCSI Standard Inquiry data structure + */ +struct scsi_inquiry_data { + uint8_t pq_pdt; /**< Peripheral Qual / Peripheral Dev Type */ +#define SCSI_INQ_PQ_CONNECTED 0x00 /**< Peripheral connected */ +#define SCSI_INQ_PQ_NOT_CONN 0x20 /**< Peripheral not connected */ +#define SCSI_INQ_PQ_NOT_SUPP 0x60 /**< Peripheral not supported */ +#define SCSI_INQ_DT_DIR_ACCESS 0x00 /**< Direct Access (SBC) */ +#define SCSI_INQ_DT_SEQ_ACCESS 0x01 /**< Sequential Access */ +#define SCSI_INQ_DT_PRINTER 0x02 /**< Printer */ +#define SCSI_INQ_DT_PROCESSOR 0x03 /**< Processor device */ +#define SCSI_INQ_DT_WRITE_ONCE 0x04 /**< Write-once device */ +#define SCSI_INQ_DT_CD_DVD 0x05 /**< CD/DVD device */ +#define SCSI_INQ_DT_OPTICAL 0x07 /**< Optical Memory */ +#define SCSI_INQ_DT_MC 0x08 /**< Medium Changer */ +#define SCSI_INQ_DT_ARRAY 0x0c /**< Storage Array Controller */ +#define SCSI_INQ_DT_ENCLOSURE 0x0d /**< Enclosure Services */ +#define SCSI_INQ_DT_RBC 0x0e /**< Simplified Direct Access */ +#define SCSI_INQ_DT_OCRW 0x0f /**< Optical card reader/writer */ +#define SCSI_INQ_DT_BCC 0x10 /**< Bridge Controller Commands */ +#define SCSI_INQ_DT_OSD 0x11 /**< Object-based Storage */ +#define SCSI_INQ_DT_NONE 0x1f /**< No Peripheral */ + uint8_t flags1; /**< Flags (byte 1) */ +#define SCSI_INQ_RMB 0x80 /**< Removable Medium */ + uint8_t version; /**< Version */ +#define SCSI_INQ_VER_NONE 0x00 /**< No standards conformance */ +#define SCSI_INQ_VER_SPC 0x03 /**< SCSI Primary Commands (link to SBC) */ +#define SCSI_INQ_VER_SPC2 0x04 /**< SCSI Primary Commands - 2 (link to SBC-2) */ +#define SCSI_INQ_VER_SPC3 0x05 /**< SCSI Primary Commands - 3 (link to SBC-2) */ +#define SCSI_INQ_VER_SPC4 0x06 /**< SCSI Primary Commands - 4 (link to SBC-3) */ + uint8_t flags3; /**< Flags (byte 3) */ +#define SCSI_INQ_NORMACA 0x20 /**< Normal ACA Supported */ +#define SCSI_INQ_HISUP 0x10 /**< Hierarchal LUN addressing */ +#define SCSI_INQ_RSP_SPC2 0x02 /**< SPC-2 / SPC-3 response format */ + uint8_t addl_len; /**< Additional Length (n-4) */ +#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) /**< Total length is \a tot */ + uint8_t flags5; /**< Flags (byte 5) */ +#define SCSI_INQ_SCCS 0x80 + uint8_t flags6; /**< Flags (byte 6) */ +#define SCSI_INQ_BQUE 0x80 +#define SCSI_INQ_ENCSERV 0x40 +#define SCSI_INQ_MULTIP 0x10 +#define SCSI_INQ_MCHGR 0x08 +#define SCSI_INQ_ADDR16 0x01 + uint8_t flags7; /**< Flags (byte 7) */ +#define SCSI_INQ_WBUS16 0x20 +#define SCSI_INQ_SYNC 0x10 +#define SCSI_INQ_LINKED 0x08 +#define SCSI_INQ_CMDQUE 0x02 + uint8_t vendor_id[8]; /**< T10 Vendor Identification */ + uint8_t product_id[16]; /**< Product Identification */ + uint8_t product_rev[4]; /**< Product Revision Level */ +}; + +/** + * \brief SCSI Standard Request sense data structure + */ +#define SCSI_SENSE_VALID 0x80 /**< Indicates the INFORMATION field contains valid information */ +#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F +#define SCSI_SENSE_CURRENT 0x70 /**< Response code 70h (current errors) */ +#define SCSI_SENSE_DEFERRED 0x71 + +#define SCSI_SENSE_FILEMARK 0x80 /**< Indicates that the current command has read a filemark or setmark. */ +#define SCSI_SENSE_EOM 0x40 /**< Indicates that an end-of-medium condition exists. */ +#define SCSI_SENSE_ILI \ + 0x20 /**< Indicates that the requested logical block length did not match the logical block length of the data on \ + the medium. */ +#define SCSI_SENSE_RESERVED 0x10 /**< Reserved */ +#define SCSI_SENSE_KEY(x) (x & 0x0F) /**< Sense Key */ + +#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len)-8) + +#define SCSI_SENSE_SKSV 0x80 /**< Indicates the SENSE-KEY SPECIFIC field contains valid information */ + +struct scsi_request_sense_data { + /** 1st byte: REQUEST SENSE response flags*/ + uint8_t valid_reponse_code; + /** 2nd byte */ + uint8_t obsolete; + /** 3rd byte */ + uint8_t sense_flag_key; + /** 4th to 7th bytes - INFORMATION field */ + uint8_t information[4]; + /** 8th byte - ADDITIONAL SENSE LENGTH field */ + uint8_t AddSenseLen; + /** 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */ + uint8_t CmdSpecINFO[4]; + /** 13th to 14th byte - ADDITIONAL SENSE CODE and QUALIFIER field */ + union { + struct { + uint8_t code; /**< ADDITIONAL SENSE CODE (ASC) */ + uint8_t qualifier; /**< ADDITIONAL SENSE CODE QUALIFIER (ASCQ) */ + } add_sense; + be16_t AddSense; /**< ASC | ASCQ */ + }; + /** 15th byte - FIELD REPLACEABLE UNIT CODE field */ + uint8_t FldReplUnitCode; + /** 16th byte */ + uint8_t SenseKeySpec[3]; +}; + +COMPILER_PACK_RESET() + +/**< Vital Product Data page codes */ +enum scsi_vpd_page_code { + SCSI_VPD_SUPPORTED_PAGES = 0x00, + SCSI_VPD_UNIT_SERIAL_NUMBER = 0x80, + SCSI_VPD_DEVICE_IDENTIFICATION = 0x83 +}; +#define SCSI_VPD_HEADER_SIZE 4 + +/**< Constants associated with the Device Identification VPD page */ +#define SCSI_VPD_ID_HEADER_SIZE 4 + +#define SCSI_VPD_CODE_SET_BINARY 1 +#define SCSI_VPD_CODE_SET_ASCII 2 +#define SCSI_VPD_CODE_SET_UTF8 3 + +#define SCSI_VPD_ID_TYPE_T10 1 + +/**< Sense keys */ +enum scsi_sense_key { + SCSI_SK_NO_SENSE = 0x0, + SCSI_SK_RECOVERED_ERROR = 0x1, + SCSI_SK_NOT_READY = 0x2, + SCSI_SK_MEDIUM_ERROR = 0x3, + SCSI_SK_HARDWARE_ERROR = 0x4, + SCSI_SK_ILLEGAL_REQUEST = 0x5, + SCSI_SK_UNIT_ATTENTION = 0x6, + SCSI_SK_DATA_PROTECT = 0x7, + SCSI_SK_BLANK_CHECK = 0x8, + SCSI_SK_VENDOR_SPECIFIC = 0x9, + SCSI_SK_COPY_ABORTED = 0xa, + SCSI_SK_ABORTED_COMMAND = 0xb, + SCSI_SK_VOLUME_OVERFLOW = 0xd, + SCSI_SK_MISCOMPARE = 0xe +}; + +/**< Additional Sense Code | Additional Sense Code Qualifier pairs (BE16) */ +enum scsi_asc_ascq { + SCSI_ASC_NO_ADDITIONAL_SENSE_INFO = 0x0000, + SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405, + SCSI_ASC_WRITE_ERROR = 0x0c00, + SCSI_ASC_UNRECOVERED_READ_ERROR = 0x1100, + SCSI_ASC_INVALID_COMMAND_OPERATION_CODE = 0x2000, + SCSI_ASC_INVALID_FIELD_IN_CDB = 0x2400, + SCSI_ASC_WRITE_PROTECTED = 0x2700, + SCSI_ASC_NOT_READY_TO_READY_CHANGE = 0x2800, + SCSI_ASC_MEDIUM_NOT_PRESENT = 0x3A00, + SCSI_ASC_INTERNAL_TARGET_FAILURE = 0x4400 +}; + +/** + * \brief SPC-2 Mode parameter + * This subclauses describes the block descriptors and the pages + * used with MODE SELECT and MODE SENSE commands + * that are applicable to all SCSI devices. + */ +enum scsi_spc_mode { + SCSI_MS_MODE_VENDOR_SPEC = 0x00, + SCSI_MS_MODE_INFEXP = 0x1C, /**< Informational exceptions control page */ + SCSI_MS_MODE_ALL = 0x3f +}; + +/** + * \brief SPC-2 Informational exceptions control page + * See chapter 8.3.8 + * \note Fields are MSB first (BE) + */ +struct spc_control_page_info_execpt { + uint8_t page_code; + uint8_t page_length; +#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A + uint8_t flags1; +#define SPC_MP_INFEXP_PERF (1 << 7) /**< Initiator Control */ +#define SPC_MP_INFEXP_EBF (1 << 5) /**< Caching Analysis Permitted */ +#define SPC_MP_INFEXP_EWASC (1 << 4) /**< Discontinuity */ +#define SPC_MP_INFEXP_DEXCPT (1 << 3) /**< Size enable */ +#define SPC_MP_INFEXP_TEST (1 << 2) /**< Write-back Cache Enable */ +#define SPC_MP_INFEXP_LOGERR (1 << 0) /**< Log errors bit */ + uint8_t mrie; +#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00 +#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01 +#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02 +#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03 +#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04 +#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05 +#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06 + be32_t interval_timer; + be32_t report_count; +}; + +enum scsi_spc_mode_sense_pc { + SCSI_MS_SENSE_PC_CURRENT = 0, + SCSI_MS_SENSE_PC_CHANGEABLE = 1, + SCSI_MS_SENSE_PC_DEFAULT = 2, + SCSI_MS_SENSE_PC_SAVED = 3 +}; + +/** + * \brief Check whether dbd field is set in sense code + * \param[in] cdb pointer to the sense code block + * \return Operation status. + */ +static inline bool scsi_mode_sense_dbd_is_set(const uint8_t *cdb) +{ + return (cdb[1] >> 3) & 1; +} + +/** + * \brief Get page code from mode sense code + * \param[in] cdb pointer to the sense code block + * \return Operation status. + */ +static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t *cdb) +{ + return cdb[2] & 0x3f; +} + +/** + * \brief Get pc from mode sense code + * \param[in] cdb pointer to the sense code block + * \return Operation status. + */ +static inline uint8_t scsi_mode_sense_get_pc(const uint8_t *cdb) +{ + return cdb[2] >> 6; +} + +/** + * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE SENSE(6) + * \note Fields are MSB first (BE) + */ +struct scsi_mode_param_header6 { + uint8_t mode_data_length; /**< Number of bytes after this */ + uint8_t medium_type; /**< Medium Type */ + uint8_t device_specific_parameter; /**< Defined by command set */ + uint8_t block_descriptor_length; /**< Length of block descriptors */ +}; + +/** + * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE SENSE(10) + * \note Fields are MSB first (BE) + */ +struct scsi_mode_param_header10 { + le16_t mode_data_length; /**< Number of bytes after this */ + uint8_t medium_type; /**< Medium Type */ + uint8_t device_specific_parameter; /**< Defined by command set */ + uint8_t flags4; /**< LONGLBA in bit 0 */ + uint8_t reserved; + le16_t block_descriptor_length; /**< Length of block descriptors */ +}; + +/** + * \brief SCSI Page_0 Mode Page header (SPF not set) + */ +struct scsi_mode_page_0_header { + uint8_t page_code; +#define SCSI_PAGE_CODE_PS (1 << 7) /**< Parameters Savable */ +#define SCSI_PAGE_CODE_SPF (1 << 6) /**< SubPage Format */ + uint8_t page_length; /**< Number of bytes after this */ +#define SCSI_MS_PAGE_LEN(total) ((total)-2) +}; + +#endif /**< SPC_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/msc/usb_protocol_msc.h b/atmel-samd/asf4/samd21/usb/class/msc/usb_protocol_msc.h new file mode 100644 index 0000000000000..f69eae232eb0b --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/msc/usb_protocol_msc.h @@ -0,0 +1,177 @@ +/** + * \file + * + * \brief USB Mass Storage Class (MSC) protocol definitions. + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _USB_PROTOCOL_MSC_H_ +#define _USB_PROTOCOL_MSC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup usb_protocol_group + * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions + * + * @{ + */ + +/** + * \name Possible Class value + */ +//@{ +#define MSC_CLASS 0x08 +//@} + +/** + * \name Possible SubClass value + * \note In practice, most devices should use + * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in + * the standard INQUIRY data block, even if the MSC spec indicates + * otherwise. In particular, RBC is not supported by certain major + * operating systems like Windows XP. + */ +//@{ +#define MSC_SUBCLASS_RBC 0x01 /**< Reduced Block Commands */ +#define MSC_SUBCLASS_ATAPI 0x02 /**< CD/DVD devices */ +#define MSC_SUBCLASS_QIC_157 0x03 /**< Tape devices */ +#define MSC_SUBCLASS_UFI 0x04 /**< Floppy disk drives */ +#define MSC_SUBCLASS_SFF_8070I 0x05 /**< Floppy disk drives */ +#define MSC_SUBCLASS_TRANSPARENT 0x06 /**< Determined by INQUIRY */ + //@} + +/** + * \name Possible protocol value + * \note Only the BULK protocol should be used in new designs. + */ +//@{ +#define MSC_PROTOCOL_CBI 0x00 /**< Command/Bulk/Interrupt */ +#define MSC_PROTOCOL_CBI_ALT 0x01 /**< W/o command completion */ +#define MSC_PROTOCOL_BULK 0x50 /**< Bulk-only */ + //@} + +/** + * \brief MSC USB requests (bRequest) + */ + +#define USB_REQ_MSC_BULK_RESET 0xFF /**< Mass Storage Reset */ +#define USB_REQ_MSC_GET_MAX_LUN 0xFE /**< Get Max LUN */ + +COMPILER_PACK_SET(1) + +/** + * \name A Command Block Wrapper (CBW) + * \note Fields are LSB first (LE) + */ +//@{ +struct usb_msc_cbw { + le32_t dCBWSignature; /**< Must contain 'USBC' (0x43425355, LE32) */ + le32_t dCBWTag; /**< Unique command ID (LE32) */ + le32_t dCBWDataTransferLength; /**< Number of bytes to transfer (LE32) */ + uint8_t bmCBWFlags; /**< Direction in bit 7 */ + uint8_t bCBWLUN; /**< Logical Unit Number */ + uint8_t bCBWCBLength; /**< Number of valid CDB bytes */ + uint8_t CDB[16]; /**< SCSI Command Descriptor Block */ +}; + +#define USB_CBW_SIGNATURE 0x43425355 /**< dCBWSignature value */ +#define USB_CBW_DIRECTION_IN (1 << 7) /**< Data from device to host */ +#define USB_CBW_DIRECTION_OUT (0 << 7) /**< Data from host to device */ +#define USB_CBW_LUN_MASK 0x0F /**< Valid bits in bCBWLUN */ +#define USB_CBW_LEN_MASK 0x1F /**< Valid bits in bCBWCBLength */ + //@} + +/** + * \name A Command Status Wrapper (CSW) + * \note Fields are LSB first (LE) + */ +//@{ +struct usb_msc_csw { + le32_t dCSWSignature; /**< Must contain 'USBS' */ + le32_t dCSWTag; /**< Same as dCBWTag */ + le32_t dCSWDataResidue; /**< Number of bytes not transfered */ + uint8_t bCSWStatus; /**< Status code */ +}; + +#define USB_CSW_SIGNATURE 0x53425355 /**< dCSWSignature value */ +#define USB_CSW_STATUS_PASS 0x00 /**< Command Passed */ +#define USB_CSW_STATUS_FAIL 0x01 /**< Command Failed */ +#define USB_CSW_STATUS_PE 0x02 /**< Phase Error */ +//@} + +COMPILER_PACK_RESET() + +//@} + +/** + * \brief Fill a Bulk-Only Mass Storage Reset request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_BOMSReset_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_MSC_BULK_RESET; + req->wValue = 0; + req->wIndex = iface; + req->wLength = 0; +} + +/** + * \brief Fill a GetMaxLUN request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_GetMaxLUN_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_MSC_GET_MAX_LUN; + req->wValue = 0; + req->wIndex = iface; + req->wLength = 1; +} + +#ifdef __cplusplus +} +#endif + +#endif // _USB_PROTOCOL_MSC_H_ diff --git a/atmel-samd/asf4/samd21/usb/class/vendor/usb_protocol_vendor.h b/atmel-samd/asf4/samd21/usb/class/vendor/usb_protocol_vendor.h new file mode 100644 index 0000000000000..e865fb808e7bc --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/class/vendor/usb_protocol_vendor.h @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief USB Vendor class protocol definitions. + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _USB_PROTOCOL_VENDOR_H_ +#define _USB_PROTOCOL_VENDOR_H_ + +/** + * \ingroup usb_protocol_group + * \defgroup usb_vendor_protocol USB Vendor Class definitions + * + */ + +/** + * \name Vendor class values + */ +#define VENDOR_CLASS 0xFF +#define VENDOR_SUBCLASS 0xFF +#define VENDOR_PROTOCOL 0xFF + +#endif /* _USB_PROTOCOL_VENDOR_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/device/usbdc.c b/atmel-samd/asf4/samd21/usb/device/usbdc.c new file mode 100644 index 0000000000000..f5243cad03196 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/device/usbdc.c @@ -0,0 +1,836 @@ +/** + * \file + * + * \brief USB Device Stack Core Layer Implementation. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "usbdc.h" + +#define USBDC_VERSION 0x00000001u + +/** + * \brief USB Device Core Sof Handler + */ +struct usbdc_sof_handler { + struct usbdc_sof_handler *next; + usbdc_sof_cb_t cb; +}; + +/** + * \brief USB Device Core Request Handler + */ +struct usbdc_req_handler { + struct usbdc_req_handler *next; + usbdc_req_cb_t cb; +}; + +/** + * \brief USB Device Core Change Handler + */ +struct usbdc_change_handler { + struct usbdc_change_handler *next; + usbdc_change_cb_t cb; +}; + +/** + * \brief USB Device Core Handler + */ +struct usbdc_handlers { + struct list_descriptor sof_list; + struct list_descriptor req_list; + struct list_descriptor change_list; +}; + +/** + * \brief USB Device Core Driver Structure + */ +struct usbdc_driver { + /** Pointer to descriptions of descriptors. */ + struct usbdc_descriptors desces; + /** Callback handlers. */ + struct usbdc_handlers handlers; + /** list of function drivers. */ + struct list_descriptor func_list; + /** Control buffer. */ + uint8_t *ctrl_buf; + /** Device status. */ + uint16_t status; + /** Device state. */ + uint8_t state; + /** Configuration value. */ + uint8_t cfg_value; + /** Control endpoint size. */ + uint8_t ctrl_size; +}; + +/** + * \brief USB Device Core Driver Instance + */ +static struct usbdc_driver usbdc; + +/** + * \brief Process the GetDescriptor request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_desc_req(const uint8_t ep, struct usb_req *req) +{ + uint8_t *cfg_desc, *str_desc; + uint16_t total_len; + uint16_t length = req->wLength; + uint8_t type = (uint8_t)(req->wValue >> 8); + uint8_t index = req->wValue & 0x00FF; + bool need_zlp = !(length & (usbdc.ctrl_size - 1)); + + switch (type) { + case USB_DT_DEVICE: + if (length > 0x12) { + length = 0x12; + } + usbdc_xfer(ep, usbdc.desces.ls_fs->sod, length, false); + return true; + case USB_DT_CONFIG: + cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index + 1); + if (NULL == cfg_desc) { + return false; + } + total_len = usb_cfg_desc_total_len(cfg_desc); + if (length <= total_len) { + need_zlp = false; + } else { + length = total_len; + } + usbdc_xfer(ep, cfg_desc, length, need_zlp); + return true; + case USB_DT_STRING: + str_desc = usb_find_str_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index); + if (NULL == str_desc) { + return false; + } + total_len = str_desc[0]; + if (length <= total_len) { + need_zlp = false; + } else { + length = total_len; + } + usbdc_xfer(ep, str_desc, length, need_zlp); + return true; + + default: + break; + } + return false; +} + +/** + * \brief Process the GetStatus request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_status_req(const uint8_t ep, const struct usb_req *req) +{ + int32_t st; + (void)ep; + + switch (req->bmRequestType & USB_REQT_RECIP_MASK) { + case USB_REQT_RECIP_DEVICE: + case USB_REQT_RECIP_INTERFACE: + st = 0; + break; + case USB_REQT_RECIP_ENDPOINT: + st = usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_GET); + if (st < 0) { + return false; + } + st = st & 0x1; + break; + default: + return false; + } + memcpy(usbdc.ctrl_buf, &st, 2); + usbdc_xfer(ep, usbdc.ctrl_buf, 2, false); + return true; +} + +/** + * \brief Process the standard Get Interface + * \param[in] req Point to usb request struct. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_interface(struct usb_req *req) +{ + struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; + int32_t rc; + + while (NULL != func) { + if (0 > (rc = func->ctrl(func, USBDF_GET_IFACE, req))) { + func = func->next; + } else { + usbdc.ctrl_buf[0] = (uint8_t)rc; + usbdc_xfer(0, usbdc.ctrl_buf, 1, false); + return true; + } + } + return false; +} + +/** + * \brief Process the standard Get request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_req(const uint8_t ep, struct usb_req *req) +{ + switch (req->bRequest) { + case USB_REQ_GET_DESC: + return usbdc_get_desc_req(ep, req); + case USB_REQ_GET_CONFIG: + *(uint8_t *)usbdc.ctrl_buf = usbdc.cfg_value; + usbdc_xfer(ep, usbdc.ctrl_buf, 1, false); + return true; + case USB_REQ_GET_STATUS: + return usbdc_get_status_req(ep, req); + case USB_REQ_GET_INTERFACE: + return usbdc_get_interface(req); + default: + return false; + } +} + +/** + * \brief Process the standard ClearFeature request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_clear_ftr_req(const uint8_t ep, const struct usb_req *req) +{ + (void)ep; + switch (req->bmRequestType & USB_REQT_RECIP_MASK) { + case USB_REQT_RECIP_ENDPOINT: + if (req->wLength != 0) { + return false; + } + usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_CLR); + return true; + default: + return false; + } +} + +/** + * \brief Process the standard SetFeature request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_set_ftr_req(const uint8_t ep, const struct usb_req *req) +{ + (void)ep; + switch (req->bmRequestType & USB_REQT_RECIP_MASK) { + case USB_REQT_RECIP_ENDPOINT: + if (req->wLength != 0) { + return false; + } + usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_SET); + return true; + default: + return false; + } +} + +/** + * \brief Unconfig, close all interfaces + */ +static void usbdc_unconfig(void) +{ + struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; + while (NULL != func) { + func->ctrl(func, USBDF_DISABLE, NULL); + func = func->next; + } +} + +/** + * \brief Apply Set Configuration Value + */ +static void usbdc_set_config(void) +{ + struct usbd_descriptors desc; + struct usbdf_driver * func; + uint8_t * cfg_desc; + uint16_t total_len; + uint8_t last_iface = 0xFF; + + if (usbdc.cfg_value == 0) { + usbdc_unconfig(); + return; + } + + cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, usbdc.cfg_value); + + if (NULL == cfg_desc) { + return; + } + + total_len = usb_cfg_desc_total_len(cfg_desc); + desc.eod = cfg_desc + total_len; + desc.sod = usb_find_desc(cfg_desc, desc.eod, USB_DT_INTERFACE); + + while (NULL != desc.sod) { + /* Apply very first alternate setting (must be 0) of the interface */ + if (last_iface != desc.sod[2] /* bInterfaceNumber */) { + last_iface = desc.sod[2]; + func = (struct usbdf_driver *)usbdc.func_list.head; + while (NULL != func) { + if (func->ctrl(func, USBDF_ENABLE, &desc)) { + func = func->next; + } else { + break; + } + } + } + desc.sod = usb_desc_next(desc.sod); + desc.sod = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); + } +} + +/** + * \brief Apply the USB device address + * \param[in] addr address to be set. + */ +static void usbdc_set_address(uint8_t addr) +{ + usb_d_set_address(addr); +} + +/** + * \brief Process the standard Set Interface + * \param[in] alt_set Alternate Setting. + * \param[in] ifc_id Interface Index. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_set_interface(uint16_t alt_set, uint16_t ifc_id) +{ + struct usbd_descriptors desc; + struct usbdf_driver * func; + uint8_t * ifc; + + desc.sod = usbdc.desces.ls_fs->sod; + desc.eod = usbdc.desces.ls_fs->eod; + if (NULL == (ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE))) { + return false; + } + + while (ifc[2] != ifc_id || ifc[3] != alt_set) { + desc.sod = usb_desc_next(desc.sod); + ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); + if (NULL == ifc) { + return false; + } + } + + desc.sod = ifc; + func = (struct usbdf_driver *)usbdc.func_list.head; + + while (NULL != func) { + if (func->ctrl(func, USBDF_DISABLE, &desc)) { + func = func->next; + } else if (ERR_NONE == func->ctrl(func, USBDF_ENABLE, &desc)) { + usbdc_xfer(0, NULL, 0, 0); + return true; + } else { + return false; + } + } + + return false; +} + +/** + * \brief Process the standard Set request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_set_req(const uint8_t ep, struct usb_req *req) +{ + switch (req->bRequest) { + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_CONFIG: + if (ERR_NONE == usbdc_xfer(ep, NULL, 0, true)) { + return true; + } else { + return false; + } + case USB_REQ_CLEAR_FTR: + return usbdc_clear_ftr_req(ep, req); + case USB_REQ_SET_FTR: + return usbdc_set_ftr_req(ep, req); + case USB_REQ_SET_INTERFACE: + return usbdc_set_interface(req->wValue, req->wIndex); + default: + return false; + } +} + +/** Invoke all registered SOF callbacks. */ +static void usbdc_sof_notify(void) +{ + struct usbdc_sof_handler *sof = (struct usbdc_sof_handler *)usbdc.handlers.sof_list.head; + + while (sof != NULL) { + if (NULL != sof->cb) { + sof->cb(); + } + sof = sof->next; + } +} + +/** Invoke all registered Change notification callbacks. */ +static void usbdc_change_notify(enum usbdc_change_type change, uint32_t value) +{ + struct usbdc_change_handler *cg = (struct usbdc_change_handler *)usbdc.handlers.change_list.head; + + while (cg != NULL) { + if (NULL != cg->cb) { + cg->cb(change, value); + } + cg = cg->next; + } +} + +/** Invoke all registered request callbacks until request handled. */ +static bool usbdc_request_handler(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + struct usbdc_req_handler *h = (struct usbdc_req_handler *)usbdc.handlers.req_list.head; + int32_t rc; + + while (h != NULL) { + if (NULL != h->cb) { + rc = h->cb(ep, req, stage); + if (0 == rc) { + return true; + } else if (ERR_NOT_FOUND != rc) { + return false; + } + } + h = h->next; + } + return false; +} + +/** + * \brief Callback invoked on USB device SOF + */ +static void usbd_sof_cb(void) +{ + usbdc_sof_notify(); +} + +/** + * \brief Callback invoked when control request is received + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_cb_ctl_req(const uint8_t ep, struct usb_req *req) +{ + if (usbdc_request_handler(ep, req, USB_SETUP_STAGE)) { + return true; + } + + // STD request handling + switch (req->bmRequestType & (USB_REQT_TYPE_MASK | USB_REQT_DIR_IN)) { + case USB_REQT_TYPE_STANDARD: + return usbdc_set_req(ep, req); + case (USB_REQT_TYPE_STANDARD | USB_REQT_DIR_IN): + return usbdc_get_req(ep, req); + default: + return false; + } +} + +/** + * \brief When control status stage is end + * \param[in] req Pointer to the request. + */ +static void usbdc_ctrl_status_end(const struct usb_req *req) +{ + switch (req->bRequest) { + case USB_REQ_SET_CONFIG: + usbdc.cfg_value = req->wValue; + usbdc_set_config(); + usbdc.state = req->wValue ? USBD_S_CONFIG : USBD_S_ADDRESS; + usbdc_change_notify(USBDC_C_STATE, usbdc.state); + break; + case USB_REQ_SET_ADDRESS: + usbdc_set_address(req->wValue); + usbdc.state = req->wValue ? USBD_S_ADDRESS : USBD_S_DEFAULT; + usbdc_change_notify(USBDC_C_STATE, usbdc.state); + break; + default: + break; + } +} + +/** + * \brief When control data stage is end + * \param[in] req Pointer to the request. + */ +static bool usbdc_ctrl_data_end(struct usb_req *req) +{ + usbdc_request_handler(0, req, USB_DATA_STAGE); + return false; +} + +/** + * \brief Callback invoked when control data done or status done + * \param[in] ep Endpoint number with direction on bit 8. + * \param[in] code Status code. + * \param[in] req Pointer to the control setup request. + * \return Data has error or not. + * \retval true There is data error, protocol error. + * \retval false There is no data error. + */ +static bool usbdc_cb_ctl_done(const uint8_t ep, const enum usb_xfer_code code, struct usb_req *req) +{ + (void)ep; + + switch (code) { + case USB_XFER_DONE: + usbdc_ctrl_status_end(req); + break; + case USB_XFER_DATA: + return usbdc_ctrl_data_end(req); + default: + break; + } + return false; +} + +/** + * \brief USB Device Core Reset + */ +void usbdc_reset(void) +{ + usbdc_unconfig(); + + usbdc.state = USBD_S_DEFAULT; + usbdc.cfg_value = 0; + + // Setup EP0 + usb_d_ep_deinit(0); + usb_d_ep0_init(usbdc.ctrl_size); + usb_d_ep_register_callback(0, USB_D_EP_CB_SETUP, (FUNC_PTR)usbdc_cb_ctl_req); + usb_d_ep_register_callback(0, USB_D_EP_CB_XFER, (FUNC_PTR)usbdc_cb_ctl_done); + usb_d_ep_enable(0); +} + +/** + * \brief Callback invoked on USB device events + * \param[in] ev Event code. + * \param[in] param Event parameter for event handling. + */ +static void usbd_event_cb(const enum usb_event ev, const uint32_t param) +{ + (void)param; + + switch (ev) { + case USB_EV_VBUS: + usbdc_change_notify(USBDC_C_CONN, param); + break; + + case USB_EV_RESET: + usbdc_reset(); + break; + + default: + break; + } +} + +/** + * \brief Issue USB device transfer + */ +int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp) +{ + struct usb_d_transfer xfer = {(uint8_t *)buf, size, ep, zlp}; + return usb_d_ep_transfer(&xfer); +} + +/** + * \brief Register the handler + */ +void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) +{ + switch (type) { + case USBDC_HDL_SOF: + list_insert_at_end(&usbdc.handlers.sof_list, (void *)h); + break; + case USBDC_HDL_REQ: + list_insert_at_end(&usbdc.handlers.req_list, (void *)h); + break; + case USBDC_HDL_CHANGE: + list_insert_at_end(&usbdc.handlers.change_list, (void *)h); + break; + default: + break; + } +} + +/** + * \brief Unregister the handler + */ +void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) +{ + switch (type) { + case USBDC_HDL_SOF: + list_delete_element(&usbdc.handlers.sof_list, (void *)h); + break; + case USBDC_HDL_REQ: + list_delete_element(&usbdc.handlers.req_list, (void *)h); + break; + case USBDC_HDL_CHANGE: + list_delete_element(&usbdc.handlers.change_list, (void *)h); + break; + default: + break; + } +} + +/** + * \brief Initialize the USB device core driver + */ +int32_t usbdc_init(uint8_t *ctrl_buf) +{ + ASSERT(ctrl_buf); + + int32_t rc; + + rc = usb_d_init(); + if (rc < 0) { + return rc; + } + + memset(&usbdc, 0, sizeof(usbdc)); + usbdc.ctrl_buf = ctrl_buf; + usb_d_register_callback(USB_D_CB_SOF, (FUNC_PTR)usbd_sof_cb); + usb_d_register_callback(USB_D_CB_EVENT, (FUNC_PTR)usbd_event_cb); + + return 0; +} + +/** + * \brief De-initialize the USB device core driver + */ +int32_t usbdc_deinit(void) +{ + usb_d_deinit(); + return 0; +} + +/** + * \brief Register/unregister function support of a USB device function + * + * Must be invoked when USB device is stopped. + */ +void usbdc_register_function(struct usbdf_driver *func) +{ + list_insert_at_end(&usbdc.func_list, func); +} + +/** + * \brief Unregister function support of a USB device function + * + * Must be invoked when USB device is stopped. + */ +void usbdc_unregister_function(struct usbdf_driver *func) +{ + list_delete_element(&usbdc.func_list, func); +} + +/** + * \brief Validate the descriptor + */ +int32_t usbdc_validate_desces(struct usbd_descriptors *desces) +{ + uint8_t *sod, *eod; + if (desces == NULL) { + return ERR_NOT_FOUND; + } + sod = usb_find_desc(desces->sod, desces->eod, USB_DT_DEVICE); + if (sod == NULL) { + return ERR_BAD_DATA; + } + sod = usb_find_desc(desces->sod, desces->eod, USB_DT_CONFIG); + if (sod == NULL) { + return ERR_BAD_DATA; + } + eod = sod + usb_cfg_desc_total_len(sod); + if (eod > desces->eod) { + return ERR_BAD_DATA; + } + return 0; +} + +/** + * \brief Validate the descriptor + */ +int32_t usbdc_check_desces(struct usbdc_descriptors *desces) +{ +#ifdef CONF_USBD_HS_SP + int32_t rc; + if (desces->hs == NULL && desces->ls_fs == NULL) { + return ERR_NOT_FOUND; + } + if (desces->hs) { + rc = usbdc_validate_desces(desces->hs); + if (rc < 0) { + return rc; + } + } +#endif + return usbdc_validate_desces(desces->ls_fs); +} + +/** + * \brief Start the USB device driver with specific descriptors set + */ +int32_t usbdc_start(struct usbd_descriptors *desces) +{ + if (usbdc.state >= USBD_S_POWER) { + return ERR_BUSY; + } + + if (desces) { + usbdc.desces.ls_fs = desces; + } else { + return ERR_BAD_DATA; + } + + usbdc.ctrl_size = desces->sod[7]; + usbdc.state = USBD_S_POWER; + usb_d_enable(); + return ERR_NONE; +} + +/** + * \brief Stop the USB device driver + */ +int32_t usbdc_stop(void) +{ + usb_d_disable(); + usbdc.state = USBD_S_OFF; + return ERR_NONE; +} + +/** + * \brief Attach the USB device to host + */ +void usbdc_attach(void) +{ + usb_d_attach(); +} + +/** + * \brief Detach the USB device from host + */ +void usbdc_detach(void) +{ + usb_d_detach(); +} + +/** + * \brief Send remote wakeup to host + */ +void usbdc_remotewakeup(void) +{ + usb_d_send_remotewakeup(); + usbdc.state = USBD_S_POWER; +} + +/** + * \brief Return USB Device endpoint0 buffer + */ +uint8_t *usbdc_get_ctrl_buffer(void) +{ + return usbdc.ctrl_buf; +} + +/** + * \brief Return current USB state + */ +uint8_t usbdc_get_state(void) +{ + if (usbdc.state & USBD_S_SUSPEND) { + return USBD_S_SUSPEND; + } + return usbdc.state; +} + +/** + * \brief Return version + */ +uint32_t usbdc_get_version(void) +{ + return USBDC_VERSION; +} diff --git a/atmel-samd/asf4/samd21/usb/device/usbdc.h b/atmel-samd/asf4/samd21/usb/device/usbdc.h new file mode 100644 index 0000000000000..515d28f1b903b --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/device/usbdc.h @@ -0,0 +1,246 @@ +/** + * \file + * + * \brief USB Device Stack Core Layer Definition. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_USBDC_H_ +#define _USB_USBDC_H_ + +#include "usb_includes.h" +#include "usb_protocol.h" +#include "hal_usb_device.h" + +/** USB device states. */ +enum usbd_state { + USBD_S_OFF = 0, + USBD_S_POWER = 1, + USBD_S_DEFAULT = 2, + USBD_S_ADDRESS = 3, + USBD_S_CONFIG = 4, + USBD_S_SUSPEND = 0x10 +}; + +/** USB device core handler type. */ +enum usbdc_handler_type { USBDC_HDL_SOF, USBDC_HDL_REQ, USBDC_HDL_CHANGE }; + +/** USB device core change notification type. */ +enum usbdc_change_type { + /** Change of connection, detected by vbus. */ + USBDC_C_CONN, + /** Change of state, by RESET, SetAddress(), SetConfig(). */ + USBDC_C_STATE, + /** Change of power. */ + USBDC_C_POWER, + /** Change of remote wakeup setting. */ + USBDC_C_REMOTE_WAKEUP +}; + +/** Power change. */ +enum usbdc_power_type { USBDC_ACTIVE, USBDC_SLEEP, USBDC_SUSPEND }; + +/** USB device general function control code. */ +enum usbdf_control { + /** Enable the function. + * int32_t ctrl(usbdf, USBDF_ENABLE, struct usbd_descriptors *desc); + * Parameter holds interface descriptor and + * configuration descriptor end position. + */ + USBDF_ENABLE, + /** Disable the function. + * int32_t ctrl(usbdf, USBDF_DISABLE, struct usbd_descriptors *desc); + * Parameter holds interface descriptor and + * configuration descriptor end position. + * Input NULL to force disable the function anyway. + */ + USBDF_DISABLE, + /** Get interface alternate setting. + * int32_t ctrl(usbdf, USBDF_GET_IFACE, struct usb_req *req); + * Parameter holds interface number who should return + * the alternate setting. + */ + USBDF_GET_IFACE +}; + +/** Describes a list of USB descriptors. */ +struct usbd_descriptors { + /** Pointer to Start of Descriptors. */ + uint8_t *sod; + /** Pointer to End of Descriptors. */ + uint8_t *eod; +}; + +/** Describes the USB device core descriptors. */ +struct usbdc_descriptors { + struct usbd_descriptors *ls_fs; +#ifdef CONF_USBD_HS_SP + struct usbd_descriptors *hs; +#endif +}; + +/** Describes a list of core handler descriptor. */ +struct usbdc_handler { + /** Pointer to next handler. */ + struct usbdc_handler *next; + /** Pointer to handler function. */ + FUNC_PTR func; +}; + +/** Forward declaration for USB device function driver. */ +struct usbdf_driver; + +/** SOF handling function. */ +typedef void (*usbdc_sof_cb_t)(void); + +/** REQ handling function. */ +typedef int32_t (*usbdc_req_cb_t)(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage); + +/** Change notification callback function. */ +typedef void (*usbdc_change_cb_t)(enum usbdc_change_type change, uint32_t value); + +/** Control function for USB device general function driver. */ +typedef int32_t (*usbdf_control_cb_t)(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param); + +/** USB device general function driver descriptor. */ +struct usbdf_driver { + /** Pointer to next function.*/ + struct usbdf_driver *next; + /** Pointer to control function.*/ + usbdf_control_cb_t ctrl; + /** Pointer to function driver specific data. */ + void *func_data; +}; + +/** + * \brief Register the handler + * \param[in] type USB device core handler type. + * \param[in] h Pointer to usb device core handler. + */ +void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); + +/** + * \brief Unregister the handler + * \param[in] type USB device core handler type. + * \param[in] h Pointer to usb device core handler. + */ +void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); + +/** + * \brief Initialize the USB device core driver + * \param[in] ctrl_buf Pointer to a buffer to be used by usb device ctrl endpoint + * Note: the size of ctrl_buf should not be less than the size of EP0 + * \return Operation status. + */ +int32_t usbdc_init(uint8_t *ctrl_buf); + +/** + * \brief Deinitialize the USB device core driver + * \return Operation status. + */ +int32_t usbdc_deinit(void); + +/** + * \brief Register function support of a USB device function + * \param[in] func Pointer to usb device function driver structure + */ +void usbdc_register_function(struct usbdf_driver *func); + +/** + * \brief Unregister function support of a USB device function + * \param[in] func Pointer to usb device function driver structure + */ +void usbdc_unregister_function(struct usbdf_driver *func); + +/** + * \brief Validate the descriptors + * \param[in] desces Pointer to usb device core descriptors + * \return Operation status. + */ +int32_t usbdc_validate_desces(struct usbd_descriptors *desces); + +/** + * \brief Issue USB device data transfer + * \param[in] ep endpointer address. + * \param[in] buf Pointer to data transfer buffer. + * \param[in] size the size of data transfer. + * \param[in] zlp flag to indicate zero length packet. + * \return Operation status. + */ +int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp); + +/** + * \brief Start the USB device driver with specific descriptors set + * \param[in] desces Pointer to usb device core descriptors + * \return Operation status. + */ +int32_t usbdc_start(struct usbd_descriptors *desces); + +/** + * \brief Stop the USB device driver + * \return Operation status. + */ +int32_t usbdc_stop(void); + +/** + * \brief Attach the USB device to host + */ +void usbdc_attach(void); + +/** + * \brief Detach the USB device from host + */ +void usbdc_detach(void); + +/** + * \brief Send remote wakeup to host + */ +void usbdc_remotewakeup(void); + +/** + * \brief Return USB device ctrl end pointer buffer start address + */ +uint8_t *usbdc_get_ctrl_buffer(void); + +/** + * \brief Return current USB state + */ +uint8_t usbdc_get_state(void); + +/** + * \brief Return version + */ +uint32_t usbdc_get_version(void); + +#endif /* USBDC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/usb_atmel.h b/atmel-samd/asf4/samd21/usb/usb_atmel.h new file mode 100644 index 0000000000000..3ca7a2927eb58 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/usb_atmel.h @@ -0,0 +1,189 @@ +/** + * \file + * + * \brief All USB VIDs and PIDs from Atmel USB applications + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _USB_ATMEL_H_ +#define _USB_ATMEL_H_ + +/** + * \defgroup usb_group USB Stack + * + * This stack includes the USB Device Stack, USB Host Stack and common + * definitions. + * @{ + */ + +//! @} + +/** + * \ingroup usb_group + * \defgroup usb_atmel_ids_group Atmel USB Identifiers + * + * This module defines Atmel PID and VIDs constants. + * + * @{ + */ + +//! \name Vendor Identifier assigned by USB org to ATMEL +#define USB_VID_ATMEL 0x03EB + +//! \name Product Identifier assigned by ATMEL to AVR applications +//! @{ + +//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others. +//! @{ +#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013 +#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017 +#define USB_PID_ATMEL_MEGA_CDC 0x2018 +#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019 +#define USB_PID_ATMEL_MEGA_MS 0x201A +#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B +#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C +#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D +#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022 +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023 +#define USB_PID_ATMEL_MEGA_MS_2 0x2029 +#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A +#define USB_PID_ATMEL_MEGA_MS_3 0x2032 +#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050 +//! @} + +//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools. +//! @{ +#define USB_PID_ATMEL_XPLAINED 0x2122 +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B +//! @} + +//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=> +//! @{ +#define USB_PID_ATMEL_UC3_ENUM 0x2300 +#define USB_PID_ATMEL_UC3_MS 0x2301 +#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302 +#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303 +#define USB_PID_ATMEL_UC3_HID 0x2304 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306 +#define USB_PID_ATMEL_UC3_CDC 0x2307 +#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308 +#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx +#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311 +#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312 +//! @} + +//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications +//! @{ +#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400 +#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401 +#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402 +#define USB_PID_ATMEL_ASF_MSC 0x2403 +#define USB_PID_ATMEL_ASF_CDC 0x2404 +#define USB_PID_ATMEL_ASF_PHDC 0x2405 +#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406 +#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420 +#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421 +#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422 +#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423 +#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424 +#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425 +#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432 +#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433 +#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434 +//! @} + +//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders +//! Note, !!!! don't use this range for demos or examples !!!! +//! @{ +#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6 +#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7 +#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8 +#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9 +#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA +#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB +#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC +#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD +#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE + +#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF +#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0 +#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1 +#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2 +#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3 +#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4 +#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5 +#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6 +#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7 +#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8 +#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9 +#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA +#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB +#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC +#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED +#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE +#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF +#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0 +#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1 +#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2 +#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3 +#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4 +#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5 +#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6 +#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7 +#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8 +#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9 +#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA +#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB +// 2FFCh to 2FFFh used by C51 family products +//! @} + +//! @} + +//! @} + +#endif // _USB_ATMEL_H_ diff --git a/atmel-samd/asf4/samd21/usb/usb_debug.h b/atmel-samd/asf4/samd21/usb/usb_debug.h new file mode 100644 index 0000000000000..4d8893208beac --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/usb_debug.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief USB Debug Files. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_DEBUG_H_ +#define _USB_DEBUG_H_ + +#define udbg_print(...) + +#endif diff --git a/atmel-samd/asf4/samd21/usb/usb_includes.h b/atmel-samd/asf4/samd21/usb/usb_includes.h new file mode 100644 index 0000000000000..b3874d31e64e3 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/usb_includes.h @@ -0,0 +1,137 @@ +/** + * \file + * + * \brief USB Include Header Files. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_INCLUDES_H_ +#define _USB_INCLUDES_H_ + +#ifdef USB_USER_INCLUDES + +#include "usb_user_includes.h" + +#else +/* Include START headers */ +#include +#include +#include +#include +#include +#include +#include + +typedef uint16_t le16_t; +typedef uint32_t le32_t; +typedef uint16_t be16_t; +typedef uint32_t be32_t; + +#if (defined __GNUC__) || (defined __CC_ARM) +#define is_constant(exp) __builtin_constant_p(exp) +#else +#define is_constant(exp) (0) +#endif + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#if (defined __GNUC__) +#define swap_u32(u32) \ + (is_constant(u32) \ + ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) \ + : ((uint32_t)__builtin_bswap32((uint32_t)(u32)))) +#else +#define swap_u32(u32) \ + ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) +#endif + +/** Get a value from/to LE16 data */ +#define LE16(x) (x) +/** Get a value from/to LE32 data */ +#define LE32(x) (x) +/** Get a value from/to BE16 data */ +#define BE16(x) swap_u16(x) +/** Get a value from/to BE32 data */ +#define BE32(x) swap_u32(x) + +/** Get byte 0 for BE 16-bit value */ +#define BE16B0(a) ((uint8_t)((a) >> 8)) +/** Get byte 1 for BE 16-bit value */ +#define BE16B1(a) ((uint8_t)((a) >> 0)) + +/** Get byte 0 for BE 32-bit value */ +#define BE32B0(a) ((uint8_t)((a) >> 24)) +/** Get byte 1 for BE 32-bit value */ +#define BE32B1(a) ((uint8_t)((a) >> 16)) +/** Get byte 2 for BE 32-bit value */ +#define BE32B2(a) ((uint8_t)((a) >> 8)) +/** Get byte 3 for BE 32-bit value */ +#define BE32B3(a) ((uint8_t)((a) >> 0)) + +/** Get byte 0 for LE 16-bit value */ +#define LE16B0(a) ((uint8_t)((a) >> 0)) +/** Get byte 1 for LE 16-bit value */ +#define LE16B1(a) ((uint8_t)((a) >> 8)) + +/** Get byte 0 for LE 32-bit value */ +#define LE32B0(a) ((uint8_t)((a) >> 0)) +/** Get byte 1 for LE 32-bit value */ +#define LE32B1(a) ((uint8_t)((a) >> 8)) +/** Get byte 2 for LE 32-bit value */ +#define LE32B2(a) ((uint8_t)((a) >> 16)) +/** Get byte 3 for LE 32-bit value */ +#define LE32B3(a) ((uint8_t)((a) >> 24)) + +#endif /* USB_USER_INCLUDES */ + +#endif /* _USB_INCLUDES_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/usb_protocol.c b/atmel-samd/asf4/samd21/usb/usb_protocol.c new file mode 100644 index 0000000000000..534e4d1d96d3c --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/usb_protocol.c @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief USB protocol implementation. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#define CONF_NO_ASSERT_CHECK + +#include "usb_protocol.h" + +#ifdef CONF_NO_ASSERT_CHECK +#define _param_error_check(cond) +#define _desc_len_check() \ + if (usb_desc_len(desc) < 2) { \ + /* Encounter an invalid descriptor. */ \ + return NULL; \ + } +#else +#define _param_error_check(cond) ASSERT(cond) +#define _desc_len_check() ASSERT(usb_desc_len(desc) >= 2) +#endif + +uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type) +{ + _param_error_check(desc && eof && (desc < eof)); + + while (desc < eof) { + _desc_len_check(); + if (type == usb_desc_type(desc)) { + return desc; + } + desc = usb_desc_next(desc); + } + return NULL; +} + +uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n) +{ + _param_error_check(desc && eof && (desc < eof)); + + while (desc < eof) { + _desc_len_check(); + if (USB_DT_INTERFACE == usb_desc_type(desc)) { + if (iface_n != desc[2]) { + return desc; + } + } + desc = usb_desc_next(desc); + } + return eof; +} + +uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof) +{ + _param_error_check(desc && eof && (desc < eof)); + + while (desc < eof) { + _desc_len_check(); + if (USB_DT_INTERFACE == usb_desc_type(desc)) { + break; + } + if (USB_DT_ENDPOINT == usb_desc_type(desc)) { + return desc; + } + desc = usb_desc_next(desc); + } + return NULL; +} + +uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value) +{ + _param_error_check(desc && eof && (desc < eof)); + + desc = usb_find_desc(desc, eof, USB_DT_CONFIG); + if (!desc) { + return NULL; + } + while (desc < eof) { + _desc_len_check(); + if (desc[1] != USB_DT_CONFIG) { + break; + } + if (desc[5] == cfg_value) { + return desc; + } + desc = usb_cfg_desc_next(desc); + } + return NULL; +} + +uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index) +{ + uint8_t i; + + _param_error_check(desc && eof && (desc < eof)); + + for (i = 0; desc < eof;) { + desc = usb_find_desc(desc, eof, USB_DT_STRING); + if (desc) { + _desc_len_check(); + if (i == str_index) { + return desc; + } + i++; + desc = usb_desc_next(desc); + } else { + return NULL; + } + } + return NULL; +} diff --git a/atmel-samd/asf4/samd21/usb/usb_protocol.h b/atmel-samd/asf4/samd21/usb/usb_protocol.h new file mode 100644 index 0000000000000..bb8d1ecd59f2e --- /dev/null +++ b/atmel-samd/asf4/samd21/usb/usb_protocol.h @@ -0,0 +1,765 @@ +/** + * \file + * + * \brief USB protocol definitions. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_PROTOCOL_H_ +#define _USB_PROTOCOL_H_ + +#include "usb_includes.h" + +/** + * \ingroup usb_group + * \defgroup usb_protocol_group USB Protocol Definitions + * + * This module defines constants and data structures provided by the USB + * 2.0 specification. + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __CC_ARM +#pragma anon_unions +#endif + +/*! Value for field bcdUSB */ +#define USB_V2_0 (0x0200) /*!< USB Specification version 2.00 */ +#define USB_V2_1 (0x0201) /*!< USB Specification version 2.01 (support BOS) */ + +/*! \name Generic definitions (Class, subclass and protocol) + */ +/*! @{ */ +#define USB_CLASS_NO (0x00) +#define USB_SUBCLASS_NO (0x00) +#define USB_PROTOCOL_NO (0x00) +/*! @} */ + +/*! \name IAD (Interface Association Descriptor) constants */ +/*! @{ */ +#define USB_CLASS_IAD (0xEF) +#define USB_SUBCLASS_IAD (0x02) +#define USB_PROTOCOL_IAD (0x01) +/*! @} */ + +/** + * \brief USB request data transfer direction (bmRequestType) + */ +#define USB_REQT_DIR_OUT (0 << 7) /*!< Host to device */ +#define USB_REQT_DIR_H2D (0 << 7) /*!< Host to device */ +#define USB_REQT_DIR_IN (1 << 7) /*!< Device to host */ +#define USB_REQT_DIR_D2H (1 << 7) /*!< Device to host */ +#define USB_REQT_DIR_MASK (1 << 7) /*!< Mask */ + +/** + * \brief USB request types (bmRequestType) + */ +#define USB_REQT_TYPE_STANDARD (0 << 5) /*!< Standard request */ +#define USB_REQT_TYPE_CLASS (1 << 5) /*!< Class-specific request */ +#define USB_REQT_TYPE_VENDOR (2 << 5) /*!< Vendor-specific request */ +#define USB_REQT_TYPE_MASK (3 << 5) /*!< Mask */ + +/** + * \brief USB recipient codes (bmRequestType) + */ +#define USB_REQT_RECIP_DEVICE (0 << 0) /*!< Recipient device */ +#define USB_REQT_RECIP_INTERFACE (1 << 0) /*!< Recipient interface */ +#define USB_REQT_RECIP_ENDPOINT (2 << 0) /*!< Recipient endpoint */ +#define USB_REQT_RECIP_OTHER (3 << 0) /*!< Recipient other */ +#define USB_REQT_RECIP_MASK (0x1F) /*!< Mask */ + +/** + * \brief Standard USB control transfer stages. + */ +enum usb_ctrl_stage { USB_SETUP_STAGE = 0, USB_DATA_STAGE = 1, USB_STATUS_STAGE = 2 }; + +/** + * \brief Standard USB requests (bRequest) + */ +enum usb_req_code { + USB_REQ_GET_STATUS = 0, + USB_REQ_CLEAR_FTR = 1, + USB_REQ_SET_FTR = 3, + USB_REQ_SET_ADDRESS = 5, + USB_REQ_GET_DESC = 6, + USB_REQ_SET_DESC = 7, + USB_REQ_GET_CONFIG = 8, + USB_REQ_SET_CONFIG = 9, + USB_REQ_GET_INTERFACE = 10, + USB_REQ_SET_INTERFACE = 11, + USB_REQ_SYNCH_FRAME = 12, + USB_REQ_SET_SEL = 48, + USB_REQ_ISOCH_DELAY = 49 +}; + +/** + * \brief Standard USB device status flags + * + */ +enum usb_dev_status { + USB_DEV_STAT_BUS_POWERED = 0, + USB_DEV_STAT_SELF_POWERED = 1, + USB_DEV_STAT_REMOTEWAKEUP = 2, + USB_DEV_STAT_U1_ENABLE = 4, + USB_DEV_STAT_U2_ENABLE = 8, + USB_DEV_STAT_LTM_ENABLE = 16 +}; + +/** + * \brief Standard USB Interface status flags + * + */ +enum usb_interface_status { + USB_IFACE_STAT_RESERVED = 0, + USB_IFACE_STAT_REMOTEWAKE_CAP = 1, + USB_IFACE_STAT_REMOTEWAKE = 2 +}; + +/** + * \brief Standard USB endpoint status flags + * + */ +enum usb_endpoint_status { USB_EP_STAT_HALT = 1 }; + +/** + * \brief Standard USB device feature flags + * + * \note valid for SetFeature request. + */ +enum usb_device_feature { + USB_DEV_FTR_REMOTE_WAKEUP = 1, /*!< Remote wakeup enabled */ + USB_DEV_FTR_TEST_MODE = 2, /*!< USB test mode */ + USB_DEV_FTR_OTG_B_HNP_ENABLE = 3, + USB_DEV_FTR_OTG_A_HNP_SP = 4, + USB_DEV_FTR_OTG_A_ALT_HNP_SP = 5, + USB_DEV_FTR_U1_ENABLE = 48, + USB_DEV_FTR_U2_ENABLE = 49, + USB_DEV_FTR_LTM_ENABLE = 50 +}; + +/** + * \brief Test Mode possible on HS USB device + * + * \note valid for USB_DEV_FTR_TEST_MODE request. + */ +enum usb_device_hs_test_mode { + USB_DEV_TEST_MODE_J = 1, + USB_DEV_TEST_MODE_K = 2, + USB_DEV_TEST_MODE_SE0_NAK = 3, + USB_DEV_TEST_MODE_PACKET = 4, + USB_DEV_TEST_MODE_FORCE_ENABLE = 5 +}; + +/** + * \brief Standard Feature Selectors for Interface + */ +enum usb_iface_feature { USB_IFACE_FTR_FUNC_SUSP = 0 }; + +/** + * \brief Standard USB endpoint feature/status flags + */ +enum usb_endpoint_feature { USB_EP_FTR_HALT = 0 }; + +/** + * \brief Standard USB Test Mode Selectors + */ +enum usb_test_mode_selector { + USB_TEST_J = 0x01, + USB_TEST_K = 0x02, + USB_TEST_SE0_NAK = 0x03, + USB_TEST_PACKET = 0x04, + USB_TEST_FORCE_ENABLE = 0x05 +}; + +/** + * \brief Standard USB descriptor types + */ +enum usb_descriptor_type { + USB_DT_DEVICE = 1, + USB_DT_CONFIG = 2, + USB_DT_STRING = 3, + USB_DT_INTERFACE = 4, + USB_DT_ENDPOINT = 5, + USB_DT_DEVICE_QUALIFIER = 6, + USB_DT_OTHER_SPEED_CONFIG = 7, + USB_DT_INTERFACE_POWER = 8, + USB_DT_OTG = 9, + USB_DT_DEBUG = 10, + USB_DT_IAD = 11, + USB_DT_BOS = 15, + USB_DT_DEV_CAP = 16, + USB_DT_SS_EP_COMPANION = 48 +}; + +/** + * \brief Capability types + */ +enum usb_capability_type { + USB_CAPT_WIRELESS = 1, + USB_CAPT_2_0_EXT = 2, + USB_CAPT_SUPER_SPEED = 3, + USB_CAPT_CONTAINER_ID = 4 +}; + +/** + * \brief USB 2.0 Extension attributes + */ +enum usb_2_0_ext_attr { USB_2_0_EXT_LPM_SP = 1 }; + +/** + * \brief USB SuperSpeed Capability attributes + */ +enum usb_ss_cap_attr { USB_SS_LTM_SP }; + +/** + * \brief USB Speed Supports + */ +enum usb_speed_sp { + USB_SPEED_LOW_SP = 1, + USB_SPEED_LS_SP = 1, + USB_SPEED_FULL_SP = 2, + USB_SPEED_FS_SP = 2, + USB_SPEED_HIGH_SP = 4, + USB_SPEED_HS_SP = 4, + USB_SPEED_SUPER_SP = 8, + USB_SPEED_SS_SP = 8 +}; + +/** + * \brief Standard USB endpoint transfer types + */ +enum usb_ep_type { + USB_EP_TYPE_CONTROL = 0x00, + USB_EP_TYPE_ISOCHRONOUS = 0x01, + USB_EP_TYPE_BULK = 0x02, + USB_EP_TYPE_INTERRUPT = 0x03, + USB_EP_TYPE_MASK = 0x03u +}; + +/** + * \brief USB endpoint interrupt types + */ +enum usb_ep_int_type { USB_EP_INT_T_PERIODIC = 0x00u, USB_EP_INT_T_NOTIFICATION = 0x01u, USB_EP_INT_T_MASK = 0x03u }; + +/** + * \brief Standard USB endpoint synchronization types + */ +enum usb_ep_sync_type { + USB_EP_SYNC_T_NO = 0x00u, + USB_EP_SYNC_T_ASYNC = 0x02u, + USB_EP_SYNC_T_ADAPTIVE = 0x02u, + USB_EP_SYNC_T_SYNC = 0x03u, + USB_EP_SYNC_T_MASK = 0x03u +}; + +/** + * \brief Standard USB endpoint usage types + */ +enum usb_ep_usage_type { + USB_EP_USAGE_T_DATA = 0x00u, + USB_EP_USAGE_T_FEEDBACK = 0x01u, + USB_EP_USAGE_T_FEEDBACK_DATA = 0x02u, + USB_EP_USAGE_T_MASK = 0x03u +}; + +/** + * \brief Standard USB language IDs for string descriptors + */ +enum usb_langid { + USB_LANGID_EN_US = 0x0409 /*!< English (United States) */ +}; + +/** + * \brief Mask selecting the index part of an endpoint address + */ +#define USB_EP_ADDR_MASK 0x0f +/** + * \brief Endpoint transfer direction is IN + */ +#define USB_EP_DIR_IN 0x80 +/** + * \brief Endpoint transfer direction is OUT + */ +#define USB_EP_DIR_OUT 0x00 + +/** + * \brief Maximum length in bytes of a USB descriptor + * + * The maximum length of a USB descriptor is limited by the 8-bit + * bLength field. + */ +#define USB_DESC_LEN_MAX 255 + +/* + * 2-byte alignment requested for all USB structures. + */ +COMPILER_PACK_SET(1) + +/** + * \brief A USB Device SETUP request + * + * The data payload of SETUP packets always follows this structure. + */ +typedef struct usb_req { + uint8_t bmRequestType; + uint8_t bRequest; + union { + le16_t wValue; + struct { + uint8_t l; + uint8_t h; + } wValueBytes; + }; + union { + le16_t wIndex; + struct { + uint8_t l; + uint8_t h; + } wIndexBytes; + }; + union { + le16_t wLength; + struct { + uint8_t l; + uint8_t h; + } wLengthBytes; + }; +} usb_req_t; + +/** + * \brief Standard USB device descriptor structure + */ +typedef struct usb_dev_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + le16_t idVendor; + le16_t idProduct; + le16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} usb_dev_desc_t; + +/** + * \brief Binary device Object Store (BOS) descriptor structure + */ +typedef struct usb_bos_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumDeviceCaps; +} usb_bos_desc_t; + +/** + * \brief Device Capability Descriptor structure + */ +typedef struct usb_cap_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t Vars[1]; +} usb_cap_desc_t; + +/** + * \brief USB 2.0 Extension Descriptor structure + */ +typedef struct usb_2_0_ext { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint32_t bmAttributes; +} usb_2_0_ext_t; + +/** + * \brief LPM Device Capabilities descriptor structure + */ +typedef struct usb_2_0_ext usb_lpm_cap_desc_t; + +/** + * \brief SuperSpeed USB Device Capability structure + */ +typedef struct usb_ss_cap_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bmAttributes; + le16_t wSpeedsSupported; + uint8_t bFunctionalitySupport; + uint8_t bU1DevExitLat; + uint8_t bU2DevExitLat; +} usb_ss_cap_desc_t; + +/** + * \brief USB Container ID Descriptor structure + */ +typedef struct usb_container_id_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t ContainerID[16]; +} usb_container_id_desc_t; + +/** + * \brief Standard USB device qualifier descriptor structure + * + * This descriptor contains information about the device when running at + * the "other" speed (i.e. if the device is currently operating at high + * speed, this descriptor can be used to determine what would change if + * the device was operating at full speed.) + */ +typedef struct usb_dev_qual_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} usb_dev_qual_desc_t; + +/** + * \brief Standard USB configuration descriptor structure + */ +typedef struct usb_config_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} usb_config_desc_t; + +#define USB_CONFIG_ATTR_MUST_SET (1 << 7) /*!< Must always be set */ +#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) /*!< Bus-powered */ +#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) /*!< Self-powered */ +#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) /*!< remote wakeup supported */ + +#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) /*!< Max power in mA */ + +/** + * \brief Standard USB association descriptor structure + */ +typedef struct usb_iad_desc { + uint8_t bLength; /*!< Size of this descriptor in bytes */ + uint8_t bDescriptorType; /*!< Interface descriptor type */ + uint8_t bFirstInterface; /*!< Number of interface */ + uint8_t bInterfaceCount; /*!< value to select alternate setting */ + uint8_t bFunctionClass; /*!< Class code assigned by the USB */ + uint8_t bFunctionSubClass; /*!< Sub-class code assigned by the USB */ + uint8_t bFunctionProtocol; /*!< Protocol code assigned by the USB */ + uint8_t iFunction; /*!< Index of string descriptor */ +} usb_iad_desc_t; + +/** + * \brief Standard USB interface descriptor structure + */ +typedef struct usb_iface_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_iface_desc_t; + +/** + * \brief Standard USB endpoint descriptor structure + */ +typedef struct usb_ep_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + le16_t wMaxPacketSize; + uint8_t bInterval; +} usb_ep_desc_t; + +/** + * \brief SuperSpeed Endpoint Companion descriptor structure + */ +typedef struct usb_ss_ep_comp_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bMaxBurst; + uint8_t bmAttributes; + le16_t wBytesPerInterval; +} usb_ss_ep_comp_desc_t; + +/** + * \brief LPM Token bmAttributes structure + */ +typedef struct usb_lpm_attributes { + uint8_t bLinkState : 4; + uint8_t HIRD : 4; + uint8_t bRemoteWake : 1; + uint8_t Reserved : 2; +} usb_lpm_attributes_t; + +/** + * \brief A standard USB string descriptor structure + */ +typedef struct usb_str_desc { + uint8_t bLength; + uint8_t bDescriptorType; +} usb_str_desc_t; + +typedef struct usb_str_langid_desc { + usb_str_desc_t desc; + le16_t string[1]; +} usb_str_langid_desc_t; + +COMPILER_PACK_RESET() + +/** \name Macros to build USB standard descriptors */ +/*@{*/ + +/** Build bytes for USB device descriptor. */ +#define USB_DEV_DESC_BYTES(bcdUSB, \ + bDeviceClass, \ + bDeviceSubClass, \ + bDeviceProtocol, \ + bMaxPacketSize0, \ + idVendor, \ + idProduct, \ + bcdDevice, \ + iManufacturer, \ + iProduct, \ + iSerialNumber, \ + bNumConfigurations) \ + 18, /* bLength */ \ + 0x01, /* bDescriptorType: DEVICE */ \ + LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0, \ + LE_BYTE0(idVendor), LE_BYTE1(idVendor), LE_BYTE0(idProduct), LE_BYTE1(idProduct), LE_BYTE0(bcdDevice), \ + LE_BYTE1(bcdDevice), iManufacturer, iProduct, iSerialNumber, bNumConfigurations + +#define USB_DEV_DESC_LEN 18 + +/** Build bytes for USB configuration descriptor. */ +#define USB_CONFIG_DESC_BYTES( \ + wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower) \ + 9, /* bLength */ \ + 0x02, /* bDescriptorType: CONFIGURATION */ \ + LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration, \ + bmAttributes, bMaxPower + +#define USB_CONFIG_DESC_LEN 9 + +/** Build bytes for USB IAD descriptor. */ +#define USB_IAD_DESC_BYTES( \ + bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction) \ + 8, /* bLength */ \ + USB_DT_IAD, /* bDescriptorType */ \ + bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction + +#define USB_IAD_DESC_LEN 8 + +/** Build bytes for USB interface descriptor. */ +#define USB_IFACE_DESC_BYTES(bInterfaceNumber, \ + bAlternateSetting, \ + bNumEndpoints, \ + bInterfaceClass, \ + bInterfaceSubClass, \ + bInterfaceProtocol, \ + iInterface) \ + 9, /* bLength */ \ + 0x04, /* bDescriptorType: INTERFACE */ \ + bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, \ + iInterface + +#define USB_IFACE_DESC_LEN 9 + +/** Build bytes for USB endpoint descriptor. */ +#define USB_ENDP_DESC_BYTES(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 7, /* bLength */ \ + 0x05, /* bDescriptorType: ENDPOINT */ \ + bEndpointAddress, bmAttributes, LE_BYTE0(wMaxPacketSize), LE_BYTE1(wMaxPacketSize), bInterval + +#define USB_ENDP_DESC_LEN 7 + +/*@}*/ + +/** \brief Get a word (calculate by little endian 16-bit data) + * \param[in] ptr Byte pointer to the address to get data + * \return a 16-bit word + */ +static inline uint16_t usb_get_u16(const uint8_t *ptr) +{ + return (ptr[0] + (ptr[1] << 8)); +} + +/** \brief Get a double word (calculate by little endian 32-bit data) + * \param[in] ptr Byte pointer to the address to get data + * \return a 32-bit word + */ +static inline uint32_t usb_get_u32(const uint8_t *ptr) +{ + return (ptr[0] + (ptr[1] << 8) + (ptr[2] << 16) + (ptr[3] << 24)); +} + +/** \brief Get descriptor length + * \param[in] desc Byte pointer to the descriptor start address + * \return descriptor length + */ +static inline uint8_t usb_desc_len(const uint8_t *desc) +{ + return desc[0]; +} + +/** \brief Get descriptor type + * \param[in] desc Byte pointer to the descriptor start address + * \return descriptor type + */ +static inline uint8_t usb_desc_type(const uint8_t *desc) +{ + return desc[1]; +} + +/** \brief Get next USB descriptor + * \param[in] desc Byte pointer to the descriptor start address + * \return Byte pointer to the next descriptor + */ +static inline uint8_t *usb_desc_next(uint8_t *desc) +{ + return (desc + usb_desc_len(desc)); +} + +/** \brief Get idVendor of USB Device Descriptor + * \param[in] dev_desc Byte pointer to the descriptor start address + * \return 16-bit idVendor value + */ +static inline uint16_t usb_dev_desc_vid(const uint8_t *dev_desc) +{ + return usb_get_u16(dev_desc + 8); +} + +/** \brief Get idProduct of USB Device Descriptor + * \param[in] dev_desc Byte pointer to the descriptor start address + * \return 16-bit idProduct value + */ +static inline uint16_t usb_dev_desc_pid(const uint8_t *dev_desc) +{ + return usb_get_u16(dev_desc + 10); +} + +/** \brief Get wTotalLength of USB Configuration Descriptor + * \param[in] cfg_desc Byte pointer to the descriptor start address + * \return 16-bit total length of configuration list + */ +static inline uint16_t usb_cfg_desc_total_len(const uint8_t *cfg_desc) +{ + return usb_get_u16(cfg_desc + 2); +} + +/** \brief Get Next USB Descriptor After the Configuration Descriptors list + * \param[in] cfg_desc Byte pointer to the descriptor start address + * \return Byte pointer to descriptor after configuration end + */ +static inline uint8_t *usb_cfg_desc_next(uint8_t *cfg_desc) +{ + return (cfg_desc + usb_cfg_desc_total_len(cfg_desc)); +} + +/** \brief Find specific USB Descriptor by its type + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] type The descriptor type expected + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type); + +/** Get interface descriptor next to the specified one (by interface number) + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] iface_n The interface number to check + * \return Pointer to the descriptor + * \retval >= eof if not found + */ +uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n); + +/** Find endpoint descriptor, breaks if interface descriptor detected + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof); + +/** Find configuration descriptor by its configuration number + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] cfg_value The configure value expected + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value); + +/** Find string descriptor by its index + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] str_index The string index expected + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index); + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* _USB_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd21/usb_start.c b/atmel-samd/asf4/samd21/usb_start.c new file mode 100644 index 0000000000000..afd8f89b2b715 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb_start.c @@ -0,0 +1,54 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#include "atmel_start.h" +#include "usb_start.h" + +static uint8_t multi_desc_bytes[] = { + /* Device descriptors and Configuration descriptors list. */ + COMPOSITE_DESCES_LS_FS, +}; + +static struct usbd_descriptors multi_desc = {multi_desc_bytes, multi_desc_bytes + sizeof(multi_desc_bytes)}; + +/** Ctrl endpoint buffer */ +static uint8_t ctrl_buffer[64]; + +/** + * \brief Composite Init + */ +void composite_device_init(void) +{ + /* usb stack init */ + usbdc_init(ctrl_buffer); + + /* usbdc_register_funcion inside */ + cdcdf_acm_init(); + + usbdc_start(&multi_desc); + usbdc_attach(); +} + +/** + * Example of using Composite Function. + * \note + * In this example, we will use a PC as a USB host: + * - Connect the DEBUG USB on XPLAINED board to PC for program download. + * - Connect the TARGET USB on XPLAINED board to PC for running program. + */ +void composite_device_example(void) +{ + while (!cdcdf_acm_is_enabled()) { + // wait cdc acm to be installed + }; +} + +void usb_init(void) +{ + + composite_device_init(); +} diff --git a/atmel-samd/asf4/samd21/usb_start.h b/atmel-samd/asf4/samd21/usb_start.h new file mode 100644 index 0000000000000..9695f7ed78d69 --- /dev/null +++ b/atmel-samd/asf4/samd21/usb_start.h @@ -0,0 +1,33 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#ifndef USB_DEVICE_MAIN_H +#define USB_DEVICE_MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "cdcdf_acm.h" +#include "hiddf_mouse.h" +#include "hiddf_keyboard.h" +#include "hiddf_generic.h" +#include "composite_desc.h" + +void composite_device_init(void); +void composite_device_example(void); + +/** + * \berif Initialize USB + */ +void usb_init(void); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // USB_DEVICE_MAIN_H diff --git a/atmel-samd/asf4/samd51/CMSIS/Documentation/Core/html/index.html b/atmel-samd/asf4/samd51/CMSIS/Documentation/Core/html/index.html new file mode 100644 index 0000000000000..3e7503ea95596 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Documentation/Core/html/index.html @@ -0,0 +1,241 @@ + + + + + +CMSIS-CORE: Overview + + + + + + + + + + + + + + +
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CMSIS-CORE +  Version 4.00 +
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CMSIS-CORE support for Cortex-M processor-based devices
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Overview
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CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

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  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
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  • System exception names to interface to system exceptions without having compatibility issues.
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  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
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  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
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  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
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  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
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This chapter provides details about the CMSIS-CORE and contains the following sections:

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CMSIS-CORE in ARM::CMSIS Pack

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Files relevant to CMSIS-CORE are present in the following ARM::CMSIS directories:

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File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Include CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device ARM reference implementations of Cortex-M devices
Device\_Template_Vendor Template Files for extension by silicon vendors
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+Cortex-M Reference Manuals

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The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

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Todo:
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+Tested and Verified Toolchains

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The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

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  • ARM: MDK-ARM Version 5.12
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  • GNU: GNU Tools ARM Embedded 4.8 2014.q3
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  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
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+

Revision History of CMSIS-CORE

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Version Description
V4.00 Added: Cortex-M7 support.
+ Added: intrinsic functions for __RRX, __LDRBT, __LDRHT, __LDRT, __STRBT, __STRHT, and __STRT
+
V3.40 Corrected: C++ include guard settings.
+
V3.30 Added: COSMIC tool chain support.
+ Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.
+ Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.
+ Corrected: GCC/CLang warnings.
+
V3.20 Added: __BKPT instruction intrinsic.
+ Added: __SMMLA instruction intrinsic for Cortex-M4.
+ Corrected: ITM_SendChar.
+ Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
+ Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.
+
V3.01 Added support for Cortex-M0+ processor.
+
V3.00 Added support for GNU GCC ARM Embedded Compiler.
+ Added function __ROR.
+ Added Register Mapping for TPIU, DWT.
+ Added support for SC000 and SC300 processors.
+ Corrected ITM_SendChar function.
+ Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
+ Documentation restructured.
V2.10 Updated documentation.
+ Updated CMSIS core include files.
+ Changed CMSIS/Device folder structure.
+ Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
+ Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
+ Added additional Debug Functionality.
+ Changed folder structure.
+ Added doxygen comments.
+ Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.
+
+
+ + + + diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/arm_common_tables.h b/atmel-samd/asf4/samd51/CMSIS/Include/arm_common_tables.h new file mode 100644 index 0000000000000..76aadca490198 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,136 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +//extern const q31_t realCoefAQ31[1024]; +//extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoef_16_q31[24]; +extern const q31_t twiddleCoef_32_q31[48]; +extern const q31_t twiddleCoef_64_q31[96]; +extern const q31_t twiddleCoef_128_q31[192]; +extern const q31_t twiddleCoef_256_q31[384]; +extern const q31_t twiddleCoef_512_q31[768]; +extern const q31_t twiddleCoef_1024_q31[1536]; +extern const q31_t twiddleCoef_2048_q31[3072]; +extern const q31_t twiddleCoef_4096_q31[6144]; +extern const q15_t twiddleCoef_16_q15[24]; +extern const q15_t twiddleCoef_32_q15[48]; +extern const q15_t twiddleCoef_64_q15[96]; +extern const q15_t twiddleCoef_128_q15[192]; +extern const q15_t twiddleCoef_256_q15[384]; +extern const q15_t twiddleCoef_512_q15[768]; +extern const q15_t twiddleCoef_1024_q15[1536]; +extern const q15_t twiddleCoef_2048_q15[3072]; +extern const q15_t twiddleCoef_4096_q15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +/* floating-point bit reversal tables */ +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* fixed-point bit reversal tables */ +#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) +#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) +#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) +#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) +#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) +#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) +#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) +#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/arm_const_structs.h b/atmel-samd/asf4/samd51/CMSIS/Include/arm_const_structs.h new file mode 100644 index 0000000000000..217f1d50e2607 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 31. July 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/arm_math.h b/atmel-samd/asf4/samd51/CMSIS/Include/arm_math.h new file mode 100644 index 0000000000000..49e23ee669353 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/arm_math.h @@ -0,0 +1,7544 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.4 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * ------------ + * + * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM_math.uvproj + * + * + * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * ------------ + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + *
+ * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | + * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | + * + *
+ * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + * + * Copyright Notice + * ------------ + * + * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + *
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + *
+ *     pData[i*numCols + j]
+ * 
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + *
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + *
+ *     ARM_MATH_SIZE_MISMATCH
+ * 
+ * Otherwise the functions return + *
+ *     ARM_MATH_SUCCESS
+ * 
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + *
+ *     ARM_MATH_MATRIX_CHECK
+ * 
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM7) + #include "core_cm7.h" +#elif defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY + #elif defined (ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE + #define ALIGN4 +#else + #if defined (__GNUC__) + #define ALIGN4 __attribute__((aligned(4))) + #else + #define ALIGN4 __align(4) + #endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __CSMC__ /* Cosmic */ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + /** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + static __INLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + static __INLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + static __INLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + static __INLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + + static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); + } + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + + static __INLINE uint32_t __CLZ( + q31_t data); + + + static __INLINE uint32_t __CLZ( + q31_t data) + { + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); + + } + +#endif + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + + static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + q31_t * pRecipTable) + { + + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); + + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + q15_t * pRecipTable) + { + + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + + } + + + /* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + + static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) + { + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + return (x); + + + } + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + + /* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + + /* + * @brief C custom defined QADD8 for M3 and M0 processors + */ + static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) + { + + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; + + } + + /* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t) x; + s = (q7_t) y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + + return sum; + } + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + + /* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ + static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + + } + + /* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ + static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) + { + + q31_t diff; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; + } + + /* + * @brief C custom defined QASX for M3 and M0 processors + */ + static __INLINE q31_t __QASX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHASX for M3 and M0 processors + */ + static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + + /* + * @brief C custom defined QSAX for M3 and M0 processors + */ + static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) + { + + q31_t sum = 0; + + sum = + ((sum + + clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + + clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); + + return sum; + } + + /* + * @brief C custom defined SHSAX for M3 and M0 processors + */ + static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) + { + + q31_t sum; + q31_t r, s; + + r = (q15_t) x; + s = (q15_t) y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; + } + + /* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined SMUADX for M3 and M0 processors + */ + static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) + { + + return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + + ((q15_t) (x >> 16) * (q15_t) y))); + } + + /* + * @brief C custom defined QADD for M3 and M0 processors + */ + static __INLINE q31_t __QADD( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x + y); + } + + /* + * @brief C custom defined QSUB for M3 and M0 processors + */ + static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) + { + return clip_q63_to_q31((q63_t) x - y); + } + + /* + * @brief C custom defined SMLAD for M3 and M0 processors + */ + static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLADX for M3 and M0 processors + */ + static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ + static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) + { + + return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + + ((q15_t) x * (q15_t) (y >> 16))); + } + + /* + * @brief C custom defined SMLALD for M3 and M0 processors + */ + static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + + ((q15_t) x * (q15_t) y)); + } + + /* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ + static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) + { + + return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + + ((q15_t) x * (q15_t) (y >> 16)); + } + + /* + * @brief C custom defined SMUAD for M3 and M0 processors + */ + static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) + { + + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + /* + * @brief C custom defined SMUSD for M3 and M0 processors + */ + static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) + { + + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); + } + + + /* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ + static __INLINE q31_t __SXTB16( + q31_t x) + { + + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); + } + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q15; + + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + + } arm_biquad_casd_df1_inst_f32; + + + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + + } arm_matrix_instance_q31; + + + + /** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + + /** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + + arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + + /** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + + void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q15; + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_q31; + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f32; + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + /** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + + void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + /** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + /** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_copy_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + + void arm_conv_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_conv_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + + void arm_conv_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + + arm_status arm_conv_partial_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR decimator. + */ + + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + + } arm_fir_decimate_instance_f32; + + + + /** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + + void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + float64_t * pCoeffs, + float64_t * pState); + + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pCoeffs, + float32_t * pState); + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_f32( + const arm_lms_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q15( + const arm_lms_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + + } arm_lms_instance_q31; + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_q31( + const arm_lms_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + /** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_f32( + float32_t * pSrcA, + uint32_t srcALen, + float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + void arm_correlate_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + + /** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + + void arm_correlate_fast_opt_q15( + q15_t * pSrcA, + uint32_t srcALen, + q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + /** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + /** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_fast_q31( + q31_t * pSrcA, + uint32_t srcALen, + q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + + void arm_correlate_opt_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + + void arm_correlate_q7( + q7_t * pSrcA, + uint32_t srcALen, + q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCcosVal); + + /* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_conj_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_squared_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + *
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + + + static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + + static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + + static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + + static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + + } + + /** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q31( + q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + + + static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; + + } + + /** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + + static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + + } + + /** + * @} end of inv_clarke group + */ + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ + void arm_q7_to_q15( + q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + + static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + + } + + /** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + + + static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q7_to_float( + q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + + static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + + } + + + /** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + + + static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + + } + + /** + * @} end of Inverse park group + */ + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_float( + q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + *
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + + static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + + } + + } + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + + + static __INLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } + + + } + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + + + static __INLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + + } + + } + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + + float32_t arm_sin_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q31_t arm_sin_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + + q15_t arm_sin_q15( + q15_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + + float32_t arm_cos_f32( + float32_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q31_t arm_cos_q31( + q31_t x); + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + + q15_t arm_cos_q15( + q15_t x); + + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + *
+   *      x1 = x0 - f(x0)/f'(x0)
+   * 
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + *
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
+ */ + + + /** + * @addtogroup SQRT + * @{ + */ + + /** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + + static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if(in > 0) + { + +// #if __FPU_USED +#if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + + } + + + /** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + /** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @} end of SQRT group + */ + + + + + + + /** + * @brief floating-point Circular write function. + */ + + static __INLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + static __INLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + /** + * @brief Q15 Circular write function. + */ + + static __INLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q15 Circular Read function. + */ + static __INLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + + static __INLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; + } + + + + /** + * @brief Q7 Circular Read function. + */ + static __INLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t) (dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t *) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q31( + q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q15( + q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_power_q7( + q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_mean_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + /** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + void arm_mean_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_var_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_rms_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + + void arm_std_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + /** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + + void arm_cmplx_mag_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + /** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + /** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + + void arm_cmplx_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q15( + q15_t * pSrcCmplx, + q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_q31( + q31_t * pSrcCmplx, + q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + + void arm_cmplx_mult_real_f32( + float32_t * pSrcCmplx, + float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + void arm_min_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + + void arm_min_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q7( + q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q15( + q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_q31( + q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + + void arm_max_f32( + float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + + void arm_cmplx_mult_cmplx_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ + void arm_float_to_q31( + float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q15( + float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ + void arm_float_to_q7( + float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q15( + q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q31_to_q7( + q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_float( + q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q31( + q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ + void arm_q15_to_q7( + q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + *
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + *
+   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
+ * \par + * The interpolated output point is computed as: + *
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + + + static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + + } + + /** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); + + } + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); + + } + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + + static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); + + } + + /** + * @} end of BilinearInterpolate group + */ + + +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//SMMLA +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) //Keil + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + +//Enter low optimization region - place directly above function definition + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition + #ifdef ARM_MATH_CM4 + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + +//Exit low optimization region - place directly after end of function definition + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) + + #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + + #define LOW_OPTIMIZATION_EXIT + + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__CSMC__) // Cosmic + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000000..5186cb4838824 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0.h @@ -0,0 +1,711 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0plus.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000000..17e43984fcf97 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,822 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm3.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000000..e1357c6735b08 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm3.h @@ -0,0 +1,1650 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm4.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000000..bb6be1305d27e --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm4.h @@ -0,0 +1,1802 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000 + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm7.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000000..242540f8b1187 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm7.h @@ -0,0 +1,2221 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 01. September 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0 + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBS control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmFunc.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmFunc.h new file mode 100644 index 0000000000000..01089f1333bd0 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,637 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmInstr.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmInstr.h new file mode 100644 index 0000000000000..d14110b2abd16 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,880 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.00 + * @date 28. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function executes a exclusive LDR instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (16 bit) + + This function executes a exclusive LDR instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDR Exclusive (32 bit) + + This function executes a exclusive LDR instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function executes a exclusive STR instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function executes a exclusive STR instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function executes a exclusive STR instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief Rotate Right with Extend (32 bit) + + This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief LDRT Unprivileged (8 bit) + + This function executes a Unprivileged LDRT instruction for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (16 bit) + + This function executes a Unprivileged LDRT instruction for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** \brief LDRT Unprivileged (32 bit) + + This function executes a Unprivileged LDRT instruction for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STRT Unprivileged (8 bit) + + This function executes a Unprivileged STRT instruction for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (16 bit) + + This function executes a Unprivileged STRT instruction for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** \brief STRT Unprivileged (32 bit) + + This function executes a Unprivileged STRT instruction for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmSimd.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmSimd.h new file mode 100644 index 0000000000000..ee58eee56dd77 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CMSIMD_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_sc000.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000000..5d0219c89f4bb --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_sc000.h @@ -0,0 +1,842 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_sc300.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000000..b6f6e8b5f2d80 --- /dev/null +++ b/atmel-samd/asf4/samd51/CMSIS/Include/core_sc300.h @@ -0,0 +1,1630 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 22. August 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/armcc/Makefile b/atmel-samd/asf4/samd51/armcc/Makefile new file mode 100644 index 0000000000000..e502d0314e8c1 --- /dev/null +++ b/atmel-samd/asf4/samd51/armcc/Makefile @@ -0,0 +1,280 @@ + +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif +endif + +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/adc \ +usb/class/cdc/device \ +hpl/ramecc \ +hpl/evsys \ +examples \ +hpl/systick \ +hpl/oscctrl \ +hpl/tc \ +hpl/osc32kctrl \ +usb \ +hpl/dmac \ +hal/src \ +hal/utils/src \ +hpl/rtc \ +hpl/trng \ +usb/class/hid/device \ +hpl/usb \ +hpl/mclk \ +hpl/gclk \ +usb/device \ +hpl/pm \ +hpl/dac \ +hpl/sercom \ +hpl/core + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hpl/systick/hpl_systick.o \ +usb/class/hid/device/hiddf_generic.o \ +hpl/evsys/hpl_evsys.o \ +hpl/core/hpl_core_m4.o \ +usb/class/cdc/device/cdcdf_acm.o \ +hpl/mclk/hpl_mclk.o \ +hal/src/hal_spi_m_sync.o \ +hal/src/hal_timer.o \ +hal/src/hal_pwm.o \ +hpl/usb/hpl_usb.o \ +hal/src/hal_i2c_m_sync.o \ +hal/src/hal_delay.o \ +hpl/pm/hpl_pm.o \ +hpl/core/hpl_init.o \ +hpl/ramecc/hpl_ramecc.o \ +hal/utils/src/utils_list.o \ +usb/class/hid/device/hiddf_mouse.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/oscctrl/hpl_oscctrl.o \ +hal/src/hal_rand_sync.o \ +hpl/trng/hpl_trng.o \ +usb/class/hid/device/hiddf_keyboard.o \ +hal/src/hal_usart_sync.o \ +hpl/dac/hpl_dac.o \ +hpl/gclk/hpl_gclk.o \ +usb/usb_protocol.o \ +hal/src/hal_init.o \ +hal/src/hal_usb_device.o \ +main.o \ +hpl/osc32kctrl/hpl_osc32kctrl.o \ +hpl/rtc/hpl_rtc.o \ +examples/driver_examples.o \ +driver_init.o \ +hal/src/hal_adc_sync.o \ +hal/src/hal_dac_sync.o \ +hpl/sercom/hpl_sercom.o \ +hal/src/hal_gpio.o \ +hal/src/hal_evsys.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +usb_start.o \ +atmel_start.o \ +usb/device/usbdc.o \ +hpl/tc/hpl_tc.o \ +hal/src/hal_atomic.o \ +hpl/adc/hpl_adc.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hpl/systick/hpl_systick.o" \ +"usb/class/hid/device/hiddf_generic.o" \ +"hpl/evsys/hpl_evsys.o" \ +"hpl/core/hpl_core_m4.o" \ +"usb/class/cdc/device/cdcdf_acm.o" \ +"hpl/mclk/hpl_mclk.o" \ +"hal/src/hal_spi_m_sync.o" \ +"hal/src/hal_timer.o" \ +"hal/src/hal_pwm.o" \ +"hpl/usb/hpl_usb.o" \ +"hal/src/hal_i2c_m_sync.o" \ +"hal/src/hal_delay.o" \ +"hpl/pm/hpl_pm.o" \ +"hpl/core/hpl_init.o" \ +"hpl/ramecc/hpl_ramecc.o" \ +"hal/utils/src/utils_list.o" \ +"usb/class/hid/device/hiddf_mouse.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/oscctrl/hpl_oscctrl.o" \ +"hal/src/hal_rand_sync.o" \ +"hpl/trng/hpl_trng.o" \ +"usb/class/hid/device/hiddf_keyboard.o" \ +"hal/src/hal_usart_sync.o" \ +"hpl/dac/hpl_dac.o" \ +"hpl/gclk/hpl_gclk.o" \ +"usb/usb_protocol.o" \ +"hal/src/hal_init.o" \ +"hal/src/hal_usb_device.o" \ +"main.o" \ +"hpl/osc32kctrl/hpl_osc32kctrl.o" \ +"hpl/rtc/hpl_rtc.o" \ +"examples/driver_examples.o" \ +"driver_init.o" \ +"hal/src/hal_adc_sync.o" \ +"hal/src/hal_dac_sync.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hal/src/hal_gpio.o" \ +"hal/src/hal_evsys.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"usb_start.o" \ +"atmel_start.o" \ +"usb/device/usbdc.o" \ +"hpl/tc/hpl_tc.o" \ +"hal/src/hal_atomic.o" \ +"hpl/adc/hpl_adc.o" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"hpl/ramecc/hpl_ramecc.d" \ +"hpl/systick/hpl_systick.d" \ +"hpl/core/hpl_core_m4.d" \ +"hpl/evsys/hpl_evsys.d" \ +"usb/class/cdc/device/cdcdf_acm.d" \ +"hal/src/hal_i2c_m_sync.d" \ +"hpl/usb/hpl_usb.d" \ +"hal/src/hal_evsys.d" \ +"hal/src/hal_pwm.d" \ +"hal/src/hal_timer.d" \ +"hal/src/hal_spi_m_sync.d" \ +"usb/class/hid/device/hiddf_mouse.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hpl/mclk/hpl_mclk.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/pm/hpl_pm.d" \ +"usb/usb_protocol.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hal/src/hal_usb_device.d" \ +"usb_start.d" \ +"hal/src/hal_init.d" \ +"hal/src/hal_usart_sync.d" \ +"usb/class/hid/device/hiddf_keyboard.d" \ +"hpl/trng/hpl_trng.d" \ +"hal/src/hal_rand_sync.d" \ +"hpl/dac/hpl_dac.d" \ +"driver_init.d" \ +"hal/src/hal_adc_sync.d" \ +"hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"main.d" \ +"examples/driver_examples.d" \ +"hpl/rtc/hpl_rtc.d" \ +"hal/src/hal_sleep.d" \ +"hpl/sercom/hpl_sercom.d" \ +"hal/src/hal_dac_sync.d" \ +"hal/src/hal_gpio.d" \ +"usb/class/hid/device/hiddf_generic.d" \ +"hal/src/hal_atomic.d" \ +"hpl/tc/hpl_tc.d" \ +"usb/device/usbdc.d" \ +"hpl/oscctrl/hpl_oscctrl.d" \ +"hpl/adc/hpl_adc.d" \ +"atmel_start.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARMCC Linker + $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ +--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ +--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ +-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \ +$(OBJS_AS_ARGS) + + @echo Finished building target: $@ + +# Compiler target(s) + + + + +%.o: %.c + @echo Building file: $< + @echo ARMCC Compiler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAMD51G19A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARMCC Assembler + $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAMD51G19A__ SETA 1" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +--depend "$(@:%.o=%.d)" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARMCC Preprocessing Assembler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAMD51G19A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/atmel-samd/asf4/samd51/atmel_start.c b/atmel-samd/asf4/samd51/atmel_start.c new file mode 100644 index 0000000000000..a075fcfa62c5d --- /dev/null +++ b/atmel-samd/asf4/samd51/atmel_start.c @@ -0,0 +1,10 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project +**/ +void atmel_start_init(void) +{ + system_init(); + usb_init(); +} diff --git a/atmel-samd/asf4/samd51/atmel_start.h b/atmel-samd/asf4/samd51/atmel_start.h new file mode 100644 index 0000000000000..71d54c217bc51 --- /dev/null +++ b/atmel-samd/asf4/samd51/atmel_start.h @@ -0,0 +1,19 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" +#include "usb_start.h" + +/** + * Initializes MCU, drivers and middleware in the project +**/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/atmel-samd/asf4/samd51/atmel_start_config.atstart b/atmel-samd/asf4/samd51/atmel_start_config.atstart new file mode 100644 index 0000000000000..ba77962954385 --- /dev/null +++ b/atmel-samd/asf4/samd51/atmel_start_config.atstart @@ -0,0 +1,1689 @@ +format_version: '2' +name: My Project +board: + identifier: CustomBoard + device: SAMD51G19A-MF +details: null +application: null +middlewares: + USB_CHAPTER_9: + user_label: USB_CHAPTER_9 + configuration: {} + definition: Atmel:USB:0.0.1::USB_Chapter_9 + functionality: USB_Chapter_9 + api: USB:Protocol:Core + dependencies: {} + USB_CLASS_HUB: + user_label: USB_CLASS_HUB + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_HUB + functionality: USB_Class_HUB + api: USB:Protocol:HUB + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_HID: + user_label: USB_CLASS_HID + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_HID + functionality: USB_Class_HID + api: USB:Protocol:HID + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_CDC: + user_label: USB_CLASS_CDC + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_CDC + functionality: USB_Class_CDC + api: USB:Protocol:CDC + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_MSC: + user_label: USB_CLASS_MSC + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_MSC + functionality: USB_Class_Mass_Storage_(MSC) + api: USB:Protocol:MSC + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_CLASS_VENDOR: + user_label: USB_CLASS_VENDOR + configuration: {} + definition: Atmel:USB:0.0.1::USB_Class_VENDOR + functionality: USB_Class_VENDOR + api: USB:Protocol:VENDOR + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB_DEVICE_STACK_CORE_INSTANCE: + user_label: USB_DEVICE_STACK_CORE_INSTANCE + configuration: {} + definition: Atmel:USB:0.0.1::USB_Device_Core + functionality: USB_Device_Core + api: USB:Device:Core + dependencies: + USB Chapter 9: USB_CHAPTER_9 + USB Device instance: USB_DEVICE_INSTANCE + USB_DEVICE_COMPOSITE_0: + user_label: USB_DEVICE_COMPOSITE_0 + configuration: + usb_composite_bcddevice: 256 + usb_composite_bcdusb: USB 2.0 version + usb_composite_bconfigval: 1 + usb_composite_bmattri: Bus power supply, not support for remote wakeup + usb_composite_bmaxpksz0: 64 bytes + usb_composite_bmaxpower: 50 + usb_composite_bnumconfig: 1 + usb_composite_cdc_acm_comm_int_maxpksz: 64 bytes + usb_composite_cdc_acm_data_buckout_maxpksz: 64 bytes + usb_composite_cdc_acm_data_builin_maxpksz: 64 bytes + usb_composite_cdc_acm_data_bulkin_epaddr: EndpointAddress = 0x81 + usb_composite_cdc_acm_data_bulkout_epaddr: EndpointAddress = 0x01 + usb_composite_cdc_acm_epaddr: EndpointAddress = 0x82 + usb_composite_cdc_acm_support: false + usb_composite_hid_generic_intin_epaddr: EndpointAddress = 0x85 + usb_composite_hid_generic_intin_maxpksz: 64 bytes + usb_composite_hid_generic_intout_epaddr: EndpointAddress = 0x03 + usb_composite_hid_generic_intout_maxpksz: 64 bytes + usb_composite_hid_generic_support: false + usb_composite_hid_keyboard_intin_epaddr: EndpointAddress = 0x84 + usb_composite_hid_keyboard_intin_maxpksz: 8 bytes + usb_composite_hid_keyboard_intout_epaddr: EndpointAddress = 0x02 + usb_composite_hid_keyboard_intout_maxpksz: 8 bytes + usb_composite_hid_keyboard_support: false + usb_composite_hid_mouse_intin_epaddr: EndpointAddress = 0x83 + usb_composite_hid_mouse_intin_maxpksz: 8 bytes + usb_composite_hid_mouse_support: false + usb_composite_iconfig: 0 + usb_composite_idproduct: 9249 + usb_composite_idvender: 1003 + usb_composite_imanufact: 0 + usb_composite_iproduct: 0 + usb_composite_iserialnum: 0 + definition: Atmel:USB:0.0.1::USB_Device_Composite + functionality: USB_Device_COMPOSITE + api: USB:Device:COMPOSITE + dependencies: + USB Class MSC: USB_CLASS_MSC + USB Class CDC: USB_CLASS_CDC + USB Device Stack Core Instance: USB_DEVICE_STACK_CORE_INSTANCE + USB Class VENDOR: USB_CLASS_VENDOR + USB Class HID: USB_CLASS_HID + USB Class HUB: USB_CLASS_HUB +drivers: + ADC_0: + user_label: ADC_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync + functionality: ADC + api: HAL:Driver:ADC_Sync + configuration: + adc_advanced_settings: false + adc_arch_adjres: 0 + adc_arch_corren: false + adc_arch_dbgrun: false + adc_arch_event_settings: false + adc_arch_flushei: false + adc_arch_flushinv: false + adc_arch_gaincorr: 0 + adc_arch_leftadj: false + adc_arch_offcomp: false + adc_arch_offsetcorr: 0 + adc_arch_ondemand: false + adc_arch_refcomp: false + adc_arch_resrdyeo: false + adc_arch_runstdby: false + adc_arch_samplen: 0 + adc_arch_samplenum: 1 sample + adc_arch_seqen: 0 + adc_arch_startei: false + adc_arch_startinv: false + adc_arch_winlt: 0 + adc_arch_winmode: No window mode + adc_arch_winmoneo: false + adc_arch_winut: 0 + adc_differential_mode: false + adc_freerunning_mode: false + adc_pinmux_negative: ADC AIN0 pin + adc_pinmux_positive: ADC AIN0 pin + adc_prescaler: Peripheral clock divided by 2 + adc_reference: Internal bandgap reference + adc_resolution: 12-bit + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: ADC + input: Generic clock generator 0 + configuration: + adc_gclk_selection: Generic clock generator 0 + DAC_0: + user_label: DAC_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::DAC::driver_config_definition::DAC::HAL:Driver:DAC.Sync + functionality: DAC + api: HAL:Driver:DAC_Sync + configuration: + adc_arch_dbgrun: true + dac0_arch_cctrl: GCLK_DAC <= 1.2MHz (100kSPS) + dac0_arch_ditrher: false + dac0_arch_leftadj: false + dac0_arch_refresh: 0 + dac0_arch_runstdby: false + dac1_arch_cctrl: GCLK_DAC <= 1.2MHz (100kSPS) + dac1_arch_ditrher: false + dac1_arch_leftadj: false + dac1_arch_refresh: 0 + dac1_arch_runstdby: false + dac_advanced_settings: false + dac_arch_diff: false + dac_arch_emptyeo_0: false + dac_arch_emptyeo_1: false + dac_arch_invei0: Detection on rising edge pf the input event + dac_arch_invei1: Detection on rising edge pf the input event + dac_arch_refsel: Unbuffered external voltage reference + dac_arch_startei_0: false + dac_arch_startei_1: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: DAC + input: Generic clock generator 0 + configuration: + dac_gclk_selection: Generic clock generator 0 + DMAC: + user_label: DMAC + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: false + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: false + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: false + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: true + dmac_lvlen3: true + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: false + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + EVENT_SYSTEM_0: + user_label: EVENT_SYSTEM_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system + functionality: Event_System + api: HAL:Driver:Event_system + configuration: + evsys_channel_0: No channel output selected + evsys_channel_1: No channel output selected + evsys_channel_10: No channel output selected + evsys_channel_11: No channel output selected + evsys_channel_12: No channel output selected + evsys_channel_17: No channel output selected + evsys_channel_18: No channel output selected + evsys_channel_19: No channel output selected + evsys_channel_2: No channel output selected + evsys_channel_20: No channel output selected + evsys_channel_21: No channel output selected + evsys_channel_22: No channel output selected + evsys_channel_23: No channel output selected + evsys_channel_24: No channel output selected + evsys_channel_25: No channel output selected + evsys_channel_26: No channel output selected + evsys_channel_27: No channel output selected + evsys_channel_28: No channel output selected + evsys_channel_29: No channel output selected + evsys_channel_3: No channel output selected + evsys_channel_30: No channel output selected + evsys_channel_31: No channel output selected + evsys_channel_32: No channel output selected + evsys_channel_33: No channel output selected + evsys_channel_34: No channel output selected + evsys_channel_35: No channel output selected + evsys_channel_36: No channel output selected + evsys_channel_37: No channel output selected + evsys_channel_38: No channel output selected + evsys_channel_39: No channel output selected + evsys_channel_4: No channel output selected + evsys_channel_40: No channel output selected + evsys_channel_41: No channel output selected + evsys_channel_42: No channel output selected + evsys_channel_43: No channel output selected + evsys_channel_44: No channel output selected + evsys_channel_45: No channel output selected + evsys_channel_46: No channel output selected + evsys_channel_47: No channel output selected + evsys_channel_48: No channel output selected + evsys_channel_49: No channel output selected + evsys_channel_5: No channel output selected + evsys_channel_50: No channel output selected + evsys_channel_51: No channel output selected + evsys_channel_52: No channel output selected + evsys_channel_53: No channel output selected + evsys_channel_54: No channel output selected + evsys_channel_55: No channel output selected + evsys_channel_56: No channel output selected + evsys_channel_57: No channel output selected + evsys_channel_58: No channel output selected + evsys_channel_59: No channel output selected + evsys_channel_6: No channel output selected + evsys_channel_60: No channel output selected + evsys_channel_61: No channel output selected + evsys_channel_62: No channel output selected + evsys_channel_63: No channel output selected + evsys_channel_64: No channel output selected + evsys_channel_65: No channel output selected + evsys_channel_66: No channel output selected + evsys_channel_7: No channel output selected + evsys_channel_8: No channel output selected + evsys_channel_9: No channel output selected + evsys_channel_setting_0: false + evsys_channel_setting_1: false + evsys_channel_setting_10: false + evsys_channel_setting_11: false + evsys_channel_setting_12: false + evsys_channel_setting_13: false + evsys_channel_setting_14: false + evsys_channel_setting_15: false + evsys_channel_setting_16: false + evsys_channel_setting_17: false + evsys_channel_setting_18: false + evsys_channel_setting_19: false + evsys_channel_setting_2: false + evsys_channel_setting_20: false + evsys_channel_setting_21: false + evsys_channel_setting_22: false + evsys_channel_setting_23: false + evsys_channel_setting_24: false + evsys_channel_setting_25: false + evsys_channel_setting_26: false + evsys_channel_setting_27: false + evsys_channel_setting_28: false + evsys_channel_setting_29: false + evsys_channel_setting_3: false + evsys_channel_setting_30: false + evsys_channel_setting_31: false + evsys_channel_setting_4: false + evsys_channel_setting_5: false + evsys_channel_setting_6: false + evsys_channel_setting_7: false + evsys_channel_setting_8: false + evsys_channel_setting_9: false + evsys_edgsel_0: No event output when using the resynchronized or synchronous + path + evsys_edgsel_1: No event output when using the resynchronized or synchronous + path + evsys_edgsel_10: No event output when using the resynchronized or synchronous + path + evsys_edgsel_11: No event output when using the resynchronized or synchronous + path + evsys_edgsel_12: No event output when using the resynchronized or synchronous + path + evsys_edgsel_13: No event output when using the resynchronized or synchronous + path + evsys_edgsel_14: No event output when using the resynchronized or synchronous + path + evsys_edgsel_15: No event output when using the resynchronized or synchronous + path + evsys_edgsel_16: No event output when using the resynchronized or synchronous + path + evsys_edgsel_17: No event output when using the resynchronized or synchronous + path + evsys_edgsel_18: No event output when using the resynchronized or synchronous + path + evsys_edgsel_19: No event output when using the resynchronized or synchronous + path + evsys_edgsel_2: No event output when using the resynchronized or synchronous + path + evsys_edgsel_20: No event output when using the resynchronized or synchronous + path + evsys_edgsel_21: No event output when using the resynchronized or synchronous + path + evsys_edgsel_22: No event output when using the resynchronized or synchronous + path + evsys_edgsel_23: No event output when using the resynchronized or synchronous + path + evsys_edgsel_24: No event output when using the resynchronized or synchronous + path + evsys_edgsel_25: No event output when using the resynchronized or synchronous + path + evsys_edgsel_26: No event output when using the resynchronized or synchronous + path + evsys_edgsel_27: No event output when using the resynchronized or synchronous + path + evsys_edgsel_28: No event output when using the resynchronized or synchronous + path + evsys_edgsel_29: No event output when using the resynchronized or synchronous + path + evsys_edgsel_3: No event output when using the resynchronized or synchronous + path + evsys_edgsel_30: No event output when using the resynchronized or synchronous + path + evsys_edgsel_31: No event output when using the resynchronized or synchronous + path + evsys_edgsel_4: No event output when using the resynchronized or synchronous + path + evsys_edgsel_5: No event output when using the resynchronized or synchronous + path + evsys_edgsel_6: No event output when using the resynchronized or synchronous + path + evsys_edgsel_7: No event output when using the resynchronized or synchronous + path + evsys_edgsel_8: No event output when using the resynchronized or synchronous + path + evsys_edgsel_9: No event output when using the resynchronized or synchronous + path + evsys_evd_0: false + evsys_evd_1: false + evsys_evd_10: false + evsys_evd_11: false + evsys_evd_12: false + evsys_evd_13: false + evsys_evd_14: false + evsys_evd_15: false + evsys_evd_16: false + evsys_evd_17: false + evsys_evd_18: false + evsys_evd_19: false + evsys_evd_2: false + evsys_evd_20: false + evsys_evd_21: false + evsys_evd_22: false + evsys_evd_23: false + evsys_evd_24: false + evsys_evd_25: false + evsys_evd_26: false + evsys_evd_27: false + evsys_evd_28: false + evsys_evd_29: false + evsys_evd_3: false + evsys_evd_30: false + evsys_evd_31: false + evsys_evd_4: false + evsys_evd_5: false + evsys_evd_6: false + evsys_evd_7: false + evsys_evd_8: false + evsys_evd_9: false + evsys_evgen_0: No event generator + evsys_evgen_1: No event generator + evsys_evgen_10: No event generator + evsys_evgen_11: No event generator + evsys_evgen_12: No event generator + evsys_evgen_13: No event generator + evsys_evgen_14: No event generator + evsys_evgen_15: No event generator + evsys_evgen_16: No event generator + evsys_evgen_17: No event generator + evsys_evgen_18: No event generator + evsys_evgen_19: No event generator + evsys_evgen_2: No event generator + evsys_evgen_20: No event generator + evsys_evgen_21: No event generator + evsys_evgen_22: No event generator + evsys_evgen_23: No event generator + evsys_evgen_24: No event generator + evsys_evgen_25: No event generator + evsys_evgen_26: No event generator + evsys_evgen_27: No event generator + evsys_evgen_28: No event generator + evsys_evgen_29: No event generator + evsys_evgen_3: No event generator + evsys_evgen_30: No event generator + evsys_evgen_31: No event generator + evsys_evgen_4: No event generator + evsys_evgen_5: No event generator + evsys_evgen_6: No event generator + evsys_evgen_7: No event generator + evsys_evgen_8: No event generator + evsys_evgen_9: No event generator + evsys_ondemand_0: false + evsys_ondemand_1: false + evsys_ondemand_10: false + evsys_ondemand_11: false + evsys_ondemand_12: false + evsys_ondemand_13: false + evsys_ondemand_14: false + evsys_ondemand_15: false + evsys_ondemand_16: false + evsys_ondemand_17: false + evsys_ondemand_18: false + evsys_ondemand_19: false + evsys_ondemand_2: false + evsys_ondemand_20: false + evsys_ondemand_21: false + evsys_ondemand_22: false + evsys_ondemand_23: false + evsys_ondemand_24: false + evsys_ondemand_25: false + evsys_ondemand_26: false + evsys_ondemand_27: false + evsys_ondemand_28: false + evsys_ondemand_29: false + evsys_ondemand_3: false + evsys_ondemand_30: false + evsys_ondemand_31: false + evsys_ondemand_4: false + evsys_ondemand_5: false + evsys_ondemand_6: false + evsys_ondemand_7: false + evsys_ondemand_8: false + evsys_ondemand_9: false + evsys_ovr_0: false + evsys_ovr_1: false + evsys_ovr_10: false + evsys_ovr_11: false + evsys_ovr_12: false + evsys_ovr_13: false + evsys_ovr_14: false + evsys_ovr_15: false + evsys_ovr_16: false + evsys_ovr_17: false + evsys_ovr_18: false + evsys_ovr_19: false + evsys_ovr_2: false + evsys_ovr_20: false + evsys_ovr_21: false + evsys_ovr_22: false + evsys_ovr_23: false + evsys_ovr_24: false + evsys_ovr_25: false + evsys_ovr_26: false + evsys_ovr_27: false + evsys_ovr_28: false + evsys_ovr_29: false + evsys_ovr_3: false + evsys_ovr_30: false + evsys_ovr_31: false + evsys_ovr_4: false + evsys_ovr_5: false + evsys_ovr_6: false + evsys_ovr_7: false + evsys_ovr_8: false + evsys_ovr_9: false + evsys_path_0: Synchronous path + evsys_path_1: Synchronous path + evsys_path_10: Synchronous path + evsys_path_11: Synchronous path + evsys_path_12: Synchronous path + evsys_path_13: Synchronous path + evsys_path_14: Synchronous path + evsys_path_15: Synchronous path + evsys_path_16: Synchronous path + evsys_path_17: Synchronous path + evsys_path_18: Synchronous path + evsys_path_19: Synchronous path + evsys_path_2: Synchronous path + evsys_path_20: Synchronous path + evsys_path_21: Synchronous path + evsys_path_22: Synchronous path + evsys_path_23: Synchronous path + evsys_path_24: Synchronous path + evsys_path_25: Synchronous path + evsys_path_26: Synchronous path + evsys_path_27: Synchronous path + evsys_path_28: Synchronous path + evsys_path_29: Synchronous path + evsys_path_3: Synchronous path + evsys_path_30: Synchronous path + evsys_path_31: Synchronous path + evsys_path_4: Synchronous path + evsys_path_5: Synchronous path + evsys_path_6: Synchronous path + evsys_path_7: Synchronous path + evsys_path_8: Synchronous path + evsys_path_9: Synchronous path + evsys_runstdby_0: false + evsys_runstdby_1: false + evsys_runstdby_10: false + evsys_runstdby_11: false + evsys_runstdby_12: false + evsys_runstdby_13: false + evsys_runstdby_14: false + evsys_runstdby_15: false + evsys_runstdby_16: false + evsys_runstdby_17: false + evsys_runstdby_18: false + evsys_runstdby_19: false + evsys_runstdby_2: false + evsys_runstdby_20: false + evsys_runstdby_21: false + evsys_runstdby_22: false + evsys_runstdby_23: false + evsys_runstdby_24: false + evsys_runstdby_25: false + evsys_runstdby_26: false + evsys_runstdby_27: false + evsys_runstdby_28: false + evsys_runstdby_29: false + evsys_runstdby_3: false + evsys_runstdby_30: false + evsys_runstdby_31: false + evsys_runstdby_4: false + evsys_runstdby_5: false + evsys_runstdby_6: false + evsys_runstdby_7: false + evsys_runstdby_8: false + evsys_runstdby_9: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: Channel 0 + input: Generic clock generator 0 + - name: Channel 1 + input: Generic clock generator 0 + - name: Channel 2 + input: Generic clock generator 0 + - name: Channel 3 + input: Generic clock generator 0 + - name: Channel 4 + input: Generic clock generator 0 + - name: Channel 5 + input: Generic clock generator 0 + - name: Channel 6 + input: Generic clock generator 0 + - name: Channel 7 + input: Generic clock generator 0 + - name: Channel 8 + input: Generic clock generator 0 + - name: Channel 9 + input: Generic clock generator 0 + - name: Channel 10 + input: Generic clock generator 0 + - name: Channel 11 + input: Generic clock generator 0 + configuration: + evsys_clk_selection_0: Generic clock generator 0 + evsys_clk_selection_1: Generic clock generator 0 + evsys_clk_selection_10: Generic clock generator 0 + evsys_clk_selection_11: Generic clock generator 0 + evsys_clk_selection_2: Generic clock generator 0 + evsys_clk_selection_3: Generic clock generator 0 + evsys_clk_selection_4: Generic clock generator 0 + evsys_clk_selection_5: Generic clock generator 0 + evsys_clk_selection_6: Generic clock generator 0 + evsys_clk_selection_7: Generic clock generator 0 + evsys_clk_selection_8: Generic clock generator 0 + evsys_clk_selection_9: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + enable_gclk_gen_0: true + enable_gclk_gen_1: false + enable_gclk_gen_10: false + enable_gclk_gen_11: false + enable_gclk_gen_2: false + enable_gclk_gen_3: false + enable_gclk_gen_4: false + enable_gclk_gen_5: false + enable_gclk_gen_6: false + enable_gclk_gen_7: false + enable_gclk_gen_8: false + enable_gclk_gen_9: false + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: true + gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '0' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: false + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: true + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: false + xosc32k_arch_enable: false + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 62592us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: false + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: false + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 3 + enable_dfll: false + enable_fdpll0: false + enable_fdpll1: false + enable_xosc0: false + enable_xosc1: true + fdpll0_arch_dcoen: false + fdpll0_arch_enable: false + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: false + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 1463 + fdpll0_ldrfrac: 13 + fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_arch_dcoen: false + fdpll1_arch_enable: false + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 1463 + fdpll1_ldrfrac: 13 + fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: true + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 31us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RTC::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + rtc_arch_comp_val: 1 + rtc_arch_prescaler: OFF(Peripheral clock divided by 1) + rtc_cmpeo0: false + rtc_cmpeo1: false + rtc_event_control: false + rtc_ovfeo: false + rtc_pereo0: false + rtc_pereo1: false + rtc_pereo2: false + rtc_pereo3: false + rtc_pereo4: false + rtc_pereo5: false + rtc_pereo6: false + rtc_pereo7: false + rtc_tampereo: false + rtc_tampevei: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: RTC + input: RTC source + configuration: + rtc_clk_selection: RTC source + SPI_0: + user_label: SPI_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM0::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync + functionality: SPI + api: HAL:Driver:SPI_Master_Sync + configuration: + spi_master_advanced: false + spi_master_arch_cpha: Sample input on leading edge + spi_master_arch_cpol: SCK is low when idle + spi_master_arch_dbgstop: Keep running + spi_master_arch_dord: MSB first + spi_master_arch_ibon: In data stream + spi_master_arch_runstdby: false + spi_master_baud_rate: 50000 + spi_master_character_size: 8 bits + spi_master_dummybyte: 511 + spi_master_rx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=2 + required_signals: + - name: SERCOM0/PAD/0 + pad: PA04 + label: MOSI + - name: SERCOM0/PAD/1 + pad: PA05 + label: SCK + - name: SERCOM0/PAD/2 + pad: PA06 + label: MISO + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + - name: Slow + input: Generic clock generator 3 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM0/PAD/0 + pad: PA08 + label: SDA + - name: SERCOM0/PAD/1 + pad: PA09 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + - name: Slow + input: Generic clock generator 3 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + USART_0: + user_label: USART_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM1::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 9600 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM1/PAD/0 + pad: PA00 + label: TX + - name: SERCOM1/PAD/1 + pad: PA01 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + - name: Slow + input: Generic clock generator 3 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + DELAY_0: + user_label: DELAY_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay + functionality: Delay + api: HAL:Driver:Delay + configuration: + systick_arch_tickint: false + optional_signals: [] + variant: null + clocks: + domain_group: null + PWM_0: + user_label: PWM_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::TC0::driver_config_definition::PWM::HAL:Driver:PWM + functionality: PWM + api: HAL:Driver:PWM + configuration: + tc_arch_alock: The Lock Update bit is not affected on overflow/underflow and + re-trigger event + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_ondemand: false + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tcinv: false + tc_arch_wave_duty_val: 500 + tc_arch_wave_per_val: 1000 + tc_mode: Counter in 16-bit mode + tc_per: 50 + tc_prescaler: No division + timer_event_control: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + configuration: + tc_gclk_selection: Generic clock generator 0 + RAND_0: + user_label: RAND_0 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::TRNG::driver_config_definition::RAND::HAL:Driver:RAND.Sync + functionality: RAND + api: HAL:Driver:RAND_Sync + configuration: + trng_datardyeo: false + trng_runstdby: false + optional_signals: [] + variant: null + clocks: + domain_group: null + USB_DEVICE_INSTANCE: + user_label: USB_DEVICE_INSTANCE + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device + functionality: USB + api: HAL:Driver:USB_Device + configuration: + usb_arch_ep0_cache: Cached by 64 bytes buffer + usb_arch_ep1_cache: Cached by 64 bytes buffer + usb_arch_ep2_cache: Cached by 64 bytes buffer + usb_arch_ep3_cache: Cached by 64 bytes buffer + usb_arch_ep4_cache: Cached by 64 bytes buffer + usb_arch_ep5_cache: Cached by 64 bytes buffer + usb_arch_ep6_cache: Cached by 64 bytes buffer + usb_arch_ep7_cache: Cached by 64 bytes buffer + usb_ep1_I_CACHE: No cache + usb_ep2_I_CACHE: No cache + usb_ep3_I_CACHE: No cache + usb_ep4_I_CACHE: No cache + usb_ep5_I_CACHE: No cache + usb_ep6_I_CACHE: No cache + usb_ep7_I_CACHE: No cache + usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02) + usbd_arch_speed: Full speed + usbd_num_ep_sp: 4 (EP0 + 3 endpoints) + optional_signals: [] + variant: + specification: default + required_signals: + - name: USB/DM + pad: PA24 + label: Data- + - name: USB/DP + pad: PA25 + label: Data+ + clocks: + domain_group: + nodes: + - name: USB + input: Generic clock generator 0 + configuration: + usb_gclk_selection: Generic clock generator 0 +pads: + PA00: + name: PA00 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA00 + mode: Peripheral IO + user_label: PA00 + configuration: null + PA01: + name: PA01 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA01 + mode: Peripheral IO + user_label: PA01 + configuration: null + PA04: + name: PA04 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA04 + mode: Digital output + user_label: PA04 + configuration: null + PA05: + name: PA05 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA05 + mode: Digital output + user_label: PA05 + configuration: null + PA06: + name: PA06 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA06 + mode: Digital input + user_label: PA06 + configuration: null + PA08: + name: PA08 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA08 + mode: Peripheral IO + user_label: PA08 + configuration: null + PA09: + name: PA09 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA09 + mode: Peripheral IO + user_label: PA09 + configuration: null + PA24: + name: PA24 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA24 + mode: Advanced + user_label: PA24 + configuration: null + PA25: + name: PA25 + definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA25 + mode: Advanced + user_label: PA25 + configuration: null +toolchain_options: [] diff --git a/atmel-samd/asf4/samd51/atmel_start_pins.h b/atmel-samd/asf4/samd51/atmel_start_pins.h new file mode 100644 index 0000000000000..edfe8887715fe --- /dev/null +++ b/atmel-samd/asf4/samd51/atmel_start_pins.h @@ -0,0 +1,40 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAMD51 has 14 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 +#define GPIO_PIN_FUNCTION_J 9 +#define GPIO_PIN_FUNCTION_K 10 +#define GPIO_PIN_FUNCTION_L 11 +#define GPIO_PIN_FUNCTION_M 12 +#define GPIO_PIN_FUNCTION_N 13 + +#define PA00 GPIO(GPIO_PORTA, 0) +#define PA01 GPIO(GPIO_PORTA, 1) +#define PA04 GPIO(GPIO_PORTA, 4) +#define PA05 GPIO(GPIO_PORTA, 5) +#define PA06 GPIO(GPIO_PORTA, 6) +#define PA08 GPIO(GPIO_PORTA, 8) +#define PA09 GPIO(GPIO_PORTA, 9) +#define PA24 GPIO(GPIO_PORTA, 24) +#define PA25 GPIO(GPIO_PORTA, 25) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/atmel-samd/asf4/samd51/config/hpl_adc_config.h b/atmel-samd/asf4/samd51/config/hpl_adc_config.h new file mode 100644 index 0000000000000..941c3ffdb36cb --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_adc_config.h @@ -0,0 +1,303 @@ +/* Auto-generated config file hpl_adc_config.h */ +#ifndef HPL_ADC_CONFIG_H +#define HPL_ADC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_ADC_0_ENABLE +#define CONF_ADC_0_ENABLE 1 +#endif + +// Basic Configuration + +// Conversion Result Resolution +// <0x0=>12-bit +// <0x1=>16-bit (averaging must be enabled) +// <0x2=>10-bit +// <0x3=>8-bit +// Defines the bit resolution for the ADC sample values (RESSEL) +// adc_resolution +#ifndef CONF_ADC_0_RESSEL +#define CONF_ADC_0_RESSEL 0x0 +#endif + +// Reference Selection +// <0x0=>Internal bandgap reference +// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) +// <0x3=>VDDANA +// <0x4=>External reference A +// <0x5=>External reference B +// <0x6=>External reference C +// Select the reference for the ADC (REFSEL) +// adc_reference +#ifndef CONF_ADC_0_REFSEL +#define CONF_ADC_0_REFSEL 0x0 +#endif + +// Prescaler configuration +// <0x0=>Peripheral clock divided by 2 +// <0x1=>Peripheral clock divided by 4 +// <0x2=>Peripheral clock divided by 8 +// <0x3=>Peripheral clock divided by 16 +// <0x4=>Peripheral clock divided by 32 +// <0x5=>Peripheral clock divided by 64 +// <0x6=>Peripheral clock divided by 128 +// <0x7=>Peripheral clock divided by 256 +// These bits define the ADC clock relative to the peripheral clock (PRESCALER) +// adc_prescaler +#ifndef CONF_ADC_0_PRESCALER +#define CONF_ADC_0_PRESCALER 0x0 +#endif + +// Free Running Mode +// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) +// adc_freerunning_mode +#ifndef CONF_ADC_0_FREERUN +#define CONF_ADC_0_FREERUN 0 +#endif + +// Differential Mode +// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) +// adc_differential_mode +#ifndef CONF_ADC_0_DIFFMODE +#define CONF_ADC_0_DIFFMODE 0 +#endif + +// Positive Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x08=>ADC AIN8 pin +// <0x09=>ADC AIN9 pin +// <0x0A=>ADC AIN10 pin +// <0x0B=>ADC AIN11 pin +// <0x0C=>ADC AIN12 pin +// <0x0D=>ADC AIN13 pin +// <0x0E=>ADC AIN14 pin +// <0x0F=>ADC AIN15 pin +// <0x18=>1/4 scaled core supply +// <0x19=>1/4 Scaled VBAT Supply +// <0x1A=>1/4 scaled I/O supply +// <0x1B=>Bandgap voltage +// <0x1C=>Temperature reference (PTAT) +// <0x1D=>Temperature reference (CTAT) +// <0x1E=>DAC Output +// These bits define the Mux selection for the positive ADC input. (MUXPOS) +// adc_pinmux_positive +#ifndef CONF_ADC_0_MUXPOS +#define CONF_ADC_0_MUXPOS 0x0 +#endif + +// Negative Mux Input Selection +// <0x00=>ADC AIN0 pin +// <0x01=>ADC AIN1 pin +// <0x02=>ADC AIN2 pin +// <0x03=>ADC AIN3 pin +// <0x04=>ADC AIN4 pin +// <0x05=>ADC AIN5 pin +// <0x06=>ADC AIN6 pin +// <0x07=>ADC AIN7 pin +// <0x18=>Internal ground +// <0x19=>I/O ground +// These bits define the Mux selection for the negative ADC input. (MUXNEG) +// adc_pinmux_negative +#ifndef CONF_ADC_0_MUXNEG +#define CONF_ADC_0_MUXNEG 0x0 +#endif + +// + +// Advanced Configuration +// adc_advanced_settings +#ifndef CONF_ADC_0_ADVANCED +#define CONF_ADC_0_ADVANCED 0 +#endif + +// Run in standby +// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) +// adc_arch_runstdby +#ifndef CONF_ADC_0_RUNSTDBY +#define CONF_ADC_0_RUNSTDBY 0 +#endif + +// Debug Run +// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) +// adc_arch_dbgrun +#ifndef CONF_ADC_0_DBGRUN +#define CONF_ADC_0_DBGRUN 0 +#endif + +// On Demand Control +// Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND) +// adc_arch_ondemand +#ifndef CONF_ADC_0_ONDEMAND +#define CONF_ADC_0_ONDEMAND 0 +#endif + +// Left-Adjusted Result +// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) +// adc_arch_leftadj +#ifndef CONF_ADC_0_LEFTADJ +#define CONF_ADC_0_LEFTADJ 0 +#endif + +// Reference Buffer Offset Compensation Enable +// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) +// adc_arch_refcomp +#ifndef CONF_ADC_0_REFCOMP +#define CONF_ADC_0_REFCOMP 0 +#endif + +// Comparator Offset Compensation Enable +// This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP) +// adc_arch_offcomp +#ifndef CONF_ADC_0_OFFCOMP +#define CONF_ADC_0_OFFCOMP 0 +#endif + +// Digital Correction Logic Enabled +// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) +// adc_arch_corren +#ifndef CONF_ADC_0_CORREN +#define CONF_ADC_0_CORREN 0 +#endif + +// Offset Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) +// adc_arch_offsetcorr +#ifndef CONF_ADC_0_OFFSETCORR +#define CONF_ADC_0_OFFSETCORR 0 +#endif + +// Gain Correction Value <0-4095> +// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) +// adc_arch_gaincorr +#ifndef CONF_ADC_0_GAINCORR +#define CONF_ADC_0_GAINCORR 0 +#endif + +// Adjusting Result / Division Coefficient <0-7> +// These bits define the division coefficient in 2n steps. (ADJRES) +// adc_arch_adjres +#ifndef CONF_ADC_0_ADJRES +#define CONF_ADC_0_ADJRES 0x0 +#endif + +// Number of Samples to be Collected +// <0x0=>1 sample +// <0x1=>2 samples +// <0x2=>4 samples +// <0x3=>8 samples +// <0x4=>16 samples +// <0x5=>32 samples +// <0x6=>64 samples +// <0x7=>128 samples +// <0x8=>256 samples +// <0x9=>512 samples +// <0xA=>1024 samples +// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) +// adc_arch_samplenum +#ifndef CONF_ADC_0_SAMPLENUM +#define CONF_ADC_0_SAMPLENUM 0x0 +#endif + +// Sampling Time Length <0-63> +// These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) +// adc_arch_samplen +#ifndef CONF_ADC_0_SAMPLEN +#define CONF_ADC_0_SAMPLEN 0 +#endif + +// Window Monitor Mode +// <0x0=>No window mode +// <0x1=>Mode 1: RESULT above lower threshold +// <0x2=>Mode 2: RESULT beneath upper threshold +// <0x3=>Mode 3: RESULT inside lower and upper threshold +// <0x4=>Mode 4: RESULT outside lower and upper threshold +// These bits enable and define the window monitor mode. (WINMODE) +// adc_arch_winmode +#ifndef CONF_ADC_0_WINMODE +#define CONF_ADC_0_WINMODE 0x0 +#endif + +// Window Monitor Lower Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINLT) +// adc_arch_winlt +#ifndef CONF_ADC_0_WINLT +#define CONF_ADC_0_WINLT 0 +#endif + +// Window Monitor Upper Threshold <0-65535> +// If the window monitor is enabled, these bits define the lower threshold value. (WINUT) +// adc_arch_winut +#ifndef CONF_ADC_0_WINUT +#define CONF_ADC_0_WINUT 0 +#endif + +// Bitmask for positive input sequence <0-524288> +// Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device). +// adc_arch_seqen +#ifndef CONF_ADC_0_SEQEN +#define CONF_ADC_0_SEQEN 0x0 +#endif + +// + +// Event Control +// adc_arch_event_settings +#ifndef CONF_ADC_0_EVENT_CONTROL +#define CONF_ADC_0_EVENT_CONTROL 0 +#endif + +// Window Monitor Event Out +// Enables event output on window event (WINMONEO) +// adc_arch_winmoneo +#ifndef CONF_ADC_0_WINMONEO +#define CONF_ADC_0_WINMONEO 0 +#endif + +// Result Ready Event Out +// Enables event output on result ready event (RESRDEO) +// adc_arch_resrdyeo +#ifndef CONF_ADC_0_RESRDYEO +#define CONF_ADC_0_RESRDYEO 0 +#endif + +// Invert flush Event Signal +// Invert the flush event input signal (FLUSHINV) +// adc_arch_flushinv +#ifndef CONF_ADC_0_FLUSHINV +#define CONF_ADC_0_FLUSHINV 0 +#endif + +// Trigger Flush On Event +// Trigger an ADC pipeline flush on event (FLUSHEI) +// adc_arch_flushei +#ifndef CONF_ADC_0_FLUSHEI +#define CONF_ADC_0_FLUSHEI 0 +#endif + +// Invert Start Conversion Event Signal +// Invert the start conversion event input signal (STARTINV) +// adc_arch_startinv +#ifndef CONF_ADC_0_STARTINV +#define CONF_ADC_0_STARTINV 0 +#endif + +// Trigger Conversion On Event +// Trigger a conversion on event. (STARTEI) +// adc_arch_startei +#ifndef CONF_ADC_0_STARTEI +#define CONF_ADC_0_STARTEI 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_ADC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_dac_config.h b/atmel-samd/asf4/samd51/config/hpl_dac_config.h new file mode 100644 index 0000000000000..24a8a116cc427 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_dac_config.h @@ -0,0 +1,169 @@ +/* Auto-generated config file hpl_dac_config.h */ +#ifndef HPL_DAC_CONFIG_H +#define HPL_DAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic configuration +// Reference Selection +// <0x00=> Unbuffered external voltage reference +// <0x01=> Voltage supply +// <0x02=> Buffered external voltage reference +// <0x03=> Internal bandgap reference +// dac_arch_refsel +#ifndef CONF_DAC_REFSEL +#define CONF_DAC_REFSEL 0 +#endif + +// Differential mode +// Indicates whether the differential mode is enabled or not +// dac_arch_diff +#ifndef CONF_DAC_DIFF +#define CONF_DAC_DIFF 0 +#endif +// + +// Advanced Configuration +// dac_advanced_settings +#ifndef CONF_DAC_ADVANCED_CONFIG +#define CONF_DAC_ADVANCED_CONFIG 0 +#endif + +// Debug Run +// Indicate whether running when CPU is halted +// adc_arch_dbgrun +#ifndef CONF_DAC_DBGRUN +#define CONF_DAC_DBGRUN 1 +#endif + +// Channel 0 configuration +// Left Adjusted Data +// Indicate how the data is adjusted in the Data and Data Buffer register +// dac0_arch_leftadj +#ifndef CONF_DAC0_LEFTADJ +#define CONF_DAC0_LEFTADJ 0 +#endif + +// Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// This defines the current in output buffer according to conversion rate +// dac0_arch_cctrl +#ifndef CONF_DAC0_CCTRL +#define CONF_DAC0_CCTRL 0 +#endif + +// Run in standby +// Indicates whether the DAC channel will continue running in standby sleep mode or not +// dac0_arch_runstdby +#ifndef CONF_DAC0_RUNSTDBY +#define CONF_DAC0_RUNSTDBY 0 +#endif + +// Dithering Mode +// Indicate whether dithering mode is enabled +// dac0_arch_ditrher +#ifndef CONF_DAC0_DITHER +#define CONF_DAC0_DITHER 0 +#endif + +// Refresh period <0x00-0xFF> +// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// dac0_arch_refresh +#ifndef CONF_DAC0_REFRESH +#define CONF_DAC0_REFRESH 0 +#endif +// +// Channel 1 configuration +// Left Adjusted Data +// Indicate how the data is adjusted in the Data and Data Buffer register +// dac1_arch_leftadj +#ifndef CONF_DAC1_LEFTADJ +#define CONF_DAC1_LEFTADJ 0 +#endif + +// Current control +// <0=> GCLK_DAC <= 1.2MHz (100kSPS) +// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) +// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) +// This defines the current in output buffer according to conversion rate +// dac1_arch_cctrl +#ifndef CONF_DAC1_CCTRL +#define CONF_DAC1_CCTRL 0 +#endif + +// Run in standby +// Indicates whether the DAC channel will continue running in standby sleep mode or not +// dac1_arch_runstdby +#ifndef CONF_DAC1_RUNSTDBY +#define CONF_DAC1_RUNSTDBY 0 +#endif + +// Dithering Mode +// Indicate whether dithering mode is enabled +// dac1_arch_ditrher +#ifndef CONF_DAC1_DITHER +#define CONF_DAC1_DITHER 0 +#endif + +// Refresh period <0x00-0xFF> +// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us +// dac1_arch_refresh +#ifndef CONF_DAC1_REFRESH +#define CONF_DAC1_REFRESH 0 +#endif +// + +// Event configuration +// Inversion of DAC 0 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// This defines the edge detection of the input event +// dac_arch_invei0 +#ifndef CONF_DAC_INVEI0 +#define CONF_DAC_INVEI0 0 +#endif + +// Data Buffer of DAC 0 Empty Event Output +// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// dac_arch_emptyeo_0 +#ifndef CONF_DAC_EMPTYEO0 +#define CONF_DAC_EMPTYEO0 0 +#endif + +// Start Conversion Event Input DAC 0 +// Indicate whether Start input event is enabled +// dac_arch_startei_0 +#ifndef CONF_DAC_STARTEI0 +#define CONF_DAC_STARTEI0 0 +#endif +// Inversion of DAC 1 event +// <0=> Detection on rising edge pf the input event +// <1=> Detection on falling edge pf the input event +// This defines the edge detection of the input event +// dac_arch_invei1 +#ifndef CONF_DAC_INVEI1 +#define CONF_DAC_INVEI1 0 +#endif + +// Data Buffer of DAC 1 Empty Event Output +// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not +// dac_arch_emptyeo_1 +#ifndef CONF_DAC_EMPTYEO1 +#define CONF_DAC_EMPTYEO1 0 +#endif + +// Start Conversion Event Input DAC 1 +// Indicate whether Start input event is enabled +// dac_arch_startei_1 +#ifndef CONF_DAC_STARTEI1 +#define CONF_DAC_STARTEI1 0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_DAC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_dmac_config.h b/atmel-samd/asf4/samd51/config/hpl_dmac_config.h new file mode 100644 index 0000000000000..90499fc27feac --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_dmac_config.h @@ -0,0 +1,7277 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 1 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 16 is running in standby mode or not +// dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 17 is running in standby mode or not +// dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 18 is running in standby mode or not +// dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 19 is running in standby mode or not +// dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 20 is running in standby mode or not +// dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 21 is running in standby mode or not +// dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 22 is running in standby mode or not +// dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 23 is running in standby mode or not +// dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// + +// Channel 24 settings +// dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 24 is running in standby mode or not +// dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// + +// Channel 25 settings +// dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 25 is running in standby mode or not +// dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// + +// Channel 26 settings +// dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 26 is running in standby mode or not +// dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// + +// Channel 27 settings +// dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 27 is running in standby mode or not +// dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// + +// Channel 28 settings +// dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 28 is running in standby mode or not +// dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// + +// Channel 29 settings +// dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 29 is running in standby mode or not +// dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// + +// Channel 30 settings +// dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 30 is running in standby mode or not +// dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// + +// Channel 31 settings +// dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 31 is running in standby mode or not +// dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_evsys_config.h b/atmel-samd/asf4/samd51/config/hpl_evsys_config.h new file mode 100644 index 0000000000000..d4c465d63ce02 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_evsys_config.h @@ -0,0 +1,8359 @@ +/* Auto-generated config file hpl_evsys_config.h */ +#ifndef HPL_EVSYS_CONFIG_H +#define HPL_EVSYS_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Channel 0 settings +// evsys_channel_setting_0 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_0 +#define CONF_EVSYS_CHANNEL_SETTINGS_0 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_0 +#ifndef CONF_EDGSEL_0 +#define CONF_EDGSEL_0 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_0 +#ifndef CONF_PATH_0 +#define CONF_PATH_0 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_0 +#ifndef CONF_EVGEN_0 +#define CONF_EVGEN_0 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_0 +#ifndef CONF_OVR_0 +#define CONF_OVR_0 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_0 +#ifndef CONF_EVD_0 +#define CONF_EVD_0 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_0 +#ifndef CONF_ONDEMAND_0 +#define CONF_ONDEMAND_0 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_0 +#ifndef CONF_RUNSTDBY_0 +#define CONF_RUNSTDBY_0 0 +#endif + +// + +// Channel 1 settings +// evsys_channel_setting_1 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_1 +#define CONF_EVSYS_CHANNEL_SETTINGS_1 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_1 +#ifndef CONF_EDGSEL_1 +#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_1 +#ifndef CONF_PATH_1 +#define CONF_PATH_1 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_1 +#ifndef CONF_EVGEN_1 +#define CONF_EVGEN_1 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_1 +#ifndef CONF_OVR_1 +#define CONF_OVR_1 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_1 +#ifndef CONF_EVD_1 +#define CONF_EVD_1 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_1 +#ifndef CONF_ONDEMAND_1 +#define CONF_ONDEMAND_1 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_1 +#ifndef CONF_RUNSTDBY_1 +#define CONF_RUNSTDBY_1 0 +#endif + +// + +// Channel 2 settings +// evsys_channel_setting_2 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_2 +#define CONF_EVSYS_CHANNEL_SETTINGS_2 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_2 +#ifndef CONF_EDGSEL_2 +#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_2 +#ifndef CONF_PATH_2 +#define CONF_PATH_2 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_2 +#ifndef CONF_EVGEN_2 +#define CONF_EVGEN_2 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_2 +#ifndef CONF_OVR_2 +#define CONF_OVR_2 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_2 +#ifndef CONF_EVD_2 +#define CONF_EVD_2 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_2 +#ifndef CONF_ONDEMAND_2 +#define CONF_ONDEMAND_2 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_2 +#ifndef CONF_RUNSTDBY_2 +#define CONF_RUNSTDBY_2 0 +#endif + +// + +// Channel 3 settings +// evsys_channel_setting_3 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_3 +#define CONF_EVSYS_CHANNEL_SETTINGS_3 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_3 +#ifndef CONF_EDGSEL_3 +#define CONF_EDGSEL_3 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_3 +#ifndef CONF_PATH_3 +#define CONF_PATH_3 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_3 +#ifndef CONF_EVGEN_3 +#define CONF_EVGEN_3 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_3 +#ifndef CONF_OVR_3 +#define CONF_OVR_3 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_3 +#ifndef CONF_EVD_3 +#define CONF_EVD_3 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_3 +#ifndef CONF_ONDEMAND_3 +#define CONF_ONDEMAND_3 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_3 +#ifndef CONF_RUNSTDBY_3 +#define CONF_RUNSTDBY_3 0 +#endif + +// + +// Channel 4 settings +// evsys_channel_setting_4 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_4 +#define CONF_EVSYS_CHANNEL_SETTINGS_4 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_4 +#ifndef CONF_EDGSEL_4 +#define CONF_EDGSEL_4 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_4 +#ifndef CONF_PATH_4 +#define CONF_PATH_4 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_4 +#ifndef CONF_EVGEN_4 +#define CONF_EVGEN_4 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_4 +#ifndef CONF_OVR_4 +#define CONF_OVR_4 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_4 +#ifndef CONF_EVD_4 +#define CONF_EVD_4 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_4 +#ifndef CONF_ONDEMAND_4 +#define CONF_ONDEMAND_4 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_4 +#ifndef CONF_RUNSTDBY_4 +#define CONF_RUNSTDBY_4 0 +#endif + +// + +// Channel 5 settings +// evsys_channel_setting_5 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5 +#define CONF_EVSYS_CHANNEL_SETTINGS_5 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_5 +#ifndef CONF_EDGSEL_5 +#define CONF_EDGSEL_5 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_5 +#ifndef CONF_PATH_5 +#define CONF_PATH_5 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_5 +#ifndef CONF_EVGEN_5 +#define CONF_EVGEN_5 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_5 +#ifndef CONF_OVR_5 +#define CONF_OVR_5 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_5 +#ifndef CONF_EVD_5 +#define CONF_EVD_5 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_5 +#ifndef CONF_ONDEMAND_5 +#define CONF_ONDEMAND_5 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_5 +#ifndef CONF_RUNSTDBY_5 +#define CONF_RUNSTDBY_5 0 +#endif + +// + +// Channel 6 settings +// evsys_channel_setting_6 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_6 +#define CONF_EVSYS_CHANNEL_SETTINGS_6 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_6 +#ifndef CONF_EDGSEL_6 +#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_6 +#ifndef CONF_PATH_6 +#define CONF_PATH_6 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_6 +#ifndef CONF_EVGEN_6 +#define CONF_EVGEN_6 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_6 +#ifndef CONF_OVR_6 +#define CONF_OVR_6 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_6 +#ifndef CONF_EVD_6 +#define CONF_EVD_6 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_6 +#ifndef CONF_ONDEMAND_6 +#define CONF_ONDEMAND_6 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_6 +#ifndef CONF_RUNSTDBY_6 +#define CONF_RUNSTDBY_6 0 +#endif + +// + +// Channel 7 settings +// evsys_channel_setting_7 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_7 +#define CONF_EVSYS_CHANNEL_SETTINGS_7 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_7 +#ifndef CONF_EDGSEL_7 +#define CONF_EDGSEL_7 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_7 +#ifndef CONF_PATH_7 +#define CONF_PATH_7 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_7 +#ifndef CONF_EVGEN_7 +#define CONF_EVGEN_7 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_7 +#ifndef CONF_OVR_7 +#define CONF_OVR_7 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_7 +#ifndef CONF_EVD_7 +#define CONF_EVD_7 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_7 +#ifndef CONF_ONDEMAND_7 +#define CONF_ONDEMAND_7 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_7 +#ifndef CONF_RUNSTDBY_7 +#define CONF_RUNSTDBY_7 0 +#endif + +// + +// Channel 8 settings +// evsys_channel_setting_8 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_8 +#define CONF_EVSYS_CHANNEL_SETTINGS_8 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_8 +#ifndef CONF_EDGSEL_8 +#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_8 +#ifndef CONF_PATH_8 +#define CONF_PATH_8 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_8 +#ifndef CONF_EVGEN_8 +#define CONF_EVGEN_8 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_8 +#ifndef CONF_OVR_8 +#define CONF_OVR_8 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_8 +#ifndef CONF_EVD_8 +#define CONF_EVD_8 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_8 +#ifndef CONF_ONDEMAND_8 +#define CONF_ONDEMAND_8 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_8 +#ifndef CONF_RUNSTDBY_8 +#define CONF_RUNSTDBY_8 0 +#endif + +// + +// Channel 9 settings +// evsys_channel_setting_9 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_9 +#define CONF_EVSYS_CHANNEL_SETTINGS_9 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_9 +#ifndef CONF_EDGSEL_9 +#define CONF_EDGSEL_9 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_9 +#ifndef CONF_PATH_9 +#define CONF_PATH_9 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_9 +#ifndef CONF_EVGEN_9 +#define CONF_EVGEN_9 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_9 +#ifndef CONF_OVR_9 +#define CONF_OVR_9 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_9 +#ifndef CONF_EVD_9 +#define CONF_EVD_9 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_9 +#ifndef CONF_ONDEMAND_9 +#define CONF_ONDEMAND_9 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_9 +#ifndef CONF_RUNSTDBY_9 +#define CONF_RUNSTDBY_9 0 +#endif + +// + +// Channel 10 settings +// evsys_channel_setting_10 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_10 +#define CONF_EVSYS_CHANNEL_SETTINGS_10 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_10 +#ifndef CONF_EDGSEL_10 +#define CONF_EDGSEL_10 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_10 +#ifndef CONF_PATH_10 +#define CONF_PATH_10 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_10 +#ifndef CONF_EVGEN_10 +#define CONF_EVGEN_10 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_10 +#ifndef CONF_OVR_10 +#define CONF_OVR_10 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_10 +#ifndef CONF_EVD_10 +#define CONF_EVD_10 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_10 +#ifndef CONF_ONDEMAND_10 +#define CONF_ONDEMAND_10 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_10 +#ifndef CONF_RUNSTDBY_10 +#define CONF_RUNSTDBY_10 0 +#endif + +// + +// Channel 11 settings +// evsys_channel_setting_11 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_11 +#define CONF_EVSYS_CHANNEL_SETTINGS_11 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_11 +#ifndef CONF_EDGSEL_11 +#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_11 +#ifndef CONF_PATH_11 +#define CONF_PATH_11 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_11 +#ifndef CONF_EVGEN_11 +#define CONF_EVGEN_11 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_11 +#ifndef CONF_OVR_11 +#define CONF_OVR_11 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_11 +#ifndef CONF_EVD_11 +#define CONF_EVD_11 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_11 +#ifndef CONF_ONDEMAND_11 +#define CONF_ONDEMAND_11 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_11 +#ifndef CONF_RUNSTDBY_11 +#define CONF_RUNSTDBY_11 0 +#endif + +// + +// Channel 12 settings +// evsys_channel_setting_12 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_12 +#define CONF_EVSYS_CHANNEL_SETTINGS_12 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_12 +#ifndef CONF_EDGSEL_12 +#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_12 +#ifndef CONF_PATH_12 +#define CONF_PATH_12 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_12 +#ifndef CONF_EVGEN_12 +#define CONF_EVGEN_12 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_12 +#ifndef CONF_OVR_12 +#define CONF_OVR_12 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_12 +#ifndef CONF_EVD_12 +#define CONF_EVD_12 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_12 +#ifndef CONF_ONDEMAND_12 +#define CONF_ONDEMAND_12 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_12 +#ifndef CONF_RUNSTDBY_12 +#define CONF_RUNSTDBY_12 0 +#endif + +// + +// Channel 13 settings +// evsys_channel_setting_13 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_13 +#define CONF_EVSYS_CHANNEL_SETTINGS_13 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_13 +#ifndef CONF_EDGSEL_13 +#define CONF_EDGSEL_13 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_13 +#ifndef CONF_PATH_13 +#define CONF_PATH_13 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_13 +#ifndef CONF_EVGEN_13 +#define CONF_EVGEN_13 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_13 +#ifndef CONF_OVR_13 +#define CONF_OVR_13 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_13 +#ifndef CONF_EVD_13 +#define CONF_EVD_13 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_13 +#ifndef CONF_ONDEMAND_13 +#define CONF_ONDEMAND_13 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_13 +#ifndef CONF_RUNSTDBY_13 +#define CONF_RUNSTDBY_13 0 +#endif + +// + +// Channel 14 settings +// evsys_channel_setting_14 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_14 +#define CONF_EVSYS_CHANNEL_SETTINGS_14 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_14 +#ifndef CONF_EDGSEL_14 +#define CONF_EDGSEL_14 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_14 +#ifndef CONF_PATH_14 +#define CONF_PATH_14 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_14 +#ifndef CONF_EVGEN_14 +#define CONF_EVGEN_14 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_14 +#ifndef CONF_OVR_14 +#define CONF_OVR_14 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_14 +#ifndef CONF_EVD_14 +#define CONF_EVD_14 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_14 +#ifndef CONF_ONDEMAND_14 +#define CONF_ONDEMAND_14 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_14 +#ifndef CONF_RUNSTDBY_14 +#define CONF_RUNSTDBY_14 0 +#endif + +// + +// Channel 15 settings +// evsys_channel_setting_15 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_15 +#define CONF_EVSYS_CHANNEL_SETTINGS_15 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_15 +#ifndef CONF_EDGSEL_15 +#define CONF_EDGSEL_15 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_15 +#ifndef CONF_PATH_15 +#define CONF_PATH_15 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_15 +#ifndef CONF_EVGEN_15 +#define CONF_EVGEN_15 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_15 +#ifndef CONF_OVR_15 +#define CONF_OVR_15 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_15 +#ifndef CONF_EVD_15 +#define CONF_EVD_15 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_15 +#ifndef CONF_ONDEMAND_15 +#define CONF_ONDEMAND_15 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_15 +#ifndef CONF_RUNSTDBY_15 +#define CONF_RUNSTDBY_15 0 +#endif + +// + +// Channel 16 settings +// evsys_channel_setting_16 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_16 +#define CONF_EVSYS_CHANNEL_SETTINGS_16 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_16 +#ifndef CONF_EDGSEL_16 +#define CONF_EDGSEL_16 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_16 +#ifndef CONF_PATH_16 +#define CONF_PATH_16 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_16 +#ifndef CONF_EVGEN_16 +#define CONF_EVGEN_16 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_16 +#ifndef CONF_OVR_16 +#define CONF_OVR_16 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_16 +#ifndef CONF_EVD_16 +#define CONF_EVD_16 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_16 +#ifndef CONF_ONDEMAND_16 +#define CONF_ONDEMAND_16 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_16 +#ifndef CONF_RUNSTDBY_16 +#define CONF_RUNSTDBY_16 0 +#endif + +// + +// Channel 17 settings +// evsys_channel_setting_17 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_17 +#define CONF_EVSYS_CHANNEL_SETTINGS_17 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_17 +#ifndef CONF_EDGSEL_17 +#define CONF_EDGSEL_17 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_17 +#ifndef CONF_PATH_17 +#define CONF_PATH_17 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_17 +#ifndef CONF_EVGEN_17 +#define CONF_EVGEN_17 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_17 +#ifndef CONF_OVR_17 +#define CONF_OVR_17 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_17 +#ifndef CONF_EVD_17 +#define CONF_EVD_17 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_17 +#ifndef CONF_ONDEMAND_17 +#define CONF_ONDEMAND_17 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_17 +#ifndef CONF_RUNSTDBY_17 +#define CONF_RUNSTDBY_17 0 +#endif + +// + +// Channel 18 settings +// evsys_channel_setting_18 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_18 +#define CONF_EVSYS_CHANNEL_SETTINGS_18 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_18 +#ifndef CONF_EDGSEL_18 +#define CONF_EDGSEL_18 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_18 +#ifndef CONF_PATH_18 +#define CONF_PATH_18 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_18 +#ifndef CONF_EVGEN_18 +#define CONF_EVGEN_18 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_18 +#ifndef CONF_OVR_18 +#define CONF_OVR_18 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_18 +#ifndef CONF_EVD_18 +#define CONF_EVD_18 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_18 +#ifndef CONF_ONDEMAND_18 +#define CONF_ONDEMAND_18 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_18 +#ifndef CONF_RUNSTDBY_18 +#define CONF_RUNSTDBY_18 0 +#endif + +// + +// Channel 19 settings +// evsys_channel_setting_19 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_19 +#define CONF_EVSYS_CHANNEL_SETTINGS_19 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_19 +#ifndef CONF_EDGSEL_19 +#define CONF_EDGSEL_19 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_19 +#ifndef CONF_PATH_19 +#define CONF_PATH_19 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_19 +#ifndef CONF_EVGEN_19 +#define CONF_EVGEN_19 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_19 +#ifndef CONF_OVR_19 +#define CONF_OVR_19 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_19 +#ifndef CONF_EVD_19 +#define CONF_EVD_19 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_19 +#ifndef CONF_ONDEMAND_19 +#define CONF_ONDEMAND_19 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_19 +#ifndef CONF_RUNSTDBY_19 +#define CONF_RUNSTDBY_19 0 +#endif + +// + +// Channel 20 settings +// evsys_channel_setting_20 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_20 +#define CONF_EVSYS_CHANNEL_SETTINGS_20 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_20 +#ifndef CONF_EDGSEL_20 +#define CONF_EDGSEL_20 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_20 +#ifndef CONF_PATH_20 +#define CONF_PATH_20 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_20 +#ifndef CONF_EVGEN_20 +#define CONF_EVGEN_20 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_20 +#ifndef CONF_OVR_20 +#define CONF_OVR_20 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_20 +#ifndef CONF_EVD_20 +#define CONF_EVD_20 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_20 +#ifndef CONF_ONDEMAND_20 +#define CONF_ONDEMAND_20 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_20 +#ifndef CONF_RUNSTDBY_20 +#define CONF_RUNSTDBY_20 0 +#endif + +// + +// Channel 21 settings +// evsys_channel_setting_21 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_21 +#define CONF_EVSYS_CHANNEL_SETTINGS_21 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_21 +#ifndef CONF_EDGSEL_21 +#define CONF_EDGSEL_21 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_21 +#ifndef CONF_PATH_21 +#define CONF_PATH_21 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_21 +#ifndef CONF_EVGEN_21 +#define CONF_EVGEN_21 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_21 +#ifndef CONF_OVR_21 +#define CONF_OVR_21 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_21 +#ifndef CONF_EVD_21 +#define CONF_EVD_21 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_21 +#ifndef CONF_ONDEMAND_21 +#define CONF_ONDEMAND_21 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_21 +#ifndef CONF_RUNSTDBY_21 +#define CONF_RUNSTDBY_21 0 +#endif + +// + +// Channel 22 settings +// evsys_channel_setting_22 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_22 +#define CONF_EVSYS_CHANNEL_SETTINGS_22 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_22 +#ifndef CONF_EDGSEL_22 +#define CONF_EDGSEL_22 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_22 +#ifndef CONF_PATH_22 +#define CONF_PATH_22 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_22 +#ifndef CONF_EVGEN_22 +#define CONF_EVGEN_22 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_22 +#ifndef CONF_OVR_22 +#define CONF_OVR_22 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_22 +#ifndef CONF_EVD_22 +#define CONF_EVD_22 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_22 +#ifndef CONF_ONDEMAND_22 +#define CONF_ONDEMAND_22 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_22 +#ifndef CONF_RUNSTDBY_22 +#define CONF_RUNSTDBY_22 0 +#endif + +// + +// Channel 23 settings +// evsys_channel_setting_23 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_23 +#define CONF_EVSYS_CHANNEL_SETTINGS_23 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_23 +#ifndef CONF_EDGSEL_23 +#define CONF_EDGSEL_23 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_23 +#ifndef CONF_PATH_23 +#define CONF_PATH_23 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_23 +#ifndef CONF_EVGEN_23 +#define CONF_EVGEN_23 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_23 +#ifndef CONF_OVR_23 +#define CONF_OVR_23 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_23 +#ifndef CONF_EVD_23 +#define CONF_EVD_23 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_23 +#ifndef CONF_ONDEMAND_23 +#define CONF_ONDEMAND_23 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_23 +#ifndef CONF_RUNSTDBY_23 +#define CONF_RUNSTDBY_23 0 +#endif + +// + +// Channel 24 settings +// evsys_channel_setting_24 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_24 +#define CONF_EVSYS_CHANNEL_SETTINGS_24 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_24 +#ifndef CONF_EDGSEL_24 +#define CONF_EDGSEL_24 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_24 +#ifndef CONF_PATH_24 +#define CONF_PATH_24 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_24 +#ifndef CONF_EVGEN_24 +#define CONF_EVGEN_24 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_24 +#ifndef CONF_OVR_24 +#define CONF_OVR_24 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_24 +#ifndef CONF_EVD_24 +#define CONF_EVD_24 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_24 +#ifndef CONF_ONDEMAND_24 +#define CONF_ONDEMAND_24 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_24 +#ifndef CONF_RUNSTDBY_24 +#define CONF_RUNSTDBY_24 0 +#endif + +// + +// Channel 25 settings +// evsys_channel_setting_25 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_25 +#define CONF_EVSYS_CHANNEL_SETTINGS_25 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_25 +#ifndef CONF_EDGSEL_25 +#define CONF_EDGSEL_25 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_25 +#ifndef CONF_PATH_25 +#define CONF_PATH_25 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_25 +#ifndef CONF_EVGEN_25 +#define CONF_EVGEN_25 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_25 +#ifndef CONF_OVR_25 +#define CONF_OVR_25 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_25 +#ifndef CONF_EVD_25 +#define CONF_EVD_25 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_25 +#ifndef CONF_ONDEMAND_25 +#define CONF_ONDEMAND_25 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_25 +#ifndef CONF_RUNSTDBY_25 +#define CONF_RUNSTDBY_25 0 +#endif + +// + +// Channel 26 settings +// evsys_channel_setting_26 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_26 +#define CONF_EVSYS_CHANNEL_SETTINGS_26 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_26 +#ifndef CONF_EDGSEL_26 +#define CONF_EDGSEL_26 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_26 +#ifndef CONF_PATH_26 +#define CONF_PATH_26 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_26 +#ifndef CONF_EVGEN_26 +#define CONF_EVGEN_26 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_26 +#ifndef CONF_OVR_26 +#define CONF_OVR_26 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_26 +#ifndef CONF_EVD_26 +#define CONF_EVD_26 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_26 +#ifndef CONF_ONDEMAND_26 +#define CONF_ONDEMAND_26 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_26 +#ifndef CONF_RUNSTDBY_26 +#define CONF_RUNSTDBY_26 0 +#endif + +// + +// Channel 27 settings +// evsys_channel_setting_27 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_27 +#define CONF_EVSYS_CHANNEL_SETTINGS_27 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_27 +#ifndef CONF_EDGSEL_27 +#define CONF_EDGSEL_27 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_27 +#ifndef CONF_PATH_27 +#define CONF_PATH_27 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_27 +#ifndef CONF_EVGEN_27 +#define CONF_EVGEN_27 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_27 +#ifndef CONF_OVR_27 +#define CONF_OVR_27 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_27 +#ifndef CONF_EVD_27 +#define CONF_EVD_27 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_27 +#ifndef CONF_ONDEMAND_27 +#define CONF_ONDEMAND_27 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_27 +#ifndef CONF_RUNSTDBY_27 +#define CONF_RUNSTDBY_27 0 +#endif + +// + +// Channel 28 settings +// evsys_channel_setting_28 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_28 +#define CONF_EVSYS_CHANNEL_SETTINGS_28 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_28 +#ifndef CONF_EDGSEL_28 +#define CONF_EDGSEL_28 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_28 +#ifndef CONF_PATH_28 +#define CONF_PATH_28 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_28 +#ifndef CONF_EVGEN_28 +#define CONF_EVGEN_28 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_28 +#ifndef CONF_OVR_28 +#define CONF_OVR_28 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_28 +#ifndef CONF_EVD_28 +#define CONF_EVD_28 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_28 +#ifndef CONF_ONDEMAND_28 +#define CONF_ONDEMAND_28 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_28 +#ifndef CONF_RUNSTDBY_28 +#define CONF_RUNSTDBY_28 0 +#endif + +// + +// Channel 29 settings +// evsys_channel_setting_29 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_29 +#define CONF_EVSYS_CHANNEL_SETTINGS_29 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_29 +#ifndef CONF_EDGSEL_29 +#define CONF_EDGSEL_29 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_29 +#ifndef CONF_PATH_29 +#define CONF_PATH_29 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_29 +#ifndef CONF_EVGEN_29 +#define CONF_EVGEN_29 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_29 +#ifndef CONF_OVR_29 +#define CONF_OVR_29 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_29 +#ifndef CONF_EVD_29 +#define CONF_EVD_29 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_29 +#ifndef CONF_ONDEMAND_29 +#define CONF_ONDEMAND_29 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_29 +#ifndef CONF_RUNSTDBY_29 +#define CONF_RUNSTDBY_29 0 +#endif + +// + +// Channel 30 settings +// evsys_channel_setting_30 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_30 +#define CONF_EVSYS_CHANNEL_SETTINGS_30 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_30 +#ifndef CONF_EDGSEL_30 +#define CONF_EDGSEL_30 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_30 +#ifndef CONF_PATH_30 +#define CONF_PATH_30 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_30 +#ifndef CONF_EVGEN_30 +#define CONF_EVGEN_30 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_30 +#ifndef CONF_OVR_30 +#define CONF_OVR_30 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_30 +#ifndef CONF_EVD_30 +#define CONF_EVD_30 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_30 +#ifndef CONF_ONDEMAND_30 +#define CONF_ONDEMAND_30 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_30 +#ifndef CONF_RUNSTDBY_30 +#define CONF_RUNSTDBY_30 0 +#endif + +// + +// Channel 31 settings +// evsys_channel_setting_31 +#ifndef CONF_EVSYS_CHANNEL_SETTINGS_31 +#define CONF_EVSYS_CHANNEL_SETTINGS_31 0 +#endif + +// Edge detection +// Indicates whether channel is enabled in standby sleep mode +// No event output when using the resynchronized or synchronous path +// Event is detected on the rising edge of the signal from event generator +// Event is detected on the falling edge of the signal from event generator +// Event is detected on the rising and falling edge of the signal from event generator +// evsys_edgsel_31 +#ifndef CONF_EDGSEL_31 +#define CONF_EDGSEL_31 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val +#endif + +// Path selection +// Indicates which path for the event signal is chosen +// Synchronous path +// Resynchronized path +// Asynchronous path +// evsys_path_31 +#ifndef CONF_PATH_31 +#define CONF_PATH_31 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val +#endif + +// Event generator +// Determines event generator for channel +// <0x0=>No event generator +// <0x1=>XOSC Clock Failure 0 +// <0x2=>XOSC Clock Failure 1 +// <0x3=>XOSC32K Clock Failure +// <0x4=>RTC period 0 +// <0x5=>RTC period 1 +// <0x6=>RTC period 2 +// <0x7=>RTC period 3 +// <0x8=>RTC period 4 +// <0x9=>RTC period 5 +// <0xA=>RTC period 6 +// <0xB=>RTC period 7 +// <0xC=>RTC compare 0 +// <0xD=>RTC compare 1 +// <0xE=>RTC compare 2 +// <0xF=>RTC compare 3 +// <0x10=>RTC Tamper Detection +// <0x11=>RTC overflow +// <0x12=>EIC external interrupt 0 +// <0x13=>EIC external interrupt 1 +// <0x14=>EIC external interrupt 2 +// <0x15=>EIC external interrupt 3 +// <0x16=>EIC external interrupt 4 +// <0x17=>EIC external interrupt 5 +// <0x18=>EIC external interrupt 6 +// <0x19=>EIC external interrupt 7 +// <0x1A=>EIC external interrupt 8 +// <0x1B=>EIC external interrupt 9 +// <0x1C=>EIC external interrupt 10 +// <0x1D=>EIC external interrupt 11 +// <0x1E=>EIC external interrupt 12 +// <0x1F=>EIC external interrupt 13 +// <0x20=>EIC external interrupt 14 +// <0x21=>EIC external interrupt 15 +// <0x22=>DMAC channel 0 +// <0x23=>DMAC channel 1 +// <0x24=>DMAC channel 2 +// <0x25=>DMAC channel 3 +// <0x28=>PAC access error +// <0x29=>TCC0 overflow +// <0x2A=>TCC0 trig +// <0x2B=>TCC0 counter +// <0x2C=>TCC0 match/capture 0 +// <0x2D=>TCC0 match/capture 1 +// <0x2E=>TCC0 match/capture 2 +// <0x2F=>TCC0 match/capture 3 +// <0x30=>TCC0 match/capture 4 +// <0x31=>TCC0 match/capture 5 +// <0x32=>TCC1 overflow +// <0x33=>TCC1 trig +// <0x34=>TCC1 counter +// <0x35=>TCC1 match/capture 0 +// <0x36=>TCC1 match/capture 1 +// <0x37=>TCC1 match/capture 2 +// <0x38=>TCC1 match/capture 3 +// <0x39=>TCC2 overflow +// <0x3A=>TCC2 trig +// <0x3B=>TCC2 counter +// <0x3C=>TCC2 match/capture 0 +// <0x3D=>TCC2 match/capture 1 +// <0x3E=>TCC2 match/capture 2 +// <0x3F=>TCC3 overflow +// <0x40=>TCC3 trig +// <0x41=>TCC3 counter +// <0x42=>TCC3 match/capture 0 +// <0x43=>TCC3 match/capture 1 +// <0x44=>TCC4 overflow +// <0x45=>TCC4 trig +// <0x46=>TCC4 counter +// <0x47=>TCC4 match/capture 0 +// <0x48=>TCC4 match/capture 1 +// <0x49=>TC0 overflow +// <0x4A=>TC0 match/capture 0 +// <0x4B=>TC0 match/capture 1 +// <0x4C=>TC1 overflow +// <0x4D=>TC1 match/capture 0 +// <0x4E=>TC1 match/capture 1 +// <0x4F=>TC2 overflow +// <0x50=>TC2 match/capture 0 +// <0x51=>TC2 match/capture 1 +// <0x52=>TC3 overflow +// <0x53=>TC3 match/capture 0 +// <0x54=>TC3 match/capture 1 +// <0x55=>TC4 overflow +// <0x56=>TC4 match/capture 0 +// <0x57=>TC4 match/capture 1 +// <0x58=>TC5 overflow +// <0x59=>TC5 match/capture 0 +// <0x5A=>TC5 match/capture 1 +// <0x5B=>TC6 overflow +// <0x5C=>TC6 match/capture 0 +// <0x5D=>TC6 match/capture 1 +// <0x5E=>TC7 overflow +// <0x5F=>TC7 match/capture 0 +// <0x60=>TC7 match/capture 1 +// <0x61=>PDEC overflow +// <0x62=>PDEC error +// <0x63=>PDEC direction +// <0x64=>PDEC VLC +// <0x65=>PDEC match channel 0 +// <0x66=>PDEC match channel 1 +// <0x67=>ADC0 result ready +// <0x68=>ADC0 window monitor +// <0x69=>ADC1 result ready +// <0x6A=>ADC1 window monitor +// <0x6B=>AC comparator 0 +// <0x6C=>AC comparator 1 +// <0x6D=>AC window 0 +// <0x6E=>DAC data buffer empty 0 +// <0x6F=>DAC data buffer empty 1 +// <0x70=>DAC result ready 0 +// <0x71=>DAC result ready 1 +// <0x73=>TRNG Data Ready +// <0x74=>CCL LUT output 0 +// <0x75=>CCL LUT output 1 +// <0x76=>CCL LUT output 2 +// <0x77=>CCL LUT output 3 +// evsys_evgen_31 +#ifndef CONF_EVGEN_31 +#define CONF_EVGEN_31 0 +#endif + +// Overrun channel interrupt +// Indicates whether overrun channel interrupt is enabled or not +// evsys_ovr_31 +#ifndef CONF_OVR_31 +#define CONF_OVR_31 0 +#endif + +// Event detected interrupt +// Indicates whether event detected interrupt is enabled or not +// evsys_evd_31 +#ifndef CONF_EVD_31 +#define CONF_EVD_31 0 +#endif + +// On demand clock +// Indicates whether clock for channel is requested on demand or not +// evsys_ondemand_31 +#ifndef CONF_ONDEMAND_31 +#define CONF_ONDEMAND_31 0 +#endif + +// Run is standby mode +// Indicates whether channel is enabled in standby sleep mode +// evsys_runstdby_31 +#ifndef CONF_RUNSTDBY_31 +#define CONF_RUNSTDBY_31 0 +#endif + +// + +// RTC events +// Channel selection for RTC Tamper Event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_0 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_0 +#define CONF_CHANNEL_0 0 +#endif +// + +// PORT events +// Channel selection for PORT event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_1 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_1 +#define CONF_CHANNEL_1 0 +#endif + +// Channel selection for PORT event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_2 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_2 +#define CONF_CHANNEL_2 0 +#endif + +// Channel selection for PORT event 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_3 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_3 +#define CONF_CHANNEL_3 0 +#endif + +// Channel selection for PORT event 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_4 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_4 +#define CONF_CHANNEL_4 0 +#endif +// + +// DMAC events +// Channel selection for DMAC channel 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_5 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_5 +#define CONF_CHANNEL_5 0 +#endif + +// Channel selection for DMAC channel 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_6 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_6 +#define CONF_CHANNEL_6 0 +#endif + +// Channel selection for DMAC channel 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_7 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_7 +#define CONF_CHANNEL_7 0 +#endif + +// Channel selection for DMAC channel 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_8 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_8 +#define CONF_CHANNEL_8 0 +#endif + +// Channel selection for DMAC channel 4 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_9 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_9 +#define CONF_CHANNEL_9 0 +#endif + +// Channel selection for DMAC channel 5 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_10 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_10 +#define CONF_CHANNEL_10 0 +#endif + +// Channel selection for DMAC channel 6 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_11 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_11 +#define CONF_CHANNEL_11 0 +#endif + +// Channel selection for DMAC channel 7 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_12 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_12 +#define CONF_CHANNEL_12 0 +#endif +// + +// Reserved +#ifndef CONF_CHANNEL_13 +#define CONF_CHANNEL_13 0 +#endif + +#ifndef CONF_CHANNEL_14 +#define CONF_CHANNEL_14 0 +#endif + +#ifndef CONF_CHANNEL_15 +#define CONF_CHANNEL_15 0 +#endif + +#ifndef CONF_CHANNEL_16 +#define CONF_CHANNEL_16 0 +#endif +// + +// TCC events +// Channel selection for TCC0 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_17 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_17 +#define CONF_CHANNEL_17 0 +#endif + +// Channel selection for TCC0 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_18 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_18 +#define CONF_CHANNEL_18 0 +#endif + +// Channel selection for TCC0 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_19 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_19 +#define CONF_CHANNEL_19 0 +#endif + +// Channel selection for TCC0 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_20 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_20 +#define CONF_CHANNEL_20 0 +#endif + +// Channel selection for TCC0 match/capture 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_21 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_21 +#define CONF_CHANNEL_21 0 +#endif + +// Channel selection for TCC0 match/capture 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_22 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_22 +#define CONF_CHANNEL_22 0 +#endif + +// Channel selection for TCC0 match/capture 4 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_23 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_23 +#define CONF_CHANNEL_23 0 +#endif + +// Channel selection for TCC0 match/capture 5 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_24 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_24 +#define CONF_CHANNEL_24 0 +#endif + +// Channel selection for TCC1 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_25 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_25 +#define CONF_CHANNEL_25 0 +#endif + +// Channel selection for TCC1 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_26 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_26 +#define CONF_CHANNEL_26 0 +#endif + +// Channel selection for TCC1 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_27 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_27 +#define CONF_CHANNEL_27 0 +#endif + +// Channel selection for TCC1 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_28 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_28 +#define CONF_CHANNEL_28 0 +#endif + +// Channel selection for TCC1 match/capture 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_29 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_29 +#define CONF_CHANNEL_29 0 +#endif + +// Channel selection for TCC1 match/capture 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_30 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_30 +#define CONF_CHANNEL_30 0 +#endif + +// Channel selection for TCC2 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_31 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_31 +#define CONF_CHANNEL_31 0 +#endif + +// Channel selection for TCC2 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_32 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_32 +#define CONF_CHANNEL_32 0 +#endif + +// Channel selection for TCC2 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_33 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_33 +#define CONF_CHANNEL_33 0 +#endif + +// Channel selection for TCC2 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_34 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_34 +#define CONF_CHANNEL_34 0 +#endif + +// Channel selection for TCC2 match/capture 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_35 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_35 +#define CONF_CHANNEL_35 0 +#endif + +// Channel selection for TCC3 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_36 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_36 +#define CONF_CHANNEL_36 0 +#endif + +// Channel selection for TCC3 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_37 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_37 +#define CONF_CHANNEL_37 0 +#endif + +// Channel selection for TCC3 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_38 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_38 +#define CONF_CHANNEL_38 0 +#endif + +// Channel selection for TCC3 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_39 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_39 +#define CONF_CHANNEL_39 0 +#endif + +// Channel selection for TCC4 Event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_40 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_40 +#define CONF_CHANNEL_40 0 +#endif + +// Channel selection for TCC4 Event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_41 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_41 +#define CONF_CHANNEL_41 0 +#endif + +// Channel selection for TCC4 match/capture 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_42 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_42 +#define CONF_CHANNEL_42 0 +#endif + +// Channel selection for TCC4 match/capture 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_43 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_43 +#define CONF_CHANNEL_43 0 +#endif +// + +// TC events +// Channel selection for TC0 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_44 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_44 +#define CONF_CHANNEL_44 0 +#endif + +// Channel selection for TC1 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_45 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_45 +#define CONF_CHANNEL_45 0 +#endif + +// Channel selection for TC2 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_46 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_46 +#define CONF_CHANNEL_46 0 +#endif + +// Channel selection for TC3 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_47 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_47 +#define CONF_CHANNEL_47 0 +#endif + +// Channel selection for TC4 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_48 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_48 +#define CONF_CHANNEL_48 0 +#endif + +// Channel selection for TC5 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_49 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_49 +#define CONF_CHANNEL_49 0 +#endif + +// Channel selection for TC6 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_50 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_50 +#define CONF_CHANNEL_50 0 +#endif + +// Channel selection for TC7 event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_51 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_51 +#define CONF_CHANNEL_51 0 +#endif +// + +// PDEC events +// Channel selection for PDEC event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_52 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_52 +#define CONF_CHANNEL_52 0 +#endif + +// Channel selection for PDEC event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_53 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_53 +#define CONF_CHANNEL_53 0 +#endif + +// Channel selection for PDEC event 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_54 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_54 +#define CONF_CHANNEL_54 0 +#endif +// + +// ADC events +// Channel selection for ADC0 start conversion event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_55 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_55 +#define CONF_CHANNEL_55 0 +#endif + +// Channel selection for ADC0 flush event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_56 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_56 +#define CONF_CHANNEL_56 0 +#endif + +// Channel selection for ADC1 start conversion event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_57 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_57 +#define CONF_CHANNEL_57 0 +#endif + +// Channel selection for ADC1 flush event +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_58 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_58 +#define CONF_CHANNEL_58 0 +#endif +// + +// AC events +// Channel selection for Start comparator event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_59 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_59 +#define CONF_CHANNEL_59 0 +#endif + +// Channel selection for Start comparator event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_60 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_60 +#define CONF_CHANNEL_60 0 +#endif +// + +// DAC events +// Channel selection for DAC Start event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_61 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_61 +#define CONF_CHANNEL_61 0 +#endif + +// Channel selection for DAC Start event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_62 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_62 +#define CONF_CHANNEL_62 0 +#endif +// + +// CCL events +// Channel selection for CCL input event 0 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_63 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_63 +#define CONF_CHANNEL_63 0 +#endif + +// Channel selection for CCL input event 1 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_64 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_64 +#define CONF_CHANNEL_64 0 +#endif + +// Channel selection for CCL input event 2 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_65 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_65 +#define CONF_CHANNEL_65 0 +#endif + +// Channel selection for CCL input event 3 +// <0x0=>No channel output selected +// <0x1=>Channel 0 +// <0x2=>Channel 1 +// <0x3=>Channel 2 +// <0x4=>Channel 3 +// <0x5=>Channel 4 +// <0x6=>Channel 5 +// <0x7=>Channel 6 +// <0x8=>Channel 7 +// <0x9=>Channel 8 +// <0xA=>Channel 9 +// <0xB=>Channel 10 +// <0xC=>Channel 11 +// <0xD=>Channel 12 +// <0xE=>Channel 13 +// <0xF=>Channel 14 +// <0x10=>Channel 15 +// <0x11=>Channel 16 +// <0x12=>Channel 17 +// <0x13=>Channel 18 +// <0x14=>Channel 19 +// <0x15=>Channel 20 +// <0x16=>Channel 21 +// <0x17=>Channel 22 +// <0x18=>Channel 23 +// <0x19=>Channel 24 +// <0x1A=>Channel 25 +// <0x1B=>Channel 26 +// <0x1C=>Channel 27 +// <0x1D=>Channel 28 +// <0x1E=>Channel 29 +// <0x1F=>Channel 30 +// <0x20=>Channel 31 +// evsys_channel_66 +// Indicates which channel is chosen for user +#ifndef CONF_CHANNEL_66 +#define CONF_CHANNEL_66 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_EVSYS_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_gclk_config.h b/atmel-samd/asf4/samd51/config/hpl_gclk_config.h new file mode 100644 index 0000000000000..ca1bfbdd25f12 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_gclk_config.h @@ -0,0 +1,908 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 1 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// Generic clock generator 8 configuration +// Indicates whether generic clock 8 configuration is enabled or not +// enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 8 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 8 +// gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 8 division <0x0000-0xFFFF> +// gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// +// + +// Generic clock generator 9 configuration +// Indicates whether generic clock 9 configuration is enabled or not +// enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 9 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 9 +// gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 9 division <0x0000-0xFFFF> +// gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// +// + +// Generic clock generator 10 configuration +// Indicates whether generic clock 10 configuration is enabled or not +// enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 10 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 10 +// gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 10 division <0x0000-0xFFFF> +// gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// +// + +// Generic clock generator 11 configuration +// Indicates whether generic clock 11 configuration is enabled or not +// enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 11 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 11 +// gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 11 division <0x0000-0xFFFF> +// gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_mclk_config.h b/atmel-samd/asf4/samd51/config/hpl_mclk_config.h new file mode 100644 index 0000000000000..a5a7de53c2596 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_mclk_config.h @@ -0,0 +1,104 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// High-Speed Clock Division +// Divide by 1 +// mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_osc32kctrl_config.h b/atmel-samd/asf4/samd51/config/hpl_osc32kctrl_config.h new file mode 100644 index 0000000000000..b6a74aaa75a6c --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_osc32kctrl_config.h @@ -0,0 +1,163 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ +#define CONF_RTCCTRL_1KHZ 1 +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 0 +#endif + +// Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x3F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_oscctrl_config.h b/atmel-samd/asf4/samd51/config/hpl_oscctrl_config.h new file mode 100644 index 0000000000000..63173629ec60d --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_oscctrl_config.h @@ -0,0 +1,634 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC0 is enabled or not +// enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +// +// + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC1 is enabled or not +// enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 1 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 1 +#endif +// +// + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source +// dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// Fine Maximum Step <0x0-0xFF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0xFF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +// + +// + +// + +// FDPLL0 Configuration +// Indicates whether configuration for FDPLL0 is enabled or not +// enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +// +// +// FDPLL1 Configuration +// Indicates whether configuration for FDPLL1 is enabled or not +// enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_rtc_config.h b/atmel-samd/asf4/samd51/config/hpl_rtc_config.h new file mode 100644 index 0000000000000..b99821da5b33c --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_rtc_config.h @@ -0,0 +1,137 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// Prescaler configuration +// <0x0=>OFF(Peripheral clock divided by 1) +// <0x1=>Peripheral clock divided by 1 +// <0x2=>Peripheral clock divided by 2 +// <0x3=>Peripheral clock divided by 4 +// <0x4=>Peripheral clock divided by 8 +// <0x5=>Peripheral clock divided by 16 +// <0x6=>Peripheral clock divided by 32 +// <0x7=>Peripheral clock divided by 64 +// <0x8=>Peripheral clock divided by 128 +// <0x9=>Peripheral clock divided by 256 +// <0xA=>Peripheral clock divided by 512 +// <0xB=>Peripheral clock divided by 1024 +// These bits define the RTC clock relative to the peripheral clock +// rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0x0 + +#endif + +// Compare Value <1-4294967295> +// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. +// rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL +#define CONF_RTC_COMP_VAL 1 + +#endif + +// Event control +// rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// Periodic Interval 0 Event Output +// This bit indicates whether Periodic interval 0 event is enabled and will be generated +// rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// Periodic Interval 1 Event Output +// This bit indicates whether Periodic interval 1 event is enabled and will be generated +// rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// Periodic Interval 2 Event Output +// This bit indicates whether Periodic interval 2 event is enabled and will be generated +// rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// Periodic Interval 3 Event Output +// This bit indicates whether Periodic interval 3 event is enabled and will be generated +// rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// Periodic Interval 4 Event Output +// This bit indicates whether Periodic interval 4 event is enabled and will be generated +// rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// Periodic Interval 5 Event Output +// This bit indicates whether Periodic interval 5 event is enabled and will be generated +// rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// Periodic Interval 6 Event Output +// This bit indicates whether Periodic interval 6 event is enabled and will be generated +// rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// Periodic Interval 7 Event Output +// This bit indicates whether Periodic interval 7 event is enabled and will be generated +// rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// Compare 0 Event Output +// This bit indicates whether Compare O event is enabled and will be generated +// rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// Compare 1 Event Output +// This bit indicates whether Compare 1 event is enabled and will be generated +// rtc_cmpeo1 +#ifndef CONF_RTC_COMPE1 +#define CONF_RTC_COMPE1 0 +#endif +// Overflow Event Output +// This bit indicates whether Overflow event is enabled and will be generated +// rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// Tamper Event Output +// This bit indicates whether Tamper event output is enabled and will be generated +// rtc_tampereo +#ifndef CONF_RTC_TAMPEREO +#define CONF_RTC_TAMPEREO 0 +#endif + +// Tamper Event Input +// This bit indicates whether Tamper event input is enabled and will be generated +// rtc_tampevei +#ifndef CONF_RTC_TAMPEVEI +#define CONF_RTC_TAMPEVEI 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_sercom_config.h b/atmel-samd/asf4/samd51/config/hpl_sercom_config.h new file mode 100644 index 0000000000000..35037bd272184 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_sercom_config.h @@ -0,0 +1,553 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// Enable configuration of module +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 1 +#endif + +// Set module in SPI Master mode +#ifndef CONF_SERCOM_0_SPI_MODE +#define CONF_SERCOM_0_SPI_MODE 0x03 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable receive buffer to receive data from slave (RXEN) +// spi_master_rx_enable +#ifndef CONF_SERCOM_0_SPI_RXEN +#define CONF_SERCOM_0_SPI_RXEN 0x1 +#endif + +// Character Size +// Bit size for all characters sent over the SPI bus (CHSIZE) +// <0x0=>8 bits +// <0x1=>9 bits +// spi_master_character_size +#ifndef CONF_SERCOM_0_SPI_CHSIZE +#define CONF_SERCOM_0_SPI_CHSIZE 0x0 +#endif + +// Baud rate <1-12000000> +// The SPI data transfer rate +// spi_master_baud_rate +#ifndef CONF_SERCOM_0_SPI_BAUD +#define CONF_SERCOM_0_SPI_BAUD 50000 +#endif + +// + +// Advanced Configuration +// spi_master_advanced +#ifndef CONF_SERCOM_0_SPI_ADVANCED +#define CONF_SERCOM_0_SPI_ADVANCED 0 +#endif + +// Dummy byte <0x00-0x1ff> +// spi_master_dummybyte +// Dummy byte used when reading data from the slave without sending any data +#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE +#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff +#endif + +// Data Order +// <0=>MSB first +// <1=>LSB first +// I least significant or most significant bit is shifted out first (DORD) +// spi_master_arch_dord +#ifndef CONF_SERCOM_0_SPI_DORD +#define CONF_SERCOM_0_SPI_DORD 0x0 +#endif + +// Clock Polarity +// <0=>SCK is low when idle +// <1=>SCK is high when idle +// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) +// spi_master_arch_cpol +#ifndef CONF_SERCOM_0_SPI_CPOL +#define CONF_SERCOM_0_SPI_CPOL 0x0 +#endif + +// Clock Phase +// <0x0=>Sample input on leading edge +// <0x1=>Sample input on trailing edge +// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) +// spi_master_arch_cpha +#ifndef CONF_SERCOM_0_SPI_CPHA +#define CONF_SERCOM_0_SPI_CPHA 0x0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when OVF is asserted (IBON) +// <0x0=>In data stream +// <0x1=>On buffer overflow +// spi_master_arch_ibon +#ifndef CONF_SERCOM_0_SPI_IBON +#define CONF_SERCOM_0_SPI_IBON 0x0 +#endif + +// Run in stand-by +// Module stays active in stand-by sleep mode. (RUNSTDBY) +// spi_master_arch_runstdby +#ifndef CONF_SERCOM_0_SPI_RUNSTDBY +#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) +// <0=>Keep running +// <1=>Halt +// spi_master_arch_dbgstop +#ifndef CONF_SERCOM_0_SPI_DBGSTOP +#define CONF_SERCOM_0_SPI_DBGSTOP 0 +#endif + +// + +// Address mode disabled in master mode +#ifndef CONF_SERCOM_0_SPI_AMODE_EN +#define CONF_SERCOM_0_SPI_AMODE_EN 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_AMODE +#define CONF_SERCOM_0_SPI_AMODE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDR +#define CONF_SERCOM_0_SPI_ADDR 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_ADDRMASK +#define CONF_SERCOM_0_SPI_ADDRMASK 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_SSDE +#define CONF_SERCOM_0_SPI_SSDE 0 +#endif + +#ifndef CONF_SERCOM_0_SPI_MSSEN +#define CONF_SERCOM_0_SPI_MSSEN 0x0 +#endif + +#ifndef CONF_SERCOM_0_SPI_PLOADEN +#define CONF_SERCOM_0_SPI_PLOADEN 0 +#endif + +// Receive Data Pinout +// <0x0=>PAD[0] +// <0x1=>PAD[1] +// <0x2=>PAD[2] +// <0x3=>PAD[3] +// spi_master_rxpo +#ifndef CONF_SERCOM_0_SPI_RXPO +#define CONF_SERCOM_0_SPI_RXPO 2 +#endif + +// Transmit Data Pinout +// <0x0=>PAD[0,1]_DO_SCK +// <0x1=>PAD[2,3]_DO_SCK +// <0x2=>PAD[3,1]_DO_SCK +// <0x3=>PAD[0,3]_DO_SCK +// spi_master_txpo +#ifndef CONF_SERCOM_0_SPI_TXPO +#define CONF_SERCOM_0_SPI_TXPO 0 +#endif + +// Calculate baud register value from requested baudrate value +#ifndef CONF_SERCOM_0_SPI_BAUD_RATE +#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 +#endif + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_0_I2CM_BAUD +#define CONF_SERCOM_0_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_0_I2CM_TRISE +#define CONF_SERCOM_0_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN +#define CONF_SERCOM_0_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN +#define CONF_SERCOM_0_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_0_I2CM_LOWTOUT +#define CONF_SERCOM_0_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_0_I2CM_INACTOUT +#define CONF_SERCOM_0_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_0_I2CM_SDAHOLD +#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY +#define CONF_SERCOM_0_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_0_I2CM_SPEED +#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_0_I2CM_TRISE +#define CONF_SERCOM_0_I2CM_TRISE 215 +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10) \ + - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000) \ + / 1000)) \ + * 10 \ + + 5) \ + / (CONF_SERCOM_0_I2CM_BAUD * 10)) +#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE +#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_0_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_0_I2CM_BAUD_RATE \ + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +#include + +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_1_USART_RXEN +#define CONF_SERCOM_1_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_1_USART_TXEN +#define CONF_SERCOM_1_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_1_USART_PARITY +#define CONF_SERCOM_1_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_1_USART_CHSIZE +#define CONF_SERCOM_1_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_1_USART_SBMODE +#define CONF_SERCOM_1_USART_SBMODE 0 +#endif + +// Baud rate <1-3000000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_1_USART_BAUD +#define CONF_SERCOM_1_USART_BAUD 9600 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_1_USART_ADVANCED_CONFIG +#define CONF_SERCOM_1_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_1_USART_RUNSTDBY +#define CONF_SERCOM_1_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_1_USART_IBON +#define CONF_SERCOM_1_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_1_USART_SFDE +#define CONF_SERCOM_1_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_1_USART_CLODEN +#define CONF_SERCOM_1_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_1_USART_MODE +#define CONF_SERCOM_1_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x3=>3x +// How many over-sampling bits used when samling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_1_USART_SAMPR +#define CONF_SERCOM_1_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_1_USART_SAMPA +#define CONF_SERCOM_1_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_1_USART_FRACTIONAL +#define CONF_SERCOM_1_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_1_USART_DORD +#define CONF_SERCOM_1_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_1_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_1_USART_ENC +#define CONF_SERCOM_1_USART_ENC 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_1_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_1_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_1_USART_INACK +#define CONF_SERCOM_1_USART_INACK 0x0 +#endif + +#ifndef CONF_SERCOM_1_USART_DSNACK +#define CONF_SERCOM_1_USART_DSNACK 0x0 +#endif + +#ifndef CONF_SERCOM_1_USART_MAXITER +#define CONF_SERCOM_1_USART_MAXITER 0x7 +#endif + +#ifndef CONF_SERCOM_1_USART_GTIME +#define CONF_SERCOM_1_USART_GTIME 0x2 +#endif + +#define CONF_SERCOM_1_USART_RXINV 0x0 +#define CONF_SERCOM_1_USART_TXINV 0x0 + +#ifndef CONF_SERCOM_1_USART_CMODE +#define CONF_SERCOM_1_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_1_USART_RXPO +#define CONF_SERCOM_1_USART_RXPO 1 /* RX is on PIN_PA01 */ +#endif + +#ifndef CONF_SERCOM_1_USART_TXPO +#define CONF_SERCOM_1_USART_TXPO 0 /* TX is on PIN_PA00 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_1_USART_PARITY == 0 +#define CONF_SERCOM_1_USART_PMODE 0 +#define CONF_SERCOM_1_USART_FORM 0 +#else +#define CONF_SERCOM_1_USART_PMODE CONF_SERCOM_1_USART_PARITY - 1 +#define CONF_SERCOM_1_USART_FORM 1 +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_1_USART_SAMPR == 0 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 1 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 16)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 2 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 3 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 8)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_1_USART_SAMPR == 4 +#ifndef CONF_SERCOM_1_USART_BAUD_RATE +#define CONF_SERCOM_1_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_systick_config.h b/atmel-samd/asf4/samd51/config/hpl_systick_config.h new file mode 100644 index 0000000000000..a7f2f36208fa7 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_tc_config.h b/atmel-samd/asf4/samd51/config/hpl_tc_config.h new file mode 100644 index 0000000000000..38d48e9b67c51 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_tc_config.h @@ -0,0 +1,209 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +// Basic settings +// Prescaler +// <0=> No division +// <1=> Divide by 2 +// <2=> Divide by 4 +// <3=> Divide by 8 +// <4=> Divide by 16 +// <5=> Divide by 64 +// <6=> Divide by 256 +// <7=> Divide by 1024 +// This defines the prescaler value +// tc_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0 +#endif +// + +// PWM Waveform Output settings +// Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tc_arch_wave_per_val +#ifndef CONF_TC0_WAVE_PER_VAL +#define CONF_TC0_WAVE_PER_VAL 0x3e8 +#endif + +// Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tc_arch_wave_duty_val +#ifndef CONF_TC0_WAVE_DUTY_VAL +#define CONF_TC0_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 \ + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 64000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 256000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) +#endif + +// + +// Advanced settings +// Mode +// Counter in 16-bit mode +// Counter in 32-bit mode +// These bits mode +// tc_mode +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT16_Val +#endif + +// Period Value <0x00000000-0xFFFFFFFF> +// tc_per +#ifndef CONF_TC0_PER +#define CONF_TC0_PER 0x32 +#endif +// + +// Advanced settings +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the will continue running in standby sleep mode or not +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// On-Demand +// Indicates whether the TC0's on-demand mode is on or not +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// Auto Lock +// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event +// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event +// tc_arch_alock +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CAPTEN0 0 +//#define CONF_TC0_CAPTEN1 0 +//#define CONF_TC0_COPEN0 0 +//#define CONF_TC0_COPEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_DIR 0 +//#define CONF_TC0_ONESHOT 0 +//#define CONF_TC0_LUPD 0 + +// Debug Running Mode +// Indicates whether the Debug Running Mode is enabled or not +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_INVEN0 0 +//#define CONF_TC0_INVEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_PERBUF 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CCBUF0 0 +//#define CONF_TC0_CCBUF1 0 + +// + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_trng_config.h b/atmel-samd/asf4/samd51/config/hpl_trng_config.h new file mode 100644 index 0000000000000..ba9014989a95f --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_trng_config.h @@ -0,0 +1,27 @@ +/* Auto-generated config file hpl_trng_config.h */ +#ifndef HPL_TRNG_CONFIG_H +#define HPL_TRNG_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced configurations + +// Run In Standby +// Indicates whether the TRNG works in standby mode +// trng_runstdby +#ifndef CONF_TRNG_RUNSTDBY +#define CONF_TRNG_RUNSTDBY 0 +#endif + +// Data Ready Event Output Enable +// Indicates whether the TRNG generates event on Data Ready +// trng_datardyeo +#ifndef CONF_TRNG_DATARDYEO +#define CONF_TRNG_DATARDYEO 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_TRNG_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_usb_config.h b/atmel-samd/asf4/samd51/config/hpl_usb_config.h new file mode 100644 index 0000000000000..73a9fea442158 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/hpl_usb_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// USB Device HAL Configuration + +// Max number of endpoints supported +// Limits the number of endpoints (described by EP address) can be used in app. +// 1 (EP0 only) +// 2 (EP0 + 1 endpoint) +// 3 (EP0 + 2 endpoints) +// 4 (EP0 + 3 endpoints) +// 5 (EP0 + 4 endpoints) +// 6 (EP0 + 5 endpoints) +// 7 (EP0 + 6 endpoints) +// 8 (EP0 + 7 endpoints) +// Max possible (by "Max Endpoint Number" config) +// usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 +#endif + +// + +// Max Endpoint Number supported +// Limits the max endpoint number. +// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// Reduce the value according to specific device design, to cut-off memory usage. +// 0 (only EP0) +// 1 (EP 0x81 or 0x01) +// 2 (EP 0x82 or 0x02) +// 3 (EP 0x83 or 0x03) +// 4 (EP 0x84 or 0x04) +// 5 (EP 0x85 or 0x05) +// 6 (EP 0x86 or 0x06) +// 7 (EP 0x87 or 0x07) +// Max possible (by HW) +// The number of physical endpoints - 1 +// usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 +#endif + +// USB Speed Limit +// Limits the working speed of the device. +// Full speed +// Low Speed +// usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// Cache buffer size for EP0 +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// Cache configuration EP1 +// Cache buffer size for EP1 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 64 +#endif + +// Cache buffer size for EP1 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 0 +#endif +// + +// Cache configuration EP2 +// Cache buffer size for EP2 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 64 +#endif + +// Cache buffer size for EP2 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// + +// Cache configuration EP3 +// Cache buffer size for EP3 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 64 +#endif + +// Cache buffer size for EP3 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// + +// Cache configuration EP4 +// Cache buffer size for EP4 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 64 +#endif + +// Cache buffer size for EP4 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// + +// Cache configuration EP5 +// Cache buffer size for EP5 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 64 +#endif + +// Cache buffer size for EP5 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// + +// Cache configuration EP6 +// Cache buffer size for EP6 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 64 +#endif + +// Cache buffer size for EP6 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// + +// Cache configuration EP7 +// Cache buffer size for EP7 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 64 +#endif + +// Cache buffer size for EP7 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/peripheral_clk_config.h b/atmel-samd/asf4/samd51/config/peripheral_clk_config.h new file mode 100644 index 0000000000000..2776054173554 --- /dev/null +++ b/atmel-samd/asf4/samd51/config/peripheral_clk_config.h @@ -0,0 +1,926 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ADC Clock Source +// adc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for ADC. +#ifndef CONF_GCLK_ADC0_SRC +#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_ADC0_FREQUENCY + * \brief ADC0's Clock frequency + */ +#ifndef CONF_GCLK_ADC0_FREQUENCY +#define CONF_GCLK_ADC0_FREQUENCY 12000000 +#endif + +// DAC Clock Source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// dac_gclk_selection +// Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 12000000 +#endif + +// EVSYS Channel 0 Clock Source +// evsys_clk_selection_0 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 0. +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC +#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 1 Clock Source +// evsys_clk_selection_1 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 1. +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC +#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 2 Clock Source +// evsys_clk_selection_2 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 2. +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC +#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 3 Clock Source +// evsys_clk_selection_3 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 3. +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC +#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 4 Clock Source +// evsys_clk_selection_4 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 4. +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC +#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 5 Clock Source +// evsys_clk_selection_5 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 5. +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC +#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 6 Clock Source +// evsys_clk_selection_6 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 6. +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC +#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 7 Clock Source +// evsys_clk_selection_7 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 7. +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC +#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 8 Clock Source +// evsys_clk_selection_8 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 8. +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC +#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 9 Clock Source +// evsys_clk_selection_9 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 9. +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC +#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 10 Clock Source +// evsys_clk_selection_10 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 10. +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC +#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000.0 +#endif + +// EVSYS Channel 11 Clock Source +// evsys_clk_selection_11 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 11. +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC +#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000.0 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 12000000 +#endif + +// RTC Clock Source +// rtc_clk_selection +// RTC source +// Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1024 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 12000000 +#endif + +// USB Clock Source +// usb_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK0_Val + +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 12000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/documentation/usb_device_composite.rst b/atmel-samd/asf4/samd51/documentation/usb_device_composite.rst new file mode 100644 index 0000000000000..1d6151cc2333f --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_device_composite.rst @@ -0,0 +1,32 @@ +==================== +USB Device Composite +==================== + +USB Device Composite is a part of the USB Device Stack library. It provides the support for +combining different USB classes into one USB device application. For more detailed features +or use cases introduction, user can refer to the related class documents. + + +Features +-------- +* Combination of different USB classes. + + +Applications +------------ + +* An USB device which is composed by CDC ACM, HID Keyboard,etc. + +Dependencies +------------ + +* USB Device Driver +* USB Device Stack Core +* USB Device CDC +* USB Device HID + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_device_core.rst b/atmel-samd/asf4/samd51/documentation/usb_device_core.rst new file mode 100644 index 0000000000000..fc70186258c2e --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_device_core.rst @@ -0,0 +1,41 @@ +=============== +USB Device Core +=============== + +USB Device Core is a part of the USB Device Stack library. It handles all the requests +during USB Enumeration process and helps upper class driver to be installed successfully +if only the descriptor configuration is correct. For more detailed description about Bus +Enumeration, user can refer to Chapter 9 (USB Device Framework) in Universal Serial Bus +Specification. + +Features +-------- +* Initialization/de-initialization +* Enabling/disabling USB device class components +* Data Transfer +* Attaching/detaching control +* Waking up by USB host +* Callbacks management on: + + * SOF event + * USB Device state change + * USB Device request handler + + +Applications +------------ + +N/A + +Dependencies +------------ + +* USB Device Driver +* USB Protocol Core + + +Limitations +----------- + +* It is recommended that at least one device class should run above the USB + device core. diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_cdc.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_cdc.rst new file mode 100644 index 0000000000000..3cf414b92a7a9 --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_protocol_cdc.rst @@ -0,0 +1,24 @@ +================ +USB CDC Protocol +================ + +USB CDC Protocol is a part of the USB Device Stack library. It provides basic +macro definitions and data structures which are compliant with CDC(Communications +Device Class) Specification version 1.2. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_core.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_core.rst new file mode 100644 index 0000000000000..4d5e01bbf392e --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_protocol_core.rst @@ -0,0 +1,40 @@ +================= +USB Protocol Core +================= + +USB Protocol Core is a part of the USB Device Stack library. It provides basic +macro definitions, data structures and API functions which are compliant with +USB specification version 2.0.0/2.0.1 for user. + +In addition, it provides interfaces of USB descriptor searching for the upper +layer to use, which is especially helpful in the USB enumeration process. + +Features +-------- +* Packaging USB device, configuration, interface, endpoint descriptors. +* Getting the descriptor length or type from an assigned USB descriptor. +* Getting VID, PID value from an assigned USB descriptor. +* Getting the total length of an USB configuration descriptor. +* Finding the next valid descriptor in a given USB descriptor. +* Finding an endpoint descriptor in a given USB descriptor. +* Finding a specific descriptor by an assigned descriptor type. +* Finding a configure descriptor by an assigned configure value. +* Finding a string descriptor by an assigned string index. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A + diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_hid.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_hid.rst new file mode 100644 index 0000000000000..613c22cec84cc --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_protocol_hid.rst @@ -0,0 +1,24 @@ +================ +USB HID Protocol +================ + +USB HID Protocol is a part of the USB Device Stack library. It provides basic +macro definitions and data structures which are compliant with HID(Human Interface +Device) Specification version 1.11. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_hub.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_hub.rst new file mode 100644 index 0000000000000..d60b0bbfd4268 --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_protocol_hub.rst @@ -0,0 +1,32 @@ +====================== +USB Protocol Hub Class +====================== + +USB Protocol Hub Class is a part of the USB Device Stack library. It provides +basic macro definitions, data structures and API functions which are compliant +with Hub part of USB specification version 2.0.0/2.0.1 for user. + +In addition, it provides interfaces of USB requests filling and input data +analyzing for the upper layer to use. + +Features +-------- +* Hub requests filling +* Hub change bitmap analyzing + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A + diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_msc.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_msc.rst new file mode 100644 index 0000000000000..6c7df54507dde --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_protocol_msc.rst @@ -0,0 +1,25 @@ +================ +USB MSC Protocol +================ + +USB MSC Protocol is a part of the USB Device Stack library. It provides basic +macro definitions and data structures which are compliant with Mass Storage +Control/Bulk/Interrupt (CBI) Specification 1.1 and Mass Storage UFI Command +Specification 1.0. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_vendor.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_vendor.rst new file mode 100644 index 0000000000000..e244675a67a59 --- /dev/null +++ b/atmel-samd/asf4/samd51/documentation/usb_protocol_vendor.rst @@ -0,0 +1,24 @@ +=================== +USB Vendor Protocol +=================== + +USB Vendor Protocol is a part of the USB Device Stack library. It provides basic +macro definitions which are compliant with Universal Serial Bus Specification +Revision 2.0. + + +Applications +------------ + +N/A + +Dependencies +------------ + +N/A + + +Limitations +----------- + +N/A diff --git a/atmel-samd/asf4/samd51/driver_init.c b/atmel-samd/asf4/samd51/driver_init.c new file mode 100644 index 0000000000000..d41c76318ac8f --- /dev/null +++ b/atmel-samd/asf4/samd51/driver_init.c @@ -0,0 +1,359 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include +#include +#include + +struct timer_descriptor TIMER_0; +struct spi_m_sync_descriptor SPI_0; + +struct adc_sync_descriptor ADC_0; + +struct dac_sync_descriptor DAC_0; + +struct i2c_m_sync_desc I2C_0; + +struct usart_sync_descriptor USART_0; + +struct pwm_descriptor PWM_0; + +struct rand_sync_desc RAND_0; + +void ADC_0_PORT_init(void) +{ +} + +void ADC_0_CLOCK_init(void) +{ + hri_mclk_set_APBDMASK_ADC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); +} + +void ADC_0_init(void) +{ + ADC_0_CLOCK_init(); + ADC_0_PORT_init(); + adc_sync_init(&ADC_0, ADC0, (void *)NULL); +} + +void DAC_0_PORT_init(void) +{ +} + +void DAC_0_CLOCK_init(void) +{ + + hri_mclk_set_APBDMASK_DAC_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, DAC_GCLK_ID, CONF_GCLK_DAC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); +} + +void DAC_0_init(void) +{ + DAC_0_CLOCK_init(); + dac_sync_init(&DAC_0, DAC); + DAC_0_PORT_init(); +} + +void EVENT_SYSTEM_0_init(void) +{ + + hri_mclk_set_APBBMASK_EVSYS_bit(MCLK); + event_system_init(); +} + +/** + * \brief Timer initialization function + * + * Enables Timer peripheral, clocks and initializes Timer driver + */ +static void TIMER_0_init(void) +{ + hri_mclk_set_APBAMASK_RTC_bit(MCLK); + timer_init(&TIMER_0, RTC, _rtc_get_timer()); +} + +void SPI_0_PORT_init(void) +{ + + // Set pin direction to output + gpio_set_pin_direction(PA04, GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA04, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0); + + // Set pin direction to output + gpio_set_pin_direction(PA05, GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA05, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1); + + // Set pin direction to input + gpio_set_pin_direction(PA06, GPIO_DIRECTION_IN); + + gpio_set_pin_pull_mode(PA06, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA06, PINMUX_PA06D_SERCOM0_PAD2); +} + +void SPI_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); +} + +void SPI_0_init(void) +{ + SPI_0_CLOCK_init(); + spi_m_sync_init(&SPI_0, SERCOM0); + SPI_0_PORT_init(); +} + +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_function(PA08, PINMUX_PA08C_SERCOM0_PAD0); + + gpio_set_pin_function(PA09, PINMUX_PA09C_SERCOM0_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM0); + I2C_0_PORT_init(); +} + +void USART_0_PORT_init(void) +{ + + gpio_set_pin_function(PA00, PINMUX_PA00D_SERCOM1_PAD0); + + gpio_set_pin_function(PA01, PINMUX_PA01D_SERCOM1_PAD1); +} + +void USART_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK); +} + +void USART_0_init(void) +{ + USART_0_CLOCK_init(); + usart_sync_init(&USART_0, SERCOM1, (void *)NULL); + USART_0_PORT_init(); +} + +void delay_driver_init(void) +{ + delay_init(SysTick); +} + +void PWM_0_PORT_init(void) +{ +} + +void PWM_0_CLOCK_init(void) +{ + hri_mclk_set_APBAMASK_TC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); +} + +void PWM_0_init(void) +{ + PWM_0_CLOCK_init(); + PWM_0_PORT_init(); + pwm_init(&PWM_0, TC0, _tc_get_pwm()); +} + +void RAND_0_CLOCK_init(void) +{ + hri_mclk_set_APBCMASK_TRNG_bit(MCLK); +} + +void RAND_0_init(void) +{ + RAND_0_CLOCK_init(); + rand_sync_init(&RAND_0, TRNG); +} + +void USB_DEVICE_INSTANCE_PORT_init(void) +{ + + gpio_set_pin_direction(PA24, + // Pin direction + // pad_direction + // Off + // In + // Out + GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA24, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_pull_mode(PA24, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA24, + // Pin function + // pad_function + // Auto : use driver pinmux if signal is imported by driver, else turn off function + // Auto + // Off + // A + // B + // C + // D + // E + // F + // G + // H + // I + // J + // K + // L + // M + // N + PINMUX_PA24H_USB_DM); + + gpio_set_pin_direction(PA25, + // Pin direction + // pad_direction + // Off + // In + // Out + GPIO_DIRECTION_OUT); + + gpio_set_pin_level(PA25, + // Initial level + // pad_initial_level + // Low + // High + false); + + gpio_set_pin_pull_mode(PA25, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA25, + // Pin function + // pad_function + // Auto : use driver pinmux if signal is imported by driver, else turn off function + // Auto + // Off + // A + // B + // C + // D + // E + // F + // G + // H + // I + // J + // K + // L + // M + // N + PINMUX_PA25H_USB_DP); +} + +/* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock + * for low speed and full speed operation. */ +#if (CONF_GCLK_USB_FREQUENCY > (48000000 + 48000000 / 400)) || (CONF_GCLK_USB_FREQUENCY < (48000000 - 48000000 / 400)) +#warning USB clock should be 48MHz ~ 0.25% clock, check your configuration! +#endif + +void USB_DEVICE_INSTANCE_CLOCK_init(void) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, CONF_GCLK_USB_SRC | GCLK_PCHCTRL_CHEN); + hri_mclk_set_AHBMASK_USB_bit(MCLK); + hri_mclk_set_APBBMASK_USB_bit(MCLK); +} + +void USB_DEVICE_INSTANCE_init(void) +{ + USB_DEVICE_INSTANCE_CLOCK_init(); + usb_d_init(); + USB_DEVICE_INSTANCE_PORT_init(); +} + +void system_init(void) +{ + init_mcu(); + + ADC_0_init(); + + DAC_0_init(); + + EVENT_SYSTEM_0_init(); + + TIMER_0_init(); + + SPI_0_init(); + + I2C_0_init(); + + USART_0_init(); + + delay_driver_init(); + + PWM_0_init(); + + RAND_0_init(); + + USB_DEVICE_INSTANCE_init(); +} diff --git a/atmel-samd/asf4/samd51/driver_init.h b/atmel-samd/asf4/samd51/driver_init.h new file mode 100644 index 0000000000000..bbae30a2ceee2 --- /dev/null +++ b/atmel-samd/asf4/samd51/driver_init.h @@ -0,0 +1,100 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include + +#include +#include + +#include + +#include + +#include +#include +#include + +#include + +#include "hal_usb_device.h" + +extern struct adc_sync_descriptor ADC_0; + +extern struct dac_sync_descriptor DAC_0; +extern struct timer_descriptor TIMER_0; +extern struct spi_m_sync_descriptor SPI_0; + +extern struct i2c_m_sync_desc I2C_0; + +extern struct usart_sync_descriptor USART_0; + +extern struct pwm_descriptor PWM_0; + +extern struct rand_sync_desc RAND_0; + +void ADC_0_PORT_init(void); +void ADC_0_CLOCK_init(void); +void ADC_0_init(void); + +void DAC_0_PORT_init(void); +void DAC_0_CLOCK_init(void); +void DAC_0_init(void); + +void SPI_0_PORT_init(void); +void SPI_0_CLOCK_init(void); +void SPI_0_init(void); + +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + +void USART_0_PORT_init(void); +void USART_0_CLOCK_init(void); +void USART_0_init(void); + +void delay_driver_init(void); + +void PWM_0_PORT_init(void); +void PWM_0_CLOCK_init(void); +void PWM_0_init(void); + +void RAND_0_CLOCK_init(void); +void RAND_0_init(void); + +void USB_DEVICE_INSTANCE_CLOCK_init(void); +void USB_DEVICE_INSTANCE_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/atmel-samd/asf4/samd51/examples/driver_examples.c b/atmel-samd/asf4/samd51/examples/driver_examples.c new file mode 100644 index 0000000000000..0b0b9ffef2c9a --- /dev/null +++ b/atmel-samd/asf4/samd51/examples/driver_examples.c @@ -0,0 +1,138 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using ADC_0 to generate waveform. + */ +void ADC_0_example(void) +{ + uint8_t buffer[2]; + + adc_sync_enable_channel(&ADC_0, 0); + + while (1) { + adc_sync_read_channel(&ADC_0, 0, buffer, 2); + } +} + +/** + * Example of using DAC_0 to generate waveform. + */ +void DAC_0_example(void) +{ + uint16_t i = 0; + + dac_sync_enable_channel(&DAC_0, 0); + + for (;;) { + dac_sync_write(&DAC_0, 0, &i, 1); + i = (i + 1) % 1024; + } +} + +static struct timer_task TIMER_0_task1, TIMER_0_task2; +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + TIMER_0_task2.interval = 200; + TIMER_0_task2.cb = TIMER_0_task2_cb; + TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_add_task(&TIMER_0, &TIMER_0_task2); + timer_start(&TIMER_0); +} + +/** + * Example of using SPI_0 to write "Hello World" using the IO abstraction. + */ +static uint8_t example_SPI_0[12] = "Hello World!"; + +void SPI_0_example(void) +{ + struct io_descriptor *io; + spi_m_sync_get_io_descriptor(&SPI_0, &io); + + spi_m_sync_enable(&SPI_0); + io_write(io, example_SPI_0, 12); +} + +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + +/** + * Example of using USART_0 to write "Hello World" using the IO abstraction. + */ +void USART_0_example(void) +{ + struct io_descriptor *io; + usart_sync_get_io_descriptor(&USART_0, &io); + usart_sync_enable(&USART_0); + + io_write(io, (uint8_t *)"Hello World!", 12); +} + +void delay_example(void) +{ + delay_ms(5000); +} + +/** + * Example of using PWM_0. + */ +void PWM_0_example(void) +{ + pwm_set_parameters(&PWM_0, 10000, 5000); + pwm_enable(&PWM_0); +} + +/** + * Example of using RAND_0 to generate waveform. + */ +void RAND_0_example(void) +{ + uint32_t random_n[4]; + rand_sync_enable(&RAND_0); + random_n[0] = rand_sync_read32(&RAND_0); + random_n[1] = rand_sync_read32(&RAND_0); + rand_sync_read_buf32(&RAND_0, &random_n[2], 2); + if (random_n[0] == random_n[1]) { + /* halt */ + while (1) + ; + } + if (random_n[2] == random_n[3]) { + /* halt */ + while (1) + ; + } +} diff --git a/atmel-samd/asf4/samd51/examples/driver_examples.h b/atmel-samd/asf4/samd51/examples/driver_examples.h new file mode 100644 index 0000000000000..31bcb9f10ae3c --- /dev/null +++ b/atmel-samd/asf4/samd51/examples/driver_examples.h @@ -0,0 +1,32 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void ADC_0_example(void); + +void DAC_0_example(void); + +void I2C_0_example(void); + +void USART_0_example(void); + +void delay_example(void); + +void PWM_0_example(void); + +void RAND_0_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/atmel-samd/asf4/samd51/gcc/Makefile b/atmel-samd/asf4/samd51/gcc/Makefile new file mode 100644 index 0000000000000..74794ef1e7a11 --- /dev/null +++ b/atmel-samd/asf4/samd51/gcc/Makefile @@ -0,0 +1,301 @@ + +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif +endif + +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/adc \ +usb/class/cdc/device \ +hpl/ramecc \ +hpl/evsys \ +examples \ +hpl/systick \ +hpl/oscctrl \ +hpl/tc \ +hpl/osc32kctrl \ +usb \ +hpl/dmac \ +hal/src \ +hal/utils/src \ +hpl/rtc \ +hpl/trng \ +usb/class/hid/device \ +hpl/usb \ +gcc \ +hpl/mclk \ +hpl/gclk \ +gcc/gcc \ +usb/device \ +hpl/pm \ +hpl/dac \ +hpl/sercom \ +hpl/core + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hpl/systick/hpl_systick.o \ +usb/class/hid/device/hiddf_generic.o \ +hpl/evsys/hpl_evsys.o \ +hpl/core/hpl_core_m4.o \ +usb/class/cdc/device/cdcdf_acm.o \ +hal/utils/src/utils_syscalls.o \ +hpl/mclk/hpl_mclk.o \ +hal/src/hal_spi_m_sync.o \ +hal/src/hal_timer.o \ +hal/src/hal_pwm.o \ +hpl/usb/hpl_usb.o \ +hal/src/hal_i2c_m_sync.o \ +hal/src/hal_delay.o \ +hpl/pm/hpl_pm.o \ +hpl/core/hpl_init.o \ +hpl/ramecc/hpl_ramecc.o \ +hal/utils/src/utils_list.o \ +usb/class/hid/device/hiddf_mouse.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/oscctrl/hpl_oscctrl.o \ +hal/src/hal_rand_sync.o \ +hpl/trng/hpl_trng.o \ +usb/class/hid/device/hiddf_keyboard.o \ +hal/src/hal_usart_sync.o \ +hpl/dac/hpl_dac.o \ +hpl/gclk/hpl_gclk.o \ +usb/usb_protocol.o \ +hal/src/hal_init.o \ +gcc/system_samd51.o \ +gcc/gcc/startup_samd51.o \ +hal/src/hal_usb_device.o \ +main.o \ +hpl/osc32kctrl/hpl_osc32kctrl.o \ +hpl/rtc/hpl_rtc.o \ +examples/driver_examples.o \ +driver_init.o \ +hal/src/hal_adc_sync.o \ +hal/src/hal_dac_sync.o \ +hpl/sercom/hpl_sercom.o \ +hal/src/hal_gpio.o \ +hal/src/hal_evsys.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +usb_start.o \ +atmel_start.o \ +usb/device/usbdc.o \ +hpl/tc/hpl_tc.o \ +hal/src/hal_atomic.o \ +hpl/adc/hpl_adc.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hpl/systick/hpl_systick.o" \ +"usb/class/hid/device/hiddf_generic.o" \ +"hpl/evsys/hpl_evsys.o" \ +"hpl/core/hpl_core_m4.o" \ +"usb/class/cdc/device/cdcdf_acm.o" \ +"hal/utils/src/utils_syscalls.o" \ +"hpl/mclk/hpl_mclk.o" \ +"hal/src/hal_spi_m_sync.o" \ +"hal/src/hal_timer.o" \ +"hal/src/hal_pwm.o" \ +"hpl/usb/hpl_usb.o" \ +"hal/src/hal_i2c_m_sync.o" \ +"hal/src/hal_delay.o" \ +"hpl/pm/hpl_pm.o" \ +"hpl/core/hpl_init.o" \ +"hpl/ramecc/hpl_ramecc.o" \ +"hal/utils/src/utils_list.o" \ +"usb/class/hid/device/hiddf_mouse.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/oscctrl/hpl_oscctrl.o" \ +"hal/src/hal_rand_sync.o" \ +"hpl/trng/hpl_trng.o" \ +"usb/class/hid/device/hiddf_keyboard.o" \ +"hal/src/hal_usart_sync.o" \ +"hpl/dac/hpl_dac.o" \ +"hpl/gclk/hpl_gclk.o" \ +"usb/usb_protocol.o" \ +"hal/src/hal_init.o" \ +"gcc/system_samd51.o" \ +"gcc/gcc/startup_samd51.o" \ +"hal/src/hal_usb_device.o" \ +"main.o" \ +"hpl/osc32kctrl/hpl_osc32kctrl.o" \ +"hpl/rtc/hpl_rtc.o" \ +"examples/driver_examples.o" \ +"driver_init.o" \ +"hal/src/hal_adc_sync.o" \ +"hal/src/hal_dac_sync.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hal/src/hal_gpio.o" \ +"hal/src/hal_evsys.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"usb_start.o" \ +"atmel_start.o" \ +"usb/device/usbdc.o" \ +"hpl/tc/hpl_tc.o" \ +"hal/src/hal_atomic.o" \ +"hpl/adc/hpl_adc.o" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"hpl/ramecc/hpl_ramecc.d" \ +"hpl/systick/hpl_systick.d" \ +"hpl/core/hpl_core_m4.d" \ +"hpl/evsys/hpl_evsys.d" \ +"hal/utils/src/utils_syscalls.d" \ +"usb/class/cdc/device/cdcdf_acm.d" \ +"gcc/gcc/startup_samd51.d" \ +"hal/src/hal_i2c_m_sync.d" \ +"hpl/usb/hpl_usb.d" \ +"hal/src/hal_evsys.d" \ +"hal/src/hal_pwm.d" \ +"hal/src/hal_timer.d" \ +"hal/src/hal_spi_m_sync.d" \ +"usb/class/hid/device/hiddf_mouse.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hpl/mclk/hpl_mclk.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/pm/hpl_pm.d" \ +"usb/usb_protocol.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hal/src/hal_usb_device.d" \ +"usb_start.d" \ +"hal/src/hal_init.d" \ +"hal/src/hal_usart_sync.d" \ +"usb/class/hid/device/hiddf_keyboard.d" \ +"hpl/trng/hpl_trng.d" \ +"hal/src/hal_rand_sync.d" \ +"hpl/dac/hpl_dac.d" \ +"driver_init.d" \ +"hal/src/hal_adc_sync.d" \ +"hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"main.d" \ +"examples/driver_examples.d" \ +"hpl/rtc/hpl_rtc.d" \ +"hal/src/hal_sleep.d" \ +"hpl/sercom/hpl_sercom.d" \ +"hal/src/hal_dac_sync.d" \ +"hal/src/hal_gpio.d" \ +"usb/class/hid/device/hiddf_generic.d" \ +"hal/src/hal_atomic.d" \ +"hpl/tc/hpl_tc.d" \ +"usb/device/usbdc.d" \ +"hpl/oscctrl/hpl_oscctrl.d" \ +"hpl/adc/hpl_adc.d" \ +"gcc/system_samd51.d" \ +"atmel_start.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARM/GNU Linker + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ +-Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \ + \ + \ +-T"../gcc/gcc/samd51g19a_flash.ld" \ +-L"../gcc/gcc" + @echo Finished building target: $@ + + "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin" + "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \ + "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex" + "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \ + .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \ + "$(OUTPUT_FILE_NAME).eep" || exit 0 + "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss" + "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf" + +# Compiler targets + + +%.o: %.c + @echo Building file: $< + @echo ARM/GNU C Compiler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARM/GNU Assembler + $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARM/GNU Preprocessing Assembler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ + $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ + $(OUTPUT_FILE_NAME).srec diff --git a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld new file mode 100644 index 0000000000000..32e509ca8e24c --- /dev/null +++ b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAMD51G19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld new file mode 100644 index 0000000000000..204f7312e2098 --- /dev/null +++ b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAMD51G19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c b/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c new file mode 100644 index 0000000000000..7963330820cbf --- /dev/null +++ b/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c @@ -0,0 +1,679 @@ +/** + * \file + * + * \brief gcc starttup file for SAMD51 + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd51.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MemManage_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DebugMon_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MCLK_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void OSCCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ +void OSCCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ +void OSCCTRL_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, + OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, + OSCCTRL_DFLLRDY */ +void OSCCTRL_3_Handler(void) __attribute__(( + weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ +void OSCCTRL_4_Handler(void) __attribute__(( + weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ +void OSC32KCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SUPC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, + SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY + */ +void SUPC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */ +void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void EIC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */ +void EIC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */ +void EIC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */ +void EIC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */ +void EIC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */ +void EIC_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */ +void EIC_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */ +void EIC_7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */ +void EIC_8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */ +void EIC_9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */ +void EIC_10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */ +void EIC_11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */ +void EIC_12_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */ +void EIC_13_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */ +void EIC_14_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */ +void EIC_15_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */ +void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, + NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, + NVMCTRL_6, NVMCTRL_7 */ +void NVMCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ +void DMAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ +void DMAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ +void DMAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ +void DMAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ +void DMAC_4_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, + DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, + DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, + DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, + DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, + DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, + DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, + DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, + DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, + DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, + DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, + DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, + DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, + DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, + DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, + DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, + DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, + DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ +void EVSYS_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */ +void EVSYS_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */ +void EVSYS_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */ +void EVSYS_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */ +void EVSYS_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, + EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, + EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, + EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, + EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, + EVSYS_OVR_9 */ +void PAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TAL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TAL_BRK */ +void TAL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TAL_IPS_0, TAL_IPS_1 */ +void RAMECC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */ +void SERCOM0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */ +void SERCOM0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */ +void SERCOM0_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ +void SERCOM1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */ +void SERCOM1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */ +void SERCOM1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */ +void SERCOM1_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ +void SERCOM2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */ +void SERCOM2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */ +void SERCOM2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */ +void SERCOM2_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ +void SERCOM3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */ +void SERCOM3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */ +void SERCOM3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */ +void SERCOM3_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 +void SERCOM4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */ +void SERCOM4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */ +void SERCOM4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */ +void SERCOM4_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#endif +#ifdef ID_SERCOM5 +void SERCOM5_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */ +void SERCOM5_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */ +void SERCOM5_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */ +void SERCOM5_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#endif +#ifdef ID_SERCOM6 +void SERCOM6_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */ +void SERCOM6_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */ +void SERCOM6_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */ +void SERCOM6_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#endif +#ifdef ID_SERCOM7 +void SERCOM7_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */ +void SERCOM7_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */ +void SERCOM7_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */ +void SERCOM7_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#endif +#ifdef ID_CAN0 +void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN1 +void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_USB +void USB_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, + USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, + USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, + USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, + USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, + USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, + USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, + USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, + USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, + USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, + USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, + USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, + USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, + USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ +void USB_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */ +void USB_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, + USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, + USB_TRCPT0_6, USB_TRCPT0_7 */ +void USB_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, + USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, + USB_TRCPT1_6, USB_TRCPT1_7 */ +#endif +#ifdef ID_GMAC +void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void TCC0_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, + TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ +void TCC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */ +void TCC0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */ +void TCC0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */ +void TCC0_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */ +void TCC0_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */ +void TCC0_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */ +void TCC1_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, + TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ +void TCC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */ +void TCC1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */ +void TCC1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */ +void TCC1_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */ +void TCC2_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, + TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ +void TCC2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */ +void TCC2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */ +void TCC2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */ +#ifdef ID_TCC3 +void TCC3_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, + TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ +void TCC3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */ +void TCC3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */ +#endif +#ifdef ID_TCC4 +void TCC4_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, + TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ +void TCC4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */ +void TCC4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */ +#endif +void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_TC4 +void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC5 +void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC6 +void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void PDEC_0_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ +void PDEC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */ +void PDEC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */ +void ADC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */ +void ADC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */ +void ADC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */ +void ADC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */ +void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DAC_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ +void DAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */ +void DAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */ +void DAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */ +void DAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */ +#ifdef ID_I2S +void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void PCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_ICM +void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PUKCC +void PUKCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_SDHC0 +void SDHC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SDHC1 +void SDHC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__((section(".vectors"), used)) const DeviceVectors exception_table + = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void *)(&_estack), + + .pfnReset_Handler = (void *)Reset_Handler, + .pfnNMI_Handler = (void *)NMI_Handler, + .pfnHardFault_Handler = (void *)HardFault_Handler, + .pfnMemManage_Handler = (void *)MemManage_Handler, + .pfnBusFault_Handler = (void *)BusFault_Handler, + .pfnUsageFault_Handler = (void *)UsageFault_Handler, + .pvReservedM9 = (void *)(0UL), /* Reserved */ + .pvReservedM8 = (void *)(0UL), /* Reserved */ + .pvReservedM7 = (void *)(0UL), /* Reserved */ + .pvReservedM6 = (void *)(0UL), /* Reserved */ + .pfnSVC_Handler = (void *)SVC_Handler, + .pfnDebugMon_Handler = (void *)DebugMon_Handler, + .pvReservedM3 = (void *)(0UL), /* Reserved */ + .pfnPendSV_Handler = (void *)PendSV_Handler, + .pfnSysTick_Handler = (void *)SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void *)MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_0_Handler = (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + .pfnOSCCTRL_1_Handler = (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + .pfnOSCCTRL_2_Handler + = (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, + OSCCTRL_DFLLRDY */ + .pfnOSCCTRL_3_Handler = (void *) + OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + .pfnOSCCTRL_4_Handler = (void *) + OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + .pfnOSC32KCTRL_Handler = (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_0_Handler = (void *)SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, + SUPC_VCORERDY, SUPC_VREGRDY */ + .pfnSUPC_1_Handler = (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ + .pfnWDT_Handler = (void *)WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void *)RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_0_Handler = (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */ + .pfnEIC_1_Handler = (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */ + .pfnEIC_2_Handler = (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */ + .pfnEIC_3_Handler = (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */ + .pfnEIC_4_Handler = (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */ + .pfnEIC_5_Handler = (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */ + .pfnEIC_6_Handler = (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */ + .pfnEIC_7_Handler = (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */ + .pfnEIC_8_Handler = (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */ + .pfnEIC_9_Handler = (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */ + .pfnEIC_10_Handler = (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */ + .pfnEIC_11_Handler = (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */ + .pfnEIC_12_Handler = (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */ + .pfnEIC_13_Handler = (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */ + .pfnEIC_14_Handler = (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */ + .pfnEIC_15_Handler = (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */ + .pfnFREQM_Handler = (void *)FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void *) + NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, + NVMCTRL_7 */ + .pfnNVMCTRL_1_Handler = (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + .pfnDMAC_0_Handler = (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + .pfnDMAC_1_Handler = (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + .pfnDMAC_2_Handler = (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + .pfnDMAC_3_Handler = (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + .pfnDMAC_4_Handler = (void *)DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, + DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, + DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, + DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, + DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, + DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, + DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, + DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, + DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, + DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, + DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, + DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, + DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, + DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, + DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, + DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, + DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, + DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, + DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, + DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, + DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + .pfnEVSYS_0_Handler = (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ + .pfnEVSYS_1_Handler = (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ + .pfnEVSYS_2_Handler = (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ + .pfnEVSYS_3_Handler = (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ + .pfnEVSYS_4_Handler = (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, + EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, + EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, + EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + .pfnPAC_Handler = (void *)PAC_Handler, /* 41 Peripheral Access Controller */ + .pfnTAL_0_Handler = (void *)TAL_0_Handler, /* 42 TAL_BRK */ + .pfnTAL_1_Handler = (void *)TAL_1_Handler, /* 43 TAL_IPS_0, TAL_IPS_1 */ + .pvReserved44 = (void *)(0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void *)RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */ + .pfnSERCOM0_1_Handler = (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */ + .pfnSERCOM0_2_Handler = (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */ + .pfnSERCOM0_3_Handler = (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + .pfnSERCOM1_0_Handler = (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */ + .pfnSERCOM1_1_Handler = (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */ + .pfnSERCOM1_2_Handler = (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */ + .pfnSERCOM1_3_Handler = (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + .pfnSERCOM2_0_Handler = (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */ + .pfnSERCOM2_1_Handler = (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */ + .pfnSERCOM2_2_Handler = (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */ + .pfnSERCOM2_3_Handler = (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + .pfnSERCOM3_0_Handler = (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */ + .pfnSERCOM3_1_Handler = (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */ + .pfnSERCOM3_2_Handler = (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */ + .pfnSERCOM3_3_Handler = (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_0_Handler = (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */ + .pfnSERCOM4_1_Handler = (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */ + .pfnSERCOM4_2_Handler = (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */ + .pfnSERCOM4_3_Handler = (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#else + .pvReserved62 = (void *)(0UL), /* 62 Reserved */ + .pvReserved63 = (void *)(0UL), /* 63 Reserved */ + .pvReserved64 = (void *)(0UL), /* 64 Reserved */ + .pvReserved65 = (void *)(0UL), /* 65 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_0_Handler = (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */ + .pfnSERCOM5_1_Handler = (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */ + .pfnSERCOM5_2_Handler = (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */ + .pfnSERCOM5_3_Handler = (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#else + .pvReserved66 = (void *)(0UL), /* 66 Reserved */ + .pvReserved67 = (void *)(0UL), /* 67 Reserved */ + .pvReserved68 = (void *)(0UL), /* 68 Reserved */ + .pvReserved69 = (void *)(0UL), /* 69 Reserved */ +#endif +#ifdef ID_SERCOM6 + .pfnSERCOM6_0_Handler = (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */ + .pfnSERCOM6_1_Handler = (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */ + .pfnSERCOM6_2_Handler = (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */ + .pfnSERCOM6_3_Handler = (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#else + .pvReserved70 = (void *)(0UL), /* 70 Reserved */ + .pvReserved71 = (void *)(0UL), /* 71 Reserved */ + .pvReserved72 = (void *)(0UL), /* 72 Reserved */ + .pvReserved73 = (void *)(0UL), /* 73 Reserved */ +#endif +#ifdef ID_SERCOM7 + .pfnSERCOM7_0_Handler = (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */ + .pfnSERCOM7_1_Handler = (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */ + .pfnSERCOM7_2_Handler = (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */ + .pfnSERCOM7_3_Handler = (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#else + .pvReserved74 = (void *)(0UL), /* 74 Reserved */ + .pvReserved75 = (void *)(0UL), /* 75 Reserved */ + .pvReserved76 = (void *)(0UL), /* 76 Reserved */ + .pvReserved77 = (void *)(0UL), /* 77 Reserved */ +#endif +#ifdef ID_CAN0 + .pfnCAN0_Handler = (void *)CAN0_Handler, /* 78 Control Area Network 0 */ +#else + .pvReserved78 = (void *)(0UL), /* 78 Reserved */ +#endif +#ifdef ID_CAN1 + .pfnCAN1_Handler = (void *)CAN1_Handler, /* 79 Control Area Network 1 */ +#else + .pvReserved79 = (void *)(0UL), /* 79 Reserved */ +#endif +#ifdef ID_USB + .pfnUSB_0_Handler = (void *) + USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, + USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, + USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, + USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, + USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, + USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, + USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, + USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, + USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, + USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, + USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + .pfnUSB_1_Handler = (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */ + .pfnUSB_2_Handler = (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, + USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + .pfnUSB_3_Handler = (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, + USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#else + .pvReserved80 = (void *)(0UL), /* 80 Reserved */ + .pvReserved81 = (void *)(0UL), /* 81 Reserved */ + .pvReserved82 = (void *)(0UL), /* 82 Reserved */ + .pvReserved83 = (void *)(0UL), /* 83 Reserved */ +#endif +#ifdef ID_GMAC + .pfnGMAC_Handler = (void *)GMAC_Handler, /* 84 Ethernet MAC */ +#else + .pvReserved84 = (void *)(0UL), /* 84 Reserved */ +#endif + .pfnTCC0_0_Handler = (void *) + TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, + TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + .pfnTCC0_1_Handler = (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */ + .pfnTCC0_2_Handler = (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */ + .pfnTCC0_3_Handler = (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */ + .pfnTCC0_4_Handler = (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */ + .pfnTCC0_5_Handler = (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */ + .pfnTCC0_6_Handler = (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */ + .pfnTCC1_0_Handler = (void *) + TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, + TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + .pfnTCC1_1_Handler = (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */ + .pfnTCC1_2_Handler = (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */ + .pfnTCC1_3_Handler = (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */ + .pfnTCC1_4_Handler = (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */ + .pfnTCC2_0_Handler = (void *) + TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, + TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + .pfnTCC2_1_Handler = (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */ + .pfnTCC2_2_Handler = (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */ + .pfnTCC2_3_Handler = (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */ +#ifdef ID_TCC3 + .pfnTCC3_0_Handler + = (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, + TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + .pfnTCC3_1_Handler = (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */ + .pfnTCC3_2_Handler = (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */ +#else + .pvReserved101 = (void *)(0UL), /* 101 Reserved */ + .pvReserved102 = (void *)(0UL), /* 102 Reserved */ + .pvReserved103 = (void *)(0UL), /* 103 Reserved */ +#endif +#ifdef ID_TCC4 + .pfnTCC4_0_Handler + = (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, + TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + .pfnTCC4_1_Handler = (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */ + .pfnTCC4_2_Handler = (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */ +#else + .pvReserved104 = (void *)(0UL), /* 104 Reserved */ + .pvReserved105 = (void *)(0UL), /* 105 Reserved */ + .pvReserved106 = (void *)(0UL), /* 106 Reserved */ +#endif + .pfnTC0_Handler = (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */ +#ifdef ID_TC4 + .pfnTC4_Handler = (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */ +#else + .pvReserved111 = (void *)(0UL), /* 111 Reserved */ +#endif +#ifdef ID_TC5 + .pfnTC5_Handler = (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */ +#else + .pvReserved112 = (void *)(0UL), /* 112 Reserved */ +#endif +#ifdef ID_TC6 + .pfnTC6_Handler = (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */ +#else + .pvReserved113 = (void *)(0UL), /* 113 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */ +#else + .pvReserved114 = (void *)(0UL), /* 114 Reserved */ +#endif + .pfnPDEC_0_Handler = (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + .pfnPDEC_1_Handler = (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */ + .pfnPDEC_2_Handler = (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */ + .pfnADC0_0_Handler = (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ + .pfnADC0_1_Handler = (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */ + .pfnADC1_0_Handler = (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ + .pfnADC1_1_Handler = (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */ + .pfnAC_Handler = (void *)AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_0_Handler + = (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + .pfnDAC_1_Handler = (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */ + .pfnDAC_2_Handler = (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */ + .pfnDAC_3_Handler = (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */ + .pfnDAC_4_Handler = (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */ +#ifdef ID_I2S + .pfnI2S_Handler = (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */ +#else + .pvReserved128 = (void *)(0UL), /* 128 Reserved */ +#endif + .pfnPCC_Handler = (void *)PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void *)AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void *)TRNG_Handler, /* 131 True Random Generator */ +#ifdef ID_ICM + .pfnICM_Handler = (void *)ICM_Handler, /* 132 Integrity Check Monitor */ +#else + .pvReserved132 = (void *)(0UL), /* 132 Reserved */ +#endif +#ifdef ID_PUKCC + .pfnPUKCC_Handler = (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ +#else + .pvReserved133 = (void *)(0UL), /* 133 Reserved */ +#endif + .pfnQSPI_Handler = (void *)QSPI_Handler, /* 134 Quad SPI interface */ +#ifdef ID_SDHC0 + .pfnSDHC0_Handler = (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ +#else + .pvReserved135 = (void *)(0UL), /* 135 Reserved */ +#endif +#ifdef ID_SDHC1 + .pfnSDHC1_Handler = (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ +#else + .pvReserved136 = (void *)(0UL) /* 136 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *)&_sfixed; + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + +#if __FPU_USED + /* Enable FPU */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); +#endif + + /* Initialize the C library */ + //__libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1) + ; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/atmel-samd/asf4/samd51/gcc/system_samd51.c b/atmel-samd/asf4/samd51/gcc/system_samd51.c new file mode 100644 index 0000000000000..fa7ed93972fb3 --- /dev/null +++ b/atmel-samd/asf4/samd51/gcc/system_samd51.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd51.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/atmel-samd/asf4/samd51/hal/documentation/adc_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/adc_sync.rst new file mode 100644 index 0000000000000..d189565ad8c73 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/adc_sync.rst @@ -0,0 +1,74 @@ +====================== +ADC Synchronous driver +====================== + +An ADC (Analog-to-Digital Converter) converts analog signals to digital values. +A reference signal with a known voltage level is quantified into equally +sized chunks, each representing a digital value from 0 to the highest number +possible with the bit resolution supported by the ADC. The input voltage +measured by the ADC is compared against these chunks and the chunk with the +closest voltage level defines the digital value that can be used to represent +the analog input voltage level. + +Usually an ADC can operate in either differential or single-ended mode. +In differential mode two signals (V+ and V-) are compared against each other +and the resulting digital value represents the relative voltage level between +V+ and V-. This means that if the input voltage level on V+ is lower than on +V- the digital value is negative, which also means that in differential +mode one bit is lost to the sign. In single-ended mode only V+ is compared +against the reference voltage, and the resulting digital value can only be +positive, but the full bit-range of the ADC can be used. + +Usually multiple resolutions are supported by the ADC, lower resolution can +reduce the conversion time, but lose accuracy. + +Some ADCs has a gain stage on the input lines which can be used to increase the +dynamic range. The default gain value is usually x1, which means that the +conversion range is from 0V to the reference voltage. +Applications can change the gain stage, to increase or reduce the conversion +range. + +The window mode allows the conversion result to be compared to a set of +predefined threshold values. Applications can use callback function to monitor +if the conversion result exceeds predefined threshold value. + +Usually multiple reference voltages are supported by the ADC, both internal and +external with difference voltage levels. The reference voltage have an impact +on the accuracy, and should be selected to cover the full range of the analog +input signal and never less than the expected maximum input voltage. + +There are two conversion modes supported by ADC, single shot and free running. +In single shot mode the ADC only make one conversion when triggered by the +application, in free running mode it continues to make conversion from it +is triggered until it is stopped by the application. When window monitoring, +the ADC should be set to free running mode. + +Features +-------- +* Initialization and de-initialization +* Support multiple Conversion Mode, Single or Free run +* Start ADC Conversion +* Read Conversion Result + +Applications +------------ +* Measurement of internal sensor. E.g., MCU internal temperature sensor value. +* Measurement of external sensor. E.g., Temperature, humidity sensor value. +* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave. + +Dependencies +------------ +* ADC hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/atmel-samd/asf4/samd51/hal/documentation/dac_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/dac_sync.rst new file mode 100644 index 0000000000000..b3f3229290b5f --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/dac_sync.rst @@ -0,0 +1,41 @@ +====================== +DAC Synchronous driver +====================== + +A DAC (Digital-to-Analog Converter) converts digital value to an analog voltage. +The digital value from 0 to the highest represent the output voltage value. +The digital highest value possible with the bit resolution supported by the +DAC. For example a 10 bit resolution DAC hardware, the highest value is 1024. +The highest output voltage possible with the reference voltage. + +The driver can convert a serials digital value. The pre-defined data should +be an data array. Application can invoke dac_sync_write to start the conversation. + +Features +-------- +* Initialization and de-initialization +* Enabling and disabling +* Support for DACs with channels +* Writing buffers with multiple samples to DAC + +Applications +------------ +* Generate audio signals by connecting the DAC output to a speaker +* Generate a reference voltage + +Dependencies +------------ +* DAC hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/atmel-samd/asf4/samd51/hal/documentation/evsys.rst b/atmel-samd/asf4/samd51/hal/documentation/evsys.rst new file mode 100644 index 0000000000000..01d40bc566558 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/evsys.rst @@ -0,0 +1,24 @@ +=================== +Event system driver +=================== + +Event system allows autonomous, low-latency and configurable communication between peripherals. + +Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition +to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that +respond to events are event users, peripherals that generate events are called event generators. A peripheral can have +one or more event generators and can have one or more event users. + +Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This +reduces the load on the CPU and system resources, compared to a traditional interrupt-based system. + +The Event System consists of several channels which route the internal events from generators +to users. Each event generator can be selected as source for multiple channels, but a channel cannot +be set to use multiple event generators at the same time. + +Event system driver allows to configure event system of an MCU. + +Limitations +----------- + + - Event channel configuration is static diff --git a/atmel-samd/asf4/samd51/hal/documentation/i2c_master_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/i2c_master_sync.rst new file mode 100644 index 0000000000000..77b4f6e9c4f29 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/i2c_master_sync.rst @@ -0,0 +1,87 @@ +============================= +I2C Master synchronous driver +============================= + +I2C (Inter-Integrated Circuit) is a two wire serial interface usually used +for on-board low-speed bi-directional communication between controllers and +peripherals. The master device is responsible for initiating and controlling +all transfers on the I2C bus. Only one master device can be active on the I2C +bus at the time, but the master role can be transferred between devices on the +same I2C bus. I2C uses only two bidirectional open-drain lines, usually +designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up +resistors. + +The stop condition is automatically controlled by the driver if the I/O write and +read functions are used, but can be manually controlled by using the +i2c_m_sync_transfer function. + +Often a master accesses different information in the slave by accessing +different registers in the slave. This is done by first sending a message to +the target slave containing the register address, followed by a repeated start +condition (no stop condition between) ending with transferring register data. +This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read +function, but limited to 8-bit register addresses. + +I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in +Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to +stick within the SCL clock frequency range supported by the selected mode. +The requested SCL clock frequency is not validated by the +i2c_m_sync_set_baudrate function against the selected I2C mode. + +Features +-------- + + * I2C Master support + * Initialization and de-initialization + * Enabling and disabling + * Run-time bus speed configuration + * Write and read I2C messages + * Slave register access functions (limited to 8-bit address) + * Manual or automatic stop condition generation + * 10- and 7- bit addressing + * I2C Modes supported + +----------------------+-------------------+ + |* Standard/Fast mode | (SCL: 1 - 400kHz) | + +----------------------+-------------------+ + |* Fastmode+ | (SCL: 1 - 1000kHz)| + +----------------------+-------------------+ + |* Highspeed mode | (SCL: 1 - 3400kHz)| + +----------------------+-------------------+ + +Applications +------------ + +* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals +* Data communication between micro controllers +* Controlling displays + +Dependencies +------------ + +* I2C Master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +General +^^^^^^^ + + * System Managmenet Bus (SMBus) not supported. + * Power Management Bus (PMBus) not supported. + +Clock considerations +^^^^^^^^^^^^^^^^^^^^ + +The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. + +Known issues and workarounds +---------------------------- + +N/A + + diff --git a/atmel-samd/asf4/samd51/hal/documentation/pwm.rst b/atmel-samd/asf4/samd51/hal/documentation/pwm.rst new file mode 100644 index 0000000000000..71785c634c13d --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/pwm.rst @@ -0,0 +1,53 @@ +The PWM Driver(bare-bone) +========================= + +Pulse-width modulation (PWM) is used to create an analog behavior +digitally by controlling the amount of power transferred to the +connected peripheral. This is achieved by controlling the high period +(duty-cycle) of a periodic signal. + +User can change the period or duty cycle whenever PWM is running. The +function pwm_set_parameters is used to configure these two parameters. +Note these are raw register values and the parameter duty_cycle means +the period of first half during one cycle, which should be not beyond +total period value. + +In addition, user can also get multi PWM channels output from different +peripherals at the same time, which is implemented more flexible by the +function pointers. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Run-time control of PWM duty-cycle and period +* Notifications about errors and one PWM cycle is done + +Applications +------------ + +Motor control, ballast, LED, H-bridge, power converters, and +other types of power control applications. + +Dependencies +------------ + +The peripheral which can perform waveform generation like frequency +generation and pulse-width modulation, such as Timer/Counter. + +Concurrency +----------- + +N/A + +Limitations +----------- + +The current driver doesn't support the features like recoverable, +non-recoverable faults, dithering, dead-time insertion. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/atmel-samd/asf4/samd51/hal/documentation/rand_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/rand_sync.rst new file mode 100644 index 0000000000000..19ec1d367cd6a --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/rand_sync.rst @@ -0,0 +1,43 @@ +========================================== +Random Number Generator Synchronous driver +========================================== + +Random Number Generator (RAND) generates a sequence of numbers that can not +be reasonably predicted better than by a random chance. + +In some implementation cases, seed is required for the Random Number Generator +to generate random numbers. rand_sync_set_seed is used to update the seed. +If it's actually not required by the generator implementation, the function just +returns ERR_UNSUPPORTED_OP. + +Features +-------- + +* Initialization and de-initialization +* Enabling and Disabling +* Setting seed +* 8-bit and 32-bit random data/data array generation + +Applications +------------ + +* Generate random keys for data encryption + +Dependencies +------------ + +* Random number generation hardware/software + +Concurrency +----------- +N/A + +Limitations +----------- + +N/A + +Known issues and workarounds +---------------------------- +N/A + diff --git a/atmel-samd/asf4/samd51/hal/documentation/spi_master_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/spi_master_sync.rst new file mode 100644 index 0000000000000..4fbe45e29c3db --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/spi_master_sync.rst @@ -0,0 +1,51 @@ +The SPI Master Synchronous Driver +================================= + +The serial peripheral interface (SPI) is a synchronous serial communication +interface. + +SPI devices communicate in full duplex mode using a master-slave +architecture with a single master. The master device originates the frame for +reading and writing. Multiple slave devices are supported through selection +with individual slave select (SS) lines. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * SPI mode + * Character size + * Data order +* Data transfer: transmission, reception and full-duplex + +Applications +------------ + +Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, +LCD controller, etc. + +Dependencies +------------ + +SPI master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +The slave select (SS) is not automatically inserted during read/write/transfer, +user must use I/O to control the devices' SS. + +Known issues and workarounds +---------------------------- + +N/A + diff --git a/atmel-samd/asf4/samd51/hal/documentation/timer.rst b/atmel-samd/asf4/samd51/hal/documentation/timer.rst new file mode 100644 index 0000000000000..c5ca63d127957 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/timer.rst @@ -0,0 +1,52 @@ +============================ +The Timer driver (bare-bone) +============================ + +The Timer driver provides means for delayed and periodical function invocation. + +A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has +been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a +configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically +changes execution delays and periods for all tasks in the timers task queue. + +A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue +and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on +the period set in the task configuration. +In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to +reuse the memory of expired task in the callback. + +Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. + +Features +-------- +* Initialization and de-initialization +* Starting and stopping +* Timer tasks - periodical invocation of functions +* Changing and obtaining of the period of a timer + +Applications +------------ +* Delayed and periodical function execution for middle-ware stacks and applications. + +Dependencies +------------ +* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. + +Concurrency +----------- +The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during +the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed +until the task adding or removing is complete. + +The task queue is not protected from the access by interrupts not used by the driver. Due to this +it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes +the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. + +Limitations +----------- +* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. +* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. + +Knows issues and workarounds +---------------------------- +Not applicable diff --git a/atmel-samd/asf4/samd51/hal/documentation/usart_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/usart_sync.rst new file mode 100644 index 0000000000000..73f76b749d1d9 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/usart_sync.rst @@ -0,0 +1,58 @@ +The USART Synchronous Driver +============================ + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. +And the SCK pin can't be set directly. Application can use a GCLK output PIN +to generate SCK. For example to communicate with a SMARTCARD with ISO7816 +(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be +config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/atmel-samd/asf4/samd51/hal/documentation/usb_device_async.rst b/atmel-samd/asf4/samd51/hal/documentation/usb_device_async.rst new file mode 100644 index 0000000000000..647eec071bebe --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/documentation/usb_device_async.rst @@ -0,0 +1,195 @@ +The USB Device Asynchronous Driver +================================== + +Universal Serial Bus (USB) is an industry standard that defines the cables, +connectors and communication protocols used in a bus for connection, +communication, and power supply between computers and electronic devices. + +The USB device driver provides necessary APIs to support USB Device states and +USB data flow. So that the USB Device enumeration, class and vendor support can +be implemented base on it. The driver is asynchronous, which means that all USB +data processing is done in callbacks.. + +To be recognized by a host, a USB device must handle a subset of the USB events. +The USB device should build up control communication to report its descriptors +to the host and accept host's requests. An application or upper stack that uses +the USB device driver should have its descriptors prepared, catch the callbacks, +monitor the control requests and handle them correctly. +Usually, a USB device application that can be enumerated may use the following +sequence: + +* Initialize +* Register callback and handle Reset event, where: + + * Initialize endpoint 0 + * Register callbacks for endpoint 0, where some of the standard requests + defined in Chapter 9, USB specification + (see `USB 2.0 Documents `_) + are handled + + * Setup request handling callback + + * On *GetDeviceDescriptor* request, sends device descriptor + * On *GetConfigurationDescriptor* request, sends configuration descriptors + * On *SetAddress* request sends no data, just goes to status phase + * On *SetConfigure* request initialize and enable other endpoints, sends + no data, just goes to status phase + * Transfer done handling callback + + * On *SetAddress* request apply the new address + * On *SetConfigure* request a global variable can be set to indicates + that the host driver is loaded and device is ready to work + * Enable endpoint 0 +* Enable +* Attach device + +To support USB transfer on endpoints, endpoints information is stored +by the driver internally, including control request data, endpoint status, +callbacks and transfer data pointers. The number of endpoints that the driver +can support is defined through configuration. To optimize RAM usage, the +number of endpoints the driver needs to support should be minimized. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* USB device attachment/detachment +* USB device address control +* USB working speed status +* USB device frame number and micro frame number status +* Sending remote wakeup to host +* Callback management for following USB events: + + * Start of Frame (SOF) + * Other USB events: + + * VBus change + * Reset + * Wakeup + * Linked Power Management (LPM) Suspend + * Suspend + * Error +* Endpoints management: + + * Endpoint initialization/de-initialization + * Endpoint enabling/disabling + * Control endpoint setup request packet + * Data transfer and abort + * Endpoint halt state control + * Endpoint status, including: + + * Endpoint address + * Last transfer result status code + * Last error status code + * Current transfer state + * Transfer size and done count + * Endpoint callback management for endpoint and its transfer events: + + * In case a setup request received on control endpoint + * In case transfer finished with/without error + +Applications +------------ + +USB Device stack, to monitor USB events, handle control requests and process +data. + +Dependencies +------------ + +* USB device capable hardware +* 48MHz clock for low-speed and full-speed and 480MHz clock for high-speed + +Concurrency +----------- + +N/A + +Limitations +----------- + +* When a buffer is used by a USB endpoint to transfer data, it must be kept + unchanged while the transfer is in progress. +* After receiving a request that has no data expected, the transfer function + must be called with data length zero to complete control status phase. + +Known issues and workarounds +---------------------------- + +N/A + +Considerations for D21 USB +-------------------------- + +Clocks +^^^^^^ + +DFLL must be used to generate 48MHz clock for USB device with either of the +following mode: + +* USB Clock Recovery Mode + + * Set "DFLL Enable", "Bypass Coarse Lock", "Chill Cycle Disable", + "USB Clock Recovery Mode", "Stable DFLL Frequency" + * Clear "Wait Lock" + * Leave "Operating Mode Selection" to "Closed Loop Mode" + +* Closed Loop Mode + + * Set "DFLL Enable" + * Clear "USB Clock Recovery Mode", "Stable DFLL Frequency" + * Select "Closed Loop Mode" of "Operating Mode Selection" + * Set "DFLL Multiply Factor" to 1464 or 1465 (48000000/32768) + * Select "Reference Clock Source" to use 32768Hz source, e.g., use GCLK1 and + for GCLK1 settings: + + * Set "Generic Clock Generator Enable" + * Select "XOSC32K" of "Generic clock generator 1 source", and for XOSC32K + settings: + + * Set "External 32K Oscillator Enable", "Enable 32KHz Output", + "Enable XTAL" + * Set a right value for "Startup time for the 32K Oscillator", e.g., + 1125092 us + +Endpoints +^^^^^^^^^ + +Each USB device endpoint number supports two endpoint addresses, corresponding +to IN and OUT endpoint. E.g., for endpoint 1, the endpoint IN has address 0x81 +and endpoint OUT has address 0x01. Thus, the possible supported endpoint +addresses are almost two times of max endpoint number (endpoint 0 must be used +as control endpoint instead of dedicated IN and OUT endpoints). + +Buffering and RAM usage optimization +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +When transferring data through USB device endpoints, buffer pointers can be +used to let endpoint get access to the buffer, but there are some limits: + +* For control endpoint there must always be a buffer available to put received + setup packet. +* For IN endpoint (transmit to host) the data must in RAM. +* For OUT endpoint (receive from host) the data pointer must be aligned, and + the data size must be aligned by max endpoint size and not zero. + +The driver has option for each endpoint to allocate internal static buffer as +cache to buffer input/output data, to remove upper limits. The configuration +affects the parameter check of transfer functions, and the RAM usage. + +* For control endpoints, cache buffer must be enabled to fill setup packet. + In addition, to support unaligned OUT packet and IN packet inside flash, the + buffer size must be equal to or larger than max endpoint size. +* For OUT endpoints, if the cache is allocated, it's possible to pass unaligned + buffer address and buffer size to transfer function. Else the transfer + function only accepts aligned buffer with it's size multiple of endpoint + packet size. +* For IN endpoints, if the cache is allocated, it's possible to pass buffer + pointer to internal flash or other memory part other than RAM to the transfer + function. + +To optimize the RAM usage, the configuration of max endpoint number, max number +of endpoints supported and the buffer usage of used input and/or output +endpoints can be adjusted. + diff --git a/atmel-samd/asf4/samd51/hal/include/hal_adc_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_adc_sync.h new file mode 100644 index 0000000000000..fb4604aa578b8 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_adc_sync.h @@ -0,0 +1,287 @@ +/** + * \file + * + * \brief ADC functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ADC_SYNC_H_INCLUDED +#define _HAL_ADC_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_adc_sync + * + * @{ + */ + +/** + * \brief ADC descriptor + * + * The ADC descriptor forward declaration. + */ +struct adc_sync_descriptor; + +/** + * \brief ADC descriptor + */ +struct adc_sync_descriptor { + /** ADC device */ + struct _adc_sync_device device; +}; + +/** + * \brief Initialize ADC + * + * This function initializes the given ADC descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr An ADC descriptor to initialize + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to a set of functions pointers + * + * \return Initialization status. + */ +int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize ADC + * + * This function deinitializes the given ADC descriptor. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr An ADC descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr); + +/** + * \brief Enable ADC + * + * Use this function to set the ADC peripheral to enabled state. + * + * \param[in] descr Pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return Operation status + * + */ +int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Disable ADC + * + * Use this function to set the ADC peripheral to disabled state. + * + * \param[in] descr Pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return Operation status + * + */ +int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Read data from ADC + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, + const uint16_t length); + +/** + * \brief Set ADC reference source + * + * This function sets ADC reference source. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] reference A reference source to set + * + * \return Status of the ADC reference source setting. + */ +int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference); + +/** + * \brief Set ADC resolution + * + * This function sets ADC resolution. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] resolution A resolution to set + * + * \return Status of the ADC resolution setting. + */ +int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * This function sets ADC positive and negative input sources. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + * + * \return Status of the ADC channels setting. + */ +int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set ADC conversion mode + * + * This function sets ADC conversion mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] mode A conversion mode to set + * + * \return Status of the ADC conversion mode setting. + */ +int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode); + +/** + * \brief Set ADC differential mode + * + * This function sets ADC differential mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + * + * \return Status of the ADC differential mode setting. + */ +int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set ADC channel gain + * + * This function sets ADC channel gain. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * \param[in] gain A gain to set + * + * \return Status of the ADC gain setting. + */ +int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, + const adc_gain_t gain); + +/** + * \brief Set ADC window mode + * + * This function sets ADC window mode. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] mode A window mode to set + * + * \return Status of the ADC window mode setting. + */ +int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode); + +/** + * \brief Set ADC thresholds + * + * This function sets ADC positive and negative thresholds. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] low_threshold A lower thresholds to set + * \param[in] up_threshold An upper thresholds to set + * + * \return Status of the ADC thresholds setting. + */ +int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * This function retrieves ADC threshold state. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[out] state The threshold state + * + * \return The state of ADC thresholds state retrieving. + */ +int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, + adc_threshold_status_t *const state); + +/** + * \brief Check if conversion is complete + * + * This function checks if the ADC has finished the conversion. + * + * \param[in] descr The pointer to the ADC descriptor + * \param[in] channel Channel number + * + * \return The status of ADC conversion completion checking. + * \retval 1 The conversion is complete + * \retval 0 The conversion is not complete + */ +int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t adc_sync_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#include + +#endif /* _HAL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_atomic.h b/atmel-samd/asf4/samd51/hal/include/hal_atomic.h new file mode 100644 index 0000000000000..8a51b2a968f81 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_atomic.h @@ -0,0 +1,137 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Some critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_dac_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_dac_sync.h new file mode 100644 index 0000000000000..79c68b2cb09ac --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_dac_sync.h @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief DAC functionality declaration. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_SYNC_DAC_H_INCLUDED +#define HAL_SYNC_DAC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_dac_sync + * + *@{ + */ + +/** + * \brief DAC synchronous descriptor. + * + * The DAC descriptor forward declaration. + */ +struct dac_sync_descriptor; + +/** + * \brief DAC synchronous channel descriptor. + * + */ +struct dac_sync_channel { + /** Pointer to buffer what to be converted */ + uint16_t *buffer; + /** The length of buffer */ + uint32_t length; +}; + +/** + * \brief DAC synchronous descriptor + */ +struct dac_sync_descriptor { + /** DAC device */ + struct _dac_sync_device device; + /** DAC selected channel */ + struct dac_sync_channel sel_ch[CHANNEL_NUM]; +}; + +/** \brief Initialize the DAC HAL instance and hardware. + * \param[out] descr A DAC descriptor to initialize + * \param[in] hw The pointer to hardware instance + * \return Operation status. + */ +int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw); + +/** \brief Deinitialize the DAC HAL instance and hardware. + * \param[in] descr Pointer to the HAL DAC descriptor + * \return Operation status. + */ +int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr); + +/** \brief Enable DAC channel. + * \param[in] descr Pointer to the HAL DAC descriptor + * \param[in] ch Channel number + * \return Operation status. + */ +int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); + +/** \brief Disable DAC channel. + * \param[in] descr Pointer to the HAL DAC descriptor + * \param[in] ch Channel number + * \return Operation status. + */ +int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); + +/** \brief DAC converts digital data to analog output. + * \param[in] descr Pointer to the HAL DAC descriptor + * \param[in] ch the Channel selected to output + * \param[in] buffer Pointer to digital data or buffer + * \param[in] length The number of elements in the buffer + * \return Operation status. + */ +int32_t dac_sync_write(struct dac_sync_descriptor *const descr, const uint8_t ch, uint16_t *buffer, uint32_t length); + +/** \brief Get DAC driver version + * + * \return Current driver version. + */ +uint32_t dac_sync_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_delay.h b/atmel-samd/asf4/samd51/hal/include/hal_delay.h new file mode 100644 index 0000000000000..48fee826f3373 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_delay.h @@ -0,0 +1,99 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_evsys.h b/atmel-samd/asf4/samd51/hal/include/hal_evsys.h new file mode 100644 index 0000000000000..f24fa4c669ba6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_evsys.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief HAL event system related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include + +#ifndef _HAL_EVSYS_H_INCLUDED +#define _HAL_EVSYS_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_evsys + * + * @{ + */ + +/** + * \brief Initialize event system. + * + * \return Initialization status. + */ +int32_t event_system_init(void); + +/** + * \brief Deinitialize event system. + * + * \return De-initialization status. + */ +int32_t event_system_deinit(void); + +/** + * \brief Enable event reception by the given user from the given channel + * + * \param[in] user A user to enable + * \param[in] channel A channel the user is assigned to + * + * \return Status of operation. + */ +int32_t event_system_enable_user(const uint16_t user, const uint16_t channel); + +/** + * \brief Disable event reception by the given user from the given channel + * + * \param[in] user A user to disable + * \param[in] channel A channel the user is assigned to + * + * \return Status of operation. + */ +int32_t event_system_disable_user(const uint16_t user, const uint16_t channel); + +/** + * \brief Enable event generation by the given generator for the given channel + * + * \param[in] generator A generator to disable + * \param[in] channel A channel the generator is assigned to + * + * \return Status of operation. + */ +int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel); + +/** + * \brief Disable event generation by the given generator for the given channel + * + * \param[in] generator A generator to disable + * \param[in] channel A channel the generator is assigned to + * + * \return Status of operation. + */ +int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t event_system_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_EVSYS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_gpio.h b/atmel-samd/asf4/samd51/hal/include/hal_gpio.h new file mode 100644 index 0000000000000..f0e8af8d777fc --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_gpio.h @@ -0,0 +1,212 @@ +/** + * \file + * + * \brief Port + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin high with internal + * resistor + * GPIO_PULL_UP = Pull pin low with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hal_i2c_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_i2c_m_sync.h new file mode 100644 index 0000000000000..65741831a7c49 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_i2c_m_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_I2C_M_SYNC_H_INCLUDED +#define _HAL_I2C_M_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_i2c_master_sync + * + * @{ + */ + +#define I2C_M_MAX_RETRY 1 + +/** + * \brief I2C descriptor structure, embed i2c_device & i2c_interface + */ +struct i2c_m_sync_desc { + struct _i2c_m_sync_device device; + struct io_descriptor io; + uint16_t slave_addr; +}; + +/** + * \brief Initialize synchronous I2C interface + * + * This function initializes the given I/O descriptor to be used as a + * synchronous I2C interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + * \retval -1 The passed parameters were invalid or the interface is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); + +/** + * \brief Deinitialize I2C interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Uninitialization status. + * \retval -1 The passed parameters were invalid or the interface is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); + +/** + * \brief Set the slave device address + * + * This function sets the next transfer target slave I2C device address. + * It takes no effect to any already started access. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] addr The slave address to access + * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN + * + * \return Masked slave address. The mask is a maximum 10-bit address, and 10th + * bit is set if a 10-bit address is used + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); + +/** + * \brief Set baudrate + * + * This function sets the I2C device to the specified baudrate. + * It only takes effect when the hardware is disabled. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] clkrate Unused parameter. Should always be 0 + * \param[in] baudrate The baudrate value set to master + * + * \return Whether successfully set the baudrate + * \retval -1 The passed parameters were invalid or the device is already enabled + * \retval 0 The baudrate set is completed successfully + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Sync version of enable hardware + * + * This function enables the I2C device, and then waits for this enabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully enable the device + * \retval -1 The passed parameters were invalid or the device enable failed + * \retval 0 The hardware enabling is completed successfully + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of disable hardware + * + * This function disables the I2C device and then waits for this disabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully disable the device + * \retval -1 The passed parameters were invalid or the device disable failed + * \retval 0 The hardware disabling is completed successfully + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of write command to I2C slave + * + * This function will write the value to a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer holding data to write to the I2C slave device + * \param[in] length The length (in bytes) to write to the I2C slave device + * + * \return Whether successfully write to the device + * \retval <0 The passed parameters were invalid or write fail + * \retval 0 Writing to register is completed successfully + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of read register value from I2C slave + * + * This function will read a byte value from a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer to hold the read data from the I2C slave device + * \param[in] length The length (in bytes) to read from the I2C slave device + * + * \return Whether successfully read from the device + * \retval <0 The passed parameters were invalid or read fail + * \retval 0 Reading from register is completed successfully + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of transfer message to/from the I2C slave + * + * This function will transfer a message between the I2C slave and the master. This function will wait for the operation + * to be done. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] msg An i2c_m_msg struct + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); + +/** + * \brief Sync version of send stop condition on the i2c bus + * + * This function will create a stop condition on the i2c bus to release the bus + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); + +/** + * \brief Return I/O descriptor for this I2C instance + * + * This function will return a I/O instance for this I2C driver instance + * + * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C + * \param[in] io_descriptor A pointer to an I/O descriptor pointer type + * + * \return Error code + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t i2c_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hal_init.h b/atmel-samd/asf4/samd51/hal/include/hal_init.h new file mode 100644 index 0000000000000..a970943eb27a7 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_init.h @@ -0,0 +1,82 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_io.h b/atmel-samd/asf4/samd51/hal/include/hal_io.h new file mode 100644 index 0000000000000..e8005e3db3e18 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_io.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_pwm.h b/atmel-samd/asf4/samd51/hal/include/hal_pwm.h new file mode 100644 index 0000000000000..29efc4bc40308 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_pwm.h @@ -0,0 +1,161 @@ +/** + * \file + * + * \brief PWM functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef HAL_PWM_H_INCLUDED +#define HAL_PWM_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_pwm_async + * + *@{ + */ + +/** + * \brief PWM descriptor + * + * The PWM descriptor forward declaration. + */ +struct pwm_descriptor; + +/** + * \brief PWM callback type + */ +typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr); + +/** + * \brief PWM callback types + */ +enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB }; + +/** + * \brief PWM callbacks + */ +struct pwm_callbacks { + pwm_cb_t period; + pwm_cb_t error; +}; + +/** \brief PWM descriptor + */ +struct pwm_descriptor { + /** PWM device */ + struct _pwm_device device; + /** PWM callback structure */ + struct pwm_callbacks pwm_cb; +}; + +/** \brief Initialize the PWM HAL instance and hardware + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to a set of functions pointers + * + * \return Operation status. + */ +int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func); + +/** \brief Deinitialize the PWM HAL instance and hardware + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_deinit(struct pwm_descriptor *const descr); + +/** \brief PWM output start + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_enable(struct pwm_descriptor *const descr); + +/** \brief PWM output stop + * + * \param[in] descr Pointer to the HAL PWM descriptor + * + * \return Operation status. + */ +int32_t pwm_disable(struct pwm_descriptor *const descr); + +/** \brief Register PWM callback + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] type Callback type + * \param[in] cb A callback function, passing NULL de-registers callback + * + * \return Operation status. + * \retval 0 Success + * \retval -1 Error + */ +int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb); + +/** \brief Change PWM parameter + * + * \param[in] descr Pointer to the HAL PWM descriptor + * \param[in] period Total period of one PWM cycle + * \param[in] duty_cycle Period of PWM first half during one cycle + * + * \return Operation status. + */ +int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, + const pwm_period_t duty_cycle); + +/** \brief Get PWM driver version + * + * \return Current driver version. + */ +uint32_t pwm_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_PWM;_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_rand_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_rand_sync.h new file mode 100644 index 0000000000000..481f48ca1b4f2 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_rand_sync.h @@ -0,0 +1,144 @@ +/** + * \file + * + * \brief Generic Random Number Generator (RAND) functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_RAND_SYNC_H_INCLUDED +#define _HAL_RAND_SYNC_H_INCLUDED + +#include + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_rand_sync + * + *@{ + */ + +/** Random Number Generator polling device. */ +struct rand_sync_desc { + struct _rand_sync_dev dev; +}; + +/** + * \brief Initialize the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + * \param[in, out] hw Pointer to the hardware for device instance + * \return Initialization operation result status, ERR_NONE (0) for OK. + */ +int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw); + +/** + * \brief Deinitialize the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + */ +void rand_sync_deinit(struct rand_sync_desc *const desc); + +/** + * \brief Enable the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + * \return Enable operation result status, ERR_NONE (0) for OK. + */ +int32_t rand_sync_enable(struct rand_sync_desc *const desc); + +/** + * \brief Disable the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + */ +void rand_sync_disable(struct rand_sync_desc *const desc); + +/** + * \brief Set seed for the Random Number Generator Driver + * \param[out] desc Pointer to the device descriptor instance struct + */ +int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed); + +/** + * \brief Read the 8-bit Random Number + * \param[in] desc Pointer to the device descriptor instance struct + * \return The random number generated + */ +uint8_t rand_sync_read8(const struct rand_sync_desc *const desc); + +/** + * \brief Read the 32-bit Random Number + * \param[in] desc Pointer to the device descriptor instance struct + * \return The random number generated + */ +uint32_t rand_sync_read32(const struct rand_sync_desc *const desc); + +/** + * \brief Read the 8-bit Random Number Sequence into a buffer + * \param[in] desc Pointer to the device descriptor instance struct + * \param[out] buf Pointer to the buffer to fill an array of generated numbers + * \param[in] len Number of random numbers to read + */ +void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len); + +/** + * \brief Read the 32-bit Random Number Sequence into a buffer + * \param[in] desc Pointer to the device descriptor instance struct + * \param[out] buf Pointer to the buffer to fill an array of generated numbers + * \param[in] len Number of random numbers to read + */ +void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t rand_sync_get_version(void); + +/* I/O read will be used to get random data. */ + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_RAND_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_sleep.h b/atmel-samd/asf4/samd51/hal/include/hal_sleep.h new file mode 100644 index 0000000000000..0a11856b1ea49 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_sleep.h @@ -0,0 +1,84 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_spi_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_spi_m_sync.h new file mode 100644 index 0000000000000..2c630ff09a2ce --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_spi_m_sync.h @@ -0,0 +1,220 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SPI_M_SYNC_H_INCLUDED +#define _HAL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup doc_driver_hal_spi_master_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** \brief SPI HAL driver struct for polling mode + * + */ +struct spi_m_sync_descriptor { + /** SPI device instance */ + struct _spi_sync_dev dev; + /** I/O read/write */ + struct io_descriptor io; + /** Flags for HAL driver */ + uint16_t flags; +}; + +/** \brief Initialize SPI HAL instance and hardware for polling mode + * + * Initialize SPI HAL with polling mode. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] hw Pointer to the hardware base. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_INVALID_DATA Error, initialized. + */ +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); + +/** \brief Deinitialize the SPI HAL instance and hardware + * + * Abort transfer, disable and reset SPI, deinit software. + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); + +/** \brief Enable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); + +/** \brief Disable SPI + * + * \param[in] spi Pointer to the HAL SPI instance. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval <0 Error code. + */ +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); + +/** \brief Set SPI baudrate + * + * Works if SPI is initialized as master, it sets the baudrate. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] baud_val The target baudrate value + * (see "baudrate calculation" for calculating the value). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The baudrate is not supported. + */ +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); + +/** \brief Set SPI mode + * + * Set the SPI transfer mode (\ref spi_transfer_mode), + * which controls the clock polarity and clock phase: + * - Mode 0: leading edge is rising edge, data sample on leading edge. + * - Mode 1: leading edge is rising edge, data sample on trailing edge. + * - Mode 2: leading edge is falling edge, data sample on leading edge. + * - Mode 3: leading edge is falling edge, data sample on trailing edge. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] mode The mode (0~3). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The mode is not supported. + */ +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); + +/** \brief Set SPI transfer character size in number of bits + * + * The character size (\ref spi_char_size) influence the way the data is + * sent/received. + * For char size <= 8-bit, data is stored byte by byte. + * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. + * Note that the default and recommended char size is 8-bit since it's + * supported by all system. + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] char_size The char size (~16, recommended 8). + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The char size is not supported. + */ +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); + +/** \brief Set SPI transfer data order + * + * \param[in] spi Pointer to the HAL SPI instance. + * \param[in] dord The data order: send LSB/MSB first. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy + * \retval ERR_INVALID_ARG The data order is not supported. + */ +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); + +/** \brief Perform the SPI data transfer (TX and RX) in polling way + * + * Activate CS, do TX and RX and deactivate CS. It blocks. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). + * + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + * \retval ERR_BUSY SPI is busy + */ +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); + +/** + * \brief Return the I/O descriptor for this SPI instance + * + * This function will return an I/O instance for this SPI driver instance. + * + * \param[in] spi An SPI master descriptor, which is used to communicate through + * SPI + * \param[in, out] io A pointer to an I/O descriptor pointer type + * + * \retval ERR_NONE + */ +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t spi_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_timer.h b/atmel-samd/asf4/samd51/hal/include/hal_timer.h new file mode 100644 index 0000000000000..b5c8f60821a3d --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_timer.h @@ -0,0 +1,216 @@ +/** + * \file + * + * \brief Timer task functionality declaration. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_TIMER_H_INCLUDED +#define _HAL_TIMER_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_timer + * + * @{ + */ + +/** + * \brief Timer mode type + */ +enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; + +/** + * \brief Timer task descriptor + * + * The timer task descriptor forward declaration. + */ +struct timer_task; + +/** + * \brief Timer task callback function type + */ +typedef void (*timer_cb_t)(const struct timer_task *const timer_task); + +/** + * \brief Timer task structure + */ +struct timer_task { + struct list_element elem; /*! List element. */ + uint32_t time_label; /*! Absolute timer start time. */ + + uint32_t interval; /*! Number of timer ticks before calling the task. */ + timer_cb_t cb; /*! Function pointer to the task. */ + enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ +}; + +/** + * \brief Timer structure + */ +struct timer_descriptor { + struct _timer_device device; + uint32_t time; + struct list_descriptor tasks; /*! Timer tasks list. */ + volatile uint8_t flags; +}; + +/** + * \brief Initialize timer + * + * This function initializes the given timer. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A timer descriptor to initialize + * \param[in] hw The pointer to the hardware instance + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); + +/** + * \brief Deinitialize timer + * + * This function deinitializes the given timer. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr A timer descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t timer_deinit(struct timer_descriptor *const descr); + +/** + * \brief Start timer + * + * This function starts the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to start + * + * \return Timer starting status. + */ +int32_t timer_start(struct timer_descriptor *const descr); + +/** + * \brief Stop timer + * + * This function stops the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * + * \return Timer stopping status. + */ +int32_t timer_stop(struct timer_descriptor *const descr); + +/** + * \brief Set amount of clock cycles per timer tick + * + * This function sets the amount of clock cycles per timer tick for the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * \param[in] clock_cycles The amount of clock cycles per tick to set + * + * \return Setting clock cycles amount status. + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); + +/** + * \brief Retrieve the amount of clock cycles in a tick + * + * This function retrieves how many clock cycles there are in a single timer tick. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to convert ticks to + * clock cycles + * \param[out] cycles The amount of clock cycles + * + * \return The status of clock cycles retrieving. + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); + +/** + * \brief Add timer task + * + * This function adds the given timer task to the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to add task to + * \param[in] task A task to add + * + * \return Timer's task adding status. + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); + +/** + * \brief Remove timer task + * + * This function removes the given timer task from the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to remove task from + * \param[in] task A task to remove + * + * \return Timer's task removing status. + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t timer_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_usart_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_usart_sync.h new file mode 100644 index 0000000000000..e2aef748d3e6a --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_usart_sync.h @@ -0,0 +1,257 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SYNC_USART_H_INCLUDED +#define _HAL_SYNC_USART_H_INCLUDED + +#include "hal_io.h" +#include + +/** + * \addtogroup doc_driver_hal_usart_sync + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Synchronous USART descriptor + */ +struct usart_sync_descriptor { + struct io_descriptor io; + struct _usart_sync_device device; +}; + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used + * as USART interface descriptor. + * It checks if the given hardware is not initialized and + * if the given hardware is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via USART + * \param[in] hw The pointer to hardware instance + * \param[in] func The pointer to as set of functions pointers + * + * \return Initialization status. + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and + * if the given hardware is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of the I/O descriptor retrieving. + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Specify action for flow control pins + * + * This function sets the action (or state) for the flow control pins + * if the flow control is enabled. + * It sets the state of flow control pins only if the automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins + * if the flow control is enabled. + * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_sync_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_usb_device.h b/atmel-samd/asf4/samd51/hal/include/hal_usb_device.h new file mode 100644 index 0000000000000..8b7bd5ec79159 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hal_usb_device.h @@ -0,0 +1,305 @@ +/** + * \file + * + * \brief SAM USB device HAL + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_USB_DEVICE_H_INCLUDED +#define _HAL_USB_DEVICE_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_usb_device + * + * @{ + */ + +/** USB device endpoint status structure. */ +struct usb_d_ep_status { + /** Endpoint address, including direction. */ + uint8_t ep; + /** Endpoint transfer status code that triggers the callback. + * \ref usb_xfer_code. */ + uint8_t code; + /** Endpoint error, if \c code is \ref USB_TRANS_ERROR. */ + uint8_t error; + /** Transfer state, \ref usb_ep_state. */ + uint8_t state; + /** Transfer count. */ + uint32_t count; + /** Transfer size. */ + uint32_t size; +}; + +/** Prototype function for callback that is invoked on USB device SOF. */ +typedef void (*usb_d_sof_cb_t)(void); + +/** Prototype function for callback that is invoked on USB device events. */ +typedef void (*usb_d_event_cb_t)(const enum usb_event event, const uint32_t param); + +/** USB device callbacks. */ +struct usb_d_callbacks { + /** Callback that is invoked on SOF. */ + usb_d_sof_cb_t sof; + /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ + usb_d_event_cb_t event; +}; + +/** Callback that is invoked when setup packet is received. + * Return \c true if request has been handled, or control endpoint will + * stall IN/OUT transactions. + */ +typedef bool (*usb_d_ep_cb_setup_t)(const uint8_t ep, const uint8_t *req); + +/** Callback that is invoked when buffer is done without error, but last packet + * is full size packet without ZLP. + * Return \c true if more data has been requested. + */ +typedef bool (*usb_d_ep_cb_more_t)(const uint8_t ep, const uint32_t count); + +/** Callback that is invoked when all data is finished, including background + * transfer, or error happens. + * In control transfer data stage, return value is checked, + * return \c false if no error happens. + */ +typedef bool (*usb_d_ep_cb_xfer_t)(const uint8_t ep, const enum usb_xfer_code code, void *param); + +/** + * \brief Initialize the USB device driver + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_init(void); + +/** + * \brief Deinitialize the USB device driver + */ +void usb_d_deinit(void); + +/** + * \brief Register the USB device callback + * \param[in] type The callback type to register. + * \param[in] func The callback function, NULL to disable callback. + */ +void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); + +/** + * \brief Enable the USB device driver + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_enable(void); + +/** + * \brief Disable the USB device driver + */ +void usb_d_disable(void); + +/** + * \brief Attach the USB device + */ +void usb_d_attach(void); + +/** + * \brief Detach the USB device + */ +void usb_d_detach(void); + +/** + * \brief Retrieve current USB working speed. + * \return USB Speed. See \ref usb_speed. + */ +enum usb_speed usb_d_get_speed(void); + +/** + * \brief Retrieve current USB frame number. + * \return Frame number. + */ +uint16_t usb_d_get_frame_num(void); + +/** + * \brief Retrieve current USB micro frame number. + * \return Micro frame number inside a frame (0~7). + * 0 if not available (not HS). + */ +uint8_t usb_d_get_uframe_num(void); + +/** + * \brief Set the USB address that is used. + * \param[in] addr The address to set. + */ +void usb_d_set_address(const uint8_t addr); + +/** + * \brief Send remote wakeup to host + * \return Operation status. + */ +void usb_d_send_remotewakeup(void); + +/** + * \brief Initialize the endpoint 0. + * + * Note that endpoint 0 must be initialized as control endpoint. + * + * \param[in] max_pkt_size Max. packet size of EP0. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep0_init(const uint8_t max_pkt_size); + +/** + * \brief Initialize the endpoint. + * + * \param[in] ep The endpoint address. + * \param[in] attr The endpoint attributes. + * \param[in] max_pkt_size Max. packet size of EP0. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size); + +/** + * \brief Disable and deinitialize the endpoint. + * \param[in] ep The endpoint address to deinitialize. + */ +void usb_d_ep_deinit(const uint8_t ep); + +/** + * \brief Register the USB device endpoint callback on initialized endpoint. + * + * \param[in] ep The endpoint address. + * \param[in] type The callback type to register. + * \param[in] func The callback function, NULL to disable callback. + */ +void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func); + +/** + * \brief Enabled the initialized endpoint. + * + * Setup request will be monitored after enabling a control endpoint. + * + * \param[in] ep The endpoint address. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep_enable(const uint8_t ep); + +/** + * \brief Disable the initialized endpoint. + * \param[in] ep The endpoint address. + */ +void usb_d_ep_disable(const uint8_t ep); + +/** + * \brief Get request data pointer to access received setup request packet + * \param[in] ep The endpoint address. + * \return Pointer to the request data. + * \retval NULL The endpoint is not a control endpoint. + */ +uint8_t *usb_d_ep_get_req(const uint8_t ep); + +/** + * \brief Endpoint transfer. + * + * For control endpoints, start the transfer according to the direction in the bmRequest + * type, and finish with STATUS stage. + * For non-control endpoints, the transfer will be unique direction. Defined by + * bit 8 of the endpoint address. + * + * \param[in] xfer Pointer to the transfer description. + * \return Operation status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer); + +/** + * \brief Abort an on-going transfer on a specific endpoint. + * + * \param[in] ep The endpoint address. + */ +void usb_d_ep_abort(const uint8_t ep); + +/** + * \brief Retrieve the endpoint status. + * + * \param[in] ep The endpoint address. + * \param[out] stat Pointer to the buffer to fill the status description. + * + * \return Endpoint status. + * \retval 1 Busy. + * \retval 0 Idle. + * \retval <0 Error code. + */ +int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat); + +/** + * \brief Endpoint halt control. + * + * \param[in] ep The endpoint address. + * \param[in] ctrl Control code (SET/CLEAR/GET). + * + * \return Operation status or HALT state (if \c ctrl is \ref USB_EP_HALT_GET). + */ +int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl); + +/** \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usb_d_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_adc_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_adc_async.h new file mode 100644 index 0000000000000..31612be00e42a --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_adc_async.h @@ -0,0 +1,274 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_ASYNC_H_INCLUDED +#define _HPL_ADC_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL ADC + * + * \section hpl_async_adc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_adc_sync.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief ADC device structure + * + * The ADC device structure forward declaration. + */ +struct _adc_async_device; + +/** + * \brief ADC callback types + */ +enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB }; + +/** + * \brief ADC interrupt callbacks + */ +struct _adc_async_callbacks { + void (*window_cb)(struct _adc_async_device *device, const uint8_t channel); + void (*error_cb)(struct _adc_async_device *device, const uint8_t channel); +}; + +/** + * \brief ADC channel interrupt callbacks + */ +struct _adc_async_ch_callbacks { + void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data); +}; + +/** + * \brief ADC descriptor device structure + */ +struct _adc_async_device { + struct _adc_async_callbacks adc_async_cb; + struct _adc_async_ch_callbacks adc_async_ch_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous ADC + * + * This function does low level ADC configuration. + * + * param[in] device The pointer to ADC device instance + * param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw); + +/** + * \brief Deinitialize ADC + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_async_deinit(struct _adc_async_device *const device); + +/** + * \brief Enable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Disable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Retrieve ADC conversion data size + * + * \param[in] device The pointer to ADC device instance + * + * \return The data size in bytes + */ +uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device); + +/** + * \brief Check if conversion is done + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * \return The status of conversion + * \retval true The conversion is done + * \retval false The conversion is not done + */ +bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Make conversion + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_async_convert(struct _adc_async_device *const device); + +/** + * \brief Retrieve the conversion result + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * The result value + */ +uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel); + +/** + * \brief Set reference source + * + * \param[in] device The pointer to ADC device instance + * \param[in] reference A reference source to set + */ +void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference); + +/** + * \brief Set resolution + * + * \param[in] device The pointer to ADC device instance + * \param[in] resolution A resolution to set + */ +void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * \param[in] device The pointer to ADC device instance + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + */ +void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set conversion mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A conversion mode to set + */ +void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode); + +/** + * \brief Set differential mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + */ +void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set gain + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] gain A gain to set + */ +void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain); + +/** + * \brief Set window mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A mode to set + */ +void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode); + +/** + * \brief Set lower threshold + * + * \param[in] device The pointer to ADC device instance + * \param[in] low_threshold A lower threshold to set + * \param[in] up_threshold An upper thresholds to set + */ +void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * \param[in] device The pointer to ADC device instance + * \param[out] state The threshold state + */ +void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state); + +/** + * \brief Enable/disable ADC channel interrupt + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, + const enum _adc_async_callback_type type, const bool state); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_ADC_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_adc_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_adc_dma.h new file mode 100644 index 0000000000000..40ff158d23a90 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_adc_dma.h @@ -0,0 +1,253 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_DMA_H_INCLUDED +#define _HPL_ADC_DMA_H_INCLUDED + +/** + * \addtogroup HPL ADC + * + * \section hpl_dma_adc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief ADC device structure + * + * The ADC device structure forward declaration. + */ +struct _adc_dma_device; + +/** + * \brief ADC callback types + */ +enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB }; + +/** + * \brief ADC interrupt callbacks + */ +struct _adc_dma_callbacks { + void (*complete)(struct _adc_dma_device *device, const uint16_t data); + void (*error)(struct _adc_dma_device *device); +}; + +/** + * \brief ADC descriptor device structure + */ +struct _adc_dma_device { + struct _adc_dma_callbacks adc_dma_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous ADC + * + * This function does low level ADC configuration. + * + * param[in] device The pointer to ADC device instance + * param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw); + +/** + * \brief Deinitialize ADC + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_dma_deinit(struct _adc_dma_device *const device); + +/** + * \brief Enable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel); + +/** + * \brief Disable ADC peripheral + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel); + +/** + * \brief Return address of ADC DMA source + * + * \param[in] device The pointer to ADC device instance + * + * \return ADC DMA source address + */ +uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device); + +/** + * \brief Retrieve ADC conversion data size + * + * \param[in] device The pointer to ADC device instance + * + * \return The data size in bytes + */ +uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device); + +/** + * \brief Check if conversion is done + * + * \param[in] device The pointer to ADC device instance + * + * \return The status of conversion + * \retval true The conversion is done + * \retval false The conversion is not done + */ +bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device); + +/** + * \brief Make conversion + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_dma_convert(struct _adc_dma_device *const device); + +/** + * \brief Set reference source + * + * \param[in] device The pointer to ADC device instance + * \param[in] reference A reference source to set + */ +void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference); + +/** + * \brief Set resolution + * + * \param[in] device The pointer to ADC device instance + * \param[in] resolution A resolution to set + */ +void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * \param[in] device The pointer to ADC device instance + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + */ +void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set conversion mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A conversion mode to set + */ +void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode); + +/** + * \brief Set differential mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + */ +void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set gain + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] gain A gain to set + */ +void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain); + +/** + * \brief Set window mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A mode to set + */ +void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode); + +/** + * \brief Set thresholds + * + * \param[in] device The pointer to ADC device instance + * \param[in] low_threshold A lower thresholds to set + * \param[in] up_threshold An upper thresholds to set + */ +void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * \param[in] device The pointer to ADC device instance + * \param[out] state The threshold state + */ +void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_ADC_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_adc_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_adc_sync.h new file mode 100644 index 0000000000000..84ab01ab32295 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_adc_sync.h @@ -0,0 +1,281 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_SYNC_H_INCLUDED +#define _HPL_ADC_SYNC_H_INCLUDED + +/** + * \addtogroup HPL ADC + * + * \section hpl_adc_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "compiler.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief ADC reference source + */ +typedef uint8_t adc_reference_t; + +/** + * \brief ADC resolution + */ +typedef uint8_t adc_resolution_t; + +/** + * \brief ADC positive input for channel + */ +typedef uint8_t adc_pos_input_t; + +/** + * \brief ADC negative input for channel + */ +typedef uint8_t adc_neg_input_t; + +/** + * \brief ADC threshold + */ +typedef uint16_t adc_threshold_t; + +/** + * \brief ADC gain + */ +typedef uint8_t adc_gain_t; + +/** + * \brief ADC conversion mode + */ +enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN }; + +/** + * \brief ADC differential mode + */ +enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL }; + +/** + * \brief ADC window mode + */ +typedef uint8_t adc_window_mode_t; + +/** + * \brief ADC threshold status + */ +typedef bool adc_threshold_status_t; + +/** + * \brief ADC sync descriptor device structure + */ +struct _adc_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous ADC + * + * This function does low level ADC configuration. + * + * param[in] device The pointer to ADC device instance + * param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize ADC + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_sync_deinit(struct _adc_sync_device *const device); + +/** + * \brief Enable ADC + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Disable ADC + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + */ +void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Retrieve ADC conversion data size + * + * \param[in] device The pointer to ADC device instance + * + * \return The data size in bytes + */ +uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device); + +/** + * \brief Check if conversion is done + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * \return The status of conversion + * \retval true The conversion is done + * \retval false The conversion is not done + */ +bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Make conversion + * + * \param[in] device The pointer to ADC device instance + */ +void _adc_sync_convert(struct _adc_sync_device *const device); + +/** + * \brief Retrieve the conversion result + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * + * \return The result value of channel + */ +uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel); + +/** + * \brief Set reference source + * + * \param[in] device The pointer to ADC device instance + * \param[in] reference A reference source to set + */ +void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference); + +/** + * \brief Set resolution + * + * \param[in] device The pointer to ADC device instance + * \param[in] resolution A resolution to set + */ +void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution); + +/** + * \brief Set ADC input source of a channel + * + * \param[in] device The pointer to ADC device instance + * \param[in] pos_input A positive input source to set + * \param[in] neg_input A negative input source to set + * \param[in] channel Channel number + */ +void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel); + +/** + * \brief Set conversion mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A conversion mode to set + */ +void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode); + +/** + * \brief Set differential mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] mode A differential mode to set + */ +void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, + const enum adc_differential_mode mode); + +/** + * \brief Set gain + * + * \param[in] device The pointer to ADC device instance + * \param[in] channel Channel number + * \param[in] gain A gain to set + */ +void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain); + +/** + * \brief Set window mode + * + * \param[in] device The pointer to ADC device instance + * \param[in] mode A mode to set + */ +void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode); + +/** + * \brief Set threshold + * + * \param[in] device The pointer to ADC device instance + * \param[in] low_threshold A lower threshold to set + * \param[in] up_threshold An upper thresholds to set + */ +void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold); + +/** + * \brief Retrieve threshold state + * + * \param[in] device The pointer to ADC device instance + * \param[out] state The threshold state + */ +void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_calendar.h b/atmel-samd/asf4/samd51/hal/include/hpl_calendar.h new file mode 100644 index 0000000000000..9b9002c2523b3 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_calendar.h @@ -0,0 +1,252 @@ +/** + * \file + * + * \brief Generic CALENDAR functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_CALENDER_H_INCLUDED +#define _HPL_CALENDER_H_INCLUDED + +#include +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Calendar structure + * + * The Calendar structure forward declaration. + */ +struct calendar_dev; + +/** + * \brief Available mask options for alarms. + * + * Available mask options for alarms. + */ +enum calendar_alarm_option { + /** Alarm disabled. */ + CALENDAR_ALARM_MATCH_DISABLED = 0, + /** Alarm match on second. */ + CALENDAR_ALARM_MATCH_SEC, + /** Alarm match on second and minute. */ + CALENDAR_ALARM_MATCH_MIN, + /** Alarm match on second, minute, and hour. */ + CALENDAR_ALARM_MATCH_HOUR, + /** Alarm match on second, minute, hour, and day. */ + CALENDAR_ALARM_MATCH_DAY, + /** Alarm match on second, minute, hour, day, and month. */ + CALENDAR_ALARM_MATCH_MONTH, + /** Alarm match on second, minute, hour, day, month and year. */ + CALENDAR_ALARM_MATCH_YEAR +}; + +/** + * \brief Available mode for alarms. + */ +enum calendar_alarm_mode { ONESHOT = 1, REPEAT }; +/** + * \brief Prototype of callback on alarm match + */ +typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev); + +/** + * \brief Structure of Calendar instance + */ +struct calendar_dev { + /** Pointer to the hardware base */ + void *hw; + /** Alarm match callback */ + calendar_drv_cb_alarm_t callback; + /** IRQ struct */ + struct _irq_descriptor irq; +}; + +/** + * \brief Time struct for calendar + */ +struct calendar_time { + /*range from 0 to 59*/ + uint8_t sec; + /*range from 0 to 59*/ + uint8_t min; + /*range from 0 to 23*/ + uint8_t hour; +}; + +/** + * \brief Time struct for calendar + */ +struct calendar_date { + /*range from 1 to 28/29/30/31*/ + uint8_t day; + /*range from 1 to 12*/ + uint8_t month; + /*absolute year>= 1970(such as 2000)*/ + uint16_t year; +}; + +/** \brief Calendar driver struct + * + */ +struct calendar_descriptor { + struct calendar_dev device; + struct list_descriptor alarms; + /*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/ + uint32_t base_year; + uint8_t flags; +}; + +/** \brief Date&Time struct for calendar + */ +struct calendar_date_time { + struct calendar_time time; + struct calendar_date date; +}; + +/** \brief struct for alarm time + */ +struct _calendar_alarm { + struct calendar_date_time datetime; + uint32_t timestamp; + enum calendar_alarm_option option; + enum calendar_alarm_mode mode; +}; + +/** + * \brief Initialize Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_init(struct calendar_dev *const dev); + +/** + * \brief Deinitialize Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_deinit(struct calendar_dev *const dev); + +/** + * \brief Enable Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_enable(struct calendar_dev *const dev); + +/** + * \brief Disable Calendar instance + * + * \param[in] dev The pointer to calendar device struct + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_disable(struct calendar_dev *const dev); +/** + * \brief Set time for calendar + * + * \param[in] dev The pointer to calendar device struct + * \param[in] p_calendar_time Pointer to the time configuration + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_set_time(struct calendar_dev *const dev, struct calendar_time *const p_calendar_time); + +/** + * \brief Set date for calendar + * + * \param[in] dev The pointer to calendar device struct + * \param[in] p_calendar_date Pointer to the date configuration + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_set_date(struct calendar_dev *const dev, struct calendar_date *const p_calendar_date); + +/** + * \brief Get the time for calendar HAL instance and hardware + * Retrieve the time from calendar instance. + * + * \param[in] dev The pointer to calendar device struct + * \param[in] date_time Pointer to value that will be filled with current time + * + * \return Return current counter value + */ +uint32_t _calendar_get_date_time(struct calendar_dev *const dev, struct calendar_date_time *const date_time); + +/** + * \brief Set compare value for calendar + * + * \param[in] dev The pointer to calendar device struct + * \param[in] alarm Pointer to the configuration + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_set_alarm(struct calendar_dev *const dev, struct _calendar_alarm *const alarm); + +/** + * \brief Register callback for calendar alarm + * + * \param[in] dev The pointer to calendar device struct + * \param[in] callback The pointer to callback function + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback); + +/** + * \brief Set calendar IRQ + * + * \param[in] dev The pointer to calendar device struct + */ +void _calendar_set_irq(struct calendar_dev *const dev); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RTC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_core.h b/atmel-samd/asf4/samd51/hal/include/hpl_core.h new file mode 100644 index 0000000000000..db448a16ac253 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_core.h @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h new file mode 100644 index 0000000000000..252158296fd0c --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h @@ -0,0 +1,181 @@ +/** + * \file + * + * \brief DAC related functionality declaration. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_DAC_H_INCLUDED +#define _HPL_DAC_H_INCLUDED + +/** + * \addtogroup hpl__dac__group DAC HPL APIs + * See interface description here: \ref hpl__dac__doc + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * DAC hardware Channel Number + */ +#ifndef CHANNEL_NUM +#define CHANNEL_NUM 2 +#endif + +/** + * \brief DAC callback types + */ +enum _dac_callback_type { DAC_DEVICE_CONVERSION_DONE_CB, DAC_DEVICE_ERROR_CB }; + +/** + * \brief DAC device structure + * + * The DAC device structure forward declaration. + */ +struct _dac_async_device; + +/** + * \brief DAC interrupt handlers structure + */ +struct _dac_callback { + /** Transmit ready(Data Buffer empty) handler */ + void (*tx_ready_cb)(struct _dac_async_device *device, const uint8_t ch); + /** Error handler */ + void (*tx_error_cb)(struct _dac_async_device *device, const uint8_t ch); +}; + +/** + * \brief DAC descriptor device structure. + */ +struct _dac_async_device { + struct _dac_callback dac_cb; /*!< Interrupt handers */ + struct _irq_descriptor irq; /*!< Interrupt descriptor */ + void * hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize asynchronous DAC. + * + * This function does low level DAC configuration. + * + * \param[in] device The pointer to DAC device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw); + +/** + * \brief Deinitialize DAC. + * + * \param[in] device The pointer to DAC device instance + */ +void _dac_async_deinit(struct _dac_async_device *const device); + +/** + * \brief Enable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch); + +/** + * \brief Disable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch); + +/** + * \brief Checks if DAC channel is enabled + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + * + * \return true channel is enabled, false otherwise + */ +bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch); + +/** + * \brief Write DAC data for output. + * + * \param[in] device The pointer to DAC device instance + * \param[in] data Digital data which to be converted + * \param[in] ch The channel selected to output + */ +void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch); + +/** + * \brief Enable/disable DAC interrupt + * + * param[in] device The pointer to DAC device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +/** + * \page hpl__dac__doc DAC HPL Interface Driver + * + * \section hpl__dac__desc DAC HPL Description + * + * The following device can use this HPL driver + * - Atmel | SMART SAM D21 + * + * \section hpl__dac__imple DAC HPL Implements + * - \subpage hpl__dac__hw_module1__doc + */ + +#endif /* _HPL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h new file mode 100644 index 0000000000000..ecbe78d59c0db --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h @@ -0,0 +1,147 @@ +/** + * \file + * + * \brief DAC related functionality declaration. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_DAC_SYNC_H_INCLUDED +#define _HPL_DAC_SYNC_H_INCLUDED + +/** + * \addtogroup hpl__dac__group DAC HPL APIs + * See interface description here: \ref hpl__dac__doc + * + */ + +/**@{*/ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * DAC hardware Channel Number + */ +#ifndef CHANNEL_NUM +#define CHANNEL_NUM 2 +#endif + +/** + * \brief DAC sync descriptor device structure. + */ +struct _dac_sync_device { + void *hw; /*!< Hardware module instance handler */ +}; + +/** + * \brief Initialize synchronous DAC. + * + * This function does low level DAC configuration. + * + * \param[in] device The pointer to DAC device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize DAC. + * + * \param[in] device The pointer to DAC device instance + */ +void _dac_sync_deinit(struct _dac_sync_device *const device); + +/** + * \brief Enable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch); + +/** + * \brief Disable DAC Channel. + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + */ +void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch); + +/** + * \brief Checks if DAC channel is enabled + * + * \param[in] device The pointer to DAC device instance + * \param[in] ch channel number + * + * \return true channel is enabled, false otherwise + */ +bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch); + +/** + * \brief Write synchronous DAC data for output. + * + * \param[in] device The pointer to DAC device instance + * \param[in] data Digital data which to be converted + * \param[in] ch The channel selected to output + */ +void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch); + +#ifdef __cplusplus +} +#endif + +/**@}*/ + +/** + * \page hpl__dac__doc DAC HPL Interface Driver + * + * \section hpl__dac__desc DAC HPL Description + * + * The following device can use this HPL driver + * - Atmel | SMART SAM D21 + * + * \section hpl__dac__imple DAC HPL Implements + * - \subpage hpl__dac__hw_module1__doc + */ + +#endif /* _HPL_DAC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_delay.h b/atmel-samd/asf4/samd51/hal/include/hpl_delay.h new file mode 100644 index 0000000000000..7d2a6f90bf863 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_delay.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_dma.h new file mode 100644 index 0000000000000..f8c8cce42392c --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_dma.h @@ -0,0 +1,167 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_evsys.h b/atmel-samd/asf4/samd51/hal/include/hpl_evsys.h new file mode 100644 index 0000000000000..43baf43536e15 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_evsys.h @@ -0,0 +1,104 @@ +/** + * \file + * + * \brief Event system related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_EVSYS_H_INCLUDED +#define _HPL_EVSYS_H_INCLUDED + +/** + * \addtogroup HPL EVSYS + * + * \section hpl_eveys_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Initialize event system. + * + * \return Status of operation. + */ +int32_t _event_system_init(void); + +/** + * \brief Deinitialize event system. + * + * \return Status of operation. + */ +int32_t _event_system_deinit(void); + +/** + * \brief Enable/disable event reception by the given user from the given + * channel + * + * \param[in] user A user to enable + * \param[in] channel A channel the user is assigned to + * \param[in] on true to enable, false to disable + * + * \return Status of operation. + */ +int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on); + +/** + * \brief Enable/disable event generation by the given generator for the given + * channel + * + * \param[in] generator A generator to enable + * \param[in] channel A channel the user is assigned to + * \param[in] on true to enable, false to disable + * + * \return Status of operation. + */ +int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_EVSYS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_gpio.h b/atmel-samd/asf4/samd51/hal/include/hpl_gpio.h new file mode 100644 index 0000000000000..e1de9c58ef117 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_gpio.h @@ -0,0 +1,195 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_async.h new file mode 100644 index 0000000000000..c00d7e733e0fc --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,215 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 0000000000000..4a643ee6567c8 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,195 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_async.h new file mode 100644 index 0000000000000..b240478f73f26 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,194 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 0000000000000..a0f4fa4652e5f --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_init.h b/atmel-samd/asf4/samd51/hal/include/hpl_init.h new file mode 100644 index 0000000000000..be54600c02693 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_init.h @@ -0,0 +1,134 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_irq.h b/atmel-samd/asf4/samd51/hal/include/hpl_irq.h new file mode 100644 index 0000000000000..7325b5711959f --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_irq.h @@ -0,0 +1,126 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_missing_features.h b/atmel-samd/asf4/samd51/hal/include/hpl_missing_features.h new file mode 100644 index 0000000000000..90fa16be4bc73 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_missing_features.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_pwm.h b/atmel-samd/asf4/samd51/hal/include/hpl_pwm.h new file mode 100644 index 0000000000000..8deb54cc02090 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_pwm.h @@ -0,0 +1,203 @@ +/** + * \file + * + * \brief PWM related functionality declaration. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_PWM_H_INCLUDED +#define _HPL_PWM_H_INCLUDED + +/** + * \addtogroup HPL PWM + * + * \section hpl_pwm_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief PWM callback types + */ +enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; + +/** + * \brief PWM pulse-width period + */ +typedef uint32_t pwm_period_t; + +/** + * \brief PWM device structure + * + * The PWM device structure forward declaration. + */ +struct _pwm_device; + +/** + * \brief PWM interrupt callbacks + */ +struct _pwm_callback { + void (*pwm_period_cb)(struct _pwm_device *device); + void (*pwm_error_cb)(struct _pwm_device *device); +}; + +/** + * \brief PWM descriptor device structure + */ +struct _pwm_device { + struct _pwm_callback callback; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief PWM functions, pointers to low-level functions + */ +struct _pwm_hpl_interface { + int32_t (*init)(struct _pwm_device *const device, void *const hw); + void (*deinit)(struct _pwm_device *const device); + void (*start_pwm)(struct _pwm_device *const device); + void (*stop_pwm)(struct _pwm_device *const device); + void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + bool (*is_pwm_enabled)(const struct _pwm_device *const device); + pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); + uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); + void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); +}; +/** + * \brief Initialize TC + * + * This function does low level TC configuration. + * + * \param[in] device The pointer to PWM device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw); + +/** + * \brief Deinitialize TC + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_deinit(struct _pwm_device *const device); + +/** + * \brief Retrieve offset of the given tc hardware instance + * + * \param[in] device The pointer to PWM device instance + * + * \return The offset of the given tc hardware instance + */ +uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); + +/** + * \brief Start hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_enable(struct _pwm_device *const device); + +/** + * \brief Stop hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_disable(struct _pwm_device *const device); + +/** + * \brief Set pwm parameter + * + * \param[in] device The pointer to PWM device instance + * \param[in] period Total period of one PWM cycle. + * \param[in] duty_cycle Period of PWM first half during one cycle. + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + +/** + * \brief Check if pwm is working + * + * \param[in] device The pointer to PWM device instance + * + * \return Check status. + * \retval true The given pwm is working + * \retval false The given pwm is not working + */ +bool _pwm_is_enabled(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform period value + * + * \param[in] device The pointer to PWM device instance + * + * \return Period value. + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform duty cycle value + * + * \param[in] device The pointer to PWM device instance + * + * \return Duty cycle value + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device); + +/** + * \brief Enable/disable PWM interrupt + * + * param[in] device The pointer to PWM device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_ramecc.h b/atmel-samd/asf4/samd51/hal/include/hpl_ramecc.h new file mode 100644 index 0000000000000..014d815ecb323 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_ramecc.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief RAMECC related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RAMECC_H_INCLUDED +#define _HPL_RAMECC_H_INCLUDED + +/** + * \addtogroup HPL RAMECC + * + * \section hpl_ramecc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief RAMECC callback type + */ +typedef void (*ramecc_cb_t)(const uint32_t data); + +/** + * \brief RAMECC callback types + */ +enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; + +/** + * \brief RAMECC interrupt callbacks + */ +struct _ramecc_callbacks { + ramecc_cb_t dual_bit_err; + ramecc_cb_t single_bit_err; +}; + +/** + * \brief RAMECC device structure + */ +struct _ramecc_device { + struct _ramecc_callbacks ramecc_cb; + struct _irq_descriptor irq; +}; + +/** + * \brief Initialize RAMECC + * + * This function does low level RAMECC configuration. + * + * \return initialize status + */ +int32_t _ramecc_init(void); + +/** + * \brief Register RAMECC callback + * + * \param[in] type The type of callback + * \param[in] cb A callback function + */ +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RAMECC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_rand_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_rand_sync.h new file mode 100644 index 0000000000000..3155b718e826d --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_rand_sync.h @@ -0,0 +1,109 @@ +/** + * \file + * + * \brief Random Number Generator (RAND) related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RAND_SYNC_H_INCLUDED +#define _HPL_RAND_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** Random Number Generator polling device. */ +struct _rand_sync_dev { + /** Pointer to private data or hardware base */ + void *prvt; + /** Number of bits generated for each read operation */ + uint8_t n_bits; +}; + +/** + * \brief Initialize the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + * \param[in, out] hw Pointer to the hardware for device instance + * \return Initialization operation result status, 0 for OK. + */ +int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw); + +/** + * \brief Deinitialize the Random Number Generator Driver + * \param[in, out] dev Pointer to the device instance struct + */ +void _rand_sync_deinit(struct _rand_sync_dev *const dev); + +/** + * \brief Enable the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + * \return Enable operation result status, 0 for OK. + */ +int32_t _rand_sync_enable(struct _rand_sync_dev *const dev); + +/** + * \brief Disable the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + */ +void _rand_sync_disable(struct _rand_sync_dev *const dev); + +/** + * \brief Set seed for the Random Number Generator Driver + * \param[out] dev Pointer to the device instance struct + * \param[in] seed The seed to set + * \return Operation result + * \retval ERR_NONE Operation complete success + * \retval ERR_UNSUPPORTED_OP Seed not supported + */ +int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed); + +/** + * \brief Polling random number until it's read back + * \param[in] dev Pointer to the device instance struct + * \return The random number value + */ +uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RAND_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_reset.h b/atmel-samd/asf4/samd51/hal/include/hpl_reset.h new file mode 100644 index 0000000000000..010b7d944a537 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_reset.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + + RESET_REASON_POR = 1, + RESET_REASON_BODCORE = 2, + RESET_REASON_BODVDD = 4, + RESET_REASON_EXT = 8, + RESET_REASON_WDT = 16, + RESET_REASON_SYST = 32, + RESET_REASON_BACKUP = 64 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_sleep.h b/atmel-samd/asf4/samd51/hal/include/hpl_sleep.h new file mode 100644 index 0000000000000..3bd6a1cb2018a --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_sleep.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi.h new file mode 100644 index 0000000000000..14177642f729f --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi.h @@ -0,0 +1,173 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2014 - 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_async.h new file mode 100644 index 0000000000000..b81ef12aff59b --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_async.h @@ -0,0 +1,137 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer complete. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_complete_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_complete_t complete; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_dma.h new file mode 100644 index 0000000000000..3f2088c05e14e --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_dma.h @@ -0,0 +1,98 @@ +/** + * \file + * + * \brief Common SPI DMA related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_DMA_H_INCLUDED +#define _HPL_SPI_DMA_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** The callback types */ +enum _spi_dma_dev_cb_type { + /** Callback type for DMA transmit. */ + SPI_DEV_CB_DMA_TX, + /** Callback type for DMA receive. */ + SPI_DEV_CB_DMA_RX, + /** Callback type for DMA error. */ + SPI_DEV_CB_DMA_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_DMA_N +}; + +struct _spi_dma_dev; + +/** + * \brief The prototype for callback on SPI DMA. + */ +typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_dma_dev_callbacks { + _spi_dma_cb_t tx; + _spi_dma_cb_t rx; + _spi_dma_cb_t error; +}; + +/** SPI driver to support DMA HAL */ +struct _spi_dma_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Pointer to callback functions */ + struct _spi_dma_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; + /** DMA resource */ + struct _dma_resource *resource; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_async.h new file mode 100644 index 0000000000000..f2d330495504a --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_async.h @@ -0,0 +1,248 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_complete_t _spi_async_dev_cb_complete_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_ss_detect(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_dma.h new file mode 100644 index 0000000000000..5e676fdc51001 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,187 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_sync.h new file mode 100644 index 0000000000000..fff1db4f2beb4 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,171 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_async.h new file mode 100644 index 0000000000000..aec3c0a6f1717 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_async.h @@ -0,0 +1,227 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_s_async_dev_cb_complete_t _spi_async_dev_cb_complete_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_sync.h new file mode 100644 index 0000000000000..d4236869714d6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,237 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_sync.h new file mode 100644 index 0000000000000..a231a0bb5cdb2 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_spi_sync.h @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_time_measure.h b/atmel-samd/asf4/samd51/hal/include/hpl_time_measure.h new file mode 100644 index 0000000000000..7502a59107db6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_time_measure.h @@ -0,0 +1,104 @@ +/** + * \file + * + * \brief Time measure related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIME_MEASURE_H_INCLUDED +#define _HPL_TIME_MEASURE_H_INCLUDED + +/** + * \addtogroup HPL Time measure + * + * \section hpl_time_measure_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief System time type + */ +typedef uint32_t system_time_t; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_init(void *const hw); + +/** + * \brief Deinitialize system time module + * + * \param[in] hw The pointer to hardware instance to initialize + */ +void _system_time_deinit(void *const hw); + +/** + * \brief Get system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get(const void *const hw); + +/** + * \brief Get maximum possible system time + * + * \param[in] hw The pointer to hardware instance to initialize + */ +system_time_t _system_time_get_max_time_value(const void *const hw); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_timer.h b/atmel-samd/asf4/samd51/hal/include/hpl_timer.h new file mode 100644 index 0000000000000..d2434e8c40f93 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_timer.h @@ -0,0 +1,170 @@ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usart.h b/atmel-samd/asf4/samd51/hal/include/hpl_usart.h new file mode 100644 index 0000000000000..f6235de93ac8e --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_usart.h @@ -0,0 +1,123 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usart_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_usart_async.h new file mode 100644 index 0000000000000..1bcb3da440126 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_usart_async.h @@ -0,0 +1,280 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usart_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_usart_sync.h new file mode 100644 index 0000000000000..c7881583cc225 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_usart_sync.h @@ -0,0 +1,253 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usb.h b/atmel-samd/asf4/samd51/hal/include/hpl_usb.h new file mode 100644 index 0000000000000..d31bd978559f6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_usb.h @@ -0,0 +1,281 @@ +/** + * \file + * + * \brief SAM USB HPL + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USB_H_INCLUDED +#define _HPL_USB_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \name USB Spec definitions */ +/*@{*/ + +/** Return 8-bit unsigned USB data. */ +#define USB_GET_U8(addr, offset) (((uint8_t *)(addr))[(offset)]) + +/** Return 16-bit unsigned USB data. */ +#define USB_GET_U16(addr, offset) ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8)) + +/** Return 32-bit unsigned USB data. */ +#define USB_GET_U32(addr, offset) \ + ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8) \ + + (((uint8_t *)(addr))[(offset) + 2] << 16) \ + + (((uint8_t *)(addr))[(offset) + 3] << 32)) + +/** Offset of bmRequestType in USB request buffer. */ +#define USB_bmRequestType_Offset 0 + +/** Offset of bRequest in USB request buffer. */ +#define USB_bRequest_Offset 1 + +/** Offset of wValue in USB request buffer. */ +#define USB_wValue_Offset 2 + +/** Offset of wIndex in USB request buffer. */ +#define USB_wIndex_Offset 4 + +/** Offset of wLength in USB request buffer. */ +#define USB_wLength_Offset 6 + +/** Get value of bmRequestType from USB request. */ +#define USB_GET_bmRequestType(req) USB_GET_U8((req), USB_bmRequestType_Offset) + +/** Get value of bRequest from USB request. */ +#define USB_GET_bRequest(req) USB_GET_U8((req), USB_bRequest_Offset) + +/** Get value of wValue from USB request. */ +#define USB_GET_wValue(req) USB_GET_U16((req), USB_wValue_Offset) + +/** Get value of wIndex from USB request. */ +#define USB_GET_wIndex(req) USB_GET_U16((req), USB_wIndex_Offset) + +/** Get value of wLength from USB request. */ +#define USB_GET_wLength(req) USB_GET_U16((req), USB_wLength_Offset) + +/** USB request IN indication of bmRequestType. */ +#define USB_REQ_TYPE_IN 0x80u + +/** USB endpoint number mask of bEndpointAddress. */ +#define USB_EP_N_MASK 0x0Fu + +/** USB endpoint direction bit of bEndpointAddress. */ +#define USB_EP_DIR 0x80u + +/** Get USB endpoint direction from endpoint address. */ +#define USB_EP_GET_DIR(ep_addr) ((ep_addr)&USB_EP_DIR) + +/** Get USB endpoint number from endpoint address. */ +#define USB_EP_GET_N(ep_addr) ((ep_addr)&USB_EP_N_MASK) + +/** Transfer type in EP descriptor bmAttributes: Control. */ +#define USB_EP_XTYPE_CTRL 0x0 + +/** Transfer type in EP descriptor bmAttributes: Isochronous. */ +#define USB_EP_XTYPE_ISOCH 0x1 + +/** Transfer type in EP descriptor bmAttributes: Bulk. */ +#define USB_EP_XTYPE_BULK 0x2 + +/** Transfer type in EP descriptor bmAttributes: Interrupt. */ +#define USB_EP_XTYPE_INTERRUPT 0x3 + +/** Transfer type mask in EP descriptor bmAttributes. */ +#define USB_EP_XTYPE_MASK 0x3u + +/*@}*/ + +/** \name USB status codes + *@{ + */ +/** USB operation is done successfully. */ +#define USB_OK 0 +/** USB (endpoint) is busy. */ +#define USB_BUSY 1 +/** USB (endpoint) is halted. */ +#define USB_HALTED 2 + +/** General error. */ +#define USB_ERROR 0x10 +/** Operation is denied by hardware (e.g., syncing). */ +#define USB_ERR_DENIED 0x11 +/** Input parameter error. */ +#define USB_ERR_PARAM 0x12 +/** Functionality is not supported (e.g., initialize endpoint without cache to be control). */ +#define USB_ERR_FUNC 0x13 +/** Re-initialize, re-enable ... */ +#define USB_ERR_REDO 0x14 +/** Not enough resource (memory, endpoints ...). */ +#define USB_ERR_ALLOC_FAIL 0x15 +/*@}*/ + +/** USB speed. */ +enum usb_speed { + /** USB Low Speed. */ + USB_SPEED_LS, + /** USB Full Speed. */ + USB_SPEED_FS, + /** USB High Speed. */ + USB_SPEED_HS, + /** USB Super Speed. */ + USB_SPEED_SS +}; + +/** USB transaction type. */ +enum usb_trans_type { + /** USB SETUP transaction. */ + USB_TRANS_SETUP, + /** USB IN transaction. */ + USB_TRANS_IN, + /** USB OUT transaction. */ + USB_TRANS_OUT +}; + +/** USB events that generates the device callbacks. */ +enum usb_event { + /** USB VBus changed, with parameter as present/not present. */ + USB_EV_VBUS, + /** USB RESET detected on bus. */ + USB_EV_RESET, + /** USB wakeup. */ + USB_EV_WAKEUP, + /** USB LPM suspend, with parameter as \ref usb_lpm_attributes. */ + USB_EV_LPM_SUSPEND, + /** USB suspend. */ + USB_EV_SUSPEND, + /** USB error, with parameter as error code. */ + USB_EV_ERROR, + /** Number of USB event types. */ + USB_EV_N +}; + +/** Control action for USB device endpoint stall. */ +enum usb_ep_stall_ctrl { + /** Clear stall of the endpoint. */ + USB_EP_STALL_CLR, + /** Stall the endpoint. */ + USB_EP_STALL_SET, + /** Return the stall status. */ + USB_EP_STALL_GET +}; + +/** Control action for USB device endpoint halt. */ +enum usb_ep_halt_ctrl { + /** Clear halt of the endpoint. */ + USB_EP_HALT_CLR = USB_EP_STALL_CLR, + /** Stall the endpoint. */ + USB_EP_HALT_SET = USB_EP_STALL_SET, + /** Return the halt status. */ + USB_EP_HALT_GET = USB_EP_STALL_GET +}; + +/** USB transactions status codes. */ +enum usb_trans_code { + /** TX or RX has been done without error. */ + USB_TRANS_DONE, + /** The endpoint is stalled. */ + USB_TRANS_STALL, + /** The endpoint transactions are aborted (cancel, control setup/status). */ + USB_TRANS_ABORT, + /** The endpoint transactions are aborted by reset/disable. */ + USB_TRANS_RESET, + /** Error is reported on the endpoint. */ + USB_TRANS_ERROR +}; + +/** Transfer status codes. */ +enum usb_xfer_code { + /** Transfer is done without error, for ctrl it means status packet done. */ + USB_XFER_DONE, + /** For control transfer only, data stage is done without error. */ + USB_XFER_DATA, + /** Endpoint stall is set. */ + USB_XFER_HALT, + /** Endpoint stall is cleared. */ + USB_XFER_UNHALT, + /** Transfer is aborted. */ + USB_XFER_ABORT, + /** Transfer is aborted because endpoint reset/disable. */ + USB_XFER_RESET, + /** There was an error. */ + USB_XFER_ERROR +}; + +/** USB endpoint errors. */ +enum usb_ep_error { + /** No error. */ + USB_EP_NO_ERROR, + /** CRC error. */ + USB_EP_ERR_CRC, + /** Endpoint transfer overflow. */ + USB_EP_ERR_OVERFLOW, + /** Other endpoint errors. */ + USB_EP_ERR_GENERAL +}; + +/** Endpoint transfer state. */ +enum usb_ep_state { + /** Endpoint is disabled. */ + USB_EP_S_DISABLED, + /** Endpoint is not busy. */ + USB_EP_S_IDLE, + /** Control transfer only, endpoint is transferring setup packet. */ + USB_EP_S_X_SETUP, + /** Endpoint is transferring data. */ + USB_EP_S_X_DATA, + /** Control transfer only, endpoint is in status stage. */ + USB_EP_S_X_STATUS, + /** Endpoint is halted. */ + USB_EP_S_HALTED, + /** Endpoint error. */ + USB_EP_S_ERROR +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USB_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usb_device.h b/atmel-samd/asf4/samd51/hal/include/hpl_usb_device.h new file mode 100644 index 0000000000000..640833f457694 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_usb_device.h @@ -0,0 +1,387 @@ +/** + * \file + * + * \brief SAM USB HPL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USB_DEVICE_H_INCLUDED +#define _HPL_USB_DEVICE_H_INCLUDED + +#include +#include "hpl_usb_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** USB Device callback type. */ +enum usb_d_cb_type { + /** USB device SOF callback. */ + USB_D_CB_SOF, + /** USB device events callbacks. */ + USB_D_CB_EVENT, + /** Number of types of USB device callback types. */ + USB_D_CB_N +}; + +/** USB Device endpoint callback type. */ +enum usb_d_ep_cb_type { + /** USB device endpoint setup callback. */ + USB_D_EP_CB_SETUP, + /** USB device endpoint more data callback. */ + USB_D_EP_CB_MORE, + /** USB device endpoint transaction done or error callback. */ + USB_D_EP_CB_XFER, + /** Number of types of USB device endpoint callback types. */ + USB_D_EP_CB_N +}; + +/** Control action for USB device LPM handshake. */ +enum usb_d_lpm_ctrl { + /** No LPM handshake, not supported. */ + USB_D_LPM_DISABLE, + /** ACK the LPM transaction. */ + USB_D_LPM_ACK, + /** NYET the LPM transaction. */ + USB_D_LPM_NYET +}; + +/** + * USB device transfer descriptor. + */ +struct usb_d_transfer { + /** Pointer to data buffer to transfer. + * Note that it's recommended that the buffer is 32-bit aligned since + * some of USB peripheral require this. + */ + uint8_t *buf; + /** Transfer size, in number of bytes. + * Note that it's recommended that the buffer size is 32-bit aligned + * (modeled by 4) since some of USB peripheral require this. + */ + uint32_t size; + /** Endpoint address. */ + uint8_t ep; + /** Append ZLP for IN transfer, wait ZLP for OUT transfer. */ + uint8_t zlp; +}; + +/** USB device transactions status structure. */ +struct usb_d_trans_status { + /** Total data size. */ + uint32_t size; + /** Total transfered data count. */ + uint32_t count; + /** Endpoint address. */ + uint8_t ep; + /** Endpoint type - CTRL/ISO/INT/BULK. */ + uint8_t xtype : 2; + /** Transactions state, busy or not. */ + uint8_t busy : 1; + /** Transactions state, setup received or not. */ + uint8_t setup : 1; + /** Transactions state, stall or not. */ + uint8_t stall : 1; + /** Transactions direction. */ + uint8_t dir : 1; +}; + +/** Prototype function for callback that is invoked on USB device SOF. */ +typedef void (*_usb_d_dev_sof_cb_t)(void); + +/** Prototype function for callback that is invoked on USB device events. */ +typedef void (*_usb_d_dev_event_cb_t)(const enum usb_event, const uint32_t param); + +/** HPL USB device callbacks. */ +struct _usb_d_dev_callbacks { + /** Callback that is invoked on SOF. */ + _usb_d_dev_sof_cb_t sof; + /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ + _usb_d_dev_event_cb_t event; +}; + +/** USB device endpoint callbacks. */ +enum usb_d_dev_ep_cb_type { + /** Setup packet is received. */ + USB_D_DEV_EP_CB_SETUP, + /** Try to require more data. */ + USB_D_DEV_EP_CB_MORE, + /** Transaction done OK/ERROR. */ + USB_D_DEV_EP_CB_DONE, + /** Number of device endpoint callbacks. */ + USB_D_DEV_EP_CB_N +}; + +/** + * Callback that is invoked when control SETUP packet has bee received. + * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and allow + * IN/OUT transactions on control endpoint. + */ +typedef void (*_usb_d_dev_ep_cb_setup_t)(const uint8_t ep); + +/** Callback that is invoked when buffer is done, but last packet is full size + * packet without ZLP. Return \c true if more data has been requested. */ +typedef bool (*_usb_d_dev_ep_cb_more_t)(const uint8_t ep, const uint32_t transfered); + +/** Callback that is invoked when all data is finished, including background + * transfer, or error happens. */ +typedef void (*_usb_d_dev_ep_cb_done_t)(const uint8_t ep, const int32_t code, const uint32_t transfered); + +/** Callbacks for HPL USB device endpoint. */ +struct _usb_d_dev_ep_callbacks { + /** Callback that is invoked when SETUP packet is received. + * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and + * allow IN/OUT transactions on control endpoint. + */ + _usb_d_dev_ep_cb_setup_t setup; + /** Callback that is invoked to check if buffer is NULL and more data is + * required. + * It's called when last packet is full size packet, without + * auto ZLP enabled. + * It could be called when background transfer is still in progress. + */ + _usb_d_dev_ep_cb_more_t more; + /** Callback that is invoked when transaction is done, including background + * transfer, or error occurs. + */ + _usb_d_dev_ep_cb_done_t done; +}; + +/** + * \brief Initialize the USB device instance + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_init(void); + +/** + * \brief Deinitialize the USB device instance + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +void _usb_d_dev_deinit(void); + +/** + * \brief Register callback to handle USB device events + * \param[in] type Callback type. See \ref usb_d_cb_type. + * \param[in] func Pointer to callback function. + * Refer to \ref _usb_d_dev_callbacks for the prototypes. + */ +void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); + +/** + * \brief Register callback to handle USB device endpoint events + * \param[in] type Callback type. See \ref usb_d_dev_ep_cb_type. + * \param[in] func Pointer to callback function. + * Refer to \ref _usb_d_dev_ep_callbacks for the prototypes. + */ +void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func); + +/** + * \brief Enable the USB device + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_enable(void); + +/** + * \brief Disable the USB device + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_disable(void); + +/** + * \brief Attach the USB device + */ +void _usb_d_dev_attach(void); + +/** + * \brief Detach the USB device + */ +void _usb_d_dev_detach(void); + +/** + * \brief Send the USB device remote wakeup to host + */ +void _usb_d_dev_send_remotewakeup(void); + +/** + * \brief Get the USB device working speed + * \return USB speed. See \ref usb_speed. + */ +enum usb_speed _usb_d_dev_get_speed(void); + +/** + * \brief Set the USB device address + * \param[in] addr Address to be used. + */ +void _usb_d_dev_set_address(const uint8_t addr); + +/** + * \brief Get the USB device address + * \return Address that is used. + */ +uint8_t _usb_d_dev_get_address(void); + +/** + * \brief Get the USB device frame number + * \return The frame number. + */ +uint16_t _usb_d_dev_get_frame_n(void); + +/** + * \brief Get the USB device micro frame number + * \return The micro frame number inside one frame (0~7). + */ +uint8_t _usb_d_dev_get_uframe_n(void); + +/** + * \brief Initialize and enable the USB device default endpoint 0 + * \param[in] max_pkt_siz Max endpoint size. + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz); + +/** + * \brief Initialize and enable the USB device endpoint + * \param[in] ep Endpoint address, + * see endpoint descriptor details in USB spec. + * \param[in] attr Endpoint attributes, + * see endpoint descriptor details in USB spec. + * \param[in] max_pkt_siz Endpoint size, + * see endpoint descriptor details in USB spec. + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, uint16_t max_pkt_siz); + +/** + * \brief Disable and deinitialize the USB device endpoint + + * \param[in] ep The endpoint to deinitialize. + */ +void _usb_d_dev_ep_deinit(const uint8_t ep); + +/** + * \brief Enable the endpoint + * \param[in] ep The endpoint to enable. + * \return Operation result status. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_enable(const uint8_t ep); + +/** + * \brief Disable the endpoint + * \param[in] ep The endpoint to disable. + */ +void _usb_d_dev_ep_disable(const uint8_t ep); + +/** + * \brief Set/Clear/Get USB device endpoint stall status + * \param[in] ep Endpoint address. + * \param[in] ctrl Operation selector. See \ref usb_ep_stall_ctrl. + * \return Operation result or stall status. + * \retval 0 Success or not stall. + * \retval 1 Endpoint is stalled. + * \retval -1 error. + */ +int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl); + +/** + * \brief Read setup request data from specific endpoint + * \param[in] ep Endpoint address. + * \param[out] req_buf Pointer to buffer to locate the setup packet. + * \return Number of bytes or error code. + * \retval <0 error code. + * \retval 0 No setup packet ready for read. + * \retval >0 Size of bytes read, and ready to start IN/OUT. Note that if + * this number is over 8, only first 8 bytes will be copied. + */ +int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf); + +/** + * \brief Start USB device transfer + * + * On different USB peripheral hardware the transaction buffer address and size + * may have different constraints. E.g., some hardware may require input address + * 32-bit aligned, and input size 32-bit aligned. Refer to the corresponding + * hardware usage reference documents. + * The constraints are checked in implementation, with error code returned. + * + * \param[in] trans Pointer to the transaction description. + * \return Operation result status. + * \retval 1 Busy. + * \retval 0 Success. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans); + +/** + * \brief Abort pending USB device transaction on specific endpoint + * \param[in] ep Endpoint address to abort. + */ +void _usb_d_dev_ep_abort(const uint8_t ep); + +/** + * \brief Retrieve endpoint status. + * \param[in] ep Endpoint address. + * \param[out] stat Pointer to buffer to fill status description. + * \return Status. + * \retval 2 Packet writing. + * \retval 1 Busy. + * \retval 0 Ready. + * \retval <0 Error code. + */ +int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usb_host.h b/atmel-samd/asf4/samd51/hal/include/hpl_usb_host.h new file mode 100644 index 0000000000000..ee48ecc3a094b --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/include/hpl_usb_host.h @@ -0,0 +1,628 @@ +/** + * \file + * + * \brief SAM USB host HPL + * + * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USB_HOST_H_INCLUDED +#define _HPL_USB_HOST_H_INCLUDED + +#include +#include +#include "hpl_usb_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** Driver version */ +#define USB_H_VERSION 0x00000001 + +/** + * @brief USB HCD callback types + */ +enum usb_h_cb_type { + /** SOF generated */ + USB_H_CB_SOF, + /** Root Hub change detected */ + USB_H_CB_ROOTHUB_CHANGE, + /** Number of USB HCD callback types */ + USB_H_CB_N +}; + +/** + * @brief USB HCD resource strategy + */ +enum usb_h_rsc_strategy { + /** Normal resource allocation, e.g., + * 1 bank for interrupt endpoint, + * 2 bank for bulk endpoint and normal iso endpoint, + * 3 bank for iso high bandwidth endpoint. + */ + USB_H_RSC_NORMAL = false, + /** Minimal resource allocation, e.g., only 1 bank for bulk endpoints */ + USB_H_RSC_MINIMAL = true +}; + +/** + * @brief USB HCD pipe states + */ +enum usb_h_pipe_state { + /** Pipe is free to allocate */ + USB_H_PIPE_S_FREE = 0x00, + /** Pipe is in configuration */ + USB_H_PIPE_S_CFG = 0x01, + /** Pipe is allocated and idle */ + USB_H_PIPE_S_IDLE = 0x02, + /** Pipe in control setup stage */ + USB_H_PIPE_S_SETUP = 0x03, + /** Pipe in data IN stage */ + USB_H_PIPE_S_DATI = 0x05, + /** Pipe in data OUT stage */ + USB_H_PIPE_S_DATO = 0x06, + /** Pipe in data IN ZLP stage */ + USB_H_PIPE_S_ZLPI = 0x07, + /** Pipe in data OUT ZLP stage */ + USB_H_PIPE_S_ZLPO = 0x08, + /** Pipe in control status IN stage */ + USB_H_PIPE_S_STATI = 0x09, + /** Pipe in control status OUT stage */ + USB_H_PIPE_S_STATO = 0x0A, + /** Taken by physical pipe (in process) */ + USB_H_PIPE_S_TAKEN = 0x10 +}; + +/** + * @brief USB HCD status code + */ +enum usb_h_status { + /** OK */ + USB_H_OK = ERR_NONE, + /** Busy */ + USB_H_BUSY = ERR_BUSY, + /** Denied */ + USB_H_DENIED = ERR_DENIED, + /** Timeout */ + USB_H_TIMEOUT = ERR_TIMEOUT, + /** Abort */ + USB_H_ABORT = ERR_ABORTED, + /** Stall protocol */ + USB_H_STALL = ERR_PROTOCOL, + /** Transfer reset by pipe re-configure */ + USB_H_RESET = ERR_REQ_FLUSHED, + /** Argument error */ + USB_H_ERR_ARG = ERR_INVALID_ARG, + /** Operation not supported */ + USB_H_ERR_UNSP_OP = ERR_UNSUPPORTED_OP, + /** No resource */ + USB_H_ERR_NO_RSC = ERR_NO_RESOURCE, + /** Not initialized */ + USB_H_ERR_NOT_INIT = ERR_NOT_INITIALIZED, + /** Some general error */ + USB_H_ERR = ERR_IO +}; + +/** Forward declare for pipe structure */ +struct usb_h_pipe; + +/** Forward declare for driver descriptor structure */ +struct usb_h_desc; + +/** + * \brief Prototyping USB HCD callback of SOF + */ +typedef void (*usb_h_cb_sof_t)(struct usb_h_desc *drv); + +/** + * \brief Prototyping USB HCD callback of root hub changing. + * According to the bitmap size, max port number is 31. + */ +typedef void (*usb_h_cb_roothub_t)(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); + +/** + * Prototyping USB HCD callback of pipe transfer done. + * For control pipe, it's forced to call even if there is no transfer + * in progress, since the pipe size could be changed at run time. + */ +typedef void (*usb_h_pipe_cb_xfer_t)(struct usb_h_pipe *pipe); + +/** Access to max packet size of a pipe */ +#define usb_h_pipe_max_pkt_size(p) (p->max_pkt_size) + +/** Access to device address of a pipe */ +#define usb_h_pipe_dev_addr(p) (p->dev) + +/** Access to endpoint address of a pipe */ +#define usb_h_pipe_ep_addr(p) (p->ep) + +/** Access to state of a pipe */ +#define usb_h_pipe_state(p) (p->x.general.state) + +/** Access to status of a pipe */ +#define usb_h_pipe_status(p) (p->x.general.status) + +/** + * @brief USB Host Controller device structure + */ +struct usb_h_desc { + /** Pointer to hardware base */ + void *hw; + /** Pointer to private data for Host Controller driver */ + void *prvt; + /** Interrupt handling descriptor */ + struct _irq_descriptor irq; + /** Callback of SOF */ + usb_h_cb_sof_t sof_cb; + /** Callback of root hub change */ + usb_h_cb_roothub_t rh_cb; +#if CONF_USB_H_INST_OWNER_SP + /** Extension for the driver owner (upper layer user) */ + void *owner; +#endif +}; + +/** + * @brief Transfer descriptor for control transfer + * + * Timing in USB 2.0 spec.: + * - 9.2.6.1 : USB sets an upper limit of 5 seconds as the upper limit for any + * command to be processed. + * - 9.2.6.3 : if a device receives a SetAddress() request, the device must be + * able to complete processing of the request and be able to + * successfully complete the Status stage of the request within + * 50 ms. + * After successful completion of the Status stage, the device is + * allowed a SetAddress() recovery interval of 2 ms. At the end of + * this interval, the device must be able to accept Setup packets + * addressed to the new address. + * - 9.2.6.4 : For standard device requests that require no Data stage, a device + * must be able to complete the request and be able to successfully + * complete the Status stage of the request within 50 ms of receipt + * of the request. This limitation applies to requests to the + * device, interface, or endpoint. + * For standard device requests that require data stage transfer to + * the host, the device must be able to return the first data packet + * to the host within 500 ms of receipt of the request. For + * subsequent data packets, if any, the device must be able to + * return them within 500 ms of successful completion of the + * transmission of the previous packet. The device must then be + * able to successfully complete the status stage within 50 ms after + * returning the last data packet. + * For standard device requests that require a data stage transfer + * to the device, the 5-second limit applies. + * - 9.2.6.5 : Unless specifically exempted in the class document, all + * class-specific requests must meet the timing limitations for + * standard device requests. + * + * Conclusion: + * 1. Whole request with data: 5 seconds + * 2. Whole request without data: 50 ms + * 3. Data packets: 500 ms + */ +struct usb_h_ctrl_xfer { + /** Pointer to transfer data */ + uint8_t *data; + /** Pointer to setup packet */ + uint8_t *setup; + /** Expected transfer size */ + uint16_t size; + /** Transfer count */ + uint16_t count; + /** Timeout for request, -1 if disable timeout */ + int16_t req_timeout; + /** Timeout between packets + * (500ms for data and 50ms for status), -1 if disabled */ + int16_t pkt_timeout; + /** Packet size during transfer (<= allocate max packet size) */ + uint16_t pkt_size; + + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief Transfer descriptor for bulk / interrupt / iso transfer + */ +struct usb_h_bulk_int_iso_xfer { + /** Expected transfer size */ + uint32_t size; + /** Transfer count */ + uint32_t count; + /** Pointer to transfer data */ + uint8_t *data; + /** Reserved */ + uint16_t reserved[3]; + + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief Transfer descriptor for periodic high bandwidth transfer + */ +struct usb_h_high_bw_xfer { + /** Expected transfer size */ + uint32_t size; + /** Transfer count */ + uint32_t count; + /** Pointer to transfer data */ + uint8_t *data; + /** Micro frame packet sizes */ + uint16_t pkt_size[3]; + + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief General transfer descriptor + */ +struct usb_h_xfer { + /** Reserved for different transfer */ + union { + uint16_t u16[9]; + uint8_t u8[18]; + } reserved; + /** Transfer state */ + uint8_t state; + /** Last transfer status */ + int8_t status; +}; + +/** + * @brief USB Host Controller Driver Pipe structure + */ +struct usb_h_pipe { + /** Pointer to the USB Host Controller Driver */ + struct usb_h_desc *hcd; + /** Pointer to the callback for transfer done */ + usb_h_pipe_cb_xfer_t done; +#if CONF_USB_H_INST_OWNER_SP + /** Pointer to the pipe owner */ + void *owner; +#endif + + /** Endpoint max packet size (bits 10..0) */ + uint16_t max_pkt_size; + /** Device address */ + uint8_t dev; + /** Endpoint address */ + uint8_t ep; + + /** Endpoint interval */ + uint8_t interval; + /** Endpoint type: Control, Isochronous, Bulk or Interrupt */ + uint8_t type; + /** Current toggle (driver dependent) */ + uint8_t toggle; + /** Endpoint number of banks (HW dependent) */ + uint8_t bank : 2; + /** Transfer speed (HW dependent) */ + uint8_t speed : 2; + /** High bandwidth periodic out */ + uint8_t high_bw_out : 1; + /** Uses DMA (on transfer) */ + uint8_t dma : 1; + /** Transfer ZLP support */ + uint8_t zlp : 1; + /** Transfer periodic */ + uint8_t periodic_start : 1; + + /** Transfer status */ + union { + /** General transfer info */ + struct usb_h_xfer general; + /** Control transfer status */ + struct usb_h_ctrl_xfer ctrl; + /** Bulk interrupt iso transfer status */ + struct usb_h_bulk_int_iso_xfer bii; + /** Periodic high bandwidth transfer status */ + struct usb_h_high_bw_xfer hbw; + } x; +}; + +/** + * @brief USB HCD Initialization + * + * @param drv Pointer to the HCD driver instance + * @param[in] hw Pointer to hardware base + * @param[in] prvt The private driver data (implement specific) + * + * @return Operation result status + * @retval ERR_DENIED Hardware has been enabled + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_init(struct usb_h_desc *drv, void *hw, void *prvt); + +/** + * @brief USB HCD de-initialization + * + * @param drv The driver + */ +void _usb_h_deinit(struct usb_h_desc *drv); + +/** + * @brief USB HCD enable + * + * @param drv The driver + */ +void _usb_h_enable(struct usb_h_desc *drv); + +/** + * @brief USB HCD disable + * + * @param drv The driver + */ +void _usb_h_disable(struct usb_h_desc *drv); + +/** + * @brief Register callbacks for USB HCD + * + * @param drv The driver + * @param[in] type The callback type + * @param[in] cb The callback function entry + * + * @return Operation result status + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_register_callback(struct usb_h_desc *drv, enum usb_h_cb_type type, FUNC_PTR cb); + +/** + * @brief Return current frame number + * + * @param drv The driver + * + * @return current frame number + */ +uint16_t _usb_h_get_frame_n(struct usb_h_desc *drv); + +/** + * @brief Return current micro frame number + * + * @param drv The driver + * + * @return current micro frame number + */ +uint8_t _usb_h_get_microframe_n(struct usb_h_desc *drv); + +/** + * @brief Suspend the USB bus + * + * @param drv The driver + */ +void _usb_h_suspend(struct usb_h_desc *drv); + +/** + * @brief Resume the USB bus + * + * @param drv The driver + */ +void _usb_h_resume(struct usb_h_desc *drv); + +/* Root hub related APIs */ + +/** + * \brief Reset the root hub port + * + * \param[in,out] drv Pointer to the USB HCD driver + * \param[in] port Root hub port, ignored if there is only one port + */ +void _usb_h_rh_reset(struct usb_h_desc *drv, uint8_t port); + +/** + * \brief Suspend the root hub port + * + * \param[in,out] drv Pointer to the USB HCD driver + * \param[in] port Root hub port, ignored if there is only one port + */ +void _usb_h_rh_suspend(struct usb_h_desc *drv, uint8_t port); + +/** + * \brief Resume the root hub port + * + * \param[in,out] drv Pointer to the USB HCD driver + * \param[in] port Root hub port, ignored if there is only one port + */ +void _usb_h_rh_resume(struct usb_h_desc *drv, uint8_t port); + +/** + * \brief Root hub or port feature status check + * + * Check USB Spec. for hub status and feature selectors. + * + * \param[in] drv Pointer to the USB HCD driver + * \param[in] port Set to 0 to get hub status, otherwise to get port status + * \param[in] ftr Hub feature/status selector + * (0: connection, 2: suspend, 4: reset, 9: LS, 10: HS) + * + * \return \c true if the status bit is 1 + */ +bool _usb_h_rh_check_status(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); + +/* Pipe transfer functions */ + +/** + * @brief Allocate a pipe for USB host communication + * + * @param drv The USB HCD driver + * @param[in] dev The device address + * @param[in] ep The endpoint address + * @param[in] max_pkt_size The endpoint maximum packet size + * @param[in] attr The endpoint attribute + * @param[in] interval The endpoint interval + * (bInterval of USB Endpoint Descriptor) + * @param[in] speed The transfer speed of the endpoint + * @param[in] minimum_rsc Minimum the resource usage, \sa usb_h_rsc_strategy + * + * @return Pointer to allocated pipe structure instance + * @retval NULL allocation fail + */ +struct usb_h_pipe *_usb_h_pipe_allocate(struct usb_h_desc *drv, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, + uint8_t attr, uint8_t interval, uint8_t speed, bool minimum_rsc); + +/** + * @brief Free an allocated pipe + * + * @param pipe The pipe + * + * @return Operation result status + * @retval ERR_BUSY Pipe is busy, use \ref _usb_h_pipe_abort to abort + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_pipe_free(struct usb_h_pipe *pipe); + +/** + * @brief Modify parameters of an allocated control pipe + * + * @param pipe The pipe + * @param[in] dev The device address + * @param[in] ep The endpoint address + * @param[in] max_pkt_size The maximum packet size, must be equal or + * less than allocated size + * @param[in] speed The working speed + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_pipe_set_control_param(struct usb_h_pipe *pipe, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, + uint8_t speed); + +/** + * @brief Register transfer callback on a pipe + * + * @param pipe The pipe + * @param[in] cb Transfer callback function + * + * @return Operation result status + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_pipe_register_callback(struct usb_h_pipe *pipe, usb_h_pipe_cb_xfer_t cb); + +/** + * @brief Issue a control transfer (request) on a pipe + * + * \note When there is data stage, timeout between data packets is 500ms, the + * timeout between last data packet and the status packet is 50ms. + * + * @param pipe The pipe + * @param[in] setup Pointer to the setup packet + * @param[in,out] data Pointer to the data buffer + * @param[in] length The data length + * @param[in] timeout Timeout for whole request in ms + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_control_xfer(struct usb_h_pipe *pipe, uint8_t *setup, uint8_t *data, uint16_t length, int16_t timeout); + +/** + * @brief Issue a bulk / interrupt / iso transfer on a pipe + * + * @param pipe The pipe + * @param[in,out] data Pointer to the data buffer + * @param[in] length The data length + * @param[in] auto_zlp Auto append ZLP for OUT + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is control pipe + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_bulk_int_iso_xfer(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, bool auto_zlp); + +/** + * @brief Issue a periodic high bandwidth output on a pipe + * + * @param pipe The pipe + * @param[in,out] data Pointer to the data buffer + * @param[in] length The data length + * @param[in] trans_pkt_size The transaction packet sizes in a micro frame, + * 0 to use endpoint max packet size + * + * @return Operation result status + * @retval ERR_NOT_INITIALIZED Pipe is not allocated + * @retval ERR_BUSY Pipe is busy transferring + * @retval ERR_INVALID_ARG Argument error + * @retval ERR_UNSUPPORTED_OP Pipe is not high bandwidth periodic pipe, or + * DMA feature not enabled, or + * high bandwidth not enabled + * @retval ERR_NONE Operation done successfully + */ +int32_t _usb_h_high_bw_out(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, uint16_t trans_pkt_size[3]); + +/** + * @brief Check if pipe is busy transferring + * + * @param pipe The pipe + * + * @return \c true if pipe is busy + */ +bool _usb_h_pipe_is_busy(struct usb_h_pipe *pipe); + +/** + * @brief Abort pending transfer on a pipe + * + * @param pipe The pipe + */ +void _usb_h_pipe_abort(struct usb_h_pipe *pipe); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_USB_HOST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/src/hal_adc_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_adc_sync.c new file mode 100644 index 0000000000000..9c7c3ab528811 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_adc_sync.c @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief ADC functionality implementation. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +/** + * \brief Indicates HAL being compiled. Must be defined before including. + */ +#define _COMPILING_HAL + +#include "hal_adc_sync.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Maximum amount of ADC interface instances + */ +#define MAX_ADC_AMOUNT ADC_INST_NUM + +/** + * \brief Initialize ADC + */ +int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func) +{ + ASSERT(descr && hw); + + return _adc_sync_init(&descr->device, hw); +} + +/** + * \brief Deinitialize ADC + */ +int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr) +{ + ASSERT(descr); + _adc_sync_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Enable ADC + */ +int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_enable_channel(&descr->device, channel); + + return ERR_NONE; +} + +/** + * \brief Disable ADC + */ +int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_disable_channel(&descr->device, channel); + return ERR_NONE; +} + +/* + * \brief Read data from ADC + */ +int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, + const uint16_t length) +{ + uint8_t data_size; + uint16_t offset = 0; + + ASSERT(descr && buffer && length); + data_size = _adc_sync_get_data_size(&descr->device); + ASSERT(!(length % data_size)); + + do { + uint16_t result; + _adc_sync_convert(&descr->device); + + while (!_adc_sync_is_channel_conversion_done(&descr->device, channel)) + ; + + result = _adc_sync_read_channel_data(&descr->device, channel); + buffer[offset] = result; + if (1 < data_size) { + buffer[offset + 1] = result >> 8; + } + offset += data_size; + } while (offset < length); + + return offset; +} + +/** + * \brief Set ADC reference source + */ +int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference) +{ + ASSERT(descr); + _adc_sync_set_reference_source(&descr->device, reference); + + return ERR_NONE; +} + +/** + * \brief Set ADC resolution + */ +int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution) +{ + ASSERT(descr); + _adc_sync_set_resolution(&descr->device, resolution); + + return ERR_NONE; +} + +/** + * \brief Set ADC input source of a channel + */ +int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + ASSERT(descr); + _adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel); + + return ERR_NONE; +} + +/** + * \brief Set ADC thresholds + */ +int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + ASSERT(descr); + _adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold); + + return ERR_NONE; +} + +/** + * \brief Set ADC gain + */ +int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain) +{ + ASSERT(descr); + _adc_sync_set_channel_gain(&descr->device, channel, gain); + + return ERR_NONE; +} + +/** + * \brief Set ADC conversion mode + */ +int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode) +{ + ASSERT(descr); + _adc_sync_set_conversion_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set ADC differential mode + */ +int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, + const enum adc_differential_mode mode) +{ + ASSERT(descr); + _adc_sync_set_channel_differential_mode(&descr->device, channel, mode); + + return ERR_NONE; +} + +/** + * \brief Set ADC window mode + */ +int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode) +{ + ASSERT(descr); + _adc_sync_set_window_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Retrieve threshold state + */ +int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state) +{ + ASSERT(descr && state); + _adc_sync_get_threshold_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Check if conversion is complete + */ +int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel) +{ + ASSERT(descr); + return _adc_sync_is_channel_conversion_done(&descr->device, channel); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t adc_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +//@} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_atomic.c b/atmel-samd/asf4/samd51/hal/src/hal_atomic.c new file mode 100644 index 0000000000000..82a11e2bdf580 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_atomic.c @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_dac_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_dac_sync.c new file mode 100644 index 0000000000000..a56e6aef77918 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_dac_sync.c @@ -0,0 +1,141 @@ +/** + * \file + * + * \brief DAC functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_dac_sync.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Initialize the DAC HAL instance and hardware. + */ +int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw) +{ + uint8_t i; + int32_t rc; + + ASSERT(descr && hw); + + rc = _dac_sync_init(&descr->device, hw); + if (rc) { + return rc; + } + + for (i = 0; i < CHANNEL_NUM; i++) { + descr->sel_ch[i].buffer = NULL; + descr->sel_ch[i].length = 0; + } + + return ERR_NONE; +} + +/** + * \brief Deinitialize the DAC HAL instance and hardware + */ +int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr) +{ + ASSERT(descr); + + _dac_sync_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Enable DAC channel + */ +int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) +{ + ASSERT(descr && (ch < CHANNEL_NUM)); + + _dac_sync_enable_channel(&descr->device, ch); + + return ERR_NONE; +} + +/** + * \brief Disable DAC channel + */ +int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) +{ + ASSERT(descr && (ch < CHANNEL_NUM)); + + _dac_sync_disable_channel(&descr->device, ch); + + return ERR_NONE; +} + +/** + * \brief DAC convert digital data to analog output + */ +int32_t dac_sync_write(struct dac_sync_descriptor *descr, const uint8_t ch, uint16_t *buffer, uint32_t length) +{ + ASSERT(descr && (ch < CHANNEL_NUM) && buffer && length); + + /* check whether channel is enable */ + if (!_dac_sync_is_channel_enable(&descr->device, ch)) { + return ERR_NOT_READY; + } + + descr->sel_ch[ch].buffer = buffer; + descr->sel_ch[ch].length = length; + + while (descr->sel_ch[ch].length) { + _dac_sync_write_data(&descr->device, *(descr->sel_ch[ch].buffer), ch); + descr->sel_ch[ch].buffer++; + descr->sel_ch[ch].length--; + } + + return ERR_NONE; +} + +/** + * \brief Get DAC driver version + */ +uint32_t dac_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_delay.c b/atmel-samd/asf4/samd51/hal/src/hal_delay.c new file mode 100644 index 0000000000000..ce963db009e88 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_delay.c @@ -0,0 +1,90 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_evsys.c b/atmel-samd/asf4/samd51/hal/src/hal_evsys.c new file mode 100644 index 0000000000000..9001d7239f10f --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_evsys.c @@ -0,0 +1,108 @@ +/** + * \file + * + * \brief HAL event system related functionality implementation. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_evsys.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Initialize event system. + */ +int32_t event_system_init(void) +{ + return _event_system_init(); +} + +/** + * \brief Deinitialize event system. + */ +int32_t event_system_deinit(void) +{ + return _event_system_deinit(); +} + +/** + * \brief Enable event reception by the given user from the given channel + */ +int32_t event_system_enable_user(const uint16_t user, const uint16_t channel) +{ + return _event_system_enable_user(user, channel, true); +} + +/** + * \brief Enable event reception by the given user from the given channel + */ +int32_t event_system_disable_user(const uint16_t user, const uint16_t channel) +{ + return _event_system_enable_user(user, channel, false); +} + +/** + * \brief Enable event generation by the given generator for the given channel + */ +int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel) +{ + return _event_system_enable_generator(generator, channel, true); +} + +/** + * \brief Enable event generation by the given generator for the given channel + */ +int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel) +{ + return _event_system_enable_generator(generator, channel, false); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t event_system_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_gpio.c b/atmel-samd/asf4/samd51/hal/src/hal_gpio.c new file mode 100644 index 0000000000000..319726290226c --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_gpio.c @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Port + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c new file mode 100644 index 0000000000000..c72fe2758aec0 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c @@ -0,0 +1,260 @@ +/** + * \file + * + * \brief I/O I2C related functionality implementation. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Sync version of I2C I/O read + */ +static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; +} + +/** + * \brief Sync version of I2C I/O write + */ +static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP; + msg.buffer = (uint8_t *)buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + return (((int32_t)n) > i2c->device.service.msg.len) ? (((int32_t)n) - i2c->device.service.msg.len) : ret; +} + +/** + * \brief Sync version of i2c initialize + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) +{ + int32_t init_status; + ASSERT(i2c); + + init_status = _i2c_m_sync_init(&i2c->device, hw); + if (init_status) { + return init_status; + } + + /* Init I/O */ + i2c->io.read = i2c_m_sync_read; + i2c->io.write = i2c_m_sync_write; + + return ERR_NONE; +} + +/** + * \brief deinitialize + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) +{ + int32_t status; + ASSERT(i2c); + + status = _i2c_m_sync_deinit(&i2c->device); + if (status) { + return status; + } + + i2c->io.read = NULL; + i2c->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c enable + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_enable(&i2c->device); +} + +/** + * \brief Sync version of i2c disable + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_disable(&i2c->device); +} + +/** + * \brief Sync version of i2c set slave address + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) +{ + return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); +} + +/** + * \brief Sync version of i2c set baudrate + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) +{ + return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); +} + +/** + * \brief Sync version of i2c write command + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c read command + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c transfer command + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) +{ + return _i2c_m_sync_transfer(&i2c->device, msg); +} + +/** + * \brief Sync version of i2c send stop condition command + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) +{ + return _i2c_m_sync_send_stop(&i2c->device); +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) +{ + *io = &i2c->io; + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t i2c_m_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_init.c b/atmel-samd/asf4/samd51/hal/src/hal_init.c new file mode 100644 index 0000000000000..bdcf2a4098541 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_init.c @@ -0,0 +1,57 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_io.c b/atmel-samd/asf4/samd51/hal/src/hal_io.c new file mode 100644 index 0000000000000..52638d9b05768 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_io.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_pwm.c b/atmel-samd/asf4/samd51/hal/src/hal_pwm.c new file mode 100644 index 0000000000000..2b9d2606fd1fe --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_pwm.c @@ -0,0 +1,169 @@ +/** + * \file + * + * \brief PWM functionality implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_pwm.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static void pwm_period_expired(struct _pwm_device *device); +static void pwm_detect_fault(struct _pwm_device *device); + +/** + * \brief Initialize pwm + */ +int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func) +{ + ASSERT(descr && hw); + _pwm_init(&descr->device, hw); + descr->device.callback.pwm_period_cb = pwm_period_expired; + descr->device.callback.pwm_error_cb = pwm_detect_fault; + return ERR_NONE; +} + +/** + * \brief Deinitialize pwm + */ +int32_t pwm_deinit(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + _pwm_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start pwm + */ +int32_t pwm_enable(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + if (_pwm_is_enabled(&descr->device)) { + return ERR_DENIED; + } + _pwm_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop pwm + */ +int32_t pwm_disable(struct pwm_descriptor *const descr) +{ + ASSERT(descr); + if (!_pwm_is_enabled(&descr->device)) { + return ERR_DENIED; + } + _pwm_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Register PWM callback + */ +int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb) +{ + switch (type) { + case PWM_PERIOD_CB: + descr->pwm_cb.period = cb; + break; + + case PWM_ERROR_CB: + descr->pwm_cb.error = cb; + break; + + default: + return ERR_INVALID_ARG; + } + ASSERT(descr); + _pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb); + return ERR_NONE; +} + +/** + * \brief Change PWM parameter + */ +int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle) +{ + ASSERT(descr); + _pwm_set_param(&descr->device, period, duty_cycle); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t pwm_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Process interrupts caused by period experied + */ +static void pwm_period_expired(struct _pwm_device *device) +{ + struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); + + if (descr->pwm_cb.period) { + descr->pwm_cb.period(descr); + } +} + +/** + * \internal Process interrupts caused by pwm fault + */ +static void pwm_detect_fault(struct _pwm_device *device) +{ + struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); + + if (descr->pwm_cb.error) { + descr->pwm_cb.error(descr); + } +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_rand_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_rand_sync.c new file mode 100644 index 0000000000000..927bdbebabf6e --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_rand_sync.c @@ -0,0 +1,132 @@ +/** + * \file + * + * \brief Generic Random Number Generator (RNG) functionality declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include "hal_rand_sync.h" + +#define HAL_RNG_SYNC_VERSION 0x00000001u + +int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw) +{ + ASSERT(desc); + + return _rand_sync_init(&desc->dev, hw); +} + +void rand_sync_deinit(struct rand_sync_desc *const desc) +{ + ASSERT(desc); + _rand_sync_deinit(&desc->dev); +} + +int32_t rand_sync_enable(struct rand_sync_desc *const desc) +{ + ASSERT(desc); + return _rand_sync_enable(&desc->dev); +} + +void rand_sync_disable(struct rand_sync_desc *const desc) +{ + ASSERT(desc); + _rand_sync_disable(&desc->dev); +} + +int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed) +{ + ASSERT(desc); + return _rand_sync_set_seed(&desc->dev, seed); +} + +/** + * \brief Read data bits + */ +static uint32_t _rand_sync_read_data(const struct _rand_sync_dev *dev, const uint8_t n_bits) +{ + uint8_t r_bits = (dev->n_bits < 1) ? 32 : dev->n_bits; + if (r_bits < n_bits) { + uint8_t i; + uint32_t d = 0; + /* Join read bits */ + for (i = 0; i < n_bits; i += r_bits) { + d |= (uint32_t)(_rand_sync_read_one(dev) << i); + } + return d; + } else { + return _rand_sync_read_one(dev); + } +} + +uint8_t rand_sync_read8(const struct rand_sync_desc *const desc) +{ + ASSERT(desc); + return (uint8_t)_rand_sync_read_data(&desc->dev, 8); +} + +uint32_t rand_sync_read32(const struct rand_sync_desc *const desc) +{ + ASSERT(desc); + return (uint32_t)_rand_sync_read_data(&desc->dev, 32); +} + +void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len) +{ + uint32_t i; + ASSERT(desc && (buf && len)); + for (i = 0; i < len; i++) { + buf[i] = (uint8_t)_rand_sync_read_data(&desc->dev, 8); + } +} + +void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len) +{ + uint32_t i; + ASSERT(desc && (buf && len)); + for (i = 0; i < len; i++) { + buf[i] = (uint32_t)_rand_sync_read_data(&desc->dev, 32); + } +} + +uint32_t rand_sync_get_version(void) +{ + return HAL_RNG_SYNC_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_sleep.c b/atmel-samd/asf4/samd51/hal/src/hal_sleep.c new file mode 100644 index 0000000000000..2d1aadd67e6c2 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_sleep.c @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_spi_m_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_spi_m_sync.c new file mode 100644 index 0000000000000..8ceaa9a4aa60f --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_spi_m_sync.c @@ -0,0 +1,212 @@ +/** + * \file + * + * \brief I/O SPI related functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_spi_m_sync.h" +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Driver version + */ +#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u + +#define SPI_DEACTIVATE_NEXT 0x8000 + +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); +static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); + +int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) +{ + int32_t rc = 0; + + ASSERT(spi && hw); + + spi->dev.prvt = (void *)hw; + + rc = _spi_m_sync_init(&spi->dev, hw); + if (rc < 0) { + return rc; + } + + spi->flags = SPI_DEACTIVATE_NEXT; + spi->io.read = _spi_m_sync_io_read; + spi->io.write = _spi_m_sync_io_write; + + return ERR_NONE; +} + +void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + + _spi_m_sync_deinit(&spi->dev); +} + +void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + + _spi_m_sync_enable(&spi->dev); +} + +void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) +{ + ASSERT(spi); + + _spi_m_sync_disable(&spi->dev); +} + +int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) +{ + ASSERT(spi); + + return _spi_m_sync_set_baudrate(&spi->dev, baud_val); +} + +int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) +{ + ASSERT(spi); + + return _spi_m_sync_set_mode(&spi->dev, mode); +} + +int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) +{ + ASSERT(spi); + + return _spi_m_sync_set_char_size(&spi->dev, char_size); +} + +int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) +{ + ASSERT(spi); + + return _spi_m_sync_set_data_order(&spi->dev, dord); +} + +/** \brief Do SPI read in polling way + * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. + * + * It blocks until all data read or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[out] buf Pointer to the buffer to store read data. + * \param[in] size Size of the data in number of characters. + * \return Operation status. + * \retval size Success. + * \retval >=0 Time out, with number of characters read. + */ +static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = buf; + xfer.txbuf = 0; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +/** \brief Do SPI data write in polling way + * For SPI master, activate CS, do buffer send and deactivate CS. The data back + * is discarded. + * + * The data read back is discarded. + * + * It blocks until all data sent or error. + * + * \param[in, out] spi Pointer to the HAL SPI instance. + * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). + * \return Operation status. + * \retval size Success. + * \retval >=0 Timeout, with number of characters transferred. + */ +static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io); + + struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); + struct spi_xfer xfer; + + xfer.rxbuf = 0; + xfer.txbuf = (uint8_t *)buf; + xfer.size = length; + + return spi_m_sync_transfer(spi, &xfer); +} + +int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) +{ + struct spi_msg msg; + + ASSERT(spi && p_xfer); + + msg.txbuf = p_xfer->txbuf; + msg.rxbuf = p_xfer->rxbuf; + msg.size = p_xfer->size; + + return _spi_m_sync_trans(&spi->dev, &msg); +} + +int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) +{ + ASSERT(spi && io); + *io = &spi->io; + return 0; +} + +uint32_t spi_m_sync_get_version(void) +{ + return SPI_M_SYNC_DRIVER_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/atmel-samd/asf4/samd51/hal/src/hal_timer.c b/atmel-samd/asf4/samd51/hal/src/hal_timer.c new file mode 100644 index 0000000000000..db0bbb8daa564 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_timer.c @@ -0,0 +1,263 @@ +/** + * \file + * + * \brief Timer functionality implementation. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_timer.h" +#include +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Timer flags + */ +#define TIMER_FLAG_QUEUE_IS_TAKEN 1 +#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 + +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); +static void timer_process_counted(struct _timer_device *device); + +/** + * \brief Initialize timer + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) +{ + ASSERT(descr && hw); + _timer_init(&descr->device, hw); + descr->time = 0; + descr->device.timer_cb.period_expired = timer_process_counted; + + return ERR_NONE; +} + +/** + * \brief Deinitialize timer + */ +int32_t timer_deinit(struct timer_descriptor *const descr) +{ + ASSERT(descr); + _timer_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start timer + */ +int32_t timer_start(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_start(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop timer + */ +int32_t timer_stop(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (!_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_stop(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Set amount of clock cycler per timer tick + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) +{ + ASSERT(descr); + _timer_set_period(&descr->device, clock_cycles); + + return ERR_NONE; +} + +/** + * \brief Add timer task + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_ALREADY_INITIALIZED; + } + task->time_label = descr->time; + timer_add_timer_task(&descr->tasks, task, descr->time); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Remove timer task + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (!is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_NOT_FOUND; + } + list_delete_element(&descr->tasks, task); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Retrieve the amount of clock cycles in a tick + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) +{ + ASSERT(descr && cycles); + *cycles = _timer_get_period(&descr->device); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t timer_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Insert a timer task into sorted timer's list + * + * \param[in] head The pointer to the head of timer task list + * \param[in] task The pointer to task to add + * \param[in] time Current timer time + */ +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) +{ + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + + if (!head) { + list_insert_as_head(list, new_task); + return; + } + + for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { + uint32_t time_left; + + if (it->time_label <= time) { + time_left = it->interval - (time - it->time_label); + } else { + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + } + if (time_left >= new_task->interval) + break; + prev = it; + } + + if (it == head) { + list_insert_as_head(list, new_task); + } else { + list_insert_after(prev, new_task); + } +} + +/** + * \internal Process interrupts + */ +static void timer_process_counted(struct _timer_device *device) +{ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wcast-align" + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); + #pragma GCC diagnostic pop + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; + + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; + return; + } + + while (it && ((time - it->time_label) >= it->interval)) { + struct timer_task *tmp = it; + + list_remove_head(&timer->tasks); + if (TIMER_TASK_REPEAT == tmp->mode) { + tmp->time_label = time; + timer_add_timer_task(&timer->tasks, tmp, time); + } + it = (struct timer_task *)list_get_head(&timer->tasks); + + tmp->cb(tmp); + } +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_usart_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_usart_sync.c new file mode 100644 index 0000000000000..ccc832db85836 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_usart_sync.c @@ -0,0 +1,285 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_sync.h" +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief Initialize usart interface + */ +int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw); + init_status = _usart_sync_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_sync_read; + descr->io.write = usart_sync_write; + + return ERR_NONE; +} + +/** + * \brief Uninitialize usart interface + */ +int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_deinit(&descr->device); + + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + _usart_sync_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_sync_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_sync_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_sync_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_sync_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_sync_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_sync_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_sync_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_sync_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_sent(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) +{ + ASSERT(descr); + return _usart_sync_is_byte_received(&descr->device); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_sync_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + while (!_usart_sync_is_byte_sent(&descr->device)) + ; + do { + _usart_sync_write_byte(&descr->device, buf[offset]); + while (!_usart_sync_is_byte_sent(&descr->device)) + ; + } while (++offset < length); + + return (int32_t)offset; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint32_t offset = 0; + struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); + + ASSERT(io_descr && buf && length); + do { + while (!_usart_sync_is_byte_received(&descr->device)) + ; + buf[offset] = _usart_sync_read_byte(&descr->device); + } while (++offset < length); + + return (int32_t)offset; +} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c b/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c new file mode 100644 index 0000000000000..ad1c9361859d9 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c @@ -0,0 +1,602 @@ +/** + * \file + * + * \brief SAM USB device HAL + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hal_usb_device.h" +#include "hal_atomic.h" + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** USB device HAL driver version. */ +#define USB_D_VERSION 0x00000001u + +/** + * Endpoint callbacks for data transfer. + */ +struct usb_d_ep_callbacks { + /** Callback that is invoked when setup packet is received. */ + usb_d_ep_cb_setup_t req; + /** Callback invoked when buffer is done, but last packet is full size + * packet without ZLP. Return \c true if new transfer has been submitted. + */ + usb_d_ep_cb_more_t more; + /** Callback invoked when transfer is finished/halted/aborted or error + * occurs. + */ + usb_d_ep_cb_xfer_t xfer; +}; + +/** + * Endpoint transfer descriptor header. + */ +struct usb_ep_xfer_hdr { + /** Transfer type, reuse \ref usb_ep_type. */ + uint8_t type; + /** Endpoint address. */ + uint8_t ep; + /** Endpoint state. */ + uint8_t state; + /** Last status code. */ + uint8_t status; +}; + +/** + * Transfer descriptor. + */ +struct usb_ep_xfer { + /** General transfer descriptor. */ + struct usb_ep_xfer_hdr hdr; + /** Pointer to data buffer. */ + uint8_t *buf; + /** Transfer size. */ + uint32_t size; + /** Control request packet. */ + uint8_t req[8]; +}; + +/** + * USB device endpoint descriptor. + */ +struct usb_d_ep { + /** On-going transfer on the endpoint. */ + struct usb_ep_xfer xfer; + /** Endpoint callbacks. */ + struct usb_d_ep_callbacks callbacks; +}; + +/** + * USB device HAL driver descriptor. + */ +struct usb_d_descriptor { + /** USB device endpoints. */ + struct usb_d_ep ep[CONF_USB_D_NUM_EP_SP]; +}; + +/** The USB HAL driver descriptor instance. */ +static struct usb_d_descriptor usb_d_inst; + +/** \brief Find the endpoint. + * \param[in] ep Endpoint address. + * \return Index of endpoint descriptor. + * \retval >=0 The index. + * \retval <0 Not found (endpoint is not initialized). + */ +static int8_t _usb_d_find_ep(const uint8_t ep) +{ + int8_t i; + for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { + if (usb_d_inst.ep[i].xfer.hdr.ep == ep) { + return i; + } + if (usb_d_inst.ep[i].xfer.hdr.type == USB_EP_XTYPE_CTRL + && (ep & USB_EP_N_MASK) == usb_d_inst.ep[i].xfer.hdr.ep) { + return i; + } + } + return -1; +} + +/** + * \brief Start transactions + * \param[in] ep Endpoint address. + * \param[in] dir Endpoint transfer direction. + * \param[in] buf Pointer to transfer buffer. + * \param[in] size Transfer size. + * \param[in] zlp Auto append ZLP for IN, or wait ZLP for OUT. + */ +static inline int32_t _usb_d_trans(const uint8_t ep, const bool dir, const uint8_t *buf, const uint32_t size, + const uint8_t zlp) +{ + struct usb_d_transfer trans + = {(uint8_t *)buf, size, dir ? (uint8_t)(ep | USB_EP_DIR) : (uint8_t)(ep & USB_EP_N_MASK), zlp}; + + return _usb_d_dev_ep_trans(&trans); +} + +/** + * \brief Dummy callback that returns false + * \param[in] unused0 Unused parameter. + * \param[in] unused1 Unused parameter. + * \param[in] unused2 Unused parameter. + * \return Always \c false. + */ +static bool usb_d_dummy_cb_false(uint32_t unused0, uint32_t unused1, uint32_t unused2) +{ + (void)unused0; + (void)unused1; + (void)unused2; + return false; +} + +/** + * \brief Callback invoked when SETUP packet is ready + * \param[in] ep Endpoint number with transfer direction on bit 8. + */ +static void usb_d_cb_trans_setup(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + uint8_t * req = ept->xfer.req; + + uint8_t n = _usb_d_dev_ep_read_req(ep, req); + if (n != 8) { + _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); + _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); + return; + } + + _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); + _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_CLR); + ept->xfer.hdr.state = USB_EP_S_IDLE; + if (!ept->callbacks.req(ep, req)) { + ept->xfer.hdr.state = USB_EP_S_HALTED; + _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); + _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); + } +} + +/** + * \brief Callback invoked when request more data + * \param[in] ep Endpoint number with transfer direction on bit 8. + * \param[in] transfered Number of bytes transfered. + */ +static bool usb_d_cb_trans_more(const uint8_t ep, const uint32_t transfered) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ept->xfer.hdr.state == USB_EP_S_X_DATA) { + return ept->callbacks.more(ep, transfered); + } + return false; +} + +/** + * \brief Handles the case that control endpoint transactions are done + * \param[in,out] ept Pointer to endpoint information. + */ +static inline void usb_d_ctrl_trans_done(struct usb_d_ep *ept) +{ + uint8_t state = ept->xfer.hdr.state; + bool req_dir = USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN; + + if (state == USB_EP_S_X_DATA) { + /* Data stage -> Status stage */ + bool err = ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DATA, ept->xfer.req); + if (err) { + ept->xfer.hdr.state = USB_EP_S_HALTED; + ept->xfer.hdr.status = USB_XFER_HALT; + _usb_d_dev_ep_stall(req_dir ? ept->xfer.hdr.ep : (ept->xfer.hdr.ep | USB_EP_DIR), USB_EP_STALL_SET); + } else { + ept->xfer.hdr.state = USB_EP_S_X_STATUS; + _usb_d_trans(ept->xfer.hdr.ep, !req_dir, NULL, 0, 1); + } + } else { + /* Status stage done */ + ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DONE, ept->xfer.req); + ept->xfer.hdr.state = USB_EP_S_X_SETUP; + } +} + +/** + * Callback when USB transactions are finished. + */ +static void _usb_d_cb_trans_done(const uint8_t ep, const int32_t code, const uint32_t transferred) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + + if (code == USB_TRANS_DONE) { + ept->xfer.hdr.status = USB_XFER_DONE; + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + usb_d_ctrl_trans_done(ept); + return; + } + ept->xfer.hdr.state = USB_EP_S_IDLE; + } else if (code == USB_TRANS_STALL) { + ept->xfer.hdr.status = USB_XFER_HALT; + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + ept->xfer.hdr.state = USB_EP_S_X_SETUP; + _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); + } else { + ept->xfer.hdr.state = USB_EP_S_HALTED; + } + } else if (code == USB_TRANS_ABORT) { + ept->xfer.hdr.status = USB_XFER_ABORT; + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + ept->xfer.hdr.state = USB_EP_S_X_SETUP; + return; + } + ept->xfer.hdr.state = USB_EP_S_IDLE; + } else if (code == USB_TRANS_RESET) { + ept->xfer.hdr.state = USB_EP_S_DISABLED; + ept->xfer.hdr.status = USB_XFER_RESET; + } else { + ept->xfer.hdr.state = USB_EP_S_ERROR; + ept->xfer.hdr.status = USB_XFER_ERROR; + } + + ept->callbacks.xfer(ep, (enum usb_xfer_code)ept->xfer.hdr.status, (void *)transferred); +} + +int32_t usb_d_init(void) +{ + int32_t rc = _usb_d_dev_init(); + uint8_t i; + if (rc < 0) { + return rc; + } + memset(usb_d_inst.ep, 0x00, sizeof(struct usb_d_ep) * CONF_USB_D_NUM_EP_SP); + for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { + usb_d_inst.ep[i].xfer.hdr.ep = 0xFF; + usb_d_inst.ep[i].callbacks.req = (usb_d_ep_cb_setup_t)usb_d_dummy_cb_false; + usb_d_inst.ep[i].callbacks.more = (usb_d_ep_cb_more_t)usb_d_dummy_cb_false; + usb_d_inst.ep[i].callbacks.xfer = (usb_d_ep_cb_xfer_t)usb_d_dummy_cb_false; + } + /* Handles device driver endpoint callbacks to build transfer. */ + _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_SETUP, (FUNC_PTR)usb_d_cb_trans_setup); + _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_MORE, (FUNC_PTR)usb_d_cb_trans_more); + _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_DONE, (FUNC_PTR)_usb_d_cb_trans_done); + return ERR_NONE; +} + +void usb_d_deinit(void) +{ + _usb_d_dev_deinit(); +} + +void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) +{ + /* Directly uses device driver callback. */ + _usb_d_dev_register_callback(type, func); +} + +int32_t usb_d_enable(void) +{ + return _usb_d_dev_enable(); +} + +void usb_d_disable(void) +{ + _usb_d_dev_disable(); +} + +void usb_d_attach(void) +{ + _usb_d_dev_attach(); +} + +void usb_d_detach(void) +{ + _usb_d_dev_detach(); +} + +enum usb_speed usb_d_get_speed(void) +{ + return _usb_d_dev_get_speed(); +} + +uint16_t usb_d_get_frame_num(void) +{ + return _usb_d_dev_get_frame_n(); +} + +uint8_t usb_d_get_uframe_num(void) +{ + return _usb_d_dev_get_uframe_n(); +} + +void usb_d_set_address(const uint8_t addr) +{ + _usb_d_dev_set_address(addr); +} + +void usb_d_send_remotewakeup(void) +{ + _usb_d_dev_send_remotewakeup(); +} + +int32_t usb_d_ep0_init(const uint8_t max_pkt_size) +{ + return usb_d_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_size); +} + +int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size) +{ + int32_t rc; + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index >= 0) { + return -USB_ERR_REDO; + } else { + ep_index = _usb_d_find_ep(0xFF); + if (ep_index < 0) { + return -USB_ERR_ALLOC_FAIL; + } + ept = &usb_d_inst.ep[ep_index]; + } + rc = _usb_d_dev_ep_init(ep, attr, max_pkt_size); + if (rc < 0) { + return rc; + } + ept->xfer.hdr.ep = ep; + ept->xfer.hdr.type = attr & USB_EP_XTYPE_MASK; + return ERR_NONE; +} + +void usb_d_ep_deinit(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index < 0) { + return; + } + _usb_d_dev_ep_deinit(ep); + ept->xfer.hdr.ep = 0xFF; +} + +int32_t usb_d_ep_enable(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + int32_t rc; + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + ept->xfer.hdr.state = (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) ? USB_EP_S_X_SETUP : USB_EP_S_IDLE; + rc = _usb_d_dev_ep_enable(ep); + if (rc < 0) { + ept->xfer.hdr.state = USB_EP_S_DISABLED; + } + return rc; +} + +void usb_d_ep_disable(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index < 0) { + return; + } + _usb_d_dev_ep_disable(ep); + ept->xfer.hdr.state = USB_EP_S_DISABLED; +} + +uint8_t *usb_d_ep_get_req(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + if (ep_index < 0) { + return NULL; + } + return usb_d_inst.ep[ep_index].xfer.req; +} + +int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer) +{ + int8_t ep_index = _usb_d_find_ep(xfer->ep); + struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; + bool dir = USB_EP_GET_DIR(xfer->ep), zlp = xfer->zlp; + uint32_t len = xfer->size; + int32_t rc; + volatile uint8_t state; + volatile hal_atomic_t flags; + + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + + atomic_enter_critical(&flags); + state = ept->xfer.hdr.state; + if (state == USB_EP_S_IDLE) { + ept->xfer.hdr.state = USB_EP_S_X_DATA; + atomic_leave_critical(&flags); + } else { + atomic_leave_critical(&flags); + switch (state) { + case USB_EP_S_HALTED: + return USB_HALTED; + case USB_EP_S_ERROR: + return -USB_ERROR; + case USB_EP_S_DISABLED: + return -USB_ERR_FUNC; + default: /* USB_EP_S_X_xxxx */ + return USB_BUSY; + } + } + + if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { + uint16_t req_len = USB_GET_wLength(ept->xfer.req); + /* SETUP without data: ZLP IN as status. */ + if (req_len == 0) { + dir = true; + len = 0; + zlp = true; + ept->xfer.hdr.state = USB_EP_S_X_STATUS; + } else { + dir = (USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN); + /* Data length not exceed requested. */ + if (len > req_len) { + len = req_len; + } + if (dir) { + /* Setup -> In */ + zlp = (req_len > len); + } else { + zlp = false; + } + } + } + + rc = _usb_d_trans(xfer->ep, dir, xfer->buf, len, zlp); + return rc; +} + +void usb_d_ep_abort(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + if (ep_index < 0) { + return; + } + _usb_d_dev_ep_abort(ep); + ept->xfer.hdr.state = USB_EP_S_IDLE; + ept->xfer.hdr.status = USB_XFER_ABORT; +} + +int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; + struct usb_d_trans_status tmp; + uint8_t state = ept->xfer.hdr.state; + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + if (stat) { + /* Check transaction status if transferring data. */ + _usb_d_dev_ep_get_status(ep, &tmp); + stat->ep = ep; + stat->state = state; + stat->code = ept->xfer.hdr.status; + stat->count = tmp.count; + stat->size = tmp.size; + } + switch (state) { + case USB_EP_S_IDLE: + return USB_OK; + case USB_EP_S_HALTED: + return USB_HALTED; + case USB_EP_S_ERROR: + return -USB_ERROR; + case USB_EP_S_DISABLED: + return -USB_ERR_FUNC; + default: + /* Busy */ + return USB_BUSY; + } +} + +static inline int32_t _usb_d_ep_halt_clr(const uint8_t ep) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + int32_t rc; + if (ep_index < 0) { + return -USB_ERR_PARAM; + } + if (ept->xfer.hdr.state == USB_EP_S_HALTED) { + rc = _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); + if (rc < 0) { + return rc; + } + ept->xfer.hdr.state = USB_EP_S_IDLE; + ept->xfer.hdr.status = USB_XFER_UNHALT; + ept->callbacks.xfer(ep, USB_XFER_UNHALT, NULL); + } + return ERR_NONE; +} + +int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl) +{ + if (ctrl == USB_EP_HALT_CLR) { + return _usb_d_ep_halt_clr(ep); + } else if (ctrl == USB_EP_HALT_SET) { + return _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); + } else { + return _usb_d_dev_ep_stall(ep, USB_EP_STALL_GET); + } +} + +void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func) +{ + int8_t ep_index = _usb_d_find_ep(ep); + struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; + FUNC_PTR f = func ? (FUNC_PTR)func : (FUNC_PTR)usb_d_dummy_cb_false; + if (ep_index < 0) { + return; + } + switch (type) { + case USB_D_EP_CB_SETUP: + ept->callbacks.req = (usb_d_ep_cb_setup_t)f; + break; + case USB_D_EP_CB_MORE: + ept->callbacks.more = (usb_d_ep_cb_more_t)f; + break; + case USB_D_EP_CB_XFER: + ept->callbacks.xfer = (usb_d_ep_cb_xfer_t)f; + break; + default: + break; + } +} + +uint32_t usb_d_get_version(void) +{ + return USB_D_VERSION; +} + +#ifdef __cplusplus +} +#endif diff --git a/atmel-samd/asf4/samd51/hal/utils/include/compiler.h b/atmel-samd/asf4/samd51/hal/utils/include/compiler.h new file mode 100644 index 0000000000000..3cd654f5372b6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/compiler.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin +******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/err_codes.h b/atmel-samd/asf4/samd51/hal/utils/include/err_codes.h new file mode 100644 index 0000000000000..ebc80e58b2c38 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/err_codes.h @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/atmel-samd/asf4/samd51/hal/utils/include/events.h b/atmel-samd/asf4/samd51/hal/utils/include/events.h new file mode 100644 index 0000000000000..13c1d62db066b --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/events.h @@ -0,0 +1,64 @@ +/** +* \file +* +* \brief Events declaration. +* +* Copyright (C) 2015 Atmel Corporation. All rights reserved. +* +* \asf_license_start +* +* \page License +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of Atmel may not be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* 4. This software may only be redistributed and used in connection with an +* Atmel microcontroller product. +* +* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +* \asf_license_stop +* +*/ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/parts.h b/atmel-samd/asf4/samd51/hal/utils/include/parts.h new file mode 100644 index 0000000000000..051336ed14432 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/parts.h @@ -0,0 +1,51 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "samd51.h" + +#include "hri_d51.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils.h b/atmel-samd/asf4/samd51/hal/utils/include/utils.h new file mode 100644 index 0000000000000..1cc588ad7de61 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils.h @@ -0,0 +1,364 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + (((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) ? 0 : ((u) & (1ul << 30)) ? 1 : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) ? 6 \ + : ((u) & (1ul << 24)) ? 7 : ((u) & (1ul << 23)) ? 8 : ((u) & (1ul << 22)) ? 9 : ((u) & (1ul << 21)) ? 10 : ((u) & (1ul << 20)) ? 11 : (( \ + u) \ + & (1ul \ + << 19)) \ + ? 12 \ + : ((u) \ + & (1ul \ + << 18)) \ + ? 13 \ + : ( \ + (u) \ + & (1ul \ + << 17)) \ + ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) \ + & (1ul \ + << 15)) \ + ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 : ((u) & (1ul << 12)) ? 19 : ((u) & (1ul << 11)) ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) & (1ul << 9)) ? 22 \ + : ((u) & (1ul << 8)) ? 23 : ((u) \ + & (1ul \ + << 7)) \ + ? 24 \ + : ((u) & (1ul << 6)) ? 25 : ((u) & (1ul << 5)) ? 26 : ((u) & (1ul << 4)) ? 27 : ((u) & (1ul << 3)) ? 28 : ((u) \ + & (1ul \ + << 2)) \ + ? 29 \ + : ((u) & (1ul << 1)) ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul \ + << 14) \ + ? 14 \ + : (u) & (1ul \ + << 15) \ + ? 15 \ + : (u) & (1ul << 16) ? 16 : (u) & (1ul << 17) ? 17 : (u) & (1ul << 18) ? 18 : (u) & (1ul << 19) ? 19 : (u) & (1ul << 20) ? 20 : (u) \ + & (1ul \ + << 21) \ + ? 21 \ + : (u) & (1ul << 22) ? 22 : (u) \ + & (1ul << 23) \ + ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 : (u) & (1ul \ + << 27) \ + ? 27 \ + : (u) & (1ul \ + << 28) \ + ? 28 \ + : (u) & (1ul << 29) ? 29 \ + : (u) & (1ul << 30) ? 30 : ( \ + u) & (1ul << 31) \ + ? 31 \ + : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_assert.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_assert.h new file mode 100644 index 0000000000000..ae679e7a35691 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils_assert.h @@ -0,0 +1,103 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void asf_assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_decrement_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_decrement_macro.h new file mode 100644 index 0000000000000..b53c5da8c73c7 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils_decrement_macro.h @@ -0,0 +1,319 @@ +/** + * \file + * + * \brief Decrement macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_DECREMENT_MACRO_H +#define _UTILS_DECREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time decrement, result value is entire integer literal + * + * \param[in] val - value to be decremented + */ +#define DEC_VALUE(val) DEC_##val + +// Preprocessor increment implementation +#define DEC_256 255 +#define DEC_255 254 +#define DEC_254 253 +#define DEC_253 252 +#define DEC_252 251 +#define DEC_251 250 +#define DEC_250 249 +#define DEC_249 248 +#define DEC_248 247 +#define DEC_247 246 +#define DEC_246 245 +#define DEC_245 244 +#define DEC_244 243 +#define DEC_243 242 +#define DEC_242 241 +#define DEC_241 240 +#define DEC_240 239 +#define DEC_239 238 +#define DEC_238 237 +#define DEC_237 236 +#define DEC_236 235 +#define DEC_235 234 +#define DEC_234 233 +#define DEC_233 232 +#define DEC_232 231 +#define DEC_231 230 +#define DEC_230 229 +#define DEC_229 228 +#define DEC_228 227 +#define DEC_227 226 +#define DEC_226 225 +#define DEC_225 224 +#define DEC_224 223 +#define DEC_223 222 +#define DEC_222 221 +#define DEC_221 220 +#define DEC_220 219 +#define DEC_219 218 +#define DEC_218 217 +#define DEC_217 216 +#define DEC_216 215 +#define DEC_215 214 +#define DEC_214 213 +#define DEC_213 212 +#define DEC_212 211 +#define DEC_211 210 +#define DEC_210 209 +#define DEC_209 208 +#define DEC_208 207 +#define DEC_207 206 +#define DEC_206 205 +#define DEC_205 204 +#define DEC_204 203 +#define DEC_203 202 +#define DEC_202 201 +#define DEC_201 200 +#define DEC_200 199 +#define DEC_199 198 +#define DEC_198 197 +#define DEC_197 196 +#define DEC_196 195 +#define DEC_195 194 +#define DEC_194 193 +#define DEC_193 192 +#define DEC_192 191 +#define DEC_191 190 +#define DEC_190 189 +#define DEC_189 188 +#define DEC_188 187 +#define DEC_187 186 +#define DEC_186 185 +#define DEC_185 184 +#define DEC_184 183 +#define DEC_183 182 +#define DEC_182 181 +#define DEC_181 180 +#define DEC_180 179 +#define DEC_179 178 +#define DEC_178 177 +#define DEC_177 176 +#define DEC_176 175 +#define DEC_175 174 +#define DEC_174 173 +#define DEC_173 172 +#define DEC_172 171 +#define DEC_171 170 +#define DEC_170 169 +#define DEC_169 168 +#define DEC_168 167 +#define DEC_167 166 +#define DEC_166 165 +#define DEC_165 164 +#define DEC_164 163 +#define DEC_163 162 +#define DEC_162 161 +#define DEC_161 160 +#define DEC_160 159 +#define DEC_159 158 +#define DEC_158 157 +#define DEC_157 156 +#define DEC_156 155 +#define DEC_155 154 +#define DEC_154 153 +#define DEC_153 152 +#define DEC_152 151 +#define DEC_151 150 +#define DEC_150 149 +#define DEC_149 148 +#define DEC_148 147 +#define DEC_147 146 +#define DEC_146 145 +#define DEC_145 144 +#define DEC_144 143 +#define DEC_143 142 +#define DEC_142 141 +#define DEC_141 140 +#define DEC_140 139 +#define DEC_139 138 +#define DEC_138 137 +#define DEC_137 136 +#define DEC_136 135 +#define DEC_135 134 +#define DEC_134 133 +#define DEC_133 132 +#define DEC_132 131 +#define DEC_131 130 +#define DEC_130 129 +#define DEC_129 128 +#define DEC_128 127 +#define DEC_127 126 +#define DEC_126 125 +#define DEC_125 124 +#define DEC_124 123 +#define DEC_123 122 +#define DEC_122 121 +#define DEC_121 120 +#define DEC_120 119 +#define DEC_119 118 +#define DEC_118 117 +#define DEC_117 116 +#define DEC_116 115 +#define DEC_115 114 +#define DEC_114 113 +#define DEC_113 112 +#define DEC_112 111 +#define DEC_111 110 +#define DEC_110 109 +#define DEC_109 108 +#define DEC_108 107 +#define DEC_107 106 +#define DEC_106 105 +#define DEC_105 104 +#define DEC_104 103 +#define DEC_103 102 +#define DEC_102 101 +#define DEC_101 100 +#define DEC_100 99 +#define DEC_99 98 +#define DEC_98 97 +#define DEC_97 96 +#define DEC_96 95 +#define DEC_95 94 +#define DEC_94 93 +#define DEC_93 92 +#define DEC_92 91 +#define DEC_91 90 +#define DEC_90 89 +#define DEC_89 88 +#define DEC_88 87 +#define DEC_87 86 +#define DEC_86 85 +#define DEC_85 84 +#define DEC_84 83 +#define DEC_83 82 +#define DEC_82 81 +#define DEC_81 80 +#define DEC_80 79 +#define DEC_79 78 +#define DEC_78 77 +#define DEC_77 76 +#define DEC_76 75 +#define DEC_75 74 +#define DEC_74 73 +#define DEC_73 72 +#define DEC_72 71 +#define DEC_71 70 +#define DEC_70 69 +#define DEC_69 68 +#define DEC_68 67 +#define DEC_67 66 +#define DEC_66 65 +#define DEC_65 64 +#define DEC_64 63 +#define DEC_63 62 +#define DEC_62 61 +#define DEC_61 60 +#define DEC_60 59 +#define DEC_59 58 +#define DEC_58 57 +#define DEC_57 56 +#define DEC_56 55 +#define DEC_55 54 +#define DEC_54 53 +#define DEC_53 52 +#define DEC_52 51 +#define DEC_51 50 +#define DEC_50 49 +#define DEC_49 48 +#define DEC_48 47 +#define DEC_47 46 +#define DEC_46 45 +#define DEC_45 44 +#define DEC_44 43 +#define DEC_43 42 +#define DEC_42 41 +#define DEC_41 40 +#define DEC_40 39 +#define DEC_39 38 +#define DEC_38 37 +#define DEC_37 36 +#define DEC_36 35 +#define DEC_35 34 +#define DEC_34 33 +#define DEC_33 32 +#define DEC_32 31 +#define DEC_31 30 +#define DEC_30 29 +#define DEC_29 28 +#define DEC_28 27 +#define DEC_27 26 +#define DEC_26 25 +#define DEC_25 24 +#define DEC_24 23 +#define DEC_23 22 +#define DEC_22 21 +#define DEC_21 20 +#define DEC_20 19 +#define DEC_19 18 +#define DEC_18 17 +#define DEC_17 16 +#define DEC_16 15 +#define DEC_15 14 +#define DEC_14 13 +#define DEC_13 12 +#define DEC_12 11 +#define DEC_11 10 +#define DEC_10 9 +#define DEC_9 8 +#define DEC_8 7 +#define DEC_7 6 +#define DEC_6 5 +#define DEC_5 4 +#define DEC_4 3 +#define DEC_3 2 +#define DEC_2 1 +#define DEC_1 0 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_DECREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_event.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_event.h new file mode 100644 index 0000000000000..48d9c88d5dc79 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils_event.h @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_increment_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_increment_macro.h new file mode 100644 index 0000000000000..9bbc63ff34a0e --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,318 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_list.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_list.h new file mode 100644 index 0000000000000..8d049ff1bcd29 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils_list.h @@ -0,0 +1,174 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_recursion_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_recursion_macro.h new file mode 100644 index 0000000000000..fcc625cd95a18 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils_recursion_macro.h @@ -0,0 +1,79 @@ +/** + * \file + * + * \brief Recursion macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_RECURSION_MACRO_H +#define _UTILS_RECURSION_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Macro recursion + * + * \param[in] macro Macro to be repeated recursively + * \param[in] arg A recursive threshold, building on this to decline by times + * defined with parameter n + * \param[in] n The number of repetitious calls to macro + */ +#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg) + +#define RECURSION0(macro, arg) +#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0) +#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1) +#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2) +#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3) +#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_RECURSION_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_repeat_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 0000000000000..aeed75d5c3cf6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,332 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_assert.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_assert.c new file mode 100644 index 0000000000000..9fe56827cc909 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/src/utils_assert.c @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUFDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_event.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_event.c new file mode 100644 index 0000000000000..ab4e9eb3fa5fe --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/src/utils_event.c @@ -0,0 +1,135 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_list.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_list.c new file mode 100644 index 0000000000000..eaf5f3410e1bb --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/src/utils_list.c @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_syscalls.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_syscalls.c new file mode 100644 index 0000000000000..7adad249ab4a5 --- /dev/null +++ b/atmel-samd/asf4/samd51/hal/utils/src/utils_syscalls.c @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c new file mode 100644 index 0000000000000..89ea5f3531370 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c @@ -0,0 +1,787 @@ + +/** + * \file + * + * \brief SAM Analog Digital Converter + * + * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONF_ADC_0_ENABLE +#define CONF_ADC_0_ENABLE 0 +#endif +#ifndef CONF_ADC_1_ENABLE +#define CONF_ADC_1_ENABLE 0 +#endif + +/** + * \brief Macro is used to fill ADC configuration structure based on its number + * + * \param[in] n The number of structures + */ +#define ADC_CONFIGURATION(n) \ + { \ + (n), (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ONDEMAND << ADC_CTRLA_ONDEMAND_Pos) \ + | ADC_CTRLA_PRESCALER(CONF_ADC_##n##_PRESCALER), \ + ADC_CTRLB_RESSEL(CONF_ADC_##n##_RESSEL) | (CONF_ADC_##n##_CORREN << ADC_CTRLB_CORREN_Pos) \ + | (CONF_ADC_##n##_FREERUN << ADC_CTRLB_FREERUN_Pos) \ + | (CONF_ADC_##n##_LEFTADJ << ADC_CTRLB_LEFTADJ_Pos) | ADC_CTRLB_WINMODE(CONF_ADC_##n##_WINMODE), \ + (CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL), \ + (CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos) \ + | (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos) \ + | (CONF_ADC_##n##_STARTINV << ADC_EVCTRL_STARTINV_Pos) \ + | (CONF_ADC_##n##_FLUSHINV << ADC_EVCTRL_FLUSHINV_Pos) \ + | (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos) \ + | (CONF_ADC_##n##_FLUSHEI << ADC_EVCTRL_FLUSHEI_Pos), \ + (CONF_ADC_##n##_DIFFMODE << ADC_INPUTCTRL_DIFFMODE_Pos) | ADC_INPUTCTRL_MUXNEG(CONF_ADC_##n##_MUXNEG) \ + | ADC_INPUTCTRL_MUXPOS(CONF_ADC_##n##_MUXPOS), \ + ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM), \ + (CONF_ADC_##n##_OFFCOMP << ADC_SAMPCTRL_OFFCOMP_Pos) | ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN), \ + ADC_WINLT_WINLT(CONF_ADC_##n##_WINLT), ADC_WINUT_WINUT(CONF_ADC_##n##_WINUT), \ + ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR), \ + CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos, \ + } + +/** + * \brief ADC configuration + */ +struct adc_configuration { + uint8_t number; + hri_adc_ctrla_reg_t ctrl_a; + hri_adc_ctrlb_reg_t ctrl_b; + hri_adc_refctrl_reg_t ref_ctrl; + hri_adc_evctrl_reg_t ev_ctrl; + hri_adc_inputctrl_reg_t input_ctrl; + hri_adc_avgctrl_reg_t avg_ctrl; + hri_adc_sampctrl_reg_t samp_ctrl; + hri_adc_winlt_reg_t win_lt; + hri_adc_winut_reg_t win_ut; + hri_adc_gaincorr_reg_t gain_corr; + hri_adc_offsetcorr_reg_t offset_corr; + hri_adc_dbgctrl_reg_t dbg_ctrl; +}; + +#define ADC_AMOUNT (CONF_ADC_0_ENABLE + CONF_ADC_1_ENABLE) + +/** + * \brief Array of ADC configurations + */ +static const struct adc_configuration _adcs[] = { +#if CONF_ADC_0_ENABLE == 1 + ADC_CONFIGURATION(0), +#endif +#if CONF_ADC_1_ENABLE == 1 + ADC_CONFIGURATION(1), +#endif +}; + +static void _adc_set_reference_source(void *const hw, const adc_reference_t reference); + +/** + * \brief Retrieve ordinal number of the given adc hardware instance + */ +static uint8_t _adc_get_hardware_index(const void *const hw) +{ + return ((uint32_t)hw - (uint32_t)ADC0) >> 10; +} + +/** \brief Return the pointer to register settings of specific ADC + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific ADC. + */ +static uint8_t _adc_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _adc_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) { + if (_adcs[i].number == n) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device) +{ + + return ADC0_0_IRQn + (_adc_get_hardware_index(device->hw) << 1); +} + +/** + * \brief Init irq param with the given afec hardware instance + */ +static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev) +{ +} + +/** + * \brief Initialize ADC + * + * \param[in] hw The pointer to hardware instance + * \param[in] i The number of hardware instance + */ +static int32_t _adc_init(void *const hw, const uint8_t i) +{ + + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + if (hri_adc_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_adc_set_CTRLA_SWRST_bit(hw); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + + hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b); + hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl); + hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl); + hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl); + hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl); + hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl); + hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt); + hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut); + hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr); + hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr); + hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl); + hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a); + + return ERR_NONE; +} + +/** + * \brief De-initialize ADC + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _adc_deinit(void *hw) +{ + hri_adc_clear_CTRLA_ENABLE_bit(hw); + hri_adc_set_CTRLA_SWRST_bit(hw); +} + +/** + * \brief Initialize ADC + */ +int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _adc_init(hw, _adc_get_regs((uint32_t)hw)); +} + +/** + * \brief Initialize ADC + */ +int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw) +{ + int32_t init_status; + uint8_t i = _adc_get_regs((uint32_t)hw); + + ASSERT(device); + + init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw)); + if (init_status) { + return init_status; + } + device->hw = hw; + _adc_init_irq_param(hw, device); + NVIC_DisableIRQ(_adc_get_irq_num(device) + 0); + NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 0); + NVIC_EnableIRQ(_adc_get_irq_num(device) + 0); + NVIC_DisableIRQ(_adc_get_irq_num(device) + 1); + NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 1); + NVIC_EnableIRQ(_adc_get_irq_num(device) + 1); + return ERR_NONE; +} + +/** + * \brief Initialize ADC + */ +int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _adc_init(hw, _adc_get_regs((uint32_t)hw)); +} + +/** + * \brief De-initialize ADC + */ +void _adc_sync_deinit(struct _adc_sync_device *const device) +{ + _adc_deinit(device->hw); +} + +/** + * \brief De-initialize ADC + */ +void _adc_async_deinit(struct _adc_async_device *const device) +{ + NVIC_DisableIRQ(_adc_get_irq_num(device)); + NVIC_ClearPendingIRQ(_adc_get_irq_num(device)); + + _adc_deinit(device->hw); +} + +/** + * \brief De-initialize ADC + */ +void _adc_dma_deinit(struct _adc_dma_device *const device) +{ + _adc_deinit(device->hw); +} + +/** + * \brief Enable ADC + */ +void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable ADC + */ +void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable ADC + */ +void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable ADC + */ +void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable ADC + */ +void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable ADC + */ +void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel) +{ + (void)channel; + + hri_adc_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Return address of ADC DMA source + */ +uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device) +{ + return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg); +} + +/** + * \brief Retrieve ADC conversion data size + */ +uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device) +{ + return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; +} + +/** + * \brief Retrieve ADC conversion data size + */ +uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device) +{ + return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; +} + +/** + * \brief Retrieve ADC conversion data size + */ +uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device) +{ + return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; +} + +/** + * \brief Check if conversion is done + */ +bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_get_interrupt_RESRDY_bit(device->hw); +} + +/** + * \brief Check if conversion is done + */ +bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_get_interrupt_RESRDY_bit(device->hw); +} + +/** + * \brief Check if conversion is done + */ +bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device) +{ + return hri_adc_get_interrupt_RESRDY_bit(device->hw); +} + +/** + * \brief Make conversion + */ +void _adc_sync_convert(struct _adc_sync_device *const device) +{ + hri_adc_set_SWTRIG_START_bit(device->hw); +} + +/** + * \brief Make conversion + */ +void _adc_async_convert(struct _adc_async_device *const device) +{ + hri_adc_set_SWTRIG_START_bit(device->hw); +} + +/** + * \brief Make conversion + */ +void _adc_dma_convert(struct _adc_dma_device *const device) +{ + hri_adc_set_SWTRIG_START_bit(device->hw); +} + +/** + * \brief Retrieve the conversion result + */ +uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_read_RESULT_reg(device->hw); +} + +/** + * \brief Retrieve the conversion result + */ +uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel) +{ + (void)channel; + + return hri_adc_read_RESULT_reg(device->hw); +} + +/** + * \brief Set reference source + */ +void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference) +{ + _adc_set_reference_source(device->hw, reference); +} + +/** + * \brief Set reference source + */ +void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference) +{ + _adc_set_reference_source(device->hw, reference); +} + +/** + * \brief Set reference source + */ +void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference) +{ + _adc_set_reference_source(device->hw, reference); +} + +/** + * \brief Set resolution + */ +void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution) +{ + hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); +} + +/** + * \brief Set resolution + */ +void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution) +{ + hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); +} + +/** + * \brief Set resolution + */ +void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution) +{ + hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); +} + +/** + * \brief Set channels input sources + */ +void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); + hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); +} + +/** + * \brief Set channels input sources + */ +void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); + hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); +} + +/** + * \brief Set channels input source + */ +void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, + const adc_neg_input_t neg_input, const uint8_t channel) +{ + (void)channel; + + hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); + hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); +} + +/** + * \brief Set thresholds + */ +void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + hri_adc_write_WINLT_reg(device->hw, low_threshold); + hri_adc_write_WINUT_reg(device->hw, up_threshold); +} + +/** + * \brief Set thresholds + */ +void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + hri_adc_write_WINLT_reg(device->hw, low_threshold); + hri_adc_write_WINUT_reg(device->hw, up_threshold); +} + +/** + * \brief Set thresholds + */ +void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, + const adc_threshold_t up_threshold) +{ + hri_adc_write_WINLT_reg(device->hw, low_threshold); + hri_adc_write_WINUT_reg(device->hw, up_threshold); +} + +/** + * \brief Set gain + */ +void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain) +{ + (void)device, (void)channel, (void)gain; +} + +/** + * \brief Set gain + */ +void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain) +{ + (void)device, (void)channel, (void)gain; +} + +/** + * \brief Set gain + */ +void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain) +{ + (void)device, (void)channel, (void)gain; +} + +/** + * \brief Set conversion mode + */ +void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode) +{ + if (ADC_CONVERSION_MODE_FREERUN == mode) { + hri_adc_set_CTRLB_FREERUN_bit(device->hw); + } else { + hri_adc_clear_CTRLB_FREERUN_bit(device->hw); + } +} + +/** + * \brief Set conversion mode + */ +void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode) +{ + if (ADC_CONVERSION_MODE_FREERUN == mode) { + hri_adc_set_CTRLB_FREERUN_bit(device->hw); + } else { + hri_adc_clear_CTRLB_FREERUN_bit(device->hw); + } +} + +/** + * \brief Set conversion mode + */ +void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode) +{ + if (ADC_CONVERSION_MODE_FREERUN == mode) { + hri_adc_set_CTRLB_FREERUN_bit(device->hw); + } else { + hri_adc_clear_CTRLB_FREERUN_bit(device->hw); + } +} + +/** + * \brief Set differential mode + */ +void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, + const enum adc_differential_mode mode) +{ + (void)channel; + + if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { + hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw); + } else { + hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw); + } +} + +/** + * \brief Set differential mode + */ +void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, + const enum adc_differential_mode mode) +{ + (void)channel; + + if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { + hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw); + } else { + hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw); + } +} + +/** + * \brief Set differential mode + */ +void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, + const enum adc_differential_mode mode) +{ + (void)channel; + + if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { + hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw); + } else { + hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw); + } +} + +/** + * \brief Set window mode + */ +void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode) +{ + hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode); +} + +/** + * \brief Set window mode + */ +void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode) +{ + hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode); +} + +/** + * \brief Set window mode + */ +void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode) +{ + hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode); +} + +/** + * \brief Retrieve threshold state + */ +void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state) +{ + *state = hri_adc_get_interrupt_WINMON_bit(device->hw); +} + +/** + * \brief Retrieve threshold state + */ +void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state) +{ + *state = hri_adc_get_interrupt_WINMON_bit(device->hw); +} + +/** + * \brief Retrieve threshold state + */ +void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state) +{ + *state = hri_adc_get_interrupt_WINMON_bit(device->hw); +} + +/** + * \brief Enable/disable ADC channel interrupt + */ +void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, + const enum _adc_async_callback_type type, const bool state) +{ + (void)channel; + + void *const hw = device->hw; + + if (ADC_ASYNC_DEVICE_MONITOR_CB == type) { + hri_adc_write_INTEN_WINMON_bit(hw, state); + } else if (ADC_ASYNC_DEVICE_ERROR_CB == type) { + hri_adc_write_INTEN_OVERRUN_bit(hw, state); + } else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) { + hri_adc_write_INTEN_RESRDY_bit(hw, state); + } +} + +/** + * \internal ADC interrupt handler + * + * \param[in] p The pointer to interrupt parameter + */ +static void _adc_interrupt_handler(struct _adc_async_device *device) +{ + void *const hw = device->hw; + + if (hri_adc_get_interrupt_RESRDY_bit(hw)) { + hri_adc_clear_interrupt_RESRDY_bit(hw); + device->adc_async_ch_cb.convert_done(device, 0, hri_adc_read_RESULT_reg(hw)); + } else if (hri_adc_get_interrupt_OVERRUN_bit(hw)) { + hri_adc_clear_interrupt_OVERRUN_bit(hw); + device->adc_async_cb.error_cb(device, 0); + } else if (hri_adc_get_interrupt_WINMON_bit(hw)) { + hri_adc_clear_interrupt_WINMON_bit(hw); + device->adc_async_cb.window_cb(device, 0); + } +} + +/** + * \brief Retrieve ADC sync helper functions + */ +void *_adc_get_adc_sync(void) +{ + return (void *)NULL; +} + +/** + * \brief Retrieve ADC async helper functions + */ +void *_adc_get_adc_async(void) +{ + return (void *)NULL; +} + +/** + * \brief Set ADC reference source + * + * \param[in] hw The pointer to hardware instance + * \param[in] reference The reference to set + */ +static void _adc_set_reference_source(void *const hw, const adc_reference_t reference) +{ + bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); + + hri_adc_clear_CTRLA_ENABLE_bit(hw); + hri_adc_write_REFCTRL_REFSEL_bf(hw, reference); + + if (enabled) { + hri_adc_set_CTRLA_ENABLE_bit(hw); + } +} diff --git a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc_base.h b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc_base.h new file mode 100644 index 0000000000000..2f9a333c90829 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc_base.h @@ -0,0 +1,82 @@ +/** + * \file + * + * \brief ADC related functionality declaration. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_ADC_ADC_H_INCLUDED +#define _HPL_ADC_ADC_H_INCLUDED + +#include +#include + +/** + * \addtogroup HPL ADC + * + * \section hpl_adc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve ADC helper functions + * + * \return A pointer to set of ADC helper functions + */ +void *_adc_get_adc_sync(void); +void *_adc_get_adc_async(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_UART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/core/hpl_core_m4.c b/atmel-samd/asf4/samd51/hpl/core/hpl_core_m4.c new file mode 100644 index 0000000000000..cea8d7c3c3356 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/core/hpl_core_m4.c @@ -0,0 +1,213 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#elif CONF_CPU_FREQUENCY < 1000000000 +#define CPU_FREQ_POWER 9 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (us * (freq / 1000000) - 1) + 1; + case 8: + return (us * (freq / 100000) - 1) / 10 + 1; + case 7: + return (us * (freq / 10000) - 1) / 100 + 1; + case 6: + return (us * (freq / 1000) - 1) / 1000 + 1; + case 5: + return (us * (freq / 100) - 1) / 10000 + 1; + case 4: + return (us * (freq / 10) - 1) / 100000 + 1; + default: + return (us * freq - 1) / 1000000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (ms * (freq / 1000000)) * 1000; + case 8: + return (ms * (freq / 100000)) * 100; + case 7: + return (ms * (freq / 10000)) * 10; + case 6: + return (ms * (freq / 1000)); + case 5: + return (ms * (freq / 100) - 1) / 10 + 1; + case 4: + return (ms * (freq / 10) - 1) / 100 + 1; + default: + return (ms * freq - 1) / 1000 + 1; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} diff --git a/atmel-samd/asf4/samd51/hpl/core/hpl_core_port.h b/atmel-samd/asf4/samd51/hpl/core/hpl_core_port.h new file mode 100644 index 0000000000000..b068af8397c49 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/core/hpl_core_port.h @@ -0,0 +1,71 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (C) 2015 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/core/hpl_init.c b/atmel-samd/asf4/samd51/hpl/core/hpl_init.c new file mode 100644 index 0000000000000..87c277b2bf542 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/core/hpl_init.c @@ -0,0 +1,69 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#include +#include + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + + hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); + _gclk_init_generators(); + _oscctrl_init_referenced_generators(); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif +} diff --git a/atmel-samd/asf4/samd51/hpl/dac/hpl_dac.c b/atmel-samd/asf4/samd51/hpl/dac/hpl_dac.c new file mode 100644 index 0000000000000..411f4f5e98b4a --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/dac/hpl_dac.c @@ -0,0 +1,326 @@ + +/** +* \file +* +* \brief SAM Digital to Analog Converter +* +* Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. +* +* \asf_license_start +* +* \page License +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions are met: +* +* 1. Redistributions of source code must retain the above copyright notice, +* this list of conditions and the following disclaimer. +* +* 2. Redistributions in binary form must reproduce the above copyright notice, +* this list of conditions and the following disclaimer in the documentation +* and/or other materials provided with the distribution. +* +* 3. The name of Atmel may not be used to endorse or promote products derived +* from this software without specific prior written permission. +* +* 4. This software may only be redistributed and used in connection with an +* Atmel microcontroller product. +* +* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED +* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +* DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS +* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* +* \asf_license_stop +* +*/ + +#include +#include +#include +#include + +/** \conf INTERNAL */ +static int32_t _dac_init(void *const hw); +static inline void _dac_deinit(void *const hw); +static inline void _dac_enable_channel(void *const hw, const uint8_t ch); +static inline void _dac_disable_channel(void *const hw, const uint8_t ch); +static inline bool _dac_is_channel_enabled(void *const hw, const uint8_t ch); +/** \endcond */ + +/** + * \brief DAC configuration type + */ +struct dac_configuration { + hri_dac_ctrlb_reg_t ctrlb; + hri_dac_evctrl_reg_t ev_ctrl; + hri_dac_dacctrl_reg_t dac_ctrl0; + hri_dac_dacctrl_reg_t dac_ctrl1; + hri_dac_dbgctrl_reg_t dbg_ctrl; +}; + +/** + * \brief Array of DAC configurations + */ +static struct dac_configuration _dac + = {(CONF_DAC_DIFF << DAC_CTRLB_DIFF_Pos) | DAC_CTRLB_REFSEL(CONF_DAC_REFSEL), + (CONF_DAC_INVEI0 << DAC_EVCTRL_INVEI0_Pos) | (CONF_DAC_EMPTYEO0 << DAC_EVCTRL_EMPTYEO0_Pos) + | (CONF_DAC_STARTEI0 << DAC_EVCTRL_STARTEI0_Pos) + | (CONF_DAC_INVEI1 << DAC_EVCTRL_INVEI1_Pos) + | (CONF_DAC_EMPTYEO1 << DAC_EVCTRL_EMPTYEO1_Pos) + | (CONF_DAC_STARTEI1 << DAC_EVCTRL_STARTEI1_Pos), + (CONF_DAC0_LEFTADJ << DAC_DACCTRL_LEFTADJ_Pos) | DAC_DACCTRL_CCTRL(CONF_DAC0_CCTRL) + | (CONF_DAC0_RUNSTDBY << DAC_DACCTRL_RUNSTDBY_Pos) + | (CONF_DAC0_DITHER << DAC_DACCTRL_DITHER_Pos) + | (CONF_DAC0_REFRESH << DAC_DACCTRL_REFRESH_Pos), + (CONF_DAC1_LEFTADJ << DAC_DACCTRL_LEFTADJ_Pos) | DAC_DACCTRL_CCTRL(CONF_DAC1_CCTRL) + | (CONF_DAC1_RUNSTDBY << DAC_DACCTRL_RUNSTDBY_Pos) + | (CONF_DAC1_DITHER << DAC_DACCTRL_DITHER_Pos) + | (CONF_DAC1_REFRESH << DAC_DACCTRL_REFRESH_Pos), + (CONF_DAC_DBGRUN << DAC_DBGCTRL_DBGRUN_Pos)}; + +/*!< Pointer to hpl device */ +static struct _dac_async_device *_dac_dev = NULL; + +/** + * \brief Initialize synchronous DAC + */ +int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _dac_init(device->hw); +} + +/** +* \brief Initialize DAC +*/ +int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _dac_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + + _dac_dev = device; + NVIC_DisableIRQ(DAC_0_IRQn + 0); + NVIC_ClearPendingIRQ(DAC_0_IRQn + 0); + NVIC_EnableIRQ(DAC_0_IRQn + 0); + NVIC_DisableIRQ(DAC_0_IRQn + 1); + NVIC_ClearPendingIRQ(DAC_0_IRQn + 1); + NVIC_EnableIRQ(DAC_0_IRQn + 1); + NVIC_DisableIRQ(DAC_0_IRQn + 2); + NVIC_ClearPendingIRQ(DAC_0_IRQn + 2); + NVIC_EnableIRQ(DAC_0_IRQn + 2); + + return ERR_NONE; +} + +/** + * \brief De-initialize DAC + */ +void _dac_sync_deinit(struct _dac_sync_device *const device) +{ + _dac_deinit(device->hw); +} + +/** + * \brief De-initialize DAC + */ +void _dac_async_deinit(struct _dac_async_device *const device) +{ + NVIC_DisableIRQ(DAC_0_IRQn + 0); + NVIC_DisableIRQ(DAC_0_IRQn + 1); + NVIC_DisableIRQ(DAC_0_IRQn + 2); + + _dac_deinit(device->hw); +} + +/** + * \brief Enable DAC Channel + */ +void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch) +{ + _dac_enable_channel(device->hw, ch); +} + +/** + * \brief Enable DAC Channel + */ +void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch) +{ + _dac_enable_channel(device->hw, ch); +} + +/** + * \brief Disable DAC Channel + */ +void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch) +{ + _dac_disable_channel(device->hw, ch); +} + +/** + * \brief Disable DAC Channel + */ +void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch) +{ + _dac_disable_channel(device->hw, ch); +} + +/** + * \brief Checks if DAC channel is enabled + */ +bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch) +{ + return _dac_is_channel_enabled(device->hw, ch); +} + +/** + * \brief Checks if DAC channel is enabled + */ +bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch) +{ + return _dac_is_channel_enabled(device->hw, ch); +} + +/** + * \brief write synchronous DAC data for output + */ +void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch) +{ + hri_dac_write_DATA_reg(device->hw, ch, data); +} + +/** + * \brief write DAC data for output + */ +void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch) +{ + hri_dac_write_DATABUF_reg(device->hw, ch, data); +} + +/** + * \brief Enable/disable DAC interrupt + */ +void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, + const bool state) +{ + void *hw = device->hw; + + if (DAC_DEVICE_CONVERSION_DONE_CB == type) { + hri_dac_write_INTEN_EMPTY0_bit(hw, state); + hri_dac_write_INTEN_EMPTY1_bit(hw, state); + } else if (DAC_DEVICE_ERROR_CB == type) { + hri_dac_write_INTEN_UNDERRUN0_bit(hw, state); + hri_dac_write_INTEN_UNDERRUN1_bit(hw, state); + } +} + +/** + * \internal Initialize DAC + * + * \param[in] hw The pointer to DAC hardware instance + * + * \return The status of initialization + */ +static int32_t _dac_init(void *const hw) +{ + ASSERT(hw == DAC); + + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + if (hri_dac_get_CTRLA_ENABLE_bit(hw)) { + return ERR_BUSY; + } + hri_dac_set_CTRLA_SWRST_bit(hw); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + + hri_dac_write_CTRLB_reg(hw, _dac.ctrlb); + hri_dac_write_EVCTRL_reg(hw, _dac.ev_ctrl); + hri_dac_write_DACCTRL_reg(hw, 0, _dac.dac_ctrl0); + hri_dac_write_DACCTRL_reg(hw, 1, _dac.dac_ctrl1); + hri_dac_write_DBGCTRL_reg(hw, _dac.dbg_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize DAC + * + * \param[in] hw The pointer to DAC hardware instance + */ +static inline void _dac_deinit(void *const hw) +{ + hri_dac_clear_CTRLA_ENABLE_bit(hw); + hri_dac_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Enable DAC channel + * + * \param[in] hw The pointer to hardware instance + * \param[in] ch The channel to enable + */ +static inline void _dac_enable_channel(void *const hw, const uint8_t ch) +{ + ASSERT(ch <= 1); + + hri_dac_clear_CTRLA_ENABLE_bit(hw); + hri_dac_set_DACCTRL_ENABLE_bit(hw, ch); + hri_dac_set_CTRLA_ENABLE_bit(hw); + + if (0 == ch) { + while (!hri_dac_get_STATUS_READY0_bit(hw)) + ; + } else { + while (!hri_dac_get_STATUS_READY1_bit(hw)) + ; + } +} + +/** + * \internal Disable DAC channel + * + * \param[in] hw The pointer to hardware instance + * \param[in] ch The channel to disable + */ +static inline void _dac_disable_channel(void *const hw, const uint8_t ch) +{ + ASSERT(ch <= 1); + + hri_dac_clear_CTRLA_ENABLE_bit(hw); + hri_dac_clear_DACCTRL_ENABLE_bit(hw, ch); + + if (hri_dac_get_DACCTRL_ENABLE_bit(hw, !ch)) { + hri_dac_set_CTRLA_ENABLE_bit(hw); + } +} + +/** + * \internal Checks if DAC channel is enabled + * + * \param[in] hw The pointer to hardware instance + * \param[in] ch The channel to check + */ +static inline bool _dac_is_channel_enabled(void *const hw, const uint8_t ch) +{ + if (ch <= 1) { + return hri_dac_get_DACCTRL_ENABLE_bit(hw, ch); + } + + return false; +} diff --git a/atmel-samd/asf4/samd51/hpl/dmac/hpl_dmac.c b/atmel-samd/asf4/samd51/hpl/dmac/hpl_dmac.c new file mode 100644 index 0000000000000..9a6602eb3daa3 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/dmac/hpl_dmac.c @@ -0,0 +1,262 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +static DmacDescriptor _descriptor_section[DMAC_CH_NUM]; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +static DmacDescriptor _write_back_section[DMAC_CH_NUM]; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* DMAC interrupt handler */ +static void _dmac_handler(void); + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ + | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ + DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ + (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ + | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) \ + | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) \ + | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint32_t ctrla; + uint8_t prilvl; + uint8_t evctrl; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); + hri_dmac_set_CTRL_SWRST_bit(DMAC); + while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) + ; + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_PRICTRL0_reg(DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) + | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) + | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) + | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (i = 0; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); + hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); + hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + } + + for (i = 0; i < 5; i++) { + NVIC_DisableIRQ(DMAC_0_IRQn + i); + NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); + NVIC_EnableIRQ(DMAC_0_IRQn + i); + } + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); + + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +/** + * \internal DMAC interrupt handler + */ +static void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); + struct _dma_resource *tmp_resource = &_resources[channel]; + + if (hri_dmac_get_CHINTFLAG_TERR_bit(DMAC, channel)) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); + tmp_resource->dma_cb.error(tmp_resource); + } else if (hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC, channel)) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} +/** +* \brief DMAC interrupt handler +*/ +void DMAC_0_Handler(void) +{ + _dmac_handler(); +} +/** +* \brief DMAC interrupt handler +*/ +void DMAC_1_Handler(void) +{ + _dmac_handler(); +} +/** +* \brief DMAC interrupt handler +*/ +void DMAC_2_Handler(void) +{ + _dmac_handler(); +} +/** +* \brief DMAC interrupt handler +*/ +void DMAC_3_Handler(void) +{ + _dmac_handler(); +} +/** +* \brief DMAC interrupt handler +*/ +void DMAC_4_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/atmel-samd/asf4/samd51/hpl/evsys/hpl_evsys.c b/atmel-samd/asf4/samd51/hpl/evsys/hpl_evsys.c new file mode 100644 index 0000000000000..024d2452716f1 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/evsys/hpl_evsys.c @@ -0,0 +1,151 @@ + +/** + * \file + * + * \brief EVSYS related functionality implementation. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +/* Stub macros for reserved channel */ +#define CONF_CHANNEL_38 0 +#define CONF_ONDEMAND_38 0 +#define CONF_RUNSTDBY_38 0 +#define CONF_EDGSEL_38 0 +#define CONF_PATH_38 0 +#define CONF_EVGEN_38 0 + +#define CONF_CHANNEL_39 0 +#define CONF_ONDEMAND_39 0 +#define CONF_RUNSTDBY_39 0 +#define CONF_EDGSEL_39 0 +#define CONF_PATH_39 0 +#define CONF_EVGEN_39 0 + +#define CONF_CHANNEL_113 0 +#define CONF_ONDEMAND_113 0 +#define CONF_RUNSTDBY_113 0 +#define CONF_EDGSEL_113 0 +#define CONF_PATH_113 0 +#define CONF_EVGEN_113 0 + +/* Event user configuration */ +#define USER_MUX_CONF(i, n) EVSYS_USER_CHANNEL(CONF_CHANNEL_##n), + +/* This macro is used for repeat macro: i - unused, n - amount of channels. + * It contains channel configuration. */ +#define CHANNEL_CONF(i, n) \ + (CONF_ONDEMAND_##n << EVSYS_CHANNEL_ONDEMAND_Pos) | (CONF_RUNSTDBY_##n << EVSYS_CHANNEL_RUNSTDBY_Pos) \ + | EVSYS_CHANNEL_EDGSEL(CONF_EDGSEL_##n) | EVSYS_CHANNEL_PATH(CONF_PATH_##n) \ + | EVSYS_CHANNEL_EVGEN(CONF_EVGEN_##n), + +/* This macro is used for repeat macro: i - unused, n - amount of channels + * It contains interrupts configuration. */ +#define INT_CFG(i, n) (CONF_OVR_##n << EVSYS_CHINTFLAG_OVR_Pos) | (CONF_EVD_##n << EVSYS_CHINTFLAG_EVD_Pos), + +static const uint8_t user_mux_confs[] = {REPEAT_MACRO(USER_MUX_CONF, i, EVSYS_USERS)}; + +static const uint16_t channel_confs[] = {REPEAT_MACRO(CHANNEL_CONF, i, EVSYS_CHANNELS)}; + +static const uint32_t interrupt_cfg[] = {REPEAT_MACRO(INT_CFG, i, EVSYS_CHANNELS)}; + +/** + * \brief Initialize event system + */ +int32_t _event_system_init(void) +{ + uint8_t i; + + /* configure user multiplexers */ + for (i = 0; i < EVSYS_USERS; i++) { + hri_evsys_write_USER_reg(EVSYS, i, user_mux_confs[i]); + } + + /* configure channels */ + for (i = 0; i < EVSYS_CHANNELS; i++) { + hri_evsys_write_CHANNEL_reg(EVSYS, i, channel_confs[i]); + hri_evsys_write_CHINTEN_reg(EVSYS, i, interrupt_cfg[i]); + } + + return ERR_NONE; +} + +/** + * \brief De-initialize event system. + */ +int32_t _event_system_deinit() +{ + hri_evsys_write_CTRLA_reg(EVSYS, EVSYS_CTRLA_SWRST); + + return ERR_NONE; +} + +/** + * \brief Enable/disable event reception by the given user from the given + * channel + */ +int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on) +{ + if (on) { + hri_evsys_write_USER_reg(EVSYS, user, channel); + } else { + hri_evsys_write_USER_reg(EVSYS, user, 0); + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable event generation by the given generator for the given + * channel + */ +int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on) +{ + if (on) { + hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, generator); + } else { + hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, 0); + } + + return ERR_NONE; +} diff --git a/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk.c b/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk.c new file mode 100644 index 0000000000000..d022c24f981ec --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk.c @@ -0,0 +1,200 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GEN_0_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) + | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_0_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_0_SOURCE); +#endif +#if CONF_GCLK_GEN_1_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) + | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_1_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_1_SOURCE); +#endif +#if CONF_GCLK_GEN_2_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) + | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_2_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_2_SOURCE); +#endif +#if CONF_GCLK_GEN_3_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) + | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_3_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_3_SOURCE); +#endif +#if CONF_GCLK_GEN_4_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) + | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_4_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_4_SOURCE); +#endif +#if CONF_GCLK_GEN_5_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) + | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_5_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_5_SOURCE); +#endif +#if CONF_GCLK_GEN_6_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) + | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_6_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_6_SOURCE); +#endif +#if CONF_GCLK_GEN_7_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) + | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_7_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_7_SOURCE); +#endif +#if CONF_GCLK_GEN_8_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) + | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_8_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_8_SOURCE); +#endif +#if CONF_GCLK_GEN_9_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) + | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_9_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_9_SOURCE); +#endif +#if CONF_GCLK_GEN_10_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) + | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_10_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_10_SOURCE); +#endif +#if CONF_GCLK_GEN_11_GENEN == 1 + hri_gclk_write_GENCTRL_reg(GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) + | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) + | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) + | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GEN_11_GENEN << GCLK_GENCTRL_GENEN_Pos) + | CONF_GCLK_GEN_11_SOURCE); +#endif +} diff --git a/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk_base.h b/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 0000000000000..701a038876017 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,90 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (C) 2014 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/mclk/hpl_mclk.c b/atmel-samd/asf4/samd51/hpl/mclk/hpl_mclk.c new file mode 100644 index 0000000000000..0788a40c0bd9f --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/mclk/hpl_mclk.c @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); +} diff --git a/atmel-samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c b/atmel-samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 0000000000000..99ed873b4efc1 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,94 @@ + +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg(hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) + | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) + | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) + | +#ifdef CONF_XOSC32K_CGM + OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | +#endif + (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSCULP32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#endif + + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/atmel-samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c b/atmel-samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 0000000000000..83f00dceb0247 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,244 @@ + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC0_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg(hw, + 0, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) + | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) + | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) + | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (CONF_XOSC0_ENALC << OSCCTRL_XOSCCTRL_ENALC_Pos) + | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) + | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (CONF_XOSC0_ONDEMAND << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) + | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) + | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC0_CONFIG == 1 +#if CONF_XOSC0_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) + ; +#endif +#if CONF_XOSC0_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_XOSC1_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg(hw, + 1, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) + | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) + | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) + | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (CONF_XOSC1_ENALC << OSCCTRL_XOSCCTRL_ENALC_Pos) + | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) + | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (CONF_XOSC1_ONDEMAND << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) + | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) + | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC1_CONFIG == 1 +#if CONF_XOSC1_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) + ; +#endif +#if CONF_XOSC1_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); +#endif +#endif + + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_DFLL_CONFIG == 1 + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); + uint8_t tmp; + hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) + ; + + hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; + + tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; + hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); + while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) + ; + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) + | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) + | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; + hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg(hw, + 0, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) + | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) + | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) + | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) + | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 0, + (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg(hw, + 1, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) + | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) + | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) + | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) + | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 1, + (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) + ; +#endif +#if CONF_FDPLL0_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) + ; +#endif +#if CONF_FDPLL1_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); +#endif + (void)hw; +} diff --git a/atmel-samd/asf4/samd51/hpl/pm/hpl_pm.c b/atmel-samd/asf4/samd51/hpl/pm/hpl_pm.c new file mode 100644 index 0000000000000..a46500e4a007c --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/pm/hpl_pm.c @@ -0,0 +1,65 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + switch (mode) { + case 2: + case 4: + case 5: + case 6: + hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} diff --git a/atmel-samd/asf4/samd51/hpl/pm/hpl_pm_base.h b/atmel-samd/asf4/samd51/hpl/pm/hpl_pm_base.h new file mode 100644 index 0000000000000..34b044d7c67a7 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/pm/hpl_pm_base.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distributionn. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/port/hpl_gpio_base.h b/atmel-samd/asf4/samd51/hpl/port/hpl_gpio_base.h new file mode 100644 index 0000000000000..5ea315af3c1d3 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/port/hpl_gpio_base.h @@ -0,0 +1,172 @@ +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT, port, mask); + } else { + hri_port_clear_OUT_reg(PORT, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} diff --git a/atmel-samd/asf4/samd51/hpl/ramecc/hpl_ramecc.c b/atmel-samd/asf4/samd51/hpl/ramecc/hpl_ramecc.c new file mode 100644 index 0000000000000..c4daec518e75e --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/ramecc/hpl_ramecc.c @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Generic RAMECC related functionality. + * + * Copyright (C) 2016 -2107 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/* RAMECC device descriptor */ +struct _ramecc_device device; + +/** + * \brief Initialize RAMECC + */ +int32_t _ramecc_init(void) +{ + if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { + return ERR_ABORTED; + } + + NVIC_DisableIRQ(RAMECC_IRQn); + NVIC_ClearPendingIRQ(RAMECC_IRQn); + NVIC_EnableIRQ(RAMECC_IRQn); + + return ERR_NONE; +} + +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) +{ + if (RAMECC_DUAL_ERROR_CB == type) { + device.ramecc_cb.dual_bit_err = cb; + hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); + } else if (RAMECC_SINGLE_ERROR_CB == type) { + device.ramecc_cb.single_bit_err = cb; + hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); + } +} + +/** + * \internal RAMECC interrupt handler + */ +void RAMECC_Handler(void) +{ + struct _ramecc_device *dev = (struct _ramecc_device *)&device; + volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); + + if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { + dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { + dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else { + return; + } +} diff --git a/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc.c b/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc.c new file mode 100644 index 0000000000000..6ef8a96ee6d06 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc.c @@ -0,0 +1,193 @@ + +/** + * \file + * + * \brief RTC Driver + * + * Copyright (C) 2014 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +/*!< Pointer to hpl device */ + +static struct _timer_device *_rtc_dev = NULL; + +/** + * \brief Initialize Timer + */ +int32_t _timer_init(struct _timer_device *const dev, void *const hw) +{ + ASSERT(dev); + + dev->hw = hw; + + hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST); + hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST); + +#if CONF_RTC_EVENT_CONTROL_ENABLE == 1 + hri_rtcmode0_write_EVCTRL_reg(dev->hw, + (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos) + | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos) + | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos) + | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos) + | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) + | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos) + | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) + | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos) + | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) + | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos) + | (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos) + | (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) + | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos)); +#endif + + hri_rtcmode0_write_CTRLA_reg( + dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC | RTC_MODE0_CTRLA_MATCHCLR); + hri_rtcmode0_write_COMP_reg(dev->hw, 0, CONF_RTC_COMP_VAL); + hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw); + + _rtc_dev = dev; + + return ERR_NONE; +} + +/** + * \brief De-initialize Timer + */ +void _timer_deinit(struct _timer_device *const dev) +{ + ASSERT(dev && dev->hw); + + NVIC_DisableIRQ(RTC_IRQn); + + hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST); +} + +/** + * \brief Start hardware timer + */ +void _timer_start(struct _timer_device *const dev) +{ + ASSERT(dev && dev->hw); + + NVIC_EnableIRQ(RTC_IRQn); + hri_rtcmode0_write_COUNT_reg(dev->hw, 0); + hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_COUNT); + hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw); +} + +/** + * \brief Stop hardware timer + */ +void _timer_stop(struct _timer_device *const dev) +{ + ASSERT(dev && dev->hw); + + hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw); +} + +/** + * \brief Set timer period + */ +void _timer_set_period(struct _timer_device *const dev, const uint32_t clock_cycles) +{ + hri_rtcmode0_write_COMP_reg(dev->hw, 0, clock_cycles); +} + +/** + * \brief Retrieve timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const dev) +{ + return hri_rtcmode0_read_COMP_reg(dev->hw, 0); +} + +/** + * \brief Check if timer is running + */ +bool _timer_is_started(const struct _timer_device *const dev) +{ + return hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw); +} + +/** + * \brief Set timer IRQ + */ +void _timer_set_irq(struct _timer_device *const dev) +{ + (void)dev; +} + +/** + * \brief RTC Timer interrupt handler + * + * \param[in] p The pointer to calendar device struct + */ +static void _rtc_timer_interrupt_handler(struct _timer_device *dev) +{ + /* Read and mask interrupt flag register */ + uint16_t flag = hri_rtcmode0_read_INTFLAG_reg(dev->hw); + + if (flag & RTC_MODE0_INTFLAG_CMP0) { + if (dev->timer_cb.period_expired) { + dev->timer_cb.period_expired(dev); + } + /* Clear interrupt flag */ + hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw); + } +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_rtc_get_timer(void) +{ + return NULL; +} + +/** +* \brief Rtc interrupt handler +*/ +void RTC_Handler(void) +{ + _rtc_timer_interrupt_handler(_rtc_dev); +} diff --git a/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc_base.h b/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc_base.h new file mode 100644 index 0000000000000..bbcf242b9a078 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc_base.h @@ -0,0 +1,62 @@ +/** + * \file + * + * \brief RTC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distributionn. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HPL_RTC2_V200_H_INCLUDED +#define _HPL_RTC2_V200_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_rtc_get_timer(void); + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_RTC2_V200_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c b/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c new file mode 100644 index 0000000000000..9fe612f72be0e --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c @@ -0,0 +1,2922 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE \ + + CONF_SERCOM_5_USART_ENABLE \ + + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ + | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ + | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ + | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ + | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_ctrlc_reg_t ctrl_c; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ + Sercom *const sercom_modules[] = SERCOM_INSTS; + /* Find index for SERCOM instance. */ + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { + return i; + } + } + return 0; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + if (hri_sercomusart_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomusart_set_CTRLA_SWRST_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + +/* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE \ + + CONF_SERCOM_5_I2CM_ENABLE \ + + CONF_SERCOM_6_I2CM_ENABLE \ + + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline void _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + _i2c_m_enable_implementation(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline void _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + /* Check if module is enabled. */ + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomi2cm_set_CTRLA_SWRST_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + +/* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE \ + + CONF_SERCOM_5_I2CS_ENABLE \ + + CONF_SERCOM_6_I2CS_ENABLE \ + + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); + if (hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + +/* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + ((CONF_SERCOM_##n##_SPI_DORD) | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) \ + | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE \ + + CONF_SERCOM_5_SPI_ENABLE \ + + CONF_SERCOM_6_SPI_ENABLE \ + + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + NVIC_EnableIRQ(_sercom_get_irq_num(hw)); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_EnableIRQ(irq++); + } + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ(irq++); + } + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + if (hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ(_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ(_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_ss_detect(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_ss_detect(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_COMPLETE == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} diff --git a/atmel-samd/asf4/samd51/hpl/systick/hpl_systick.c b/atmel-samd/asf4/samd51/hpl/systick/hpl_systick.c new file mode 100644 index 0000000000000..5ea3aac34aa2d --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/systick/hpl_systick.c @@ -0,0 +1,117 @@ + +/** + * \file + * + * \brief SysTick related functionality implementation. + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#ifdef _UNIT_TEST_ +#include +#endif + +/** + * \brief Initialize system time module + */ +void _system_time_init(void *const hw) +{ + (void)hw; + SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); + SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) + | (1 << SysTick_CTRL_CLKSOURCE_Pos); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + _system_time_init(hw); +} + +/** + * \brief De-initialize system time module + */ +void _system_time_deinit(void *const hw) +{ + (void)hw; + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +/** + * \brief Get system time + */ +system_time_t _system_time_get(const void *const hw) +{ + (void)hw; + return (system_time_t)SysTick->VAL; +} + +/** + * \brief Get maximum possible system time + */ +system_time_t _system_time_get_max_time_value(const void *const hw) +{ + (void)hw; + return 0xFFFFFF; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ + (void)hw; + uint8_t n = cycles >> 24; + uint32_t buf = cycles; + + while (n--) { + SysTick->LOAD = 0xFFFFFF; + SysTick->VAL = 0xFFFFFF; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; + buf -= 0xFFFFFF; + } + + SysTick->LOAD = buf; + SysTick->VAL = buf; + while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) + ; +} diff --git a/atmel-samd/asf4/samd51/hpl/tc/hpl_tc.c b/atmel-samd/asf4/samd51/hpl/tc/hpl_tc.c new file mode 100644 index 0000000000000..a897d8f39be32 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/tc/hpl_tc.c @@ -0,0 +1,377 @@ + +/** + * \file + * + * \brief SAM TC + * + * Copyright (C) 2014 - 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 0 +#endif +#ifndef CONF_TC1_ENABLE +#define CONF_TC1_ENABLE 0 +#endif +#ifndef CONF_TC2_ENABLE +#define CONF_TC2_ENABLE 0 +#endif +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 0 +#endif +#ifndef CONF_TC4_ENABLE +#define CONF_TC4_ENABLE 0 +#endif +#ifndef CONF_TC5_ENABLE +#define CONF_TC5_ENABLE 0 +#endif +#ifndef CONF_TC6_ENABLE +#define CONF_TC6_ENABLE 0 +#endif +#ifndef CONF_TC7_ENABLE +#define CONF_TC7_ENABLE 0 +#endif + +/** + * \brief Macro is used to fill usart configuration structure based on its + * number + * + * \param[in] n The number of structures + */ +#define TC_CONFIGURATION(n) \ + { \ + n, TC##n##_IRQn, \ + TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ + | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ + | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ + (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ + | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ + | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ + (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ + } +/** + * \brief TC configuration type + */ +struct tc_configuration { + uint8_t number; + IRQn_Type irq; + hri_tc_ctrla_reg_t ctrl_a; + hri_tc_evctrl_reg_t event_ctrl; + hri_tc_dbgctrl_reg_t dbg_ctrl; + hri_tc_per_reg_t per; + hri_tc_cc32_reg_t cc0; + hri_tc_cc32_reg_t cc1; +}; + +/** + * \brief Array of TC configurations + */ +static struct tc_configuration _tcs[] = { +#if CONF_TC0_ENABLE == 1 + TC_CONFIGURATION(0), +#endif +#if CONF_TC1_ENABLE == 1 + TC_CONFIGURATION(1), +#endif +#if CONF_TC2_ENABLE == 1 + TC_CONFIGURATION(2), +#endif +#if CONF_TC3_ENABLE == 1 + TC_CONFIGURATION(3), +#endif +#if CONF_TC4_ENABLE == 1 + TC_CONFIGURATION(4), +#endif +#if CONF_TC5_ENABLE == 1 + TC_CONFIGURATION(5), +#endif +#if CONF_TC6_ENABLE == 1 + TC_CONFIGURATION(6), +#endif +#if CONF_TC7_ENABLE == 1 + TC_CONFIGURATION(7), +#endif +}; + +static struct _pwm_device *_tc0_dev = NULL; + +static int8_t get_tc_index(const void *const hw); +static void _tc_init_irq_param(const void *const hw, void *dev); +static inline uint8_t _get_hardware_offset(const void *const hw); +/** + * \brief Initialize TC for PWM mode + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw) +{ + int8_t i = get_tc_index(hw); + device->hw = hw; + + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + if (hri_tc_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_tc_set_CTRLA_SWRST_bit(hw); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); + hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); + hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MPWM_Val); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { + hri_tccount16_write_CC_reg(hw, 0, (hri_tc_count16_reg_t)_tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, (hri_tc_count16_reg_t)_tcs[i].cc1); + } else { + /* 8-bit resolution is not accepted by duty cycle control */ + return -1; + } + + _tc_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ(_tcs[i].irq); + NVIC_ClearPendingIRQ(_tcs[i].irq); + NVIC_EnableIRQ(_tcs[i].irq); + + return 0; +} +/** + * \brief De-initialize TC for PWM mode + */ +void _pwm_deinit(struct _pwm_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + NVIC_DisableIRQ(_tcs[i].irq); + + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_set_CTRLA_SWRST_bit(hw); +} +/** + * \brief Start PWM + */ +void _pwm_enable(struct _pwm_device *const device) +{ + hri_tc_set_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Stop PWM + */ +void _pwm_disable(struct _pwm_device *const device) +{ + hri_tc_clear_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Set PWM parameter + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + + _tcs[i].cc0 = period; + _tcs[i].cc1 = duty_cycle; + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + } else { + hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1); + } +} +/** + * \brief Get pwm waveform period value + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0)); + } else { + return (pwm_period_t)(hri_tccount16_read_CC_reg(hw, 0)); + } +} +/** + * \brief Get pwm waveform duty cycle + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + uint32_t per; + uint32_t duty_cycle; + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + per = hri_tccount32_read_CC_reg(hw, 0); + duty_cycle = hri_tccount32_read_CC_reg(hw, 1); + } else { + per = hri_tccount16_read_CC_reg(hw, 0); + duty_cycle = hri_tccount16_read_CC_reg(hw, 1); + } + + return ((duty_cycle * 1000) / per); +} +/** + * \brief Check if PWM is running + */ +bool _pwm_is_enabled(const struct _pwm_device *const device) +{ + return hri_tc_get_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Enable/disable PWM interrupt + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable) +{ + ASSERT(device); + + if (PWM_DEVICE_PERIOD_CB == type) { + hri_tc_write_INTEN_OVF_bit(device->hw, disable); + } else if (PWM_DEVICE_ERROR_CB == type) { + hri_tc_write_INTEN_ERR_bit(device->hw, disable); + } +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Retrieve pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void) +{ + return NULL; +} +/** + * \internal TC interrupt handler for PWM + * + * \param[in] instance TC instance number + */ +static void tc_pwm_interrupt_handler(struct _pwm_device *device) +{ + void *const hw = device->hw; + + if (hri_tc_get_interrupt_OVF_bit(hw)) { + hri_tc_clear_interrupt_OVF_bit(hw); + if (NULL != device->callback.pwm_period_cb) { + device->callback.pwm_period_cb(device); + } + } + if (hri_tc_get_INTEN_ERR_bit(hw)) { + hri_tc_clear_interrupt_ERR_bit(hw); + if (NULL != device->callback.pwm_error_cb) { + device->callback.pwm_error_cb(device); + } + } +} + +/** +* \brief TC interrupt handler +*/ +void TC0_Handler(void) +{ + tc_pwm_interrupt_handler(_tc0_dev); +} + +/** + * \internal Retrieve TC index + * + * \param[in] hw The pointer to hardware instance + * + * \return The index of TC configuration + */ +static int8_t get_tc_index(const void *const hw) +{ + uint8_t index = _get_hardware_offset(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_tcs); i++) { + if (_tcs[i].number == index) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \brief Init irq param with the given tc hardware instance + */ +static void _tc_init_irq_param(const void *const hw, void *dev) +{ + if (hw == TC0) { + _tc0_dev = (struct _pwm_device *)dev; + } +} + +/** + * \internal Retrieve TC hardware index + * + * \param[in] hw The pointer to hardware instance + */ +static inline uint8_t _get_hardware_offset(const void *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)tc_modules[i]) { + return i; + } + } + return 0; +} diff --git a/atmel-samd/asf4/samd51/hpl/tc/hpl_tc_base.h b/atmel-samd/asf4/samd51/hpl/tc/hpl_tc_base.h new file mode 100644 index 0000000000000..9d7f2c72a5ec2 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/tc/hpl_tc_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief SAM Timer/Counter + * + * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distributionn. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HPL_TC_BASE_H_INCLUDED +#define _HPL_TC_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup tc_group TC Hardware Proxy Layer + * + * \section tc_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void); + +/** + * \brief Retrieve pwm helper functions + * + * \return A pointer to set of pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void); + +//@} +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/trng/hpl_trng.c b/atmel-samd/asf4/samd51/hpl/trng/hpl_trng.c new file mode 100644 index 0000000000000..2b1f35a16e4d4 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/trng/hpl_trng.c @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief True Random Number Generator + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +static inline int32_t _trng_init(void *hw) +{ + if (hri_trng_get_CTRLA_reg(hw, TRNG_CTRLA_ENABLE)) { + return ERR_DENIED; + } + if (CONF_TRNG_RUNSTDBY) { + hri_trng_set_CTRLA_RUNSTDBY_bit(hw); + } else { + hri_trng_clear_CTRLA_RUNSTDBY_bit(hw); + } + if (CONF_TRNG_DATARDYEO) { + hri_trng_set_EVCTRL_DATARDYEO_bit(hw); + } else { + hri_trng_clear_EVCTRL_DATARDYEO_bit(hw); + } + return ERR_NONE; +} + +int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw) +{ + int32_t rc; + + ASSERT(dev && hw); + + rc = _trng_init(hw); + if (rc == ERR_NONE) { + dev->prvt = hw; + dev->n_bits = 32; + } + return rc; +} + +void _rand_sync_deinit(struct _rand_sync_dev *const dev) +{ + _rand_sync_disable(dev); +} + +int32_t _rand_sync_enable(struct _rand_sync_dev *const dev) +{ + ASSERT(dev); + ASSERT(dev->prvt); + + hri_trng_set_CTRLA_ENABLE_bit(dev->prvt); + return ERR_NONE; +} + +void _rand_sync_disable(struct _rand_sync_dev *const dev) +{ + ASSERT(dev); + ASSERT(dev->prvt); + + hri_trng_clear_CTRLA_ENABLE_bit(dev->prvt); +} + +int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed) +{ + (void)dev; + (void)seed; + return ERR_UNSUPPORTED_OP; +} + +uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev) +{ + ASSERT(dev); + ASSERT(dev->prvt); + ASSERT(hri_trng_get_CTRLA_reg(dev->prvt, TRNG_CTRLA_ENABLE)); + + while (!hri_trng_get_INTFLAG_reg(dev->prvt, TRNG_INTFLAG_DATARDY)) { + /* Wait until data ready. */ + } + return hri_trng_read_DATA_reg(dev->prvt); +} diff --git a/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c b/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c new file mode 100644 index 0000000000000..bdf245aa50a46 --- /dev/null +++ b/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c @@ -0,0 +1,2088 @@ +/** + * \file + * + * \brief SAM USB HPL + * + * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include +#include + +/** + * \brief Dummy callback function + * \return Always false. + */ +static bool _dummy_func_no_return(uint32_t unused0, uint32_t unused1) +{ + (void)unused0; + (void)unused1; + return false; +} + +/** + * \brief Load USB calibration value from NVM + */ +static void _usb_load_calib(void) +{ +#define NVM_USB_PAD_TRANSN_POS 32 +#define NVM_USB_PAD_TRANSN_SIZE 5 +#define NVM_USB_PAD_TRANSP_POS 37 +#define NVM_USB_PAD_TRANSP_SIZE 5 +#define NVM_USB_PAD_TRIM_POS 42 +#define NVM_USB_PAD_TRIM_SIZE 3 + Usb * hw = USB; + uint32_t pad_transn + = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRANSN_POS / 32)) >> (NVM_USB_PAD_TRANSN_POS % 32)) + & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1); + uint32_t pad_transp + = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRANSP_POS / 32)) >> (NVM_USB_PAD_TRANSP_POS % 32)) + & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1); + uint32_t pad_trim = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRIM_POS / 32)) >> (NVM_USB_PAD_TRIM_POS % 32)) + & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1); + if (pad_transn == 0 || pad_transn == 0x1F) { + pad_transn = 9; + } + if (pad_transp == 0 || pad_transp == 0x1F) { + pad_transp = 25; + } + if (pad_trim == 0 || pad_trim == 0x7) { + pad_trim = 6; + } + + hw->DEVICE.PADCAL.reg = USB_PADCAL_TRANSN(pad_transn) | USB_PADCAL_TRANSP(pad_transp) | USB_PADCAL_TRIM(pad_trim); + + hw->DEVICE.QOSCTRL.bit.CQOS = 3; + hw->DEVICE.QOSCTRL.bit.DQOS = 3; +} + +/** \name USB clock source management */ +/*@{*/ + +/** USB clock is generated by DFLL. */ +#define USB_CLK_SRC_DFLL 0 + +/** USB clock is generated by DPLL. */ +#define USB_CLK_SRC_DPLL 1 + +/** Uses DFLL as USB clock source. */ +#define CONF_USB_D_CLK_SRC USB_CLK_SRC_DFLL + +/** Retry for USB remote wakeup sending. */ +#define CONF_USB_RMT_WKUP_RETRY 5 + +/** + * \brief Wait DPLL clock to be ready + */ +static inline void _usb_d_dev_wait_dpll_rdy(void) +{ +#define DPLL_READY_FLAG (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK) + while (hri_oscctrl_get_DPLLSTATUS_reg(OSCCTRL, 0, DPLL_READY_FLAG) != DPLL_READY_FLAG) + ; +} + +/** + * \brief Wait DFLL clock to be ready + */ +static inline void _usb_d_dev_wait_dfll_rdy(void) +{ + if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(OSCCTRL)) { + while (hri_oscctrl_get_STATUS_reg(OSCCTRL, (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC)) + != (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC)) + ; + } else { + while (hri_oscctrl_get_STATUS_reg(OSCCTRL, OSCCTRL_STATUS_DFLLRDY) != OSCCTRL_STATUS_DFLLRDY) + ; + } +} + +/** + * \brief Wait USB source clock to be ready + * \param[in] clk_src Clock source, could be \ref USB_CLK_SRC_DFLL or + * \ref USB_CLK_SRC_DPLL. + */ +static inline void _usb_d_dev_wait_clk_rdy(const uint8_t clk_src) +{ + if (clk_src == USB_CLK_SRC_DFLL) { + _usb_d_dev_wait_dfll_rdy(); + } else if (clk_src == USB_CLK_SRC_DPLL) { + _usb_d_dev_wait_dpll_rdy(); + } +} + +/*@}*/ + +/** \name USB general settings */ +/*@{*/ + +/** Increase the value to be aligned. */ +#define _usb_align_up(val) (((val)&0x3) ? (((val) + 4 - ((val)&0x3))) : (val)) + +/** Check if the buffer is in RAM (can DMA), or cache needed + * \param[in] a Buffer start address. + * \param[in] s Buffer size, in number of bytes. + * \return \c true If the buffer is in RAM. + */ +#define _IN_RAM(a, s) ((0x20000000 <= (uint32_t)(a)) && (((uint32_t)(a) + (s)) < 0x20008000)) + +/** Check if the address should be placed in RAM. */ +#define _usb_is_addr4dma(addr, size) _IN_RAM((addr), (size)) + +/** Check if the address is 32-bit aligned. */ +#define _usb_is_aligned(val) (((uint32_t)(val)&0x3) == 0) +/*@}*/ + +/* Cache static configurations. + * By default, all OUT endpoint have 64 bytes cache. */ +#ifndef CONF_USB_EP0_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP0_CACHE 64 +#endif + +#ifndef CONF_USB_EP0_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP0_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP1_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP1_CACHE 64 +#endif + +#ifndef CONF_USB_EP1_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP1_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP2_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP2_CACHE 64 +#endif + +#ifndef CONF_USB_EP2_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP2_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP3_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP3_CACHE 64 +#endif + +#ifndef CONF_USB_EP3_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP3_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP4_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP4_CACHE 64 +#endif + +#ifndef CONF_USB_EP4_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP4_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP5_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP5_CACHE 64 +#endif + +#ifndef CONF_USB_EP5_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP5_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP6_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP6_CACHE 64 +#endif + +#ifndef CONF_USB_EP6_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP6_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP7_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP7_CACHE 64 +#endif + +#ifndef CONF_USB_EP7_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP7_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP8_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP8_CACHE 64 +#endif + +#ifndef CONF_USB_EP8_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP8_I_CACHE 0 +#endif + +#ifndef CONF_USB_EP9_CACHE +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#define CONF_USB_EP9_CACHE 64 +#endif + +#ifndef CONF_USB_EP9_I_CACHE +/** Endpoint cache buffer for IN transactions (none-control). */ +#define CONF_USB_EP9_I_CACHE 0 +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP0_CACHE +static uint32_t _usb_ep0_cache[_usb_align_up(CONF_USB_EP0_CACHE) / 4]; +#else +#define _usb_ep0_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#define _usb_ep0_i_cache NULL + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 +uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; +#else +#define _usb_ep1_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1 +uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; +#else +#define _usb_ep1_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP2_CACHE && CONF_USB_D_MAX_EP_N >= 2 +static uint32_t _usb_ep2_cache[_usb_align_up(CONF_USB_EP2_CACHE) / 4]; +#else +#define _usb_ep2_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP2_I_CACHE && CONF_USB_D_MAX_EP_N >= 2 +static uint32_t _usb_ep2_i_cache[_usb_align_up(CONF_USB_EP2_I_CACHE) / 4]; +#else +#define _usb_ep2_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP3_CACHE && CONF_USB_D_MAX_EP_N >= 3 +static uint32_t _usb_ep3_cache[_usb_align_up(CONF_USB_EP3_CACHE) / 4]; +#else +#define _usb_ep3_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP3_I_CACHE && CONF_USB_D_MAX_EP_N >= 3 +static uint32_t _usb_ep3_i_cache[_usb_align_up(CONF_USB_EP3_I_CACHE) / 4]; +#else +#define _usb_ep3_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP4_CACHE && CONF_USB_D_MAX_EP_N >= 4 +static uint32_t _usb_ep4_cache[_usb_align_up(CONF_USB_EP4_CACHE) / 4]; +#else +#define _usb_ep4_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP4_I_CACHE && CONF_USB_D_MAX_EP_N >= 4 +static uint32_t _usb_ep4_i_cache[_usb_align_up(CONF_USB_EP4_I_CACHE) / 4]; +#else +#define _usb_ep4_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP5_CACHE && CONF_USB_D_MAX_EP_N >= 5 +static uint32_t _usb_ep5_cache[_usb_align_up(CONF_USB_EP5_CACHE) / 4]; +#else +#define _usb_ep5_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP5_I_CACHE && CONF_USB_D_MAX_EP_N >= 5 +static uint32_t _usb_ep5_i_cache[_usb_align_up(CONF_USB_EP5_I_CACHE) / 4]; +#else +#define _usb_ep5_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP6_CACHE && CONF_USB_D_MAX_EP_N >= 6 +static uint32_t _usb_ep6_cache[_usb_align_up(CONF_USB_EP6_CACHE) / 4]; +#else +#define _usb_ep6_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP6_I_CACHE && CONF_USB_D_MAX_EP_N >= 6 +static uint32_t _usb_ep6_i_cache[_usb_align_up(CONF_USB_EP6_I_CACHE) / 4]; +#else +#define _usb_ep6_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP7_CACHE && CONF_USB_D_MAX_EP_N >= 7 +static uint32_t _usb_ep7_cache[_usb_align_up(CONF_USB_EP7_CACHE) / 4]; +#else +#define _usb_ep7_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP7_I_CACHE && CONF_USB_D_MAX_EP_N >= 7 +static uint32_t _usb_ep7_i_cache[_usb_align_up(CONF_USB_EP7_I_CACHE) / 4]; +#else +#define _usb_ep7_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP8_CACHE && CONF_USB_D_MAX_EP_N >= 8 +static uint32_t _usb_ep8_cache[_usb_align_up(CONF_USB_EP8_CACHE) / 4]; +#else +#define _usb_ep8_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP8_I_CACHE && CONF_USB_D_MAX_EP_N >= 8 +static uint32_t _usb_ep8_i_cache[_usb_align_up(CONF_USB_EP8_I_CACHE) / 4]; +#else +#define _usb_ep8_i_cache NULL +#endif + +/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT + * transactions (control). */ +#if CONF_USB_EP9_CACHE && CONF_USB_D_MAX_EP_N >= 9 +static uint32_t _usb_ep9_cache[_usb_align_up(CONF_USB_EP9_CACHE) / 4]; +#else +#define _usb_ep9_cache NULL +#endif + +/** Endpoint cache buffer for IN transactions (none-control). */ +#if CONF_USB_EP9_I_CACHE && CONF_USB_D_MAX_EP_N >= 9 +static uint32_t _usb_ep9_i_cache[_usb_align_up(CONF_USB_EP9_I_CACHE) / 4]; +#else +#define _usb_ep9_i_cache NULL +#endif + +/** Access endpoint cache buffer for OUT transactions (none-control) or + * SETUP/IN/OUT transactions (control). */ +#define _USB_EP_CACHE(n) ((void *)_usb_ep##n##_cache) + +/** Access endpoint cache buffer for IN transactions (none-control). */ +#define _USB_EP_I_CACHE(n) ((void *)_usb_ep##n##_i_cache) + +/** The configuration settings for one of the endpoint hardware. */ +struct _usb_ep_cfg_item { + /* Endpoint cache buffer for OUT transactions (none-control) or + * SETUP/IN/OUT transactions (control). */ + void *cache; + /* endpoint cache buffer for IN transactions (none-control). */ + void *i_cache; + /* Cache buffer size for OUT transactions (none-control) or + * SETUP/IN/OUT transactions (control). */ + uint16_t size; + /* Cache buffer size for IN transactions (none-control). */ + uint16_t i_size; +}; + +/** Build the endpoint configuration settings for one endpoint. */ +#define _USB_EP_CFG_ITEM(n) \ + { \ + _USB_EP_CACHE(n), _USB_EP_I_CACHE(n), CONF_USB_EP##n##_CACHE, CONF_USB_EP##n##_I_CACHE, \ + } + +/** The configuration settings for all endpoint. */ +static const struct _usb_ep_cfg_item _usb_ep_cfgs[] = {_USB_EP_CFG_ITEM(0) +#if CONF_USB_D_MAX_EP_N >= 1 + , + _USB_EP_CFG_ITEM(1) +#endif +#if CONF_USB_D_MAX_EP_N >= 2 + , + _USB_EP_CFG_ITEM(2) +#endif +#if CONF_USB_D_MAX_EP_N >= 3 + , + _USB_EP_CFG_ITEM(3) +#endif +#if CONF_USB_D_MAX_EP_N >= 4 + , + _USB_EP_CFG_ITEM(4) +#endif +#if CONF_USB_D_MAX_EP_N >= 5 + , + _USB_EP_CFG_ITEM(5) +#endif +#if CONF_USB_D_MAX_EP_N >= 6 + , + _USB_EP_CFG_ITEM(6) +#endif +#if CONF_USB_D_MAX_EP_N >= 7 + , + _USB_EP_CFG_ITEM(7) +#endif +#if CONF_USB_D_MAX_EP_N >= 8 + , + _USB_EP_CFG_ITEM(8) +#endif +#if CONF_USB_D_MAX_EP_N >= 9 + , + _USB_EP_CFG_ITEM(9) +#endif +}; + +/** \name HW specific settings and implements */ +/*@{*/ + +/** Number of endpoints supported. */ +#define USB_D_N_EP (1 + CONF_USB_D_NUM_EP_SP * 2) + +/** HPL USB device endpoint struct. */ +struct _usb_d_dev_ep { + /** Pointer to transaction buffer. */ + uint8_t *trans_buf; + /** Transaction size. */ + uint32_t trans_size; + /** Transaction transferred count. */ + uint32_t trans_count; + + /** Pointer to cache buffer, must be aligned. */ + uint8_t *cache; + + /** Endpoint size. */ + uint16_t size; + /** Endpoint address. */ + uint8_t ep; + /** Feature flags. */ + union { + /** Interpreted by bit fields. */ + struct { + /** EPCFG.ETYPE. */ + uint8_t eptype : 3; + /** Stall status. */ + uint8_t is_stalled : 1; + /** Transaction auto ZLP. */ + uint8_t need_zlp : 1; + /** Transaction with cache */ + uint8_t use_cache : 1; + /** Endpoint is busy. */ + uint8_t is_busy : 1; + /** Transaction direction. */ + uint8_t dir : 1; + } bits; + uint8_t u8; + } flags; +}; + +/** Check if the endpoint is used. */ +#define _usb_d_dev_ep_is_used(ept) ((ept)->ep != 0xFF) + +/** Check if the endpoint is busy doing transactions. */ +#define _usb_d_dev_ep_is_busy(ept) ((ept)->flags.bits.is_busy) + +/** Check if the endpoint is control endpoint. */ +#define _usb_d_dev_ep_is_ctrl(ept) ((ept)->flags.bits.eptype == USB_D_EPTYPE_CTRL) + +/** Check if the endpoint transactions are IN. */ +#define _usb_d_dev_ep_is_in(ept) ((ept)->flags.bits.dir) + +/** Interrupt flags for SETUP transaction. */ +#define USB_D_SETUP_INT_FLAGS (USB_DEVICE_EPINTFLAG_RXSTP) + +/** Interrupt flags for BANK1 transactions. */ +#define USB_D_BANK1_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT1 | USB_DEVICE_EPINTFLAG_TRFAIL1 | USB_DEVICE_EPINTFLAG_STALL1) + +/** Interrupt flags for BANK0 transactions. */ +#define USB_D_BANK0_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT0 | USB_DEVICE_EPINTFLAG_TRFAIL0 | USB_DEVICE_EPINTFLAG_STALL0) + +/** Interrupt flags for SETUP/IN/OUT transactions. */ +#define USB_D_ALL_INT_FLAGS (0x7F) + +/** Interrupt flags for WAKEUP event. */ +#define USB_D_WAKEUP_INT_FLAGS (USB_DEVICE_INTFLAG_UPRSM | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_WAKEUP) + +/** Interrupt flags for SUSPEND event. */ +#define USB_D_SUSPEND_INT_FLAGS (USB_DEVICE_INTFLAG_LPMSUSP | USB_DEVICE_INTFLAG_SUSPEND) + +/** Max data bytes for a single DMA transfer. */ +#define USB_D_DEV_TRANS_MAX 8192 /* 14-bits, uses 13-bits. */ + +/** Endpoint type setting to disable. */ +#define USB_D_EPTYPE_DISABLE 0 + +/** Endpoint type setting to work as control endpoint. */ +#define USB_D_EPTYPE_CTRL 1 + +/** Endpoint type setting to work as isochronous endpoint. */ +#define USB_D_EPTYPE_ISOCH 2 + +/** Endpoint type setting to work as interrupt endpoint. */ +#define USB_D_EPTYPE_INT 3 + +/** Endpoint type setting to work as bulk endpoint. */ +#define USB_D_EPTYPE_BULK 4 + +/** Endpoint type setting for dual bank endpoint. */ +#define USB_D_EPTYPE_DUAL 5 + +/** EPCFG register value for control endpoints. */ +#define USB_D_EPCFG_CTRL 0x11 + +/** HPL USB device struct. */ +struct _usb_d_dev { + /** Callbacks of USB device. */ + struct _usb_d_dev_callbacks callbacks; + /** Endpoint transaction callbacks. */ + struct _usb_d_dev_ep_callbacks ep_callbacks; + /** Endpoints (ep0 + others). */ + struct _usb_d_dev_ep ep[USB_D_N_EP]; +}; + +/** Private data for SAM0 USB peripheral. + */ +typedef struct _usb_d_dev_prvt { + /** USB device descriptor table for peripheral to work. */ + UsbDeviceDescriptor desc_table[CONF_USB_D_MAX_EP_N + 1]; +} usb_d_dev_prvt_t; + +/*@}*/ + +/** USB device driver instance. */ +static struct _usb_d_dev dev_inst; + +/** USB device driver private data instance. */ +static struct _usb_d_dev_prvt prvt_inst; + +static void _usb_d_dev_reset_epts(void); + +static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t status); +static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code); + +static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr); +static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr); + +static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept); + +/** \brief ACK the endpoint interrupt + * \param[in] epn Endpoint number. + * \param[in] flags Interrupt flags. + */ +static inline void _usbd_ep_int_ack(uint8_t epn, uint32_t flags) +{ + hri_usbendpoint_clear_EPINTFLAG_reg(USB, epn, flags); +} + +/** \brief Enable the endpoint interrupt + * \param[in] epn Endpoint number. + * \param[in] flags Interrupt flags. + */ +static inline void _usbd_ep_int_en(uint8_t epn, uint32_t flags) +{ + hri_usbendpoint_set_EPINTEN_reg(USB, epn, flags); +} + +/** \brief Disable the endpoint interrupt + * \param[in] epn Endpoint number. + * \param[in] flags Interrupt flags. + */ +static inline void _usbd_ep_int_dis(uint8_t epn, uint32_t flags) +{ + hri_usbendpoint_clear_EPINTEN_reg(USB, epn, flags); +} + +/** \brief Check if endpoint is control endpoint + * \param[in] epn Endpoint number. + */ +static inline bool _usbd_ep_is_ctrl(uint8_t epn) +{ + return (hri_usbendpoint_read_EPCFG_reg(USB, epn) == USB_D_EPCFG_CTRL); +} + +/** \brief Set endpoint stall + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] st Stall status. + */ +static inline void _usbd_ep_set_stall(uint8_t epn, uint8_t bank_n, bool st) +{ + if (st) { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); + } else { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); + } +} + +/** \brief Check if the endpoint is stalled + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \return \c true if it's stalled. + */ +static inline bool _usbd_ep_is_stalled(uint8_t epn, uint8_t bank_n) +{ + Usb *hw = USB; + return (hri_usbendpoint_read_EPSTATUS_reg(hw, epn) & (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); +} + +/** \brief Check if stall has been sent from the endpoint + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \return \c true if it's sent. + */ +static inline bool _usbd_ep_is_stall_sent(uint8_t epn, uint8_t bank_n) +{ + Usb *hw = USB; + return (hri_usbendpoint_read_EPINTFLAG_reg(hw, epn) & (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); +} + +/** \brief ACK endpoint STALL interrupt + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + */ +static inline void _usbd_ep_ack_stall(uint8_t epn, uint8_t bank_n) +{ + _usbd_ep_int_ack(epn, (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); +} + +/** \brief Enable/disable endpoint STALL interrupt + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] en \c true to enable, \c false to disable. + */ +static inline void _usbd_ep_int_stall_en(uint8_t epn, uint8_t bank_n, const bool en) +{ + if (en) { + _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); + } else { + _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); + } +} + +/** \brief Stop SETUP transactions + * \param[in] epn Endpoint number. + */ +static inline void _usbd_ep_stop_setup(uint8_t epn) +{ + hri_usbendpoint_clear_EPINTEN_RXSTP_bit(USB, epn); +} + +/** \brief Check if SETUP packet is ready in cache + * \param[in] epn Endpoint number. + */ +static inline bool _usbd_ep_is_setup(uint8_t epn) +{ + return hri_usbendpoint_get_EPINTFLAG_reg(USB, epn, USB_DEVICE_EPINTFLAG_RXSTP); +} + +/** \brief ACK endpoint SETUP interrupt + * \param[in] epn Endpoint number. + */ +static inline void _usbd_ep_ack_setup(uint8_t epn) +{ + _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_RXSTP); +} + +/** \brief Set endpoint toggle value + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] tgl Toggle value. + */ +static inline void _usbd_ep_set_toggle(uint8_t epn, uint8_t bank_n, uint8_t tgl) +{ + if (tgl) { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); + } else { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); + } +} + +/** \brief ACK IN/OUT complete interrupt + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + */ +static inline void _usbd_ep_ack_io_cpt(uint8_t epn, uint8_t bank_n) +{ + _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_TRCPT0 << bank_n); +} + +/** \brief Set DMA buffer used for bank data + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] addr DMA buffer address to set. + */ +static inline void _usbd_ep_set_buf(uint8_t epn, uint8_t bank_n, uint32_t addr) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->ADDR.reg = addr; +} + +/** \brief Set bank count for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] count Data count for IN. + */ +static inline void _usbd_ep_set_in_count(uint8_t epn, uint8_t bank_n, uint16_t count) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.MULTI_PACKET_SIZE = count; +} + +/** \brief Set bank size for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size for IN. + */ +static inline void _usbd_ep_set_in_size(uint8_t epn, uint8_t bank_n, uint16_t size) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.BYTE_COUNT = size; +} + +/** \brief Set bank count for OUT transaction + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] count Data count for OUT. + */ +static inline void _usbd_ep_set_out_count(uint8_t epn, uint8_t bank_n, uint16_t count) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.BYTE_COUNT = count; +} + +/** \brief Set bank size for OUT transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size for OUT. + */ +static inline void _usbd_ep_set_out_size(uint8_t epn, uint8_t bank_n, uint16_t size) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->PCKSIZE.bit.MULTI_PACKET_SIZE = size; +} + +/** Set bank size and count for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size. + * \param[in] count Initial data count. + */ +static inline void _usbd_ep_set_in_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) +{ + _usbd_ep_set_in_size(epn, bank_n, size); + _usbd_ep_set_in_count(epn, bank_n, count); +} + +/** \brief Set bank size and count for OUT transaction + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] size Data size. + * \param[in] count Initial data count. + */ +static inline void _usbd_ep_set_out_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) +{ + _usbd_ep_set_out_size(epn, bank_n, size); + _usbd_ep_set_out_count(epn, bank_n, count); +} + +/** \brief Clear bank status + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + */ +static inline void _usbd_ep_clear_bank_status(uint8_t epn, uint8_t bank_n) +{ + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; + bank->STATUS_BK.reg = 0; +} + +/** Set IN ready for IN transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] rdy Set to \c true to indicate IN packet ready to TX. + */ +static inline void _usbd_ep_set_in_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) +{ + if (rdy) { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } else { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } +} + +/** \brief Set bank ready for OUT transactions + * \param[in] epn Endpoint number. + * \param[in] bank_n Endpoint bank number. + * \param[in] rdy Set to \c true to indicate OUT bank ready to RX. + */ +static inline void _usbd_ep_set_out_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) +{ + if (rdy) { + hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } else { + hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); + } +} + +/** + * \brief Convert USB endpoint size to HW PCKSIZE.SIZE + * \param[in] n Number of bytes of endpoint size. + */ +static inline uint8_t _usbd_ep_pcksize_size(uint16_t n) +{ + return ( + (n > 512) + ? 7 + : ((n > 256) ? 6 : ((n > 128) ? 5 : ((n > 64) ? 4 : ((n > 32) ? 3 : ((n > 16) ? 2 : ((n > 8) ? 1 : 0))))))); +} + +/** + * \brief Obtain endpoint descriptor pointer + * \param[in] epn Endpoint number. + * \param[in] dir Endpoint direction. + */ +static inline struct _usb_d_dev_ep *_usb_d_dev_ept(uint8_t epn, bool dir) +{ + uint8_t ep_index = (epn == 0) ? 0 : (dir ? (epn + CONF_USB_D_MAX_EP_N) : epn); + return &dev_inst.ep[ep_index]; +} + +/** + * \brief Handles USB SOF interrupt + */ +static inline void _usb_d_dev_sof(void) +{ + /* ACK SOF interrupt. */ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_SOF); + dev_inst.callbacks.sof(); +} + +/** + * \brief Handles USB LPM Suspend interrupt + */ +static inline void _usb_d_dev_lpmsusp(void) +{ + uint8_t i; + uint32_t lpm_variable = 0; + + /* ACK LPMSUSP interrupt. */ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); + /* Change interrupt masks */ + hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + + /* Find LPM data */ + for (i = 0; i < CONF_USB_D_MAX_EP_N; i++) { + UsbDeviceDescBank *bank = &prvt_inst.desc_table[i].DeviceDescBank[0]; + if (bank->EXTREG.bit.SUBPID == 0x3) { + /* Save LPM variable */ + lpm_variable = bank->EXTREG.bit.VARIABLE; + /* Clear */ + bank->EXTREG.reg = 0; + break; + } + } + dev_inst.callbacks.event(USB_EV_LPM_SUSPEND, lpm_variable); +} + +/** + * \brief Handles USB RAM Error interrupt + */ +static inline void _usb_d_dev_ramerr(void) +{ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_RAMACER); + dev_inst.callbacks.event(USB_EV_ERROR, 0); +} + +/** + * \brief Handles USB resume/wakeup interrupts + */ +static inline void _usb_d_dev_wakeup(void) +{ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_WAKEUP_INT_FLAGS); + hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + + _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); + dev_inst.callbacks.event(USB_EV_WAKEUP, 0); +} + +/** + * \brief Handles USB signal reset interrupt + */ +static inline void _usb_d_dev_reset(void) +{ + /* EP0 will not be reseted by USB RESET, disable manually. */ + hri_usbendpoint_write_EPCFG_reg(USB, 0, 0); + + hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_EORST); + hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + + _usb_d_dev_reset_epts(); + dev_inst.callbacks.event(USB_EV_RESET, 0); +} + +static inline void _usb_d_dev_suspend(void) +{ + hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); + hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); + hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); + + dev_inst.callbacks.event(USB_EV_SUSPEND, 0); +} + +/** + * \brief Handles USB non-endpoint interrupt + */ +static inline bool _usb_d_dev_handle_nep(void) +{ + bool rc = true; + uint16_t flags = hri_usbdevice_read_INTFLAG_reg(USB); + flags &= hri_usbdevice_read_INTEN_reg(USB); + + if (flags & USB_DEVICE_INTFLAG_SOF) { + _usb_d_dev_sof(); + return true; + } + if (flags & USB_DEVICE_INTFLAG_LPMSUSP) { + _usb_d_dev_lpmsusp(); + } else if (flags & USB_DEVICE_INTFLAG_RAMACER) { + _usb_d_dev_ramerr(); + } else if (flags & USB_D_WAKEUP_INT_FLAGS) { + _usb_d_dev_wakeup(); + } else if (flags & USB_DEVICE_INTFLAG_EORST) { + _usb_d_dev_reset(); + } else if (flags & USB_DEVICE_INTFLAG_SUSPEND) { + _usb_d_dev_suspend(); + } else { + rc = false; + } + return rc; +} + +/** + * \brief Prepare next IN transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] isr Invoked from ISR. + */ +static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; + uint16_t trans_count = isr ? bank[1].PCKSIZE.bit.BYTE_COUNT : 0; + uint16_t trans_next; + uint16_t last_pkt = trans_count & ((ept->size == 1023) ? ept->size : (ept->size - 1)); + uint8_t inten = 0; + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + + if (isr) { + _usbd_ep_ack_io_cpt(epn, 1); + } + + ept->trans_count += trans_count; + /* Send more data. */ + if (ept->trans_count < ept->trans_size) { + trans_next = ept->trans_size - ept->trans_count; + if (ept->flags.bits.use_cache) { + if (trans_next > ept->size) { + trans_next = ept->size; + } + memcpy(ept->cache, &ept->trans_buf[ept->trans_count], trans_next); + _usbd_ep_set_buf(epn, 1, (uint32_t)ept->cache); + } else { + if (trans_next > USB_D_DEV_TRANS_MAX) { + trans_next = USB_D_DEV_TRANS_MAX; + } + _usbd_ep_set_buf(epn, 1, (uint32_t)&ept->trans_buf[ept->trans_count]); + } + _usbd_ep_set_in_trans(epn, 1, trans_next, 0); + goto _in_tx_exec; + } else if (ept->flags.bits.need_zlp) { + ept->flags.bits.need_zlp = 0; + _usbd_ep_set_in_trans(epn, 1, 0, 0); + goto _in_tx_exec; + } + /* Complete. */ + if (is_ctrl) { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRCPT0); + } else { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS); + } + + /* No ping-pong, so ask more data without background transfer. */ + if (last_pkt == ept->size) { + ept->flags.bits.is_busy = 0; + if (dev_inst.ep_callbacks.more(ept->ep, ept->trans_count)) { + /* More data added. */ + return; + } + ept->flags.bits.is_busy = 1; + } + /* Finish normally. */ + _usb_d_dev_trans_done(ept, USB_TRANS_DONE); + return; + +_in_tx_exec: + if (!isr) { + if (is_ctrl) { + /* Control endpoint: SETUP or OUT will abort IN transaction. + * SETUP: terminate the IN without any notification. Trigger + * SETUP callback. + * OUT NAK: terminate IN. + */ + inten = USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL0; + } else { + /* Initialize normal IN transaction. */ + inten = USB_D_BANK1_INT_FLAGS; + } + hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); + } + _usbd_ep_set_in_rdy(epn, 1, true); +} + +/** + * \brief Prepare next OUT transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] isr Invoked from ISR. + */ +static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; + uint16_t trans_size = isr ? bank->PCKSIZE.bit.MULTI_PACKET_SIZE : 0; + uint16_t last_trans = isr ? bank->PCKSIZE.bit.BYTE_COUNT : 0; + uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); + uint16_t last_pkt = last_trans & size_mask; + uint16_t trans_next; + uint8_t inten; + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + + if (isr) { + _usbd_ep_ack_io_cpt(epn, 0); + } + + /* If cache is used, copy data to buffer. */ + if (ept->flags.bits.use_cache && ept->trans_size) { + uint16_t buf_remain = ept->trans_size - ept->trans_count; + memcpy(&ept->trans_buf[ept->trans_count], ept->cache, (buf_remain > last_pkt) ? last_pkt : buf_remain); + } + + /* Force wait ZLP */ + if (ept->trans_size == 0 && ept->flags.bits.need_zlp) { + ept->flags.bits.need_zlp = 0; + ept->flags.bits.use_cache = 1; + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + _usbd_ep_set_out_trans(epn, 0, ept->size, 0); + goto _out_rx_exec; + } else if (isr && last_pkt < ept->size) { + /* Short packet. */ + ept->flags.bits.need_zlp = 0; + ept->trans_count += last_trans; + } else { + /* Full packets. */ + ept->trans_count += trans_size; + + /* Wait more data */ + if (ept->trans_count < ept->trans_size) { + /* Continue OUT */ + trans_next = ept->trans_size - ept->trans_count; + if (ept->flags.bits.use_cache) { + /* Expect single packet each time. */ + if (trans_next > ept->size) { + trans_next = ept->size; + } + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + } else { + /* Multiple packets each time. */ + if (trans_next > ept->size) { + if (trans_next > USB_D_DEV_TRANS_MAX) { + trans_next = USB_D_DEV_TRANS_MAX; + } else { + /* Must expect multiple of ep size. */ + trans_next -= trans_next & size_mask; + } + } else if (trans_next < ept->size) { + /* Last un-aligned packet should be cached. */ + ept->flags.bits.use_cache = 1; + } + _usbd_ep_set_buf(epn, 0, (uint32_t)&ept->trans_buf[ept->trans_count]); + } + _usbd_ep_set_out_trans(epn, 0, trans_next, 0); + goto _out_rx_exec; + } + } + /* Finish normally. */ + if (is_ctrl) { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1); + } else { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS); + } + /* Use ep0 out cache for next setup packets */ + if (0 == epn) { + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + } + _usb_d_dev_trans_done(ept, USB_TRANS_DONE); + return; + +_out_rx_exec: + if (!isr) { + if (is_ctrl) { + /* Initialize control OUT transaction. */ + + /* Control transfer: SETUP or IN request will abort the + * OUT transactions. + * SETUP: terminate OUT without any notification. + * Trigger SETUP notification. + * IN NAK: finish OUT normally. Notify data done. + */ + _usbd_ep_clear_bank_status(epn, 1); + /* Detect OUT, SETUP, NAK IN */ + inten = USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1; + } else { + /* Initialize normal OUT transaction. */ + inten = USB_D_BANK0_INT_FLAGS; + } + hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); + } + _usbd_ep_set_out_rdy(epn, 0, true); +} + +/** + * \brief Handles setup received interrupt + * \param[in] ept Pointer to endpoint information. + */ +static void _usb_d_dev_handle_setup(struct _usb_d_dev_ep *ept) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + + if (!is_ctrl) { + /* Should never be here! */ + _usbd_ep_ack_setup(epn); + _usbd_ep_stop_setup(epn); + return; + } + /* Control transfer: + * SETUP transaction will terminate IN/OUT transaction, + * and start new transaction with received SETUP packet. + */ + if (_usb_d_dev_ep_is_busy(ept)) { + ept->flags.bits.is_busy = 0; + + /* Stop transfer on either direction. */ + _usbd_ep_set_in_rdy(epn, 1, false); + _usbd_ep_set_out_rdy(epn, 0, false); + } + ept->flags.bits.is_stalled = 0; + + /* Clear status and notify SETUP */ + _usbd_ep_clear_bank_status(epn, 0); + _usbd_ep_clear_bank_status(epn, 1); + _usbd_ep_int_ack(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); + _usbd_ep_int_dis(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); + /* Invoke callback. */ + dev_inst.ep_callbacks.setup(ept->ep); +} + +/** + * \brief Handles stall sent interrupt + * \param[in] ept Pointer to endpoint information. + * \param[in] bank_n Bank number. + */ +static void _usb_d_dev_handle_stall(struct _usb_d_dev_ep *ept, const uint8_t bank_n) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + /* Clear interrupt enable. Leave status there for status check. */ + _usbd_ep_int_stall_en(epn, bank_n, false); + _usb_d_dev_trans_done(ept, USB_TRANS_STALL); +} + +/** + * \brief Handles transaction fail interrupt + * \param[in] ept Pointer to endpoint information. + * \param[in] bank_n Bank number. + */ +static void _usb_d_dev_handle_trfail(struct _usb_d_dev_ep *ept, const uint8_t bank_n) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + const uint8_t fail[2] = {USB_DEVICE_EPINTFLAG_TRFAIL0, USB_DEVICE_EPINTFLAG_TRFAIL1}; + UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; + uint8_t eptype + = bank_n ? hri_usbendpoint_read_EPCFG_EPTYPE1_bf(hw, epn) : hri_usbendpoint_read_EPCFG_EPTYPE0_bf(hw, epn); + bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); + USB_DEVICE_STATUS_BK_Type st; + st.reg = bank[bank_n].STATUS_BK.reg; + + if ((eptype == USB_D_EPTYPE_ISOCH) && st.bit.CRCERR) { + bank[bank_n].STATUS_BK.bit.CRCERR = 0; + hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); + _usb_d_dev_trans_stop(ept, bank_n, USB_TRANS_ERROR); + } else if (st.bit.ERRORFLOW) { + bank[bank_n].STATUS_BK.bit.ERRORFLOW = 0; + hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); + /* Abort control transfer. */ + if (is_ctrl && _usb_d_dev_ep_is_busy(ept)) { + if (bank_n != _usb_d_dev_ep_is_in(ept)) { + _usb_d_dev_trans_stop(ept, _usb_d_dev_ep_is_in(ept), USB_TRANS_DONE); + } + } + } else { + _usbd_ep_clear_bank_status(epn, bank_n); + hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); + } +} + +/** + * \brief Analyze flags for setup transaction + * \param[in] ept Pointer to endpoint information. + * \param[in] flags Endpoint interrupt flags. + */ +static inline void _usb_d_dev_trans_setup_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) +{ + /* + * SETPU is automatically ACKed by hardware + * OUT & IN should be set to NAK when checking SETUP + * No need to check OUT & IN status. + */ + if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { + _usb_d_dev_handle_setup(ept); + } else if (flags & USB_DEVICE_EPINTFLAG_STALL1) { + _usb_d_dev_handle_stall(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_STALL0) { + _usb_d_dev_handle_stall(ept, 0); + } +} + +/** + * \brief Analyze flags for IN transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] flags Endpoint interrupt flags. + */ +static inline void _usb_d_dev_trans_in_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) +{ + /* + * Check IN flags + * If control endpoint, SETUP & OUT is checked to see if abort + */ + if (flags & USB_DEVICE_EPINTFLAG_STALL1) { + _usb_d_dev_handle_stall(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { + _usb_d_dev_handle_trfail(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT1) { + _usb_d_dev_in_next(ept, true); + } else if (_usb_d_dev_ep_is_ctrl(ept)) { + /* Check OUT NAK + * Check SETUP + */ + if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { + _usb_d_dev_handle_trfail(ept, 0); + } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { + _usb_d_dev_handle_setup(ept); + } + } +} + +/** + * \brief Analyze flags for OUT transactions + * \param[in] ept Pointer to endpoint information. + * \param[in] flags Endpoint interrupt flags. + */ +static inline void _usb_d_dev_trans_out_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) +{ + /* + * Check OUT flags. + * If control endpoint, SETUP & IN NAK is checked to see if abort + */ + if (flags & USB_DEVICE_EPINTFLAG_STALL0) { + _usb_d_dev_handle_stall(ept, 0); + } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { + _usb_d_dev_handle_trfail(ept, 0); + } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT0) { + _usb_d_dev_out_next(ept, true); + } else if (_usb_d_dev_ep_is_ctrl(ept)) { + /* Check IN NAK + * Check SETUP + */ + if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { + _usb_d_dev_handle_trfail(ept, 1); + } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { + _usb_d_dev_handle_setup(ept); + } + } +} + +/** + * \brief Handles the endpoint interrupts. + * \param[in] epint Endpoint interrupt summary (by bits). + * \param[in] ept Pointer to endpoint information. + */ +static inline void _usb_d_dev_handle_eps(uint32_t epint, struct _usb_d_dev_ep *ept) +{ + Usb *hw = USB; + + uint8_t flags, mask; + uint8_t epn = USB_EP_GET_N(ept->ep); + + if (!(epint & (1u << epn))) { + return; + } + flags = hw->DEVICE.DeviceEndpoint[epn].EPINTFLAG.reg; + mask = hw->DEVICE.DeviceEndpoint[epn].EPINTENSET.reg; + flags &= mask; + if (flags) { + if (!_usb_d_dev_ep_is_busy(ept)) { + _usb_d_dev_trans_setup_isr(ept, flags); + } else if (_usb_d_dev_ep_is_in(ept)) { + _usb_d_dev_trans_in_isr(ept, flags); + } else { + _usb_d_dev_trans_out_isr(ept, flags); + } + } +} + +/** + * \brief USB device interrupt handler + * \param[in] unused The parameter is not used + */ +static void _usb_d_dev_handler(void) +{ + Usb * hw = USB; + uint8_t i; + + uint16_t epint = hw->DEVICE.EPINTSMRY.reg; + if (0 == epint) { + if (_usb_d_dev_handle_nep()) { + return; + } + } + /* Handle endpoints */ + for (i = 0; i < USB_D_N_EP; i++) { + struct _usb_d_dev_ep *ept = &dev_inst.ep[i]; + if (ept->ep == 0xFF) { + continue; + } + _usb_d_dev_handle_eps(epint, ept); + } +} + +/** + * \brief Reset all endpoint software instances + */ +static void _usb_d_dev_reset_epts(void) +{ + uint8_t i; + for (i = 0; i < USB_D_N_EP; i++) { + _usb_d_dev_trans_done(&dev_inst.ep[i], USB_TRANS_RESET); + dev_inst.ep[i].ep = 0xFF; + dev_inst.ep[i].flags.u8 = 0; + } + memset(prvt_inst.desc_table, 0, sizeof(UsbDeviceDescriptor) * (CONF_USB_D_MAX_EP_N + 1)); +} + +int32_t _usb_d_dev_init(void) +{ + Usb * hw = USB; + uint8_t speed = CONF_USB_D_SPEED; + const uint8_t spdconf[4] = { + USB_DEVICE_CTRLB_SPDCONF(1), /* LS */ + USB_DEVICE_CTRLB_SPDCONF(0), /* FS */ + 0, + 0 /* Reserved */ + }; + + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + if (hri_usbdevice_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + hri_usbdevice_set_CTRLA_SWRST_bit(hw); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + + dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)_dummy_func_no_return; + dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)_dummy_func_no_return; + + dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)_dummy_func_no_return; + dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)_dummy_func_no_return; + dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)_dummy_func_no_return; + + _usb_d_dev_reset_epts(); + + _usb_load_calib(); + + hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_RUNSTDBY); + hri_usbdevice_write_DESCADD_reg(hw, (uint32_t)prvt_inst.desc_table); + hri_usbdevice_write_CTRLB_reg(hw, spdconf[speed] | USB_DEVICE_CTRLB_DETACH); + + return ERR_NONE; +} + +void _usb_d_dev_deinit(void) +{ + Usb *hw = USB; + + while (_usb_d_dev_disable() < 0) + ; + + hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_SWRST); + + NVIC_DisableIRQ(USB_0_IRQn); + NVIC_ClearPendingIRQ(USB_0_IRQn); + NVIC_DisableIRQ(USB_1_IRQn); + NVIC_ClearPendingIRQ(USB_1_IRQn); + NVIC_DisableIRQ(USB_2_IRQn); + NVIC_ClearPendingIRQ(USB_2_IRQn); + NVIC_DisableIRQ(USB_3_IRQn); + NVIC_ClearPendingIRQ(USB_3_IRQn); +} + +int32_t _usb_d_dev_enable(void) +{ + Usb * hw = USB; + uint8_t ctrla; + + if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { + return -USB_ERR_DENIED; + } + ctrla = hri_usbdevice_read_CTRLA_reg(hw); + if ((ctrla & USB_CTRLA_ENABLE) == 0) { + hri_usbdevice_write_CTRLA_reg(hw, ctrla | USB_CTRLA_ENABLE); + } + + NVIC_EnableIRQ(USB_0_IRQn); + NVIC_EnableIRQ(USB_1_IRQn); + NVIC_EnableIRQ(USB_2_IRQn); + NVIC_EnableIRQ(USB_3_IRQn); + + hri_usbdevice_set_INTEN_reg(hw, + USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER + | USB_D_SUSPEND_INT_FLAGS); + + return ERR_NONE; +} + +int32_t _usb_d_dev_disable(void) +{ + Usb * hw = USB; + uint8_t ctrla; + + if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { + return -USB_ERR_DENIED; + } + + ctrla = hri_usbdevice_read_CTRLA_reg(hw); + if (ctrla & USB_CTRLA_ENABLE) { + hri_usbdevice_write_CTRLA_reg(hw, ctrla & ~USB_CTRLA_ENABLE); + } + + NVIC_DisableIRQ(USB_0_IRQn); + NVIC_DisableIRQ(USB_1_IRQn); + NVIC_DisableIRQ(USB_2_IRQn); + NVIC_DisableIRQ(USB_3_IRQn); + + hri_usbdevice_clear_INTEN_reg(hw, + USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER + | USB_D_SUSPEND_INT_FLAGS + | USB_D_WAKEUP_INT_FLAGS); + + return ERR_NONE; +} + +void _usb_d_dev_attach(void) +{ + hri_usbdevice_clear_CTRLB_DETACH_bit(USB); +} + +void _usb_d_dev_detach(void) +{ + hri_usbdevice_set_CTRLB_DETACH_bit(USB); +} + +#ifndef USB_FSMSTATUS_FSMSTATE_ON +#define USB_FSMSTATUS_FSMSTATE_ON USB_FSMSTATUS_FSMSTATE(2ul) +#endif +void _usb_d_dev_send_remotewakeup(void) +{ + uint32_t retry = CONF_USB_RMT_WKUP_RETRY; + _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); + while ((USB_FSMSTATUS_FSMSTATE_ON != hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(USB)) && (retry--)) { + USB->DEVICE.CTRLB.bit.UPRSM = 1; + } +} + +enum usb_speed _usb_d_dev_get_speed(void) +{ + uint8_t sp = (enum usb_speed)hri_usbdevice_read_STATUS_SPEED_bf(USB); + const enum usb_speed speed[2] = {USB_SPEED_FS, USB_SPEED_LS}; + + return speed[sp]; +} + +void _usb_d_dev_set_address(uint8_t addr) +{ + hri_usbdevice_write_DADD_reg(USB, USB_DEVICE_DADD_ADDEN | USB_DEVICE_DADD_DADD(addr)); +} + +uint8_t _usb_d_dev_get_address(void) +{ + uint8_t addr = hri_usbdevice_read_DADD_DADD_bf(USB); + return addr; +} + +uint16_t _usb_d_dev_get_frame_n(void) +{ + uint16_t fn = hri_usbdevice_read_FNUM_FNUM_bf(USB); + return fn; +} + +uint8_t _usb_d_dev_get_uframe_n(void) +{ + uint8_t ufn = hri_usbdevice_read_FNUM_MFNUM_bf(USB); + return ufn; +} + +/** + * \brief Start a setup transaction + * \param[in] ept Endpoint information. + */ +static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ept->ep); + + _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); + _usbd_ep_set_out_trans(epn, 0, ept->size, 0); + + hri_usbendpoint_clear_EPSTATUS_reg(hw, epn, USB_DEVICE_EPSTATUS_STALLRQ(0x3) | USB_DEVICE_EPSTATUS_BK1RDY); + _usbd_ep_set_out_rdy(epn, 0, false); + + hri_usbendpoint_set_EPINTEN_reg(hw, epn, USB_D_SETUP_INT_FLAGS); +} + +int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz) +{ + return _usb_d_dev_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_siz); +} + +int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_siz) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + uint8_t ep_type = attr & USB_EP_XTYPE_MASK; + const struct _usb_ep_cfg_item *pcfg = &_usb_ep_cfgs[epn]; + + if (epn > CONF_USB_D_MAX_EP_N) { + return -USB_ERR_PARAM; + } + if (ept->ep != 0xFF) { + return -USB_ERR_REDO; + } + if (ep_type == USB_EP_XTYPE_CTRL) { + struct _usb_d_dev_ep *ept_in = _usb_d_dev_ept(epn, !dir); + if (ept_in->ep != 0xFF) { + return -USB_ERR_REDO; + } + if (pcfg->cache == NULL) { + return -USB_ERR_FUNC; + } + } + if ((dir ? pcfg->i_cache : pcfg->cache) && ((dir ? pcfg->i_size : pcfg->size) < max_pkt_siz)) { + return -USB_ERR_FUNC; + } + + /* Initialize EP n settings */ + ept->cache = (uint8_t *)(dir ? pcfg->i_cache : pcfg->cache); + ept->size = max_pkt_siz; + ept->flags.u8 = (ep_type + 1); + ept->ep = ep; + + return USB_OK; +} + +void _usb_d_dev_ep_deinit(uint8_t ep) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { + return; + } + + /* Finish pending transactions. */ + _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); + + /* Disable the endpoint. */ + if (_usb_d_dev_ep_is_ctrl(ept)) { + hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg = 0; + } else if (USB_EP_GET_DIR(ep)) { + hw->DEVICE.DeviceEndpoint[USB_EP_GET_N(ep)].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + } else { + hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + } + ept->flags.u8 = 0; + ept->ep = 0xFF; +} + +int32_t _usb_d_dev_ep_enable(const uint8_t ep) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + uint8_t epcfg = hri_usbendpoint_read_EPCFG_reg(hw, epn); + UsbDeviceDescBank * bank; + + if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { + return -USB_ERR_PARAM; + } + + bank = prvt_inst.desc_table[epn].DeviceDescBank; + if (ept->flags.bits.eptype == USB_D_EPTYPE_CTRL) { + if (epcfg & (USB_DEVICE_EPCFG_EPTYPE1_Msk | USB_DEVICE_EPCFG_EPTYPE0_Msk)) { + return -USB_ERR_REDO; + } + hri_usbendpoint_write_EPCFG_reg(hw, epn, USB_D_EPCFG_CTRL); + bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) + | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + bank[1].PCKSIZE.reg + = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + /* By default, control endpoint accept SETUP and NAK all other token. */ + _usbd_ep_set_out_rdy(epn, 0, false); + _usbd_ep_set_in_rdy(epn, 1, false); + + _usbd_ep_clear_bank_status(epn, 0); + _usbd_ep_clear_bank_status(epn, 1); + + /* Enable SETUP reception for control endpoint. */ + _usb_d_dev_trans_setup(ept); + + } else if (dir) { + if (epcfg & USB_DEVICE_EPCFG_EPTYPE1_Msk) { + return -USB_ERR_REDO; + } + epcfg |= USB_DEVICE_EPCFG_EPTYPE1(ept->flags.bits.eptype); + hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); + + bank[1].PCKSIZE.reg + = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + + /* By default, IN endpoint will NAK all token. */ + _usbd_ep_set_in_rdy(epn, 1, false); + _usbd_ep_clear_bank_status(epn, 1); + + } else { + + if (epcfg & USB_DEVICE_EPCFG_EPTYPE0_Msk) { + return -USB_ERR_REDO; + } + epcfg |= USB_DEVICE_EPCFG_EPTYPE0(ept->flags.bits.eptype); + hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); + + bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) + | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); + + /* By default, OUT endpoint will NAK all token. */ + _usbd_ep_set_out_rdy(epn, 0, false); + _usbd_ep_clear_bank_status(epn, 0); + } + + return USB_OK; +} + +void _usb_d_dev_ep_disable(const uint8_t ep) +{ + Usb * hw = USB; + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); + if (_usb_d_dev_ep_is_ctrl(ept)) { + hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_ALL_INT_FLAGS); + } +} + +/** + * \brief Get endpoint stall status + * \param[in] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \return Stall status. + * \retval \c true Endpoint is stalled. + * \retval \c false Endpoint is not stalled. + */ +static inline int32_t _usb_d_dev_ep_stall_get(struct _usb_d_dev_ep *ept, bool dir) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + return _usbd_ep_is_stalled(epn, dir); +} + +/** + * \brief Set endpoint stall + * \param[in, out] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \return Always 0, success. + */ +static inline int32_t _usb_d_dev_ep_stall_set(struct _usb_d_dev_ep *ept, bool dir) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + _usbd_ep_set_stall(epn, dir, true); + _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); + ept->flags.bits.is_stalled = 1; + /* In stall interrupt abort the transfer. */ + return ERR_NONE; +} + +/** + * \brief Clear endpoint stall + * \param[in, out] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \return Always 0, success. + */ +static inline int32_t _usb_d_dev_ep_stall_clr(struct _usb_d_dev_ep *ept, bool dir) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + bool is_stalled = _usbd_ep_is_stalled(epn, dir); + if (!is_stalled) { + return ERR_NONE; + } + _usbd_ep_set_stall(epn, dir, false); + _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); + if (_usbd_ep_is_stall_sent(epn, dir)) { + _usbd_ep_ack_stall(epn, dir); + _usbd_ep_set_toggle(epn, dir, 0); + } + if (_usb_d_dev_ep_is_ctrl(ept)) { + if ((hri_usbendpoint_read_EPSTATUS_reg(USB, epn) & USB_DEVICE_EPSTATUS_STALLRQ_Msk) == 0) { + ept->flags.bits.is_stalled = 0; + } + } else { + ept->flags.bits.is_stalled = 0; + } + return ERR_NONE; +} + +int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + int32_t rc; + + if (epn > CONF_USB_D_MAX_EP_N) { + return -USB_ERR_PARAM; + } + + if (USB_EP_STALL_SET == ctrl) { + rc = _usb_d_dev_ep_stall_set(ept, dir); + } else if (USB_EP_STALL_CLR == ctrl) { + rc = _usb_d_dev_ep_stall_clr(ept, dir); + } else { + rc = _usb_d_dev_ep_stall_get(ept, dir); + } + return rc; +} + +/** + * \brief Finish the transaction and invoke callback + * \param[in, out] ept Pointer to endpoint information. + * \param[in] code Information code passed. + */ +static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t code) +{ + if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { + return; + } + ept->flags.bits.is_busy = 0; + dev_inst.ep_callbacks.done(ept->ep, code, ept->trans_count); +} + +/** + * \brief Terminate the transaction with specific status code + * \param[in, out] ept Pointer to endpoint information. + * \param[in] dir Endpoint direction. + * \param[in] code Information code passed. + */ +static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code) +{ + uint8_t epn = USB_EP_GET_N(ept->ep); + ; + const uint8_t intflags[2] = {USB_D_BANK0_INT_FLAGS, USB_D_BANK1_INT_FLAGS}; + if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { + return; + } + /* Stop transfer */ + if (dir) { + /* NAK IN */ + _usbd_ep_set_in_rdy(epn, 1, false); + } else { + /* NAK OUT */ + _usbd_ep_set_out_rdy(epn, 0, false); + } + _usbd_ep_int_ack(epn, intflags[dir]); + _usbd_ep_int_dis(epn, intflags[dir]); + _usb_d_dev_trans_done(ept, code); +} + +int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf) +{ + uint8_t epn = USB_EP_GET_N(ep); + UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; + uint32_t addr = bank[0].ADDR.reg; + uint16_t bytes = bank[0].PCKSIZE.bit.BYTE_COUNT; + + if (epn > CONF_USB_D_MAX_EP_N || !req_buf) { + return -USB_ERR_PARAM; + } + if (!_usbd_ep_is_ctrl(epn)) { + return -USB_ERR_FUNC; + } + if (!_usbd_ep_is_setup(epn)) { + return ERR_NONE; + } + memcpy(req_buf, (void *)addr, 8); + _usbd_ep_ack_setup(epn); + + return bytes; +} + +int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans) +{ + uint8_t epn = USB_EP_GET_N(trans->ep); + bool dir = USB_EP_GET_DIR(trans->ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + + uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); + bool size_n_aligned = (trans->size & size_mask); + + bool use_cache = false; + + volatile hal_atomic_t flags; + + if (epn > CONF_USB_D_MAX_EP_N) { + return -USB_ERR_PARAM; + } + + /* Cases that needs cache: + * 1. Buffer not in RAM (cache all). + * 2. IN/OUT with unaligned buffer (cache all). + * 3. OUT with unaligned packet size (cache last packet). + * 4. OUT size < 8 (sub-case for 3). + */ + if (!_usb_is_addr4dma(trans->buf, trans->size) || (!_usb_is_aligned(trans->buf)) + || (!dir && (trans->size < ept->size))) { + if (!ept->cache) { + return -33; + return -USB_ERR_FUNC; + } + /* Use cache all the time. */ + use_cache = true; + } + if (!dir && size_n_aligned) { + if (!ept->cache) { + return -USB_ERR_PARAM; + } + /* Set 'use_cache' on last packet. */ + } + + /* Check halt */ + if (ept->flags.bits.is_stalled) { + return USB_HALTED; + } + + /* Try to start transactions. */ + + atomic_enter_critical(&flags); + if (_usb_d_dev_ep_is_busy(ept)) { + atomic_leave_critical(&flags); + return USB_BUSY; + } + ept->flags.bits.is_busy = 1; + atomic_leave_critical(&flags); + + /* Copy transaction information. */ + ept->trans_buf = trans->buf; + ept->trans_size = trans->size; + ept->trans_count = 0; + + ept->flags.bits.dir = dir; + ept->flags.bits.use_cache = use_cache; + ept->flags.bits.need_zlp = (trans->zlp && (!size_n_aligned)); + + if (dir) { + _usb_d_dev_in_next(ept, false); + } else { + _usb_d_dev_out_next(ept, false); + } + + return ERR_NONE; +} + +void _usb_d_dev_ep_abort(const uint8_t ep) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + if (epn > CONF_USB_D_MAX_EP_N) { + return; + } + _usb_d_dev_trans_stop(ept, dir, USB_TRANS_ABORT); +} + +int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat) +{ + uint8_t epn = USB_EP_GET_N(ep); + bool dir = USB_EP_GET_DIR(ep); + struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); + bool busy, stall; + + if (epn > CONF_USB_D_MAX_EP_N) { + return USB_ERR_PARAM; + } + busy = ept->flags.bits.is_busy; + stall = ept->flags.bits.is_stalled; + if (stat) { + stat->stall = stall; + stat->busy = busy; + stat->setup = USB->DEVICE.DeviceEndpoint[epn].EPINTFLAG.bit.RXSTP; + stat->dir = ept->flags.bits.dir; + stat->size = ept->trans_size; + stat->count = ept->trans_count; + stat->ep = ep; + stat->xtype = ept->flags.bits.eptype - 1; + } + if (stall) { + return USB_HALTED; + } + if (busy) { + return USB_BUSY; + } + return USB_OK; +} + +void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) +{ + FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; + if (type == USB_D_CB_EVENT) { + dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)f; + } else if (type == USB_D_CB_SOF) { + dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)f; + } +} + +void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func) +{ + FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; + if (type == USB_D_DEV_EP_CB_SETUP) { + dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)f; + } else if (type == USB_D_DEV_EP_CB_MORE) { + dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)f; + } else if (type == USB_D_DEV_EP_CB_DONE) { + dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)f; + } +} + +/** +* \brief USB interrupt handler +*/ +void USB_0_Handler(void) +{ + + _usb_d_dev_handler(); +} +/** +* \brief USB interrupt handler +*/ +void USB_1_Handler(void) +{ + + _usb_d_dev_handler(); +} +/** +* \brief USB interrupt handler +*/ +void USB_2_Handler(void) +{ + + _usb_d_dev_handler(); +} +/** +* \brief USB interrupt handler +*/ +void USB_3_Handler(void) +{ + + _usb_d_dev_handler(); +} diff --git a/atmel-samd/asf4/samd51/hri/hri_ac_d51.h b/atmel-samd/asf4/samd51/hri/hri_ac_d51.h new file mode 100644 index 0000000000000..37688c2ce774d --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_ac_d51.h @@ -0,0 +1,1827 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_AC_COMPONENT_ +#ifndef _HRI_AC_D51_H_INCLUDED_ +#define _HRI_AC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_calib_reg_t; +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= ~AC_CALIB_BIAS0_Msk; + tmp |= AC_CALIB_BIAS0(data); + ((Ac *)hw)->CALIB.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) +{ + return ((Ac *)hw)->CALIB.reg; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_D51_H_INCLUDED */ +#endif /* _SAMD51_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_adc_d51.h b/atmel-samd/asf4/samd51/hri/hri_adc_d51.h new file mode 100644 index 0000000000000..be2d352d2dac6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_adc_d51.h @@ -0,0 +1,3736 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_ADC_COMPONENT_ +#ifndef _HRI_ADC_D51_H_INCLUDED_ +#define _HRI_ADC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrla_reg_t; +typedef uint16_t hri_adc_ctrlb_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_ress_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_dseqctrl_reg_t; +typedef uint32_t hri_adc_dseqdata_reg_t; +typedef uint32_t hri_adc_dseqstat_reg_t; +typedef uint32_t hri_adc_syncbusy_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_status_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQDATA.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_SLAVEEN; + tmp |= value << ADC_CTRLA_SLAVEEN_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_R2R; + tmp |= value << ADC_CTRLA_R2R_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_DUALSEL_Msk; + tmp |= ADC_CTRLA_DUALSEL(data); + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_PRESCALER_Msk; + tmp |= ADC_CTRLA_PRESCALER(data); + ((Adc *)hw)->CTRLA.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DIFFMODE; + tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DSEQSTOP; + tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_LEFTADJ; + tmp |= value << ADC_CTRLB_LEFTADJ_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_FREERUN; + tmp |= value << ADC_CTRLB_FREERUN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_CORREN; + tmp |= value << ADC_CTRLB_CORREN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINSS; + tmp |= value << ADC_CTRLB_WINSS_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_RESSEL_Msk; + tmp |= ADC_CTRLB_RESSEL(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINMODE_Msk; + tmp |= ADC_CTRLB_WINMODE(data); + ((Adc *)hw)->CTRLB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_INPUTCTRL; + tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_CTRLB; + tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_REFCTRL; + tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AVGCTRL; + tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_SAMPCTRL; + tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINLT; + tmp |= value << ADC_DSEQCTRL_WINLT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINUT; + tmp |= value << ADC_DSEQCTRL_WINUT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_GAINCORR; + tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_OFFSETCORR; + tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AUTOSTART; + tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DSEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASR2R_Msk; + tmp |= ADC_CALIB_BIASR2R(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->STATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL + | ADC_SYNCBUSY_WINLT + | ADC_SYNCBUSY_WINUT + | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->DSEQSTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) +{ + return ((Adc *)hw)->DSEQSTAT.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) +{ + return ((Adc *)hw)->RESS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_D51_H_INCLUDED */ +#endif /* _SAMD51_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_aes_d51.h b/atmel-samd/asf4/samd51/hri/hri_aes_d51.h new file mode 100644 index 0000000000000..c9b1313d91bfe --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_aes_d51.h @@ -0,0 +1,1296 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_AES_COMPONENT_ +#ifndef _HRI_AES_D51_H_INCLUDED_ +#define _HRI_AES_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= ~AES_DBGCTRL_DBGRUN; + tmp |= value << AES_DBGCTRL_DBGRUN_Pos; + ((Aes *)hw)->DBGCTRL.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) +{ + return ((Aes *)hw)->DBGCTRL.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_D51_H_INCLUDED */ +#endif /* _SAMD51_AES_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_ccl_d51.h b/atmel-samd/asf4/samd51/hri/hri_ccl_d51.h new file mode 100644 index 0000000000000..e218cc997d9dd --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_ccl_d51.h @@ -0,0 +1,785 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_CCL_COMPONENT_ +#ifndef _HRI_CCL_D51_H_INCLUDED_ +#define _HRI_CCL_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_D51_H_INCLUDED */ +#endif /* _SAMD51_CCL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_cmcc_d51.h b/atmel-samd/asf4/samd51/hri/hri_cmcc_d51.h new file mode 100644 index 0000000000000..d67c14b7c08a2 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_cmcc_d51.h @@ -0,0 +1,370 @@ +/** + * \file + * + * \brief SAM CMCC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_CMCC_COMPONENT_ +#ifndef _HRI_CMCC_D51_H_INCLUDED_ +#define _HRI_CMCC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) +#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CMCC_CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_cmcc_cfg_reg_t; +typedef uint32_t hri_cmcc_ctrl_reg_t; +typedef uint32_t hri_cmcc_lckway_reg_t; +typedef uint32_t hri_cmcc_maint0_reg_t; +typedef uint32_t hri_cmcc_maint1_reg_t; +typedef uint32_t hri_cmcc_mcfg_reg_t; +typedef uint32_t hri_cmcc_mctrl_reg_t; +typedef uint32_t hri_cmcc_men_reg_t; +typedef uint32_t hri_cmcc_msr_reg_t; +typedef uint32_t hri_cmcc_sr_reg_t; +typedef uint32_t hri_cmcc_type_reg_t; + +static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT0.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT1.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->CFG.reg; +} + +static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->LCKWAY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) +{ + return ((Cmcc *)hw)->LCKWAY.reg; +} + +static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MCFG.reg; +} + +static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MEN.reg; +} + +static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; +} + +static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; +} + +static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->TYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) +{ + return ((Cmcc *)hw)->TYPE.reg; +} + +static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) +{ + return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->SR.reg; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MSR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CMCC_D51_H_INCLUDED */ +#endif /* _SAMD51_CMCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_d51.h b/atmel-samd/asf4/samd51/hri/hri_d51.h new file mode 100644 index 0000000000000..fe1b0f91b7bf1 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_d51.h @@ -0,0 +1,85 @@ +/** + * \file + * + * \brief SAM D51 HRI top-level header file + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifndef _HRI_D51_H_INCLUDED_ +#define _HRI_D51_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_D51_H_INCLUDED_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_dac_d51.h b/atmel-samd/asf4/samd51/hri/hri_dac_d51.h new file mode 100644 index 0000000000000..ba27fd5297c23 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_dac_d51.h @@ -0,0 +1,1701 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_DAC_COMPONENT_ +#ifndef _HRI_DAC_D51_H_INCLUDED_ +#define _HRI_DAC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_dacctrl_reg_t; +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint16_t hri_dac_result_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; +} + +static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; +} + +static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; +} + +static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; +} + +static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; +} + +static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; +} + +static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; +} + +static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; +} + +static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; +} + +static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; +} + +static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; +} + +static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA[index].reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF[index].reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DIFF; + tmp |= value << DAC_CTRLB_DIFF_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI0; + tmp |= value << DAC_EVCTRL_STARTEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI1; + tmp |= value << DAC_EVCTRL_STARTEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO0; + tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO1; + tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI0; + tmp |= value << DAC_EVCTRL_INVEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI1; + tmp |= value << DAC_EVCTRL_INVEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO0; + tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO1; + tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_LEFTADJ; + tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_ENABLE; + tmp |= value << DAC_DACCTRL_ENABLE_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_FEXT; + tmp |= value << DAC_DACCTRL_FEXT_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_RUNSTDBY; + tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_DITHER; + tmp |= value << DAC_DACCTRL_DITHER_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_CCTRL_Msk; + tmp |= DAC_DACCTRL_CCTRL(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_REFRESH_Msk; + tmp |= DAC_DACCTRL_REFRESH(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_OSR_Msk; + tmp |= DAC_DACCTRL_OSR(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Dac *)hw)->DACCTRL[index].reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; +} + +static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->RESULT[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) +{ + return ((Dac *)hw)->RESULT[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_D51_H_INCLUDED */ +#endif /* _SAMD51_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_dmac_d51.h b/atmel-samd/asf4/samd51/hri/hri_dmac_d51.h new file mode 100644 index 0000000000000..71aeb73c1b6ae --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_dmac_d51.h @@ -0,0 +1,6844 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_D51_H_INCLUDED_ +#define _HRI_DMAC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrla_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacchannel_chctrla_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrlb_reg_t; +typedef uint8_t hri_dmac_chevctrl_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chprilvl_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmacchannel_chctrlb_reg_t; +typedef uint8_t hri_dmacchannel_chevctrl_reg_t; +typedef uint8_t hri_dmacchannel_chintenset_reg_t; +typedef uint8_t hri_dmacchannel_chintflag_reg_t; +typedef uint8_t hri_dmacchannel_chprilvl_reg_t; +typedef uint8_t hri_dmacchannel_chstatus_reg_t; + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; + tmp |= DMAC_CRCCTRL_CRCMODE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS0_Msk; + tmp |= DMAC_PRICTRL0_QOS0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS1_Msk; + tmp |= DMAC_PRICTRL0_QOS1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS2_Msk; + tmp |= DMAC_PRICTRL0_QOS2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS3_Msk; + tmp |= DMAC_PRICTRL0_QOS3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_CRCERR; + tmp |= value << DMAC_INTPEND_CRCERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; + tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = data; + ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((DmacChannel *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLB.reg; +} + +static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((DmacChannel *)hw)->CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHPRILVL.reg; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHEVCTRL.reg; +} + +static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHSTATUS.reg; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; +} + +static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; +} + +static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_D51_H_INCLUDED */ +#endif /* _SAMD51_DMAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_dsu_d51.h b/atmel-samd/asf4/samd51/hri/hri_dsu_d51.h new file mode 100644 index 0000000000000..b7128008d2a4f --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_dsu_d51.h @@ -0,0 +1,3766 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (C) 2017 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_DSU_COMPONENT_ +#ifndef _HRI_DSU_D51_H_INCLUDED_ +#define _HRI_DSU_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cfg_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_dcfg_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_mbafail_reg_t; +typedef uint32_t hri_dsu_mbbusy0_reg_t; +typedef uint32_t hri_dsu_mbconfig_reg_t; +typedef uint32_t hri_dsu_mbcontext_reg_t; +typedef uint32_t hri_dsu_mbctrl_reg_t; +typedef uint32_t hri_dsu_mbdexp_reg_t; +typedef uint32_t hri_dsu_mbdfail_reg_t; +typedef uint32_t hri_dsu_mbenable0_reg_t; +typedef uint32_t hri_dsu_mbgstat_reg_t; +typedef uint32_t hri_dsu_mbstatus0_reg_t; +typedef uint32_t hri_dsu_mbword_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; +} + +static inline bool hri_dsu_get_STATUSB_TDCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD0) >> DSU_STATUSB_TDCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_TDCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD1) >> DSU_STATUSB_TDCCD1_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline hri_dsu_mbdfail_reg_t hri_dsu_get_MBDFAIL_DATA_bf(const void *const hw, hri_dsu_mbdfail_reg_t mask) +{ + return (((Dsu *)hw)->MBDFAIL.reg & DSU_MBDFAIL_DATA(mask)) >> DSU_MBDFAIL_DATA_Pos; +} + +static inline hri_dsu_mbdfail_reg_t hri_dsu_read_MBDFAIL_DATA_bf(const void *const hw) +{ + return (((Dsu *)hw)->MBDFAIL.reg & DSU_MBDFAIL_DATA_Msk) >> DSU_MBDFAIL_DATA_Pos; +} + +static inline hri_dsu_mbdfail_reg_t hri_dsu_get_MBDFAIL_reg(const void *const hw, hri_dsu_mbdfail_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBDFAIL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_mbdfail_reg_t hri_dsu_read_MBDFAIL_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBDFAIL.reg; +} + +static inline hri_dsu_mbdexp_reg_t hri_dsu_get_MBDEXP_DATA_bf(const void *const hw, hri_dsu_mbdexp_reg_t mask) +{ + return (((Dsu *)hw)->MBDEXP.reg & DSU_MBDEXP_DATA(mask)) >> DSU_MBDEXP_DATA_Pos; +} + +static inline hri_dsu_mbdexp_reg_t hri_dsu_read_MBDEXP_DATA_bf(const void *const hw) +{ + return (((Dsu *)hw)->MBDEXP.reg & DSU_MBDEXP_DATA_Msk) >> DSU_MBDEXP_DATA_Pos; +} + +static inline hri_dsu_mbdexp_reg_t hri_dsu_get_MBDEXP_reg(const void *const hw, hri_dsu_mbdexp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBDEXP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_mbdexp_reg_t hri_dsu_read_MBDEXP_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBDEXP.reg; +} + +static inline hri_dsu_mbafail_reg_t hri_dsu_get_MBAFAIL_ADDR_bf(const void *const hw, hri_dsu_mbafail_reg_t mask) +{ + return (((Dsu *)hw)->MBAFAIL.reg & DSU_MBAFAIL_ADDR(mask)) >> DSU_MBAFAIL_ADDR_Pos; +} + +static inline hri_dsu_mbafail_reg_t hri_dsu_read_MBAFAIL_ADDR_bf(const void *const hw) +{ + return (((Dsu *)hw)->MBAFAIL.reg & DSU_MBAFAIL_ADDR_Msk) >> DSU_MBAFAIL_ADDR_Pos; +} + +static inline hri_dsu_mbafail_reg_t hri_dsu_get_MBAFAIL_reg(const void *const hw, hri_dsu_mbafail_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBAFAIL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_mbafail_reg_t hri_dsu_read_MBAFAIL_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBAFAIL.reg; +} + +static inline bool hri_dsu_get_MBCONTEXT_PORT_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_PORT) >> DSU_MBCONTEXT_PORT_Pos; +} + +static inline hri_dsu_mbcontext_reg_t hri_dsu_get_MBCONTEXT_SUBSTEP_bf(const void *const hw, + hri_dsu_mbcontext_reg_t mask) +{ + return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_SUBSTEP(mask)) >> DSU_MBCONTEXT_SUBSTEP_Pos; +} + +static inline hri_dsu_mbcontext_reg_t hri_dsu_read_MBCONTEXT_SUBSTEP_bf(const void *const hw) +{ + return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_SUBSTEP_Msk) >> DSU_MBCONTEXT_SUBSTEP_Pos; +} + +static inline hri_dsu_mbcontext_reg_t hri_dsu_get_MBCONTEXT_STEP_bf(const void *const hw, hri_dsu_mbcontext_reg_t mask) +{ + return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_STEP(mask)) >> DSU_MBCONTEXT_STEP_Pos; +} + +static inline hri_dsu_mbcontext_reg_t hri_dsu_read_MBCONTEXT_STEP_bf(const void *const hw) +{ + return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_STEP_Msk) >> DSU_MBCONTEXT_STEP_Pos; +} + +static inline hri_dsu_mbcontext_reg_t hri_dsu_get_MBCONTEXT_reg(const void *const hw, hri_dsu_mbcontext_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCONTEXT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_mbcontext_reg_t hri_dsu_read_MBCONTEXT_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBCONTEXT.reg; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY0_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY0) >> DSU_MBBUSY0_BUSY0_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY1_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY1) >> DSU_MBBUSY0_BUSY1_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY2_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY2) >> DSU_MBBUSY0_BUSY2_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY3_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY3) >> DSU_MBBUSY0_BUSY3_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY4_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY4) >> DSU_MBBUSY0_BUSY4_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY5_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY5) >> DSU_MBBUSY0_BUSY5_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY6_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY6) >> DSU_MBBUSY0_BUSY6_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY7_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY7) >> DSU_MBBUSY0_BUSY7_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY8_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY8) >> DSU_MBBUSY0_BUSY8_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY9_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY9) >> DSU_MBBUSY0_BUSY9_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY10_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY10) >> DSU_MBBUSY0_BUSY10_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY11_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY11) >> DSU_MBBUSY0_BUSY11_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY12_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY12) >> DSU_MBBUSY0_BUSY12_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY13_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY13) >> DSU_MBBUSY0_BUSY13_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY14_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY14) >> DSU_MBBUSY0_BUSY14_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY15_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY15) >> DSU_MBBUSY0_BUSY15_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY16_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY16) >> DSU_MBBUSY0_BUSY16_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY17_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY17) >> DSU_MBBUSY0_BUSY17_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY18_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY18) >> DSU_MBBUSY0_BUSY18_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY19_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY19) >> DSU_MBBUSY0_BUSY19_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY20_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY20) >> DSU_MBBUSY0_BUSY20_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY21_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY21) >> DSU_MBBUSY0_BUSY21_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY22_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY22) >> DSU_MBBUSY0_BUSY22_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY23_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY23) >> DSU_MBBUSY0_BUSY23_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY24_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY24) >> DSU_MBBUSY0_BUSY24_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY25_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY25) >> DSU_MBBUSY0_BUSY25_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY26_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY26) >> DSU_MBBUSY0_BUSY26_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY27_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY27) >> DSU_MBBUSY0_BUSY27_Pos; +} + +static inline bool hri_dsu_get_MBBUSY0_BUSY28_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY28) >> DSU_MBBUSY0_BUSY28_Pos; +} + +static inline hri_dsu_mbbusy0_reg_t hri_dsu_get_MBBUSY0_reg(const void *const hw, hri_dsu_mbbusy0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBBUSY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_mbbusy0_reg_t hri_dsu_read_MBBUSY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBBUSY0.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_ETBRAMEN; + tmp |= value << DSU_CFG_ETBRAMEN_Pos; + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_LQOS_Msk; + tmp |= DSU_CFG_LQOS(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; + tmp |= DSU_CFG_DCCDMALEVEL(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) +{ + return ((Dsu *)hw)->CFG.reg; +} + +static inline void hri_dsu_set_MBCTRL_SWRST_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg |= DSU_MBCTRL_SWRST; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBCTRL_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCTRL.reg; + tmp = (tmp & DSU_MBCTRL_SWRST) >> DSU_MBCTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_set_MBCTRL_ENABLE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg |= DSU_MBCTRL_ENABLE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBCTRL_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCTRL.reg; + tmp = (tmp & DSU_MBCTRL_ENABLE) >> DSU_MBCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBCTRL.reg; + tmp &= ~DSU_MBCTRL_ENABLE; + tmp |= value << DSU_MBCTRL_ENABLE_Pos; + ((Dsu *)hw)->MBCTRL.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBCTRL_ENABLE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg &= ~DSU_MBCTRL_ENABLE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBCTRL_ENABLE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg ^= DSU_MBCTRL_ENABLE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbctrl_reg_t hri_dsu_get_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCTRL.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbctrl_reg_t hri_dsu_read_MBCTRL_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBCTRL.reg; +} + +static inline void hri_dsu_set_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg |= DSU_MBCONFIG_DEFRDMARGIN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp = (tmp & DSU_MBCONFIG_DEFRDMARGIN) >> DSU_MBCONFIG_DEFRDMARGIN_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBCONFIG_DEFRDMARGIN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp &= ~DSU_MBCONFIG_DEFRDMARGIN; + tmp |= value << DSU_MBCONFIG_DEFRDMARGIN_Pos; + ((Dsu *)hw)->MBCONFIG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg &= ~DSU_MBCONFIG_DEFRDMARGIN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg ^= DSU_MBCONFIG_DEFRDMARGIN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBCONFIG_DBG_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg |= DSU_MBCONFIG_DBG; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBCONFIG_DBG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp = (tmp & DSU_MBCONFIG_DBG) >> DSU_MBCONFIG_DBG_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBCONFIG_DBG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp &= ~DSU_MBCONFIG_DBG; + tmp |= value << DSU_MBCONFIG_DBG_Pos; + ((Dsu *)hw)->MBCONFIG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBCONFIG_DBG_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg &= ~DSU_MBCONFIG_DBG; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBCONFIG_DBG_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg ^= DSU_MBCONFIG_DBG; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg |= DSU_MBCONFIG_ALGO(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbconfig_reg_t hri_dsu_get_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp = (tmp & DSU_MBCONFIG_ALGO(mask)) >> DSU_MBCONFIG_ALGO_Pos; + return tmp; +} + +static inline void hri_dsu_write_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp &= ~DSU_MBCONFIG_ALGO_Msk; + tmp |= DSU_MBCONFIG_ALGO(data); + ((Dsu *)hw)->MBCONFIG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg &= ~DSU_MBCONFIG_ALGO(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg ^= DSU_MBCONFIG_ALGO(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbconfig_reg_t hri_dsu_read_MBCONFIG_ALGO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp = (tmp & DSU_MBCONFIG_ALGO_Msk) >> DSU_MBCONFIG_ALGO_Pos; + return tmp; +} + +static inline void hri_dsu_set_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbconfig_reg_t hri_dsu_get_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBCONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBCONFIG.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbconfig_reg_t hri_dsu_read_MBCONFIG_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBCONFIG.reg; +} + +static inline void hri_dsu_set_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBWORD.reg |= DSU_MBWORD_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbword_reg_t hri_dsu_get_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBWORD.reg; + tmp = (tmp & DSU_MBWORD_DATA(mask)) >> DSU_MBWORD_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBWORD.reg; + tmp &= ~DSU_MBWORD_DATA_Msk; + tmp |= DSU_MBWORD_DATA(data); + ((Dsu *)hw)->MBWORD.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBWORD.reg &= ~DSU_MBWORD_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBWORD.reg ^= DSU_MBWORD_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbword_reg_t hri_dsu_read_MBWORD_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBWORD.reg; + tmp = (tmp & DSU_MBWORD_DATA_Msk) >> DSU_MBWORD_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBWORD.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbword_reg_t hri_dsu_get_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBWORD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBWORD.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBWORD.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBWORD.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbword_reg_t hri_dsu_read_MBWORD_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBWORD.reg; +} + +static inline void hri_dsu_set_MBGSTAT_ALLDONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_ALLDONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBGSTAT_ALLDONE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp = (tmp & DSU_MBGSTAT_ALLDONE) >> DSU_MBGSTAT_ALLDONE_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBGSTAT_ALLDONE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp &= ~DSU_MBGSTAT_ALLDONE; + tmp |= value << DSU_MBGSTAT_ALLDONE_Pos; + ((Dsu *)hw)->MBGSTAT.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBGSTAT_ALLDONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_ALLDONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBGSTAT_ALLDONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_ALLDONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBGSTAT_FAILED_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_FAILED; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBGSTAT_FAILED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp = (tmp & DSU_MBGSTAT_FAILED) >> DSU_MBGSTAT_FAILED_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBGSTAT_FAILED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp &= ~DSU_MBGSTAT_FAILED; + tmp |= value << DSU_MBGSTAT_FAILED_Pos; + ((Dsu *)hw)->MBGSTAT.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBGSTAT_FAILED_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_FAILED; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBGSTAT_FAILED_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_FAILED; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBGSTAT_ERRINFO_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_ERRINFO; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBGSTAT_ERRINFO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp = (tmp & DSU_MBGSTAT_ERRINFO) >> DSU_MBGSTAT_ERRINFO_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBGSTAT_ERRINFO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp &= ~DSU_MBGSTAT_ERRINFO; + tmp |= value << DSU_MBGSTAT_ERRINFO_Pos; + ((Dsu *)hw)->MBGSTAT.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBGSTAT_ERRINFO_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_ERRINFO; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBGSTAT_ERRINFO_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_ERRINFO; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBGSTAT_CONFIGURED_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_CONFIGURED; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBGSTAT_CONFIGURED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp = (tmp & DSU_MBGSTAT_CONFIGURED) >> DSU_MBGSTAT_CONFIGURED_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBGSTAT_CONFIGURED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp &= ~DSU_MBGSTAT_CONFIGURED; + tmp |= value << DSU_MBGSTAT_CONFIGURED_Pos; + ((Dsu *)hw)->MBGSTAT.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBGSTAT_CONFIGURED_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_CONFIGURED; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBGSTAT_CONFIGURED_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_CONFIGURED; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbgstat_reg_t hri_dsu_get_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBGSTAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBGSTAT.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbgstat_reg_t hri_dsu_read_MBGSTAT_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBGSTAT.reg; +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE0_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE0; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE0) >> DSU_MBENABLE0_ENABLE0_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE0; + tmp |= value << DSU_MBENABLE0_ENABLE0_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE0_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE0; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE0_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE0; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE1_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE1; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE1) >> DSU_MBENABLE0_ENABLE1_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE1; + tmp |= value << DSU_MBENABLE0_ENABLE1_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE1_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE1; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE1_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE1; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE2_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE2; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE2) >> DSU_MBENABLE0_ENABLE2_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE2; + tmp |= value << DSU_MBENABLE0_ENABLE2_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE2_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE2; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE2_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE2; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE3_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE3; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE3) >> DSU_MBENABLE0_ENABLE3_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE3; + tmp |= value << DSU_MBENABLE0_ENABLE3_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE3_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE3; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE3_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE3; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE4_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE4; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE4) >> DSU_MBENABLE0_ENABLE4_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE4; + tmp |= value << DSU_MBENABLE0_ENABLE4_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE4_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE4; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE4_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE4; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE5_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE5; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE5) >> DSU_MBENABLE0_ENABLE5_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE5; + tmp |= value << DSU_MBENABLE0_ENABLE5_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE5_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE5; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE5_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE5; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE6_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE6; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE6) >> DSU_MBENABLE0_ENABLE6_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE6; + tmp |= value << DSU_MBENABLE0_ENABLE6_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE6_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE6; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE6_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE6; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE7_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE7; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE7) >> DSU_MBENABLE0_ENABLE7_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE7; + tmp |= value << DSU_MBENABLE0_ENABLE7_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE7_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE7; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE7_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE7; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE8_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE8; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE8) >> DSU_MBENABLE0_ENABLE8_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE8; + tmp |= value << DSU_MBENABLE0_ENABLE8_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE8_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE8; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE8_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE8; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE9_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE9; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE9) >> DSU_MBENABLE0_ENABLE9_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE9; + tmp |= value << DSU_MBENABLE0_ENABLE9_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE9_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE9; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE9_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE9; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE10_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE10; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE10) >> DSU_MBENABLE0_ENABLE10_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE10; + tmp |= value << DSU_MBENABLE0_ENABLE10_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE10_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE10; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE10_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE10; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE11_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE11; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE11) >> DSU_MBENABLE0_ENABLE11_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE11; + tmp |= value << DSU_MBENABLE0_ENABLE11_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE11_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE11; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE11_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE11; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE12_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE12; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE12) >> DSU_MBENABLE0_ENABLE12_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE12; + tmp |= value << DSU_MBENABLE0_ENABLE12_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE12_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE12; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE12_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE12; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE13_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE13; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE13) >> DSU_MBENABLE0_ENABLE13_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE13; + tmp |= value << DSU_MBENABLE0_ENABLE13_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE13_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE13; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE13_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE13; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE14_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE14; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE14) >> DSU_MBENABLE0_ENABLE14_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE14; + tmp |= value << DSU_MBENABLE0_ENABLE14_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE14_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE14; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE14_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE14; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE15_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE15; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE15) >> DSU_MBENABLE0_ENABLE15_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE15; + tmp |= value << DSU_MBENABLE0_ENABLE15_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE15_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE15; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE15_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE15; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE16_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE16; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE16) >> DSU_MBENABLE0_ENABLE16_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE16; + tmp |= value << DSU_MBENABLE0_ENABLE16_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE16_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE16; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE16_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE16; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE17_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE17; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE17) >> DSU_MBENABLE0_ENABLE17_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE17; + tmp |= value << DSU_MBENABLE0_ENABLE17_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE17_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE17; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE17_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE17; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE18_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE18; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE18) >> DSU_MBENABLE0_ENABLE18_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE18; + tmp |= value << DSU_MBENABLE0_ENABLE18_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE18_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE18; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE18_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE18; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE19_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE19; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE19) >> DSU_MBENABLE0_ENABLE19_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE19; + tmp |= value << DSU_MBENABLE0_ENABLE19_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE19_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE19; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE19_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE19; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE20_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE20; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE20) >> DSU_MBENABLE0_ENABLE20_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE20; + tmp |= value << DSU_MBENABLE0_ENABLE20_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE20_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE20; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE20_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE20; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE21_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE21; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE21) >> DSU_MBENABLE0_ENABLE21_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE21; + tmp |= value << DSU_MBENABLE0_ENABLE21_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE21_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE21; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE21_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE21; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE22_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE22; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE22) >> DSU_MBENABLE0_ENABLE22_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE22; + tmp |= value << DSU_MBENABLE0_ENABLE22_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE22_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE22; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE22_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE22; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE23_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE23; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE23) >> DSU_MBENABLE0_ENABLE23_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE23; + tmp |= value << DSU_MBENABLE0_ENABLE23_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE23_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE23; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE23_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE23; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE24_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE24; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE24) >> DSU_MBENABLE0_ENABLE24_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE24; + tmp |= value << DSU_MBENABLE0_ENABLE24_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE24_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE24; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE24_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE24; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE25_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE25; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE25) >> DSU_MBENABLE0_ENABLE25_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE25; + tmp |= value << DSU_MBENABLE0_ENABLE25_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE25_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE25; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE25_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE25; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE26_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE26; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE26) >> DSU_MBENABLE0_ENABLE26_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE26; + tmp |= value << DSU_MBENABLE0_ENABLE26_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE26_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE26; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE26_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE26; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE27_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE27; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE27) >> DSU_MBENABLE0_ENABLE27_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE27; + tmp |= value << DSU_MBENABLE0_ENABLE27_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE27_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE27; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE27_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE27; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_ENABLE28_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE28; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBENABLE0_ENABLE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp = (tmp & DSU_MBENABLE0_ENABLE28) >> DSU_MBENABLE0_ENABLE28_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_MBENABLE0_ENABLE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= ~DSU_MBENABLE0_ENABLE28; + tmp |= value << DSU_MBENABLE0_ENABLE28_Pos; + ((Dsu *)hw)->MBENABLE0.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_ENABLE28_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE28; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_ENABLE28_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE28; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbenable0_reg_t hri_dsu_get_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBENABLE0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBENABLE0.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbenable0_reg_t hri_dsu_read_MBENABLE0_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBENABLE0.reg; +} + +static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= ~DSU_DCFG_DCFG_Msk; + tmp |= DSU_DCFG_DCFG(data); + ((Dsu *)hw)->DCFG[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCFG[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCFG[index].reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS0_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS0) >> DSU_MBSTATUS0_STATUS0_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS0_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS0; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS1_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS1) >> DSU_MBSTATUS0_STATUS1_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS1_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS1; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS2_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS2) >> DSU_MBSTATUS0_STATUS2_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS2_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS2; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS3_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS3) >> DSU_MBSTATUS0_STATUS3_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS3_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS3; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS4_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS4) >> DSU_MBSTATUS0_STATUS4_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS4_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS4; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS5_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS5) >> DSU_MBSTATUS0_STATUS5_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS5_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS5; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS6_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS6) >> DSU_MBSTATUS0_STATUS6_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS6_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS6; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS7_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS7) >> DSU_MBSTATUS0_STATUS7_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS7_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS7; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS8_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS8) >> DSU_MBSTATUS0_STATUS8_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS8_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS8; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS9_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS9) >> DSU_MBSTATUS0_STATUS9_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS9_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS9; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS10_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS10) >> DSU_MBSTATUS0_STATUS10_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS10_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS10; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS11_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS11) >> DSU_MBSTATUS0_STATUS11_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS11_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS11; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS12_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS12) >> DSU_MBSTATUS0_STATUS12_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS12_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS12; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS13_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS13) >> DSU_MBSTATUS0_STATUS13_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS13_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS13; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS14_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS14) >> DSU_MBSTATUS0_STATUS14_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS14_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS14; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS15_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS15) >> DSU_MBSTATUS0_STATUS15_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS15_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS15; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS16_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS16) >> DSU_MBSTATUS0_STATUS16_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS16_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS16; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS17_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS17) >> DSU_MBSTATUS0_STATUS17_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS17_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS17; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS18_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS18) >> DSU_MBSTATUS0_STATUS18_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS18_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS18; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS19_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS19) >> DSU_MBSTATUS0_STATUS19_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS19_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS19; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS20_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS20) >> DSU_MBSTATUS0_STATUS20_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS20_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS20; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS21_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS21) >> DSU_MBSTATUS0_STATUS21_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS21_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS21; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS22_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS22) >> DSU_MBSTATUS0_STATUS22_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS22_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS22; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS23_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS23) >> DSU_MBSTATUS0_STATUS23_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS23_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS23; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS24_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS24) >> DSU_MBSTATUS0_STATUS24_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS24_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS24; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS25_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS25) >> DSU_MBSTATUS0_STATUS25_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS25_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS25; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS26_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS26) >> DSU_MBSTATUS0_STATUS26_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS26_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS26; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS27_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS27) >> DSU_MBSTATUS0_STATUS27_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS27_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS27; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_MBSTATUS0_STATUS28_bit(const void *const hw) +{ + return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS28) >> DSU_MBSTATUS0_STATUS28_Pos; +} + +static inline void hri_dsu_clear_MBSTATUS0_STATUS28_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS28; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbstatus0_reg_t hri_dsu_get_MBSTATUS0_reg(const void *const hw, hri_dsu_mbstatus0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MBSTATUS0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_MBSTATUS0_reg(const void *const hw, hri_dsu_mbstatus0_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->MBSTATUS0.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_mbstatus0_reg_t hri_dsu_read_MBSTATUS0_reg(const void *const hw) +{ + return ((Dsu *)hw)->MBSTATUS0.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_D51_H_INCLUDED */ +#endif /* _SAMD51_DSU_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_eic_d51.h b/atmel-samd/asf4/samd51/hri/hri_eic_d51.h new file mode 100644 index 0000000000000..267a0a0ce0c40 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_eic_d51.h @@ -0,0 +1,1841 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_EIC_COMPONENT_ +#ifndef _HRI_EIC_D51_H_INCLUDED_ +#define _HRI_EIC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_debouncen_reg_t; +typedef uint32_t hri_eic_dprescaler_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_pinstate_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, + hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; + tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); + ((Eic *)hw)->DEBOUNCEN.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) +{ + return ((Eic *)hw)->DEBOUNCEN.reg; +} + +static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES0; + tmp |= value << EIC_DPRESCALER_STATES0_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES1; + tmp |= value << EIC_DPRESCALER_STATES1_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_TICKON; + tmp |= value << EIC_DPRESCALER_TICKON_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; + tmp |= EIC_DPRESCALER_PRESCALER0(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; + tmp |= EIC_DPRESCALER_PRESCALER1(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) +{ + return ((Eic *)hw)->DPRESCALER.reg; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->PINSTATE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) +{ + return ((Eic *)hw)->PINSTATE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_D51_H_INCLUDED */ +#endif /* _SAMD51_EIC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_evsys_d51.h b/atmel-samd/asf4/samd51/hri/hri_evsys_d51.h new file mode 100644 index 0000000000000..0663068faa135 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_evsys_d51.h @@ -0,0 +1,1716 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_D51_H_INCLUDED_ +#define _HRI_EVSYS_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_evsys_intpend_reg_t; +typedef uint32_t hri_evsys_busych_reg_t; +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_intstatus_reg_t; +typedef uint32_t hri_evsys_readyusr_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint32_t hri_evsyschannel_channel_reg_t; +typedef uint8_t hri_evsys_chintenset_reg_t; +typedef uint8_t hri_evsys_chintflag_reg_t; +typedef uint8_t hri_evsys_chstatus_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; +typedef uint8_t hri_evsys_prictrl_reg_t; +typedef uint8_t hri_evsyschannel_chintenset_reg_t; +typedef uint8_t hri_evsyschannel_chintflag_reg_t; +typedef uint8_t hri_evsyschannel_chstatus_reg_t; + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_RREN; + tmp |= value << EVSYS_PRICTRL_RREN_Pos; + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_PRI_Msk; + tmp |= EVSYS_PRICTRL_PRI(data); + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) +{ + return ((Evsys *)hw)->PRICTRL.reg; +} + +static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_OVR; + tmp |= value << EVSYS_INTPEND_OVR_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_EVD; + tmp |= value << EVSYS_INTPEND_EVD_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_READY; + tmp |= value << EVSYS_INTPEND_READY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_BUSY; + tmp |= value << EVSYS_INTPEND_BUSY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_ID_Msk; + tmp |= EVSYS_INTPEND_ID(data); + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTPEND.reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, + hri_evsys_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTSTATUS.reg; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) +{ + return ((Evsys *)hw)->BUSYCH.reg; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->READYUSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) +{ + return ((Evsys *)hw)->READYUSR.reg; +} + +static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = data; + ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHANNEL.reg; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t data) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; +} + +static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_D51_H_INCLUDED */ +#endif /* _SAMD51_EVSYS_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_freqm_d51.h b/atmel-samd/asf4/samd51/hri/hri_freqm_d51.h new file mode 100644 index 0000000000000..17f510ef4b72a --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_freqm_d51.h @@ -0,0 +1,467 @@ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_D51_H_INCLUDED_ +#define _HRI_FREQM_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_D51_H_INCLUDED */ +#endif /* _SAMD51_FREQM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_gclk_d51.h b/atmel-samd/asf4/samd51/hri/hri_gclk_d51.h new file mode 100644 index 0000000000000..17d82e20db27a --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_gclk_d51.h @@ -0,0 +1,770 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_D51_H_INCLUDED_ +#define _HRI_GCLK_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_D51_H_INCLUDED */ +#endif /* _SAMD51_GCLK_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_hmatrixb_d51.h b/atmel-samd/asf4/samd51/hri/hri_hmatrixb_d51.h new file mode 100644 index 0000000000000..0d00c8782fdc9 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_hmatrixb_d51.h @@ -0,0 +1,246 @@ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_D51_H_INCLUDED_ +#define _HRI_HMATRIXB_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_D51_H_INCLUDED */ +#endif /* _SAMD51_HMATRIXB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_i2s_d51.h b/atmel-samd/asf4/samd51/hri/hri_i2s_d51.h new file mode 100644 index 0000000000000..e03430339c118 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_i2s_d51.h @@ -0,0 +1,3107 @@ +/** + * \file + * + * \brief SAM I2S + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_I2S_COMPONENT_ +#ifndef _HRI_I2S_D51_H_INCLUDED_ +#define _HRI_I2S_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_I2S_CRITICAL_SECTIONS) +#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define I2S_CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_i2s_intenset_reg_t; +typedef uint16_t hri_i2s_intflag_reg_t; +typedef uint16_t hri_i2s_syncbusy_reg_t; +typedef uint32_t hri_i2s_clkctrl_reg_t; +typedef uint32_t hri_i2s_rxctrl_reg_t; +typedef uint32_t hri_i2s_rxdata_reg_t; +typedef uint32_t hri_i2s_txctrl_reg_t; +typedef uint32_t hri_i2s_txdata_reg_t; +typedef uint8_t hri_i2s_ctrla_reg_t; + +static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + while (((I2s *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + return ((I2s *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; +} + +static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; +} + +static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; +} + +static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; +} + +static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; +} + +static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; +} + +static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; +} + +static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; +} + +static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; +} + +static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; +} + +static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; +} + +static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; +} + +static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; +} + +static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; +} + +static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; +} + +static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; +} + +static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENSET.reg = mask; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) +{ + return ((I2s *)hw)->INTENSET.reg; +} + +static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) +{ + ((I2s *)hw)->INTENSET.reg = data; + ((I2s *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) +{ + return ((I2s *)hw)->INTFLAG.reg; +} + +static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + ((I2s *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXDATA.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_ENABLE; + tmp |= value << I2S_CTRLA_ENABLE_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN0; + tmp |= value << I2S_CTRLA_CKEN0_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN1; + tmp |= value << I2S_CTRLA_CKEN1_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_TXEN; + tmp |= value << I2S_CTRLA_TXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_RXEN; + tmp |= value << I2S_CTRLA_RXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + hri_i2s_wait_for_sync(hw, + I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 + | I2S_SYNCBUSY_TXEN + | I2S_SYNCBUSY_RXEN); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) +{ + return ((I2s *)hw)->CTRLA.reg; +} + +static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_BITDELAY; + tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSSEL; + tmp |= value << I2S_CLKCTRL_FSSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSINV; + tmp |= value << I2S_CLKCTRL_FSINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSOUTINV; + tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKSEL; + tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKOUTINV; + tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKSEL; + tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKEN; + tmp |= value << I2S_CLKCTRL_MCKEN_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTINV; + tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; + tmp |= I2S_CLKCTRL_SLOTSIZE(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; + tmp |= I2S_CLKCTRL_NBSLOTS(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; + tmp |= I2S_CLKCTRL_FSWIDTH(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; + tmp |= I2S_CLKCTRL_MCKDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; + tmp |= I2S_CLKCTRL_MCKOUTDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->CLKCTRL[index].reg; +} + +static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXSAME; + tmp |= value << I2S_TXCTRL_TXSAME_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTADJ; + tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_WORDADJ; + tmp |= value << I2S_TXCTRL_WORDADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_BITREV; + tmp |= value << I2S_TXCTRL_BITREV_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS0; + tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS1; + tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS2; + tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS3; + tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS4; + tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS5; + tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS6; + tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS7; + tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_MONO; + tmp |= value << I2S_TXCTRL_MONO_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DMA; + tmp |= value << I2S_TXCTRL_DMA_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; + tmp |= I2S_TXCTRL_TXDEFAULT(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DATASIZE_Msk; + tmp |= I2S_TXCTRL_DATASIZE(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_EXTEND_Msk; + tmp |= I2S_TXCTRL_EXTEND(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->TXCTRL.reg; +} + +static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_CLKSEL; + tmp |= value << I2S_RXCTRL_CLKSEL_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTADJ; + tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_WORDADJ; + tmp |= value << I2S_RXCTRL_WORDADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_BITREV; + tmp |= value << I2S_RXCTRL_BITREV_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS0; + tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS1; + tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS2; + tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS3; + tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS4; + tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS5; + tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS6; + tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS7; + tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_MONO; + tmp |= value << I2S_RXCTRL_MONO_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DMA; + tmp |= value << I2S_RXCTRL_DMA_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_RXLOOP; + tmp |= value << I2S_RXCTRL_RXLOOP_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SERMODE_Msk; + tmp |= I2S_RXCTRL_SERMODE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DATASIZE_Msk; + tmp |= I2S_RXCTRL_DATASIZE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_EXTEND_Msk; + tmp |= I2S_RXCTRL_EXTEND(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->RXCTRL.reg; +} + +static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) +{ + return ((I2s *)hw)->SYNCBUSY.reg; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) +{ + return ((I2s *)hw)->RXDATA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_I2S_D51_H_INCLUDED */ +#endif /* _SAMD51_I2S_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_icm_d51.h b/atmel-samd/asf4/samd51/hri/hri_icm_d51.h new file mode 100644 index 0000000000000..ce434a275715c --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_icm_d51.h @@ -0,0 +1,770 @@ +/** + * \file + * + * \brief SAM ICM + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_ICM_COMPONENT_ +#ifndef _HRI_ICM_D51_H_INCLUDED_ +#define _HRI_ICM_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ICM_CRITICAL_SECTIONS) +#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ICM_CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_icm_cfg_reg_t; +typedef uint32_t hri_icm_ctrl_reg_t; +typedef uint32_t hri_icm_dscr_reg_t; +typedef uint32_t hri_icm_hash_reg_t; +typedef uint32_t hri_icm_imr_reg_t; +typedef uint32_t hri_icm_isr_reg_t; +typedef uint32_t hri_icm_sr_reg_t; +typedef uint32_t hri_icm_uasr_reg_t; +typedef uint32_t hri_icm_uihval_reg_t; +typedef uint32_t hri_icmdescriptor_raddr_reg_t; +typedef uint32_t hri_icmdescriptor_rcfg_reg_t; +typedef uint32_t hri_icmdescriptor_rctrl_reg_t; +typedef uint32_t hri_icmdescriptor_rnext_reg_t; + +static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, + hri_icmdescriptor_raddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RADDR.reg; +} + +static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, + hri_icmdescriptor_rcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCFG.reg; +} + +static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, + hri_icmdescriptor_rctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCTRL.reg; +} + +static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, + hri_icmdescriptor_rnext_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RNEXT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RNEXT.reg; +} + +static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; +} + +static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; +} + +static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; + } else { + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; + } +} + +static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; +} + +static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); +} + +static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); +} + +static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); +} + +static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); +} + +static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); +} + +static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); +} + +static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); +} + +static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); +} + +static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); +} + +static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); +} + +static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); +} + +static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); +} + +static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = mask; +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) +{ + return ((Icm *)hw)->IMR.reg; +} + +static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = data; + ((Icm *)hw)->IDR.reg = ~data; +} + +static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = mask; +} + +static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->UIHVAL[index].reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) +{ + return ((Icm *)hw)->CFG.reg; +} + +static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->DSCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) +{ + return ((Icm *)hw)->DSCR.reg; +} + +static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->HASH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) +{ + return ((Icm *)hw)->HASH.reg; +} + +static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) +{ + return ((Icm *)hw)->SR.reg; +} + +static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) +{ + return ((Icm *)hw)->ISR.reg; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->UASR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) +{ + return ((Icm *)hw)->UASR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ICM_D51_H_INCLUDED */ +#endif /* _SAMD51_ICM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_mclk_d51.h b/atmel-samd/asf4/samd51/hri/hri_mclk_d51.h new file mode 100644 index 0000000000000..59e7698825ad9 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_mclk_d51.h @@ -0,0 +1,3445 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_D51_H_INCLUDED_ +#define _HRI_MCLK_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint32_t hri_mclk_apbdmask_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_hsdiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_DIV_Msk; + tmp |= MCLK_CPUDIV_DIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB3; + tmp |= value << MCLK_AHBMASK_HPB3_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HMATRIX; + tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CMCC; + tmp |= value << MCLK_AHBMASK_CMCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_BKUPRAM; + tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI; + tmp |= value << MCLK_AHBMASK_QSPI_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC0; + tmp |= value << MCLK_AHBMASK_SDHC0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC1; + tmp |= value << MCLK_AHBMASK_SDHC1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_ICM; + tmp |= value << MCLK_AHBMASK_ICM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PUKCC; + tmp |= value << MCLK_AHBMASK_PUKCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI_2X; + tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM0; + tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM1; + tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC0; + tmp |= value << MCLK_APBAMASK_TC0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC1; + tmp |= value << MCLK_APBAMASK_TC1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_HMATRIX; + tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_EVSYS; + tmp |= value << MCLK_APBBMASK_EVSYS_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM2; + tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM3; + tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC0; + tmp |= value << MCLK_APBBMASK_TCC0_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC1; + tmp |= value << MCLK_APBBMASK_TCC1_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC2; + tmp |= value << MCLK_APBBMASK_TC2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC3; + tmp |= value << MCLK_APBBMASK_TC3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TAL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TAL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TAL) >> MCLK_APBBMASK_TAL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TAL; + tmp |= value << MCLK_APBBMASK_TAL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TAL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TAL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TAL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TAL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_RAMECC; + tmp |= value << MCLK_APBBMASK_RAMECC_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC3; + tmp |= value << MCLK_APBCMASK_TCC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC4; + tmp |= value << MCLK_APBCMASK_TC4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC5; + tmp |= value << MCLK_APBCMASK_TC5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PDEC; + tmp |= value << MCLK_APBCMASK_PDEC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ICM; + tmp |= value << MCLK_APBCMASK_ICM_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_QSPI; + tmp |= value << MCLK_APBCMASK_QSPI_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM4; + tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM5; + tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM6; + tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM7; + tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TCC4; + tmp |= value << MCLK_APBDMASK_TCC4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC6; + tmp |= value << MCLK_APBDMASK_TC6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC7; + tmp |= value << MCLK_APBDMASK_TC7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC0; + tmp |= value << MCLK_APBDMASK_ADC0_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC1; + tmp |= value << MCLK_APBDMASK_ADC1_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_DAC; + tmp |= value << MCLK_APBDMASK_DAC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_I2S; + tmp |= value << MCLK_APBDMASK_I2S_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_PCC; + tmp |= value << MCLK_APBDMASK_PCC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBDMASK.reg; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->HSDIV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->HSDIV.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_D51_H_INCLUDED */ +#endif /* _SAMD51_MCLK_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_nvmctrl_d51.h b/atmel-samd/asf4/samd51/hri/hri_nvmctrl_d51.h new file mode 100644 index 0000000000000..94f2e9b7e0443 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_nvmctrl_d51.h @@ -0,0 +1,1627 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_D51_H_INCLUDED_ +#define _HRI_NVMCTRL_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_ctrlb_reg_t; +typedef uint16_t hri_nvmctrl_intenset_reg_t; +typedef uint16_t hri_nvmctrl_intflag_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_eccerr_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint32_t hri_nvmctrl_pbldata_reg_t; +typedef uint32_t hri_nvmctrl_runlock_reg_t; +typedef uint32_t hri_nvmctrl_seestat_reg_t; +typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; +typedef uint8_t hri_nvmctrl_seecfg_reg_t; + +static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; +} + +static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; +} + +static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; +} + +static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; + } +} + +static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; +} + +static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AUTOWS; + tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_SUSPEN; + tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS0; + tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS1; + tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; + tmp |= NVMCTRL_CTRLA_WMODE(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_PRM_Msk; + tmp |= NVMCTRL_CTRLA_PRM(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_RWS_Msk; + tmp |= NVMCTRL_CTRLA_RWS(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; + tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; + tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, + hri_nvmctrl_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->DBGCTRL.reg; +} + +static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_WMODE; + tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_APRDIS; + tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEECFG.reg; +} + +static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, + hri_nvmctrl_status_reg_t mask) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->RUNLOCK.reg; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) +{ + return ((Nvmctrl *)hw)->PBLDATA[index].reg; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ECCERR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ECCERR.reg; +} + +static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->SEESTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEESTAT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_D51_H_INCLUDED */ +#endif /* _SAMD51_NVMCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_osc32kctrl_d51.h b/atmel-samd/asf4/samd51/hri/hri_osc32kctrl_d51.h new file mode 100644 index 0000000000000..3d5b853ff7de3 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_osc32kctrl_d51.h @@ -0,0 +1,1208 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_D51_H_INCLUDED_ +#define _HRI_OSC32KCTRL_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; +typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; + tmp |= OSC32KCTRL_XOSC32K_CGM(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_D51_H_INCLUDED */ +#endif /* _SAMD51_OSC32KCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_oscctrl_d51.h b/atmel-samd/asf4/samd51/hri/hri_oscctrl_d51.h new file mode 100644 index 0000000000000..abb2b47f74e0a --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_oscctrl_d51.h @@ -0,0 +1,4360 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_D51_H_INCLUDED_ +#define _HRI_OSCCTRL_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_dpllstatus_reg_t; +typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint32_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; +typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; +typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_dfllctrla_reg_t; +typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) + >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t +hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) + >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) + >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO0; + tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO1; + tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENALC; + tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IMULT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; + tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Oscctrl *)hw)->XOSCCTRL[index].reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, + hri_oscctrl_dfllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_MODE; + tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; + tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; + tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, + hri_oscctrl_dfllctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; + tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_D51_H_INCLUDED */ +#endif /* _SAMD51_OSCCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pac_d51.h b/atmel-samd/asf4/samd51/hri/hri_pac_d51.h new file mode 100644 index 0000000000000..6830c5d841fbe --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_pac_d51.h @@ -0,0 +1,1493 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_PAC_COMPONENT_ +#ifndef _HRI_PAC_D51_H_INCLUDED_ +#define _HRI_PAC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_intflagd_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_statusd_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; +} + +static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; +} + +static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; +} + +static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; +} + +static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; +} + +static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; +} + +static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; +} + +static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; +} + +static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; +} + +static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; +} + +static inline bool hri_pac_get_INTFLAGB_TAL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TAL) >> PAC_INTFLAGB_TAL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TAL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TAL; +} + +static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; +} + +static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; +} + +static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; +} + +static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; +} + +static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; +} + +static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; +} + +static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; +} + +static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; +} + +static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; +} + +static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; +} + +static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; +} + +static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; +} + +static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; +} + +static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGD.reg; +} + +static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + ((Pac *)hw)->INTFLAGD.reg = mask; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; +} + +static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSB_TAL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TAL) >> PAC_STATUSB_TAL_Pos; +} + +static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; +} + +static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; +} + +static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; +} + +static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; +} + +static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; +} + +static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; +} + +static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; +} + +static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSD.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_D51_H_INCLUDED */ +#endif /* _SAMD51_PAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pcc_d51.h b/atmel-samd/asf4/samd51/hri/hri_pcc_d51.h new file mode 100644 index 0000000000000..334e116d43ea3 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_pcc_d51.h @@ -0,0 +1,307 @@ +/** + * \file + * + * \brief SAM PCC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_PCC_COMPONENT_ +#ifndef _HRI_PCC_D51_H_INCLUDED_ +#define _HRI_PCC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PCC_CRITICAL_SECTIONS) +#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PCC_CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pcc_imr_reg_t; +typedef uint32_t hri_pcc_isr_reg_t; +typedef uint32_t hri_pcc_mr_reg_t; +typedef uint32_t hri_pcc_rhr_reg_t; +typedef uint32_t hri_pcc_wpmr_reg_t; +typedef uint32_t hri_pcc_wpsr_reg_t; + +static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; +} + +static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; +} + +static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; + } +} + +static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; +} + +static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; +} + +static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; +} + +static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; + } +} + +static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; +} + +static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IER.reg = mask; +} + +static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->IMR.reg; +} + +static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) +{ + ((Pcc *)hw)->IER.reg = data; + ((Pcc *)hw)->IDR.reg = ~data; +} + +static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IDR.reg = mask; +} + +static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->MR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) +{ + return ((Pcc *)hw)->MR.reg; +} + +static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPMR.reg; +} + +static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; +} + +static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; +} + +static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) +{ + return ((Pcc *)hw)->ISR.reg; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->RHR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) +{ + return ((Pcc *)hw)->RHR.reg; +} + +static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPSR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PCC_D51_H_INCLUDED */ +#endif /* _SAMD51_PCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pdec_d51.h b/atmel-samd/asf4/samd51/hri/hri_pdec_d51.h new file mode 100644 index 0000000000000..afaa30f202210 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_pdec_d51.h @@ -0,0 +1,2642 @@ +/** + * \file + * + * \brief SAM PDEC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_PDEC_COMPONENT_ +#ifndef _HRI_PDEC_D51_H_INCLUDED_ +#define _HRI_PDEC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) +#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PDEC_CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pdec_evctrl_reg_t; +typedef uint16_t hri_pdec_status_reg_t; +typedef uint32_t hri_pdec_cc_reg_t; +typedef uint32_t hri_pdec_ccbuf_reg_t; +typedef uint32_t hri_pdec_count_reg_t; +typedef uint32_t hri_pdec_ctrla_reg_t; +typedef uint32_t hri_pdec_syncbusy_reg_t; +typedef uint8_t hri_pdec_ctrlbset_reg_t; +typedef uint8_t hri_pdec_dbgctrl_reg_t; +typedef uint8_t hri_pdec_filter_reg_t; +typedef uint8_t hri_pdec_filterbuf_reg_t; +typedef uint8_t hri_pdec_intenset_reg_t; +typedef uint8_t hri_pdec_intflag_reg_t; +typedef uint8_t hri_pdec_presc_reg_t; +typedef uint8_t hri_pdec_prescbuf_reg_t; + +static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + while (((Pdec *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + return ((Pdec *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; +} + +static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; + } else { + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; + } +} + +static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; +} + +static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); + ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); +} + +static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) +{ + return ((Pdec *)hw)->CTRLBSET.reg; +} + +static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = data; + ((Pdec *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; +} + +static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; +} + +static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; + } +} + +static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; +} + +static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; +} + +static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; +} + +static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; + } +} + +static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; +} + +static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; +} + +static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; +} + +static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; + } +} + +static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; +} + +static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; +} + +static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; +} + +static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; + } +} + +static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; +} + +static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; +} + +static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; +} + +static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; + } +} + +static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; +} + +static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; +} + +static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; +} + +static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; + } +} + +static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; +} + +static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENSET.reg = mask; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTENSET.reg; +} + +static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) +{ + ((Pdec *)hw)->INTENSET.reg = data; + ((Pdec *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTFLAG.reg; +} + +static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + ((Pdec *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ENABLE; + tmp |= value << PDEC_CTRLA_ENABLE_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_RUNSTDBY; + tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ALOCK; + tmp |= value << PDEC_CTRLA_ALOCK_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_SWAP; + tmp |= value << PDEC_CTRLA_SWAP_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PEREN; + tmp |= value << PDEC_CTRLA_PEREN_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN0; + tmp |= value << PDEC_CTRLA_PINEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN1; + tmp |= value << PDEC_CTRLA_PINEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN2; + tmp |= value << PDEC_CTRLA_PINEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN0; + tmp |= value << PDEC_CTRLA_PINVEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN1; + tmp |= value << PDEC_CTRLA_PINVEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN2; + tmp |= value << PDEC_CTRLA_PINVEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MODE_Msk; + tmp |= PDEC_CTRLA_MODE(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_CONF_Msk; + tmp |= PDEC_CTRLA_CONF(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ANGULAR_Msk; + tmp |= PDEC_CTRLA_ANGULAR(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MAXCMP_Msk; + tmp |= PDEC_CTRLA_MAXCMP(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) +{ + return ((Pdec *)hw)->CTRLA.reg; +} + +static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_OVFEO; + tmp |= value << PDEC_EVCTRL_OVFEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_ERREO; + tmp |= value << PDEC_EVCTRL_ERREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_DIREO; + tmp |= value << PDEC_EVCTRL_DIREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_VLCEO; + tmp |= value << PDEC_EVCTRL_VLCEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO0; + tmp |= value << PDEC_EVCTRL_MCEO0_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO1; + tmp |= value << PDEC_EVCTRL_MCEO1_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVACT_Msk; + tmp |= PDEC_EVCTRL_EVACT(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVINV_Msk; + tmp |= PDEC_EVCTRL_EVINV(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVEI_Msk; + tmp |= PDEC_EVCTRL_EVEI(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->EVCTRL.reg; +} + +static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= ~PDEC_DBGCTRL_DBGRUN; + tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; + ((Pdec *)hw)->DBGCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->DBGCTRL.reg; +} + +static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= ~PDEC_PRESC_PRESC_Msk; + tmp |= PDEC_PRESC_PRESC(data); + ((Pdec *)hw)->PRESC.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) +{ + return ((Pdec *)hw)->PRESC.reg; +} + +static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= ~PDEC_FILTER_FILTER_Msk; + tmp |= PDEC_FILTER_FILTER(data); + ((Pdec *)hw)->FILTER.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) +{ + return ((Pdec *)hw)->FILTER.reg; +} + +static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, + hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; + tmp |= PDEC_PRESCBUF_PRESCBUF(data); + ((Pdec *)hw)->PRESCBUF.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) +{ + return ((Pdec *)hw)->PRESCBUF.reg; +} + +static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, + hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; + tmp |= PDEC_FILTERBUF_FILTERBUF(data); + ((Pdec *)hw)->FILTERBUF.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) +{ + return ((Pdec *)hw)->FILTERBUF.reg; +} + +static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= ~PDEC_COUNT_COUNT_Msk; + tmp |= PDEC_COUNT_COUNT(data); + ((Pdec *)hw)->COUNT.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) +{ + return ((Pdec *)hw)->COUNT.reg; +} + +static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= ~PDEC_CC_CC_Msk; + tmp |= PDEC_CC_CC(data); + ((Pdec *)hw)->CC[index].reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Pdec *)hw)->CC[index].reg; +} + +static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= ~PDEC_CCBUF_CCBUF_Msk; + tmp |= PDEC_CCBUF_CCBUF(data); + ((Pdec *)hw)->CCBUF[index].reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Pdec *)hw)->CCBUF[index].reg; +} + +static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Pdec *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; +} + +static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; +} + +static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) +{ + return ((Pdec *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PDEC_D51_H_INCLUDED */ +#endif /* _SAMD51_PDEC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pm_d51.h b/atmel-samd/asf4/samd51/hri/hri_pm_d51.h new file mode 100644 index 0000000000000..3dde1282f96d6 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_pm_d51.h @@ -0,0 +1,829 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_PM_COMPONENT_ +#ifndef _HRI_PM_D51_H_INCLUDED_ +#define _HRI_PM_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_pm_bkupcfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_hibcfg_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_pwsakdly_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; +typedef uint8_t hri_pm_stdbycfg_reg_t; + +static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; +} + +static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; +} + +static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; + } +} + +static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_RAMCFG_Msk; + tmp |= PM_STDBYCFG_RAMCFG(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; + tmp |= PM_STDBYCFG_FASTWKUP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_RAMCFG_Msk; + tmp |= PM_HIBCFG_RAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_BRAMCFG_Msk; + tmp |= PM_HIBCFG_BRAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->HIBCFG.reg; +} + +static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; + tmp |= PM_BKUPCFG_BRAMCFG(data); + ((Pm *)hw)->BKUPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->BKUPCFG.reg; +} + +static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_IGNACK; + tmp |= value << PM_PWSAKDLY_IGNACK_Pos; + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; + tmp |= PM_PWSAKDLY_DLYVAL(data); + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) +{ + return ((Pm *)hw)->PWSAKDLY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_D51_H_INCLUDED */ +#endif /* _SAMD51_PM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_port_d51.h b/atmel-samd/asf4/samd51/hri/hri_port_d51.h new file mode 100644 index 0000000000000..cc2decac80a93 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_port_d51.h @@ -0,0 +1,2537 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_PORT_COMPONENT_ +#ifndef _HRI_PORT_D51_H_INCLUDED_ +#define _HRI_PORT_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_D51_H_INCLUDED */ +#endif /* _SAMD51_PORT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_qspi_d51.h b/atmel-samd/asf4/samd51/hri/hri_qspi_d51.h new file mode 100644 index 0000000000000..9474a03a70d3e --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_qspi_d51.h @@ -0,0 +1,2067 @@ +/** + * \file + * + * \brief SAM QSPI + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_QSPI_COMPONENT_ +#ifndef _HRI_QSPI_D51_H_INCLUDED_ +#define _HRI_QSPI_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) +#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define QSPI_CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_qspi_baud_reg_t; +typedef uint32_t hri_qspi_ctrla_reg_t; +typedef uint32_t hri_qspi_ctrlb_reg_t; +typedef uint32_t hri_qspi_instraddr_reg_t; +typedef uint32_t hri_qspi_instrctrl_reg_t; +typedef uint32_t hri_qspi_instrframe_reg_t; +typedef uint32_t hri_qspi_intenset_reg_t; +typedef uint32_t hri_qspi_intflag_reg_t; +typedef uint32_t hri_qspi_rxdata_reg_t; +typedef uint32_t hri_qspi_scrambctrl_reg_t; +typedef uint32_t hri_qspi_scrambkey_reg_t; +typedef uint32_t hri_qspi_status_reg_t; +typedef uint32_t hri_qspi_txdata_reg_t; + +static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; +} + +static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; +} + +static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; + } +} + +static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; +} + +static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; +} + +static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; +} + +static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; + } +} + +static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; +} + +static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; +} + +static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; +} + +static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; + } +} + +static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; +} + +static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; +} + +static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; +} + +static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; + } +} + +static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; +} + +static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; +} + +static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; +} + +static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; + } +} + +static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; +} + +static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; +} + +static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; +} + +static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; + } +} + +static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; +} + +static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENSET.reg = mask; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTENSET.reg; +} + +static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) +{ + ((Qspi *)hw)->INTENSET.reg = data; + ((Qspi *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTFLAG.reg; +} + +static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + ((Qspi *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->TXDATA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBKEY.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_ENABLE; + tmp |= value << QSPI_CTRLA_ENABLE_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_LASTXFER; + tmp |= value << QSPI_CTRLA_LASTXFER_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLA.reg; +} + +static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_MODE; + tmp |= value << QSPI_CTRLB_MODE_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_LOOPEN; + tmp |= value << QSPI_CTRLB_LOOPEN_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_WDRBT; + tmp |= value << QSPI_CTRLB_WDRBT_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_SMEMREG; + tmp |= value << QSPI_CTRLB_SMEMREG_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_CSMODE_Msk; + tmp |= QSPI_CTRLB_CSMODE(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DATALEN_Msk; + tmp |= QSPI_CTRLB_DATALEN(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYBCT_Msk; + tmp |= QSPI_CTRLB_DLYBCT(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYCS_Msk; + tmp |= QSPI_CTRLB_DLYCS(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLB.reg; +} + +static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPOL; + tmp |= value << QSPI_BAUD_CPOL_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPHA; + tmp |= value << QSPI_BAUD_CPHA_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_BAUD_Msk; + tmp |= QSPI_BAUD_BAUD(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_DLYBS_Msk; + tmp |= QSPI_BAUD_DLYBS(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) +{ + return ((Qspi *)hw)->BAUD.reg; +} + +static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, + hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= ~QSPI_INSTRADDR_ADDR_Msk; + tmp |= QSPI_INSTRADDR_ADDR(data); + ((Qspi *)hw)->INSTRADDR.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRADDR.reg; +} + +static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; + tmp |= QSPI_INSTRCTRL_INSTR(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; + tmp |= QSPI_INSTRCTRL_OPTCODE(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRCTRL.reg; +} + +static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_INSTREN; + tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDREN; + tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; + tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DATAEN; + tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDRLEN; + tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_CRMODE; + tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DDREN; + tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; + tmp |= QSPI_INSTRFRAME_WIDTH(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; + tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; + tmp |= QSPI_INSTRFRAME_TFRTYPE(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; + tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRFRAME.reg; +} + +static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_ENABLE; + tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, + hri_qspi_scrambctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->SCRAMBCTRL.reg; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) +{ + return ((Qspi *)hw)->RXDATA.reg; +} + +static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; +} + +static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; +} + +static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) +{ + return ((Qspi *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_QSPI_D51_H_INCLUDED */ +#endif /* _SAMD51_QSPI_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_ramecc_d51.h b/atmel-samd/asf4/samd51/hri/hri_ramecc_d51.h new file mode 100644 index 0000000000000..97147807db98f --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_ramecc_d51.h @@ -0,0 +1,371 @@ +/** + * \file + * + * \brief SAM RAMECC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_RAMECC_COMPONENT_ +#ifndef _HRI_RAMECC_D51_H_INCLUDED_ +#define _HRI_RAMECC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) +#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RAMECC_CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ramecc_erraddr_reg_t; +typedef uint8_t hri_ramecc_dbgctrl_reg_t; +typedef uint8_t hri_ramecc_intenset_reg_t; +typedef uint8_t hri_ramecc_intflag_reg_t; +typedef uint8_t hri_ramecc_status_reg_t; + +static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; +} + +static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; + } +} + +static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; +} + +static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; +} + +static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; + } +} + +static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; +} + +static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENSET.reg = mask; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTENSET.reg; +} + +static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) +{ + ((Ramecc *)hw)->INTENSET.reg = data; + ((Ramecc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTFLAG.reg; +} + +static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + ((Ramecc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCDIS; + tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCELOG; + tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg = data; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ramecc *)hw)->DBGCTRL.reg; +} + +static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) +{ + return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) +{ + return ((Ramecc *)hw)->STATUS.reg; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, + hri_ramecc_erraddr_reg_t mask) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ramecc *)hw)->ERRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) +{ + return ((Ramecc *)hw)->ERRADDR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RAMECC_D51_H_INCLUDED */ +#endif /* _SAMD51_RAMECC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_rstc_d51.h b/atmel-samd/asf4/samd51/hri/hri_rstc_d51.h new file mode 100644 index 0000000000000..75dde1108e435 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_rstc_d51.h @@ -0,0 +1,151 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_D51_H_INCLUDED_ +#define _HRI_RSTC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_D51_H_INCLUDED */ +#endif /* _SAMD51_RSTC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_rtc_d51.h b/atmel-samd/asf4/samd51/hri/hri_rtc_d51.h new file mode 100644 index 0000000000000..1df33141c1270 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_rtc_d51.h @@ -0,0 +1,12310 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_RTC_COMPONENT_ +#ifndef _HRI_RTC_D51_H_INCLUDED_ +#define _HRI_RTC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_ctrlb_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_ctrlb_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_ctrlb_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_bkup_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_gp_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode0_tampctrl_reg_t; +typedef uint32_t hri_rtcmode0_tampid_reg_t; +typedef uint32_t hri_rtcmode0_timestamp_reg_t; +typedef uint32_t hri_rtcmode1_bkup_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_gp_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_tampctrl_reg_t; +typedef uint32_t hri_rtcmode1_tampid_reg_t; +typedef uint32_t hri_rtcmode1_timestamp_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_bkup_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_gp_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_tampctrl_reg_t; +typedef uint32_t hri_rtcmode2_tampid_reg_t; +typedef uint32_t hri_rtcmode2_timestamp_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode0_dbgctrl_reg_t; +typedef uint8_t hri_rtcmode0_freqcorr_reg_t; +typedef uint8_t hri_rtcmode1_dbgctrl_reg_t; +typedef uint8_t hri_rtcmode1_freqcorr_reg_t; +typedef uint8_t hri_rtcmode2_dbgctrl_reg_t; +typedef uint8_t hri_rtcmode2_freqcorr_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcalarm_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_BKTRST; + tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_GPTRST; + tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP0EN; + tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP2EN; + tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_RTCOUT; + tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DMAEN; + tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; + tmp |= RTC_MODE2_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; + tmp |= RTC_MODE2_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRLB.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE2.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_get_DBGCTRL_reg(const void *const hw, + hri_rtcmode2_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.DBGCTRL.reg; +} + +static inline void hri_rtcmode2_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_VALUE_bf(const void *const hw, + hri_rtcmode2_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_reg(const void *const hw, + hri_rtcmode2_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.FREQCORR.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.FREQCORR.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode2_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.GP[index].reg |= RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_get_GP_GP_bf(const void *const hw, uint8_t index, + hri_rtcmode2_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE2.GP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.GP[index].reg &= ~RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + ((Rtc *)hw)->MODE2.GP[index].reg ^= RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.GP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_get_GP_reg(const void *const hw, uint8_t index, + hri_rtcmode2_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.GP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.GP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.GP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_read_GP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE2.GP[index].reg; +} + +static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(const void *const hw, + hri_rtcmode2_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(const void *const hw, + hri_rtcmode2_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(const void *const hw, + hri_rtcmode2_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(const void *const hw, + hri_rtcmode2_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(const void *const hw, + hri_rtcmode2_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_reg(const void *const hw, + hri_rtcmode2_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.TAMPCTRL.reg; +} + +static inline void hri_rtcmode2_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampid_reg_t hri_rtcmode2_get_TAMPID_reg(const void *const hw, + hri_rtcmode2_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_tampid_reg_t hri_rtcmode2_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.TAMPID.reg; +} + +static inline void hri_rtcmode2_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, + hri_rtcmode2_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE2.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_get_BKUP_reg(const void *const hw, uint8_t index, + hri_rtcmode2_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE2.BKUP[index].reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_BKTRST; + tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_GPTRST; + tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP0EN; + tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP2EN; + tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_RTCOUT; + tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DMAEN; + tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; + tmp |= RTC_MODE0_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; + tmp |= RTC_MODE0_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRLB.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_get_DBGCTRL_reg(const void *const hw, + hri_rtcmode0_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtcmode0_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_VALUE_bf(const void *const hw, + hri_rtcmode0_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_reg(const void *const hw, + hri_rtcmode0_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode0_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_get_GP_GP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE0.GP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_get_GP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_read_GP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(const void *const hw, + hri_rtcmode0_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(const void *const hw, + hri_rtcmode0_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(const void *const hw, + hri_rtcmode0_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(const void *const hw, + hri_rtcmode0_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(const void *const hw, + hri_rtcmode0_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_reg(const void *const hw, + hri_rtcmode0_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; +} + +static inline void hri_rtcmode0_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampid_reg_t hri_rtcmode0_get_TAMPID_reg(const void *const hw, + hri_rtcmode0_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_tampid_reg_t hri_rtcmode0_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPID.reg; +} + +static inline void hri_rtcmode0_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_get_BKUP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.BKUP[index].reg; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_BKTRST; + tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_GPTRST; + tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP0EN; + tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP2EN; + tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_RTCOUT; + tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DMAEN; + tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; + tmp |= RTC_MODE1_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; + tmp |= RTC_MODE1_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRLB.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE1.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_get_DBGCTRL_reg(const void *const hw, + hri_rtcmode1_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.DBGCTRL.reg; +} + +static inline void hri_rtcmode1_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_VALUE_bf(const void *const hw, + hri_rtcmode1_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_reg(const void *const hw, + hri_rtcmode1_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.FREQCORR.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.FREQCORR.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.GP[index].reg |= RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_get_GP_GP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE1.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE1.GP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.GP[index].reg &= ~RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + ((Rtc *)hw)->MODE1.GP[index].reg ^= RTC_GP_GP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.GP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_get_GP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.GP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.GP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.GP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_read_GP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE1.GP[index].reg; +} + +static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(const void *const hw, + hri_rtcmode1_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(const void *const hw, + hri_rtcmode1_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(const void *const hw, + hri_rtcmode1_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(const void *const hw, + hri_rtcmode1_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(const void *const hw, + hri_rtcmode1_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_reg(const void *const hw, + hri_rtcmode1_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.TAMPCTRL.reg; +} + +static inline void hri_rtcmode1_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampid_reg_t hri_rtcmode1_get_TAMPID_reg(const void *const hw, + hri_rtcmode1_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_tampid_reg_t hri_rtcmode1_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.TAMPID.reg; +} + +static inline void hri_rtcmode1_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE1.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_get_BKUP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE1.BKUP[index].reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_D51_H_INCLUDED */ +#endif /* _SAMD51_RTC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_sdhc_d51.h b/atmel-samd/asf4/samd51/hri/hri_sdhc_d51.h new file mode 100644 index 0000000000000..2095b6682253b --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_sdhc_d51.h @@ -0,0 +1,9878 @@ +/** + * \file + * + * \brief SAM SDHC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_SDHC_COMPONENT_ +#ifndef _HRI_SDHC_D51_H_INCLUDED_ +#define _HRI_SDHC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) +#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDHC_CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sdhc_acesr_reg_t; +typedef uint16_t hri_sdhc_bcr_reg_t; +typedef uint16_t hri_sdhc_bsr_reg_t; +typedef uint16_t hri_sdhc_ccr_reg_t; +typedef uint16_t hri_sdhc_cr_reg_t; +typedef uint16_t hri_sdhc_eisier_reg_t; +typedef uint16_t hri_sdhc_eister_reg_t; +typedef uint16_t hri_sdhc_eistr_reg_t; +typedef uint16_t hri_sdhc_feraces_reg_t; +typedef uint16_t hri_sdhc_fereis_reg_t; +typedef uint16_t hri_sdhc_hc2r_reg_t; +typedef uint16_t hri_sdhc_hcvr_reg_t; +typedef uint16_t hri_sdhc_nisier_reg_t; +typedef uint16_t hri_sdhc_nister_reg_t; +typedef uint16_t hri_sdhc_nistr_reg_t; +typedef uint16_t hri_sdhc_pvr_reg_t; +typedef uint16_t hri_sdhc_sisr_reg_t; +typedef uint16_t hri_sdhc_tmr_reg_t; +typedef uint32_t hri_sdhc_acr_reg_t; +typedef uint32_t hri_sdhc_arg1r_reg_t; +typedef uint32_t hri_sdhc_asar_reg_t; +typedef uint32_t hri_sdhc_bdpr_reg_t; +typedef uint32_t hri_sdhc_ca0r_reg_t; +typedef uint32_t hri_sdhc_ca1r_reg_t; +typedef uint32_t hri_sdhc_cacr_reg_t; +typedef uint32_t hri_sdhc_cc2r_reg_t; +typedef uint32_t hri_sdhc_mccar_reg_t; +typedef uint32_t hri_sdhc_psr_reg_t; +typedef uint32_t hri_sdhc_rr_reg_t; +typedef uint32_t hri_sdhc_ssar_reg_t; +typedef uint8_t hri_sdhc_aesr_reg_t; +typedef uint8_t hri_sdhc_bgcr_reg_t; +typedef uint8_t hri_sdhc_dbgr_reg_t; +typedef uint8_t hri_sdhc_hc1r_reg_t; +typedef uint8_t hri_sdhc_mc1r_reg_t; +typedef uint8_t hri_sdhc_mc2r_reg_t; +typedef uint8_t hri_sdhc_pcr_reg_t; +typedef uint8_t hri_sdhc_srr_reg_t; +typedef uint8_t hri_sdhc_tcr_reg_t; +typedef uint8_t hri_sdhc_wcr_reg_t; + +static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; + tmp |= SDHC_SSAR_CMD23_ARG2(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_ADDR_Msk; + tmp |= SDHC_SSAR_ADDR(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SSAR.reg; +} + +static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SSAR.reg; +} + +static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_LEDCTRL; + tmp |= value << SDHC_HC1R_LEDCTRL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DW; + tmp |= value << SDHC_HC1R_DW_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_HSEN; + tmp |= value << SDHC_HC1R_HSEN_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDTL; + tmp |= value << SDHC_HC1R_CARDDTL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDSEL; + tmp |= value << SDHC_HC1R_CARDDSEL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_EMMC_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_EMMC_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_EMMC_DW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_EMMC_DW) >> SDHC_HC1R_EMMC_DW_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_EMMC_DW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_EMMC_DW; + tmp |= value << SDHC_HC1R_EMMC_DW_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_EMMC_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_EMMC_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_EMMC_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_EMMC_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_EMMC_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_EMMC_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_EMMC_HSEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_EMMC_HSEN) >> SDHC_HC1R_EMMC_HSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_EMMC_HSEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_EMMC_HSEN; + tmp |= value << SDHC_HC1R_EMMC_HSEN_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_EMMC_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_EMMC_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_EMMC_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DMASEL_Msk; + tmp |= SDHC_HC1R_DMASEL(data); + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_EMMC_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_EMMC_DMASEL(mask)) >> SDHC_HC1R_EMMC_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_EMMC_DMASEL_Msk; + tmp |= SDHC_HC1R_EMMC_DMASEL(data); + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_EMMC_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_EMMC_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_EMMC_DMASEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_EMMC_DMASEL_Msk) >> SDHC_HC1R_EMMC_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC1R.reg; +} + +static inline void hri_sdhc_set_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC1R.reg; +} + +static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_STPBGR; + tmp |= value << SDHC_BGCR_STPBGR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_CONTR; + tmp |= value << SDHC_BGCR_CONTR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_RWCTRL; + tmp |= value << SDHC_BGCR_RWCTRL_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_INTBG; + tmp |= value << SDHC_BGCR_INTBG_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_EMMC_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_EMMC_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_EMMC_STPBGR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_EMMC_STPBGR) >> SDHC_BGCR_EMMC_STPBGR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_EMMC_STPBGR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_EMMC_STPBGR; + tmp |= value << SDHC_BGCR_EMMC_STPBGR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_EMMC_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_EMMC_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_EMMC_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_EMMC_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_EMMC_CONTR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_EMMC_CONTR) >> SDHC_BGCR_EMMC_CONTR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_EMMC_CONTR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_EMMC_CONTR; + tmp |= value << SDHC_BGCR_EMMC_CONTR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_EMMC_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_EMMC_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_EMMC_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BGCR.reg; +} + +static inline void hri_sdhc_set_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BGCR.reg; +} + +static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CMDC; + tmp |= value << SDHC_NISTR_CMDC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_TRFC; + tmp |= value << SDHC_NISTR_TRFC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BLKGE; + tmp |= value << SDHC_NISTR_BLKGE_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_DMAINT; + tmp |= value << SDHC_NISTR_DMAINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BWRRDY; + tmp |= value << SDHC_NISTR_BWRRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BRDRDY; + tmp |= value << SDHC_NISTR_BRDRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINS; + tmp |= value << SDHC_NISTR_CINS_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CREM; + tmp |= value << SDHC_NISTR_CREM_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINT; + tmp |= value << SDHC_NISTR_CINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_ERRINT; + tmp |= value << SDHC_NISTR_ERRINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_CMDC) >> SDHC_NISTR_EMMC_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_CMDC; + tmp |= value << SDHC_NISTR_EMMC_CMDC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_TRFC) >> SDHC_NISTR_EMMC_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_TRFC; + tmp |= value << SDHC_NISTR_EMMC_TRFC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BLKGE) >> SDHC_NISTR_EMMC_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BLKGE; + tmp |= value << SDHC_NISTR_EMMC_BLKGE_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_DMAINT) >> SDHC_NISTR_EMMC_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_DMAINT; + tmp |= value << SDHC_NISTR_EMMC_DMAINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BWRRDY) >> SDHC_NISTR_EMMC_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BWRRDY; + tmp |= value << SDHC_NISTR_EMMC_BWRRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BRDRDY) >> SDHC_NISTR_EMMC_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BRDRDY; + tmp |= value << SDHC_NISTR_EMMC_BRDRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BOOTAR; + tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_ERRINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_ERRINT) >> SDHC_NISTR_EMMC_ERRINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_ERRINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_ERRINT; + tmp |= value << SDHC_NISTR_EMMC_ERRINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTR.reg; +} + +static inline void hri_sdhc_set_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTR.reg; +} + +static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDTEO; + tmp |= value << SDHC_EISTR_CMDTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDCRC; + tmp |= value << SDHC_EISTR_CMDCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDEND; + tmp |= value << SDHC_EISTR_CMDEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDIDX; + tmp |= value << SDHC_EISTR_CMDIDX_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATTEO; + tmp |= value << SDHC_EISTR_DATTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATCRC; + tmp |= value << SDHC_EISTR_DATCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATEND; + tmp |= value << SDHC_EISTR_DATEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CURLIM; + tmp |= value << SDHC_EISTR_CURLIM_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ACMD; + tmp |= value << SDHC_EISTR_ACMD_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ADMA; + tmp |= value << SDHC_EISTR_ADMA_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_CMDTEO) >> SDHC_EISTR_EMMC_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_CMDTEO; + tmp |= value << SDHC_EISTR_EMMC_CMDTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_CMDCRC) >> SDHC_EISTR_EMMC_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_CMDCRC; + tmp |= value << SDHC_EISTR_EMMC_CMDCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_CMDEND) >> SDHC_EISTR_EMMC_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_CMDEND; + tmp |= value << SDHC_EISTR_EMMC_CMDEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_CMDIDX) >> SDHC_EISTR_EMMC_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_CMDIDX; + tmp |= value << SDHC_EISTR_EMMC_CMDIDX_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_DATTEO) >> SDHC_EISTR_EMMC_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_DATTEO; + tmp |= value << SDHC_EISTR_EMMC_DATTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_DATCRC) >> SDHC_EISTR_EMMC_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_DATCRC; + tmp |= value << SDHC_EISTR_EMMC_DATCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_DATEND) >> SDHC_EISTR_EMMC_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_DATEND; + tmp |= value << SDHC_EISTR_EMMC_DATEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_CURLIM) >> SDHC_EISTR_EMMC_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_CURLIM; + tmp |= value << SDHC_EISTR_EMMC_CURLIM_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_ACMD) >> SDHC_EISTR_EMMC_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_ACMD; + tmp |= value << SDHC_EISTR_EMMC_ACMD_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_ADMA) >> SDHC_EISTR_EMMC_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_ADMA; + tmp |= value << SDHC_EISTR_EMMC_ADMA_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_BOOTAE; + tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTR.reg; +} + +static inline void hri_sdhc_set_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTR.reg; +} + +static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CMDC; + tmp |= value << SDHC_NISTER_CMDC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_TRFC; + tmp |= value << SDHC_NISTER_TRFC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BLKGE; + tmp |= value << SDHC_NISTER_BLKGE_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_DMAINT; + tmp |= value << SDHC_NISTER_DMAINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BWRRDY; + tmp |= value << SDHC_NISTER_BWRRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BRDRDY; + tmp |= value << SDHC_NISTER_BRDRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINS; + tmp |= value << SDHC_NISTER_CINS_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CREM; + tmp |= value << SDHC_NISTER_CREM_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINT; + tmp |= value << SDHC_NISTER_CINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_CMDC) >> SDHC_NISTER_EMMC_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_CMDC; + tmp |= value << SDHC_NISTER_EMMC_CMDC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_TRFC) >> SDHC_NISTER_EMMC_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_TRFC; + tmp |= value << SDHC_NISTER_EMMC_TRFC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BLKGE) >> SDHC_NISTER_EMMC_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BLKGE; + tmp |= value << SDHC_NISTER_EMMC_BLKGE_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_DMAINT) >> SDHC_NISTER_EMMC_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_DMAINT; + tmp |= value << SDHC_NISTER_EMMC_DMAINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BWRRDY) >> SDHC_NISTER_EMMC_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BWRRDY; + tmp |= value << SDHC_NISTER_EMMC_BWRRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BRDRDY) >> SDHC_NISTER_EMMC_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BRDRDY; + tmp |= value << SDHC_NISTER_EMMC_BRDRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BOOTAR; + tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTER.reg; +} + +static inline void hri_sdhc_set_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTER.reg; +} + +static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDTEO; + tmp |= value << SDHC_EISTER_CMDTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDCRC; + tmp |= value << SDHC_EISTER_CMDCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDEND; + tmp |= value << SDHC_EISTER_CMDEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDIDX; + tmp |= value << SDHC_EISTER_CMDIDX_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATTEO; + tmp |= value << SDHC_EISTER_DATTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATCRC; + tmp |= value << SDHC_EISTER_DATCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATEND; + tmp |= value << SDHC_EISTER_DATEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CURLIM; + tmp |= value << SDHC_EISTER_CURLIM_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ACMD; + tmp |= value << SDHC_EISTER_ACMD_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ADMA; + tmp |= value << SDHC_EISTER_ADMA_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_CMDTEO) >> SDHC_EISTER_EMMC_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_CMDTEO; + tmp |= value << SDHC_EISTER_EMMC_CMDTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_CMDCRC) >> SDHC_EISTER_EMMC_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_CMDCRC; + tmp |= value << SDHC_EISTER_EMMC_CMDCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_CMDEND) >> SDHC_EISTER_EMMC_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_CMDEND; + tmp |= value << SDHC_EISTER_EMMC_CMDEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_CMDIDX) >> SDHC_EISTER_EMMC_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_CMDIDX; + tmp |= value << SDHC_EISTER_EMMC_CMDIDX_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_DATTEO) >> SDHC_EISTER_EMMC_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_DATTEO; + tmp |= value << SDHC_EISTER_EMMC_DATTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_DATCRC) >> SDHC_EISTER_EMMC_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_DATCRC; + tmp |= value << SDHC_EISTER_EMMC_DATCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_DATEND) >> SDHC_EISTER_EMMC_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_DATEND; + tmp |= value << SDHC_EISTER_EMMC_DATEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_CURLIM) >> SDHC_EISTER_EMMC_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_CURLIM; + tmp |= value << SDHC_EISTER_EMMC_CURLIM_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_ACMD) >> SDHC_EISTER_EMMC_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_ACMD; + tmp |= value << SDHC_EISTER_EMMC_ACMD_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_ADMA) >> SDHC_EISTER_EMMC_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_ADMA; + tmp |= value << SDHC_EISTER_EMMC_ADMA_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_BOOTAE; + tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTER.reg; +} + +static inline void hri_sdhc_set_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTER.reg; +} + +static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CMDC; + tmp |= value << SDHC_NISIER_CMDC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_TRFC; + tmp |= value << SDHC_NISIER_TRFC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BLKGE; + tmp |= value << SDHC_NISIER_BLKGE_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_DMAINT; + tmp |= value << SDHC_NISIER_DMAINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BWRRDY; + tmp |= value << SDHC_NISIER_BWRRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BRDRDY; + tmp |= value << SDHC_NISIER_BRDRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINS; + tmp |= value << SDHC_NISIER_CINS_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CREM; + tmp |= value << SDHC_NISIER_CREM_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINT; + tmp |= value << SDHC_NISIER_CINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_CMDC) >> SDHC_NISIER_EMMC_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_CMDC; + tmp |= value << SDHC_NISIER_EMMC_CMDC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_TRFC) >> SDHC_NISIER_EMMC_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_TRFC; + tmp |= value << SDHC_NISIER_EMMC_TRFC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BLKGE) >> SDHC_NISIER_EMMC_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BLKGE; + tmp |= value << SDHC_NISIER_EMMC_BLKGE_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_DMAINT) >> SDHC_NISIER_EMMC_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_DMAINT; + tmp |= value << SDHC_NISIER_EMMC_DMAINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BWRRDY) >> SDHC_NISIER_EMMC_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BWRRDY; + tmp |= value << SDHC_NISIER_EMMC_BWRRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BRDRDY) >> SDHC_NISIER_EMMC_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BRDRDY; + tmp |= value << SDHC_NISIER_EMMC_BRDRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BOOTAR; + tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISIER.reg; +} + +static inline void hri_sdhc_set_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISIER.reg; +} + +static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDTEO; + tmp |= value << SDHC_EISIER_CMDTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDCRC; + tmp |= value << SDHC_EISIER_CMDCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDEND; + tmp |= value << SDHC_EISIER_CMDEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDIDX; + tmp |= value << SDHC_EISIER_CMDIDX_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATTEO; + tmp |= value << SDHC_EISIER_DATTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATCRC; + tmp |= value << SDHC_EISIER_DATCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATEND; + tmp |= value << SDHC_EISIER_DATEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CURLIM; + tmp |= value << SDHC_EISIER_CURLIM_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ACMD; + tmp |= value << SDHC_EISIER_ACMD_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ADMA; + tmp |= value << SDHC_EISIER_ADMA_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_CMDTEO) >> SDHC_EISIER_EMMC_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_CMDTEO; + tmp |= value << SDHC_EISIER_EMMC_CMDTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_CMDCRC) >> SDHC_EISIER_EMMC_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_CMDCRC; + tmp |= value << SDHC_EISIER_EMMC_CMDCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_CMDEND) >> SDHC_EISIER_EMMC_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_CMDEND; + tmp |= value << SDHC_EISIER_EMMC_CMDEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_CMDIDX) >> SDHC_EISIER_EMMC_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_CMDIDX; + tmp |= value << SDHC_EISIER_EMMC_CMDIDX_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_DATTEO) >> SDHC_EISIER_EMMC_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_DATTEO; + tmp |= value << SDHC_EISIER_EMMC_DATTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_DATCRC) >> SDHC_EISIER_EMMC_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_DATCRC; + tmp |= value << SDHC_EISIER_EMMC_DATCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_DATEND) >> SDHC_EISIER_EMMC_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_DATEND; + tmp |= value << SDHC_EISIER_EMMC_DATEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_CURLIM) >> SDHC_EISIER_EMMC_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_CURLIM; + tmp |= value << SDHC_EISIER_EMMC_CURLIM_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_ACMD) >> SDHC_EISIER_EMMC_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_ACMD; + tmp |= value << SDHC_EISIER_EMMC_ACMD_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_ADMA) >> SDHC_EISIER_EMMC_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_ADMA; + tmp |= value << SDHC_EISIER_EMMC_ADMA_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_BOOTAE; + tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISIER.reg; +} + +static inline void hri_sdhc_set_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISIER.reg; +} + +static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_VS18EN; + tmp |= value << SDHC_HC2R_VS18EN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EXTUN; + tmp |= value << SDHC_HC2R_EXTUN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_SLCKSEL; + tmp |= value << SDHC_HC2R_SLCKSEL_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_ASINTEN; + tmp |= value << SDHC_HC2R_ASINTEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_PVALEN; + tmp |= value << SDHC_HC2R_PVALEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EMMC_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EMMC_EXTUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_EXTUN) >> SDHC_HC2R_EMMC_EXTUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_EXTUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_EXTUN; + tmp |= value << SDHC_HC2R_EMMC_EXTUN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_SLCKSEL) >> SDHC_HC2R_EMMC_SLCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_SLCKSEL; + tmp |= value << SDHC_HC2R_EMMC_SLCKSEL_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EMMC_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EMMC_PVALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_PVALEN) >> SDHC_HC2R_EMMC_PVALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_PVALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_PVALEN; + tmp |= value << SDHC_HC2R_EMMC_PVALEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_UHSMS_Msk; + tmp |= SDHC_HC2R_UHSMS(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_DRVSEL_Msk; + tmp |= SDHC_HC2R_DRVSEL(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; + tmp |= SDHC_HC2R_EMMC_HS200EN(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_DRVSEL(mask)) >> SDHC_HC2R_EMMC_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_DRVSEL_Msk; + tmp |= SDHC_HC2R_EMMC_DRVSEL(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_DRVSEL_Msk) >> SDHC_HC2R_EMMC_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC2R.reg; +} + +static inline void hri_sdhc_set_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC2R.reg; +} + +static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FERACES.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FEREIS.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; + tmp |= SDHC_BSR_BLOCKSIZE(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BOUNDARY_Msk; + tmp |= SDHC_BSR_BOUNDARY(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BSR.reg; +} + +static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= ~SDHC_BCR_BCNT_Msk; + tmp |= SDHC_BCR_BCNT(data); + ((Sdhc *)hw)->BCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BCR.reg; +} + +static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= ~SDHC_ARG1R_ARG_Msk; + tmp |= SDHC_ARG1R_ARG(data); + ((Sdhc *)hw)->ARG1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ARG1R.reg; +} + +static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DMAEN; + tmp |= value << SDHC_TMR_DMAEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_BCEN; + tmp |= value << SDHC_TMR_BCEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DTDSEL; + tmp |= value << SDHC_TMR_DTDSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_MSBSEL; + tmp |= value << SDHC_TMR_MSBSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_ACMDEN_Msk; + tmp |= SDHC_TMR_ACMDEN(data); + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TMR.reg; +} + +static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDCCEN; + tmp |= value << SDHC_CR_CMDCCEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDICEN; + tmp |= value << SDHC_CR_CMDICEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_DPSEL; + tmp |= value << SDHC_CR_DPSEL_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_RESPTYP_Msk; + tmp |= SDHC_CR_RESPTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDTYP_Msk; + tmp |= SDHC_CR_CMDTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDIDX_Msk; + tmp |= SDHC_CR_CMDIDX(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CR.reg; +} + +static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= ~SDHC_BDPR_BUFDATA_Msk; + tmp |= SDHC_BDPR_BUFDATA(data); + ((Sdhc *)hw)->BDPR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BDPR.reg; +} + +static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBPWR; + tmp |= value << SDHC_PCR_SDBPWR_Pos; + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBVSEL_Msk; + tmp |= SDHC_PCR_SDBVSEL(data); + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PCR.reg; +} + +static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINT; + tmp |= value << SDHC_WCR_WKENCINT_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINS; + tmp |= value << SDHC_WCR_WKENCINS_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCREM; + tmp |= value << SDHC_WCR_WKENCREM_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->WCR.reg; +} + +static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKEN; + tmp |= value << SDHC_CCR_INTCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKS; + tmp |= value << SDHC_CCR_INTCLKS_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKEN; + tmp |= value << SDHC_CCR_SDCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_CLKGSEL; + tmp |= value << SDHC_CCR_CLKGSEL_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; + tmp |= SDHC_CCR_USDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; + tmp |= SDHC_CCR_SDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CCR.reg; +} + +static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= ~SDHC_TCR_DTCVAL_Msk; + tmp |= SDHC_TCR_DTCVAL(data); + ((Sdhc *)hw)->TCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TCR.reg; +} + +static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTALL; + tmp |= value << SDHC_SRR_SWRSTALL_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTCMD; + tmp |= value << SDHC_SRR_SWRSTCMD_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTDAT; + tmp |= value << SDHC_SRR_SWRSTDAT_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SRR.reg; +} + +static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, + hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= ~SDHC_ASAR_ADMASA_Msk; + tmp |= SDHC_ASAR_ADMASA(data); + ((Sdhc *)hw)->ASAR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->ASAR[index].reg; +} + +static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_CLKGSEL; + tmp |= value << SDHC_PVR_CLKGSEL_Pos; + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; + tmp |= SDHC_PVR_SDCLKFSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_DRVSEL_Msk; + tmp |= SDHC_PVR_DRVSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->PVR[index].reg; +} + +static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_DDR; + tmp |= value << SDHC_MC1R_DDR_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_OPD; + tmp |= value << SDHC_MC1R_OPD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_BOOTA; + tmp |= value << SDHC_MC1R_BOOTA_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_RSTN; + tmp |= value << SDHC_MC1R_RSTN_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_FCD; + tmp |= value << SDHC_MC1R_FCD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_CMDTYP_Msk; + tmp |= SDHC_MC1R_CMDTYP(data); + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MC1R.reg; +} + +static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= ~SDHC_ACR_BMAX_Msk; + tmp |= SDHC_ACR_BMAX(data); + ((Sdhc *)hw)->ACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACR.reg; +} + +static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= ~SDHC_CC2R_FSDCLKD; + tmp |= value << SDHC_CC2R_FSDCLKD_Pos; + ((Sdhc *)hw)->CC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CC2R.reg; +} + +static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_CAPWREN; + tmp |= value << SDHC_CACR_CAPWREN_Pos; + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_KEY_Msk; + tmp |= SDHC_CACR_KEY(data); + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CACR.reg; +} + +static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= ~SDHC_DBGR_NIDBG; + tmp |= value << SDHC_DBGR_NIDBG_Pos; + ((Sdhc *)hw)->DBGR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->DBGR.reg; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->RR[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->RR[index].reg; +} + +static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; +} + +static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; +} + +static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PSR.reg; +} + +static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; +} + +static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->ACESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACESR.reg; +} + +static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA0R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA0R.reg; +} + +static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA1R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA1R.reg; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->MCCAR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MCCAR.reg; +} + +static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->AESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->AESR.reg; +} + +static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->SISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SISR.reg; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HCVR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HCVR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDHC_D51_H_INCLUDED */ +#endif /* _SAMD51_SDHC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_sercom_d51.h b/atmel-samd/asf4/samd51/hri/hri_sercom_d51.h new file mode 100644 index 0000000000000..9e09d23f3436e --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_sercom_d51.h @@ -0,0 +1,8591 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_D51_H_INCLUDED_ +#define _HRI_SERCOM_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_length_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_length_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_length_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cm_data_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cs_data_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_ctrlc_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_data_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_DATA32B; + tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; + tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLC.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LENEN; + tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; + tmp |= SERCOM_SPI_LENGTH_LEN(data); + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.LENGTH.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, + hri_sercomi2cm_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD(mask)) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD_Msk) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD(mask)) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD_Msk) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_USARTFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD(mask)) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_USARTFP_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_USARTFP_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_USARTFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_USARTFP_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD_Msk) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXINV; + tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXINV; + tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; + tmp |= SERCOM_USART_CTRLB_LINCMD(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_INACK; + tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DSNACK; + tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; + tmp |= SERCOM_USART_CTRLC_BRKLEN(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; + tmp |= SERCOM_USART_CTRLC_HDRDLY(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; + tmp |= SERCOM_USART_CTRLC_MAXITER(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; + tmp |= SERCOM_USART_CTRLC_DATA32B(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; + tmp |= SERCOM_USART_LENGTH_LEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; + tmp |= SERCOM_USART_LENGTH_LENEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.LENGTH.reg; +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, + hri_sercomusart_rxerrcnt_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXERRCNT.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; + tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLC.reg; +} + +static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LENEN; + tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; + tmp |= SERCOM_I2CS_LENGTH_LEN(data); + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.LENGTH.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_D51_H_INCLUDED */ +#endif /* _SAMD51_SERCOM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_supc_d51.h b/atmel-samd/asf4/samd51/hri/hri_supc_d51.h new file mode 100644 index 0000000000000..90797c85b7dd9 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_supc_d51.h @@ -0,0 +1,2311 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_D51_H_INCLUDED_ +#define _HRI_SUPC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod12_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; +} + +static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; +} + +static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; +} + +static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; +} + +static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; +} + +static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; +} + +static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNHIB; + tmp |= value << SUPC_BOD33_RUNHIB_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST_Msk; + tmp |= SUPC_BOD33_HYST(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; + tmp |= SUPC_BOD33_VBATLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ENABLE; + tmp |= value << SUPC_BOD12_ENABLE_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_HYST; + tmp |= value << SUPC_BOD12_HYST_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_STDBYCFG; + tmp |= value << SUPC_BOD12_STDBYCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_RUNSTDBY; + tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTCFG; + tmp |= value << SUPC_BOD12_ACTCFG_Pos; + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_ACTION_Msk; + tmp |= SUPC_BOD12_ACTION(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_PSEL_Msk; + tmp |= SUPC_BOD12_PSEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= ~SUPC_BOD12_LEVEL_Msk; + tmp |= SUPC_BOD12_LEVEL(data); + ((Supc *)hw)->BOD12.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD12.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD12.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD12.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL; + tmp |= value << SUPC_VREG_SEL_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNBKUP; + tmp |= value << SUPC_VREG_RUNBKUP_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSEN; + tmp |= value << SUPC_VREG_VSEN_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSSEL; + tmp |= value << SUPC_VREF_TSSEL_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF; + tmp |= value << SUPC_BBPS_CONF_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_D51_H_INCLUDED */ +#endif /* _SAMD51_SUPC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_tal_d51.h b/atmel-samd/asf4/samd51/hri/hri_tal_d51.h new file mode 100644 index 0000000000000..cacb98a2da6d8 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_tal_d51.h @@ -0,0 +1,10867 @@ +/** + * \file + * + * \brief SAM TAL + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_TAL_COMPONENT_ +#ifndef _HRI_TAL_D51_H_INCLUDED_ +#define _HRI_TAL_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TAL_CRITICAL_SECTIONS) +#define TAL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TAL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TAL_CRITICAL_SECTION_ENTER() +#define TAL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tal_brkstatus_reg_t; +typedef uint16_t hri_tal_evctrl_reg_t; +typedef uint16_t hri_tal_irqmon_reg_t; +typedef uint32_t hri_tal_cpuirqs_reg_t; +typedef uint32_t hri_tal_dmacpusel0_reg_t; +typedef uint32_t hri_tal_dmacpusel1_reg_t; +typedef uint32_t hri_tal_eiccpusel0_reg_t; +typedef uint32_t hri_tal_evcpusel0_reg_t; +typedef uint32_t hri_tal_intcpusel0_reg_t; +typedef uint32_t hri_tal_intcpusel1_reg_t; +typedef uint32_t hri_tal_intcpusel2_reg_t; +typedef uint32_t hri_tal_intcpusel3_reg_t; +typedef uint32_t hri_tal_intcpusel4_reg_t; +typedef uint32_t hri_tal_intcpusel5_reg_t; +typedef uint32_t hri_tal_intcpusel6_reg_t; +typedef uint32_t hri_tal_intcpusel7_reg_t; +typedef uint32_t hri_tal_intcpusel8_reg_t; +typedef uint32_t hri_tal_irqtrig_reg_t; +typedef uint32_t hri_tal_sflag_reg_t; +typedef uint32_t hri_tal_smask_reg_t; +typedef uint32_t hri_talcpuirqs_cpuirqs_reg_t; +typedef uint32_t hri_talsmasks_smask_reg_t; +typedef uint8_t hri_tal_ctictrla_reg_t; +typedef uint8_t hri_tal_ctimask_reg_t; +typedef uint8_t hri_tal_ctrla_reg_t; +typedef uint8_t hri_tal_extctrl_reg_t; +typedef uint8_t hri_tal_globmask_reg_t; +typedef uint8_t hri_tal_halt_reg_t; +typedef uint8_t hri_tal_intenset_reg_t; +typedef uint8_t hri_tal_intflag_reg_t; +typedef uint8_t hri_tal_intstatus_reg_t; +typedef uint8_t hri_tal_restart_reg_t; +typedef uint8_t hri_tal_sflagclrr_reg_t; +typedef uint8_t hri_talctis_ctictrla_reg_t; +typedef uint8_t hri_talctis_ctimask_reg_t; + +static inline void hri_talsmasks_set_SMASK_IPS0_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS0) >> TAL_SMASK_IPS0_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS0; + tmp |= value << TAL_SMASK_IPS0_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS0_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS0_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS1_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS1) >> TAL_SMASK_IPS1_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS1; + tmp |= value << TAL_SMASK_IPS1_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS1_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS1_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS2_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS2; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS2) >> TAL_SMASK_IPS2_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS2; + tmp |= value << TAL_SMASK_IPS2_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS2_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS2; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS2_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS2; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS3_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS3; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS3) >> TAL_SMASK_IPS3_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS3; + tmp |= value << TAL_SMASK_IPS3_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS3_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS3; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS3_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS3; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS4_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS4; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS4) >> TAL_SMASK_IPS4_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS4; + tmp |= value << TAL_SMASK_IPS4_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS4_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS4; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS4_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS4; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS5_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS5; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS5) >> TAL_SMASK_IPS5_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS5; + tmp |= value << TAL_SMASK_IPS5_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS5_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS5; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS5_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS5; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS6_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS6; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS6) >> TAL_SMASK_IPS6_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS6; + tmp |= value << TAL_SMASK_IPS6_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS6_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS6; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS6_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS6; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS7_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS7; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS7) >> TAL_SMASK_IPS7_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS7; + tmp |= value << TAL_SMASK_IPS7_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS7_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS7; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS7_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS7; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS8_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS8; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS8_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS8) >> TAL_SMASK_IPS8_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS8_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS8; + tmp |= value << TAL_SMASK_IPS8_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS8_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS8; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS8_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS8; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS9_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS9; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS9_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS9) >> TAL_SMASK_IPS9_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS9_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS9; + tmp |= value << TAL_SMASK_IPS9_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS9_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS9; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS9_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS9; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS10_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS10; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS10_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS10) >> TAL_SMASK_IPS10_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS10_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS10; + tmp |= value << TAL_SMASK_IPS10_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS10_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS10; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS10_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS10; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS11_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS11; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS11_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS11) >> TAL_SMASK_IPS11_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS11_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS11; + tmp |= value << TAL_SMASK_IPS11_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS11_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS11; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS11_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS11; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS12_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS12; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS12_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS12) >> TAL_SMASK_IPS12_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS12_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS12; + tmp |= value << TAL_SMASK_IPS12_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS12_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS12; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS12_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS12; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS13_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS13; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS13_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS13) >> TAL_SMASK_IPS13_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS13_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS13; + tmp |= value << TAL_SMASK_IPS13_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS13_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS13; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS13_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS13; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS14_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS14; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS14_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS14) >> TAL_SMASK_IPS14_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS14_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS14; + tmp |= value << TAL_SMASK_IPS14_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS14_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS14; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS14_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS14; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS15_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS15; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS15_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS15) >> TAL_SMASK_IPS15_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS15_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS15; + tmp |= value << TAL_SMASK_IPS15_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS15_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS15; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS15_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS15; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS16_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS16; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS16_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS16) >> TAL_SMASK_IPS16_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS16_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS16; + tmp |= value << TAL_SMASK_IPS16_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS16_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS16; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS16_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS16; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS17_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS17; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS17_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS17) >> TAL_SMASK_IPS17_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS17_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS17; + tmp |= value << TAL_SMASK_IPS17_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS17_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS17; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS17_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS17; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS18_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS18; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS18_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS18) >> TAL_SMASK_IPS18_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS18_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS18; + tmp |= value << TAL_SMASK_IPS18_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS18_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS18; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS18_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS18; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS19_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS19; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS19_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS19) >> TAL_SMASK_IPS19_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS19_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS19; + tmp |= value << TAL_SMASK_IPS19_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS19_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS19; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS19_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS19; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS20_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS20; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS20_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS20) >> TAL_SMASK_IPS20_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS20_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS20; + tmp |= value << TAL_SMASK_IPS20_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS20_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS20; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS20_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS20; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS21_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS21; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS21_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS21) >> TAL_SMASK_IPS21_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS21_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS21; + tmp |= value << TAL_SMASK_IPS21_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS21_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS21; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS21_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS21; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS22_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS22; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS22_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS22) >> TAL_SMASK_IPS22_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS22_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS22; + tmp |= value << TAL_SMASK_IPS22_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS22_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS22; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS22_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS22; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS23_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS23; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS23_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS23) >> TAL_SMASK_IPS23_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS23_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS23; + tmp |= value << TAL_SMASK_IPS23_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS23_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS23; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS23_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS23; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS24_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS24; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS24_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS24) >> TAL_SMASK_IPS24_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS24_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS24; + tmp |= value << TAL_SMASK_IPS24_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS24_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS24; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS24_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS24; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS25_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS25; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS25_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS25) >> TAL_SMASK_IPS25_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS25_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS25; + tmp |= value << TAL_SMASK_IPS25_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS25_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS25; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS25_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS25; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS26_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS26; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS26_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS26) >> TAL_SMASK_IPS26_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS26_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS26; + tmp |= value << TAL_SMASK_IPS26_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS26_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS26; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS26_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS26; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS27_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS27; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS27_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS27) >> TAL_SMASK_IPS27_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS27_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS27; + tmp |= value << TAL_SMASK_IPS27_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS27_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS27; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS27_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS27; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS28_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS28; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS28_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS28) >> TAL_SMASK_IPS28_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS28_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS28; + tmp |= value << TAL_SMASK_IPS28_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS28_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS28; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS28_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS28; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS29_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS29; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS29_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS29) >> TAL_SMASK_IPS29_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS29_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS29; + tmp |= value << TAL_SMASK_IPS29_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS29_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS29; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS29_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS29; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS30_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS30; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS30_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS30) >> TAL_SMASK_IPS30_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS30_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS30; + tmp |= value << TAL_SMASK_IPS30_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS30_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS30; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS30_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS30; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_IPS31_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS31; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talsmasks_get_SMASK_IPS31_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS31) >> TAL_SMASK_IPS31_Pos; + return (bool)tmp; +} + +static inline void hri_talsmasks_write_SMASK_IPS31_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS31; + tmp |= value << TAL_SMASK_IPS31_Pos; + ((TalSmasks *)hw)->SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_IPS31_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS31; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_IPS31_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS31; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_set_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_smask_reg_t hri_talsmasks_get_SMASK_reg(const void *const hw, uint8_t index, + hri_tal_smask_reg_t mask) +{ + uint32_t tmp; + tmp = ((TalSmasks *)hw)->SMASK[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_talsmasks_write_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_clear_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talsmasks_toggle_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalSmasks *)hw)->SMASK[index].reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_smask_reg_t hri_talsmasks_read_SMASK_reg(const void *const hw, uint8_t index) +{ + return ((TalSmasks *)hw)->SMASK[index].reg; +} + +static inline void hri_tal_set_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS0) >> TAL_SMASK_IPS0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS0; + tmp |= value << TAL_SMASK_IPS0_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS1) >> TAL_SMASK_IPS1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS1; + tmp |= value << TAL_SMASK_IPS1_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS2; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS2) >> TAL_SMASK_IPS2_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS2; + tmp |= value << TAL_SMASK_IPS2_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS2; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS2; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS3; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS3) >> TAL_SMASK_IPS3_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS3; + tmp |= value << TAL_SMASK_IPS3_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS3; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS3; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS4; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS4) >> TAL_SMASK_IPS4_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS4; + tmp |= value << TAL_SMASK_IPS4_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS4; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS4; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS5; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS5) >> TAL_SMASK_IPS5_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS5; + tmp |= value << TAL_SMASK_IPS5_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS5; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS5; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS6; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS6) >> TAL_SMASK_IPS6_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS6; + tmp |= value << TAL_SMASK_IPS6_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS6; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS6; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS7; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS7) >> TAL_SMASK_IPS7_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS7; + tmp |= value << TAL_SMASK_IPS7_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS7; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS7; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS8; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS8) >> TAL_SMASK_IPS8_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS8; + tmp |= value << TAL_SMASK_IPS8_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS8; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS8; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS9; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS9) >> TAL_SMASK_IPS9_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS9; + tmp |= value << TAL_SMASK_IPS9_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS9; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS9; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS10; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS10) >> TAL_SMASK_IPS10_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS10; + tmp |= value << TAL_SMASK_IPS10_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS10; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS10; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS11; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS11) >> TAL_SMASK_IPS11_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS11; + tmp |= value << TAL_SMASK_IPS11_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS11; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS11; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS12; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS12) >> TAL_SMASK_IPS12_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS12; + tmp |= value << TAL_SMASK_IPS12_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS12; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS12; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS13; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS13) >> TAL_SMASK_IPS13_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS13; + tmp |= value << TAL_SMASK_IPS13_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS13; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS13; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS14; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS14) >> TAL_SMASK_IPS14_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS14; + tmp |= value << TAL_SMASK_IPS14_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS14; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS14; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS15; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS15) >> TAL_SMASK_IPS15_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS15; + tmp |= value << TAL_SMASK_IPS15_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS15; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS15; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS16; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS16) >> TAL_SMASK_IPS16_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS16; + tmp |= value << TAL_SMASK_IPS16_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS16; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS16; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS17; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS17) >> TAL_SMASK_IPS17_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS17; + tmp |= value << TAL_SMASK_IPS17_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS17; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS17; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS18; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS18) >> TAL_SMASK_IPS18_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS18; + tmp |= value << TAL_SMASK_IPS18_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS18; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS18; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS19; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS19) >> TAL_SMASK_IPS19_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS19; + tmp |= value << TAL_SMASK_IPS19_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS19; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS19; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS20; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS20) >> TAL_SMASK_IPS20_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS20; + tmp |= value << TAL_SMASK_IPS20_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS20; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS20; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS21; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS21) >> TAL_SMASK_IPS21_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS21; + tmp |= value << TAL_SMASK_IPS21_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS21; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS21; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS22; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS22) >> TAL_SMASK_IPS22_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS22; + tmp |= value << TAL_SMASK_IPS22_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS22; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS22; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS23; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS23) >> TAL_SMASK_IPS23_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS23; + tmp |= value << TAL_SMASK_IPS23_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS23; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS23; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS24; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS24) >> TAL_SMASK_IPS24_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS24; + tmp |= value << TAL_SMASK_IPS24_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS24; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS24; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS25; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS25) >> TAL_SMASK_IPS25_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS25; + tmp |= value << TAL_SMASK_IPS25_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS25; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS25; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS26; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS26) >> TAL_SMASK_IPS26_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS26; + tmp |= value << TAL_SMASK_IPS26_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS26; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS26; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS27; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS27) >> TAL_SMASK_IPS27_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS27; + tmp |= value << TAL_SMASK_IPS27_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS27; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS27; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS28; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS28) >> TAL_SMASK_IPS28_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS28; + tmp |= value << TAL_SMASK_IPS28_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS28; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS28; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS29; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS29) >> TAL_SMASK_IPS29_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS29; + tmp |= value << TAL_SMASK_IPS29_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS29; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS29; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS30; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS30) >> TAL_SMASK_IPS30_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS30; + tmp |= value << TAL_SMASK_IPS30_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS30; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS30; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS31; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp = (tmp & TAL_SMASK_IPS31) >> TAL_SMASK_IPS31_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= ~TAL_SMASK_IPS31; + tmp |= value << TAL_SMASK_IPS31_Pos; + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS31; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS31; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_tal_smask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_smask_reg_t hri_tal_get_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_tal_smask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_tal_smask_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_tal_smask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_tal_smask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_smask_reg_t hri_tal_read_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; +} + +static inline void hri_tal_set_INTEN_BRK_bit(const void *const hw) +{ + ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; +} + +static inline bool hri_tal_get_INTEN_BRK_bit(const void *const hw) +{ + return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_BRK) >> TAL_INTENSET_BRK_Pos; +} + +static inline void hri_tal_write_INTEN_BRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; + } else { + ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; + } +} + +static inline void hri_tal_clear_INTEN_BRK_bit(const void *const hw) +{ + ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; +} + +static inline void hri_tal_set_INTEN_IPS0_bit(const void *const hw) +{ + ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS0; +} + +static inline bool hri_tal_get_INTEN_IPS0_bit(const void *const hw) +{ + return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_IPS0) >> TAL_INTENSET_IPS0_Pos; +} + +static inline void hri_tal_write_INTEN_IPS0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS0; + } else { + ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS0; + } +} + +static inline void hri_tal_clear_INTEN_IPS0_bit(const void *const hw) +{ + ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS0; +} + +static inline void hri_tal_set_INTEN_IPS1_bit(const void *const hw) +{ + ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS1; +} + +static inline bool hri_tal_get_INTEN_IPS1_bit(const void *const hw) +{ + return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_IPS1) >> TAL_INTENSET_IPS1_Pos; +} + +static inline void hri_tal_write_INTEN_IPS1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS1; + } else { + ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS1; + } +} + +static inline void hri_tal_clear_INTEN_IPS1_bit(const void *const hw) +{ + ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS1; +} + +static inline void hri_tal_set_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask) +{ + ((Tal *)hw)->INTENSET.reg = mask; +} + +static inline hri_tal_intenset_reg_t hri_tal_get_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tal_intenset_reg_t hri_tal_read_INTEN_reg(const void *const hw) +{ + return ((Tal *)hw)->INTENSET.reg; +} + +static inline void hri_tal_write_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t data) +{ + ((Tal *)hw)->INTENSET.reg = data; + ((Tal *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tal_clear_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask) +{ + ((Tal *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_tal_set_SFLAG_IPS0_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS0; +} + +static inline bool hri_tal_get_SFLAG_IPS0_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS0) >> TAL_SFLAG_IPS0_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS0_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS0; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS0; + } +} + +static inline void hri_tal_clear_SFLAG_IPS0_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS0; +} + +static inline void hri_tal_set_SFLAG_IPS1_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS1; +} + +static inline bool hri_tal_get_SFLAG_IPS1_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS1) >> TAL_SFLAG_IPS1_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS1_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS1; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS1; + } +} + +static inline void hri_tal_clear_SFLAG_IPS1_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS1; +} + +static inline void hri_tal_set_SFLAG_IPS2_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS2; +} + +static inline bool hri_tal_get_SFLAG_IPS2_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS2) >> TAL_SFLAG_IPS2_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS2_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS2; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS2; + } +} + +static inline void hri_tal_clear_SFLAG_IPS2_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS2; +} + +static inline void hri_tal_set_SFLAG_IPS3_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS3; +} + +static inline bool hri_tal_get_SFLAG_IPS3_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS3) >> TAL_SFLAG_IPS3_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS3_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS3; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS3; + } +} + +static inline void hri_tal_clear_SFLAG_IPS3_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS3; +} + +static inline void hri_tal_set_SFLAG_IPS4_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS4; +} + +static inline bool hri_tal_get_SFLAG_IPS4_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS4) >> TAL_SFLAG_IPS4_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS4_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS4; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS4; + } +} + +static inline void hri_tal_clear_SFLAG_IPS4_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS4; +} + +static inline void hri_tal_set_SFLAG_IPS5_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS5; +} + +static inline bool hri_tal_get_SFLAG_IPS5_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS5) >> TAL_SFLAG_IPS5_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS5_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS5; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS5; + } +} + +static inline void hri_tal_clear_SFLAG_IPS5_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS5; +} + +static inline void hri_tal_set_SFLAG_IPS6_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS6; +} + +static inline bool hri_tal_get_SFLAG_IPS6_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS6) >> TAL_SFLAG_IPS6_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS6_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS6; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS6; + } +} + +static inline void hri_tal_clear_SFLAG_IPS6_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS6; +} + +static inline void hri_tal_set_SFLAG_IPS7_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS7; +} + +static inline bool hri_tal_get_SFLAG_IPS7_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS7) >> TAL_SFLAG_IPS7_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS7_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS7; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS7; + } +} + +static inline void hri_tal_clear_SFLAG_IPS7_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS7; +} + +static inline void hri_tal_set_SFLAG_IPS8_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS8; +} + +static inline bool hri_tal_get_SFLAG_IPS8_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS8) >> TAL_SFLAG_IPS8_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS8_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS8; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS8; + } +} + +static inline void hri_tal_clear_SFLAG_IPS8_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS8; +} + +static inline void hri_tal_set_SFLAG_IPS9_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS9; +} + +static inline bool hri_tal_get_SFLAG_IPS9_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS9) >> TAL_SFLAG_IPS9_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS9_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS9; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS9; + } +} + +static inline void hri_tal_clear_SFLAG_IPS9_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS9; +} + +static inline void hri_tal_set_SFLAG_IPS10_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS10; +} + +static inline bool hri_tal_get_SFLAG_IPS10_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS10) >> TAL_SFLAG_IPS10_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS10_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS10; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS10; + } +} + +static inline void hri_tal_clear_SFLAG_IPS10_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS10; +} + +static inline void hri_tal_set_SFLAG_IPS11_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS11; +} + +static inline bool hri_tal_get_SFLAG_IPS11_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS11) >> TAL_SFLAG_IPS11_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS11_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS11; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS11; + } +} + +static inline void hri_tal_clear_SFLAG_IPS11_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS11; +} + +static inline void hri_tal_set_SFLAG_IPS12_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS12; +} + +static inline bool hri_tal_get_SFLAG_IPS12_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS12) >> TAL_SFLAG_IPS12_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS12_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS12; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS12; + } +} + +static inline void hri_tal_clear_SFLAG_IPS12_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS12; +} + +static inline void hri_tal_set_SFLAG_IPS13_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS13; +} + +static inline bool hri_tal_get_SFLAG_IPS13_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS13) >> TAL_SFLAG_IPS13_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS13_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS13; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS13; + } +} + +static inline void hri_tal_clear_SFLAG_IPS13_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS13; +} + +static inline void hri_tal_set_SFLAG_IPS14_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS14; +} + +static inline bool hri_tal_get_SFLAG_IPS14_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS14) >> TAL_SFLAG_IPS14_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS14_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS14; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS14; + } +} + +static inline void hri_tal_clear_SFLAG_IPS14_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS14; +} + +static inline void hri_tal_set_SFLAG_IPS15_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS15; +} + +static inline bool hri_tal_get_SFLAG_IPS15_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS15) >> TAL_SFLAG_IPS15_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS15_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS15; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS15; + } +} + +static inline void hri_tal_clear_SFLAG_IPS15_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS15; +} + +static inline void hri_tal_set_SFLAG_IPS16_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS16; +} + +static inline bool hri_tal_get_SFLAG_IPS16_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS16) >> TAL_SFLAG_IPS16_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS16_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS16; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS16; + } +} + +static inline void hri_tal_clear_SFLAG_IPS16_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS16; +} + +static inline void hri_tal_set_SFLAG_IPS17_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS17; +} + +static inline bool hri_tal_get_SFLAG_IPS17_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS17) >> TAL_SFLAG_IPS17_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS17_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS17; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS17; + } +} + +static inline void hri_tal_clear_SFLAG_IPS17_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS17; +} + +static inline void hri_tal_set_SFLAG_IPS18_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS18; +} + +static inline bool hri_tal_get_SFLAG_IPS18_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS18) >> TAL_SFLAG_IPS18_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS18_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS18; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS18; + } +} + +static inline void hri_tal_clear_SFLAG_IPS18_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS18; +} + +static inline void hri_tal_set_SFLAG_IPS19_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS19; +} + +static inline bool hri_tal_get_SFLAG_IPS19_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS19) >> TAL_SFLAG_IPS19_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS19_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS19; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS19; + } +} + +static inline void hri_tal_clear_SFLAG_IPS19_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS19; +} + +static inline void hri_tal_set_SFLAG_IPS20_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS20; +} + +static inline bool hri_tal_get_SFLAG_IPS20_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS20) >> TAL_SFLAG_IPS20_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS20_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS20; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS20; + } +} + +static inline void hri_tal_clear_SFLAG_IPS20_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS20; +} + +static inline void hri_tal_set_SFLAG_IPS21_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS21; +} + +static inline bool hri_tal_get_SFLAG_IPS21_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS21) >> TAL_SFLAG_IPS21_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS21_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS21; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS21; + } +} + +static inline void hri_tal_clear_SFLAG_IPS21_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS21; +} + +static inline void hri_tal_set_SFLAG_IPS22_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS22; +} + +static inline bool hri_tal_get_SFLAG_IPS22_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS22) >> TAL_SFLAG_IPS22_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS22_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS22; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS22; + } +} + +static inline void hri_tal_clear_SFLAG_IPS22_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS22; +} + +static inline void hri_tal_set_SFLAG_IPS23_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS23; +} + +static inline bool hri_tal_get_SFLAG_IPS23_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS23) >> TAL_SFLAG_IPS23_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS23_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS23; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS23; + } +} + +static inline void hri_tal_clear_SFLAG_IPS23_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS23; +} + +static inline void hri_tal_set_SFLAG_IPS24_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS24; +} + +static inline bool hri_tal_get_SFLAG_IPS24_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS24) >> TAL_SFLAG_IPS24_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS24_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS24; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS24; + } +} + +static inline void hri_tal_clear_SFLAG_IPS24_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS24; +} + +static inline void hri_tal_set_SFLAG_IPS25_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS25; +} + +static inline bool hri_tal_get_SFLAG_IPS25_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS25) >> TAL_SFLAG_IPS25_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS25_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS25; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS25; + } +} + +static inline void hri_tal_clear_SFLAG_IPS25_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS25; +} + +static inline void hri_tal_set_SFLAG_IPS26_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS26; +} + +static inline bool hri_tal_get_SFLAG_IPS26_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS26) >> TAL_SFLAG_IPS26_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS26_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS26; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS26; + } +} + +static inline void hri_tal_clear_SFLAG_IPS26_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS26; +} + +static inline void hri_tal_set_SFLAG_IPS27_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS27; +} + +static inline bool hri_tal_get_SFLAG_IPS27_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS27) >> TAL_SFLAG_IPS27_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS27_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS27; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS27; + } +} + +static inline void hri_tal_clear_SFLAG_IPS27_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS27; +} + +static inline void hri_tal_set_SFLAG_IPS28_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS28; +} + +static inline bool hri_tal_get_SFLAG_IPS28_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS28) >> TAL_SFLAG_IPS28_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS28_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS28; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS28; + } +} + +static inline void hri_tal_clear_SFLAG_IPS28_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS28; +} + +static inline void hri_tal_set_SFLAG_IPS29_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS29; +} + +static inline bool hri_tal_get_SFLAG_IPS29_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS29) >> TAL_SFLAG_IPS29_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS29_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS29; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS29; + } +} + +static inline void hri_tal_clear_SFLAG_IPS29_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS29; +} + +static inline void hri_tal_set_SFLAG_IPS30_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS30; +} + +static inline bool hri_tal_get_SFLAG_IPS30_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS30) >> TAL_SFLAG_IPS30_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS30_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS30; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS30; + } +} + +static inline void hri_tal_clear_SFLAG_IPS30_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS30; +} + +static inline void hri_tal_set_SFLAG_IPS31_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS31; +} + +static inline bool hri_tal_get_SFLAG_IPS31_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS31) >> TAL_SFLAG_IPS31_Pos; +} + +static inline void hri_tal_write_SFLAG_IPS31_bit(const void *const hw, uint8_t index, bool value) +{ + if (value == 0x0) { + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS31; + } else { + ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS31; + } +} + +static inline void hri_tal_clear_SFLAG_IPS31_bit(const void *const hw, uint8_t index) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS31; +} + +static inline void hri_tal_set_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t mask) +{ + ((Tal *)hw)->SFLAGSET[index].reg = mask; +} + +static inline hri_tal_sflag_reg_t hri_tal_get_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->SFLAG[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_tal_sflag_reg_t hri_tal_read_SFLAG_reg(const void *const hw, uint8_t index) +{ + return ((Tal *)hw)->SFLAG[index].reg; +} + +static inline void hri_tal_write_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t data) +{ + ((Tal *)hw)->SFLAGSET[index].reg = data; + ((Tal *)hw)->SFLAGCLR[index].reg = ~data; +} + +static inline void hri_tal_clear_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t mask) +{ + ((Tal *)hw)->SFLAGCLR[index].reg = mask; +} + +static inline bool hri_tal_get_INTFLAG_BRK_bit(const void *const hw) +{ + return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_BRK) >> TAL_INTFLAG_BRK_Pos; +} + +static inline void hri_tal_clear_INTFLAG_BRK_bit(const void *const hw) +{ + ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_BRK; +} + +static inline bool hri_tal_get_INTFLAG_IPS0_bit(const void *const hw) +{ + return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS0) >> TAL_INTFLAG_IPS0_Pos; +} + +static inline void hri_tal_clear_INTFLAG_IPS0_bit(const void *const hw) +{ + ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS0; +} + +static inline bool hri_tal_get_INTFLAG_IPS1_bit(const void *const hw) +{ + return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS1) >> TAL_INTFLAG_IPS1_Pos; +} + +static inline void hri_tal_clear_INTFLAG_IPS1_bit(const void *const hw) +{ + ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS1; +} + +static inline bool hri_tal_get_interrupt_BRK_bit(const void *const hw) +{ + return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_BRK) >> TAL_INTFLAG_BRK_Pos; +} + +static inline void hri_tal_clear_interrupt_BRK_bit(const void *const hw) +{ + ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_BRK; +} + +static inline bool hri_tal_get_interrupt_IPS0_bit(const void *const hw) +{ + return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS0) >> TAL_INTFLAG_IPS0_Pos; +} + +static inline void hri_tal_clear_interrupt_IPS0_bit(const void *const hw) +{ + ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS0; +} + +static inline bool hri_tal_get_interrupt_IPS1_bit(const void *const hw) +{ + return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS1) >> TAL_INTFLAG_IPS1_Pos; +} + +static inline void hri_tal_clear_interrupt_IPS1_bit(const void *const hw) +{ + ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS1; +} + +static inline hri_tal_intflag_reg_t hri_tal_get_INTFLAG_reg(const void *const hw, hri_tal_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tal_intflag_reg_t hri_tal_read_INTFLAG_reg(const void *const hw) +{ + return ((Tal *)hw)->INTFLAG.reg; +} + +static inline void hri_tal_clear_INTFLAG_reg(const void *const hw, hri_tal_intflag_reg_t mask) +{ + ((Tal *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tal_write_HALT_reg(const void *const hw, hri_tal_halt_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->HALT.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_write_RESTART_reg(const void *const hw, hri_tal_restart_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->RESTART.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTRLA_SWRST_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_SWRST; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->CTRLA.reg; + tmp = (tmp & TAL_CTRLA_SWRST) >> TAL_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tal_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->CTRLA.reg; + tmp = (tmp & TAL_CTRLA_ENABLE) >> TAL_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->CTRLA.reg; + tmp &= ~TAL_CTRLA_ENABLE; + tmp |= value << TAL_CTRLA_ENABLE_Pos; + ((Tal *)hw)->CTRLA.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg &= ~TAL_CTRLA_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg ^= TAL_CTRLA_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctrla_reg_t hri_tal_get_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->CTRLA.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctrla_reg_t hri_tal_read_CTRLA_reg(const void *const hw) +{ + return ((Tal *)hw)->CTRLA.reg; +} + +static inline void hri_tal_set_EXTCTRL_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg |= TAL_EXTCTRL_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EXTCTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->EXTCTRL.reg; + tmp = (tmp & TAL_EXTCTRL_ENABLE) >> TAL_EXTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EXTCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EXTCTRL.reg; + tmp &= ~TAL_EXTCTRL_ENABLE; + tmp |= value << TAL_EXTCTRL_ENABLE_Pos; + ((Tal *)hw)->EXTCTRL.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EXTCTRL_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg &= ~TAL_EXTCTRL_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EXTCTRL_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg ^= TAL_EXTCTRL_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EXTCTRL_INV_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg |= TAL_EXTCTRL_INV; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EXTCTRL_INV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->EXTCTRL.reg; + tmp = (tmp & TAL_EXTCTRL_INV) >> TAL_EXTCTRL_INV_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EXTCTRL_INV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EXTCTRL.reg; + tmp &= ~TAL_EXTCTRL_INV; + tmp |= value << TAL_EXTCTRL_INV_Pos; + ((Tal *)hw)->EXTCTRL.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EXTCTRL_INV_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg &= ~TAL_EXTCTRL_INV; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EXTCTRL_INV_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg ^= TAL_EXTCTRL_INV; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_extctrl_reg_t hri_tal_get_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->EXTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EXTCTRL.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_extctrl_reg_t hri_tal_read_EXTCTRL_reg(const void *const hw) +{ + return ((Tal *)hw)->EXTCTRL.reg; +} + +static inline void hri_tal_set_EVCTRL_BRKEI_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_BRKEI; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCTRL_BRKEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->EVCTRL.reg; + tmp = (tmp & TAL_EVCTRL_BRKEI) >> TAL_EVCTRL_BRKEI_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCTRL_BRKEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCTRL.reg; + tmp &= ~TAL_EVCTRL_BRKEI; + tmp |= value << TAL_EVCTRL_BRKEI_Pos; + ((Tal *)hw)->EVCTRL.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCTRL_BRKEI_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_BRKEI; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCTRL_BRKEI_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_BRKEI; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCTRL_BRKEO_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_BRKEO; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCTRL_BRKEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->EVCTRL.reg; + tmp = (tmp & TAL_EVCTRL_BRKEO) >> TAL_EVCTRL_BRKEO_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCTRL_BRKEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCTRL.reg; + tmp &= ~TAL_EVCTRL_BRKEO; + tmp |= value << TAL_EVCTRL_BRKEO_Pos; + ((Tal *)hw)->EVCTRL.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCTRL_BRKEO_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_BRKEO; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCTRL_BRKEO_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_BRKEO; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCTRL_IRQMONEO0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_IRQMONEO0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCTRL_IRQMONEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->EVCTRL.reg; + tmp = (tmp & TAL_EVCTRL_IRQMONEO0) >> TAL_EVCTRL_IRQMONEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCTRL_IRQMONEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCTRL.reg; + tmp &= ~TAL_EVCTRL_IRQMONEO0; + tmp |= value << TAL_EVCTRL_IRQMONEO0_Pos; + ((Tal *)hw)->EVCTRL.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCTRL_IRQMONEO0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_IRQMONEO0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCTRL_IRQMONEO0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_IRQMONEO0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_evctrl_reg_t hri_tal_get_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCTRL.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_evctrl_reg_t hri_tal_read_EVCTRL_reg(const void *const hw) +{ + return ((Tal *)hw)->EVCTRL.reg; +} + +static inline void hri_tal_set_GLOBMASK_CPU0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_GLOBMASK_CPU0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp = (tmp & TAL_GLOBMASK_CPU0) >> TAL_GLOBMASK_CPU0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_GLOBMASK_CPU0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp &= ~TAL_GLOBMASK_CPU0; + tmp |= value << TAL_GLOBMASK_CPU0_Pos; + ((Tal *)hw)->GLOBMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_GLOBMASK_CPU0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_GLOBMASK_CPU0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_GLOBMASK_CPU1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_GLOBMASK_CPU1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp = (tmp & TAL_GLOBMASK_CPU1) >> TAL_GLOBMASK_CPU1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_GLOBMASK_CPU1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp &= ~TAL_GLOBMASK_CPU1; + tmp |= value << TAL_GLOBMASK_CPU1_Pos; + ((Tal *)hw)->GLOBMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_GLOBMASK_CPU1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_GLOBMASK_CPU1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_GLOBMASK_EVBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_GLOBMASK_EVBRK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp = (tmp & TAL_GLOBMASK_EVBRK) >> TAL_GLOBMASK_EVBRK_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_GLOBMASK_EVBRK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp &= ~TAL_GLOBMASK_EVBRK; + tmp |= value << TAL_GLOBMASK_EVBRK_Pos; + ((Tal *)hw)->GLOBMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_GLOBMASK_EVBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_GLOBMASK_EVBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_GLOBMASK_EXTBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_GLOBMASK_EXTBRK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp = (tmp & TAL_GLOBMASK_EXTBRK) >> TAL_GLOBMASK_EXTBRK_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_GLOBMASK_EXTBRK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp &= ~TAL_GLOBMASK_EXTBRK; + tmp |= value << TAL_GLOBMASK_EXTBRK_Pos; + ((Tal *)hw)->GLOBMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_GLOBMASK_EXTBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_GLOBMASK_EXTBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_globmask_reg_t hri_tal_get_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->GLOBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->GLOBMASK.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_globmask_reg_t hri_tal_read_GLOBMASK_reg(const void *const hw) +{ + return ((Tal *)hw)->GLOBMASK.reg; +} + +static inline void hri_tal_set_DMACPUSEL0_CH0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH0_Msk) >> TAL_DMACPUSEL0_CH0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH0_Msk; + tmp |= value << TAL_DMACPUSEL0_CH0_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH1_Msk) >> TAL_DMACPUSEL0_CH1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH1_Msk; + tmp |= value << TAL_DMACPUSEL0_CH1_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH2_Msk) >> TAL_DMACPUSEL0_CH2_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH2_Msk; + tmp |= value << TAL_DMACPUSEL0_CH2_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH3_Msk) >> TAL_DMACPUSEL0_CH3_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH3_Msk; + tmp |= value << TAL_DMACPUSEL0_CH3_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH4_Msk) >> TAL_DMACPUSEL0_CH4_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH4_Msk; + tmp |= value << TAL_DMACPUSEL0_CH4_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH5_Msk) >> TAL_DMACPUSEL0_CH5_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH5_Msk; + tmp |= value << TAL_DMACPUSEL0_CH5_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH6_Msk) >> TAL_DMACPUSEL0_CH6_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH6_Msk; + tmp |= value << TAL_DMACPUSEL0_CH6_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH7_Msk) >> TAL_DMACPUSEL0_CH7_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH7_Msk; + tmp |= value << TAL_DMACPUSEL0_CH7_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH8_Msk) >> TAL_DMACPUSEL0_CH8_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH8_Msk; + tmp |= value << TAL_DMACPUSEL0_CH8_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH9_Msk) >> TAL_DMACPUSEL0_CH9_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH9_Msk; + tmp |= value << TAL_DMACPUSEL0_CH9_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH10_Msk) >> TAL_DMACPUSEL0_CH10_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH10_Msk; + tmp |= value << TAL_DMACPUSEL0_CH10_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH11_Msk) >> TAL_DMACPUSEL0_CH11_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH11_Msk; + tmp |= value << TAL_DMACPUSEL0_CH11_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH12_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH12_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH12_Msk) >> TAL_DMACPUSEL0_CH12_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH12_Msk; + tmp |= value << TAL_DMACPUSEL0_CH12_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH12_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH12_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH12_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH12_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH13_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH13_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH13_Msk) >> TAL_DMACPUSEL0_CH13_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH13_Msk; + tmp |= value << TAL_DMACPUSEL0_CH13_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH13_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH13_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH13_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH13_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH14_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH14_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH14_Msk) >> TAL_DMACPUSEL0_CH14_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH14_Msk; + tmp |= value << TAL_DMACPUSEL0_CH14_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH14_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH14_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH14_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH14_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_CH15_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH15_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL0_CH15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp = (tmp & TAL_DMACPUSEL0_CH15_Msk) >> TAL_DMACPUSEL0_CH15_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_CH15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= ~TAL_DMACPUSEL0_CH15_Msk; + tmp |= value << TAL_DMACPUSEL0_CH15_Pos; + ((Tal *)hw)->DMACPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_CH15_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH15_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_CH15_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH15_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_dmacpusel0_reg_t hri_tal_get_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL0.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_dmacpusel0_reg_t hri_tal_read_DMACPUSEL0_reg(const void *const hw) +{ + return ((Tal *)hw)->DMACPUSEL0.reg; +} + +static inline void hri_tal_set_DMACPUSEL1_CH16_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH16_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH16_Msk) >> TAL_DMACPUSEL1_CH16_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH16_Msk; + tmp |= value << TAL_DMACPUSEL1_CH16_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH16_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH16_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH16_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH16_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH17_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH17_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH17_Msk) >> TAL_DMACPUSEL1_CH17_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH17_Msk; + tmp |= value << TAL_DMACPUSEL1_CH17_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH17_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH17_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH17_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH17_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH18_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH18_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH18_Msk) >> TAL_DMACPUSEL1_CH18_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH18_Msk; + tmp |= value << TAL_DMACPUSEL1_CH18_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH18_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH18_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH18_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH18_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH19_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH19_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH19_Msk) >> TAL_DMACPUSEL1_CH19_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH19_Msk; + tmp |= value << TAL_DMACPUSEL1_CH19_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH19_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH19_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH19_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH19_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH20_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH20_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH20_Msk) >> TAL_DMACPUSEL1_CH20_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH20_Msk; + tmp |= value << TAL_DMACPUSEL1_CH20_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH20_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH20_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH20_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH20_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH21_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH21_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH21_Msk) >> TAL_DMACPUSEL1_CH21_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH21_Msk; + tmp |= value << TAL_DMACPUSEL1_CH21_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH21_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH21_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH21_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH21_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH22_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH22_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH22_Msk) >> TAL_DMACPUSEL1_CH22_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH22_Msk; + tmp |= value << TAL_DMACPUSEL1_CH22_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH22_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH22_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH22_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH22_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH23_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH23_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH23_Msk) >> TAL_DMACPUSEL1_CH23_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH23_Msk; + tmp |= value << TAL_DMACPUSEL1_CH23_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH23_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH23_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH23_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH23_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH24_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH24_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH24_Msk) >> TAL_DMACPUSEL1_CH24_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH24_Msk; + tmp |= value << TAL_DMACPUSEL1_CH24_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH24_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH24_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH24_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH24_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH25_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH25_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH25_Msk) >> TAL_DMACPUSEL1_CH25_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH25_Msk; + tmp |= value << TAL_DMACPUSEL1_CH25_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH25_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH25_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH25_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH25_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH26_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH26_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH26_Msk) >> TAL_DMACPUSEL1_CH26_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH26_Msk; + tmp |= value << TAL_DMACPUSEL1_CH26_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH26_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH26_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH26_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH26_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH27_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH27_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH27_Msk) >> TAL_DMACPUSEL1_CH27_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH27_Msk; + tmp |= value << TAL_DMACPUSEL1_CH27_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH27_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH27_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH27_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH27_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH28_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH28_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH28_Msk) >> TAL_DMACPUSEL1_CH28_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH28_Msk; + tmp |= value << TAL_DMACPUSEL1_CH28_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH28_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH28_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH28_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH28_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH29_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH29_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH29_Msk) >> TAL_DMACPUSEL1_CH29_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH29_Msk; + tmp |= value << TAL_DMACPUSEL1_CH29_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH29_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH29_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH29_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH29_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH30_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH30_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH30_Msk) >> TAL_DMACPUSEL1_CH30_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH30_Msk; + tmp |= value << TAL_DMACPUSEL1_CH30_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH30_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH30_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH30_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH30_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_CH31_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH31_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_DMACPUSEL1_CH31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp = (tmp & TAL_DMACPUSEL1_CH31_Msk) >> TAL_DMACPUSEL1_CH31_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_CH31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= ~TAL_DMACPUSEL1_CH31_Msk; + tmp |= value << TAL_DMACPUSEL1_CH31_Pos; + ((Tal *)hw)->DMACPUSEL1.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_CH31_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH31_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_CH31_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH31_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_dmacpusel1_reg_t hri_tal_get_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->DMACPUSEL1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->DMACPUSEL1.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_dmacpusel1_reg_t hri_tal_read_DMACPUSEL1_reg(const void *const hw) +{ + return ((Tal *)hw)->DMACPUSEL1.reg; +} + +static inline void hri_tal_set_EVCPUSEL0_CH0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH0_Msk) >> TAL_EVCPUSEL0_CH0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH0_Msk; + tmp |= value << TAL_EVCPUSEL0_CH0_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH1_Msk) >> TAL_EVCPUSEL0_CH1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH1_Msk; + tmp |= value << TAL_EVCPUSEL0_CH1_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH2_Msk) >> TAL_EVCPUSEL0_CH2_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH2_Msk; + tmp |= value << TAL_EVCPUSEL0_CH2_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH3_Msk) >> TAL_EVCPUSEL0_CH3_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH3_Msk; + tmp |= value << TAL_EVCPUSEL0_CH3_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH4_Msk) >> TAL_EVCPUSEL0_CH4_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH4_Msk; + tmp |= value << TAL_EVCPUSEL0_CH4_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH5_Msk) >> TAL_EVCPUSEL0_CH5_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH5_Msk; + tmp |= value << TAL_EVCPUSEL0_CH5_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH6_Msk) >> TAL_EVCPUSEL0_CH6_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH6_Msk; + tmp |= value << TAL_EVCPUSEL0_CH6_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH7_Msk) >> TAL_EVCPUSEL0_CH7_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH7_Msk; + tmp |= value << TAL_EVCPUSEL0_CH7_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH8_Msk) >> TAL_EVCPUSEL0_CH8_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH8_Msk; + tmp |= value << TAL_EVCPUSEL0_CH8_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH9_Msk) >> TAL_EVCPUSEL0_CH9_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH9_Msk; + tmp |= value << TAL_EVCPUSEL0_CH9_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH10_Msk) >> TAL_EVCPUSEL0_CH10_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH10_Msk; + tmp |= value << TAL_EVCPUSEL0_CH10_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_CH11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EVCPUSEL0_CH11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp = (tmp & TAL_EVCPUSEL0_CH11_Msk) >> TAL_EVCPUSEL0_CH11_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_CH11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= ~TAL_EVCPUSEL0_CH11_Msk; + tmp |= value << TAL_EVCPUSEL0_CH11_Pos; + ((Tal *)hw)->EVCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_CH11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_CH11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_evcpusel0_reg_t hri_tal_get_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EVCPUSEL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EVCPUSEL0.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_evcpusel0_reg_t hri_tal_read_EVCPUSEL0_reg(const void *const hw) +{ + return ((Tal *)hw)->EVCPUSEL0.reg; +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT0_Msk) >> TAL_EICCPUSEL0_EXTINT0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT0_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT0_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT1_Msk) >> TAL_EICCPUSEL0_EXTINT1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT1_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT1_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT2_Msk) >> TAL_EICCPUSEL0_EXTINT2_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT2_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT2_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT3_Msk) >> TAL_EICCPUSEL0_EXTINT3_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT3_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT3_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT4_Msk) >> TAL_EICCPUSEL0_EXTINT4_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT4_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT4_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT5_Msk) >> TAL_EICCPUSEL0_EXTINT5_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT5_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT5_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT6_Msk) >> TAL_EICCPUSEL0_EXTINT6_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT6_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT6_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT7_Msk) >> TAL_EICCPUSEL0_EXTINT7_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT7_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT7_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT8_Msk) >> TAL_EICCPUSEL0_EXTINT8_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT8_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT8_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT8_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT8_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT9_Msk) >> TAL_EICCPUSEL0_EXTINT9_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT9_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT9_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT9_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT9_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT10_Msk) >> TAL_EICCPUSEL0_EXTINT10_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT10_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT10_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT10_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT10_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT11_Msk) >> TAL_EICCPUSEL0_EXTINT11_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT11_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT11_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT11_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT11_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT12_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT12_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT12_Msk) >> TAL_EICCPUSEL0_EXTINT12_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT12_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT12_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT12_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT12_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT12_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT12_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT13_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT13_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT13_Msk) >> TAL_EICCPUSEL0_EXTINT13_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT13_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT13_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT13_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT13_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT13_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT13_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT14_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT14_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT14_Msk) >> TAL_EICCPUSEL0_EXTINT14_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT14_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT14_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT14_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT14_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT14_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT14_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_EXTINT15_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT15_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_EICCPUSEL0_EXTINT15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp = (tmp & TAL_EICCPUSEL0_EXTINT15_Msk) >> TAL_EICCPUSEL0_EXTINT15_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_EXTINT15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= ~TAL_EICCPUSEL0_EXTINT15_Msk; + tmp |= value << TAL_EICCPUSEL0_EXTINT15_Pos; + ((Tal *)hw)->EICCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_EXTINT15_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT15_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_EXTINT15_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT15_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_eiccpusel0_reg_t hri_tal_get_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->EICCPUSEL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->EICCPUSEL0.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_eiccpusel0_reg_t hri_tal_read_EICCPUSEL0_reg(const void *const hw) +{ + return ((Tal *)hw)->EICCPUSEL0.reg; +} + +static inline void hri_tal_set_INTCPUSEL0_PAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_PAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_PAC_Msk) >> TAL_INTCPUSEL0_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_PAC_Msk; + tmp |= value << TAL_INTCPUSEL0_PAC_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_PAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_PAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_PAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_PAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_PM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_PM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_PM_Msk) >> TAL_INTCPUSEL0_PM_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_PM_Msk; + tmp |= value << TAL_INTCPUSEL0_PM_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_PM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_PM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_PM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_PM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_MCLK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_MCLK_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_MCLK_Msk) >> TAL_INTCPUSEL0_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_MCLK_Msk; + tmp |= value << TAL_INTCPUSEL0_MCLK_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_MCLK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_MCLK_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_MCLK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_MCLK_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_OSCCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_OSCCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_OSCCTRL_Msk) >> TAL_INTCPUSEL0_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_OSCCTRL_Msk; + tmp |= value << TAL_INTCPUSEL0_OSCCTRL_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_OSCCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_OSCCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_OSCCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_OSCCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_OSC32KCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_OSC32KCTRL_Msk) >> TAL_INTCPUSEL0_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_OSC32KCTRL_Msk; + tmp |= value << TAL_INTCPUSEL0_OSC32KCTRL_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_OSC32KCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_OSC32KCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_SUPC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SUPC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_SUPC_Msk) >> TAL_INTCPUSEL0_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_SUPC_Msk; + tmp |= value << TAL_INTCPUSEL0_SUPC_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_SUPC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SUPC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_SUPC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SUPC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_WDT_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_WDT_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_WDT_Msk) >> TAL_INTCPUSEL0_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_WDT_Msk; + tmp |= value << TAL_INTCPUSEL0_WDT_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_WDT_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_WDT_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_WDT_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_WDT_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_RTC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_RTC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_RTC_Msk) >> TAL_INTCPUSEL0_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_RTC_Msk; + tmp |= value << TAL_INTCPUSEL0_RTC_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_RTC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_RTC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_RTC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_RTC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_EIC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_EIC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_EIC_Msk) >> TAL_INTCPUSEL0_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_EIC_Msk; + tmp |= value << TAL_INTCPUSEL0_EIC_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_EIC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_EIC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_EIC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_EIC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_FREQM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_FREQM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_FREQM_Msk) >> TAL_INTCPUSEL0_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_FREQM_Msk; + tmp |= value << TAL_INTCPUSEL0_FREQM_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_FREQM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_FREQM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_FREQM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_FREQM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_SERCOM0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_SERCOM0_Msk) >> TAL_INTCPUSEL0_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_SERCOM0_Msk; + tmp |= value << TAL_INTCPUSEL0_SERCOM0_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_SERCOM0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_SERCOM0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_SERCOM1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_SERCOM1_Msk) >> TAL_INTCPUSEL0_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_SERCOM1_Msk; + tmp |= value << TAL_INTCPUSEL0_SERCOM1_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_SERCOM1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_SERCOM1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_TC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_TC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_TC0_Msk) >> TAL_INTCPUSEL0_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_TC0_Msk; + tmp |= value << TAL_INTCPUSEL0_TC0_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_TC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_TC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_TC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_TC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_TC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_TC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL0_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp = (tmp & TAL_INTCPUSEL0_TC1_Msk) >> TAL_INTCPUSEL0_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= ~TAL_INTCPUSEL0_TC1_Msk; + tmp |= value << TAL_INTCPUSEL0_TC1_Pos; + ((Tal *)hw)->INTCPUSEL0.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_TC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_TC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_TC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_TC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel0_reg_t hri_tal_get_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL0.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel0_reg_t hri_tal_read_INTCPUSEL0_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL0.reg; +} + +static inline void hri_tal_set_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL1.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel1_reg_t hri_tal_get_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL1.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL1.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL1.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel1_reg_t hri_tal_read_INTCPUSEL1_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL1.reg; +} + +static inline void hri_tal_set_INTCPUSEL2_USB_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_USB_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_USB_Msk) >> TAL_INTCPUSEL2_USB_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_USB_Msk; + tmp |= value << TAL_INTCPUSEL2_USB_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_USB_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_USB_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_USB_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_USB_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_NVMCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_NVMCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_NVMCTRL_Msk) >> TAL_INTCPUSEL2_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_NVMCTRL_Msk; + tmp |= value << TAL_INTCPUSEL2_NVMCTRL_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_NVMCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_NVMCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_NVMCTRL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_NVMCTRL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_DMAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_DMAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_DMAC_Msk) >> TAL_INTCPUSEL2_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_DMAC_Msk; + tmp |= value << TAL_INTCPUSEL2_DMAC_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_DMAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_DMAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_DMAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_DMAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_EVSYS_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_EVSYS_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_EVSYS_Msk) >> TAL_INTCPUSEL2_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_EVSYS_Msk; + tmp |= value << TAL_INTCPUSEL2_EVSYS_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_EVSYS_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_EVSYS_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_EVSYS_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_EVSYS_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_PICOP_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_PICOP_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_PICOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_PICOP_Msk) >> TAL_INTCPUSEL2_PICOP_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_PICOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_PICOP_Msk; + tmp |= value << TAL_INTCPUSEL2_PICOP_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_PICOP_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_PICOP_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_PICOP_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_PICOP_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_SERCOM2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_SERCOM2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_SERCOM2_Msk) >> TAL_INTCPUSEL2_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_SERCOM2_Msk; + tmp |= value << TAL_INTCPUSEL2_SERCOM2_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_SERCOM2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_SERCOM2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_SERCOM2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_SERCOM2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_SERCOM3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_SERCOM3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_SERCOM3_Msk) >> TAL_INTCPUSEL2_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_SERCOM3_Msk; + tmp |= value << TAL_INTCPUSEL2_SERCOM3_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_SERCOM3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_SERCOM3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_SERCOM3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_SERCOM3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_TCC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TCC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_TCC0_Msk) >> TAL_INTCPUSEL2_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_TCC0_Msk; + tmp |= value << TAL_INTCPUSEL2_TCC0_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_TCC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TCC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_TCC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TCC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_TCC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TCC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_TCC1_Msk) >> TAL_INTCPUSEL2_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_TCC1_Msk; + tmp |= value << TAL_INTCPUSEL2_TCC1_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_TCC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TCC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_TCC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TCC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_TC2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TC2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_TC2_Msk) >> TAL_INTCPUSEL2_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_TC2_Msk; + tmp |= value << TAL_INTCPUSEL2_TC2_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_TC2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TC2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_TC2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TC2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_TC3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TC3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_TC3_Msk) >> TAL_INTCPUSEL2_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_TC3_Msk; + tmp |= value << TAL_INTCPUSEL2_TC3_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_TC3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TC3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_TC3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TC3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_TAL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TAL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL2_TAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp = (tmp & TAL_INTCPUSEL2_TAL_Msk) >> TAL_INTCPUSEL2_TAL_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_TAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= ~TAL_INTCPUSEL2_TAL_Msk; + tmp |= value << TAL_INTCPUSEL2_TAL_Pos; + ((Tal *)hw)->INTCPUSEL2.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_TAL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TAL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_TAL_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TAL_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel2_reg_t hri_tal_get_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL2.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel2_reg_t hri_tal_read_INTCPUSEL2_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL2.reg; +} + +static inline void hri_tal_set_INTCPUSEL3_RAMECC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL3.reg |= TAL_INTCPUSEL3_RAMECC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL3_RAMECC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL3.reg; + tmp = (tmp & TAL_INTCPUSEL3_RAMECC_Msk) >> TAL_INTCPUSEL3_RAMECC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL3_RAMECC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL3.reg; + tmp &= ~TAL_INTCPUSEL3_RAMECC_Msk; + tmp |= value << TAL_INTCPUSEL3_RAMECC_Pos; + ((Tal *)hw)->INTCPUSEL3.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL3_RAMECC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL3.reg &= ~TAL_INTCPUSEL3_RAMECC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL3_RAMECC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL3.reg ^= TAL_INTCPUSEL3_RAMECC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL3.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel3_reg_t hri_tal_get_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL3.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL3.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL3.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL3.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel3_reg_t hri_tal_read_INTCPUSEL3_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL3.reg; +} + +static inline void hri_tal_set_INTCPUSEL4_CAN0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_CAN0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_CAN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_CAN0_Msk) >> TAL_INTCPUSEL4_CAN0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_CAN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_CAN0_Msk; + tmp |= value << TAL_INTCPUSEL4_CAN0_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_CAN0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_CAN0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_CAN0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_CAN0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_CAN1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_CAN1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_CAN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_CAN1_Msk) >> TAL_INTCPUSEL4_CAN1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_CAN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_CAN1_Msk; + tmp |= value << TAL_INTCPUSEL4_CAN1_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_CAN1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_CAN1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_CAN1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_CAN1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_GMAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_GMAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_GMAC_Msk) >> TAL_INTCPUSEL4_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_GMAC_Msk; + tmp |= value << TAL_INTCPUSEL4_GMAC_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_GMAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_GMAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_GMAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_GMAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_TCC2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TCC2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_TCC2_Msk) >> TAL_INTCPUSEL4_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_TCC2_Msk; + tmp |= value << TAL_INTCPUSEL4_TCC2_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_TCC2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TCC2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_TCC2_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TCC2_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_TCC3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TCC3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_TCC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_TCC3_Msk) >> TAL_INTCPUSEL4_TCC3_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_TCC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_TCC3_Msk; + tmp |= value << TAL_INTCPUSEL4_TCC3_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_TCC3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TCC3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_TCC3_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TCC3_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_TC4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TC4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_TC4_Msk) >> TAL_INTCPUSEL4_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_TC4_Msk; + tmp |= value << TAL_INTCPUSEL4_TC4_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_TC4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TC4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_TC4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TC4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_TC5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TC5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_TC5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_TC5_Msk) >> TAL_INTCPUSEL4_TC5_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_TC5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_TC5_Msk; + tmp |= value << TAL_INTCPUSEL4_TC5_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_TC5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TC5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_TC5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TC5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_PDEC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_PDEC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_PDEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_PDEC_Msk) >> TAL_INTCPUSEL4_PDEC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_PDEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_PDEC_Msk; + tmp |= value << TAL_INTCPUSEL4_PDEC_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_PDEC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_PDEC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_PDEC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_PDEC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_AC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_AC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_AC_Msk) >> TAL_INTCPUSEL4_AC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_AC_Msk; + tmp |= value << TAL_INTCPUSEL4_AC_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_AC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_AC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_AC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_AC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_AES_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_AES_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_AES_Msk) >> TAL_INTCPUSEL4_AES_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_AES_Msk; + tmp |= value << TAL_INTCPUSEL4_AES_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_AES_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_AES_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_AES_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_AES_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_TRNG_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TRNG_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_TRNG_Msk) >> TAL_INTCPUSEL4_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_TRNG_Msk; + tmp |= value << TAL_INTCPUSEL4_TRNG_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_TRNG_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TRNG_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_TRNG_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TRNG_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_ICM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_ICM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_ICM_Msk) >> TAL_INTCPUSEL4_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_ICM_Msk; + tmp |= value << TAL_INTCPUSEL4_ICM_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_ICM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_ICM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_ICM_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_ICM_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_PUKCC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_PUKCC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_PUKCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_PUKCC_Msk) >> TAL_INTCPUSEL4_PUKCC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_PUKCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_PUKCC_Msk; + tmp |= value << TAL_INTCPUSEL4_PUKCC_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_PUKCC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_PUKCC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_PUKCC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_PUKCC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_QSPI_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_QSPI_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL4_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp = (tmp & TAL_INTCPUSEL4_QSPI_Msk) >> TAL_INTCPUSEL4_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= ~TAL_INTCPUSEL4_QSPI_Msk; + tmp |= value << TAL_INTCPUSEL4_QSPI_Pos; + ((Tal *)hw)->INTCPUSEL4.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_QSPI_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_QSPI_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_QSPI_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_QSPI_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel4_reg_t hri_tal_get_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL4.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL4.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel4_reg_t hri_tal_read_INTCPUSEL4_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL4.reg; +} + +static inline void hri_tal_set_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL5.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel5_reg_t hri_tal_get_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL5.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL5.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL5.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL5.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel5_reg_t hri_tal_read_INTCPUSEL5_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL5.reg; +} + +static inline void hri_tal_set_INTCPUSEL6_SERCOM4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_SERCOM4_Msk) >> TAL_INTCPUSEL6_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_SERCOM4_Msk; + tmp |= value << TAL_INTCPUSEL6_SERCOM4_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_SERCOM4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_SERCOM4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_SERCOM5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_SERCOM5_Msk) >> TAL_INTCPUSEL6_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_SERCOM5_Msk; + tmp |= value << TAL_INTCPUSEL6_SERCOM5_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_SERCOM5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_SERCOM5_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM5_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_SERCOM6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_SERCOM6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_SERCOM6_Msk) >> TAL_INTCPUSEL6_SERCOM6_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_SERCOM6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_SERCOM6_Msk; + tmp |= value << TAL_INTCPUSEL6_SERCOM6_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_SERCOM6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_SERCOM6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_SERCOM7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_SERCOM7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_SERCOM7_Msk) >> TAL_INTCPUSEL6_SERCOM7_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_SERCOM7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_SERCOM7_Msk; + tmp |= value << TAL_INTCPUSEL6_SERCOM7_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_SERCOM7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_SERCOM7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_TCC4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_TCC4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_TCC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_TCC4_Msk) >> TAL_INTCPUSEL6_TCC4_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_TCC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_TCC4_Msk; + tmp |= value << TAL_INTCPUSEL6_TCC4_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_TCC4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_TCC4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_TCC4_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_TCC4_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_TC6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_TC6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_TC6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_TC6_Msk) >> TAL_INTCPUSEL6_TC6_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_TC6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_TC6_Msk; + tmp |= value << TAL_INTCPUSEL6_TC6_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_TC6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_TC6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_TC6_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_TC6_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_TC7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_TC7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_TC7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_TC7_Msk) >> TAL_INTCPUSEL6_TC7_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_TC7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_TC7_Msk; + tmp |= value << TAL_INTCPUSEL6_TC7_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_TC7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_TC7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_TC7_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_TC7_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_ADC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_ADC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_ADC0_Msk) >> TAL_INTCPUSEL6_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_ADC0_Msk; + tmp |= value << TAL_INTCPUSEL6_ADC0_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_ADC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_ADC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_ADC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_ADC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_ADC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_ADC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_ADC1_Msk) >> TAL_INTCPUSEL6_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_ADC1_Msk; + tmp |= value << TAL_INTCPUSEL6_ADC1_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_ADC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_ADC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_ADC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_ADC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_DAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_DAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_DAC_Msk) >> TAL_INTCPUSEL6_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_DAC_Msk; + tmp |= value << TAL_INTCPUSEL6_DAC_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_DAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_DAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_DAC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_DAC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_I2S_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_I2S_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_I2S_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_I2S_Msk) >> TAL_INTCPUSEL6_I2S_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_I2S_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_I2S_Msk; + tmp |= value << TAL_INTCPUSEL6_I2S_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_I2S_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_I2S_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_I2S_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_I2S_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_PCC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_PCC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL6_PCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp = (tmp & TAL_INTCPUSEL6_PCC_Msk) >> TAL_INTCPUSEL6_PCC_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_PCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= ~TAL_INTCPUSEL6_PCC_Msk; + tmp |= value << TAL_INTCPUSEL6_PCC_Pos; + ((Tal *)hw)->INTCPUSEL6.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_PCC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_PCC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_PCC_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_PCC_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel6_reg_t hri_tal_get_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL6.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL6.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel6_reg_t hri_tal_read_INTCPUSEL6_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL6.reg; +} + +static inline void hri_tal_set_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL7.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel7_reg_t hri_tal_get_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL7.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL7.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL7.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL7.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel7_reg_t hri_tal_read_INTCPUSEL7_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL7.reg; +} + +static inline void hri_tal_set_INTCPUSEL8_SDHC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg |= TAL_INTCPUSEL8_SDHC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL8_SDHC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL8.reg; + tmp = (tmp & TAL_INTCPUSEL8_SDHC0_Msk) >> TAL_INTCPUSEL8_SDHC0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL8_SDHC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL8.reg; + tmp &= ~TAL_INTCPUSEL8_SDHC0_Msk; + tmp |= value << TAL_INTCPUSEL8_SDHC0_Pos; + ((Tal *)hw)->INTCPUSEL8.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL8_SDHC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg &= ~TAL_INTCPUSEL8_SDHC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL8_SDHC0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg ^= TAL_INTCPUSEL8_SDHC0_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL8_SDHC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg |= TAL_INTCPUSEL8_SDHC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_INTCPUSEL8_SDHC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL8.reg; + tmp = (tmp & TAL_INTCPUSEL8_SDHC1_Msk) >> TAL_INTCPUSEL8_SDHC1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_INTCPUSEL8_SDHC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->INTCPUSEL8.reg; + tmp &= ~TAL_INTCPUSEL8_SDHC1_Msk; + tmp |= value << TAL_INTCPUSEL8_SDHC1_Pos; + ((Tal *)hw)->INTCPUSEL8.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL8_SDHC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg &= ~TAL_INTCPUSEL8_SDHC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL8_SDHC1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg ^= TAL_INTCPUSEL8_SDHC1_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel8_reg_t hri_tal_get_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->INTCPUSEL8.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->INTCPUSEL8.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_intcpusel8_reg_t hri_tal_read_INTCPUSEL8_reg(const void *const hw) +{ + return ((Tal *)hw)->INTCPUSEL8.reg; +} + +static inline void hri_tal_set_IRQTRIG_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_IRQTRIG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp = (tmp & TAL_IRQTRIG_ENABLE) >> TAL_IRQTRIG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_IRQTRIG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp &= ~TAL_IRQTRIG_ENABLE; + tmp |= value << TAL_IRQTRIG_ENABLE_Pos; + ((Tal *)hw)->IRQTRIG.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQTRIG_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQTRIG_ENABLE_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_ENABLE; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_IRQNUM(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp = (tmp & TAL_IRQTRIG_IRQNUM(mask)) >> TAL_IRQTRIG_IRQNUM_Pos; + return tmp; +} + +static inline void hri_tal_write_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t data) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp &= ~TAL_IRQTRIG_IRQNUM_Msk; + tmp |= TAL_IRQTRIG_IRQNUM(data); + ((Tal *)hw)->IRQTRIG.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_IRQNUM(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_IRQNUM(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_IRQNUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp = (tmp & TAL_IRQTRIG_IRQNUM_Msk) >> TAL_IRQTRIG_IRQNUM_Pos; + return tmp; +} + +static inline void hri_tal_set_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_OVERRIDE(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp = (tmp & TAL_IRQTRIG_OVERRIDE(mask)) >> TAL_IRQTRIG_OVERRIDE_Pos; + return tmp; +} + +static inline void hri_tal_write_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t data) +{ + uint32_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp &= ~TAL_IRQTRIG_OVERRIDE_Msk; + tmp |= TAL_IRQTRIG_OVERRIDE(data); + ((Tal *)hw)->IRQTRIG.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_OVERRIDE(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_OVERRIDE(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_OVERRIDE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp = (tmp & TAL_IRQTRIG_OVERRIDE_Msk) >> TAL_IRQTRIG_OVERRIDE_Pos; + return tmp; +} + +static inline void hri_tal_set_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->IRQTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQTRIG.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_reg(const void *const hw) +{ + return ((Tal *)hw)->IRQTRIG.reg; +} + +static inline void hri_tal_set_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_EXTEND; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp = (tmp & TAL_IRQMON_EXTEND) >> TAL_IRQMON_EXTEND_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_IRQMON_EXTEND_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp &= ~TAL_IRQMON_EXTEND; + tmp |= value << TAL_IRQMON_EXTEND_Pos; + ((Tal *)hw)->IRQMON[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_EXTEND; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_EXTEND; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_IRQMON_DROP_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_DROP; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_IRQMON_DROP_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp = (tmp & TAL_IRQMON_DROP) >> TAL_IRQMON_DROP_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_IRQMON_DROP_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp &= ~TAL_IRQMON_DROP; + tmp |= value << TAL_IRQMON_DROP_Pos; + ((Tal *)hw)->IRQMON[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQMON_DROP_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_DROP; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQMON_DROP_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_DROP; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_IRQMON_CPUID_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_CPUID_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_IRQMON_CPUID_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp = (tmp & TAL_IRQMON_CPUID_Msk) >> TAL_IRQMON_CPUID_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_IRQMON_CPUID_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp &= ~TAL_IRQMON_CPUID_Msk; + tmp |= value << TAL_IRQMON_CPUID_Pos; + ((Tal *)hw)->IRQMON[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQMON_CPUID_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_CPUID_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQMON_CPUID_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_CPUID_Msk; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_IRQNUM(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqmon_reg_t hri_tal_get_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, + hri_tal_irqmon_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp = (tmp & TAL_IRQMON_IRQNUM(mask)) >> TAL_IRQMON_IRQNUM_Pos; + return tmp; +} + +static inline void hri_tal_write_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t data) +{ + uint16_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp &= ~TAL_IRQMON_IRQNUM_Msk; + tmp |= TAL_IRQMON_IRQNUM(data); + ((Tal *)hw)->IRQMON[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_IRQNUM(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_IRQNUM(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqmon_reg_t hri_tal_read_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp = (tmp & TAL_IRQMON_IRQNUM_Msk) >> TAL_IRQMON_IRQNUM_Pos; + return tmp; +} + +static inline void hri_tal_set_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqmon_reg_t hri_tal_get_IRQMON_reg(const void *const hw, uint8_t index, + hri_tal_irqmon_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->IRQMON[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->IRQMON[index].reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_irqmon_reg_t hri_tal_read_IRQMON_reg(const void *const hw, uint8_t index) +{ + return ((Tal *)hw)->IRQMON[index].reg; +} + +static inline void hri_tal_set_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->SFLAGCLRR[index].reg |= TAL_SFLAGCLRR_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->SFLAGCLRR[index].reg; + tmp = (tmp & TAL_SFLAGCLRR_IPS) >> TAL_SFLAGCLRR_IPS_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->SFLAGCLRR[index].reg; + tmp &= ~TAL_SFLAGCLRR_IPS; + tmp |= value << TAL_SFLAGCLRR_IPS_Pos; + ((Tal *)hw)->SFLAGCLRR[index].reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->SFLAGCLRR[index].reg &= ~TAL_SFLAGCLRR_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->SFLAGCLRR[index].reg ^= TAL_SFLAGCLRR_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->SFLAGCLRR[index].reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_sflagclrr_reg_t hri_tal_get_SFLAGCLRR_reg(const void *const hw, uint8_t index, + hri_tal_sflagclrr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->SFLAGCLRR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->SFLAGCLRR[index].reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->SFLAGCLRR[index].reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->SFLAGCLRR[index].reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_sflagclrr_reg_t hri_tal_read_SFLAGCLRR_reg(const void *const hw, uint8_t index) +{ + return ((Tal *)hw)->SFLAGCLRR[index].reg; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_CPU0_bf(const void *const hw, hri_tal_brkstatus_reg_t mask) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU0(mask)) >> TAL_BRKSTATUS_CPU0_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_CPU0_bf(const void *const hw) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU0_Msk) >> TAL_BRKSTATUS_CPU0_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_CPU1_bf(const void *const hw, hri_tal_brkstatus_reg_t mask) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU1(mask)) >> TAL_BRKSTATUS_CPU1_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_CPU1_bf(const void *const hw) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU1_Msk) >> TAL_BRKSTATUS_CPU1_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_EVBRK_bf(const void *const hw, hri_tal_brkstatus_reg_t mask) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EVBRK(mask)) >> TAL_BRKSTATUS_EVBRK_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_EVBRK_bf(const void *const hw) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EVBRK_Msk) >> TAL_BRKSTATUS_EVBRK_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_EXTBRK_bf(const void *const hw, + hri_tal_brkstatus_reg_t mask) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EXTBRK(mask)) >> TAL_BRKSTATUS_EXTBRK_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_EXTBRK_bf(const void *const hw) +{ + return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EXTBRK_Msk) >> TAL_BRKSTATUS_EXTBRK_Pos; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_reg(const void *const hw, hri_tal_brkstatus_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tal *)hw)->BRKSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_reg(const void *const hw) +{ + return ((Tal *)hw)->BRKSTATUS.reg; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ0_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ0) >> TAL_INTSTATUS_IRQ0_Pos; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ1_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ1) >> TAL_INTSTATUS_IRQ1_Pos; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ2_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ2) >> TAL_INTSTATUS_IRQ2_Pos; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ3_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ3) >> TAL_INTSTATUS_IRQ3_Pos; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ4_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ4) >> TAL_INTSTATUS_IRQ4_Pos; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ5_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ5) >> TAL_INTSTATUS_IRQ5_Pos; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ6_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ6) >> TAL_INTSTATUS_IRQ6_Pos; +} + +static inline bool hri_tal_get_INTSTATUS_IRQ7_bit(const void *const hw, uint8_t index) +{ + return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ7) >> TAL_INTSTATUS_IRQ7_Pos; +} + +static inline hri_tal_intstatus_reg_t hri_tal_get_INTSTATUS_reg(const void *const hw, uint8_t index, + hri_tal_intstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->INTSTATUS[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_tal_intstatus_reg_t hri_tal_read_INTSTATUS_reg(const void *const hw, uint8_t index) +{ + return ((Tal *)hw)->INTSTATUS[index].reg; +} + +static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_get_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t index, + hri_tal_cpuirqs_reg_t mask) +{ + return (((TalCpuirqs *)hw)->CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS(mask)) >> TAL_CPUIRQS_CPUIRQS_Pos; +} + +static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_read_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t index) +{ + return (((TalCpuirqs *)hw)->CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS_Msk) >> TAL_CPUIRQS_CPUIRQS_Pos; +} + +static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_get_CPUIRQS_reg(const void *const hw, uint8_t index, + hri_tal_cpuirqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((TalCpuirqs *)hw)->CPUIRQS[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_read_CPUIRQS_reg(const void *const hw, uint8_t index) +{ + return ((TalCpuirqs *)hw)->CPUIRQS[index].reg; +} + +static inline hri_tal_cpuirqs_reg_t hri_tal_get_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_tal_cpuirqs_reg_t mask) +{ + return (((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS(mask)) + >> TAL_CPUIRQS_CPUIRQS_Pos; +} + +static inline hri_tal_cpuirqs_reg_t hri_tal_read_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return (((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS_Msk) + >> TAL_CPUIRQS_CPUIRQS_Pos; +} + +static inline hri_tal_cpuirqs_reg_t hri_tal_get_CPUIRQS_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_tal_cpuirqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_tal_cpuirqs_reg_t hri_tal_read_CPUIRQS_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg; +} + +static inline void hri_talctis_set_CTICTRLA_RESTART_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_RESTART; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talctis_get_CTICTRLA_RESTART_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_RESTART) >> TAL_CTICTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_talctis_write_CTICTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp &= ~TAL_CTICTRLA_RESTART; + tmp |= value << TAL_CTICTRLA_RESTART_Pos; + ((TalCtis *)hw)->CTICTRLA.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTICTRLA_RESTART_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_RESTART; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTICTRLA_RESTART_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_RESTART; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_set_CTICTRLA_IPS_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talctis_get_CTICTRLA_IPS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_IPS) >> TAL_CTICTRLA_IPS_Pos; + return (bool)tmp; +} + +static inline void hri_talctis_write_CTICTRLA_IPS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp &= ~TAL_CTICTRLA_IPS; + tmp |= value << TAL_CTICTRLA_IPS_Pos; + ((TalCtis *)hw)->CTICTRLA.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTICTRLA_IPS_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTICTRLA_IPS_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_set_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_BRK(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_talctis_get_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_BRK(mask)) >> TAL_CTICTRLA_BRK_Pos; + return tmp; +} + +static inline void hri_talctis_write_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t data) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp &= ~TAL_CTICTRLA_BRK_Msk; + tmp |= TAL_CTICTRLA_BRK(data); + ((TalCtis *)hw)->CTICTRLA.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_BRK(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_BRK(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_talctis_read_CTICTRLA_BRK_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_BRK_Msk) >> TAL_CTICTRLA_BRK_Pos; + return tmp; +} + +static inline void hri_talctis_set_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_talctis_get_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTICTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_talctis_write_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTICTRLA.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_talctis_read_CTICTRLA_reg(const void *const hw) +{ + return ((TalCtis *)hw)->CTICTRLA.reg; +} + +static inline void hri_talctis_set_CTIMASK_CPU0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talctis_get_CTIMASK_CPU0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_CPU0) >> TAL_CTIMASK_CPU0_Pos; + return (bool)tmp; +} + +static inline void hri_talctis_write_CTIMASK_CPU0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp &= ~TAL_CTIMASK_CPU0; + tmp |= value << TAL_CTIMASK_CPU0_Pos; + ((TalCtis *)hw)->CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTIMASK_CPU0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTIMASK_CPU0_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_set_CTIMASK_CPU1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talctis_get_CTIMASK_CPU1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_CPU1) >> TAL_CTIMASK_CPU1_Pos; + return (bool)tmp; +} + +static inline void hri_talctis_write_CTIMASK_CPU1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp &= ~TAL_CTIMASK_CPU1; + tmp |= value << TAL_CTIMASK_CPU1_Pos; + ((TalCtis *)hw)->CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTIMASK_CPU1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTIMASK_CPU1_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_set_CTIMASK_EVBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talctis_get_CTIMASK_EVBRK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_EVBRK) >> TAL_CTIMASK_EVBRK_Pos; + return (bool)tmp; +} + +static inline void hri_talctis_write_CTIMASK_EVBRK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp &= ~TAL_CTIMASK_EVBRK; + tmp |= value << TAL_CTIMASK_EVBRK_Pos; + ((TalCtis *)hw)->CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTIMASK_EVBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTIMASK_EVBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_set_CTIMASK_EXTBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_talctis_get_CTIMASK_EXTBRK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_EXTBRK) >> TAL_CTIMASK_EXTBRK_Pos; + return (bool)tmp; +} + +static inline void hri_talctis_write_CTIMASK_EXTBRK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp &= ~TAL_CTIMASK_EXTBRK; + tmp |= value << TAL_CTIMASK_EXTBRK_Pos; + ((TalCtis *)hw)->CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTIMASK_EXTBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTIMASK_EXTBRK_bit(const void *const hw) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_set_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctimask_reg_t hri_talctis_get_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) +{ + uint8_t tmp; + tmp = ((TalCtis *)hw)->CTIMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_talctis_write_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_clear_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_talctis_toggle_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((TalCtis *)hw)->CTIMASK.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctimask_reg_t hri_talctis_read_CTIMASK_reg(const void *const hw) +{ + return ((TalCtis *)hw)->CTIMASK.reg; +} + +static inline void hri_tal_set_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_RESTART; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_RESTART) >> TAL_CTICTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp &= ~TAL_CTICTRLA_RESTART; + tmp |= value << TAL_CTICTRLA_RESTART_Pos; + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_RESTART; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_RESTART; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_IPS) >> TAL_CTICTRLA_IPS_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp &= ~TAL_CTICTRLA_IPS; + tmp |= value << TAL_CTICTRLA_IPS_Pos; + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_IPS; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_BRK(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_tal_get_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_BRK(mask)) >> TAL_CTICTRLA_BRK_Pos; + return tmp; +} + +static inline void hri_tal_write_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t data) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp &= ~TAL_CTICTRLA_BRK_Msk; + tmp |= TAL_CTICTRLA_BRK(data); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_BRK(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_BRK(mask); + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_tal_read_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp = (tmp & TAL_CTICTRLA_BRK_Msk) >> TAL_CTICTRLA_BRK_Pos; + return tmp; +} + +static inline void hri_tal_set_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_tal_get_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_tal_ctictrla_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctictrla_reg_t hri_tal_read_CTICTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; +} + +static inline void hri_tal_set_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_CPU0) >> TAL_CTIMASK_CPU0_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp &= ~TAL_CTIMASK_CPU0; + tmp |= value << TAL_CTIMASK_CPU0_Pos; + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_CPU0; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_CPU1) >> TAL_CTIMASK_CPU1_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp &= ~TAL_CTIMASK_CPU1; + tmp |= value << TAL_CTIMASK_CPU1_Pos; + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_CPU1; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_EVBRK) >> TAL_CTIMASK_EVBRK_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp &= ~TAL_CTIMASK_EVBRK; + tmp |= value << TAL_CTIMASK_EVBRK_Pos; + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_EVBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tal_get_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp = (tmp & TAL_CTIMASK_EXTBRK) >> TAL_CTIMASK_EXTBRK_Pos; + return (bool)tmp; +} + +static inline void hri_tal_write_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + TAL_CRITICAL_SECTION_ENTER(); + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp &= ~TAL_CTIMASK_EXTBRK; + tmp |= value << TAL_CTIMASK_EXTBRK_Pos; + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_EXTBRK; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_set_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctimask_reg_t hri_tal_get_CTIMASK_reg(const void *const hw, uint8_t submodule_index, + hri_tal_ctimask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tal_write_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t data) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = data; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_clear_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tal_toggle_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask) +{ + TAL_CRITICAL_SECTION_ENTER(); + ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= mask; + TAL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tal_ctimask_reg_t hri_tal_read_CTIMASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TAL_D51_H_INCLUDED */ +#endif /* _SAMD51_TAL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_tc_d51.h b/atmel-samd/asf4/samd51/hri/hri_tc_d51.h new file mode 100644 index 0000000000000..4812958587178 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_tc_d51.h @@ -0,0 +1,2861 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_TC_COMPONENT_ +#ifndef _HRI_TC_D51_H_INCLUDED_ +#define _HRI_TC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_cc16_reg_t; +typedef uint16_t hri_tc_ccbuf16_reg_t; +typedef uint16_t hri_tc_count16_reg_t; +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint32_t hri_tc_cc32_reg_t; +typedef uint32_t hri_tc_ccbuf32_reg_t; +typedef uint32_t hri_tc_count32_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint8_t hri_tc_cc8_reg_t; +typedef uint8_t hri_tc_ccbuf8_reg_t; +typedef uint8_t hri_tc_count8_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_per_reg_t; +typedef uint8_t hri_tc_perbuf_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tc_count16_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf16_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tc_ccbuf16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf16_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf16_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tc_ccbuf16_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf16_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tc_count32_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf32_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tc_ccbuf32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf32_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf32_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tc_ccbuf32_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf32_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT8.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT8.INTENSET.reg = data; + ((Tc *)hw)->COUNT8.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT8.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT8.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ENABLE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ENABLE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ENABLE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ONDEMAND; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ALOCK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ALOCK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ALOCK; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_COPEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_COPEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_COPEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_COPEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_COPEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_COPEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_MODE(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_MODE(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE0_Msk; + tmp |= TC_CTRLA_CAPTMODE0(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE1_Msk; + tmp |= TC_CTRLA_CAPTMODE1(data); + ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CTRLA.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT8.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT8.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT8.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT8.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tc_count8_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tc_set_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_get_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tc_write_PER_PER_bf(const void *const hw, hri_tc_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tc_set_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_get_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_PER_reg(const void *const hw, hri_tc_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_PER_reg(const void *const hw, hri_tc_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_per_reg_t hri_tc_read_PER_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_perbuf_reg_t hri_tc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_perbuf_reg_t hri_tc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tc_set_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_perbuf_reg_t hri_tc_get_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_perbuf_reg_t hri_tc_read_PERBUF_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf8_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tc_ccbuf8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf8_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf8_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tc_ccbuf8_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ccbuf8_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT8.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_STOP; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_SLAVE; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_PERBUFV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_CCBUFV0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_CCBUFV1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.STATUS.reg = mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT8.STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_D51_H_INCLUDED */ +#endif /* _SAMD51_TC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_tcc_d51.h b/atmel-samd/asf4/samd51/hri/hri_tcc_d51.h new file mode 100644 index 0000000000000..8a2472887bb76 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_tcc_d51.h @@ -0,0 +1,10329 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_TCC_COMPONENT_ +#ifndef _HRI_TCC_D51_H_INCLUDED_ +#define _HRI_TCC_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH4_COUNT(mask)) >> TCC_COUNT_DITH4_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_DITH4_COUNT_Msk; + tmp |= TCC_COUNT_DITH4_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH4_COUNT_Msk) >> TCC_COUNT_DITH4_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH5_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH5_COUNT(mask)) >> TCC_COUNT_DITH5_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_DITH5_COUNT_Msk; + tmp |= TCC_COUNT_DITH5_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH5_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH5_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH5_COUNT_Msk) >> TCC_COUNT_DITH5_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH6_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH6_COUNT(mask)) >> TCC_COUNT_DITH6_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_DITH6_COUNT_Msk; + tmp |= TCC_COUNT_DITH6_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH6_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH6_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_DITH6_COUNT_Msk) >> TCC_COUNT_DITH6_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_PER(mask)) >> TCC_PER_DITH4_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_PER_Msk; + tmp |= TCC_PER_DITH4_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_PER_Msk) >> TCC_PER_DITH4_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_PER(mask)) >> TCC_PER_DITH5_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_PER_Msk; + tmp |= TCC_PER_DITH5_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_PER_Msk) >> TCC_PER_DITH5_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_PER(mask)) >> TCC_PER_DITH6_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_PER_Msk; + tmp |= TCC_PER_DITH6_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_PER_Msk) >> TCC_PER_DITH6_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_CC(mask)) >> TCC_CC_DITH4_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_CC_Msk; + tmp |= TCC_CC_DITH4_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_CC_Msk) >> TCC_CC_DITH4_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_CC(mask)) >> TCC_CC_DITH5_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_CC_Msk; + tmp |= TCC_CC_DITH5_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_CC_Msk) >> TCC_CC_DITH5_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_CC(mask)) >> TCC_CC_DITH6_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_CC_Msk; + tmp |= TCC_CC_DITH6_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_CC_Msk) >> TCC_CC_DITH6_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_PERBUF(mask)) >> TCC_PERBUF_DITH4_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_PERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_PERBUF_Msk) >> TCC_PERBUF_DITH4_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_PERBUF(mask)) >> TCC_PERBUF_DITH5_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_PERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_PERBUF_Msk) >> TCC_PERBUF_DITH5_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_PERBUF(mask)) >> TCC_PERBUF_DITH6_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_PERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_PERBUF_Msk) >> TCC_PERBUF_DITH6_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_CCBUF(mask)) >> TCC_CCBUF_DITH4_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_CCBUF_Msk; + tmp |= TCC_CCBUF_DITH4_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_CCBUF_Msk) >> TCC_CCBUF_DITH4_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_CCBUF(mask)) >> TCC_CCBUF_DITH5_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_CCBUF_Msk; + tmp |= TCC_CCBUF_DITH5_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_CCBUF_Msk) >> TCC_CCBUF_DITH5_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_CCBUF(mask)) >> TCC_CCBUF_DITH6_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_CCBUF_Msk; + tmp |= TCC_CCBUF_DITH6_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_CCBUF_Msk) >> TCC_CCBUF_DITH6_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_reg(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline void hri_tcc_set_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_reg(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline void hri_tcc_set_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_reg(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; +} + +static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; +} + +static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; + } +} + +static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; +} + +static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; +} + +static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; +} + +static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; + } +} + +static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN4; + tmp |= value << TCC_CTRLA_CPTEN4_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN5; + tmp |= value << TCC_CTRLA_CPTEN5_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI4; + tmp |= value << TCC_EVCTRL_MCEI4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI5; + tmp |= value << TCC_EVCTRL_MCEI5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO4; + tmp |= value << TCC_EVCTRL_MCEO4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO5; + tmp |= value << TCC_EVCTRL_MCEO5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL4; + tmp |= value << TCC_WAVE_POL4_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL5; + tmp |= value << TCC_WAVE_POL5_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + return ((Tcc *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_D51_H_INCLUDED */ +#endif /* _SAMD51_TCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_trng_d51.h b/atmel-samd/asf4/samd51/hri/hri_trng_d51.h new file mode 100644 index 0000000000000..070e4c1ece591 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_trng_d51.h @@ -0,0 +1,389 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_D51_H_INCLUDED_ +#define _HRI_TRNG_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_D51_H_INCLUDED */ +#endif /* _SAMD51_TRNG_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_usb_d51.h b/atmel-samd/asf4/samd51/hri/hri_usb_d51.h new file mode 100644 index 0000000000000..5a3047d22e341 --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_usb_d51.h @@ -0,0 +1,9851 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_USB_COMPONENT_ +#ifndef _HRI_USB_D51_H_INCLUDED_ +#define _HRI_USB_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_descriptor_extreg_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbdevice_padcal_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_descriptor_ctrl_pipe_reg_t; +typedef uint16_t hri_usbhost_descriptor_extreg_reg_t; +typedef uint16_t hri_usbhost_descriptor_status_pipe_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_padcal_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdevice_descadd_reg_t; +typedef uint32_t hri_usbdevice_descriptor_addr_reg_t; +typedef uint32_t hri_usbdevice_descriptor_pcksize_reg_t; +typedef uint32_t hri_usbhost_descadd_reg_t; +typedef uint32_t hri_usbhost_descriptor_addr_reg_t; +typedef uint32_t hri_usbhost_descriptor_pcksize_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdevice_ctrla_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_descriptor_status_bk_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_fsmstatus_reg_t; +typedef uint8_t hri_usbdevice_qosctrl_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbdevice_syncbusy_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_ctrla_reg_t; +typedef uint8_t hri_usbhost_descriptor_status_bk_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_fsmstatus_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_qosctrl_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbhost_syncbusy_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usbdevice_wait_for_sync(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usbdevice_is_syncing(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline void hri_usbhost_wait_for_sync(const void *const hw, hri_usbhost_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->HOST.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usbhost_is_syncing(const void *const hw, hri_usbhost_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg & reg; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrla_reg_t hri_usbhost_get_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrla_reg_t hri_usbhost_read_CTRLA_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usbhost_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_CQOS_bf(const void *const hw, + hri_usbhost_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_DQOS_bf(const void *const hw, + hri_usbhost_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbhost_set_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_reg(const void *const hw, + hri_usbhost_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_AUTORESUME; + tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usbhost_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_DESCADD_bf(const void *const hw, + hri_usbhost_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbhost_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbhost_set_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_reg(const void *const hw, + hri_usbhost_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usbhost_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSP_bf(const void *const hw, + hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSN_bf(const void *const hw, + hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRIM_bf(const void *const hw, + hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline bool hri_usbhost_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usbhost_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usbhost_syncbusy_reg_t hri_usbhost_get_SYNCBUSY_reg(const void *const hw, + hri_usbhost_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_syncbusy_reg_t hri_usbhost_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usbhost_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_reg(const void *const hw, + hri_usbhost_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_descriptor_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descriptor_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_get_CTRLA_reg(const void *const hw, + hri_usbdevice_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLA.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_read_CTRLA_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLA.reg; +} + +static inline void hri_usbdevice_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_CQOS_bf(const void *const hw, + hri_usbdevice_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_DQOS_bf(const void *const hw, + hri_usbdevice_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_reg(const void *const hw, + hri_usbdevice_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbdevice_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_DESCADD_bf(const void *const hw, + hri_usbdevice_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->DEVICE.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_reg(const void *const hw, + hri_usbdevice_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DESCADD.reg; +} + +static inline void hri_usbdevice_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSP_bf(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSN_bf(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRIM_bf(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_reg(const void *const hw, + hri_usbdevice_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.PADCAL.reg; +} + +static inline bool hri_usbdevice_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usbdevice_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_get_SYNCBUSY_reg(const void *const hw, + hri_usbdevice_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usbdevice_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_reg(const void *const hw, + hri_usbdevice_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_descriptor_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_descriptor_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_D51_H_INCLUDED */ +#endif /* _SAMD51_USB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_wdt_d51.h b/atmel-samd/asf4/samd51/hri/hri_wdt_d51.h new file mode 100644 index 0000000000000..f711c59c3d42a --- /dev/null +++ b/atmel-samd/asf4/samd51/hri/hri_wdt_d51.h @@ -0,0 +1,619 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (C) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + */ + +#ifdef _SAMD51_WDT_COMPONENT_ +#ifndef _HRI_WDT_D51_H_INCLUDED_ +#define _HRI_WDT_D51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_D51_H_INCLUDED */ +#endif /* _SAMD51_WDT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component-version.h b/atmel-samd/asf4/samd51/include/component-version.h new file mode 100644 index 0000000000000..43414ee1b62f2 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component-version.h @@ -0,0 +1,65 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 0 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION +// is at least 8 digits long. +// +#define COMPONENT_VERSION 00010000 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 66 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.0" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2017-05-22 10:59:01" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/atmel-samd/asf4/samd51/include/component/ac.h b/atmel-samd/asf4/samd51/include/component/ac.h new file mode 100644 index 0000000000000..7f7796beb3cdc --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/ac.h @@ -0,0 +1,597 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_AC_COMPONENT_ +#define _SAMD51_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_AC Analog Comparators */ +/*@{*/ + +#define AC_U2501 +#define REV_AC 0x100 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ + uint16_t :14; /*!< bit: 2..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} AC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ +#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ + +#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ +#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) +#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/adc.h b/atmel-samd/asf4/samd51/include/component/adc.h new file mode 100644 index 0000000000000..a8114910615a0 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/adc.h @@ -0,0 +1,870 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_ADC_COMPONENT_ +#define _SAMD51_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2500 +#define REV_ADC 0x100 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t :1; /*!< bit: 2 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ + uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :4; /*!< bit: 11..14 Reserved */ + uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ +#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) +#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ +#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ +#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) +#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ +#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) +#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :2; /*!< bit: 5.. 6 Reserved */ + uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :2; /*!< bit: 13..14 Reserved */ + uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ +#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ +#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ +#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ +#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) +#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ +#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) +#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ +#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) +#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ +#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) +#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ + uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ + uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ + uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ + uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ + uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ + uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ + uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ + uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) +#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ +#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ +#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ + +#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ +#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) +#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ +#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ +#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) +#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ +#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) +#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ +#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) +#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ +#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) +#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ +#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) +#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ +#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) +#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ +#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) +#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ +#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) +#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ +#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) +#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ +#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) +#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQSTAT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ +#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ +#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) +#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ +#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) +#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ +#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) +#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ +#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) +#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ +#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) +#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ +#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) +#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ +#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) +#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ +#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) +#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ +#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) +#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ +#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) +#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ +#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ + +#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ +#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) +#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ +#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ + RoReg8 Reserved1[0x1]; + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x17]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ + __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ + RoReg8 Reserved3[0x2]; + __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ + RoReg8 Reserved4[0x2]; + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/aes.h b/atmel-samd/asf4/samd51/include/component/aes.h new file mode 100644 index 0000000000000..6d85768c933aa --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/aes.h @@ -0,0 +1,374 @@ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_AES_COMPONENT_ +#define _SAMD51_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAMD51_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x220 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ + uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ + uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ + uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_AES_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/can.h b/atmel-samd/asf4/samd51/include/component/can.h new file mode 100644 index 0000000000000..9d6754998c61a --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/can.h @@ -0,0 +1,3207 @@ +/** + * \file + * + * \brief Component description for CAN + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_CAN_COMPONENT_ +#define _SAMD51_CAN_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CAN */ +/* ========================================================================== */ +/** \addtogroup SAMD51_CAN Control Area Network */ +/*@{*/ + +#define CAN_U2003 +#define REV_CAN 0x321 + +/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :20; /*!< bit: 0..19 Reserved */ + uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ + uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ + uint32_t REL:4; /*!< bit: 28..31 Core Release */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CREL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ +#define CAN_CREL_RESETVALUE 0x32100000u /**< \brief (CAN_CREL reset_value) Core Release */ + +#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ +#define CAN_CREL_SUBSTEP_Msk (0xFu << CAN_CREL_SUBSTEP_Pos) +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) +#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ +#define CAN_CREL_STEP_Msk (0xFu << CAN_CREL_STEP_Pos) +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) +#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ +#define CAN_CREL_REL_Msk (0xFu << CAN_CREL_REL_Pos) +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) +#define CAN_CREL_MASK 0xFFF00000u /**< \brief (CAN_CREL) MASK Register */ + +/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ENDN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ +#define CAN_ENDN_RESETVALUE 0x87654321u /**< \brief (CAN_ENDN reset_value) Endian */ + +#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ +#define CAN_ENDN_ETV_Msk (0xFFFFFFFFu << CAN_ENDN_ETV_Pos) +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) +#define CAN_ENDN_MASK 0xFFFFFFFFu /**< \brief (CAN_ENDN) MASK Register */ + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_MRCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ +#define CAN_MRCFG_RESETVALUE 0x00000002u /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ + +#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ +#define CAN_MRCFG_QOS_Msk (0x3u << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) +#define CAN_MRCFG_QOS_DISABLE_Val 0x0u /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val 0x1u /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val 0x2u /**< \brief (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val 0x3u /**< \brief (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_MASK 0x00000003u /**< \brief (CAN_MRCFG) MASK Register */ + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ + uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ + uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ + uint32_t :2; /*!< bit: 21..22 Reserved */ + uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_DBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ +#define CAN_DBTP_RESETVALUE 0x00000A33u /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ + +#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ +#define CAN_DBTP_DSJW_Msk (0xFu << CAN_DBTP_DSJW_Pos) +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) +#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ +#define CAN_DBTP_DTSEG2_Msk (0xFu << CAN_DBTP_DTSEG2_Pos) +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) +#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ +#define CAN_DBTP_DTSEG1_Msk (0x1Fu << CAN_DBTP_DTSEG1_Pos) +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) +#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ +#define CAN_DBTP_DBRP_Msk (0x1Fu << CAN_DBTP_DBRP_Pos) +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) +#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ +#define CAN_DBTP_TDC (0x1u << CAN_DBTP_TDC_Pos) +#define CAN_DBTP_MASK 0x009F1FFFu /**< \brief (CAN_DBTP) MASK Register */ + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ + uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ + uint32_t RX:1; /*!< bit: 7 Receive Pin */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TEST_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ +#define CAN_TEST_RESETVALUE 0x00000000u /**< \brief (CAN_TEST reset_value) Test */ + +#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ +#define CAN_TEST_LBCK (0x1u << CAN_TEST_LBCK_Pos) +#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ +#define CAN_TEST_TX_Msk (0x3u << CAN_TEST_TX_Pos) +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) +#define CAN_TEST_TX_CORE_Val 0x0u /**< \brief (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val 0x1u /**< \brief (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val 0x2u /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val 0x3u /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ +#define CAN_TEST_RX (0x1u << CAN_TEST_RX_Pos) +#define CAN_TEST_MASK 0x000000F0u /**< \brief (CAN_TEST) MASK Register */ + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ + uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RWD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ +#define CAN_RWD_RESETVALUE 0x00000000u /**< \brief (CAN_RWD reset_value) RAM Watchdog */ + +#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ +#define CAN_RWD_WDC_Msk (0xFFu << CAN_RWD_WDC_Pos) +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) +#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ +#define CAN_RWD_WDV_Msk (0xFFu << CAN_RWD_WDV_Pos) +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) +#define CAN_RWD_MASK 0x0000FFFFu /**< \brief (CAN_RWD) MASK Register */ + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INIT:1; /*!< bit: 0 Initialization */ + uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ + uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ + uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ + uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ + uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ + uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ + uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ + uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ + uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ + uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ + uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ + uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CCCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ +#define CAN_CCCR_RESETVALUE 0x00000001u /**< \brief (CAN_CCCR reset_value) CC Control */ + +#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ +#define CAN_CCCR_INIT (0x1u << CAN_CCCR_INIT_Pos) +#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ +#define CAN_CCCR_CCE (0x1u << CAN_CCCR_CCE_Pos) +#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ +#define CAN_CCCR_ASM (0x1u << CAN_CCCR_ASM_Pos) +#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ +#define CAN_CCCR_CSA (0x1u << CAN_CCCR_CSA_Pos) +#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ +#define CAN_CCCR_CSR (0x1u << CAN_CCCR_CSR_Pos) +#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ +#define CAN_CCCR_MON (0x1u << CAN_CCCR_MON_Pos) +#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ +#define CAN_CCCR_DAR (0x1u << CAN_CCCR_DAR_Pos) +#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ +#define CAN_CCCR_TEST (0x1u << CAN_CCCR_TEST_Pos) +#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ +#define CAN_CCCR_FDOE (0x1u << CAN_CCCR_FDOE_Pos) +#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ +#define CAN_CCCR_BRSE (0x1u << CAN_CCCR_BRSE_Pos) +#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ +#define CAN_CCCR_PXHD (0x1u << CAN_CCCR_PXHD_Pos) +#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ +#define CAN_CCCR_EFBI (0x1u << CAN_CCCR_EFBI_Pos) +#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ +#define CAN_CCCR_TXP (0x1u << CAN_CCCR_TXP_Pos) +#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ +#define CAN_CCCR_NISO (0x1u << CAN_CCCR_NISO_Pos) +#define CAN_CCCR_MASK 0x0000F3FFu /**< \brief (CAN_CCCR) MASK Register */ + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ + uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ + uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ +#define CAN_NBTP_RESETVALUE 0x06000A03u /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ + +#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ +#define CAN_NBTP_NTSEG2_Msk (0x7Fu << CAN_NBTP_NTSEG2_Pos) +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) +#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ +#define CAN_NBTP_NTSEG1_Msk (0xFFu << CAN_NBTP_NTSEG1_Pos) +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) +#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ +#define CAN_NBTP_NBRP_Msk (0x1FFu << CAN_NBTP_NBRP_Pos) +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) +#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ +#define CAN_NBTP_NSJW_Msk (0x7Fu << CAN_NBTP_NSJW_Pos) +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) +#define CAN_NBTP_MASK 0xFFFFFF7Fu /**< \brief (CAN_NBTP) MASK Register */ + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ + uint32_t :14; /*!< bit: 2..15 Reserved */ + uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ +#define CAN_TSCC_RESETVALUE 0x00000000u /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ + +#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ +#define CAN_TSCC_TSS_Msk (0x3u << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) +#define CAN_TSCC_TSS_ZERO_Val 0x0u /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val 0x1u /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val 0x2u /**< \brief (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ +#define CAN_TSCC_TCP_Msk (0xFu << CAN_TSCC_TCP_Pos) +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) +#define CAN_TSCC_MASK 0x000F0003u /**< \brief (CAN_TSCC) MASK Register */ + +/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ +#define CAN_TSCV_RESETVALUE 0x00000000u /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ + +#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ +#define CAN_TSCV_TSC_Msk (0xFFFFu << CAN_TSCV_TSC_Pos) +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) +#define CAN_TSCV_MASK 0x0000FFFFu /**< \brief (CAN_TSCV) MASK Register */ + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ + uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ +#define CAN_TOCC_RESETVALUE 0xFFFF0000u /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ + +#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ +#define CAN_TOCC_ETOC (0x1u << CAN_TOCC_ETOC_Pos) +#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ +#define CAN_TOCC_TOS_Msk (0x3u << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) +#define CAN_TOCC_TOS_CONT_Val 0x0u /**< \brief (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val 0x1u /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val 0x2u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val 0x3u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ +#define CAN_TOCC_TOP_Msk (0xFFFFu << CAN_TOCC_TOP_Pos) +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) +#define CAN_TOCC_MASK 0xFFFF0007u /**< \brief (CAN_TOCC) MASK Register */ + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ +#define CAN_TOCV_RESETVALUE 0x0000FFFFu /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ + +#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ +#define CAN_TOCV_TOC_Msk (0xFFFFu << CAN_TOCV_TOC_Pos) +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) +#define CAN_TOCV_MASK 0x0000FFFFu /**< \brief (CAN_TOCV) MASK Register */ + +/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ + uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ + uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ + uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ECR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ +#define CAN_ECR_RESETVALUE 0x00000000u /**< \brief (CAN_ECR reset_value) Error Counter */ + +#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ +#define CAN_ECR_TEC_Msk (0xFFu << CAN_ECR_TEC_Pos) +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) +#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ +#define CAN_ECR_REC_Msk (0x7Fu << CAN_ECR_REC_Pos) +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) +#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ +#define CAN_ECR_RP (0x1u << CAN_ECR_RP_Pos) +#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ +#define CAN_ECR_CEL_Msk (0xFFu << CAN_ECR_CEL_Pos) +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) +#define CAN_ECR_MASK 0x00FFFFFFu /**< \brief (CAN_ECR) MASK Register */ + +/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ + uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ + uint32_t EP:1; /*!< bit: 5 Error Passive */ + uint32_t EW:1; /*!< bit: 6 Warning Status */ + uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ + uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ + uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ + uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ + uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ + uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_PSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ +#define CAN_PSR_RESETVALUE 0x00000707u /**< \brief (CAN_PSR reset_value) Protocol Status */ + +#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ +#define CAN_PSR_LEC_Msk (0x7u << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) +#define CAN_PSR_LEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ +#define CAN_PSR_ACT_Msk (0x3u << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) +#define CAN_PSR_ACT_SYNC_Val 0x0u /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val 0x1u /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val 0x2u /**< \brief (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val 0x3u /**< \brief (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ +#define CAN_PSR_EP (0x1u << CAN_PSR_EP_Pos) +#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ +#define CAN_PSR_EW (0x1u << CAN_PSR_EW_Pos) +#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ +#define CAN_PSR_BO (0x1u << CAN_PSR_BO_Pos) +#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ +#define CAN_PSR_DLEC_Msk (0x7u << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) +#define CAN_PSR_DLEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ +#define CAN_PSR_RESI (0x1u << CAN_PSR_RESI_Pos) +#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ +#define CAN_PSR_RBRS (0x1u << CAN_PSR_RBRS_Pos) +#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ +#define CAN_PSR_RFDF (0x1u << CAN_PSR_RFDF_Pos) +#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ +#define CAN_PSR_PXE (0x1u << CAN_PSR_PXE_Pos) +#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ +#define CAN_PSR_TDCV_Msk (0x7Fu << CAN_PSR_TDCV_Pos) +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) +#define CAN_PSR_MASK 0x007F7FFFu /**< \brief (CAN_PSR) MASK Register */ + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TDCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ +#define CAN_TDCR_RESETVALUE 0x00000000u /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ + +#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ +#define CAN_TDCR_TDCF_Msk (0x7Fu << CAN_TDCR_TDCF_Pos) +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) +#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ +#define CAN_TDCR_TDCO_Msk (0x7Fu << CAN_TDCR_TDCO_Pos) +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) +#define CAN_TDCR_MASK 0x00007F7Fu /**< \brief (CAN_TDCR) MASK Register */ + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ + uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ + uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ + uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ + uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ + uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ + uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ + uint32_t HPM:1; /*!< bit: 8 High Priority Message */ + uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ + uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ + uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ + uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ + uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ + uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ + uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ + uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ + uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ + uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ + uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ + uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ + uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ + uint32_t EP:1; /*!< bit: 23 Error Passive */ + uint32_t EW:1; /*!< bit: 24 Warning Status */ + uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ + uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ + uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ + uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ + uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ +#define CAN_IR_RESETVALUE 0x00000000u /**< \brief (CAN_IR reset_value) Interrupt */ + +#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ +#define CAN_IR_RF0N (0x1u << CAN_IR_RF0N_Pos) +#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ +#define CAN_IR_RF0W (0x1u << CAN_IR_RF0W_Pos) +#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ +#define CAN_IR_RF0F (0x1u << CAN_IR_RF0F_Pos) +#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ +#define CAN_IR_RF0L (0x1u << CAN_IR_RF0L_Pos) +#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ +#define CAN_IR_RF1N (0x1u << CAN_IR_RF1N_Pos) +#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ +#define CAN_IR_RF1W (0x1u << CAN_IR_RF1W_Pos) +#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ +#define CAN_IR_RF1F (0x1u << CAN_IR_RF1F_Pos) +#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ +#define CAN_IR_RF1L (0x1u << CAN_IR_RF1L_Pos) +#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ +#define CAN_IR_HPM (0x1u << CAN_IR_HPM_Pos) +#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ +#define CAN_IR_TC (0x1u << CAN_IR_TC_Pos) +#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ +#define CAN_IR_TCF (0x1u << CAN_IR_TCF_Pos) +#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ +#define CAN_IR_TFE (0x1u << CAN_IR_TFE_Pos) +#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ +#define CAN_IR_TEFN (0x1u << CAN_IR_TEFN_Pos) +#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ +#define CAN_IR_TEFW (0x1u << CAN_IR_TEFW_Pos) +#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ +#define CAN_IR_TEFF (0x1u << CAN_IR_TEFF_Pos) +#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ +#define CAN_IR_TEFL (0x1u << CAN_IR_TEFL_Pos) +#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ +#define CAN_IR_TSW (0x1u << CAN_IR_TSW_Pos) +#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ +#define CAN_IR_MRAF (0x1u << CAN_IR_MRAF_Pos) +#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ +#define CAN_IR_TOO (0x1u << CAN_IR_TOO_Pos) +#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ +#define CAN_IR_DRX (0x1u << CAN_IR_DRX_Pos) +#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ +#define CAN_IR_BEC (0x1u << CAN_IR_BEC_Pos) +#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ +#define CAN_IR_BEU (0x1u << CAN_IR_BEU_Pos) +#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ +#define CAN_IR_ELO (0x1u << CAN_IR_ELO_Pos) +#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ +#define CAN_IR_EP (0x1u << CAN_IR_EP_Pos) +#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ +#define CAN_IR_EW (0x1u << CAN_IR_EW_Pos) +#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ +#define CAN_IR_BO (0x1u << CAN_IR_BO_Pos) +#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ +#define CAN_IR_WDI (0x1u << CAN_IR_WDI_Pos) +#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ +#define CAN_IR_PEA (0x1u << CAN_IR_PEA_Pos) +#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ +#define CAN_IR_PED (0x1u << CAN_IR_PED_Pos) +#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ +#define CAN_IR_ARA (0x1u << CAN_IR_ARA_Pos) +#define CAN_IR_MASK 0x3FFFFFFFu /**< \brief (CAN_IR) MASK Register */ + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ + uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ + uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ + uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ + uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ + uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ + uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ + uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ + uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ + uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ + uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ + uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ + uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ + uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ + uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ + uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ + uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ + uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ + uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ + uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ + uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ + uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ + uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ + uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ + uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ + uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ + uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ + uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ + uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ + uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ +#define CAN_IE_RESETVALUE 0x00000000u /**< \brief (CAN_IE reset_value) Interrupt Enable */ + +#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ +#define CAN_IE_RF0NE (0x1u << CAN_IE_RF0NE_Pos) +#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF0WE (0x1u << CAN_IE_RF0WE_Pos) +#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ +#define CAN_IE_RF0FE (0x1u << CAN_IE_RF0FE_Pos) +#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ +#define CAN_IE_RF0LE (0x1u << CAN_IE_RF0LE_Pos) +#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ +#define CAN_IE_RF1NE (0x1u << CAN_IE_RF1NE_Pos) +#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF1WE (0x1u << CAN_IE_RF1WE_Pos) +#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ +#define CAN_IE_RF1FE (0x1u << CAN_IE_RF1FE_Pos) +#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ +#define CAN_IE_RF1LE (0x1u << CAN_IE_RF1LE_Pos) +#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ +#define CAN_IE_HPME (0x1u << CAN_IE_HPME_Pos) +#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ +#define CAN_IE_TCE (0x1u << CAN_IE_TCE_Pos) +#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define CAN_IE_TCFE (0x1u << CAN_IE_TCFE_Pos) +#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ +#define CAN_IE_TFEE (0x1u << CAN_IE_TFEE_Pos) +#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define CAN_IE_TEFNE (0x1u << CAN_IE_TEFNE_Pos) +#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define CAN_IE_TEFWE (0x1u << CAN_IE_TEFWE_Pos) +#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define CAN_IE_TEFFE (0x1u << CAN_IE_TEFFE_Pos) +#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ +#define CAN_IE_TEFLE (0x1u << CAN_IE_TEFLE_Pos) +#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ +#define CAN_IE_TSWE (0x1u << CAN_IE_TSWE_Pos) +#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ +#define CAN_IE_MRAFE (0x1u << CAN_IE_MRAFE_Pos) +#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ +#define CAN_IE_TOOE (0x1u << CAN_IE_TOOE_Pos) +#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ +#define CAN_IE_DRXE (0x1u << CAN_IE_DRXE_Pos) +#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ +#define CAN_IE_BECE (0x1u << CAN_IE_BECE_Pos) +#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ +#define CAN_IE_BEUE (0x1u << CAN_IE_BEUE_Pos) +#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ +#define CAN_IE_ELOE (0x1u << CAN_IE_ELOE_Pos) +#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ +#define CAN_IE_EPE (0x1u << CAN_IE_EPE_Pos) +#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ +#define CAN_IE_EWE (0x1u << CAN_IE_EWE_Pos) +#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ +#define CAN_IE_BOE (0x1u << CAN_IE_BOE_Pos) +#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ +#define CAN_IE_WDIE (0x1u << CAN_IE_WDIE_Pos) +#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ +#define CAN_IE_PEAE (0x1u << CAN_IE_PEAE_Pos) +#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ +#define CAN_IE_PEDE (0x1u << CAN_IE_PEDE_Pos) +#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ +#define CAN_IE_ARAE (0x1u << CAN_IE_ARAE_Pos) +#define CAN_IE_MASK 0x3FFFFFFFu /**< \brief (CAN_IE) MASK Register */ + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ + uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ + uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ + uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ + uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ + uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ + uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ + uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ + uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ + uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ + uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ + uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ + uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ + uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ + uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ + uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ + uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ + uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ + uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ + uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ + uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ + uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ + uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ + uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ + uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ + uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ + uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ + uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ + uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ + uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ +#define CAN_ILS_RESETVALUE 0x00000000u /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ + +#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ +#define CAN_ILS_RF0NL (0x1u << CAN_ILS_RF0NL_Pos) +#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF0WL (0x1u << CAN_ILS_RF0WL_Pos) +#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ +#define CAN_ILS_RF0FL (0x1u << CAN_ILS_RF0FL_Pos) +#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ +#define CAN_ILS_RF0LL (0x1u << CAN_ILS_RF0LL_Pos) +#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ +#define CAN_ILS_RF1NL (0x1u << CAN_ILS_RF1NL_Pos) +#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF1WL (0x1u << CAN_ILS_RF1WL_Pos) +#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ +#define CAN_ILS_RF1FL (0x1u << CAN_ILS_RF1FL_Pos) +#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ +#define CAN_ILS_RF1LL (0x1u << CAN_ILS_RF1LL_Pos) +#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ +#define CAN_ILS_HPML (0x1u << CAN_ILS_HPML_Pos) +#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ +#define CAN_ILS_TCL (0x1u << CAN_ILS_TCL_Pos) +#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define CAN_ILS_TCFL (0x1u << CAN_ILS_TCFL_Pos) +#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ +#define CAN_ILS_TFEL (0x1u << CAN_ILS_TFEL_Pos) +#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define CAN_ILS_TEFNL (0x1u << CAN_ILS_TEFNL_Pos) +#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define CAN_ILS_TEFWL (0x1u << CAN_ILS_TEFWL_Pos) +#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define CAN_ILS_TEFFL (0x1u << CAN_ILS_TEFFL_Pos) +#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ +#define CAN_ILS_TEFLL (0x1u << CAN_ILS_TEFLL_Pos) +#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ +#define CAN_ILS_TSWL (0x1u << CAN_ILS_TSWL_Pos) +#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ +#define CAN_ILS_MRAFL (0x1u << CAN_ILS_MRAFL_Pos) +#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ +#define CAN_ILS_TOOL (0x1u << CAN_ILS_TOOL_Pos) +#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ +#define CAN_ILS_DRXL (0x1u << CAN_ILS_DRXL_Pos) +#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ +#define CAN_ILS_BECL (0x1u << CAN_ILS_BECL_Pos) +#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ +#define CAN_ILS_BEUL (0x1u << CAN_ILS_BEUL_Pos) +#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ +#define CAN_ILS_ELOL (0x1u << CAN_ILS_ELOL_Pos) +#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ +#define CAN_ILS_EPL (0x1u << CAN_ILS_EPL_Pos) +#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ +#define CAN_ILS_EWL (0x1u << CAN_ILS_EWL_Pos) +#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ +#define CAN_ILS_BOL (0x1u << CAN_ILS_BOL_Pos) +#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ +#define CAN_ILS_WDIL (0x1u << CAN_ILS_WDIL_Pos) +#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ +#define CAN_ILS_PEAL (0x1u << CAN_ILS_PEAL_Pos) +#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ +#define CAN_ILS_PEDL (0x1u << CAN_ILS_PEDL_Pos) +#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ +#define CAN_ILS_ARAL (0x1u << CAN_ILS_ARAL_Pos) +#define CAN_ILS_MASK 0x3FFFFFFFu /**< \brief (CAN_ILS) MASK Register */ + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ + uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ +#define CAN_ILE_RESETVALUE 0x00000000u /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ + +#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ +#define CAN_ILE_EINT0 (0x1u << CAN_ILE_EINT0_Pos) +#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ +#define CAN_ILE_EINT1 (0x1u << CAN_ILE_EINT1_Pos) +#define CAN_ILE_MASK 0x00000003u /**< \brief (CAN_ILE) MASK Register */ + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ + uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ + uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ + uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_GFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ +#define CAN_GFC_RESETVALUE 0x00000000u /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ + +#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ +#define CAN_GFC_RRFE (0x1u << CAN_GFC_RRFE_Pos) +#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ +#define CAN_GFC_RRFS (0x1u << CAN_GFC_RRFS_Pos) +#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ +#define CAN_GFC_ANFE_Msk (0x3u << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) +#define CAN_GFC_ANFE_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ +#define CAN_GFC_ANFS_Msk (0x3u << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) +#define CAN_GFC_ANFS_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_MASK 0x0000003Fu /**< \brief (CAN_GFC) MASK Register */ + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ + uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ +#define CAN_SIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ + +#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ +#define CAN_SIDFC_FLSSA_Msk (0xFFFFu << CAN_SIDFC_FLSSA_Pos) +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) +#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ +#define CAN_SIDFC_LSS_Msk (0xFFu << CAN_SIDFC_LSS_Pos) +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) +#define CAN_SIDFC_MASK 0x00FFFFFFu /**< \brief (CAN_SIDFC) MASK Register */ + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ + uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ +#define CAN_XIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ + +#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ +#define CAN_XIDFC_FLESA_Msk (0xFFFFu << CAN_XIDFC_FLESA_Pos) +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) +#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ +#define CAN_XIDFC_LSE_Msk (0x7Fu << CAN_XIDFC_LSE_Pos) +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) +#define CAN_XIDFC_MASK 0x007FFFFFu /**< \brief (CAN_XIDFC) MASK Register */ + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ + uint32_t :3; /*!< bit: 29..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDAM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ +#define CAN_XIDAM_RESETVALUE 0x1FFFFFFFu /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ + +#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ +#define CAN_XIDAM_EIDM_Msk (0x1FFFFFFFu << CAN_XIDAM_EIDM_Pos) +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) +#define CAN_XIDAM_MASK 0x1FFFFFFFu /**< \brief (CAN_XIDAM) MASK Register */ + +/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ + uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ + uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ + uint32_t FLST:1; /*!< bit: 15 Filter List */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_HPMS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ +#define CAN_HPMS_RESETVALUE 0x00000000u /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ + +#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ +#define CAN_HPMS_BIDX_Msk (0x3Fu << CAN_HPMS_BIDX_Pos) +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) +#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ +#define CAN_HPMS_MSI_Msk (0x3u << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) +#define CAN_HPMS_MSI_NONE_Val 0x0u /**< \brief (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val 0x1u /**< \brief (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val 0x2u /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val 0x3u /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ +#define CAN_HPMS_FIDX_Msk (0x7Fu << CAN_HPMS_FIDX_Pos) +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) +#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ +#define CAN_HPMS_FLST (0x1u << CAN_HPMS_FLST_Pos) +#define CAN_HPMS_MASK 0x0000FFFFu /**< \brief (CAN_HPMS) MASK Register */ + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND0:1; /*!< bit: 0 New Data 0 */ + uint32_t ND1:1; /*!< bit: 1 New Data 1 */ + uint32_t ND2:1; /*!< bit: 2 New Data 2 */ + uint32_t ND3:1; /*!< bit: 3 New Data 3 */ + uint32_t ND4:1; /*!< bit: 4 New Data 4 */ + uint32_t ND5:1; /*!< bit: 5 New Data 5 */ + uint32_t ND6:1; /*!< bit: 6 New Data 6 */ + uint32_t ND7:1; /*!< bit: 7 New Data 7 */ + uint32_t ND8:1; /*!< bit: 8 New Data 8 */ + uint32_t ND9:1; /*!< bit: 9 New Data 9 */ + uint32_t ND10:1; /*!< bit: 10 New Data 10 */ + uint32_t ND11:1; /*!< bit: 11 New Data 11 */ + uint32_t ND12:1; /*!< bit: 12 New Data 12 */ + uint32_t ND13:1; /*!< bit: 13 New Data 13 */ + uint32_t ND14:1; /*!< bit: 14 New Data 14 */ + uint32_t ND15:1; /*!< bit: 15 New Data 15 */ + uint32_t ND16:1; /*!< bit: 16 New Data 16 */ + uint32_t ND17:1; /*!< bit: 17 New Data 17 */ + uint32_t ND18:1; /*!< bit: 18 New Data 18 */ + uint32_t ND19:1; /*!< bit: 19 New Data 19 */ + uint32_t ND20:1; /*!< bit: 20 New Data 20 */ + uint32_t ND21:1; /*!< bit: 21 New Data 21 */ + uint32_t ND22:1; /*!< bit: 22 New Data 22 */ + uint32_t ND23:1; /*!< bit: 23 New Data 23 */ + uint32_t ND24:1; /*!< bit: 24 New Data 24 */ + uint32_t ND25:1; /*!< bit: 25 New Data 25 */ + uint32_t ND26:1; /*!< bit: 26 New Data 26 */ + uint32_t ND27:1; /*!< bit: 27 New Data 27 */ + uint32_t ND28:1; /*!< bit: 28 New Data 28 */ + uint32_t ND29:1; /*!< bit: 29 New Data 29 */ + uint32_t ND30:1; /*!< bit: 30 New Data 30 */ + uint32_t ND31:1; /*!< bit: 31 New Data 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ +#define CAN_NDAT1_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ + +#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ +#define CAN_NDAT1_ND0 (0x1u << CAN_NDAT1_ND0_Pos) +#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ +#define CAN_NDAT1_ND1 (0x1u << CAN_NDAT1_ND1_Pos) +#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ +#define CAN_NDAT1_ND2 (0x1u << CAN_NDAT1_ND2_Pos) +#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ +#define CAN_NDAT1_ND3 (0x1u << CAN_NDAT1_ND3_Pos) +#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ +#define CAN_NDAT1_ND4 (0x1u << CAN_NDAT1_ND4_Pos) +#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ +#define CAN_NDAT1_ND5 (0x1u << CAN_NDAT1_ND5_Pos) +#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ +#define CAN_NDAT1_ND6 (0x1u << CAN_NDAT1_ND6_Pos) +#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ +#define CAN_NDAT1_ND7 (0x1u << CAN_NDAT1_ND7_Pos) +#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ +#define CAN_NDAT1_ND8 (0x1u << CAN_NDAT1_ND8_Pos) +#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ +#define CAN_NDAT1_ND9 (0x1u << CAN_NDAT1_ND9_Pos) +#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ +#define CAN_NDAT1_ND10 (0x1u << CAN_NDAT1_ND10_Pos) +#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ +#define CAN_NDAT1_ND11 (0x1u << CAN_NDAT1_ND11_Pos) +#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ +#define CAN_NDAT1_ND12 (0x1u << CAN_NDAT1_ND12_Pos) +#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ +#define CAN_NDAT1_ND13 (0x1u << CAN_NDAT1_ND13_Pos) +#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ +#define CAN_NDAT1_ND14 (0x1u << CAN_NDAT1_ND14_Pos) +#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ +#define CAN_NDAT1_ND15 (0x1u << CAN_NDAT1_ND15_Pos) +#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ +#define CAN_NDAT1_ND16 (0x1u << CAN_NDAT1_ND16_Pos) +#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ +#define CAN_NDAT1_ND17 (0x1u << CAN_NDAT1_ND17_Pos) +#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ +#define CAN_NDAT1_ND18 (0x1u << CAN_NDAT1_ND18_Pos) +#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ +#define CAN_NDAT1_ND19 (0x1u << CAN_NDAT1_ND19_Pos) +#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ +#define CAN_NDAT1_ND20 (0x1u << CAN_NDAT1_ND20_Pos) +#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ +#define CAN_NDAT1_ND21 (0x1u << CAN_NDAT1_ND21_Pos) +#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ +#define CAN_NDAT1_ND22 (0x1u << CAN_NDAT1_ND22_Pos) +#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ +#define CAN_NDAT1_ND23 (0x1u << CAN_NDAT1_ND23_Pos) +#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ +#define CAN_NDAT1_ND24 (0x1u << CAN_NDAT1_ND24_Pos) +#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ +#define CAN_NDAT1_ND25 (0x1u << CAN_NDAT1_ND25_Pos) +#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ +#define CAN_NDAT1_ND26 (0x1u << CAN_NDAT1_ND26_Pos) +#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ +#define CAN_NDAT1_ND27 (0x1u << CAN_NDAT1_ND27_Pos) +#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ +#define CAN_NDAT1_ND28 (0x1u << CAN_NDAT1_ND28_Pos) +#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ +#define CAN_NDAT1_ND29 (0x1u << CAN_NDAT1_ND29_Pos) +#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ +#define CAN_NDAT1_ND30 (0x1u << CAN_NDAT1_ND30_Pos) +#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ +#define CAN_NDAT1_ND31 (0x1u << CAN_NDAT1_ND31_Pos) +#define CAN_NDAT1_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT1) MASK Register */ + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND32:1; /*!< bit: 0 New Data 32 */ + uint32_t ND33:1; /*!< bit: 1 New Data 33 */ + uint32_t ND34:1; /*!< bit: 2 New Data 34 */ + uint32_t ND35:1; /*!< bit: 3 New Data 35 */ + uint32_t ND36:1; /*!< bit: 4 New Data 36 */ + uint32_t ND37:1; /*!< bit: 5 New Data 37 */ + uint32_t ND38:1; /*!< bit: 6 New Data 38 */ + uint32_t ND39:1; /*!< bit: 7 New Data 39 */ + uint32_t ND40:1; /*!< bit: 8 New Data 40 */ + uint32_t ND41:1; /*!< bit: 9 New Data 41 */ + uint32_t ND42:1; /*!< bit: 10 New Data 42 */ + uint32_t ND43:1; /*!< bit: 11 New Data 43 */ + uint32_t ND44:1; /*!< bit: 12 New Data 44 */ + uint32_t ND45:1; /*!< bit: 13 New Data 45 */ + uint32_t ND46:1; /*!< bit: 14 New Data 46 */ + uint32_t ND47:1; /*!< bit: 15 New Data 47 */ + uint32_t ND48:1; /*!< bit: 16 New Data 48 */ + uint32_t ND49:1; /*!< bit: 17 New Data 49 */ + uint32_t ND50:1; /*!< bit: 18 New Data 50 */ + uint32_t ND51:1; /*!< bit: 19 New Data 51 */ + uint32_t ND52:1; /*!< bit: 20 New Data 52 */ + uint32_t ND53:1; /*!< bit: 21 New Data 53 */ + uint32_t ND54:1; /*!< bit: 22 New Data 54 */ + uint32_t ND55:1; /*!< bit: 23 New Data 55 */ + uint32_t ND56:1; /*!< bit: 24 New Data 56 */ + uint32_t ND57:1; /*!< bit: 25 New Data 57 */ + uint32_t ND58:1; /*!< bit: 26 New Data 58 */ + uint32_t ND59:1; /*!< bit: 27 New Data 59 */ + uint32_t ND60:1; /*!< bit: 28 New Data 60 */ + uint32_t ND61:1; /*!< bit: 29 New Data 61 */ + uint32_t ND62:1; /*!< bit: 30 New Data 62 */ + uint32_t ND63:1; /*!< bit: 31 New Data 63 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ +#define CAN_NDAT2_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ + +#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ +#define CAN_NDAT2_ND32 (0x1u << CAN_NDAT2_ND32_Pos) +#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ +#define CAN_NDAT2_ND33 (0x1u << CAN_NDAT2_ND33_Pos) +#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ +#define CAN_NDAT2_ND34 (0x1u << CAN_NDAT2_ND34_Pos) +#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ +#define CAN_NDAT2_ND35 (0x1u << CAN_NDAT2_ND35_Pos) +#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ +#define CAN_NDAT2_ND36 (0x1u << CAN_NDAT2_ND36_Pos) +#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ +#define CAN_NDAT2_ND37 (0x1u << CAN_NDAT2_ND37_Pos) +#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ +#define CAN_NDAT2_ND38 (0x1u << CAN_NDAT2_ND38_Pos) +#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ +#define CAN_NDAT2_ND39 (0x1u << CAN_NDAT2_ND39_Pos) +#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ +#define CAN_NDAT2_ND40 (0x1u << CAN_NDAT2_ND40_Pos) +#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ +#define CAN_NDAT2_ND41 (0x1u << CAN_NDAT2_ND41_Pos) +#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ +#define CAN_NDAT2_ND42 (0x1u << CAN_NDAT2_ND42_Pos) +#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ +#define CAN_NDAT2_ND43 (0x1u << CAN_NDAT2_ND43_Pos) +#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ +#define CAN_NDAT2_ND44 (0x1u << CAN_NDAT2_ND44_Pos) +#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ +#define CAN_NDAT2_ND45 (0x1u << CAN_NDAT2_ND45_Pos) +#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ +#define CAN_NDAT2_ND46 (0x1u << CAN_NDAT2_ND46_Pos) +#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ +#define CAN_NDAT2_ND47 (0x1u << CAN_NDAT2_ND47_Pos) +#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ +#define CAN_NDAT2_ND48 (0x1u << CAN_NDAT2_ND48_Pos) +#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ +#define CAN_NDAT2_ND49 (0x1u << CAN_NDAT2_ND49_Pos) +#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ +#define CAN_NDAT2_ND50 (0x1u << CAN_NDAT2_ND50_Pos) +#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ +#define CAN_NDAT2_ND51 (0x1u << CAN_NDAT2_ND51_Pos) +#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ +#define CAN_NDAT2_ND52 (0x1u << CAN_NDAT2_ND52_Pos) +#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ +#define CAN_NDAT2_ND53 (0x1u << CAN_NDAT2_ND53_Pos) +#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ +#define CAN_NDAT2_ND54 (0x1u << CAN_NDAT2_ND54_Pos) +#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ +#define CAN_NDAT2_ND55 (0x1u << CAN_NDAT2_ND55_Pos) +#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ +#define CAN_NDAT2_ND56 (0x1u << CAN_NDAT2_ND56_Pos) +#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ +#define CAN_NDAT2_ND57 (0x1u << CAN_NDAT2_ND57_Pos) +#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ +#define CAN_NDAT2_ND58 (0x1u << CAN_NDAT2_ND58_Pos) +#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ +#define CAN_NDAT2_ND59 (0x1u << CAN_NDAT2_ND59_Pos) +#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ +#define CAN_NDAT2_ND60 (0x1u << CAN_NDAT2_ND60_Pos) +#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ +#define CAN_NDAT2_ND61 (0x1u << CAN_NDAT2_ND61_Pos) +#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ +#define CAN_NDAT2_ND62 (0x1u << CAN_NDAT2_ND62_Pos) +#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ +#define CAN_NDAT2_ND63 (0x1u << CAN_NDAT2_ND63_Pos) +#define CAN_NDAT2_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT2) MASK Register */ + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ + uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ + uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ +#define CAN_RXF0C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ + +#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ +#define CAN_RXF0C_F0SA_Msk (0xFFFFu << CAN_RXF0C_F0SA_Pos) +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) +#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ +#define CAN_RXF0C_F0S_Msk (0x7Fu << CAN_RXF0C_F0S_Pos) +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) +#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ +#define CAN_RXF0C_F0WM_Msk (0x7Fu << CAN_RXF0C_F0WM_Pos) +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) +#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ +#define CAN_RXF0C_F0OM (0x1u << CAN_RXF0C_F0OM_Pos) +#define CAN_RXF0C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF0C) MASK Register */ + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ +#define CAN_RXF0S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ + +#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ +#define CAN_RXF0S_F0FL_Msk (0x7Fu << CAN_RXF0S_F0FL_Pos) +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) +#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ +#define CAN_RXF0S_F0GI_Msk (0x3Fu << CAN_RXF0S_F0GI_Pos) +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) +#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ +#define CAN_RXF0S_F0PI_Msk (0x3Fu << CAN_RXF0S_F0PI_Pos) +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) +#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ +#define CAN_RXF0S_F0F (0x1u << CAN_RXF0S_F0F_Pos) +#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ +#define CAN_RXF0S_RF0L (0x1u << CAN_RXF0S_RF0L_Pos) +#define CAN_RXF0S_MASK 0x033F3F7Fu /**< \brief (CAN_RXF0S) MASK Register */ + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ +#define CAN_RXF0A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ + +#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ +#define CAN_RXF0A_F0AI_Msk (0x3Fu << CAN_RXF0A_F0AI_Pos) +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) +#define CAN_RXF0A_MASK 0x0000003Fu /**< \brief (CAN_RXF0A) MASK Register */ + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ +#define CAN_RXBC_RESETVALUE 0x00000000u /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ + +#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ +#define CAN_RXBC_RBSA_Msk (0xFFFFu << CAN_RXBC_RBSA_Pos) +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) +#define CAN_RXBC_MASK 0x0000FFFFu /**< \brief (CAN_RXBC) MASK Register */ + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ + uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ + uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ +#define CAN_RXF1C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ + +#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ +#define CAN_RXF1C_F1SA_Msk (0xFFFFu << CAN_RXF1C_F1SA_Pos) +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) +#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ +#define CAN_RXF1C_F1S_Msk (0x7Fu << CAN_RXF1C_F1S_Pos) +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) +#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ +#define CAN_RXF1C_F1WM_Msk (0x7Fu << CAN_RXF1C_F1WM_Pos) +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) +#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ +#define CAN_RXF1C_F1OM (0x1u << CAN_RXF1C_F1OM_Pos) +#define CAN_RXF1C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF1C) MASK Register */ + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ + uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ + uint32_t :4; /*!< bit: 26..29 Reserved */ + uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ +#define CAN_RXF1S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ + +#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ +#define CAN_RXF1S_F1FL_Msk (0x7Fu << CAN_RXF1S_F1FL_Pos) +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) +#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ +#define CAN_RXF1S_F1GI_Msk (0x3Fu << CAN_RXF1S_F1GI_Pos) +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) +#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ +#define CAN_RXF1S_F1PI_Msk (0x3Fu << CAN_RXF1S_F1PI_Pos) +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) +#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ +#define CAN_RXF1S_F1F (0x1u << CAN_RXF1S_F1F_Pos) +#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ +#define CAN_RXF1S_RF1L (0x1u << CAN_RXF1S_RF1L_Pos) +#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ +#define CAN_RXF1S_DMS_Msk (0x3u << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) +#define CAN_RXF1S_DMS_IDLE_Val 0x0u /**< \brief (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val 0x1u /**< \brief (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val 0x2u /**< \brief (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val 0x3u /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_MASK 0xC33F3F7Fu /**< \brief (CAN_RXF1S) MASK Register */ + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ +#define CAN_RXF1A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ + +#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ +#define CAN_RXF1A_F1AI_Msk (0x3Fu << CAN_RXF1A_F1AI_Pos) +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) +#define CAN_RXF1A_MASK 0x0000003Fu /**< \brief (CAN_RXF1A) MASK Register */ + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ +#define CAN_RXESC_RESETVALUE 0x00000000u /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ + +#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ +#define CAN_RXESC_F0DS_Msk (0x7u << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) +#define CAN_RXESC_F0DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ +#define CAN_RXESC_F1DS_Msk (0x7u << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) +#define CAN_RXESC_F1DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ +#define CAN_RXESC_RBDS_Msk (0x7u << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) +#define CAN_RXESC_RBDS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_MASK 0x00000777u /**< \brief (CAN_RXESC) MASK Register */ + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ + uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ + uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ +#define CAN_TXBC_RESETVALUE 0x00000000u /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ + +#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ +#define CAN_TXBC_TBSA_Msk (0xFFFFu << CAN_TXBC_TBSA_Pos) +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) +#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ +#define CAN_TXBC_NDTB_Msk (0x3Fu << CAN_TXBC_NDTB_Pos) +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) +#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ +#define CAN_TXBC_TFQS_Msk (0x3Fu << CAN_TXBC_TFQS_Pos) +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) +#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ +#define CAN_TXBC_TFQM (0x1u << CAN_TXBC_TFQM_Pos) +#define CAN_TXBC_MASK 0x7F3FFFFFu /**< \brief (CAN_TXBC) MASK Register */ + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ + uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXFQS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ +#define CAN_TXFQS_RESETVALUE 0x00000000u /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ + +#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ +#define CAN_TXFQS_TFFL_Msk (0x3Fu << CAN_TXFQS_TFFL_Pos) +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) +#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ +#define CAN_TXFQS_TFGI_Msk (0x1Fu << CAN_TXFQS_TFGI_Pos) +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) +#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ +#define CAN_TXFQS_TFQPI_Msk (0x1Fu << CAN_TXFQS_TFQPI_Pos) +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) +#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ +#define CAN_TXFQS_TFQF (0x1u << CAN_TXFQS_TFQF_Pos) +#define CAN_TXFQS_MASK 0x003F1F3Fu /**< \brief (CAN_TXFQS) MASK Register */ + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ +#define CAN_TXESC_RESETVALUE 0x00000000u /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ + +#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ +#define CAN_TXESC_TBDS_Msk (0x7u << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) +#define CAN_TXESC_TBDS_DATA8_Val 0x0u /**< \brief (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val 0x1u /**< \brief (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val 0x2u /**< \brief (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val 0x3u /**< \brief (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val 0x4u /**< \brief (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val 0x5u /**< \brief (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val 0x6u /**< \brief (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val 0x7u /**< \brief (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_MASK 0x00000007u /**< \brief (CAN_TXESC) MASK Register */ + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ + uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ + uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ + uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ + uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ + uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ + uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ + uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ + uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ + uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ + uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ + uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ + uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ + uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ + uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ + uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ + uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ + uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ + uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ + uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ + uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ + uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ + uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ + uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ + uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ + uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ + uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ + uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ + uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ + uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ + uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ + uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBRP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ +#define CAN_TXBRP_RESETVALUE 0x00000000u /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ + +#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ +#define CAN_TXBRP_TRP0 (0x1u << CAN_TXBRP_TRP0_Pos) +#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ +#define CAN_TXBRP_TRP1 (0x1u << CAN_TXBRP_TRP1_Pos) +#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ +#define CAN_TXBRP_TRP2 (0x1u << CAN_TXBRP_TRP2_Pos) +#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ +#define CAN_TXBRP_TRP3 (0x1u << CAN_TXBRP_TRP3_Pos) +#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ +#define CAN_TXBRP_TRP4 (0x1u << CAN_TXBRP_TRP4_Pos) +#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ +#define CAN_TXBRP_TRP5 (0x1u << CAN_TXBRP_TRP5_Pos) +#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ +#define CAN_TXBRP_TRP6 (0x1u << CAN_TXBRP_TRP6_Pos) +#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ +#define CAN_TXBRP_TRP7 (0x1u << CAN_TXBRP_TRP7_Pos) +#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ +#define CAN_TXBRP_TRP8 (0x1u << CAN_TXBRP_TRP8_Pos) +#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ +#define CAN_TXBRP_TRP9 (0x1u << CAN_TXBRP_TRP9_Pos) +#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ +#define CAN_TXBRP_TRP10 (0x1u << CAN_TXBRP_TRP10_Pos) +#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ +#define CAN_TXBRP_TRP11 (0x1u << CAN_TXBRP_TRP11_Pos) +#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ +#define CAN_TXBRP_TRP12 (0x1u << CAN_TXBRP_TRP12_Pos) +#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ +#define CAN_TXBRP_TRP13 (0x1u << CAN_TXBRP_TRP13_Pos) +#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ +#define CAN_TXBRP_TRP14 (0x1u << CAN_TXBRP_TRP14_Pos) +#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ +#define CAN_TXBRP_TRP15 (0x1u << CAN_TXBRP_TRP15_Pos) +#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ +#define CAN_TXBRP_TRP16 (0x1u << CAN_TXBRP_TRP16_Pos) +#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ +#define CAN_TXBRP_TRP17 (0x1u << CAN_TXBRP_TRP17_Pos) +#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ +#define CAN_TXBRP_TRP18 (0x1u << CAN_TXBRP_TRP18_Pos) +#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ +#define CAN_TXBRP_TRP19 (0x1u << CAN_TXBRP_TRP19_Pos) +#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ +#define CAN_TXBRP_TRP20 (0x1u << CAN_TXBRP_TRP20_Pos) +#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ +#define CAN_TXBRP_TRP21 (0x1u << CAN_TXBRP_TRP21_Pos) +#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ +#define CAN_TXBRP_TRP22 (0x1u << CAN_TXBRP_TRP22_Pos) +#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ +#define CAN_TXBRP_TRP23 (0x1u << CAN_TXBRP_TRP23_Pos) +#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ +#define CAN_TXBRP_TRP24 (0x1u << CAN_TXBRP_TRP24_Pos) +#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ +#define CAN_TXBRP_TRP25 (0x1u << CAN_TXBRP_TRP25_Pos) +#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ +#define CAN_TXBRP_TRP26 (0x1u << CAN_TXBRP_TRP26_Pos) +#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ +#define CAN_TXBRP_TRP27 (0x1u << CAN_TXBRP_TRP27_Pos) +#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ +#define CAN_TXBRP_TRP28 (0x1u << CAN_TXBRP_TRP28_Pos) +#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ +#define CAN_TXBRP_TRP29 (0x1u << CAN_TXBRP_TRP29_Pos) +#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ +#define CAN_TXBRP_TRP30 (0x1u << CAN_TXBRP_TRP30_Pos) +#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ +#define CAN_TXBRP_TRP31 (0x1u << CAN_TXBRP_TRP31_Pos) +#define CAN_TXBRP_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBRP) MASK Register */ + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ + uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ + uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ + uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ + uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ + uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ + uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ + uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ + uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ + uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ + uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ + uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ + uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ + uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ + uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ + uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ + uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ + uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ + uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ + uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ + uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ + uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ + uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ + uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ + uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ + uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ + uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ + uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ + uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ + uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ + uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ + uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ +#define CAN_TXBAR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ + +#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ +#define CAN_TXBAR_AR0 (0x1u << CAN_TXBAR_AR0_Pos) +#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ +#define CAN_TXBAR_AR1 (0x1u << CAN_TXBAR_AR1_Pos) +#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ +#define CAN_TXBAR_AR2 (0x1u << CAN_TXBAR_AR2_Pos) +#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ +#define CAN_TXBAR_AR3 (0x1u << CAN_TXBAR_AR3_Pos) +#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ +#define CAN_TXBAR_AR4 (0x1u << CAN_TXBAR_AR4_Pos) +#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ +#define CAN_TXBAR_AR5 (0x1u << CAN_TXBAR_AR5_Pos) +#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ +#define CAN_TXBAR_AR6 (0x1u << CAN_TXBAR_AR6_Pos) +#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ +#define CAN_TXBAR_AR7 (0x1u << CAN_TXBAR_AR7_Pos) +#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ +#define CAN_TXBAR_AR8 (0x1u << CAN_TXBAR_AR8_Pos) +#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ +#define CAN_TXBAR_AR9 (0x1u << CAN_TXBAR_AR9_Pos) +#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ +#define CAN_TXBAR_AR10 (0x1u << CAN_TXBAR_AR10_Pos) +#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ +#define CAN_TXBAR_AR11 (0x1u << CAN_TXBAR_AR11_Pos) +#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ +#define CAN_TXBAR_AR12 (0x1u << CAN_TXBAR_AR12_Pos) +#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ +#define CAN_TXBAR_AR13 (0x1u << CAN_TXBAR_AR13_Pos) +#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ +#define CAN_TXBAR_AR14 (0x1u << CAN_TXBAR_AR14_Pos) +#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ +#define CAN_TXBAR_AR15 (0x1u << CAN_TXBAR_AR15_Pos) +#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ +#define CAN_TXBAR_AR16 (0x1u << CAN_TXBAR_AR16_Pos) +#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ +#define CAN_TXBAR_AR17 (0x1u << CAN_TXBAR_AR17_Pos) +#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ +#define CAN_TXBAR_AR18 (0x1u << CAN_TXBAR_AR18_Pos) +#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ +#define CAN_TXBAR_AR19 (0x1u << CAN_TXBAR_AR19_Pos) +#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ +#define CAN_TXBAR_AR20 (0x1u << CAN_TXBAR_AR20_Pos) +#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ +#define CAN_TXBAR_AR21 (0x1u << CAN_TXBAR_AR21_Pos) +#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ +#define CAN_TXBAR_AR22 (0x1u << CAN_TXBAR_AR22_Pos) +#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ +#define CAN_TXBAR_AR23 (0x1u << CAN_TXBAR_AR23_Pos) +#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ +#define CAN_TXBAR_AR24 (0x1u << CAN_TXBAR_AR24_Pos) +#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ +#define CAN_TXBAR_AR25 (0x1u << CAN_TXBAR_AR25_Pos) +#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ +#define CAN_TXBAR_AR26 (0x1u << CAN_TXBAR_AR26_Pos) +#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ +#define CAN_TXBAR_AR27 (0x1u << CAN_TXBAR_AR27_Pos) +#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ +#define CAN_TXBAR_AR28 (0x1u << CAN_TXBAR_AR28_Pos) +#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ +#define CAN_TXBAR_AR29 (0x1u << CAN_TXBAR_AR29_Pos) +#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ +#define CAN_TXBAR_AR30 (0x1u << CAN_TXBAR_AR30_Pos) +#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ +#define CAN_TXBAR_AR31 (0x1u << CAN_TXBAR_AR31_Pos) +#define CAN_TXBAR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBAR) MASK Register */ + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ + uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ + uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ + uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ + uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ + uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ + uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ + uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ + uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ + uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ + uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ + uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ + uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ + uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ + uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ + uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ + uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ + uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ + uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ + uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ + uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ + uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ + uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ + uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ + uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ + uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ + uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ + uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ + uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ + uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ + uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ + uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ +#define CAN_TXBCR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ + +#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ +#define CAN_TXBCR_CR0 (0x1u << CAN_TXBCR_CR0_Pos) +#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ +#define CAN_TXBCR_CR1 (0x1u << CAN_TXBCR_CR1_Pos) +#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ +#define CAN_TXBCR_CR2 (0x1u << CAN_TXBCR_CR2_Pos) +#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ +#define CAN_TXBCR_CR3 (0x1u << CAN_TXBCR_CR3_Pos) +#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ +#define CAN_TXBCR_CR4 (0x1u << CAN_TXBCR_CR4_Pos) +#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ +#define CAN_TXBCR_CR5 (0x1u << CAN_TXBCR_CR5_Pos) +#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ +#define CAN_TXBCR_CR6 (0x1u << CAN_TXBCR_CR6_Pos) +#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ +#define CAN_TXBCR_CR7 (0x1u << CAN_TXBCR_CR7_Pos) +#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ +#define CAN_TXBCR_CR8 (0x1u << CAN_TXBCR_CR8_Pos) +#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ +#define CAN_TXBCR_CR9 (0x1u << CAN_TXBCR_CR9_Pos) +#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ +#define CAN_TXBCR_CR10 (0x1u << CAN_TXBCR_CR10_Pos) +#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ +#define CAN_TXBCR_CR11 (0x1u << CAN_TXBCR_CR11_Pos) +#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ +#define CAN_TXBCR_CR12 (0x1u << CAN_TXBCR_CR12_Pos) +#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ +#define CAN_TXBCR_CR13 (0x1u << CAN_TXBCR_CR13_Pos) +#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ +#define CAN_TXBCR_CR14 (0x1u << CAN_TXBCR_CR14_Pos) +#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ +#define CAN_TXBCR_CR15 (0x1u << CAN_TXBCR_CR15_Pos) +#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ +#define CAN_TXBCR_CR16 (0x1u << CAN_TXBCR_CR16_Pos) +#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ +#define CAN_TXBCR_CR17 (0x1u << CAN_TXBCR_CR17_Pos) +#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ +#define CAN_TXBCR_CR18 (0x1u << CAN_TXBCR_CR18_Pos) +#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ +#define CAN_TXBCR_CR19 (0x1u << CAN_TXBCR_CR19_Pos) +#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ +#define CAN_TXBCR_CR20 (0x1u << CAN_TXBCR_CR20_Pos) +#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ +#define CAN_TXBCR_CR21 (0x1u << CAN_TXBCR_CR21_Pos) +#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ +#define CAN_TXBCR_CR22 (0x1u << CAN_TXBCR_CR22_Pos) +#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ +#define CAN_TXBCR_CR23 (0x1u << CAN_TXBCR_CR23_Pos) +#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ +#define CAN_TXBCR_CR24 (0x1u << CAN_TXBCR_CR24_Pos) +#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ +#define CAN_TXBCR_CR25 (0x1u << CAN_TXBCR_CR25_Pos) +#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ +#define CAN_TXBCR_CR26 (0x1u << CAN_TXBCR_CR26_Pos) +#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ +#define CAN_TXBCR_CR27 (0x1u << CAN_TXBCR_CR27_Pos) +#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ +#define CAN_TXBCR_CR28 (0x1u << CAN_TXBCR_CR28_Pos) +#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ +#define CAN_TXBCR_CR29 (0x1u << CAN_TXBCR_CR29_Pos) +#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ +#define CAN_TXBCR_CR30 (0x1u << CAN_TXBCR_CR30_Pos) +#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ +#define CAN_TXBCR_CR31 (0x1u << CAN_TXBCR_CR31_Pos) +#define CAN_TXBCR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCR) MASK Register */ + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ + uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ + uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ + uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ + uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ + uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ + uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ + uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ + uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ + uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ + uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ + uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ + uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ + uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ + uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ + uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ + uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ + uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ + uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ + uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ + uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ + uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ + uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ + uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ + uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ + uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ + uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ + uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ + uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ + uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ + uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ + uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTO_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ +#define CAN_TXBTO_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ + +#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ +#define CAN_TXBTO_TO0 (0x1u << CAN_TXBTO_TO0_Pos) +#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ +#define CAN_TXBTO_TO1 (0x1u << CAN_TXBTO_TO1_Pos) +#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ +#define CAN_TXBTO_TO2 (0x1u << CAN_TXBTO_TO2_Pos) +#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ +#define CAN_TXBTO_TO3 (0x1u << CAN_TXBTO_TO3_Pos) +#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ +#define CAN_TXBTO_TO4 (0x1u << CAN_TXBTO_TO4_Pos) +#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ +#define CAN_TXBTO_TO5 (0x1u << CAN_TXBTO_TO5_Pos) +#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ +#define CAN_TXBTO_TO6 (0x1u << CAN_TXBTO_TO6_Pos) +#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ +#define CAN_TXBTO_TO7 (0x1u << CAN_TXBTO_TO7_Pos) +#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ +#define CAN_TXBTO_TO8 (0x1u << CAN_TXBTO_TO8_Pos) +#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ +#define CAN_TXBTO_TO9 (0x1u << CAN_TXBTO_TO9_Pos) +#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ +#define CAN_TXBTO_TO10 (0x1u << CAN_TXBTO_TO10_Pos) +#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ +#define CAN_TXBTO_TO11 (0x1u << CAN_TXBTO_TO11_Pos) +#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ +#define CAN_TXBTO_TO12 (0x1u << CAN_TXBTO_TO12_Pos) +#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ +#define CAN_TXBTO_TO13 (0x1u << CAN_TXBTO_TO13_Pos) +#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ +#define CAN_TXBTO_TO14 (0x1u << CAN_TXBTO_TO14_Pos) +#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ +#define CAN_TXBTO_TO15 (0x1u << CAN_TXBTO_TO15_Pos) +#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ +#define CAN_TXBTO_TO16 (0x1u << CAN_TXBTO_TO16_Pos) +#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ +#define CAN_TXBTO_TO17 (0x1u << CAN_TXBTO_TO17_Pos) +#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ +#define CAN_TXBTO_TO18 (0x1u << CAN_TXBTO_TO18_Pos) +#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ +#define CAN_TXBTO_TO19 (0x1u << CAN_TXBTO_TO19_Pos) +#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ +#define CAN_TXBTO_TO20 (0x1u << CAN_TXBTO_TO20_Pos) +#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ +#define CAN_TXBTO_TO21 (0x1u << CAN_TXBTO_TO21_Pos) +#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ +#define CAN_TXBTO_TO22 (0x1u << CAN_TXBTO_TO22_Pos) +#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ +#define CAN_TXBTO_TO23 (0x1u << CAN_TXBTO_TO23_Pos) +#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ +#define CAN_TXBTO_TO24 (0x1u << CAN_TXBTO_TO24_Pos) +#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ +#define CAN_TXBTO_TO25 (0x1u << CAN_TXBTO_TO25_Pos) +#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ +#define CAN_TXBTO_TO26 (0x1u << CAN_TXBTO_TO26_Pos) +#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ +#define CAN_TXBTO_TO27 (0x1u << CAN_TXBTO_TO27_Pos) +#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ +#define CAN_TXBTO_TO28 (0x1u << CAN_TXBTO_TO28_Pos) +#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ +#define CAN_TXBTO_TO29 (0x1u << CAN_TXBTO_TO29_Pos) +#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ +#define CAN_TXBTO_TO30 (0x1u << CAN_TXBTO_TO30_Pos) +#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ +#define CAN_TXBTO_TO31 (0x1u << CAN_TXBTO_TO31_Pos) +#define CAN_TXBTO_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTO) MASK Register */ + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ + uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ + uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ + uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ + uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ + uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ + uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ + uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ + uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ + uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ + uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ + uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ + uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ + uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ + uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ + uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ + uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ + uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ + uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ + uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ + uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ + uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ + uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ + uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ + uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ + uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ + uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ + uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ + uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ + uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ + uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ + uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ +#define CAN_TXBCF_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ + +#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ +#define CAN_TXBCF_CF0 (0x1u << CAN_TXBCF_CF0_Pos) +#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ +#define CAN_TXBCF_CF1 (0x1u << CAN_TXBCF_CF1_Pos) +#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ +#define CAN_TXBCF_CF2 (0x1u << CAN_TXBCF_CF2_Pos) +#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ +#define CAN_TXBCF_CF3 (0x1u << CAN_TXBCF_CF3_Pos) +#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ +#define CAN_TXBCF_CF4 (0x1u << CAN_TXBCF_CF4_Pos) +#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ +#define CAN_TXBCF_CF5 (0x1u << CAN_TXBCF_CF5_Pos) +#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ +#define CAN_TXBCF_CF6 (0x1u << CAN_TXBCF_CF6_Pos) +#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ +#define CAN_TXBCF_CF7 (0x1u << CAN_TXBCF_CF7_Pos) +#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ +#define CAN_TXBCF_CF8 (0x1u << CAN_TXBCF_CF8_Pos) +#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ +#define CAN_TXBCF_CF9 (0x1u << CAN_TXBCF_CF9_Pos) +#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ +#define CAN_TXBCF_CF10 (0x1u << CAN_TXBCF_CF10_Pos) +#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ +#define CAN_TXBCF_CF11 (0x1u << CAN_TXBCF_CF11_Pos) +#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ +#define CAN_TXBCF_CF12 (0x1u << CAN_TXBCF_CF12_Pos) +#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ +#define CAN_TXBCF_CF13 (0x1u << CAN_TXBCF_CF13_Pos) +#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ +#define CAN_TXBCF_CF14 (0x1u << CAN_TXBCF_CF14_Pos) +#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ +#define CAN_TXBCF_CF15 (0x1u << CAN_TXBCF_CF15_Pos) +#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ +#define CAN_TXBCF_CF16 (0x1u << CAN_TXBCF_CF16_Pos) +#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ +#define CAN_TXBCF_CF17 (0x1u << CAN_TXBCF_CF17_Pos) +#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ +#define CAN_TXBCF_CF18 (0x1u << CAN_TXBCF_CF18_Pos) +#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ +#define CAN_TXBCF_CF19 (0x1u << CAN_TXBCF_CF19_Pos) +#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ +#define CAN_TXBCF_CF20 (0x1u << CAN_TXBCF_CF20_Pos) +#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ +#define CAN_TXBCF_CF21 (0x1u << CAN_TXBCF_CF21_Pos) +#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ +#define CAN_TXBCF_CF22 (0x1u << CAN_TXBCF_CF22_Pos) +#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ +#define CAN_TXBCF_CF23 (0x1u << CAN_TXBCF_CF23_Pos) +#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ +#define CAN_TXBCF_CF24 (0x1u << CAN_TXBCF_CF24_Pos) +#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ +#define CAN_TXBCF_CF25 (0x1u << CAN_TXBCF_CF25_Pos) +#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ +#define CAN_TXBCF_CF26 (0x1u << CAN_TXBCF_CF26_Pos) +#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ +#define CAN_TXBCF_CF27 (0x1u << CAN_TXBCF_CF27_Pos) +#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ +#define CAN_TXBCF_CF28 (0x1u << CAN_TXBCF_CF28_Pos) +#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ +#define CAN_TXBCF_CF29 (0x1u << CAN_TXBCF_CF29_Pos) +#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ +#define CAN_TXBCF_CF30 (0x1u << CAN_TXBCF_CF30_Pos) +#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ +#define CAN_TXBCF_CF31 (0x1u << CAN_TXBCF_CF31_Pos) +#define CAN_TXBCF_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCF) MASK Register */ + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ + uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ + uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ + uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ + uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ + uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ + uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ + uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ + uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ + uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ + uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ + uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ + uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ + uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ + uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ + uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ + uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ + uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ + uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ + uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ + uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ + uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ + uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ + uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ + uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ + uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ + uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ + uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ + uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ + uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ + uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ + uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ +#define CAN_TXBTIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ + +#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ +#define CAN_TXBTIE_TIE0 (0x1u << CAN_TXBTIE_TIE0_Pos) +#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ +#define CAN_TXBTIE_TIE1 (0x1u << CAN_TXBTIE_TIE1_Pos) +#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ +#define CAN_TXBTIE_TIE2 (0x1u << CAN_TXBTIE_TIE2_Pos) +#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ +#define CAN_TXBTIE_TIE3 (0x1u << CAN_TXBTIE_TIE3_Pos) +#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ +#define CAN_TXBTIE_TIE4 (0x1u << CAN_TXBTIE_TIE4_Pos) +#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ +#define CAN_TXBTIE_TIE5 (0x1u << CAN_TXBTIE_TIE5_Pos) +#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ +#define CAN_TXBTIE_TIE6 (0x1u << CAN_TXBTIE_TIE6_Pos) +#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ +#define CAN_TXBTIE_TIE7 (0x1u << CAN_TXBTIE_TIE7_Pos) +#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ +#define CAN_TXBTIE_TIE8 (0x1u << CAN_TXBTIE_TIE8_Pos) +#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ +#define CAN_TXBTIE_TIE9 (0x1u << CAN_TXBTIE_TIE9_Pos) +#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ +#define CAN_TXBTIE_TIE10 (0x1u << CAN_TXBTIE_TIE10_Pos) +#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ +#define CAN_TXBTIE_TIE11 (0x1u << CAN_TXBTIE_TIE11_Pos) +#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ +#define CAN_TXBTIE_TIE12 (0x1u << CAN_TXBTIE_TIE12_Pos) +#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ +#define CAN_TXBTIE_TIE13 (0x1u << CAN_TXBTIE_TIE13_Pos) +#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ +#define CAN_TXBTIE_TIE14 (0x1u << CAN_TXBTIE_TIE14_Pos) +#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ +#define CAN_TXBTIE_TIE15 (0x1u << CAN_TXBTIE_TIE15_Pos) +#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ +#define CAN_TXBTIE_TIE16 (0x1u << CAN_TXBTIE_TIE16_Pos) +#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ +#define CAN_TXBTIE_TIE17 (0x1u << CAN_TXBTIE_TIE17_Pos) +#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ +#define CAN_TXBTIE_TIE18 (0x1u << CAN_TXBTIE_TIE18_Pos) +#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ +#define CAN_TXBTIE_TIE19 (0x1u << CAN_TXBTIE_TIE19_Pos) +#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ +#define CAN_TXBTIE_TIE20 (0x1u << CAN_TXBTIE_TIE20_Pos) +#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ +#define CAN_TXBTIE_TIE21 (0x1u << CAN_TXBTIE_TIE21_Pos) +#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ +#define CAN_TXBTIE_TIE22 (0x1u << CAN_TXBTIE_TIE22_Pos) +#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ +#define CAN_TXBTIE_TIE23 (0x1u << CAN_TXBTIE_TIE23_Pos) +#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ +#define CAN_TXBTIE_TIE24 (0x1u << CAN_TXBTIE_TIE24_Pos) +#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ +#define CAN_TXBTIE_TIE25 (0x1u << CAN_TXBTIE_TIE25_Pos) +#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ +#define CAN_TXBTIE_TIE26 (0x1u << CAN_TXBTIE_TIE26_Pos) +#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ +#define CAN_TXBTIE_TIE27 (0x1u << CAN_TXBTIE_TIE27_Pos) +#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ +#define CAN_TXBTIE_TIE28 (0x1u << CAN_TXBTIE_TIE28_Pos) +#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ +#define CAN_TXBTIE_TIE29 (0x1u << CAN_TXBTIE_TIE29_Pos) +#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ +#define CAN_TXBTIE_TIE30 (0x1u << CAN_TXBTIE_TIE30_Pos) +#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ +#define CAN_TXBTIE_TIE31 (0x1u << CAN_TXBTIE_TIE31_Pos) +#define CAN_TXBTIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTIE) MASK Register */ + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ + uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ + uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ + uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ + uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ + uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ + uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ + uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ + uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ + uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ + uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ + uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ + uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ + uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ + uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ + uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ + uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ + uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ + uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ + uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ + uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ + uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ + uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ + uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ + uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ + uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ + uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ + uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ + uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ + uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ + uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ + uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ +#define CAN_TXBCIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ + +#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ +#define CAN_TXBCIE_CFIE0 (0x1u << CAN_TXBCIE_CFIE0_Pos) +#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ +#define CAN_TXBCIE_CFIE1 (0x1u << CAN_TXBCIE_CFIE1_Pos) +#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ +#define CAN_TXBCIE_CFIE2 (0x1u << CAN_TXBCIE_CFIE2_Pos) +#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ +#define CAN_TXBCIE_CFIE3 (0x1u << CAN_TXBCIE_CFIE3_Pos) +#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ +#define CAN_TXBCIE_CFIE4 (0x1u << CAN_TXBCIE_CFIE4_Pos) +#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ +#define CAN_TXBCIE_CFIE5 (0x1u << CAN_TXBCIE_CFIE5_Pos) +#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ +#define CAN_TXBCIE_CFIE6 (0x1u << CAN_TXBCIE_CFIE6_Pos) +#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ +#define CAN_TXBCIE_CFIE7 (0x1u << CAN_TXBCIE_CFIE7_Pos) +#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ +#define CAN_TXBCIE_CFIE8 (0x1u << CAN_TXBCIE_CFIE8_Pos) +#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ +#define CAN_TXBCIE_CFIE9 (0x1u << CAN_TXBCIE_CFIE9_Pos) +#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ +#define CAN_TXBCIE_CFIE10 (0x1u << CAN_TXBCIE_CFIE10_Pos) +#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ +#define CAN_TXBCIE_CFIE11 (0x1u << CAN_TXBCIE_CFIE11_Pos) +#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ +#define CAN_TXBCIE_CFIE12 (0x1u << CAN_TXBCIE_CFIE12_Pos) +#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ +#define CAN_TXBCIE_CFIE13 (0x1u << CAN_TXBCIE_CFIE13_Pos) +#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ +#define CAN_TXBCIE_CFIE14 (0x1u << CAN_TXBCIE_CFIE14_Pos) +#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ +#define CAN_TXBCIE_CFIE15 (0x1u << CAN_TXBCIE_CFIE15_Pos) +#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ +#define CAN_TXBCIE_CFIE16 (0x1u << CAN_TXBCIE_CFIE16_Pos) +#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ +#define CAN_TXBCIE_CFIE17 (0x1u << CAN_TXBCIE_CFIE17_Pos) +#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ +#define CAN_TXBCIE_CFIE18 (0x1u << CAN_TXBCIE_CFIE18_Pos) +#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ +#define CAN_TXBCIE_CFIE19 (0x1u << CAN_TXBCIE_CFIE19_Pos) +#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ +#define CAN_TXBCIE_CFIE20 (0x1u << CAN_TXBCIE_CFIE20_Pos) +#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ +#define CAN_TXBCIE_CFIE21 (0x1u << CAN_TXBCIE_CFIE21_Pos) +#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ +#define CAN_TXBCIE_CFIE22 (0x1u << CAN_TXBCIE_CFIE22_Pos) +#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ +#define CAN_TXBCIE_CFIE23 (0x1u << CAN_TXBCIE_CFIE23_Pos) +#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ +#define CAN_TXBCIE_CFIE24 (0x1u << CAN_TXBCIE_CFIE24_Pos) +#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ +#define CAN_TXBCIE_CFIE25 (0x1u << CAN_TXBCIE_CFIE25_Pos) +#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ +#define CAN_TXBCIE_CFIE26 (0x1u << CAN_TXBCIE_CFIE26_Pos) +#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ +#define CAN_TXBCIE_CFIE27 (0x1u << CAN_TXBCIE_CFIE27_Pos) +#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ +#define CAN_TXBCIE_CFIE28 (0x1u << CAN_TXBCIE_CFIE28_Pos) +#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ +#define CAN_TXBCIE_CFIE29 (0x1u << CAN_TXBCIE_CFIE29_Pos) +#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ +#define CAN_TXBCIE_CFIE30 (0x1u << CAN_TXBCIE_CFIE30_Pos) +#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ +#define CAN_TXBCIE_CFIE31 (0x1u << CAN_TXBCIE_CFIE31_Pos) +#define CAN_TXBCIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCIE) MASK Register */ + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ + uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ +#define CAN_TXEFC_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ + +#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ +#define CAN_TXEFC_EFSA_Msk (0xFFFFu << CAN_TXEFC_EFSA_Pos) +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) +#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ +#define CAN_TXEFC_EFS_Msk (0x3Fu << CAN_TXEFC_EFS_Pos) +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) +#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ +#define CAN_TXEFC_EFWM_Msk (0x3Fu << CAN_TXEFC_EFWM_Pos) +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) +#define CAN_TXEFC_MASK 0x3F3FFFFFu /**< \brief (CAN_TXEFC) MASK Register */ + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ + uint32_t :3; /*!< bit: 21..23 Reserved */ + uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ +#define CAN_TXEFS_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ + +#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ +#define CAN_TXEFS_EFFL_Msk (0x3Fu << CAN_TXEFS_EFFL_Pos) +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) +#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ +#define CAN_TXEFS_EFGI_Msk (0x1Fu << CAN_TXEFS_EFGI_Pos) +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) +#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ +#define CAN_TXEFS_EFPI_Msk (0x1Fu << CAN_TXEFS_EFPI_Pos) +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) +#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ +#define CAN_TXEFS_EFF (0x1u << CAN_TXEFS_EFF_Pos) +#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ +#define CAN_TXEFS_TEFL (0x1u << CAN_TXEFS_TEFL_Pos) +#define CAN_TXEFS_MASK 0x031F1F3Fu /**< \brief (CAN_TXEFS) MASK Register */ + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ +#define CAN_TXEFA_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ + +#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ +#define CAN_TXEFA_EFAI_Msk (0x1Fu << CAN_TXEFA_EFAI_Pos) +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) +#define CAN_TXEFA_MASK 0x0000001Fu /**< \brief (CAN_TXEFA) MASK Register */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ +#define CAN_RXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ + +#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ +#define CAN_RXBE_0_ID_Msk (0x1FFFFFFFu << CAN_RXBE_0_ID_Pos) +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) +#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ +#define CAN_RXBE_0_RTR (0x1u << CAN_RXBE_0_RTR_Pos) +#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ +#define CAN_RXBE_0_XTD (0x1u << CAN_RXBE_0_XTD_Pos) +#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ +#define CAN_RXBE_0_ESI (0x1u << CAN_RXBE_0_ESI_Pos) +#define CAN_RXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_0) MASK Register */ + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ +#define CAN_RXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ + +#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ +#define CAN_RXBE_1_RXTS_Msk (0xFFFFu << CAN_RXBE_1_RXTS_Pos) +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) +#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ +#define CAN_RXBE_1_DLC_Msk (0xFu << CAN_RXBE_1_DLC_Pos) +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) +#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ +#define CAN_RXBE_1_BRS (0x1u << CAN_RXBE_1_BRS_Pos) +#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ +#define CAN_RXBE_1_FDF (0x1u << CAN_RXBE_1_FDF_Pos) +#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ +#define CAN_RXBE_1_FIDX_Msk (0x7Fu << CAN_RXBE_1_FIDX_Pos) +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) +#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ +#define CAN_RXBE_1_ANMF (0x1u << CAN_RXBE_1_ANMF_Pos) +#define CAN_RXBE_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXBE_1) MASK Register */ + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ +#define CAN_RXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ + +#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ +#define CAN_RXBE_DATA_DB0_Msk (0xFFu << CAN_RXBE_DATA_DB0_Pos) +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) +#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ +#define CAN_RXBE_DATA_DB1_Msk (0xFFu << CAN_RXBE_DATA_DB1_Pos) +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) +#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ +#define CAN_RXBE_DATA_DB2_Msk (0xFFu << CAN_RXBE_DATA_DB2_Pos) +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) +#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ +#define CAN_RXBE_DATA_DB3_Msk (0xFFu << CAN_RXBE_DATA_DB3_Pos) +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) +#define CAN_RXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_DATA) MASK Register */ + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ +#define CAN_RXF0E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ + +#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ +#define CAN_RXF0E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF0E_0_ID_Pos) +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) +#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ +#define CAN_RXF0E_0_RTR (0x1u << CAN_RXF0E_0_RTR_Pos) +#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ +#define CAN_RXF0E_0_XTD (0x1u << CAN_RXF0E_0_XTD_Pos) +#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ +#define CAN_RXF0E_0_ESI (0x1u << CAN_RXF0E_0_ESI_Pos) +#define CAN_RXF0E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_0) MASK Register */ + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ +#define CAN_RXF0E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ + +#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ +#define CAN_RXF0E_1_RXTS_Msk (0xFFFFu << CAN_RXF0E_1_RXTS_Pos) +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) +#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ +#define CAN_RXF0E_1_DLC_Msk (0xFu << CAN_RXF0E_1_DLC_Pos) +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) +#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ +#define CAN_RXF0E_1_BRS (0x1u << CAN_RXF0E_1_BRS_Pos) +#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ +#define CAN_RXF0E_1_FDF (0x1u << CAN_RXF0E_1_FDF_Pos) +#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ +#define CAN_RXF0E_1_FIDX_Msk (0x7Fu << CAN_RXF0E_1_FIDX_Pos) +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) +#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ +#define CAN_RXF0E_1_ANMF (0x1u << CAN_RXF0E_1_ANMF_Pos) +#define CAN_RXF0E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF0E_1) MASK Register */ + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ +#define CAN_RXF0E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ + +#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ +#define CAN_RXF0E_DATA_DB0_Msk (0xFFu << CAN_RXF0E_DATA_DB0_Pos) +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) +#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ +#define CAN_RXF0E_DATA_DB1_Msk (0xFFu << CAN_RXF0E_DATA_DB1_Pos) +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) +#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ +#define CAN_RXF0E_DATA_DB2_Msk (0xFFu << CAN_RXF0E_DATA_DB2_Pos) +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) +#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ +#define CAN_RXF0E_DATA_DB3_Msk (0xFFu << CAN_RXF0E_DATA_DB3_Pos) +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) +#define CAN_RXF0E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_DATA) MASK Register */ + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ +#define CAN_RXF1E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ + +#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ +#define CAN_RXF1E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF1E_0_ID_Pos) +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) +#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ +#define CAN_RXF1E_0_RTR (0x1u << CAN_RXF1E_0_RTR_Pos) +#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ +#define CAN_RXF1E_0_XTD (0x1u << CAN_RXF1E_0_XTD_Pos) +#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ +#define CAN_RXF1E_0_ESI (0x1u << CAN_RXF1E_0_ESI_Pos) +#define CAN_RXF1E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_0) MASK Register */ + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ +#define CAN_RXF1E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ + +#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ +#define CAN_RXF1E_1_RXTS_Msk (0xFFFFu << CAN_RXF1E_1_RXTS_Pos) +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) +#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ +#define CAN_RXF1E_1_DLC_Msk (0xFu << CAN_RXF1E_1_DLC_Pos) +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) +#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ +#define CAN_RXF1E_1_BRS (0x1u << CAN_RXF1E_1_BRS_Pos) +#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ +#define CAN_RXF1E_1_FDF (0x1u << CAN_RXF1E_1_FDF_Pos) +#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ +#define CAN_RXF1E_1_FIDX_Msk (0x7Fu << CAN_RXF1E_1_FIDX_Pos) +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) +#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ +#define CAN_RXF1E_1_ANMF (0x1u << CAN_RXF1E_1_ANMF_Pos) +#define CAN_RXF1E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF1E_1) MASK Register */ + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ +#define CAN_RXF1E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ + +#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ +#define CAN_RXF1E_DATA_DB0_Msk (0xFFu << CAN_RXF1E_DATA_DB0_Pos) +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) +#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ +#define CAN_RXF1E_DATA_DB1_Msk (0xFFu << CAN_RXF1E_DATA_DB1_Pos) +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) +#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ +#define CAN_RXF1E_DATA_DB2_Msk (0xFFu << CAN_RXF1E_DATA_DB2_Pos) +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) +#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ +#define CAN_RXF1E_DATA_DB3_Msk (0xFFu << CAN_RXF1E_DATA_DB3_Pos) +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) +#define CAN_RXF1E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_DATA) MASK Register */ + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ + uint32_t :5; /*!< bit: 11..15 Reserved */ + uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ + uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ + uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ +#define CAN_SIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ + +#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ +#define CAN_SIDFE_0_SFID2_Msk (0x7FFu << CAN_SIDFE_0_SFID2_Pos) +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) +#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ +#define CAN_SIDFE_0_SFID1_Msk (0x7FFu << CAN_SIDFE_0_SFID1_Pos) +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) +#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ +#define CAN_SIDFE_0_SFEC_Msk (0x7u << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) +#define CAN_SIDFE_0_SFEC_DISABLE_Val 0x0u /**< \brief (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val 0x1u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val 0x2u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val 0x3u /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val 0x4u /**< \brief (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val 0x5u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val 0x6u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val 0x7u /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ +#define CAN_SIDFE_0_SFT_Msk (0x3u << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) +#define CAN_SIDFE_0_SFT_RANGE_Val 0x0u /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val 0x1u /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val 0x2u /**< \brief (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_MASK 0xFFFF07FFu /**< \brief (CAN_SIDFE_0) MASK Register */ + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ +#define CAN_TXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ + +#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ +#define CAN_TXBE_0_ID_Msk (0x1FFFFFFFu << CAN_TXBE_0_ID_Pos) +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) +#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ +#define CAN_TXBE_0_RTR (0x1u << CAN_TXBE_0_RTR_Pos) +#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ +#define CAN_TXBE_0_XTD (0x1u << CAN_TXBE_0_XTD_Pos) +#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ +#define CAN_TXBE_0_ESI (0x1u << CAN_TXBE_0_ESI_Pos) +#define CAN_TXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_0) MASK Register */ + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t DLC:4; /*!< bit: 16..19 Identifier */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ +#define CAN_TXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ + +#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ +#define CAN_TXBE_1_DLC_Msk (0xFu << CAN_TXBE_1_DLC_Pos) +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) +#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ +#define CAN_TXBE_1_BRS (0x1u << CAN_TXBE_1_BRS_Pos) +#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ +#define CAN_TXBE_1_FDF (0x1u << CAN_TXBE_1_FDF_Pos) +#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ +#define CAN_TXBE_1_EFC (0x1u << CAN_TXBE_1_EFC_Pos) +#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ +#define CAN_TXBE_1_MM_Msk (0xFFu << CAN_TXBE_1_MM_Pos) +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) +#define CAN_TXBE_1_MASK 0xFFBF0000u /**< \brief (CAN_TXBE_1) MASK Register */ + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ +#define CAN_TXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ + +#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ +#define CAN_TXBE_DATA_DB0_Msk (0xFFu << CAN_TXBE_DATA_DB0_Pos) +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) +#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ +#define CAN_TXBE_DATA_DB1_Msk (0xFFu << CAN_TXBE_DATA_DB1_Pos) +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) +#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ +#define CAN_TXBE_DATA_DB2_Msk (0xFFu << CAN_TXBE_DATA_DB2_Pos) +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) +#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ +#define CAN_TXBE_DATA_DB3_Msk (0xFFu << CAN_TXBE_DATA_DB3_Pos) +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) +#define CAN_TXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_DATA) MASK Register */ + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ +#define CAN_TXEFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ + +#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ +#define CAN_TXEFE_0_ID_Msk (0x1FFFFFFFu << CAN_TXEFE_0_ID_Pos) +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) +#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ +#define CAN_TXEFE_0_RTR (0x1u << CAN_TXEFE_0_RTR_Pos) +#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ +#define CAN_TXEFE_0_XTD (0x1u << CAN_TXEFE_0_XTD_Pos) +#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ +#define CAN_TXEFE_0_ESI (0x1u << CAN_TXEFE_0_ESI_Pos) +#define CAN_TXEFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_0) MASK Register */ + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t ET:2; /*!< bit: 22..23 Event Type */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ +#define CAN_TXEFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ + +#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ +#define CAN_TXEFE_1_TXTS_Msk (0xFFFFu << CAN_TXEFE_1_TXTS_Pos) +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) +#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ +#define CAN_TXEFE_1_DLC_Msk (0xFu << CAN_TXEFE_1_DLC_Pos) +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) +#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ +#define CAN_TXEFE_1_BRS (0x1u << CAN_TXEFE_1_BRS_Pos) +#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ +#define CAN_TXEFE_1_FDF (0x1u << CAN_TXEFE_1_FDF_Pos) +#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ +#define CAN_TXEFE_1_ET_Msk (0x3u << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) +#define CAN_TXEFE_1_ET_TXE_Val 0x1u /**< \brief (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val 0x2u /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ +#define CAN_TXEFE_1_MM_Msk (0xFFu << CAN_TXEFE_1_MM_Pos) +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) +#define CAN_TXEFE_1_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_1) MASK Register */ + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ + uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ +#define CAN_XIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ + +#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ +#define CAN_XIDFE_0_EFID1_Msk (0x1FFFFFFFu << CAN_XIDFE_0_EFID1_Pos) +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) +#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ +#define CAN_XIDFE_0_EFEC_Msk (0x7u << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) +#define CAN_XIDFE_0_EFEC_DISABLE_Val 0x0u /**< \brief (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val 0x1u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val 0x2u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val 0x3u /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val 0x4u /**< \brief (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val 0x5u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val 0x6u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val 0x7u /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_XIDFE_0) MASK Register */ + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ +#define CAN_XIDFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ + +#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ +#define CAN_XIDFE_1_EFID2_Msk (0x1FFFFFFFu << CAN_XIDFE_1_EFID2_Pos) +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) +#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ +#define CAN_XIDFE_1_EFT_Msk (0x3u << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) +#define CAN_XIDFE_1_EFT_RANGEM_Val 0x0u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val 0x1u /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val 0x2u /**< \brief (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val 0x3u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_MASK 0xDFFFFFFFu /**< \brief (CAN_XIDFE_1) MASK Register */ + +/** \brief CAN APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ + __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ + __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ + __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ + __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ + RoReg8 Reserved1[0x10]; + __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ + __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ + __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved2[0x4]; + __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ + __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ + RoReg8 Reserved3[0x20]; + __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved4[0x4]; + __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ + __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ + __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + RoReg8 Reserved5[0x8]; + __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} Can; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} CanMramRxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf0e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} CanMramRxf0e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf1e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} CanMramRxf1e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_sidfe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ +} CanMramSidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} CanMramTxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txefe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} CanMramTxefe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_xifde hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} CanMramXifde +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SECTION_CAN_MRAM_RXBE + +#define SECTION_CAN_MRAM_RXF0E + +#define SECTION_CAN_MRAM_RXF1E + +#define SECTION_CAN_MRAM_SIDFE + +#define SECTION_CAN_MRAM_TXBE + +#define SECTION_CAN_MRAM_TXEFE + +#define SECTION_CAN_MRAM_XIFDE + +/*@}*/ + +#endif /* _SAMD51_CAN_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/ccl.h b/atmel-samd/asf4/samd51/include/component/ccl.h new file mode 100644 index 0000000000000..73967aef2c088 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/ccl.h @@ -0,0 +1,227 @@ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_CCL_COMPONENT_ +#define _SAMD51_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAMD51_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x110 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ + uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_CCL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/cmcc.h b/atmel-samd/asf4/samd51/include/component/cmcc.h new file mode 100644 index 0000000000000..1f7513be4f989 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/cmcc.h @@ -0,0 +1,356 @@ +/** + * \file + * + * \brief Component description for CMCC + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_CMCC_COMPONENT_ +#define _SAMD51_CMCC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CMCC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */ +/*@{*/ + +#define CMCC_U2015 +#define REV_CMCC 0x600 + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ + uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ + uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ + uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ + uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ + uint32_t :18; /*!< bit: 14..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_TYPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ +#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ + +#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ +#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) +#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ +#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) +#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ +#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ +#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) +#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ +#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ +#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ + uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ +#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ + +#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ +#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) +#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ +#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) +#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ +#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ +#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ + +#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ +#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) +#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_SR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ +#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ + +#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ +#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) +#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_LCKWAY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ +#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ + +#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ +#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) +#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ +#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ + +#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ +#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) +#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ + uint32_t :16; /*!< bit: 12..27 Reserved */ + uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ +#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ + +#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ +#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) +#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ +#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) +#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ +#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ + +#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ +#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ +#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ + +#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ +#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) +#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ +#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ + +#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ +#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) +#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ +#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ + +#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ +#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) +#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ + +/** \brief CMCC APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ + __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ + __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ + __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + RoReg8 Reserved1[0xC]; + __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} Cmcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_CMCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/dac.h b/atmel-samd/asf4/samd51/include/component/dac.h new file mode 100644 index 0000000000000..72f4df29ff536 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/dac.h @@ -0,0 +1,543 @@ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_DAC_COMPONENT_ +#define _SAMD51_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */ +/*@{*/ + +#define DAC_U2502 +#define REV_DAC 0x100 + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ +#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ + uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ +#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) +#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ + uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ + uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ + uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ + uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ + uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ + uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ + uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ + uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ + uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ + uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ +#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) +#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ +#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ +#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) +#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ +#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ +#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) +#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ +#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) +#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ +#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) +#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ +#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) +#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) +#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) +#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) +#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) +#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) +#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) +#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) +#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) +#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) +#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) +#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) +#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) +#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) +#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) +#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) +#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) +#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) +#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ + __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ + __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ + __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ + __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ + __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ + __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ + __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ + __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ + __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ + __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ +#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) +#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ +#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ +#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) +#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ +#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) +#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ +#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) +#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ +#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) +#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ +#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) +#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ +#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) +#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) +#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ + uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ + uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ + uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ + uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ +#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) +#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ +#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) +#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ +#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) +#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ +#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) +#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) +#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ + uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ + uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ + uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ + uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ + uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DAC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ + +#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ +#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ +#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ +#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) +#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ +#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) +#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ +#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) +#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ +#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) +#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) +#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ + uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ + uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ + uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ + uint16_t :1; /*!< bit: 12 Reserved */ + uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DACCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ +#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ + +#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ +#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) +#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ +#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) +#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ +#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) +#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ +#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) +#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ +#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) +#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ +#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) +#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ +#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) +#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ +#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) +#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ +#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ + +#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ +#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) +#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ +#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ + +#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ +#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) +#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ + __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ + __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ + __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x3]; + __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/dmac.h b/atmel-samd/asf4/samd51/include/component/dmac.h new file mode 100644 index 0000000000000..2ab792bcbad00 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/component/dmac.h @@ -0,0 +1,1415 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_DMAC_COMPONENT_ +#define _SAMD51_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2503 +#define REV_DMAC 0x100 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t :6; /*!< bit: 2.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ +#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) +#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ +#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ +#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) +#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ + uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ + uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ + uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ + uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ + uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ + uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ + uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ + uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ + uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ + uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ + uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ + uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ + uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ + uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ + uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ + uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ + uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ + uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ + uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ + uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ + uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ + uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ + uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ +#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) +#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ +#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) +#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ +#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) +#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ +#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) +#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ +#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ + uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ + uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ + uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ + uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ + uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ + uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ + uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ + uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ + uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ + uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ + uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ + uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ + uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ + uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ + uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ + uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ + uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ + uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ + uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) +#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) +#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) +#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) +#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos) +#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos) +#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos) +#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos) +#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos) +#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos) +#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos) +#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos) +#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos) +#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos) +#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos) +#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos) +#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos) +#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos) +#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos) +#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ + uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ + uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ + uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ + uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ + uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ + uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ + uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ + uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ + uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ + uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ + uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ + uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ + uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ + uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ + uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ + uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ + uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ + uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ + uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ +#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) +#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ +#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) +#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ +#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) +#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ +#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) +#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */ +#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos) +#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */ +#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos) +#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */ +#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos) +#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */ +#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos) +#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */ +#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos) +#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */ +#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos) +#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */ +#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos) +#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */ +#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos) +#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */ +#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos) +#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */ +#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos) +#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */ +#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos) +#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */ +#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos) +#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */ +#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos) +#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */ +#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos) +#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */ +#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos) +#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ +#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ + uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ + uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ + uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ + uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ + uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ + uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ + uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ + uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ + uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ + uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ + uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ + uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ + uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ + uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ + uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ + uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ + uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ + uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ + uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ +#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) +#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ +#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) +#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ +#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) +#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ +#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) +#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */ +#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos) +#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */ +#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos) +#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */ +#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos) +#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */ +#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos) +#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */ +#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos) +#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */ +#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos) +#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */ +#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos) +#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */ +#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos) +#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */ +#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos) +#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */ +#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos) +#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */ +#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos) +#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */ +#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos) +#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */ +#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos) +#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */ +#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos) +#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */ +#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos) +#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ +#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint32_t :4; /*!< bit: 2.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ + uint32_t :5; /*!< bit: 15..19 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ + uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ +#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ +#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ +#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) +#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) +#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ +#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) +#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ +#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) +#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ +#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ +#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ +#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ +#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) +#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ +#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ +#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) +#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ +#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ +#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ + +#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHPRILVL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ +#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ + +#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ +#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) +#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ +#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ +#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ +#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ +#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ +#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ +#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ + +/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ + uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ + uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHEVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ +#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ + +#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ +#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) +#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ +#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ +#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ +#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ +#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ +#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ +#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ +#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) +#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ +#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ +#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ +#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos) +#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ +#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos) +#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ +#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ +#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos) +#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits +#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 10 // Index of Generic Clock +#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value +#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value +#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented +#define USB_PIPE_NUM 8 // Number of USB pipes +#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system +#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) +#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode +#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested +#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode + +#endif /* _SAMD51_USB_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd51/include/instance/wdt.h b/atmel-samd/asf4/samd51/include/instance/wdt.h new file mode 100644 index 0000000000000..3590a7c375416 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/instance/wdt.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_WDT_INSTANCE_ +#define _SAMD51_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAMD51_WDT_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51g18a.h b/atmel-samd/asf4/samd51/include/pio/samd51g18a.h new file mode 100644 index 0000000000000..7df83ceb71d7e --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51g18a.h @@ -0,0 +1,1359 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51G18A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G18A_PIO_ +#define _SAMD51G18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51G18A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51g19a.h b/atmel-samd/asf4/samd51/include/pio/samd51g19a.h new file mode 100644 index 0000000000000..75bbb8ba04893 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51g19a.h @@ -0,0 +1,1359 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51G19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G19A_PIO_ +#define _SAMD51G19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51G19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j18a.h b/atmel-samd/asf4/samd51/include/pio/samd51j18a.h new file mode 100644 index 0000000000000..dd802f85fe949 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51j18a.h @@ -0,0 +1,1862 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51J18A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J18A_PIO_ +#define _SAMD51J18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ +#define MUX_PB31H_TAL_BRK _L_(7) +#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) +#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51J18A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j19a.h b/atmel-samd/asf4/samd51/include/pio/samd51j19a.h new file mode 100644 index 0000000000000..76191476af319 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51j19a.h @@ -0,0 +1,1862 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51J19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J19A_PIO_ +#define _SAMD51J19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ +#define MUX_PB31H_TAL_BRK _L_(7) +#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) +#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51J19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j20a.h b/atmel-samd/asf4/samd51/include/pio/samd51j20a.h new file mode 100644 index 0000000000000..51bedee2fcb8b --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51j20a.h @@ -0,0 +1,1862 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51J20A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J20A_PIO_ +#define _SAMD51J20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ +#define MUX_PB31H_TAL_BRK _L_(7) +#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) +#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51J20A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51n19a.h b/atmel-samd/asf4/samd51/include/pio/samd51n19a.h new file mode 100644 index 0000000000000..6f169eee10cff --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51n19a.h @@ -0,0 +1,2569 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51N19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N19A_PIO_ +#define _SAMD51N19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ +#define MUX_PB31H_TAL_BRK _L_(7) +#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) +#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51N19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51n20a.h b/atmel-samd/asf4/samd51/include/pio/samd51n20a.h new file mode 100644 index 0000000000000..8ec9a1ddd70e7 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51n20a.h @@ -0,0 +1,2569 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51N20A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N20A_PIO_ +#define _SAMD51N20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ +#define MUX_PB31H_TAL_BRK _L_(7) +#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) +#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51N20A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51p19a.h b/atmel-samd/asf4/samd51/include/pio/samd51p19a.h new file mode 100644 index 0000000000000..195771bda4783 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51p19a.h @@ -0,0 +1,2883 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51P19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P19A_PIO_ +#define _SAMD51P19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ +#define MUX_PB31H_TAL_BRK _L_(7) +#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) +#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51P19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51p20a.h b/atmel-samd/asf4/samd51/include/pio/samd51p20a.h new file mode 100644 index 0000000000000..2551b2873b80e --- /dev/null +++ b/atmel-samd/asf4/samd51/include/pio/samd51p20a.h @@ -0,0 +1,2883 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51P20A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P20A_PIO_ +#define _SAMD51P20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TAL peripheral ========== */ +#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ +#define MUX_PA27H_TAL_BRK _L_(7) +#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) +#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) +#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ +#define MUX_PB31H_TAL_BRK _L_(7) +#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) +#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51P20A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/sam.h b/atmel-samd/asf4/samd51/include/sam.h new file mode 100644 index 0000000000000..092538e106bdc --- /dev/null +++ b/atmel-samd/asf4/samd51/include/sam.h @@ -0,0 +1,53 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) +#include "samd51g18a.h" +#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) +#include "samd51g19a.h" +#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) +#include "samd51j18a.h" +#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) +#include "samd51j19a.h" +#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) +#include "samd51j20a.h" +#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) +#include "samd51n19a.h" +#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) +#include "samd51n20a.h" +#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) +#include "samd51p19a.h" +#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) +#include "samd51p20a.h" +#else +#error Library does not support the specified device +#endif + +#endif /* _SAM_ */ diff --git a/atmel-samd/asf4/samd51/include/samd51.h b/atmel-samd/asf4/samd51/include/samd51.h new file mode 100644 index 0000000000000..4869ad9b472c8 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51.h @@ -0,0 +1,59 @@ +/** + * \file + * + * \brief Top header file for SAMD51 + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_ +#define _SAMD51_ + +/** + * \defgroup SAMD51_definitions SAMD51 Device Definitions + * \brief SAMD51 CMSIS Definitions. + */ + +#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) + #include "samd51g18a.h" +#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) + #include "samd51g19a.h" +#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) + #include "samd51j18a.h" +#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) + #include "samd51j19a.h" +#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) + #include "samd51j20a.h" +#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) + #include "samd51n19a.h" +#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) + #include "samd51n20a.h" +#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) + #include "samd51p19a.h" +#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) + #include "samd51p20a.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMD51_ */ diff --git a/atmel-samd/asf4/samd51/include/samd51g18a.h b/atmel-samd/asf4/samd51/include/samd51g18a.h new file mode 100644 index 0000000000000..239f73e94abdb --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51g18a.h @@ -0,0 +1,1033 @@ +/** + * \file + * + * \brief Header file for SAMD51G18A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G18A_ +#define _SAMD51G18A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51G18A_definitions SAMD51G18A definitions + * This file defines all structures and symbols for SAMD51G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51G18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51G18A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51G18A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G18A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51G18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51G18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51G18A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51G18A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51G18A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51G18A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51G18A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51G18A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51G18A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51G18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51G18A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TC0_IRQn = 107, /**< 107 SAMD51G18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51G18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51G18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51G18A Basic Timer Counter 3 (TC3) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51G18A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + PCC_IRQn = 129, /**< 129 SAMD51G18A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51G18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51G18A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51G18A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51G18A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51G18A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51G18A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pvReserved101; + void* pvReserved102; + void* pvReserved103; + void* pvReserved104; + void* pvReserved105; + void* pvReserved106; + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pvReserved111; + void* pvReserved112; + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pvReserved128; + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060008) +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51G18A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51g19a.h b/atmel-samd/asf4/samd51/include/samd51g19a.h new file mode 100644 index 0000000000000..ab62fabad8f67 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51g19a.h @@ -0,0 +1,1033 @@ +/** + * \file + * + * \brief Header file for SAMD51G19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G19A_ +#define _SAMD51G19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51G19A_definitions SAMD51G19A definitions + * This file defines all structures and symbols for SAMD51G19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51G19A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51G19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51G19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51G19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51G19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51G19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51G19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51G19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51G19A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51G19A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51G19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51G19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51G19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51G19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TC0_IRQn = 107, /**< 107 SAMD51G19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51G19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51G19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51G19A Basic Timer Counter 3 (TC3) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51G19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + PCC_IRQn = 129, /**< 129 SAMD51G19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51G19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51G19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51G19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51G19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51G19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51G19A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pvReserved101; + void* pvReserved102; + void* pvReserved103; + void* pvReserved104; + void* pvReserved105; + void* pvReserved106; + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pvReserved111; + void* pvReserved112; + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pvReserved128; + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51g19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060007) +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51G19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51j18a.h b/atmel-samd/asf4/samd51/include/samd51j18a.h new file mode 100644 index 0000000000000..0d33551e3580f --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51j18a.h @@ -0,0 +1,1075 @@ +/** + * \file + * + * \brief Header file for SAMD51J18A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J18A_ +#define _SAMD51J18A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51J18A_definitions SAMD51J18A definitions + * This file defines all structures and symbols for SAMD51J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51J18A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51J18A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51J18A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J18A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51J18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51J18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51J18A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51J18A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51J18A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51J18A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51J18A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51J18A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51J18A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51J18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51J18A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51J18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51J18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51J18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51J18A Basic Timer Counter 5 (TC5) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51J18A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51J18A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51J18A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51J18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51J18A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51J18A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51J18A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51J18A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51J18A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060006) +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51J18A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51j19a.h b/atmel-samd/asf4/samd51/include/samd51j19a.h new file mode 100644 index 0000000000000..7748fcd0c7123 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51j19a.h @@ -0,0 +1,1075 @@ +/** + * \file + * + * \brief Header file for SAMD51J19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J19A_ +#define _SAMD51J19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51J19A_definitions SAMD51J19A definitions + * This file defines all structures and symbols for SAMD51J19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51J19A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51J19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51J19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51J19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51J19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51J19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51J19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51J19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51J19A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51J19A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51J19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51J19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51J19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51J19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51J19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51J19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51J19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51J19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51J19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51J19A Basic Timer Counter 5 (TC5) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51J19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51J19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51J19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51J19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51J19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51J19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51J19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51J19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51J19A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51j19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060005) +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51J19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51j20a.h b/atmel-samd/asf4/samd51/include/samd51j20a.h new file mode 100644 index 0000000000000..17fcd9466712e --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51j20a.h @@ -0,0 +1,1075 @@ +/** + * \file + * + * \brief Header file for SAMD51J20A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J20A_ +#define _SAMD51J20A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51J20A_definitions SAMD51J20A definitions + * This file defines all structures and symbols for SAMD51J20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51J20A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51J20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51J20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51J20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51J20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51J20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51J20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51J20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51J20A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51J20A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51J20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51J20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51J20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51J20A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51J20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51J20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51J20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51J20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51J20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51J20A Basic Timer Counter 5 (TC5) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51J20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51J20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51J20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51J20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51J20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51J20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51J20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51J20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51J20A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51j20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060004) +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51J20A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51n19a.h b/atmel-samd/asf4/samd51/include/samd51n19a.h new file mode 100644 index 0000000000000..0c9220cc93dd8 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51n19a.h @@ -0,0 +1,1117 @@ +/** + * \file + * + * \brief Header file for SAMD51N19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N19A_ +#define _SAMD51N19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51N19A_definitions SAMD51N19A definitions + * This file defines all structures and symbols for SAMD51N19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51N19A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51N19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51N19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51N19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51N19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51N19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51N19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51N19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51N19A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51N19A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51N19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51N19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51N19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51N19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51N19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51N19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51N19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51N19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51N19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51N19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51N19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51N19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51N19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51N19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51N19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51N19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51N19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51N19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51N19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51N19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51N19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51N19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51n19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060003) +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51N19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51n20a.h b/atmel-samd/asf4/samd51/include/samd51n20a.h new file mode 100644 index 0000000000000..e392a7fb4b16c --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51n20a.h @@ -0,0 +1,1117 @@ +/** + * \file + * + * \brief Header file for SAMD51N20A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N20A_ +#define _SAMD51N20A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51N20A_definitions SAMD51N20A definitions + * This file defines all structures and symbols for SAMD51N20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51N20A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51N20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51N20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51N20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51N20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51N20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51N20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51N20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51N20A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51N20A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51N20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51N20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51N20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51N20A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51N20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51N20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51N20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51N20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51N20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51N20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51N20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51N20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51N20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51N20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51N20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51N20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51N20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51N20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51N20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51N20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51N20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51N20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51n20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060002) +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51N20A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51p19a.h b/atmel-samd/asf4/samd51/include/samd51p19a.h new file mode 100644 index 0000000000000..62c58fd52465c --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51p19a.h @@ -0,0 +1,1117 @@ +/** + * \file + * + * \brief Header file for SAMD51P19A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P19A_ +#define _SAMD51P19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51P19A_definitions SAMD51P19A definitions + * This file defines all structures and symbols for SAMD51P19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51P19A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51P19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51P19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51P19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51P19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51P19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51P19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51P19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51P19A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51P19A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51P19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51P19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51P19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51P19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51P19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51P19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51P19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51P19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51P19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51P19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51P19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51P19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51P19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51P19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51P19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51P19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51P19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51P19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51P19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51P19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51P19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51P19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51p19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060001) +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51P19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51p20a.h b/atmel-samd/asf4/samd51/include/samd51p20a.h new file mode 100644 index 0000000000000..35bc1a51187ce --- /dev/null +++ b/atmel-samd/asf4/samd51/include/samd51p20a.h @@ -0,0 +1,1117 @@ +/** + * \file + * + * \brief Header file for SAMD51P20A + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P20A_ +#define _SAMD51P20A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51P20A_definitions SAMD51P20A definitions + * This file defines all structures and symbols for SAMD51P20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ + /****** SAMD51P20A-specific Interrupt Numbers ***********************/ + PM_IRQn = 0, /**< 0 SAMD51P20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51P20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51P20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51P20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51P20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51P20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51P20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51P20A Peripheral Access Controller (PAC) */ + TAL_0_IRQn = 42, /**< 42 SAMD51P20A Trigger Allocator (TAL): TAL_BRK */ + TAL_1_IRQn = 43, /**< 43 SAMD51P20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ + RAMECC_IRQn = 45, /**< 45 SAMD51P20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51P20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51P20A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51P20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51P20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51P20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51P20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51P20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51P20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51P20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51P20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51P20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51P20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51P20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51P20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51P20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51P20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51P20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51P20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51P20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51P20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ + void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void TAL_0_Handler ( void ); +void TAL_1_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +//#define LITTLE_ENDIAN 1 +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tal.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tal.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ +#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ +#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ +#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ +#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ +#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ +#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ +#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ +#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ +#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ +#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ +#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ +#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ +#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ +#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ +#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ +#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ +#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ +#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ +#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ +#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ +#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ +#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ +#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ +#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ +#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ +#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51p20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060000) +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51P20A_H */ diff --git a/atmel-samd/asf4/samd51/include/system_samd51.h b/atmel-samd/asf4/samd51/include/system_samd51.h new file mode 100644 index 0000000000000..2f4d2ad583a67 --- /dev/null +++ b/atmel-samd/asf4/samd51/include/system_samd51.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2017 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAMD51_H_INCLUDED_ +#define _SYSTEM_SAMD51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAMD51_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/main.c b/atmel-samd/asf4/samd51/main.c new file mode 100644 index 0000000000000..4652da488fb76 --- /dev/null +++ b/atmel-samd/asf4/samd51/main.c @@ -0,0 +1,11 @@ +#include + +int main(void) +{ + /* Initializes MCU, drivers and middleware */ + atmel_start_init(); + + /* Replace with your application code */ + while (1) { + } +} diff --git a/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.c b/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.c new file mode 100644 index 0000000000000..f0a8de446e4d1 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.c @@ -0,0 +1,389 @@ +/** + * \file + * + * \brief USB Device Stack CDC ACM Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "cdcdf_acm.h" + +#define CDCDF_ACM_VERSION 0x00000001u +#define CDCDF_ACM_COMM_EP_INDEX 0 +#define CDCDF_ACM_DATA_EP_INDEX 1 + +/** USB Device CDC ACM Fucntion Specific Data */ +struct cdcdf_acm_func_data { + /** CDC Device ACM Interface information */ + uint8_t func_iface[2]; + /** CDC Device ACM IN Endpoint */ + uint8_t func_ep_in[2]; + /** CDC Device ACM OUT Endpoint */ + uint8_t func_ep_out; + /** CDC Device ACM Enable Flag */ + bool enabled; +}; + +static struct usbdf_driver _cdcdf_acm; +static struct cdcdf_acm_func_data _cdcdf_acm_funcd; +static struct usb_cdc_line_coding usbd_cdc_line_coding; + +static cdcdf_acm_notify_state_t cdcdf_acm_notify_state = NULL; +static cdcdf_acm_set_line_coding_t cdcdf_acm_set_line_coding = NULL; + +/** + * \brief Enable CDC ACM Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t cdcdf_acm_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); + + usb_ep_desc_t ep_desc; + usb_iface_desc_t ifc_desc; + uint8_t * ifc, *ep; + uint8_t i; + + ifc = desc->sod; + for (i = 0; i < 2; i++) { + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if ((CDC_CLASS_COMM == ifc_desc.bInterfaceClass) || (CDC_CLASS_DATA == ifc_desc.bInterfaceClass)) { + if (func_data->func_iface[i] == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface[i] != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface[i] = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); + while (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in[i] = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in[i]); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + } + desc->sod = ep; + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + } + ifc = usb_find_desc(usb_desc_next(desc->sod), desc->eod, USB_DT_INTERFACE); + } + // Installed + _cdcdf_acm_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable CDC ACM Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t cdcdf_acm_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + uint8_t i; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + // Check interface + if ((ifc_desc.bInterfaceClass != CDC_CLASS_COMM) && (ifc_desc.bInterfaceClass != CDC_CLASS_DATA)) { + return ERR_NOT_FOUND; + } + } + + for (i = 0; i < 2; i++) { + if (func_data->func_iface[i] == 0xFF) { + continue; + } else { + func_data->func_iface[i] = 0xFF; + if (func_data->func_ep_in[i] != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in[i]); + func_data->func_ep_in[i] = 0xFF; + } + } + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + _cdcdf_acm_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief CDC ACM Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t cdcdf_acm_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return cdcdf_acm_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return cdcdf_acm_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the CDC class set request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t cdcdf_acm_set_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + struct usb_cdc_line_coding line_coding_tmp; + uint16_t len = req->wLength; + uint8_t * ctrl_buf = usbdc_get_ctrl_buffer(); + + switch (req->bRequest) { + case USB_REQ_CDC_SET_LINE_CODING: + if (sizeof(struct usb_cdc_line_coding) != len) { + return ERR_INVALID_DATA; + } + if (USB_SETUP_STAGE == stage) { + return usbdc_xfer(ep, ctrl_buf, len, false); + } else { + memcpy(&line_coding_tmp, ctrl_buf, sizeof(struct usb_cdc_line_coding)); + if ((NULL == cdcdf_acm_set_line_coding) || (true == cdcdf_acm_set_line_coding(&line_coding_tmp))) { + usbd_cdc_line_coding = line_coding_tmp; + } + return ERR_NONE; + } + case USB_REQ_CDC_SET_CONTROL_LINE_STATE: + usbdc_xfer(0, NULL, 0, 0); + if (NULL != cdcdf_acm_notify_state) { + cdcdf_acm_notify_state(req->wValue); + } + return ERR_NONE; + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the CDC class get request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t cdcdf_acm_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + uint16_t len = req->wLength; + + if (USB_DATA_STAGE == stage) { + return ERR_NONE; + } + + switch (req->bRequest) { + case USB_REQ_CDC_GET_LINE_CODING: + if (sizeof(struct usb_cdc_line_coding) != len) { + return ERR_INVALID_DATA; + } + return usbdc_xfer(ep, (uint8_t *)&usbd_cdc_line_coding, len, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the CDC class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t cdcdf_acm_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if ((req->wIndex == _cdcdf_acm_funcd.func_iface[0]) || (req->wIndex == _cdcdf_acm_funcd.func_iface[1])) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return cdcdf_acm_get_req(ep, req, stage); + } else { + return cdcdf_acm_set_req(ep, req, stage); + } + } else { + return ERR_NOT_FOUND; + } +} + +/** USB Device CDC ACM Handler Struct */ +static struct usbdc_handler cdcdf_acm_req_h = {NULL, (FUNC_PTR)cdcdf_acm_req}; + +/** + * \brief Initialize the USB CDC ACM Function Driver + */ +int32_t cdcdf_acm_init(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _cdcdf_acm.ctrl = cdcdf_acm_ctrl; + _cdcdf_acm.func_data = &_cdcdf_acm_funcd; + + usbdc_register_function(&_cdcdf_acm); + usbdc_register_handler(USBDC_HDL_REQ, &cdcdf_acm_req_h); + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB CDC ACM Function Driver + */ +void cdcdf_acm_deinit(void) +{ + usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_COMM_EP_INDEX]); + usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); + usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_out); +} + +/** + * \brief USB CDC ACM Function Read Data + */ +int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size) +{ + if (!cdcdf_acm_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_cdcdf_acm_funcd.func_ep_out, buf, size, false); +} + +/** + * \brief USB CDC ACM Function Write Data + */ +int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size) +{ + if (!cdcdf_acm_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], buf, size, true); +} + +/** + * \brief USB CDC ACM Stop the data transfer + */ +void cdcdf_acm_stop_xfer(void) +{ + /* Stop transfer. */ + usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); + usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_out); +} + +/** + * \brief USB CDC ACM Function Register Callback + */ +int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func) +{ + switch (cb_type) { + case CDCDF_ACM_CB_READ: + usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_out, USB_D_EP_CB_XFER, func); + break; + case CDCDF_ACM_CB_WRITE: + usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], USB_D_EP_CB_XFER, func); + break; + case CDCDF_ACM_CB_LINE_CODING_C: + cdcdf_acm_set_line_coding = (cdcdf_acm_set_line_coding_t)func; + break; + case CDCDF_ACM_CB_STATE_C: + cdcdf_acm_notify_state = (cdcdf_acm_notify_state_t)func; + break; + default: + return ERR_INVALID_ARG; + } + return ERR_NONE; +} + +/** + * \brief Check whether CDC ACM Function is enabled + */ +bool cdcdf_acm_is_enabled(void) +{ + return _cdcdf_acm_funcd.enabled; +} + +/** + * \brief Return the CDC ACM line coding structure start address + */ +const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void) +{ + return (const struct usb_cdc_line_coding *)&usbd_cdc_line_coding; +} + +/** + * \brief Return version + */ +uint32_t cdcdf_acm_get_version(void) +{ + return CDCDF_ACM_VERSION; +} diff --git a/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.h b/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.h new file mode 100644 index 0000000000000..913e734be4578 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.h @@ -0,0 +1,114 @@ +/** + * \file + * + * \brief USB Device Stack CDC ACM Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_CDC_ACM_SER_H_ +#define USBDF_CDC_ACM_SER_H_ + +#include "usbdc.h" +#include "usb_protocol_cdc.h" + +/** CDC ACM Class Callback Type */ +enum cdcdf_acm_cb_type { CDCDF_ACM_CB_READ, CDCDF_ACM_CB_WRITE, CDCDF_ACM_CB_LINE_CODING_C, CDCDF_ACM_CB_STATE_C }; + +/** CDC ACM Notify Line State Callback. */ +typedef void (*cdcdf_acm_notify_state_t)(uint16_t); + +/** CDC ACM Set Line Coding Callback. */ +typedef bool (*cdcdf_acm_set_line_coding_t)(struct usb_cdc_line_coding *); + +/** + * \brief Initialize the USB CDC ACM Function Driver + * \return Operation status. + */ +int32_t cdcdf_acm_init(void); + +/** + * \brief Deinitialize the USB CDC ACM Function Driver + * \return Operation status. + */ +void cdcdf_acm_deinit(void); + +/** + * \brief USB CDC ACM Function Read Data + * \param[in] buf Pointer to the buffer which receives data + * \param[in] size the size of data to be received + * \return Operation status. + */ +int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size); + +/** + * \brief USB CDC ACM Function Write Data + * \param[in] buf Pointer to the buffer which stores data + * \param[in] size the size of data to be sent + * \return Operation status. + */ +int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size); + +/** + * \brief USB CDC ACM Stop the currnet data transfer + */ +void cdcdf_acm_stop_xfer(void); + +/** + * \brief USB CDC ACM Function Register Callback + * \param[in] cb_type Callback type of CDC ACM Function + * \param[in] func Pointer to callback function + * \return Operation status. + */ +int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func); + +/** + * \brief Check whether CDC ACM Function is enabled + * \return Operation status. + * \return true CDC ACM Function is enabled + * \return false CDC ACM Function is disabled + */ +bool cdcdf_acm_is_enabled(void); + +/** + * \brief Return the CDC ACM line coding structure start address + * \return Pointer to USB CDC ACM line coding data. + */ +const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void); + +/** + * \brief Return version + */ +uint32_t cdcdf_acm_get_version(void); + +#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h b/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h new file mode 100644 index 0000000000000..6017864cb2755 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h @@ -0,0 +1,407 @@ +/** + * \file + * + * \brief USB Communication Device Class (CDC) protocol definitions + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ +#ifndef _USB_PROTOCOL_CDC_H_ +#define _USB_PROTOCOL_CDC_H_ + +#include "usb_includes.h" + +/** + * \ingroup usb_protocol_group + * \defgroup cdc_protocol_group Communication Device Class Definitions + * @{ + */ + +/** + * \name Possible values of class + */ +//@{ +#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class +#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface +#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface +//@} + +//! \name USB CDC Subclass IDs +//@{ +#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model +#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model +#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model +#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model +#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model +#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model +#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model +//@} + +//! \name USB CDC Communication Interface Protocol IDs +//@{ +#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands +//@} + +//! \name USB CDC Data Interface Protocol IDs +//@{ +#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI +#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC +#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent +#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol +#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol +#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor +#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures +#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control +#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN +#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands +#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver + /** + * \brief Describes the Protocol Unit Functional Descriptors [sic] + * on Communication Class Interface + */ +#define CDC_PROTOCOL_PUFD 0xFE +//@} + +//! \name USB CDC Functional Descriptor Types +//@{ +#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor +#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor +//@} + +//! \name USB CDC Functional Descriptor Subtypes +//@{ +#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor +#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management +#define CDC_SCS_ACM 0x02 //!< Abstract Control Management +#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor +//@} + +//! \name USB CDC Request IDs +//@{ +#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define USB_REQ_CDC_SET_COMM_FEATURE 0x02 +#define USB_REQ_CDC_GET_COMM_FEATURE 0x03 +#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04 +#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10 +#define USB_REQ_CDC_SET_HOOK_STATE 0x11 +#define USB_REQ_CDC_PULSE_SETUP 0x12 +#define USB_REQ_CDC_SEND_PULSE 0x13 +#define USB_REQ_CDC_SET_PULSE_TIME 0x14 +#define USB_REQ_CDC_RING_AUX_JACK 0x15 +#define USB_REQ_CDC_SET_LINE_CODING 0x20 +#define USB_REQ_CDC_GET_LINE_CODING 0x21 +#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22 +#define USB_REQ_CDC_SEND_BREAK 0x23 +#define USB_REQ_CDC_SET_RINGER_PARMS 0x30 +#define USB_REQ_CDC_GET_RINGER_PARMS 0x31 +#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32 +#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33 +#define USB_REQ_CDC_SET_LINE_PARMS 0x34 +#define USB_REQ_CDC_GET_LINE_PARMS 0x35 +#define USB_REQ_CDC_DIAL_DIGITS 0x36 +#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37 +#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38 +#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39 +#define USB_REQ_CDC_GET_PROFILE 0x3A +#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41 +#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42 +#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44 +#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50 +#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51 +#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52 +#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53 +// Added bNotification codes according cdc spec 1.1 chapter 6.3 +#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09 +#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20 +#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 +#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 +//@} + +/* + * Need to pack structures tightly, or the compiler might insert padding + * and violate the spec-mandated layout. + */ +COMPILER_PACK_SET(1) + +//! \name USB CDC Descriptors +//@{ + +//! CDC Header Functional Descriptor +typedef struct usb_cdc_hdr_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + le16_t bcdCDC; +} usb_cdc_hdr_desc_t; + +#define USB_CDC_HDR_DESC_LEN 5 +#define USB_CDC_HDR_DESC_BYTES(bcdCDC) \ + USB_CDC_HDR_DESC_LEN, /* bFunctionLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_SCS_HEADER, /* bDescriptorSubtype */ \ + LE_BYTE0(bcdCDC), LE_BYTE1(bcdCDC) /* bcdCDC */ + +//! CDC Call Management Functional Descriptor +typedef struct usb_cdc_call_mgmt_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} usb_cdc_call_mgmt_desc_t; + +#define USB_CDC_CALL_MGMT_DESC_LEN 5 +#define USB_CDC_CALL_MGMT_DESC_BYTES(bmCapabilities, bDataInterface) \ + USB_CDC_CALL_MGMT_DESC_LEN, /* bFunctionLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_SCS_CALL_MGMT, /* bDescriptorSubtype */ \ + bmCapabilities, bDataInterface + +//! CDC ACM Functional Descriptor +typedef struct usb_cdc_acm_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} usb_cdc_acm_desc_t; + +#define USB_CDC_ACM_DESC_LEN 4 +#define USB_CDC_ACM_DESC_BYTES(bmCapabilities) \ + USB_CDC_ACM_DESC_LEN, /* bFunctionLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_SCS_ACM, /* bDescriptorSubType */ \ + bmCapabilities + +//! CDC Union Functional Descriptor +typedef struct usb_cdc_union_desc { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bMasterInterface; + uint8_t bSlaveInterface0; +} usb_cdc_union_desc_t; + +#define USB_CDC_UNION_DESC_LEN 5 +#define USB_CDC_UNION_DESC_BYTES(bMasterInterface, bSlaveInterface) \ + USB_CDC_UNION_DESC_LEN, CDC_CS_INTERFACE, CDC_SCS_UNION, bMasterInterface, bSlaveInterface + +//! \name USB CDC Call Management Capabilities +//@{ +//! Device handles call management itself +#define CDC_CALL_MGMT_SUPPORTED (1 << 0) +//! Device can send/receive call management info over a Data Class interface +#define CDC_CALL_MGMT_OVER_DCI (1 << 1) +//@} + +//! \name USB CDC ACM Capabilities +//@{ +//! Device supports the request combination of +//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. +#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0) +//! Device supports the request combination of +//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, +//! and the notification Serial_State. +#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1) +//! Device supports the request Send_Break +#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2) +//! Device supports the notification Network_Connection. +#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3) +//@} +//@} + +//! \name USB CDC line control +//@{ + +//! \name USB CDC line coding +//@{ + +//! Line Coding structure +typedef struct usb_cdc_line_coding { + le32_t dwDTERate; //!< Data rate, bits per second + uint8_t bCharFormat; //!< 0-1 Stop bit,1-1.5 Stop bits,2-2 Stop bits + uint8_t bParityType; //!< 0-None,1-Odd,2-Even,3-Mark,4-Space + uint8_t bDataBits; //!< 5,6,7,8 or 16 +} usb_cdc_line_coding_t; + +//! Possible values of bCharFormat +enum cdc_char_format { + CDC_STOP_BITS_1 = 0, //!< 1 stop bit + CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits + CDC_STOP_BITS_2 = 2 //!< 2 stop bits +}; + +//! Possible values of bParityType +enum cdc_parity { + CDC_PAR_NONE = 0, //!< No parity + CDC_PAR_ODD = 1, //!< Odd parity + CDC_PAR_EVEN = 2, //!< Even parity + CDC_PAR_MARK = 3, //!< Parity forced to 0 (space) + CDC_PAR_SPACE = 4 //!< Parity forced to 1 (mark) +}; +//@} + +//! \name USB CDC control signals +//! spec 1.1 chapter 6.2.14 +//@{ + +//! Control signal structure +typedef struct usb_cdc_control_signal { + union { + le16_t value; + struct { + uint8_t dte_present; + uint8_t carrier_ctrl; + } modem; + struct { + uint8_t DTR : 1; //!< Data Terminal Ready + uint8_t RTS : 1; //!< Request To Send + } rs232; + struct { + uint8_t s108_2 : 1; //!< V.24 signal 108/2 + uint8_t s105 : 1; //!< V.24 signal 105 + } v24; + }; +} usb_cdc_control_signal_t; + +//! \name Possible values in usb_cdc_control_signal_t +//@{ +//! Carrier control for half duplex modems. +//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS. +//! The device ignores the value of this bit +//! when operating in full duplex mode. +#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1) +//! Indicates to DCE if DTE is present or not. +//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. +#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0) +//@} +//@} + +//! \name USB CDC notification message +//@{ + +typedef struct usb_cdc_notify_msg { + uint8_t bmRequestType; + uint8_t bNotification; + union { + le16_t wValue; + struct { + uint8_t low; + uint8_t high; + } wValueBytes; + }; + union { + le16_t wIndex; + struct { + uint8_t low; + uint8_t high; + } wIndexBytes; + }; + union { + le16_t wLength; + struct { + uint8_t low; + uint8_t high; + } wLengthBytes; + }; +} usb_cdc_notify_msg_t; + +//! \name USB CDC serial state +//@{* + +//! UART State Bitmap (cdc spec 1.1 chapter 6.3.5) +typedef union usb_cdc_uart_state { + le16_t value; + struct { + uint8_t bRxCarrier : 1; + uint8_t bTxCarrier : 1; + uint8_t bBreak : 1; + uint8_t bRingSignal : 1; + uint8_t bFraming : 1; + uint8_t bParity : 1; + uint8_t bOverRun; + } bitmap; + struct { + uint8_t bDCD : 1; + uint8_t bDSR : 1; + uint8_t bBreak : 1; + uint8_t bRingSignal : 1; + uint8_t bFraming : 1; + uint8_t bParity : 1; + uint8_t bOverRun; + } rs232; + struct { + uint8_t bS109 : 1; //!< V.24 signal 109 + uint8_t bS106 : 1; //!< V.24 signal 106 + uint8_t bBreak : 1; + uint8_t bRingSignal : 1; + uint8_t bFraming : 1; + uint8_t bParity : 1; + uint8_t bOverRun; + } v24; +} usb_cdc_uart_state_t; + +//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5) +typedef struct usb_cdc_notify_serial_state { + usb_cdc_notify_msg_t header; + union usb_cdc_uart_state state; +} usb_cdc_notify_serial_state_t; + +//! \name Possible values in usb_cdc_notify_serial_state_t +//@{ +#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1 << 0)) +#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1 << 1)) +#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1 << 2)) +#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1 << 3)) +#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1 << 4)) +#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1 << 5)) +#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1 << 6)) +//@} +//! @} + +//! @} + +COMPILER_PACK_RESET() + +//! @} + +#endif // _USB_PROTOCOL_CDC_H_ diff --git a/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h b/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h new file mode 100644 index 0000000000000..68db57af99e98 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h @@ -0,0 +1,170 @@ +/** + * \file + * + * \brief USB Device Stack Composite Class Descriptor Setting. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_COMPOSITE_DESC_H_ +#define USBDF_COMPOSITE_DESC_H_ + +#include "usb_protocol.h" +#include "usbd_composite_config.h" + +#if CONF_USB_COMPOSITE_CDC_ACM_EN == 1 +#define CONF_CDC_ACM_IFC_LEN 66 +#define CONF_CDC_ACM_IFC_NUM 2 +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM 0 +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM 1 +#define CONF_CDC_ACM_IFC_DESC \ + USB_IAD_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x02, CDC_CLASS_DEVICE, CDC_SUBCLASS_ACM, CDC_PROTOCOL_V25TER, 0x00) \ + , \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, \ + 0x00, \ + 0x01, \ + CDC_CLASS_DEVICE, \ + CDC_SUBCLASS_ACM, \ + CDC_PROTOCOL_V25TER, \ + 0x00), \ + USB_CDC_HDR_DESC_BYTES(0x1001), USB_CDC_CALL_MGMT_DESC_BYTES(0x01, 0x00), USB_CDC_ACM_DESC_BYTES(0x02), \ + USB_CDC_UNION_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x01), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR, 3, CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ, 10), \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM, 0x00, 2, 0x0A, 0x00, 0x00, 0x00), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ, 0x00), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ, 0x00), +#else +#define CONF_CDC_ACM_IFC_LEN 0 +#define CONF_CDC_ACM_IFC_NUM 0 +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM -2 +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM -1 +#define CONF_CDC_ACM_IFC_DESC +#endif + +#if CONF_USB_COMPOSITE_HID_MOUSE_EN == 1 +#define CONF_HID_MOUSE_IFC_LEN 25 +#define CONF_HID_MOUSE_IFC_NUM 1 +#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM (CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM + 1) +#define CONF_HID_MOUSE_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM, 0x00, 0x01, 0x03, 0x01, 0x02, 0x00) \ + , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 0x34), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ, 10), +#else +#define CONF_HID_MOUSE_IFC_LEN 0 +#define CONF_HID_MOUSE_IFC_NUM 0 +#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM +#define CONF_HID_MOUSE_IFC_DESC +#endif + +#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN == 1 +#define CONF_HID_KEYBOARD_IFC_LEN 32 +#define CONF_HID_KEYBOARD_IFC_NUM 1 +#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM (CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM + 1) +#define CONF_HID_KEYBOARD_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM, 0x00, 0x02, 0x03, 0x01, 0x01, 0x00) \ + , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 59), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ, 10), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ, 10), +#else +#define CONF_HID_KEYBOARD_IFC_LEN 0 +#define CONF_HID_KEYBOARD_IFC_NUM 0 +#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM +#define CONF_HID_KEYBOARD_IFC_DESC +#endif + +#if CONF_USB_COMPOSITE_HID_GENERIC_EN == 1 +#define CONF_HID_GENERIC_IFC_LEN 32 +#define CONF_HID_GENERIC_IFC_NUM 1 +#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM (CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM + 1) +#define CONF_HID_GENERIC_IFC_DESC \ + USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM, 0x00, 0x02, 0x03, 0x00, 0x00, 0x00) \ + , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ, 10), \ + USB_ENDP_DESC_BYTES( \ + CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ, 10), +#else +#define CONF_HID_GENERIC_IFC_LEN 0 +#define CONF_HID_GENERIC_IFC_NUM 0 +#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM +#define CONF_HID_GENERIC_IFC_DESC +#endif + +#define CONF_USB_COMPOSITE_TOTAL_LEN \ + (USB_CONFIG_DESC_LEN + CONF_CDC_ACM_IFC_LEN + CONF_HID_MOUSE_IFC_LEN + CONF_HID_KEYBOARD_IFC_LEN \ + + CONF_HID_GENERIC_IFC_LEN) + +#define CONF_USB_COMPOSITE_IFC_NUM \ + (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM) + +#define COMPOSITE_DEV_DESC \ + USB_DEV_DESC_BYTES(CONF_USB_COMPOSITE_BCDUSB, \ + 0xEF, \ + 0x02, \ + 0x01, \ + CONF_USB_COMPOSITE_BMAXPKSZ0, \ + CONF_USB_COMPOSITE_IDVENDER, \ + CONF_USB_COMPOSITE_IDPRODUCT, \ + CONF_USB_COMPOSITE_BCDDEVICE, \ + CONF_USB_COMPOSITE_IMANUFACT, \ + CONF_USB_COMPOSITE_IPRODUCT, \ + CONF_USB_COMPOSITE_ISERIALNUM, \ + CONF_USB_COMPOSITE_BNUMCONFIG) + +#define COMPOSITE_CFG_DESC \ + USB_CONFIG_DESC_BYTES(CONF_USB_COMPOSITE_TOTAL_LEN, \ + CONF_USB_COMPOSITE_IFC_NUM, \ + CONF_USB_COMPOSITE_BCONFIGVAL, \ + CONF_USB_COMPOSITE_ICONFIG, \ + CONF_USB_COMPOSITE_BMATTRI, \ + CONF_USB_COMPOSITE_BMAXPOWER) + +#define COMPOSITE_IFACE_DESCES \ + CONF_CDC_ACM_IFC_DESC \ + CONF_HID_MOUSE_IFC_DESC \ + CONF_HID_KEYBOARD_IFC_DESC \ + CONF_HID_GENERIC_IFC_DESC + +/** USB Device descriptors and configuration descriptors */ +#define COMPOSITE_DESCES_LS_FS \ + COMPOSITE_DEV_DESC, COMPOSITE_CFG_DESC, COMPOSITE_IFACE_DESCES CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC, \ + CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC, CONF_USB_COMPOSITE_PRODUCT_STR_DESC + +#endif /* USBDF_COMPOSITE_DESC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h b/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h new file mode 100644 index 0000000000000..1b29802b031f7 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file usbd_composite_config.h */ +#ifndef USBD_COMPOSITE_CONFIG_H +#define USBD_COMPOSITE_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Composite Device Descriptor + +// bcdUSB +// <0x0200=> USB 2.0 version +// <0x0210=> USB 2.1 version +// usb_composite_bcdusb +#ifndef CONF_USB_COMPOSITE_BCDUSB +#define CONF_USB_COMPOSITE_BCDUSB 0x200 +#endif + +// bMaxPackeSize0 +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_bmaxpksz0 +#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 +#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 +#endif + +// idVender <0x0000-0xFFFF> +// usb_composite_idvender +#ifndef CONF_USB_COMPOSITE_IDVENDER +#define CONF_USB_COMPOSITE_IDVENDER 0x3eb +#endif + +// idProduct <0x0000-0xFFFF> +// usb_composite_idproduct +#ifndef CONF_USB_COMPOSITE_IDPRODUCT +#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 +#endif + +// bcdDevice <0x0000-0xFFFF> +// usb_composite_bcddevice +#ifndef CONF_USB_COMPOSITE_BCDDEVICE +#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 +#endif + +// iManufacturer <0x00-0xFF> +// usb_composite_imanufact +#ifndef CONF_USB_COMPOSITE_IMANUFACT +#define CONF_USB_COMPOSITE_IMANUFACT 0x0 +#endif + +#ifndef CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC +#define CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC 0x04, 0x03, 0x09, 0x04 +#endif + +#ifndef CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC +#define CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC \ + 0x14, 0x03, 0x41, 0x00, 0x54, 0x00, 0x4D, 0x00, 0x45, 0x00, 0x4C, 0x00, 0x20, 0x00, 0x41, 0x00, 0x53, 0x00, 0x46, \ + 0x00 +#endif + +// iProduct <0x00-0xFF> +// usb_composite_iproduct +#ifndef CONF_USB_COMPOSITE_IPRODUCT +#define CONF_USB_COMPOSITE_IPRODUCT 0x0 +#endif + +#ifndef CONF_USB_COMPOSITE_PRODUCT_STR_DESC +#define CONF_USB_COMPOSITE_PRODUCT_STR_DESC \ + 0x22, 0x03, 0x43, 0x00, 0x6f, 0x00, 0x6d, 0x00, 0x70, 0x00, 0x6f, 0x00, 0x73, 0x00, 0x69, 0x00, 0x74, 0x00, 0x65, \ + 0x00, 0x20, 0x00, 0x44, 0x00, 0x65, 0x00, 0x76, 0x00, 0x69, 0x00, 0x63, 0x00, 0x65, 0x00 +#endif + +// iSerialNumber <0x00-0xFF> +// usb_composite_iserialnum +#ifndef CONF_USB_COMPOSITE_ISERIALNUM +#define CONF_USB_COMPOSITE_ISERIALNUM 0x0 +#endif + +// bNumConfigurations <0x01-0xFF> +// usb_composite_bnumconfig +#ifndef CONF_USB_COMPOSITE_BNUMCONFIG +#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 +#endif +// + +// Composite Configuration Descriptor + +// bConfigurationValue <0x01-0xFF> +// usb_composite_bconfigval +#ifndef CONF_USB_COMPOSITE_BCONFIGVAL +#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 +#endif + +// iConfiguration <0x00-0xFF> +// usb_composite_iconfig +#ifndef CONF_USB_COMPOSITE_ICONFIG +#define CONF_USB_COMPOSITE_ICONFIG 0x0 +#endif + +// bmAttributes +// <0x80=> Bus power supply, not support for remote wakeup +// <0xA0=> Bus power supply, support for remote wakeup +// <0xC0=> Self powered, not support for remote wakeup +// <0xE0=> Self powered, support for remote wakeup +// usb_composite_bmattri +#ifndef CONF_USB_COMPOSITE_BMATTRI +#define CONF_USB_COMPOSITE_BMATTRI 0x80 +#endif + +// bMaxPower <0x00-0xFF> +// usb_composite_bmaxpower +#ifndef CONF_USB_COMPOSITE_BMAXPOWER +#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 +#endif +// + +// CDC ACM Support +// usb_composite_cdc_acm_support +#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN +#define CONF_USB_COMPOSITE_CDC_ACM_EN 1 +#endif + +// CDC ACM Comm Interrupt IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_cdc_acm_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 +#endif + +// CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_cdc_acm_comm_int_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_cdc_acm_data_bulkin_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 +#endif + +// CDC ACM Data BULK IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_cdc_acm_data_builin_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 +#endif + +// CDC ACM Data BULK OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// usb_composite_cdc_acm_data_bulkout_epaddr +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 +#endif + +// CDC ACM Data BULK OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_cdc_acm_data_buckout_maxpksz +#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 +#endif +// + +// HID Mouse Support +// usb_composite_hid_mouse_support +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN +#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 +#endif + +// HID Mouse INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_hid_mouse_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 +#endif + +// HID Mouse INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_mouse_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 +#endif + +// + +// HID Keyboard Support +// usb_composite_hid_keyboard_support +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN +#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 +#endif + +// HID Keyboard INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_hid_keyboard_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 +#endif + +// HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_keyboard_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// usb_composite_hid_keyboard_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 +#endif + +// HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_keyboard_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 +#endif + +// + +// HID Generic Support +// usb_composite_hid_generic_support +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN +#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 +#endif + +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT +#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ + 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ + 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ + 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 +#endif + +// HID Generic INTERRUPT IN Endpoint Address +// <0x81=> EndpointAddress = 0x81 +// <0x82=> EndpointAddress = 0x82 +// <0x83=> EndpointAddress = 0x83 +// <0x84=> EndpointAddress = 0x84 +// <0x85=> EndpointAddress = 0x85 +// <0x86=> EndpointAddress = 0x86 +// <0x87=> EndpointAddress = 0x87 +// usb_composite_hid_generic_intin_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 +#endif + +// HID Generic INTERRUPT IN Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_generic_intin_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 +#endif + +// HID Generic INTERRUPT OUT Endpoint Address +// <0x01=> EndpointAddress = 0x01 +// <0x02=> EndpointAddress = 0x02 +// <0x03=> EndpointAddress = 0x03 +// <0x04=> EndpointAddress = 0x04 +// <0x05=> EndpointAddress = 0x05 +// <0x06=> EndpointAddress = 0x06 +// <0x07=> EndpointAddress = 0x07 +// usb_composite_hid_generic_intout_epaddr +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 +#endif + +// HID Generic INTERRUPT OUT Endpoint wMaxPacketSize +// <0x0008=> 8 bytes +// <0x0010=> 16 bytes +// <0x0020=> 32 bytes +// <0x0040=> 64 bytes +// usb_composite_hid_generic_intout_maxpksz +// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. +#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ +#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 +#endif + +// + +// <<< end of configuration section >>> + +#endif // USBD_COMPOSITE_CONFIG_H diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.c b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.c new file mode 100644 index 0000000000000..2c7cd35847379 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.c @@ -0,0 +1,358 @@ +/** + * \file + * + * \brief USB Device Stack HID Generic Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hiddf_generic.h" +#include + +#define HIDDF_GENERIC_VERSION 0x00000001u + +/** USB Device HID Generic Function Specific Data */ +struct hiddf_generic_func_data { + /** HID Device Generic Interface information */ + uint8_t func_iface; + /** HID Device Generic IN Endpoint */ + uint8_t func_ep_in; + /** HID Device Generic OUT Endpoint */ + uint8_t func_ep_out; + /** HID Device Generic Report Descriptor */ + const uint8_t *report_desc; + /** HID Device Generic Report Descriptor Length */ + uint32_t report_desc_len; + /** HID Device Generic Enable Flag */ + bool enabled; +}; + +/* USB Device HID Generic Function Instance */ +static struct usbdf_driver _hiddf_generic; + +/* USB Device HID Generic Function Data Instance */ +static struct hiddf_generic_func_data _hiddf_generic_funcd; + +/* USB Device HID Generic Set Report Function Callback */ +static hiddf_generic_set_report_t hiddf_generic_set_report = NULL; + +/** + * \brief Enable HID Generic Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t hid_generic_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + uint8_t * ifc, *ep, i; + usb_iface_desc_t ifc_desc; + usb_ep_desc_t ep_desc; + + struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (HID_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + for (i = 0; i < 2; i++) { + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + desc->sod = ep; + if (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + } + } else { + return ERR_NOT_FOUND; + } + } + + // Installed + _hiddf_generic_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable HID Generic Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t hid_generic_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + if (ifc_desc.bInterfaceClass != HID_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + _hiddf_generic_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief HID Generic Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t hid_generic_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return hid_generic_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return hid_generic_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class get descriptor + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_generic_get_desc(uint8_t ep, struct usb_req *req) +{ + switch (req->wValue >> 8) { + case USB_DT_HID_REPORT: + return usbdc_xfer(ep, (uint8_t *)_hiddf_generic_funcd.report_desc, _hiddf_generic_funcd.report_desc_len, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_generic_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + uint8_t *ctrl_buf = usbdc_get_ctrl_buffer(); + uint16_t len = req->wLength; + + if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_generic_funcd.func_iface)) { + return hid_generic_get_desc(ep, req); + } else { + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if (req->wIndex == _hiddf_generic_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return ERR_INVALID_ARG; + } else { + if (USB_REQ_HID_SET_REPORT == req->bRequest) { + if (USB_SETUP_STAGE == stage) { + return usbdc_xfer(ep, ctrl_buf, len, false); + } else { + if (NULL != hiddf_generic_set_report) { + hiddf_generic_set_report(ctrl_buf, len); + } + return ERR_NONE; + } + } else { + return usbdc_xfer(0, NULL, 0, 0); + } + } + } else { + return ERR_NOT_FOUND; + } + } +} + +/** USB Device HID Generic Handler Struct */ +static struct usbdc_handler hid_generic_req_h = {NULL, (FUNC_PTR)hid_generic_req}; + +/** + * \brief Initialize the USB HID Generic Function Driver + */ +int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len) +{ + if (NULL == report_desc || 0 == len) { + return ERR_INVALID_ARG; + } + + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_generic_funcd.report_desc = report_desc; + _hiddf_generic_funcd.report_desc_len = len; + _hiddf_generic.ctrl = hid_generic_ctrl; + _hiddf_generic.func_data = &_hiddf_generic_funcd; + + usbdc_register_function(&_hiddf_generic); + usbdc_register_handler(USBDC_HDL_REQ, &hid_generic_req_h); + + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB HID Generic Function Driver + */ +int32_t hiddf_generic_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_generic.ctrl = NULL; + _hiddf_generic.func_data = NULL; + + usbdc_unregister_function(&_hiddf_generic); + usbdc_unregister_handler(USBDC_HDL_REQ, &hid_generic_req_h); + return ERR_NONE; +} + +/** + * \brief Check whether HID Generic Function is enabled + */ +bool hiddf_generic_is_enabled(void) +{ + return _hiddf_generic_funcd.enabled; +} + +/** + * \brief USB HID Generic Function Read Data + */ +int32_t hiddf_generic_read(uint8_t *buf, uint32_t size) +{ + if (!hiddf_generic_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_hiddf_generic_funcd.func_ep_out, buf, size, false); +} + +/** + * \brief USB HID Generic Function Write Data + */ +int32_t hiddf_generic_write(uint8_t *buf, uint32_t size) +{ + if (!hiddf_generic_is_enabled()) { + return ERR_DENIED; + } + return usbdc_xfer(_hiddf_generic_funcd.func_ep_in, buf, size, false); +} + +/** + * \brief USB HID Generic Function Register Callback + */ +int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func) +{ + if (!hiddf_generic_is_enabled()) { + return ERR_DENIED; + } + switch (cb_type) { + case HIDDF_GENERIC_CB_READ: + usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_out, USB_D_EP_CB_XFER, func); + break; + case HIDDF_GENERIC_CB_WRITE: + usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_in, USB_D_EP_CB_XFER, func); + break; + case HIDDF_GENERIC_CB_SET_REPORT: + hiddf_generic_set_report = (hiddf_generic_set_report_t)func; + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Return version + */ +uint32_t hiddf_generic_get_version(void) +{ + return HIDDF_GENERIC_VERSION; +} diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.h b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.h new file mode 100644 index 0000000000000..c12f1575ad86d --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.h @@ -0,0 +1,102 @@ +/** + * \file + * + * \brief USB Device Stack HID Generic Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_HID_GENERIC_H_ +#define USBDF_HID_GENERIC_H_ + +#include "usbdc.h" +#include "usb_protocol_hid.h" + +/** HID Generic Callback Type */ +enum hiddf_generic_cb_type { HIDDF_GENERIC_CB_READ, HIDDF_GENERIC_CB_WRITE, HIDDF_GENERIC_CB_SET_REPORT }; + +/** HID Generic Set Report Callback. */ +typedef bool (*hiddf_generic_set_report_t)(uint8_t *, uint16_t); + +/** + * \brief Initialize the USB HID Generic Function Driver + * \param[in] report_desc Point to usr HID Report Descriptor + * \param[in] len length of usr HID Report Descriptor + * \return Operation status. + */ +int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len); + +/** + * \brief Deinitialize the USB HID Generic Function Driver + * \return Operation status. + */ +int32_t hiddf_generic_deinit(void); + +/** + * \brief Check whether HID Generic Function is enabled + * \return Operation status. + * \return true HID Generic Function is enabled + * \return false HID Generic Function is disabled + */ +bool hiddf_generic_is_enabled(void); + +/** + * \brief USB HID Generic Function Read Data + * \param[in] buf Pointer to the buffer which receives data + * \param[in] size the size of data to be received + * \return Operation status. + */ +int32_t hiddf_generic_read(uint8_t *buf, uint32_t size); + +/** + * \brief USB HID Generic Function Write Data + * \param[in] buf Pointer to the buffer which stores data + * \param[in] size the size of data to be sent + * \return Operation status. + */ +int32_t hiddf_generic_write(uint8_t *buf, uint32_t size); + +/** + * \brief USB HID Generic Function Register Callback + * \param[in] cb_type Callback type of HID Generic Function + * \param[in] func Pointer to callback function + * \return Operation status. + */ +int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func); + +/** + * \brief Return version + */ +uint32_t hiddf_generic_get_version(void); + +#endif /* USBDF_HID_GENERIC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.c b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.c new file mode 100644 index 0000000000000..835481e416eae --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.c @@ -0,0 +1,365 @@ +/** + * \file + * + * \brief USB Device Stack HID Keyboard Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hiddf_keyboard.h" +#include + +#define HIDDF_KEYBOARD_VERSION 0x00000001u + +#define KEYBOARD_REPORT_DESC_LEN 59 + +/** USB Device HID Keyboard Function Specific Data */ +struct hiddf_keyboard_func_data { + /* HID Device Keyboard Report */ + uint8_t kb_report[8]; + /** HID Device Keyboard Interface information */ + uint8_t func_iface; + /** HID Device Keyboard IN Endpoint */ + uint8_t func_ep_in; + /** HID Device Keyboard OUT Endpoint */ + uint8_t func_ep_out; + /** HID Device Keyboard Enable Flag */ + bool enabled; +}; + +/* HID report descriptor for standard HID keyboard */ +const uint8_t keyboard_report_desc[KEYBOARD_REPORT_DESC_LEN] = { + 0x05, 0x01, /* Usage Page (Generic Desktop) */ + 0x09, 0x06, /* Usage (Keyboard) */ + 0xA1, 0x01, /* Collection (Application) */ + 0x05, 0x07, /* Usage Page (Keyboard) */ + 0x19, 0xE0, /* Usage Minimum (224) */ + 0x29, 0xE7, /* Usage Maximum (231) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x08, /* Report Count (8) */ + 0x81, 0x02, /* Input (Data, Variable, Absolute) */ + 0x81, 0x01, /* Input (Constant) */ + 0x19, 0x00, /* Usage Minimum (0) */ + 0x29, 0x65, /* Usage Maximum (101) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x65, /* Logical Maximum (101) */ + 0x75, 0x08, /* Report Size (8) */ + 0x95, 0x06, /* Report Count (6) */ + 0x81, 0x00, /* Input (Data, Array) */ + 0x05, 0x08, /* Usage Page (LED) */ + 0x19, 0x01, /* Usage Minimum (1) */ + 0x29, 0x05, /* Usage Maximum (5) */ + 0x15, 0x00, /* Logical Minimum (0) */ + 0x25, 0x01, /* Logical Maximum (1) */ + 0x75, 0x01, /* Report Size (1) */ + 0x95, 0x05, /* Report Count (5) */ + 0x91, 0x02, /* Output (Data, Variable, Absolute) */ + 0x95, 0x03, /* Report Count (3) */ + 0x91, 0x01, /* Output (Constant) */ + 0xC0 /* End Collection */ +}; + +/* USB Device HID Keyboard Function Instance */ +static struct usbdf_driver _hiddf_keyboard; + +/* USB Device HID Keyboard Function Data Instance */ +static struct hiddf_keyboard_func_data _hiddf_keyboard_funcd; + +/** + * \brief Enable HID Keyboard Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t hid_keyboard_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + uint8_t * ifc, *ep, i; + usb_iface_desc_t ifc_desc; + usb_ep_desc_t ep_desc; + + struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (HID_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + for (i = 0; i < 2; i++) { + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + desc->sod = ep; + if (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + } else { + func_data->func_ep_out = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_out); + } + } else { + return ERR_NOT_FOUND; + } + } + + // Installed + _hiddf_keyboard_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable HID Keyboard Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t hid_keyboard_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + if (ifc_desc.bInterfaceClass != HID_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + if (func_data->func_ep_out != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_out); + func_data->func_ep_out = 0xFF; + } + + _hiddf_keyboard_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief HID Keyboard Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t hid_keyboard_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return hid_keyboard_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return hid_keyboard_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class get descriptor + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_keyboard_get_desc(uint8_t ep, struct usb_req *req) +{ + switch (req->wValue >> 8) { + case USB_DT_HID_REPORT: + return usbdc_xfer(ep, (uint8_t *)keyboard_report_desc, KEYBOARD_REPORT_DESC_LEN, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_keyboard_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_keyboard_funcd.func_iface)) { + return hid_keyboard_get_desc(ep, req); + } else { + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if (req->wIndex == _hiddf_keyboard_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return ERR_INVALID_ARG; + } else { + return usbdc_xfer(0, NULL, 0, 0); + } + } else { + return ERR_NOT_FOUND; + } + } + (void)stage; +} + +/** USB Device HID Keyboard Handler Struct */ +static struct usbdc_handler hid_keyboard_req_h = {NULL, (FUNC_PTR)hid_keyboard_req}; + +/** + * \brief Initialize the USB HID Keyboard Function Driver + */ +int32_t hiddf_keyboard_init(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_keyboard.ctrl = hid_keyboard_ctrl; + _hiddf_keyboard.func_data = &_hiddf_keyboard_funcd; + + usbdc_register_function(&_hiddf_keyboard); + usbdc_register_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB HID Keyboard Function Driver + */ +int32_t hiddf_keyboard_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_keyboard.ctrl = NULL; + _hiddf_keyboard.func_data = NULL; + + usbdc_unregister_function(&_hiddf_keyboard); + usbdc_unregister_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); + return ERR_NONE; +} + +/** + * \brief Check whether HID Keyboard Function is enabled + */ +bool hiddf_keyboard_is_enabled(void) +{ + return _hiddf_keyboard_funcd.enabled; +} + +/** + * \brief Process the HID Keyboard key state change request + * \param keys_desc[] keys_descriptor array for state changing + * \param keys_count total keys amount for state changing + * \return Operation status. + */ +int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count) +{ + uint8_t i, j; + uint8_t modifier_keys, regular_keys; + + if (!hiddf_keyboard_is_enabled()) { + return ERR_DENIED; + } + + memset(_hiddf_keyboard_funcd.kb_report, 0x00, 8); + modifier_keys = 0; + + for (i = 0; i < keys_count; i++) { + if (true == keys_desc[i].b_modifier) { + modifier_keys++; + } + } + + regular_keys = keys_count - modifier_keys; + + if (regular_keys > 6) { + memset(&_hiddf_keyboard_funcd.kb_report[2], 0xFF, 6); + } else { + i = 2; + for (j = 0; j < keys_count; j++) { + if (HID_KB_KEY_DOWN == keys_desc[j].state) { + if (true == keys_desc[j].b_modifier) { + _hiddf_keyboard_funcd.kb_report[0] |= keys_desc[j].key_id; + } else { + _hiddf_keyboard_funcd.kb_report[i++] = keys_desc[j].key_id; + } + } + } + } + return usbdc_xfer(_hiddf_keyboard_funcd.func_ep_in, &_hiddf_keyboard_funcd.kb_report[0], 8, false); +} + +/** + * \brief Return version + */ +uint32_t hiddf_keyboard_get_version(void) +{ + return HIDDF_KEYBOARD_VERSION; +} diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.h b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.h new file mode 100644 index 0000000000000..3295d1b785a3f --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.h @@ -0,0 +1,91 @@ +/** + * \file + * + * \brief USB Device Stack HID Keyboard Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_HID_KEYBOARD_H_ +#define USBDF_HID_KEYBOARD_H_ + +#include "usbdc.h" +#include "usb_protocol_hid.h" + +/** HID Keyboard Class Key State Type */ +enum hiddf_kb_key_state { HID_KB_KEY_UP, HID_KB_KEY_DOWN }; + +/** Describes the USB HID Keyboard Key descriptors. */ +struct hiddf_kb_key_descriptors { + /* HID Key Value, defined in usb_protocol_hid.h */ + uint8_t key_id; + /* Flag whether it is a modifier key */ + bool b_modifier; + /* Key State */ + enum hiddf_kb_key_state state; +}; + +/** + * \brief Initialize the USB HID Keyboard Function Driver + * \return Operation status. + */ +int32_t hiddf_keyboard_init(void); + +/** + * \brief Deinitialize the USB HID Keyboard Function Driver + * \return Operation status. + */ +int32_t hiddf_keyboard_deinit(void); + +/** + * \brief Check whether HID Keyboard Function is enabled + * \return Operation status. + * \return true HID Keyboard Function is enabled + * \return false HID Keyboard Function is disabled + */ +bool hiddf_keyboard_is_enabled(void); + +/** + * \brief Process the HID Keyboard key state change request + * \param keys_desc[] keys_descriptor array for state changing + * \param keys_count total keys amount for state changing + * \return Operation status. + */ +int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count); + +/** + * \brief Return version + */ +uint32_t hiddf_keyboard_get_version(void); + +#endif /* USBDF_HID_KEYBOARD_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.c b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.c new file mode 100644 index 0000000000000..7a58ce66e0824 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.c @@ -0,0 +1,363 @@ +/** + * \file + * + * \brief USB Device Stack HID Mouse Function Implementation. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "hiddf_mouse.h" + +#define HIDDF_MOUSE_VERSION 0x00000001u + +#define MOUSE_REPORT_DESC_LEN 52 + +/** USB Device HID Mouse Function Specific Data */ +struct hiddf_mouse_func_data { + /* HID Device Mouse Report */ + union { + /** Interpreted by bytes. */ + struct { + /** Button Status. */ + uint8_t button_state; + /** X Axis Variant.*/ + uint8_t x_axis_var; + /** Y Axis Variant.*/ + uint8_t y_axis_var; + /** Scroll Variant.*/ + uint8_t scroll_var; + } bytes; + uint32_t u32; + } mouse_report; + /** HID Device Mouse Interface information */ + uint8_t func_iface; + /** HID Device Mouse IN Endpoint */ + uint8_t func_ep_in; + /** HID Device Mouse Enable Flag */ + bool enabled; +}; + +/* HID report descriptor for standard HID mouse */ +const uint8_t mouse_report_desc[MOUSE_REPORT_DESC_LEN] = { + 0x05, 0x01, /* Usage Page (Generic Desktop), */ + 0x09, 0x02, /* Usage (Mouse), */ + 0xA1, 0x01, /* Collection (Application), */ + 0x09, 0x01, /* Usage (Pointer), */ + 0xA1, 0x00, /* Collection (Physical), */ + 0x05, 0x09, /* Usage Page (Buttons), */ + 0x19, 0x01, /* Usage Minimum (01), */ + 0x29, 0x03, /* Usage Maximum (03), */ + 0x15, 0x00, /* Logical Minimum (0), */ + 0x25, 0x01, /* Logical Maximum (1), */ + 0x75, 0x01, /* Report Size (1), */ + 0x95, 0x03, /* Report Count (3), */ + 0x81, 0x02, /* Input (Data, Variable, Absolute) */ + 0x75, 0x05, /* Report Size (5), */ + 0x95, 0x01, /* Report Count (1), */ + 0x81, 0x01, /* Input (Constant), */ + 0x05, 0x01, /* Usage Page (Generic Desktop), */ + 0x09, 0x30, /* Usage (X), */ + 0x09, 0x31, /* Usage (Y), */ + 0x09, 0x38, /* Usage (Scroll), */ + 0x15, 0x81, /* Logical Minimum (-127), */ + 0x25, 0x7F, /* Logical Maximum (127), */ + 0x75, 0x08, /* Report Size (8), */ + 0x95, 0x03, /* Report Count (3), */ + 0x81, 0x06, /* Input (Data, Variable, Relative) */ + 0xC0, /* End Collection, */ + 0xC0, /* End Collection */ +}; + +/* USB Device HID Mouse Function Instance */ +static struct usbdf_driver _hiddf_mouse; + +/* USB Device HID Mouse Function Data Instance */ +static struct hiddf_mouse_func_data _hiddf_mouse_funcd; + +/** + * \brief Enable HID Mouse Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB interface descriptor + * \return Operation status. + */ +static int32_t hid_mouse_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + uint8_t * ifc, *ep; + usb_iface_desc_t ifc_desc; + usb_ep_desc_t ep_desc; + + struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); + + ifc = desc->sod; + if (NULL == ifc) { + return ERR_NOT_FOUND; + } + + ifc_desc.bInterfaceNumber = ifc[2]; + ifc_desc.bInterfaceClass = ifc[5]; + + if (HID_CLASS == ifc_desc.bInterfaceClass) { + if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized + return ERR_ALREADY_INITIALIZED; + } else if (func_data->func_iface != 0xFF) { // Occupied + return ERR_NO_RESOURCE; + } else { + func_data->func_iface = ifc_desc.bInterfaceNumber; + } + } else { // Not supported by this function driver + return ERR_NOT_FOUND; + } + + // Install endpoints + ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); + desc->sod = ep; + if (NULL != ep) { + ep_desc.bEndpointAddress = ep[2]; + ep_desc.bmAttributes = ep[3]; + ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); + if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { + return ERR_NOT_INITIALIZED; + } + if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { + func_data->func_ep_in = ep_desc.bEndpointAddress; + usb_d_ep_enable(func_data->func_ep_in); + } else { + return ERR_INVALID_DATA; + } + } else { + return ERR_NOT_FOUND; + } + // Installed + _hiddf_mouse_funcd.enabled = true; + return ERR_NONE; +} + +/** + * \brief Disable HID Mouse Function + * \param[in] drv Pointer to USB device function driver + * \param[in] desc Pointer to USB device descriptor + * \return Operation status. + */ +static int32_t hid_mouse_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) +{ + struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); + + usb_iface_desc_t ifc_desc; + + if (desc) { + ifc_desc.bInterfaceClass = desc->sod[5]; + if (ifc_desc.bInterfaceClass != HID_CLASS) { + return ERR_NOT_FOUND; + } + } + + if (func_data->func_iface != 0xFF) { + func_data->func_iface = 0xFF; + } + + if (func_data->func_ep_in != 0xFF) { + usb_d_ep_deinit(func_data->func_ep_in); + func_data->func_ep_in = 0xFF; + } + + _hiddf_mouse_funcd.enabled = false; + return ERR_NONE; +} + +/** + * \brief HID Mouse Control Function + * \param[in] drv Pointer to USB device function driver + * \param[in] ctrl USB device general function control type + * \param[in] param Parameter pointer + * \return Operation status. + */ +static int32_t hid_mouse_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) +{ + switch (ctrl) { + case USBDF_ENABLE: + return hid_mouse_enable(drv, (struct usbd_descriptors *)param); + + case USBDF_DISABLE: + return hid_mouse_disable(drv, (struct usbd_descriptors *)param); + + case USBDF_GET_IFACE: + return ERR_UNSUPPORTED_OP; + + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class get descriptor + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_mouse_get_desc(uint8_t ep, struct usb_req *req) +{ + switch (req->wValue >> 8) { + case USB_DT_HID_REPORT: + return usbdc_xfer(ep, (uint8_t *)mouse_report_desc, MOUSE_REPORT_DESC_LEN, false); + default: + return ERR_INVALID_ARG; + } +} + +/** + * \brief Process the HID class request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + */ +static int32_t hid_mouse_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_mouse_funcd.func_iface)) { + return hid_mouse_get_desc(ep, req); + } else { + if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request + return ERR_NOT_FOUND; + } + if (req->wIndex == _hiddf_mouse_funcd.func_iface) { + if (req->bmRequestType & USB_EP_DIR_IN) { + return ERR_INVALID_ARG; + } else { + return usbdc_xfer(0, NULL, 0, 0); + } + } else { + return ERR_NOT_FOUND; + } + } + (void)stage; +} + +/** USB Device HID Mouse Handler Struct */ +static struct usbdc_handler hid_mouse_req_h = {NULL, (FUNC_PTR)hid_mouse_req}; + +/** + * \brief Initialize the USB HID Mouse Function Driver + */ +int32_t hiddf_mouse_init(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_mouse.ctrl = hid_mouse_ctrl; + _hiddf_mouse.func_data = &_hiddf_mouse_funcd; + + usbdc_register_function(&_hiddf_mouse); + usbdc_register_handler(USBDC_HDL_REQ, &hid_mouse_req_h); + return ERR_NONE; +} + +/** + * \brief Deinitialize the USB HID Mouse Function Driver + */ +int32_t hiddf_mouse_deinit(void) +{ + if (usbdc_get_state() > USBD_S_POWER) { + return ERR_DENIED; + } + + _hiddf_mouse.ctrl = NULL; + _hiddf_mouse.func_data = NULL; + + usbdc_unregister_function(&_hiddf_mouse); + usbdc_unregister_handler(USBDC_HDL_REQ, &hid_mouse_req_h); + return ERR_NONE; +} + +/** + * \brief Check whether HID Mouse Function is enabled + */ +bool hiddf_mouse_is_enabled(void) +{ + return _hiddf_mouse_funcd.enabled; +} + +/** + * \brief Move the mouse pointer + * \param pos Signed value to move + * \param type HID mouse class pointer move type + * \return Operation status. + */ +int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type) +{ + + _hiddf_mouse_funcd.mouse_report.u32 = 0; + + if (type == HID_MOUSE_X_AXIS_MV) { + _hiddf_mouse_funcd.mouse_report.bytes.x_axis_var = pos; + } else if (type == HID_MOUSE_Y_AXIS_MV) { + _hiddf_mouse_funcd.mouse_report.bytes.y_axis_var = pos; + } else if (type == HID_MOUSE_SCROLL_MV) { + _hiddf_mouse_funcd.mouse_report.bytes.scroll_var = pos; + } else { + return ERR_INVALID_ARG; + } + + return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); +} + +/** + * \brief Changes button state + * \param b_state New button state + * \param type Button type + * \return Operation status. + */ +int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type) +{ + _hiddf_mouse_funcd.mouse_report.u32 = 0; + + if (b_state == HID_MOUSE_BTN_DOWN) { + _hiddf_mouse_funcd.mouse_report.bytes.button_state = type; + } else { + _hiddf_mouse_funcd.mouse_report.bytes.button_state = 0x00; + } + + return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); +} + +/** + * \brief Return version + */ +uint32_t hiddf_mouse_get_version(void) +{ + return HIDDF_MOUSE_VERSION; +} diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.h b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.h new file mode 100644 index 0000000000000..464b1e92dfbf7 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief USB Device Stack HID Mouse Function Definition. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef USBDF_HID_MOUSE_H_ +#define USBDF_HID_MOUSE_H_ + +#include "usbdc.h" +#include "usb_protocol_hid.h" + +/** HID Mouse Class Button State Type */ +enum hiddf_mouse_button_state { HID_MOUSE_BTN_UP, HID_MOUSE_BTN_DOWN }; + +/* HID Mosue Class Button Type */ +enum hiddf_mouse_button_type { HID_MOUSE_LEFT_BTN = 0x01, HID_MOUSE_RIGHT_BTN = 0x02, HID_MOUSE_MIDDLE_BTN = 0x04 }; + +/* HID Mouse Class Pointer Move Type */ +enum hiddf_mouse_move_type { HID_MOUSE_X_AXIS_MV = 0x01, HID_MOUSE_Y_AXIS_MV = 0x02, HID_MOUSE_SCROLL_MV = 0x03 }; + +/** + * \brief Initialize the USB HID Mouse Function Driver + * \return Operation status. + */ +int32_t hiddf_mouse_init(void); + +/** + * \brief Deinitialize the USB HID Mouse Function Driver + * \return Operation status. + */ +int32_t hiddf_mouse_deinit(void); + +/** + * \brief Check whether HID Mouse Function is enabled + * \return Operation status. + * \return true HID Mouse Function is enabled + * \return false HID Mouse Function is disabled + */ +bool hiddf_mouse_is_enabled(void); + +/** + * \brief Move the mouse pointer + * \param pos Signed value to move + * \param type HID mouse class pointer move type + * \return Operation status. + */ +int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type); + +/** + * \brief Changes button state + * \param b_state New button state + * \param type Button type + * \return Operation status. + */ +int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type); + +/** + * \brief Return version + */ +uint32_t hiddf_mouse_get_version(void); + +#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/hid/usb_protocol_hid.h b/atmel-samd/asf4/samd51/usb/class/hid/usb_protocol_hid.h new file mode 100644 index 0000000000000..71d74e632d30f --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hid/usb_protocol_hid.h @@ -0,0 +1,597 @@ +/** + * \file + * + * \brief USB Human Interface Device (HID) protocol definitions. + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _USB_PROTOCOL_HID_H_ +#define _USB_PROTOCOL_HID_H_ + +#include "usb_includes.h" + +/** + * \ingroup usb_protocol_group + * \defgroup usb_hid_protocol USB Human Interface Device (HID) + * protocol definitions + * \brief USB Human Interface Device (HID) protocol definitions + * + * @{ + */ + +//! \name Possible Class value +//@{ +#define HID_CLASS 0x03 +//@} + +//! \name Possible SubClass value +//@{ +//! Interface subclass NO support BOOT protocol +#define HID_SUB_CLASS_NOBOOT 0x00 +//! Interface subclass support BOOT protocol +#define HID_SUB_CLASS_BOOT 0x01 +//@} + +//! \name Possible protocol value +//@{ +//! Protocol generic standard +#define HID_PROTOCOL_GENERIC 0x00 +//! Protocol keyboard standard +#define HID_PROTOCOL_KEYBOARD 0x01 +//! Protocol mouse standard +#define HID_PROTOCOL_MOUSE 0x02 +//@} + +//! \brief Hid USB requests (bRequest) + +#define USB_REQ_HID_GET_REPORT 0x01 +#define USB_REQ_HID_GET_IDLE 0x02 +#define USB_REQ_HID_GET_PROTOCOL 0x03 +#define USB_REQ_HID_SET_REPORT 0x09 +#define USB_REQ_HID_SET_IDLE 0x0A +#define USB_REQ_HID_SET_PROTOCOL 0x0B + +//! \brief HID USB descriptor types +#define USB_DT_HID 0x21 +#define USB_DT_HID_REPORT 0x22 +#define USB_DT_HID_PHYSICAL 0x23 + +//! \brief HID Type for report descriptor +#define USB_HID_ITEM_REPORT_TYPE_MAIN 0 +#define USB_HID_ITEM_REPORT_TYPE_GLOBAL 1 +#define USB_HID_ITEM_REPORT_TYPE_LOCAL 2 +#define USB_HID_ITEM_REPORT_TYPE_LONG 3 + +//! \brief HID report type +#define USB_HID_REPORT_TYPE_INPUT 1 +#define USB_HID_REPORT_TYPE_OUTPUT 2 +#define USB_HID_REPORT_TYPE_FEATURE 3 + +//! \brief HID protocol +#define USB_HID_PROCOTOL_BOOT 0 +#define USB_HID_PROCOTOL_REPORT 1 + +#define USB_HID_DESC_BYTES(bLength, bCountryCode, bNumDescriptors, bDescriptorType, bDescriptorLength) \ + bLength, 0x21, 0x10, 0x01, bCountryCode, bNumDescriptors, bDescriptorType, LE_BYTE0(bDescriptorLength), \ + LE_BYTE1(bDescriptorLength) + +COMPILER_PACK_SET(1) + +//! \brief HID Descriptor +typedef struct usb_hid_descriptor { + uint8_t bLength; //!< Size of this descriptor in bytes + uint8_t bDescriptorType; //!< HID descriptor type + le16_t bcdHID; //!< Binary Coded Decimal Spec. release + uint8_t bCountryCode; //!< Hardware target country + uint8_t bNumDescriptors; //!< Number of HID class descriptors to follow + uint8_t bRDescriptorType; //!< Report descriptor type + le16_t wDescriptorLength; //!< Total length of Report descriptor +} usb_hid_descriptor_t; + +COMPILER_PACK_RESET() + +//! \name HID Report type +//! Used by SETUP_HID_GET_REPORT & SETUP_HID_SET_REPORT +//! @{ +#define REPORT_TYPE_INPUT 0x01 +#define REPORT_TYPE_OUTPUT 0x02 +#define REPORT_TYPE_FEATURE 0x03 +//! @} + +//! \name Constants of field DESCRIPTOR_HID +//! @{ +//! Numeric expression identifying the HID Class +//! Specification release (here V1.11) +#define USB_HID_BDC_V1_11 0x0111 +//! Numeric expression specifying the number of class descriptors +//! Note: Always at least one i.e. Report descriptor. +#define USB_HID_NUM_DESC 0x01 + +//! \name Country code +//! @{ +#define USB_HID_NO_COUNTRY_CODE 0 // Not Supported +#define USB_HID_COUNTRY_ARABIC 1 // Arabic +#define USB_HID_COUNTRY_BELGIAN 2 // Belgian +#define USB_HID_COUNTRY_CANADIAN_BILINGUAL 3 // Canadian-Bilingual +#define USB_HID_COUNTRY_CANADIAN_FRENCH 4 // Canadian-French +#define USB_HID_COUNTRY_CZECH_REPUBLIC 5 // Czech Republic +#define USB_HID_COUNTRY_DANISH 6 // Danish +#define USB_HID_COUNTRY_FINNISH 7 // Finnish +#define USB_HID_COUNTRY_FRENCH 8 // French +#define USB_HID_COUNTRY_GERMAN 9 // German +#define USB_HID_COUNTRY_GREEK 10 // Greek +#define USB_HID_COUNTRY_HEBREW 11 // Hebrew +#define USB_HID_COUNTRY_HUNGARY 12 // Hungary +#define USB_HID_COUNTRY_INTERNATIONAL_ISO 13 // International (ISO) +#define USB_HID_COUNTRY_ITALIAN 14 // Italian +#define USB_HID_COUNTRY_JAPAN_KATAKANA 15 // Japan (Katakana) +#define USB_HID_COUNTRY_KOREAN 16 // Korean +#define USB_HID_COUNTRY_LATIN_AMERICAN 17 // Latin American +#define USB_HID_COUNTRY_NETHERLANDS_DUTCH 18 // Netherlands/Dutch +#define USB_HID_COUNTRY_NORWEGIAN 19 // Norwegian +#define USB_HID_COUNTRY_PERSIAN_FARSI 20 // Persian (Farsi) +#define USB_HID_COUNTRY_POLAND 21 // Poland +#define USB_HID_COUNTRY_PORTUGUESE 22 // Portuguese +#define USB_HID_COUNTRY_RUSSIA 23 // Russia +#define USB_HID_COUNTRY_SLOVAKIA 24 // Slovakia +#define USB_HID_COUNTRY_SPANISH 25 // Spanish +#define USB_HID_COUNTRY_SWEDISH 26 // Swedish +#define USB_HID_COUNTRY_SWISS_FRENCH 27 // Swiss/French +#define USB_HID_COUNTRY_SWISS_GERMAN 28 // Swiss/German +#define USB_HID_COUNTRY_SWITZERLAND 29 // Switzerland +#define USB_HID_COUNTRY_TAIWAN 30 // Taiwan +#define USB_HID_COUNTRY_TURKISH_Q 31 // Turkish-Q +#define USB_HID_COUNTRY_UK 32 // UK +#define USB_HID_COUNTRY_US 33 // US +#define USB_HID_COUNTRY_YUGOSLAVIA 34 // Yugoslavia +#define USB_HID_COUNTRY_TURKISH_F 35 // Turkish-F + //! @} + //! @} +//! @} + +//! \name HID KEYS values +//! @{ +#define HID_A 0x04 +#define HID_B 0x05 +#define HID_C 0x06 +#define HID_D 0x07 +#define HID_E 0x08 +#define HID_F 0x09 +#define HID_G 0x0A +#define HID_H 0x0B +#define HID_I 0x0C +#define HID_J 0x0D +#define HID_K 0x0E +#define HID_L 0x0F +#define HID_M 0x10 +#define HID_N 0x11 +#define HID_O 0x12 +#define HID_P 0x13 +#define HID_Q 0x14 +#define HID_R 0x15 +#define HID_S 0x16 +#define HID_T 0x17 +#define HID_U 0x18 +#define HID_V 0x19 +#define HID_W 0x1A +#define HID_X 0x1B +#define HID_Y 0x1C +#define HID_Z 0x1D +#define HID_1 30 +#define HID_2 31 +#define HID_3 32 +#define HID_4 33 +#define HID_5 34 +#define HID_6 35 +#define HID_7 36 +#define HID_8 37 +#define HID_9 38 +#define HID_0 39 +#define HID_ENTER 40 +#define HID_ESCAPE 41 +#define HID_BACKSPACE 42 +#define HID_TAB 43 +#define HID_SPACEBAR 44 +#define HID_UNDERSCORE 45 +#define HID_PLUS 46 +#define HID_OPEN_BRACKET 47 // { +#define HID_CLOSE_BRACKET 48 // } +#define HID_BACKSLASH 49 +#define HID_ASH 50 // # ~ +#define HID_COLON 51 // ; : +#define HID_QUOTE 52 // ' " +#define HID_TILDE 53 +#define HID_COMMA 54 +#define HID_DOT 55 +#define HID_SLASH 56 +#define HID_CAPS_LOCK 57 +#define HID_F1 58 +#define HID_F2 59 +#define HID_F3 60 +#define HID_F4 61 +#define HID_F5 62 +#define HID_F6 63 +#define HID_F7 64 +#define HID_F8 65 +#define HID_F9 66 +#define HID_F10 67 +#define HID_F11 68 +#define HID_F12 69 +#define HID_PRINTSCREEN 70 +#define HID_SCROLL_LOCK 71 +#define HID_PAUSE 72 +#define HID_INSERT 73 +#define HID_HOME 74 +#define HID_PAGEUP 75 +#define HID_DELETE 76 +#define HID_END 77 +#define HID_PAGEDOWN 78 +#define HID_RIGHT 79 +#define HID_LEFT 80 +#define HID_DOWN 81 +#define HID_UP 82 +#define HID_KEYPAD_NUM_LOCK 83 +#define HID_KEYPAD_DIVIDE 84 +#define HID_KEYPAD_AT 85 +#define HID_KEYPAD_MULTIPLY 85 +#define HID_KEYPAD_MINUS 86 +#define HID_KEYPAD_PLUS 87 +#define HID_KEYPAD_ENTER 88 +#define HID_KEYPAD_1 89 +#define HID_KEYPAD_2 90 +#define HID_KEYPAD_3 91 +#define HID_KEYPAD_4 92 +#define HID_KEYPAD_5 93 +#define HID_KEYPAD_6 94 +#define HID_KEYPAD_7 95 +#define HID_KEYPAD_8 96 +#define HID_KEYPAD_9 97 +#define HID_KEYPAD_0 98 + +//! \name HID modifier values +//! @{ +#define HID_MODIFIER_NONE 0x00 +#define HID_MODIFIER_LEFT_CTRL 0x01 +#define HID_MODIFIER_LEFT_SHIFT 0x02 +#define HID_MODIFIER_LEFT_ALT 0x04 +#define HID_MODIFIER_LEFT_UI 0x08 +#define HID_MODIFIER_RIGHT_CTRL 0x10 +#define HID_MODIFIER_RIGHT_SHIFT 0x20 +#define HID_MODIFIER_RIGHT_ALT 0x40 +#define HID_MODIFIER_RIGHT_UI 0x80 +//! @} +//! @} + +//! \name HID KEYS LED values +//! @{ +#define HID_LED_NUM_LOCK (1 << 0) +#define HID_LED_CAPS_LOCK (1 << 1) +#define HID_LED_SCROLL_LOCK (1 << 2) +#define HID_LED_COMPOSE (1 << 3) +#define HID_LED_KANA (1 << 4) +//! @} + +/** \name Standard HID mouse definitions from HID spec. example */ +/*@{*/ + +/** \brief Structure for standard HID keyboard modified keys */ +typedef union hid_kbd_modifier { + uint8_t byte; + struct { + uint8_t lctrl : 1; /**< Left Ctrl */ + uint8_t lshift : 1; /**< Left Shift */ + uint8_t lalt : 1; /**< Left Alt */ + uint8_t lgui : 1; /**< Left Gui */ + uint8_t rctrl : 1; /**< Right Ctrl */ + uint8_t rshift : 1; /**< Right Shift */ + uint8_t ralt : 1; /**< Right Alt */ + uint8_t rgui : 1; /**< Right Gui */ + } bm; +} hid_kbd_modifier_t; +#define HID_KBD_L_CTRL (1 << 0) /**< Left Ctrl */ +#define HID_KBD_L_SHIFT (1 << 1) /**< Left Shift */ +#define HID_KBD_L_ALT (1 << 2) /**< Left Alt */ +#define HID_KBD_L_GUI (1 << 3) /**< Left Gui */ +#define HID_KBD_R_CTRL (1 << 4) /**< Right Ctrl */ +#define HID_KBD_R_SHIFT (1 << 5) /**< Right Shift */ +#define HID_KBD_R_ALT (1 << 6) /**< Right Alt */ +#define HID_KBD_R_GUI (1 << 7) /**< Right Gui */ + +/** \brief Structure for standard HID keyboard input report */ +typedef union hid_kbd_input_report { + uint8_t byte[8]; + struct { + union hid_kbd_modifier modifier; + uint8_t reserved_oem; + uint8_t key[6]; /** < Key array */ + } field; +} hid_kbd_input_report_t; +/** Access to the modifier keys in HID keyboard report + * \param rpt Pointer to report data of bytes + */ +#define hid_kbd_modifier_keys(rpt) (rpt[0]) +/** Access to the OEM reserved in HID keyboard report + * \param rpt Pointer to report data of bytes + */ +#define hid_kbd_oem(rpt) (rpt[1]) +/** Access to the Key code in HID keyboard report + * \param rpt Pointer to report data of bytes + * \param i Index in the report key array (0~n) + */ +#define hid_kbd_keycode(rpt, i) (rpt[2 + i]) + +/** \brief Structure for standard HID keyboard output report */ +typedef union hid_kbd_output_report { + uint8_t byte; + struct { + uint8_t num_lock : 1; /**< LED of Num Lock */ + uint8_t caps_lock : 1; /**< LED of Caps Lock */ + uint8_t scroll_lock : 1; /**< LED of Scroll Lock */ + uint8_t compose : 1; /**< LED of COMPOSE LOCK */ + uint8_t kana : 1; /**< LED of KANA */ + uint8_t constant : 3; + } field; +} hid_kbd_output_report_t; +#define HID_KBD_NUM_LOCK (1 << 0) /**< LED of Num Lock */ +#define HID_KBD_CAPS_LOCK (1 << 1) /**< LED of Caps Lock */ +#define HID_KBD_SCROLL_LOCK (1 << 2) /**< LED of Scroll Lock */ +#define HID_KBD_COMPOSE (1 << 3) /**< LED of COMPOSE LOCK */ +#define HID_KBD_KANA (1 << 4) /**< LED of KANA */ + +/*@}*/ + +/** \name Standard HID mouse definitions from HID spec. example */ +/*@{*/ +/** \brief Structure for standard HID mouse report */ +typedef union hid_mouse_report { + uint8_t byte[3]; + struct { + uint8_t btn1 : 1; /**< Button 1 */ + uint8_t btn2 : 2; /**< Button 2 */ + uint8_t btn3 : 3; /**< Button 3 */ + uint8_t device_spec : 5; + int8_t x; /**< X displacement */ + int8_t y; /**< Y displacement */ + } field; + /* More bytes are optional */ +} hid_mouse_report_t; +#define HID_MOUSE_BTN1 (1 << 0) /**< Button 1 */ +#define HID_MOUSE_BTN2 (1 << 1) /**< Button 2 */ +#define HID_MOUSE_BTN3 (1 << 2) /**< Button 3 */ + +/** Access to the button state in HID mouse report + * \param rpt Pointer to report data of bytes + */ +#define hid_mouse_btn_state(rpt) (rpt[0]) +/** Check if the button is done in HID mouse report + * \param rpt Pointer to report data of bytes + * \param btn Button bitmap to check + */ +#define hid_mouse_is_btn_down(rpt, btn) (rpt[0] & (btn)) +/** Access to the relative X displacement in HID mouse report + * \param rpt Pointer to report data of bytes + */ +#define hid_mouse_x(rpt) ((int8_t)rpt[1]) +/** Access to the relative Y displacement in HID mouse report + * \param rpt Pointer to report data of bytes + */ +#define hid_mouse_y(rpt) ((int8_t)rpt[2]) + +/*@}*/ + +/** \name Standard HID joystick definitions from HID spec. example */ +/*@{*/ + +/** \brief Structure for standard HID joystick report */ +typedef union hid_joystick_report { + uint8_t byte[4]; + struct { + int8_t x; + int8_t y; + uint8_t hat_sw : 4; /**< Hat switch */ + uint8_t btn1 : 1; /**< Button 1 */ + uint8_t btn2 : 1; /**< Button 2 */ + uint8_t btn3 : 1; /**< Button 3 */ + uint8_t btn4 : 1; /**< Button 4 */ + uint8_t throttle; + } field; +} hid_joystick_report_t; +#define HID_JOYSTICK_BTN1 (1 << 4) /**< Button 1 */ +#define HID_JOYSTICK_BTN2 (1 << 5) /**< Button 2 */ +#define HID_JOYSTICK_BTN3 (1 << 6) /**< Button 3 */ +#define HID_JOYSTICK_BTN4 (1 << 7) /**< Button 4 */ + +/** Access to the absolute X position in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_x(rpt) ((int8_t)rpt[0]) +/** Access to the absolute Y position in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_y(rpt) ((int8_t)rpt[1]) +/** Access to the button state in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_btn_state(rpt) (rpt[2]) +/** Check if the button is done in HID joystick report + * \param rpt Pointer to report data of bytes + * \param btn Button bitmap to check + */ +#define hid_joystick_is_btn_down(rpt, btn) (rpt[2] & (btn)) +/** Get the Hat switch in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_hat_sw(rpt) (rpt[2] & 0xF) +/** Access to the throttle in HID joystick report + * \param rpt Pointer to report data of bytes + */ +#define hid_joystick_throttle(rpt) (rpt[3]) + +/*@}*/ + +/** + * \brief Fill a GetHIDDescriptor request + * \param[out] req Pointer to the request to fill + * \param[in] type Descriptor type + * \param[in] index Descriptor index + * \param[in] iface Interface Number + * \param[in] len Descriptor Length + */ +static inline void usb_fill_GetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, + uint16_t len) +{ + req->bmRequestType = 0x81; + req->bRequest = USB_REQ_GET_DESC; + req->wValue = (type << 8) | index; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a SetHIDDescriptor request + * \param[out] req Pointer to the request to fill + * \param[in] type Descriptor type + * \param[in] index Descriptor index + * \param[in] iface Interface Number + * \param[in] len Descriptor Length + */ +static inline void usb_fill_SetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, + uint16_t len) +{ + req->bmRequestType = 0x01; + req->bRequest = USB_REQ_SET_DESC; + req->wValue = (type << 8) | index; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a GetReport request + * \param[out] req Pointer to the request to fill + * \param[in] type Report type + * \param[in] id Report ID + * \param[in] iface Interface Number + * \param[in] len Report Length + */ +static inline void usb_fill_GetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_HID_GET_REPORT; + req->wValue = (type << 8) | id; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a SetReport request + * \param[out] req Pointer to the request to fill + * \param[in] type Report type + * \param[in] id Report ID + * \param[in] iface Interface Number + * \param[in] len Report Length + */ +static inline void usb_fill_SetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_HID_GET_REPORT; + req->wValue = (type << 8) | id; + req->wIndex = iface; + req->wLength = len; +} + +/** + * \brief Fill a GetIdle request + * \param[out] req Pointer to the request to fill + * \param[in] id Report ID + * \param[in] iface Interface Number + */ +static inline void usb_fill_GetIdle_req(struct usb_req *req, uint8_t id, uint8_t iface) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_HID_GET_IDLE; + req->wValue = id; + req->wIndex = iface; + req->wLength = 1; +} + +/** + * \brief Fill a SetIdle request + * \param[out] req Pointer to the request to fill + * \param[in] duration Duration value + * \param[in] id Report ID + * \param[in] iface Interface Number + */ +static inline void usb_fill_SetIdle_req(struct usb_req *req, uint8_t duration, uint8_t id, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_HID_SET_IDLE; + req->wValue = (duration << 8) | id; + req->wIndex = iface; + req->wLength = 0; +} + +/** + * \brief Fill a GetProtocol request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_GetProtocol_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_HID_GET_PROTOCOL; + req->wValue = 0; + req->wIndex = iface; + req->wLength = 1; +} + +/** + * \brief Fill a SetProtocol request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_SetProtocol_req(struct usb_req *req, uint8_t protocol, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_HID_SET_PROTOCOL; + req->wValue = protocol; + req->wIndex = iface; + req->wLength = 0; +} + +#endif // _USB_PROTOCOL_HID_H_ diff --git a/atmel-samd/asf4/samd51/usb/class/hub/usb_protocol_hub.h b/atmel-samd/asf4/samd51/usb/class/hub/usb_protocol_hub.h new file mode 100644 index 0000000000000..dbfc04a2cbb3a --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/hub/usb_protocol_hub.h @@ -0,0 +1,364 @@ +/** + * \file + * + * \brief USB hub protocol definitions. + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _USB_PROTOCOL_HUB_H_ +#define _USB_PROTOCOL_HUB_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** \name Possible class value */ +/*@{*/ +#define HUB_CLASS 0x09 +/*@}*/ + +/** \brief Hub USB requests (bRequest) */ +enum usb_reqid_hub { + USB_REQ_HUB_GET_STATUS = 0, + /** CLEAR_FEATURE */ + USB_REQ_HUB_CLR_FTR = 1, + /** SET_FEATURE */ + USB_REQ_HUB_SET_FTR = 3, + /** GET_DESCRIPTOR */ + USB_REQ_HUB_GET_DESC = 6, + /** SET_DESCRIPTOR */ + USB_REQ_HUB_SET_DESC = 7, + /** CLEAR_TT_BUFFER */ + USB_REQ_HUB_CLR_TT_BUF = 8, + /** RESET_TT */ + USB_REQ_HUB_RESET_TT = 9, + /** GET_TT_STATE */ + USB_REQ_HUB_GET_TT_STATE = 10, + /** STOP_TT */ + USB_REQ_HUB_STOP_TT +}; + +/** \brief Hub USB descriptor type */ +enum usb_descriptor_type_hub { USB_DT_HUB = 0x29 }; + +/** \brief Hub feature selector */ +enum usb_hub_ftr_sel { + USB_HUB_FTR_C_HUB_LOCAL_POWER = 0, + USB_HUB_FTR_C_HUB_OVER_CURRENT = 1, + USB_HUB_FTR_PORT_CONNECTION = 0, + USB_HUB_FTR_PORT_ENABLE = 1, + USB_HUB_FTR_PORT_SUSPEND = 2, + USB_HUB_FTR_PORT_OVER_CURRENT = 3, + USB_HUB_FTR_PORT_RESET = 4, + USB_HUB_FTR_PORT_POWER = 8, + USB_HUB_FTR_PORT_LOW_SPEED = 9, + USB_HUB_FTR_PORT_LS = 9, + USB_HUB_FTR_PORT_HIGH_SPEED = 10, + USB_HUB_FTR_PORT_HS = 10, + USB_HUB_FTR_C_PORT_CONNECTION = 16, + USB_HUB_FTR_C_PORT_ENABLE = 17, + USB_HUB_FTR_C_PORT_SUSPEND = 18, + USB_HUB_FTR_C_PORT_OVER_CURRENT = 19, + USB_HUB_FTR_C_PORT_RESET = 20, + USB_HUB_FTR_PORT_TEST = 21, + USB_HUB_FTR_PORT_INDICATOR +}; + +COMPILER_PACK_SET(1) + +/** + * \brief General Hub Descriptor + */ +typedef struct usb_hub_descriptor { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint32_t variables[1]; +} usb_hub_descriptor_t; + +/** + * \brief Hub Descriptor with no more than 7 ports + */ +typedef struct usb_hub_descriptor_7p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[1]; + uint8_t PortPwrCtrlMask[1]; +} usb_hub_descriptor_7p_t; + +/** + * \brief Hub Descriptor with no more than 15 ports + */ +typedef struct usb_hub_descriptor_15p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[2]; + uint8_t PortPwrCtrlMask[2]; +} usb_hub_descriptor_15p_t; + +/** + * \brief Hub Descriptor with no more than 23 ports + */ +typedef struct usb_hub_descriptor_23p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[3]; + uint8_t PortPwrCtrlMask[3]; +} usb_hub_descriptor_23p_t; + +/** + * \brief Hub Descriptor with no more than 31 ports + */ +typedef struct usb_hub_descriptor_31p { + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable[4]; + uint8_t PortPwrCtrlMask[4]; +} usb_hub_descriptor_31p_t; + +COMPILER_PACK_RESET() + +/** + * \brief Check if hub change is detected + * \param[in] bitmap Pointer to the bitmap location + * \return \c true if hub change is detected + */ +static inline bool usb_is_hub_change_detected(const uint8_t *bitmap) +{ + return (*bitmap & 0x1); +} + +/** + * \brief Check if port change is detected + * \param[in] bitmap Pointer to the bitmap location + * \param[in] port Port number ( 1 ~ n ) + * \return \c true if port change is detected + */ +static inline bool usb_is_port_change_detected(const uint8_t *bitmap, const uint8_t port) +{ + uint8_t idx = port >> 3; + uint8_t pos = port & 0x7; + return (bitmap[idx] & (1u << pos)); +} + +/** + * \brief Fill a ClearHubFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + */ +static inline void usb_fill_ClrHubFtr_req(struct usb_req *req, uint8_t ftr) +{ + req->bmRequestType = 0x20; + req->bRequest = USB_REQ_CLEAR_FTR; + req->wValue = ftr; + req->wIndex = 0; + req->wLength = 0; +} + +/** + * \brief Fill a ClearPortFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_ClrPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_CLEAR_FTR; + req->wValue = ftr; + req->wIndex = port; + req->wLength = 0; +} + +/** + * \brief Fill a ClearTTBuffer request + * \param[out] req Pointer to the request to fill + * \param[in] dev Dev_Addr + * \param[in] ep EP_Num + * \param[in] tt_port TT_port + */ +static inline void usb_fill_ClrTTBuf_req(struct usb_req *req, uint8_t dev, uint8_t ep, uint8_t tt_port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_HUB_CLR_TT_BUF; + req->wValue = (dev << 8) | ep; + req->wIndex = tt_port; + req->wLength = 0; +} + +/** + * \brief Fill a GetHubDescriptor request + * \param[out] req Pointer to the request to fill + * \param[in] len Length of available buffer for request data + */ +static inline void usb_fill_GetHubDesc_req(struct usb_req *req, uint16_t len) +{ + req->bmRequestType = 0xA0; + req->bRequest = USB_REQ_GET_DESC; + req->wValue = (USB_DT_HUB << 8) | 0; + req->wIndex = 0; + req->wLength = len; +} + +/** + * \brief Fill a GetHubStatus request + * \param[out] req Pointer to the request to fill + */ +static inline void usb_fill_GetHubStatus_req(struct usb_req *req) +{ + req->bmRequestType = 0xA0; + req->bRequest = USB_REQ_GET_STATUS; + req->wValue = 0; + req->wIndex = 0; + req->wLength = 4; +} + +/** + * \brief Fill a GetPortStatus request + * \param[out] req Pointer to the request to fill + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_GetPortStatus_req(struct usb_req *req, uint8_t port) +{ + req->bmRequestType = 0xA3; + req->bRequest = USB_REQ_GET_STATUS; + req->wValue = 0; + req->wIndex = port; + req->wLength = 4; +} + +/** + * \brief Fill a ResetTT request + * \param[out] req Pointer to the request to fill + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_ResetTT_req(struct usb_req *req, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_HUB_RESET_TT; + req->wValue = 0; + req->wIndex = port; + req->wLength = 0; +} + +/** + * \brief Fill a SetHubFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + */ +static inline void usb_fill_SetHubFtr_req(struct usb_req *req, uint8_t ftr) +{ + req->bmRequestType = 0x20; + req->bRequest = USB_REQ_SET_FTR; + req->wValue = ftr; + req->wIndex = 0; + req->wLength = 0; +} + +/** + * \brief Fill a SetPortFeature request + * \param[out] req Pointer to the request to fill + * \param[in] ftr Feature selector + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_SetPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_SET_FTR; + req->wValue = ftr; + req->wIndex = port; + req->wLength = 0; +} + +/** + * \brief Fill a GetTTState request + * \param[out] req Pointer to the request to fill + * \param[in] tt_flags TT_Flags + * \param[in] port Port number ( 1 ~ n ) + * \param[in] len TT State Length + */ +static inline void usb_fill_GetTTState_req(struct usb_req *req, uint16_t tt_flags, uint8_t port, uint16_t len) +{ + req->bmRequestType = 0xA3; + req->bRequest = USB_REQ_HUB_GET_TT_STATE; + req->wValue = tt_flags; + req->wIndex = port; + req->wLength = len; +} + +/** + * \brief Fill a StopTT request + * \param[out] req Pointer to the request to fill + * \param[in] port Port number ( 1 ~ n ) + */ +static inline void usb_fill_StopTT_req(struct usb_req *req, uint8_t port) +{ + req->bmRequestType = 0x23; + req->bRequest = USB_REQ_HUB_STOP_TT; + req->wValue = 0; + req->wIndex = port; + req->wLength = 0; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _USB_PROTOCOL_HUB_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/msc/sbc_protocol.h b/atmel-samd/asf4/samd51/usb/class/msc/sbc_protocol.h new file mode 100644 index 0000000000000..9259335228d0c --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/msc/sbc_protocol.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SCSI Block Commands + * + * This file contains definitions of some of the commands found in the + * SCSI SBC-2 standard. + * + * Note that the SBC specification depends on several commands defined + * by the SCSI Primary Commands (SPC) standard. Each version of the SBC + * standard is meant to be used in conjunction with a specific version + * of the SPC standard, as follows: + * - SBC depends on SPC + * - SBC-2 depends on SPC-3 + * - SBC-3 depends on SPC-4 + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _SBC_PROTOCOL_H_ +#define _SBC_PROTOCOL_H_ + +/** + * \ingroup usb_msc_protocol + * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions + * + * @{ + */ + +/** \name SCSI commands defined by SBC-2 */ +#define SBC_FORMAT_UNIT 0x04 +#define SBC_READ6 0x08 +#define SBC_WRITE6 0x0A +#define SBC_START_STOP_UNIT 0x1B +#define SBC_READ_CAPACITY10 0x25 +#define SBC_READ10 0x28 +#define SBC_WRITE10 0x2A +#define SBC_VERIFY10 0x2F + +/** \name SBC-2 Mode page definitions */ +enum scsi_sbc_mode { + SCSI_MS_MODE_RW_ERR_RECOV = 0x01, /**< Read-Write Error Recovery mode page */ + SCSI_MS_MODE_FORMAT_DEVICE = 0x03, /**< Format Device mode page */ + SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, /**< Flexible Disk mode page */ + SCSI_MS_MODE_CACHING = 0x08 +}; + +/** \name SBC-2 Device-Specific Parameter */ +#define SCSI_MS_SBC_WP 0x80 /**< Write Protected */ +#define SCSI_MS_SBC_DPOFUA 0x10 /**< DPO and FUA supported */ + +/** + * \brief SBC-2 Short LBA mode parameter block descriptor + * \note Fields are MSB first (BE) + */ +struct sbc_slba_block_desc { + be32_t nr_blocks; /**< Number of Blocks (BE32) */ + be32_t block_len; /**< Block Length (BE32) */ +#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU /**< Mask reserved bits */ +}; + +/** + * \brief SBC-2 Caching mode page + * \note Fields are MSB first (BE) + */ +struct sbc_caching_mode_page { + uint8_t page_code; + uint8_t page_length; + uint8_t flags2; +#define SBC_MP_CACHE_IC (1 << 7) /**< Initiator Control */ +#define SBC_MP_CACHE_ABPF (1 << 6) /**< Abort Pre-Fetch */ +#define SBC_MP_CACHE_CAP (1 << 5) /**< Catching Analysis Permitted */ +#define SBC_MP_CACHE_DISC (1 << 4) /**< Discontinuity */ +#define SBC_MP_CACHE_SIZE (1 << 3) /**< Size enable */ +#define SBC_MP_CACHE_WCE (1 << 2) /**< Write back Cache Enable */ +#define SBC_MP_CACHE_MF (1 << 1) /**< Multiplication Factor */ +#define SBC_MP_CACHE_RCD (1 << 0) /**< Read Cache Disable */ + uint8_t retention; + be16_t dis_pf_transfer_len; + be16_t min_prefetch; + be16_t max_prefetch; + be16_t max_prefetch_ceil; + uint8_t flags12; +#define SBC_MP_CACHE_FSW (1 << 7) /**< Force Sequential Write */ +#define SBC_MP_CACHE_LBCSS (1 << 6) /**< Logical Blk Cache Seg Sz */ +#define SBC_MP_CACHE_DRA (1 << 5) /**< Disable Read-Ahead */ +#define SBC_MP_CACHE_NV_DIS (1 << 0) /**< Non-Volatile Cache Disable */ + uint8_t nr_cache_segments; + be16_t cache_segment_size; + uint8_t reserved[4]; +}; + +/** + * \brief SBC-2 Read-Write Error Recovery mode page + * \note Fields are MSB first (BE) + */ +struct sbc_rdwr_error_recovery_mode_page { + uint8_t page_code; + uint8_t page_length; +#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A + uint8_t flags1; +#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7) +#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6) +#define SBC_MP_RW_ERR_RECOV_TB (1 << 5) +#define SBC_MP_RW_ERR_RECOV_RC (1 << 4) +#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3) +#define SBC_MP_RW_ERR_RECOV_PER (1 << 2) +#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1) +#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0) + uint8_t read_retry_count; + uint8_t correction_span; + uint8_t head_offset_count; + uint8_t data_strobe_offset_count; + uint8_t flags2; + uint8_t write_retry_count; + uint8_t flags3; + be16_t recovery_time_limit; +}; + +/** + * \brief SBC-2 READ CAPACITY (10) parameter data (8 bytes) + * \note Fields are MSB first (BE) + */ +struct sbc_read_capacity10_data { + be32_t max_lba; /**< LBA of last logical block (BE32) */ + be32_t block_len; /**< Number of bytes in the last logical block (BE32) */ +}; + +#endif /*_SBC_PROTOCOL_H_*/ diff --git a/atmel-samd/asf4/samd51/usb/class/msc/spc_protocol.h b/atmel-samd/asf4/samd51/usb/class/msc/spc_protocol.h new file mode 100644 index 0000000000000..c44cbef32bd02 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/msc/spc_protocol.h @@ -0,0 +1,340 @@ +/** + * \file + * + * \brief SCSI Primary Commands + * + * This file contains definitions of some of the commands found in the + * SPC-2 standard. + * + * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +#ifndef _SPC_PROTOCOL_H_ +#define _SPC_PROTOCOL_H_ + +/** + * \ingroup usb_msc_protocol + * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions + * + * + */ + +/**< \name SCSI commands defined by SPC-2 */ +#define SPC_TEST_UNIT_READY 0x00 +#define SPC_REQUEST_SENSE 0x03 +#define SPC_INQUIRY 0x12 +#define SPC_MODE_SELECT6 0x15 +#define SPC_MODE_SENSE6 0x1A +#define SPC_SEND_DIAGNOSTIC 0x1D +#define SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +#define SPC_MODE_SENSE10 0x5A +#define SPC_REPORT_LUNS 0xA0 + +/**< \brief May be set in byte 0 of the INQUIRY CDB */ +/**< Enable Vital Product Data */ +#define SCSI_INQ_REQ_EVPD 0x01 +/**< Command Support Data specified by the PAGE OR OPERATION CODE field */ +#define SCSI_INQ_REQ_CMDT 0x02 + +COMPILER_PACK_SET(1) + +/** + * \brief SCSI Standard Inquiry data structure + */ +struct scsi_inquiry_data { + uint8_t pq_pdt; /**< Peripheral Qual / Peripheral Dev Type */ +#define SCSI_INQ_PQ_CONNECTED 0x00 /**< Peripheral connected */ +#define SCSI_INQ_PQ_NOT_CONN 0x20 /**< Peripheral not connected */ +#define SCSI_INQ_PQ_NOT_SUPP 0x60 /**< Peripheral not supported */ +#define SCSI_INQ_DT_DIR_ACCESS 0x00 /**< Direct Access (SBC) */ +#define SCSI_INQ_DT_SEQ_ACCESS 0x01 /**< Sequential Access */ +#define SCSI_INQ_DT_PRINTER 0x02 /**< Printer */ +#define SCSI_INQ_DT_PROCESSOR 0x03 /**< Processor device */ +#define SCSI_INQ_DT_WRITE_ONCE 0x04 /**< Write-once device */ +#define SCSI_INQ_DT_CD_DVD 0x05 /**< CD/DVD device */ +#define SCSI_INQ_DT_OPTICAL 0x07 /**< Optical Memory */ +#define SCSI_INQ_DT_MC 0x08 /**< Medium Changer */ +#define SCSI_INQ_DT_ARRAY 0x0c /**< Storage Array Controller */ +#define SCSI_INQ_DT_ENCLOSURE 0x0d /**< Enclosure Services */ +#define SCSI_INQ_DT_RBC 0x0e /**< Simplified Direct Access */ +#define SCSI_INQ_DT_OCRW 0x0f /**< Optical card reader/writer */ +#define SCSI_INQ_DT_BCC 0x10 /**< Bridge Controller Commands */ +#define SCSI_INQ_DT_OSD 0x11 /**< Object-based Storage */ +#define SCSI_INQ_DT_NONE 0x1f /**< No Peripheral */ + uint8_t flags1; /**< Flags (byte 1) */ +#define SCSI_INQ_RMB 0x80 /**< Removable Medium */ + uint8_t version; /**< Version */ +#define SCSI_INQ_VER_NONE 0x00 /**< No standards conformance */ +#define SCSI_INQ_VER_SPC 0x03 /**< SCSI Primary Commands (link to SBC) */ +#define SCSI_INQ_VER_SPC2 0x04 /**< SCSI Primary Commands - 2 (link to SBC-2) */ +#define SCSI_INQ_VER_SPC3 0x05 /**< SCSI Primary Commands - 3 (link to SBC-2) */ +#define SCSI_INQ_VER_SPC4 0x06 /**< SCSI Primary Commands - 4 (link to SBC-3) */ + uint8_t flags3; /**< Flags (byte 3) */ +#define SCSI_INQ_NORMACA 0x20 /**< Normal ACA Supported */ +#define SCSI_INQ_HISUP 0x10 /**< Hierarchal LUN addressing */ +#define SCSI_INQ_RSP_SPC2 0x02 /**< SPC-2 / SPC-3 response format */ + uint8_t addl_len; /**< Additional Length (n-4) */ +#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) /**< Total length is \a tot */ + uint8_t flags5; /**< Flags (byte 5) */ +#define SCSI_INQ_SCCS 0x80 + uint8_t flags6; /**< Flags (byte 6) */ +#define SCSI_INQ_BQUE 0x80 +#define SCSI_INQ_ENCSERV 0x40 +#define SCSI_INQ_MULTIP 0x10 +#define SCSI_INQ_MCHGR 0x08 +#define SCSI_INQ_ADDR16 0x01 + uint8_t flags7; /**< Flags (byte 7) */ +#define SCSI_INQ_WBUS16 0x20 +#define SCSI_INQ_SYNC 0x10 +#define SCSI_INQ_LINKED 0x08 +#define SCSI_INQ_CMDQUE 0x02 + uint8_t vendor_id[8]; /**< T10 Vendor Identification */ + uint8_t product_id[16]; /**< Product Identification */ + uint8_t product_rev[4]; /**< Product Revision Level */ +}; + +/** + * \brief SCSI Standard Request sense data structure + */ +#define SCSI_SENSE_VALID 0x80 /**< Indicates the INFORMATION field contains valid information */ +#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F +#define SCSI_SENSE_CURRENT 0x70 /**< Response code 70h (current errors) */ +#define SCSI_SENSE_DEFERRED 0x71 + +#define SCSI_SENSE_FILEMARK 0x80 /**< Indicates that the current command has read a filemark or setmark. */ +#define SCSI_SENSE_EOM 0x40 /**< Indicates that an end-of-medium condition exists. */ +#define SCSI_SENSE_ILI \ + 0x20 /**< Indicates that the requested logical block length did not match the logical block length of the data on \ + the medium. */ +#define SCSI_SENSE_RESERVED 0x10 /**< Reserved */ +#define SCSI_SENSE_KEY(x) (x & 0x0F) /**< Sense Key */ + +#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len)-8) + +#define SCSI_SENSE_SKSV 0x80 /**< Indicates the SENSE-KEY SPECIFIC field contains valid information */ + +struct scsi_request_sense_data { + /** 1st byte: REQUEST SENSE response flags*/ + uint8_t valid_reponse_code; + /** 2nd byte */ + uint8_t obsolete; + /** 3rd byte */ + uint8_t sense_flag_key; + /** 4th to 7th bytes - INFORMATION field */ + uint8_t information[4]; + /** 8th byte - ADDITIONAL SENSE LENGTH field */ + uint8_t AddSenseLen; + /** 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */ + uint8_t CmdSpecINFO[4]; + /** 13th to 14th byte - ADDITIONAL SENSE CODE and QUALIFIER field */ + union { + struct { + uint8_t code; /**< ADDITIONAL SENSE CODE (ASC) */ + uint8_t qualifier; /**< ADDITIONAL SENSE CODE QUALIFIER (ASCQ) */ + } add_sense; + be16_t AddSense; /**< ASC | ASCQ */ + }; + /** 15th byte - FIELD REPLACEABLE UNIT CODE field */ + uint8_t FldReplUnitCode; + /** 16th byte */ + uint8_t SenseKeySpec[3]; +}; + +COMPILER_PACK_RESET() + +/**< Vital Product Data page codes */ +enum scsi_vpd_page_code { + SCSI_VPD_SUPPORTED_PAGES = 0x00, + SCSI_VPD_UNIT_SERIAL_NUMBER = 0x80, + SCSI_VPD_DEVICE_IDENTIFICATION = 0x83 +}; +#define SCSI_VPD_HEADER_SIZE 4 + +/**< Constants associated with the Device Identification VPD page */ +#define SCSI_VPD_ID_HEADER_SIZE 4 + +#define SCSI_VPD_CODE_SET_BINARY 1 +#define SCSI_VPD_CODE_SET_ASCII 2 +#define SCSI_VPD_CODE_SET_UTF8 3 + +#define SCSI_VPD_ID_TYPE_T10 1 + +/**< Sense keys */ +enum scsi_sense_key { + SCSI_SK_NO_SENSE = 0x0, + SCSI_SK_RECOVERED_ERROR = 0x1, + SCSI_SK_NOT_READY = 0x2, + SCSI_SK_MEDIUM_ERROR = 0x3, + SCSI_SK_HARDWARE_ERROR = 0x4, + SCSI_SK_ILLEGAL_REQUEST = 0x5, + SCSI_SK_UNIT_ATTENTION = 0x6, + SCSI_SK_DATA_PROTECT = 0x7, + SCSI_SK_BLANK_CHECK = 0x8, + SCSI_SK_VENDOR_SPECIFIC = 0x9, + SCSI_SK_COPY_ABORTED = 0xa, + SCSI_SK_ABORTED_COMMAND = 0xb, + SCSI_SK_VOLUME_OVERFLOW = 0xd, + SCSI_SK_MISCOMPARE = 0xe +}; + +/**< Additional Sense Code | Additional Sense Code Qualifier pairs (BE16) */ +enum scsi_asc_ascq { + SCSI_ASC_NO_ADDITIONAL_SENSE_INFO = 0x0000, + SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405, + SCSI_ASC_WRITE_ERROR = 0x0c00, + SCSI_ASC_UNRECOVERED_READ_ERROR = 0x1100, + SCSI_ASC_INVALID_COMMAND_OPERATION_CODE = 0x2000, + SCSI_ASC_INVALID_FIELD_IN_CDB = 0x2400, + SCSI_ASC_WRITE_PROTECTED = 0x2700, + SCSI_ASC_NOT_READY_TO_READY_CHANGE = 0x2800, + SCSI_ASC_MEDIUM_NOT_PRESENT = 0x3A00, + SCSI_ASC_INTERNAL_TARGET_FAILURE = 0x4400 +}; + +/** + * \brief SPC-2 Mode parameter + * This subclauses describes the block descriptors and the pages + * used with MODE SELECT and MODE SENSE commands + * that are applicable to all SCSI devices. + */ +enum scsi_spc_mode { + SCSI_MS_MODE_VENDOR_SPEC = 0x00, + SCSI_MS_MODE_INFEXP = 0x1C, /**< Informational exceptions control page */ + SCSI_MS_MODE_ALL = 0x3f +}; + +/** + * \brief SPC-2 Informational exceptions control page + * See chapter 8.3.8 + * \note Fields are MSB first (BE) + */ +struct spc_control_page_info_execpt { + uint8_t page_code; + uint8_t page_length; +#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A + uint8_t flags1; +#define SPC_MP_INFEXP_PERF (1 << 7) /**< Initiator Control */ +#define SPC_MP_INFEXP_EBF (1 << 5) /**< Caching Analysis Permitted */ +#define SPC_MP_INFEXP_EWASC (1 << 4) /**< Discontinuity */ +#define SPC_MP_INFEXP_DEXCPT (1 << 3) /**< Size enable */ +#define SPC_MP_INFEXP_TEST (1 << 2) /**< Write-back Cache Enable */ +#define SPC_MP_INFEXP_LOGERR (1 << 0) /**< Log errors bit */ + uint8_t mrie; +#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00 +#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01 +#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02 +#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03 +#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04 +#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05 +#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06 + be32_t interval_timer; + be32_t report_count; +}; + +enum scsi_spc_mode_sense_pc { + SCSI_MS_SENSE_PC_CURRENT = 0, + SCSI_MS_SENSE_PC_CHANGEABLE = 1, + SCSI_MS_SENSE_PC_DEFAULT = 2, + SCSI_MS_SENSE_PC_SAVED = 3 +}; + +/** + * \brief Check whether dbd field is set in sense code + * \param[in] cdb pointer to the sense code block + * \return Operation status. + */ +static inline bool scsi_mode_sense_dbd_is_set(const uint8_t *cdb) +{ + return (cdb[1] >> 3) & 1; +} + +/** + * \brief Get page code from mode sense code + * \param[in] cdb pointer to the sense code block + * \return Operation status. + */ +static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t *cdb) +{ + return cdb[2] & 0x3f; +} + +/** + * \brief Get pc from mode sense code + * \param[in] cdb pointer to the sense code block + * \return Operation status. + */ +static inline uint8_t scsi_mode_sense_get_pc(const uint8_t *cdb) +{ + return cdb[2] >> 6; +} + +/** + * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE SENSE(6) + * \note Fields are MSB first (BE) + */ +struct scsi_mode_param_header6 { + uint8_t mode_data_length; /**< Number of bytes after this */ + uint8_t medium_type; /**< Medium Type */ + uint8_t device_specific_parameter; /**< Defined by command set */ + uint8_t block_descriptor_length; /**< Length of block descriptors */ +}; + +/** + * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE SENSE(10) + * \note Fields are MSB first (BE) + */ +struct scsi_mode_param_header10 { + le16_t mode_data_length; /**< Number of bytes after this */ + uint8_t medium_type; /**< Medium Type */ + uint8_t device_specific_parameter; /**< Defined by command set */ + uint8_t flags4; /**< LONGLBA in bit 0 */ + uint8_t reserved; + le16_t block_descriptor_length; /**< Length of block descriptors */ +}; + +/** + * \brief SCSI Page_0 Mode Page header (SPF not set) + */ +struct scsi_mode_page_0_header { + uint8_t page_code; +#define SCSI_PAGE_CODE_PS (1 << 7) /**< Parameters Savable */ +#define SCSI_PAGE_CODE_SPF (1 << 6) /**< SubPage Format */ + uint8_t page_length; /**< Number of bytes after this */ +#define SCSI_MS_PAGE_LEN(total) ((total)-2) +}; + +#endif /**< SPC_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/msc/usb_protocol_msc.h b/atmel-samd/asf4/samd51/usb/class/msc/usb_protocol_msc.h new file mode 100644 index 0000000000000..f69eae232eb0b --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/msc/usb_protocol_msc.h @@ -0,0 +1,177 @@ +/** + * \file + * + * \brief USB Mass Storage Class (MSC) protocol definitions. + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#ifndef _USB_PROTOCOL_MSC_H_ +#define _USB_PROTOCOL_MSC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \ingroup usb_protocol_group + * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions + * + * @{ + */ + +/** + * \name Possible Class value + */ +//@{ +#define MSC_CLASS 0x08 +//@} + +/** + * \name Possible SubClass value + * \note In practice, most devices should use + * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in + * the standard INQUIRY data block, even if the MSC spec indicates + * otherwise. In particular, RBC is not supported by certain major + * operating systems like Windows XP. + */ +//@{ +#define MSC_SUBCLASS_RBC 0x01 /**< Reduced Block Commands */ +#define MSC_SUBCLASS_ATAPI 0x02 /**< CD/DVD devices */ +#define MSC_SUBCLASS_QIC_157 0x03 /**< Tape devices */ +#define MSC_SUBCLASS_UFI 0x04 /**< Floppy disk drives */ +#define MSC_SUBCLASS_SFF_8070I 0x05 /**< Floppy disk drives */ +#define MSC_SUBCLASS_TRANSPARENT 0x06 /**< Determined by INQUIRY */ + //@} + +/** + * \name Possible protocol value + * \note Only the BULK protocol should be used in new designs. + */ +//@{ +#define MSC_PROTOCOL_CBI 0x00 /**< Command/Bulk/Interrupt */ +#define MSC_PROTOCOL_CBI_ALT 0x01 /**< W/o command completion */ +#define MSC_PROTOCOL_BULK 0x50 /**< Bulk-only */ + //@} + +/** + * \brief MSC USB requests (bRequest) + */ + +#define USB_REQ_MSC_BULK_RESET 0xFF /**< Mass Storage Reset */ +#define USB_REQ_MSC_GET_MAX_LUN 0xFE /**< Get Max LUN */ + +COMPILER_PACK_SET(1) + +/** + * \name A Command Block Wrapper (CBW) + * \note Fields are LSB first (LE) + */ +//@{ +struct usb_msc_cbw { + le32_t dCBWSignature; /**< Must contain 'USBC' (0x43425355, LE32) */ + le32_t dCBWTag; /**< Unique command ID (LE32) */ + le32_t dCBWDataTransferLength; /**< Number of bytes to transfer (LE32) */ + uint8_t bmCBWFlags; /**< Direction in bit 7 */ + uint8_t bCBWLUN; /**< Logical Unit Number */ + uint8_t bCBWCBLength; /**< Number of valid CDB bytes */ + uint8_t CDB[16]; /**< SCSI Command Descriptor Block */ +}; + +#define USB_CBW_SIGNATURE 0x43425355 /**< dCBWSignature value */ +#define USB_CBW_DIRECTION_IN (1 << 7) /**< Data from device to host */ +#define USB_CBW_DIRECTION_OUT (0 << 7) /**< Data from host to device */ +#define USB_CBW_LUN_MASK 0x0F /**< Valid bits in bCBWLUN */ +#define USB_CBW_LEN_MASK 0x1F /**< Valid bits in bCBWCBLength */ + //@} + +/** + * \name A Command Status Wrapper (CSW) + * \note Fields are LSB first (LE) + */ +//@{ +struct usb_msc_csw { + le32_t dCSWSignature; /**< Must contain 'USBS' */ + le32_t dCSWTag; /**< Same as dCBWTag */ + le32_t dCSWDataResidue; /**< Number of bytes not transfered */ + uint8_t bCSWStatus; /**< Status code */ +}; + +#define USB_CSW_SIGNATURE 0x53425355 /**< dCSWSignature value */ +#define USB_CSW_STATUS_PASS 0x00 /**< Command Passed */ +#define USB_CSW_STATUS_FAIL 0x01 /**< Command Failed */ +#define USB_CSW_STATUS_PE 0x02 /**< Phase Error */ +//@} + +COMPILER_PACK_RESET() + +//@} + +/** + * \brief Fill a Bulk-Only Mass Storage Reset request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_BOMSReset_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0x21; + req->bRequest = USB_REQ_MSC_BULK_RESET; + req->wValue = 0; + req->wIndex = iface; + req->wLength = 0; +} + +/** + * \brief Fill a GetMaxLUN request + * \param[out] req Pointer to the request to fill + * \param[in] iface Interface Number + */ +static inline void usb_fill_GetMaxLUN_req(struct usb_req *req, uint8_t iface) +{ + req->bmRequestType = 0xA1; + req->bRequest = USB_REQ_MSC_GET_MAX_LUN; + req->wValue = 0; + req->wIndex = iface; + req->wLength = 1; +} + +#ifdef __cplusplus +} +#endif + +#endif // _USB_PROTOCOL_MSC_H_ diff --git a/atmel-samd/asf4/samd51/usb/class/vendor/usb_protocol_vendor.h b/atmel-samd/asf4/samd51/usb/class/vendor/usb_protocol_vendor.h new file mode 100644 index 0000000000000..e865fb808e7bc --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/class/vendor/usb_protocol_vendor.h @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief USB Vendor class protocol definitions. + * + * Copyright (c) 2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _USB_PROTOCOL_VENDOR_H_ +#define _USB_PROTOCOL_VENDOR_H_ + +/** + * \ingroup usb_protocol_group + * \defgroup usb_vendor_protocol USB Vendor Class definitions + * + */ + +/** + * \name Vendor class values + */ +#define VENDOR_CLASS 0xFF +#define VENDOR_SUBCLASS 0xFF +#define VENDOR_PROTOCOL 0xFF + +#endif /* _USB_PROTOCOL_VENDOR_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/device/usbdc.c b/atmel-samd/asf4/samd51/usb/device/usbdc.c new file mode 100644 index 0000000000000..f5243cad03196 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/device/usbdc.c @@ -0,0 +1,836 @@ +/** + * \file + * + * \brief USB Device Stack Core Layer Implementation. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel micro controller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ + +#include "usbdc.h" + +#define USBDC_VERSION 0x00000001u + +/** + * \brief USB Device Core Sof Handler + */ +struct usbdc_sof_handler { + struct usbdc_sof_handler *next; + usbdc_sof_cb_t cb; +}; + +/** + * \brief USB Device Core Request Handler + */ +struct usbdc_req_handler { + struct usbdc_req_handler *next; + usbdc_req_cb_t cb; +}; + +/** + * \brief USB Device Core Change Handler + */ +struct usbdc_change_handler { + struct usbdc_change_handler *next; + usbdc_change_cb_t cb; +}; + +/** + * \brief USB Device Core Handler + */ +struct usbdc_handlers { + struct list_descriptor sof_list; + struct list_descriptor req_list; + struct list_descriptor change_list; +}; + +/** + * \brief USB Device Core Driver Structure + */ +struct usbdc_driver { + /** Pointer to descriptions of descriptors. */ + struct usbdc_descriptors desces; + /** Callback handlers. */ + struct usbdc_handlers handlers; + /** list of function drivers. */ + struct list_descriptor func_list; + /** Control buffer. */ + uint8_t *ctrl_buf; + /** Device status. */ + uint16_t status; + /** Device state. */ + uint8_t state; + /** Configuration value. */ + uint8_t cfg_value; + /** Control endpoint size. */ + uint8_t ctrl_size; +}; + +/** + * \brief USB Device Core Driver Instance + */ +static struct usbdc_driver usbdc; + +/** + * \brief Process the GetDescriptor request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_desc_req(const uint8_t ep, struct usb_req *req) +{ + uint8_t *cfg_desc, *str_desc; + uint16_t total_len; + uint16_t length = req->wLength; + uint8_t type = (uint8_t)(req->wValue >> 8); + uint8_t index = req->wValue & 0x00FF; + bool need_zlp = !(length & (usbdc.ctrl_size - 1)); + + switch (type) { + case USB_DT_DEVICE: + if (length > 0x12) { + length = 0x12; + } + usbdc_xfer(ep, usbdc.desces.ls_fs->sod, length, false); + return true; + case USB_DT_CONFIG: + cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index + 1); + if (NULL == cfg_desc) { + return false; + } + total_len = usb_cfg_desc_total_len(cfg_desc); + if (length <= total_len) { + need_zlp = false; + } else { + length = total_len; + } + usbdc_xfer(ep, cfg_desc, length, need_zlp); + return true; + case USB_DT_STRING: + str_desc = usb_find_str_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index); + if (NULL == str_desc) { + return false; + } + total_len = str_desc[0]; + if (length <= total_len) { + need_zlp = false; + } else { + length = total_len; + } + usbdc_xfer(ep, str_desc, length, need_zlp); + return true; + + default: + break; + } + return false; +} + +/** + * \brief Process the GetStatus request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_status_req(const uint8_t ep, const struct usb_req *req) +{ + int32_t st; + (void)ep; + + switch (req->bmRequestType & USB_REQT_RECIP_MASK) { + case USB_REQT_RECIP_DEVICE: + case USB_REQT_RECIP_INTERFACE: + st = 0; + break; + case USB_REQT_RECIP_ENDPOINT: + st = usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_GET); + if (st < 0) { + return false; + } + st = st & 0x1; + break; + default: + return false; + } + memcpy(usbdc.ctrl_buf, &st, 2); + usbdc_xfer(ep, usbdc.ctrl_buf, 2, false); + return true; +} + +/** + * \brief Process the standard Get Interface + * \param[in] req Point to usb request struct. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_interface(struct usb_req *req) +{ + struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; + int32_t rc; + + while (NULL != func) { + if (0 > (rc = func->ctrl(func, USBDF_GET_IFACE, req))) { + func = func->next; + } else { + usbdc.ctrl_buf[0] = (uint8_t)rc; + usbdc_xfer(0, usbdc.ctrl_buf, 1, false); + return true; + } + } + return false; +} + +/** + * \brief Process the standard Get request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_get_req(const uint8_t ep, struct usb_req *req) +{ + switch (req->bRequest) { + case USB_REQ_GET_DESC: + return usbdc_get_desc_req(ep, req); + case USB_REQ_GET_CONFIG: + *(uint8_t *)usbdc.ctrl_buf = usbdc.cfg_value; + usbdc_xfer(ep, usbdc.ctrl_buf, 1, false); + return true; + case USB_REQ_GET_STATUS: + return usbdc_get_status_req(ep, req); + case USB_REQ_GET_INTERFACE: + return usbdc_get_interface(req); + default: + return false; + } +} + +/** + * \brief Process the standard ClearFeature request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_clear_ftr_req(const uint8_t ep, const struct usb_req *req) +{ + (void)ep; + switch (req->bmRequestType & USB_REQT_RECIP_MASK) { + case USB_REQT_RECIP_ENDPOINT: + if (req->wLength != 0) { + return false; + } + usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_CLR); + return true; + default: + return false; + } +} + +/** + * \brief Process the standard SetFeature request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_set_ftr_req(const uint8_t ep, const struct usb_req *req) +{ + (void)ep; + switch (req->bmRequestType & USB_REQT_RECIP_MASK) { + case USB_REQT_RECIP_ENDPOINT: + if (req->wLength != 0) { + return false; + } + usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_SET); + return true; + default: + return false; + } +} + +/** + * \brief Unconfig, close all interfaces + */ +static void usbdc_unconfig(void) +{ + struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; + while (NULL != func) { + func->ctrl(func, USBDF_DISABLE, NULL); + func = func->next; + } +} + +/** + * \brief Apply Set Configuration Value + */ +static void usbdc_set_config(void) +{ + struct usbd_descriptors desc; + struct usbdf_driver * func; + uint8_t * cfg_desc; + uint16_t total_len; + uint8_t last_iface = 0xFF; + + if (usbdc.cfg_value == 0) { + usbdc_unconfig(); + return; + } + + cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, usbdc.cfg_value); + + if (NULL == cfg_desc) { + return; + } + + total_len = usb_cfg_desc_total_len(cfg_desc); + desc.eod = cfg_desc + total_len; + desc.sod = usb_find_desc(cfg_desc, desc.eod, USB_DT_INTERFACE); + + while (NULL != desc.sod) { + /* Apply very first alternate setting (must be 0) of the interface */ + if (last_iface != desc.sod[2] /* bInterfaceNumber */) { + last_iface = desc.sod[2]; + func = (struct usbdf_driver *)usbdc.func_list.head; + while (NULL != func) { + if (func->ctrl(func, USBDF_ENABLE, &desc)) { + func = func->next; + } else { + break; + } + } + } + desc.sod = usb_desc_next(desc.sod); + desc.sod = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); + } +} + +/** + * \brief Apply the USB device address + * \param[in] addr address to be set. + */ +static void usbdc_set_address(uint8_t addr) +{ + usb_d_set_address(addr); +} + +/** + * \brief Process the standard Set Interface + * \param[in] alt_set Alternate Setting. + * \param[in] ifc_id Interface Index. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_set_interface(uint16_t alt_set, uint16_t ifc_id) +{ + struct usbd_descriptors desc; + struct usbdf_driver * func; + uint8_t * ifc; + + desc.sod = usbdc.desces.ls_fs->sod; + desc.eod = usbdc.desces.ls_fs->eod; + if (NULL == (ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE))) { + return false; + } + + while (ifc[2] != ifc_id || ifc[3] != alt_set) { + desc.sod = usb_desc_next(desc.sod); + ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); + if (NULL == ifc) { + return false; + } + } + + desc.sod = ifc; + func = (struct usbdf_driver *)usbdc.func_list.head; + + while (NULL != func) { + if (func->ctrl(func, USBDF_DISABLE, &desc)) { + func = func->next; + } else if (ERR_NONE == func->ctrl(func, USBDF_ENABLE, &desc)) { + usbdc_xfer(0, NULL, 0, 0); + return true; + } else { + return false; + } + } + + return false; +} + +/** + * \brief Process the standard Set request + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_set_req(const uint8_t ep, struct usb_req *req) +{ + switch (req->bRequest) { + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_CONFIG: + if (ERR_NONE == usbdc_xfer(ep, NULL, 0, true)) { + return true; + } else { + return false; + } + case USB_REQ_CLEAR_FTR: + return usbdc_clear_ftr_req(ep, req); + case USB_REQ_SET_FTR: + return usbdc_set_ftr_req(ep, req); + case USB_REQ_SET_INTERFACE: + return usbdc_set_interface(req->wValue, req->wIndex); + default: + return false; + } +} + +/** Invoke all registered SOF callbacks. */ +static void usbdc_sof_notify(void) +{ + struct usbdc_sof_handler *sof = (struct usbdc_sof_handler *)usbdc.handlers.sof_list.head; + + while (sof != NULL) { + if (NULL != sof->cb) { + sof->cb(); + } + sof = sof->next; + } +} + +/** Invoke all registered Change notification callbacks. */ +static void usbdc_change_notify(enum usbdc_change_type change, uint32_t value) +{ + struct usbdc_change_handler *cg = (struct usbdc_change_handler *)usbdc.handlers.change_list.head; + + while (cg != NULL) { + if (NULL != cg->cb) { + cg->cb(change, value); + } + cg = cg->next; + } +} + +/** Invoke all registered request callbacks until request handled. */ +static bool usbdc_request_handler(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) +{ + struct usbdc_req_handler *h = (struct usbdc_req_handler *)usbdc.handlers.req_list.head; + int32_t rc; + + while (h != NULL) { + if (NULL != h->cb) { + rc = h->cb(ep, req, stage); + if (0 == rc) { + return true; + } else if (ERR_NOT_FOUND != rc) { + return false; + } + } + h = h->next; + } + return false; +} + +/** + * \brief Callback invoked on USB device SOF + */ +static void usbd_sof_cb(void) +{ + usbdc_sof_notify(); +} + +/** + * \brief Callback invoked when control request is received + * \param[in] ep Endpoint address. + * \param[in] req Pointer to the request. + * \return Operation status. + * \retval true Request is handled OK. + * \retval false Request not supported. + */ +static bool usbdc_cb_ctl_req(const uint8_t ep, struct usb_req *req) +{ + if (usbdc_request_handler(ep, req, USB_SETUP_STAGE)) { + return true; + } + + // STD request handling + switch (req->bmRequestType & (USB_REQT_TYPE_MASK | USB_REQT_DIR_IN)) { + case USB_REQT_TYPE_STANDARD: + return usbdc_set_req(ep, req); + case (USB_REQT_TYPE_STANDARD | USB_REQT_DIR_IN): + return usbdc_get_req(ep, req); + default: + return false; + } +} + +/** + * \brief When control status stage is end + * \param[in] req Pointer to the request. + */ +static void usbdc_ctrl_status_end(const struct usb_req *req) +{ + switch (req->bRequest) { + case USB_REQ_SET_CONFIG: + usbdc.cfg_value = req->wValue; + usbdc_set_config(); + usbdc.state = req->wValue ? USBD_S_CONFIG : USBD_S_ADDRESS; + usbdc_change_notify(USBDC_C_STATE, usbdc.state); + break; + case USB_REQ_SET_ADDRESS: + usbdc_set_address(req->wValue); + usbdc.state = req->wValue ? USBD_S_ADDRESS : USBD_S_DEFAULT; + usbdc_change_notify(USBDC_C_STATE, usbdc.state); + break; + default: + break; + } +} + +/** + * \brief When control data stage is end + * \param[in] req Pointer to the request. + */ +static bool usbdc_ctrl_data_end(struct usb_req *req) +{ + usbdc_request_handler(0, req, USB_DATA_STAGE); + return false; +} + +/** + * \brief Callback invoked when control data done or status done + * \param[in] ep Endpoint number with direction on bit 8. + * \param[in] code Status code. + * \param[in] req Pointer to the control setup request. + * \return Data has error or not. + * \retval true There is data error, protocol error. + * \retval false There is no data error. + */ +static bool usbdc_cb_ctl_done(const uint8_t ep, const enum usb_xfer_code code, struct usb_req *req) +{ + (void)ep; + + switch (code) { + case USB_XFER_DONE: + usbdc_ctrl_status_end(req); + break; + case USB_XFER_DATA: + return usbdc_ctrl_data_end(req); + default: + break; + } + return false; +} + +/** + * \brief USB Device Core Reset + */ +void usbdc_reset(void) +{ + usbdc_unconfig(); + + usbdc.state = USBD_S_DEFAULT; + usbdc.cfg_value = 0; + + // Setup EP0 + usb_d_ep_deinit(0); + usb_d_ep0_init(usbdc.ctrl_size); + usb_d_ep_register_callback(0, USB_D_EP_CB_SETUP, (FUNC_PTR)usbdc_cb_ctl_req); + usb_d_ep_register_callback(0, USB_D_EP_CB_XFER, (FUNC_PTR)usbdc_cb_ctl_done); + usb_d_ep_enable(0); +} + +/** + * \brief Callback invoked on USB device events + * \param[in] ev Event code. + * \param[in] param Event parameter for event handling. + */ +static void usbd_event_cb(const enum usb_event ev, const uint32_t param) +{ + (void)param; + + switch (ev) { + case USB_EV_VBUS: + usbdc_change_notify(USBDC_C_CONN, param); + break; + + case USB_EV_RESET: + usbdc_reset(); + break; + + default: + break; + } +} + +/** + * \brief Issue USB device transfer + */ +int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp) +{ + struct usb_d_transfer xfer = {(uint8_t *)buf, size, ep, zlp}; + return usb_d_ep_transfer(&xfer); +} + +/** + * \brief Register the handler + */ +void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) +{ + switch (type) { + case USBDC_HDL_SOF: + list_insert_at_end(&usbdc.handlers.sof_list, (void *)h); + break; + case USBDC_HDL_REQ: + list_insert_at_end(&usbdc.handlers.req_list, (void *)h); + break; + case USBDC_HDL_CHANGE: + list_insert_at_end(&usbdc.handlers.change_list, (void *)h); + break; + default: + break; + } +} + +/** + * \brief Unregister the handler + */ +void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) +{ + switch (type) { + case USBDC_HDL_SOF: + list_delete_element(&usbdc.handlers.sof_list, (void *)h); + break; + case USBDC_HDL_REQ: + list_delete_element(&usbdc.handlers.req_list, (void *)h); + break; + case USBDC_HDL_CHANGE: + list_delete_element(&usbdc.handlers.change_list, (void *)h); + break; + default: + break; + } +} + +/** + * \brief Initialize the USB device core driver + */ +int32_t usbdc_init(uint8_t *ctrl_buf) +{ + ASSERT(ctrl_buf); + + int32_t rc; + + rc = usb_d_init(); + if (rc < 0) { + return rc; + } + + memset(&usbdc, 0, sizeof(usbdc)); + usbdc.ctrl_buf = ctrl_buf; + usb_d_register_callback(USB_D_CB_SOF, (FUNC_PTR)usbd_sof_cb); + usb_d_register_callback(USB_D_CB_EVENT, (FUNC_PTR)usbd_event_cb); + + return 0; +} + +/** + * \brief De-initialize the USB device core driver + */ +int32_t usbdc_deinit(void) +{ + usb_d_deinit(); + return 0; +} + +/** + * \brief Register/unregister function support of a USB device function + * + * Must be invoked when USB device is stopped. + */ +void usbdc_register_function(struct usbdf_driver *func) +{ + list_insert_at_end(&usbdc.func_list, func); +} + +/** + * \brief Unregister function support of a USB device function + * + * Must be invoked when USB device is stopped. + */ +void usbdc_unregister_function(struct usbdf_driver *func) +{ + list_delete_element(&usbdc.func_list, func); +} + +/** + * \brief Validate the descriptor + */ +int32_t usbdc_validate_desces(struct usbd_descriptors *desces) +{ + uint8_t *sod, *eod; + if (desces == NULL) { + return ERR_NOT_FOUND; + } + sod = usb_find_desc(desces->sod, desces->eod, USB_DT_DEVICE); + if (sod == NULL) { + return ERR_BAD_DATA; + } + sod = usb_find_desc(desces->sod, desces->eod, USB_DT_CONFIG); + if (sod == NULL) { + return ERR_BAD_DATA; + } + eod = sod + usb_cfg_desc_total_len(sod); + if (eod > desces->eod) { + return ERR_BAD_DATA; + } + return 0; +} + +/** + * \brief Validate the descriptor + */ +int32_t usbdc_check_desces(struct usbdc_descriptors *desces) +{ +#ifdef CONF_USBD_HS_SP + int32_t rc; + if (desces->hs == NULL && desces->ls_fs == NULL) { + return ERR_NOT_FOUND; + } + if (desces->hs) { + rc = usbdc_validate_desces(desces->hs); + if (rc < 0) { + return rc; + } + } +#endif + return usbdc_validate_desces(desces->ls_fs); +} + +/** + * \brief Start the USB device driver with specific descriptors set + */ +int32_t usbdc_start(struct usbd_descriptors *desces) +{ + if (usbdc.state >= USBD_S_POWER) { + return ERR_BUSY; + } + + if (desces) { + usbdc.desces.ls_fs = desces; + } else { + return ERR_BAD_DATA; + } + + usbdc.ctrl_size = desces->sod[7]; + usbdc.state = USBD_S_POWER; + usb_d_enable(); + return ERR_NONE; +} + +/** + * \brief Stop the USB device driver + */ +int32_t usbdc_stop(void) +{ + usb_d_disable(); + usbdc.state = USBD_S_OFF; + return ERR_NONE; +} + +/** + * \brief Attach the USB device to host + */ +void usbdc_attach(void) +{ + usb_d_attach(); +} + +/** + * \brief Detach the USB device from host + */ +void usbdc_detach(void) +{ + usb_d_detach(); +} + +/** + * \brief Send remote wakeup to host + */ +void usbdc_remotewakeup(void) +{ + usb_d_send_remotewakeup(); + usbdc.state = USBD_S_POWER; +} + +/** + * \brief Return USB Device endpoint0 buffer + */ +uint8_t *usbdc_get_ctrl_buffer(void) +{ + return usbdc.ctrl_buf; +} + +/** + * \brief Return current USB state + */ +uint8_t usbdc_get_state(void) +{ + if (usbdc.state & USBD_S_SUSPEND) { + return USBD_S_SUSPEND; + } + return usbdc.state; +} + +/** + * \brief Return version + */ +uint32_t usbdc_get_version(void) +{ + return USBDC_VERSION; +} diff --git a/atmel-samd/asf4/samd51/usb/device/usbdc.h b/atmel-samd/asf4/samd51/usb/device/usbdc.h new file mode 100644 index 0000000000000..515d28f1b903b --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/device/usbdc.h @@ -0,0 +1,246 @@ +/** + * \file + * + * \brief USB Device Stack Core Layer Definition. + * + * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_USBDC_H_ +#define _USB_USBDC_H_ + +#include "usb_includes.h" +#include "usb_protocol.h" +#include "hal_usb_device.h" + +/** USB device states. */ +enum usbd_state { + USBD_S_OFF = 0, + USBD_S_POWER = 1, + USBD_S_DEFAULT = 2, + USBD_S_ADDRESS = 3, + USBD_S_CONFIG = 4, + USBD_S_SUSPEND = 0x10 +}; + +/** USB device core handler type. */ +enum usbdc_handler_type { USBDC_HDL_SOF, USBDC_HDL_REQ, USBDC_HDL_CHANGE }; + +/** USB device core change notification type. */ +enum usbdc_change_type { + /** Change of connection, detected by vbus. */ + USBDC_C_CONN, + /** Change of state, by RESET, SetAddress(), SetConfig(). */ + USBDC_C_STATE, + /** Change of power. */ + USBDC_C_POWER, + /** Change of remote wakeup setting. */ + USBDC_C_REMOTE_WAKEUP +}; + +/** Power change. */ +enum usbdc_power_type { USBDC_ACTIVE, USBDC_SLEEP, USBDC_SUSPEND }; + +/** USB device general function control code. */ +enum usbdf_control { + /** Enable the function. + * int32_t ctrl(usbdf, USBDF_ENABLE, struct usbd_descriptors *desc); + * Parameter holds interface descriptor and + * configuration descriptor end position. + */ + USBDF_ENABLE, + /** Disable the function. + * int32_t ctrl(usbdf, USBDF_DISABLE, struct usbd_descriptors *desc); + * Parameter holds interface descriptor and + * configuration descriptor end position. + * Input NULL to force disable the function anyway. + */ + USBDF_DISABLE, + /** Get interface alternate setting. + * int32_t ctrl(usbdf, USBDF_GET_IFACE, struct usb_req *req); + * Parameter holds interface number who should return + * the alternate setting. + */ + USBDF_GET_IFACE +}; + +/** Describes a list of USB descriptors. */ +struct usbd_descriptors { + /** Pointer to Start of Descriptors. */ + uint8_t *sod; + /** Pointer to End of Descriptors. */ + uint8_t *eod; +}; + +/** Describes the USB device core descriptors. */ +struct usbdc_descriptors { + struct usbd_descriptors *ls_fs; +#ifdef CONF_USBD_HS_SP + struct usbd_descriptors *hs; +#endif +}; + +/** Describes a list of core handler descriptor. */ +struct usbdc_handler { + /** Pointer to next handler. */ + struct usbdc_handler *next; + /** Pointer to handler function. */ + FUNC_PTR func; +}; + +/** Forward declaration for USB device function driver. */ +struct usbdf_driver; + +/** SOF handling function. */ +typedef void (*usbdc_sof_cb_t)(void); + +/** REQ handling function. */ +typedef int32_t (*usbdc_req_cb_t)(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage); + +/** Change notification callback function. */ +typedef void (*usbdc_change_cb_t)(enum usbdc_change_type change, uint32_t value); + +/** Control function for USB device general function driver. */ +typedef int32_t (*usbdf_control_cb_t)(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param); + +/** USB device general function driver descriptor. */ +struct usbdf_driver { + /** Pointer to next function.*/ + struct usbdf_driver *next; + /** Pointer to control function.*/ + usbdf_control_cb_t ctrl; + /** Pointer to function driver specific data. */ + void *func_data; +}; + +/** + * \brief Register the handler + * \param[in] type USB device core handler type. + * \param[in] h Pointer to usb device core handler. + */ +void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); + +/** + * \brief Unregister the handler + * \param[in] type USB device core handler type. + * \param[in] h Pointer to usb device core handler. + */ +void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); + +/** + * \brief Initialize the USB device core driver + * \param[in] ctrl_buf Pointer to a buffer to be used by usb device ctrl endpoint + * Note: the size of ctrl_buf should not be less than the size of EP0 + * \return Operation status. + */ +int32_t usbdc_init(uint8_t *ctrl_buf); + +/** + * \brief Deinitialize the USB device core driver + * \return Operation status. + */ +int32_t usbdc_deinit(void); + +/** + * \brief Register function support of a USB device function + * \param[in] func Pointer to usb device function driver structure + */ +void usbdc_register_function(struct usbdf_driver *func); + +/** + * \brief Unregister function support of a USB device function + * \param[in] func Pointer to usb device function driver structure + */ +void usbdc_unregister_function(struct usbdf_driver *func); + +/** + * \brief Validate the descriptors + * \param[in] desces Pointer to usb device core descriptors + * \return Operation status. + */ +int32_t usbdc_validate_desces(struct usbd_descriptors *desces); + +/** + * \brief Issue USB device data transfer + * \param[in] ep endpointer address. + * \param[in] buf Pointer to data transfer buffer. + * \param[in] size the size of data transfer. + * \param[in] zlp flag to indicate zero length packet. + * \return Operation status. + */ +int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp); + +/** + * \brief Start the USB device driver with specific descriptors set + * \param[in] desces Pointer to usb device core descriptors + * \return Operation status. + */ +int32_t usbdc_start(struct usbd_descriptors *desces); + +/** + * \brief Stop the USB device driver + * \return Operation status. + */ +int32_t usbdc_stop(void); + +/** + * \brief Attach the USB device to host + */ +void usbdc_attach(void); + +/** + * \brief Detach the USB device from host + */ +void usbdc_detach(void); + +/** + * \brief Send remote wakeup to host + */ +void usbdc_remotewakeup(void); + +/** + * \brief Return USB device ctrl end pointer buffer start address + */ +uint8_t *usbdc_get_ctrl_buffer(void); + +/** + * \brief Return current USB state + */ +uint8_t usbdc_get_state(void); + +/** + * \brief Return version + */ +uint32_t usbdc_get_version(void); + +#endif /* USBDC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/usb_atmel.h b/atmel-samd/asf4/samd51/usb/usb_atmel.h new file mode 100644 index 0000000000000..3ca7a2927eb58 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/usb_atmel.h @@ -0,0 +1,189 @@ +/** + * \file + * + * \brief All USB VIDs and PIDs from Atmel USB applications + * + * Copyright (c) 2015 Atmel Corporation. All rights reserved. + * + * \asf_license_start + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel microcontroller product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Atmel Support + */ + +#ifndef _USB_ATMEL_H_ +#define _USB_ATMEL_H_ + +/** + * \defgroup usb_group USB Stack + * + * This stack includes the USB Device Stack, USB Host Stack and common + * definitions. + * @{ + */ + +//! @} + +/** + * \ingroup usb_group + * \defgroup usb_atmel_ids_group Atmel USB Identifiers + * + * This module defines Atmel PID and VIDs constants. + * + * @{ + */ + +//! \name Vendor Identifier assigned by USB org to ATMEL +#define USB_VID_ATMEL 0x03EB + +//! \name Product Identifier assigned by ATMEL to AVR applications +//! @{ + +//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others. +//! @{ +#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013 +#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017 +#define USB_PID_ATMEL_MEGA_CDC 0x2018 +#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019 +#define USB_PID_ATMEL_MEGA_MS 0x201A +#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B +#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C +#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D +#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022 +#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023 +#define USB_PID_ATMEL_MEGA_MS_2 0x2029 +#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A +#define USB_PID_ATMEL_MEGA_MS_3 0x2032 +#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050 +//! @} + +//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools. +//! @{ +#define USB_PID_ATMEL_XPLAINED 0x2122 +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A +#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B +//! @} + +//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=> +//! @{ +#define USB_PID_ATMEL_UC3_ENUM 0x2300 +#define USB_PID_ATMEL_UC3_MS 0x2301 +#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302 +#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303 +#define USB_PID_ATMEL_UC3_HID 0x2304 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305 +#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306 +#define USB_PID_ATMEL_UC3_CDC 0x2307 +#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308 +#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx +#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311 +#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312 +//! @} + +//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications +//! @{ +#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400 +#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401 +#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402 +#define USB_PID_ATMEL_ASF_MSC 0x2403 +#define USB_PID_ATMEL_ASF_CDC 0x2404 +#define USB_PID_ATMEL_ASF_PHDC 0x2405 +#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406 +#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420 +#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421 +#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422 +#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423 +#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424 +#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425 +#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431 +#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432 +#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433 +#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434 +//! @} + +//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders +//! Note, !!!! don't use this range for demos or examples !!!! +//! @{ +#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6 +#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7 +#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8 +#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9 +#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA +#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB +#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC +#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD +#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE + +#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF +#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0 +#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1 +#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2 +#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3 +#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4 +#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5 +#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6 +#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7 +#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8 +#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9 +#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA +#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB +#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC +#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED +#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE +#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF +#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0 +#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1 +#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2 +#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3 +#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4 +#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5 +#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6 +#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7 +#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8 +#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9 +#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA +#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB +// 2FFCh to 2FFFh used by C51 family products +//! @} + +//! @} + +//! @} + +#endif // _USB_ATMEL_H_ diff --git a/atmel-samd/asf4/samd51/usb/usb_debug.h b/atmel-samd/asf4/samd51/usb/usb_debug.h new file mode 100644 index 0000000000000..4d8893208beac --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/usb_debug.h @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief USB Debug Files. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_DEBUG_H_ +#define _USB_DEBUG_H_ + +#define udbg_print(...) + +#endif diff --git a/atmel-samd/asf4/samd51/usb/usb_includes.h b/atmel-samd/asf4/samd51/usb/usb_includes.h new file mode 100644 index 0000000000000..b3874d31e64e3 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/usb_includes.h @@ -0,0 +1,137 @@ +/** + * \file + * + * \brief USB Include Header Files. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_INCLUDES_H_ +#define _USB_INCLUDES_H_ + +#ifdef USB_USER_INCLUDES + +#include "usb_user_includes.h" + +#else +/* Include START headers */ +#include +#include +#include +#include +#include +#include +#include + +typedef uint16_t le16_t; +typedef uint32_t le32_t; +typedef uint16_t be16_t; +typedef uint32_t be32_t; + +#if (defined __GNUC__) || (defined __CC_ARM) +#define is_constant(exp) __builtin_constant_p(exp) +#else +#define is_constant(exp) (0) +#endif + +/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). + * + * \param u16 U16 of which to toggle the endianism. + * + * \return Value resulting from \a u16 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8))) + +/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). + * + * \param u32 U32 of which to toggle the endianism. + * + * \return Value resulting from \a u32 with toggled endianism. + * + * \note More optimized if only used with values known at compile time. + */ +#if (defined __GNUC__) +#define swap_u32(u32) \ + (is_constant(u32) \ + ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) \ + : ((uint32_t)__builtin_bswap32((uint32_t)(u32)))) +#else +#define swap_u32(u32) \ + ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) +#endif + +/** Get a value from/to LE16 data */ +#define LE16(x) (x) +/** Get a value from/to LE32 data */ +#define LE32(x) (x) +/** Get a value from/to BE16 data */ +#define BE16(x) swap_u16(x) +/** Get a value from/to BE32 data */ +#define BE32(x) swap_u32(x) + +/** Get byte 0 for BE 16-bit value */ +#define BE16B0(a) ((uint8_t)((a) >> 8)) +/** Get byte 1 for BE 16-bit value */ +#define BE16B1(a) ((uint8_t)((a) >> 0)) + +/** Get byte 0 for BE 32-bit value */ +#define BE32B0(a) ((uint8_t)((a) >> 24)) +/** Get byte 1 for BE 32-bit value */ +#define BE32B1(a) ((uint8_t)((a) >> 16)) +/** Get byte 2 for BE 32-bit value */ +#define BE32B2(a) ((uint8_t)((a) >> 8)) +/** Get byte 3 for BE 32-bit value */ +#define BE32B3(a) ((uint8_t)((a) >> 0)) + +/** Get byte 0 for LE 16-bit value */ +#define LE16B0(a) ((uint8_t)((a) >> 0)) +/** Get byte 1 for LE 16-bit value */ +#define LE16B1(a) ((uint8_t)((a) >> 8)) + +/** Get byte 0 for LE 32-bit value */ +#define LE32B0(a) ((uint8_t)((a) >> 0)) +/** Get byte 1 for LE 32-bit value */ +#define LE32B1(a) ((uint8_t)((a) >> 8)) +/** Get byte 2 for LE 32-bit value */ +#define LE32B2(a) ((uint8_t)((a) >> 16)) +/** Get byte 3 for LE 32-bit value */ +#define LE32B3(a) ((uint8_t)((a) >> 24)) + +#endif /* USB_USER_INCLUDES */ + +#endif /* _USB_INCLUDES_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/usb_protocol.c b/atmel-samd/asf4/samd51/usb/usb_protocol.c new file mode 100644 index 0000000000000..534e4d1d96d3c --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/usb_protocol.c @@ -0,0 +1,146 @@ +/** + * \file + * + * \brief USB protocol implementation. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#define CONF_NO_ASSERT_CHECK + +#include "usb_protocol.h" + +#ifdef CONF_NO_ASSERT_CHECK +#define _param_error_check(cond) +#define _desc_len_check() \ + if (usb_desc_len(desc) < 2) { \ + /* Encounter an invalid descriptor. */ \ + return NULL; \ + } +#else +#define _param_error_check(cond) ASSERT(cond) +#define _desc_len_check() ASSERT(usb_desc_len(desc) >= 2) +#endif + +uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type) +{ + _param_error_check(desc && eof && (desc < eof)); + + while (desc < eof) { + _desc_len_check(); + if (type == usb_desc_type(desc)) { + return desc; + } + desc = usb_desc_next(desc); + } + return NULL; +} + +uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n) +{ + _param_error_check(desc && eof && (desc < eof)); + + while (desc < eof) { + _desc_len_check(); + if (USB_DT_INTERFACE == usb_desc_type(desc)) { + if (iface_n != desc[2]) { + return desc; + } + } + desc = usb_desc_next(desc); + } + return eof; +} + +uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof) +{ + _param_error_check(desc && eof && (desc < eof)); + + while (desc < eof) { + _desc_len_check(); + if (USB_DT_INTERFACE == usb_desc_type(desc)) { + break; + } + if (USB_DT_ENDPOINT == usb_desc_type(desc)) { + return desc; + } + desc = usb_desc_next(desc); + } + return NULL; +} + +uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value) +{ + _param_error_check(desc && eof && (desc < eof)); + + desc = usb_find_desc(desc, eof, USB_DT_CONFIG); + if (!desc) { + return NULL; + } + while (desc < eof) { + _desc_len_check(); + if (desc[1] != USB_DT_CONFIG) { + break; + } + if (desc[5] == cfg_value) { + return desc; + } + desc = usb_cfg_desc_next(desc); + } + return NULL; +} + +uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index) +{ + uint8_t i; + + _param_error_check(desc && eof && (desc < eof)); + + for (i = 0; desc < eof;) { + desc = usb_find_desc(desc, eof, USB_DT_STRING); + if (desc) { + _desc_len_check(); + if (i == str_index) { + return desc; + } + i++; + desc = usb_desc_next(desc); + } else { + return NULL; + } + } + return NULL; +} diff --git a/atmel-samd/asf4/samd51/usb/usb_protocol.h b/atmel-samd/asf4/samd51/usb/usb_protocol.h new file mode 100644 index 0000000000000..bb8d1ecd59f2e --- /dev/null +++ b/atmel-samd/asf4/samd51/usb/usb_protocol.h @@ -0,0 +1,765 @@ +/** + * \file + * + * \brief USB protocol definitions. + * + * This file contains the USB definitions and data structures provided by the + * USB 2.0 specification. + * + * Copyright (C) 2015 Atmel Corporation. All rights reserved. + * + * \page License + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of Atmel may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * 4. This software may only be redistributed and used in connection with an + * Atmel AVR product. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef _USB_PROTOCOL_H_ +#define _USB_PROTOCOL_H_ + +#include "usb_includes.h" + +/** + * \ingroup usb_group + * \defgroup usb_protocol_group USB Protocol Definitions + * + * This module defines constants and data structures provided by the USB + * 2.0 specification. + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __CC_ARM +#pragma anon_unions +#endif + +/*! Value for field bcdUSB */ +#define USB_V2_0 (0x0200) /*!< USB Specification version 2.00 */ +#define USB_V2_1 (0x0201) /*!< USB Specification version 2.01 (support BOS) */ + +/*! \name Generic definitions (Class, subclass and protocol) + */ +/*! @{ */ +#define USB_CLASS_NO (0x00) +#define USB_SUBCLASS_NO (0x00) +#define USB_PROTOCOL_NO (0x00) +/*! @} */ + +/*! \name IAD (Interface Association Descriptor) constants */ +/*! @{ */ +#define USB_CLASS_IAD (0xEF) +#define USB_SUBCLASS_IAD (0x02) +#define USB_PROTOCOL_IAD (0x01) +/*! @} */ + +/** + * \brief USB request data transfer direction (bmRequestType) + */ +#define USB_REQT_DIR_OUT (0 << 7) /*!< Host to device */ +#define USB_REQT_DIR_H2D (0 << 7) /*!< Host to device */ +#define USB_REQT_DIR_IN (1 << 7) /*!< Device to host */ +#define USB_REQT_DIR_D2H (1 << 7) /*!< Device to host */ +#define USB_REQT_DIR_MASK (1 << 7) /*!< Mask */ + +/** + * \brief USB request types (bmRequestType) + */ +#define USB_REQT_TYPE_STANDARD (0 << 5) /*!< Standard request */ +#define USB_REQT_TYPE_CLASS (1 << 5) /*!< Class-specific request */ +#define USB_REQT_TYPE_VENDOR (2 << 5) /*!< Vendor-specific request */ +#define USB_REQT_TYPE_MASK (3 << 5) /*!< Mask */ + +/** + * \brief USB recipient codes (bmRequestType) + */ +#define USB_REQT_RECIP_DEVICE (0 << 0) /*!< Recipient device */ +#define USB_REQT_RECIP_INTERFACE (1 << 0) /*!< Recipient interface */ +#define USB_REQT_RECIP_ENDPOINT (2 << 0) /*!< Recipient endpoint */ +#define USB_REQT_RECIP_OTHER (3 << 0) /*!< Recipient other */ +#define USB_REQT_RECIP_MASK (0x1F) /*!< Mask */ + +/** + * \brief Standard USB control transfer stages. + */ +enum usb_ctrl_stage { USB_SETUP_STAGE = 0, USB_DATA_STAGE = 1, USB_STATUS_STAGE = 2 }; + +/** + * \brief Standard USB requests (bRequest) + */ +enum usb_req_code { + USB_REQ_GET_STATUS = 0, + USB_REQ_CLEAR_FTR = 1, + USB_REQ_SET_FTR = 3, + USB_REQ_SET_ADDRESS = 5, + USB_REQ_GET_DESC = 6, + USB_REQ_SET_DESC = 7, + USB_REQ_GET_CONFIG = 8, + USB_REQ_SET_CONFIG = 9, + USB_REQ_GET_INTERFACE = 10, + USB_REQ_SET_INTERFACE = 11, + USB_REQ_SYNCH_FRAME = 12, + USB_REQ_SET_SEL = 48, + USB_REQ_ISOCH_DELAY = 49 +}; + +/** + * \brief Standard USB device status flags + * + */ +enum usb_dev_status { + USB_DEV_STAT_BUS_POWERED = 0, + USB_DEV_STAT_SELF_POWERED = 1, + USB_DEV_STAT_REMOTEWAKEUP = 2, + USB_DEV_STAT_U1_ENABLE = 4, + USB_DEV_STAT_U2_ENABLE = 8, + USB_DEV_STAT_LTM_ENABLE = 16 +}; + +/** + * \brief Standard USB Interface status flags + * + */ +enum usb_interface_status { + USB_IFACE_STAT_RESERVED = 0, + USB_IFACE_STAT_REMOTEWAKE_CAP = 1, + USB_IFACE_STAT_REMOTEWAKE = 2 +}; + +/** + * \brief Standard USB endpoint status flags + * + */ +enum usb_endpoint_status { USB_EP_STAT_HALT = 1 }; + +/** + * \brief Standard USB device feature flags + * + * \note valid for SetFeature request. + */ +enum usb_device_feature { + USB_DEV_FTR_REMOTE_WAKEUP = 1, /*!< Remote wakeup enabled */ + USB_DEV_FTR_TEST_MODE = 2, /*!< USB test mode */ + USB_DEV_FTR_OTG_B_HNP_ENABLE = 3, + USB_DEV_FTR_OTG_A_HNP_SP = 4, + USB_DEV_FTR_OTG_A_ALT_HNP_SP = 5, + USB_DEV_FTR_U1_ENABLE = 48, + USB_DEV_FTR_U2_ENABLE = 49, + USB_DEV_FTR_LTM_ENABLE = 50 +}; + +/** + * \brief Test Mode possible on HS USB device + * + * \note valid for USB_DEV_FTR_TEST_MODE request. + */ +enum usb_device_hs_test_mode { + USB_DEV_TEST_MODE_J = 1, + USB_DEV_TEST_MODE_K = 2, + USB_DEV_TEST_MODE_SE0_NAK = 3, + USB_DEV_TEST_MODE_PACKET = 4, + USB_DEV_TEST_MODE_FORCE_ENABLE = 5 +}; + +/** + * \brief Standard Feature Selectors for Interface + */ +enum usb_iface_feature { USB_IFACE_FTR_FUNC_SUSP = 0 }; + +/** + * \brief Standard USB endpoint feature/status flags + */ +enum usb_endpoint_feature { USB_EP_FTR_HALT = 0 }; + +/** + * \brief Standard USB Test Mode Selectors + */ +enum usb_test_mode_selector { + USB_TEST_J = 0x01, + USB_TEST_K = 0x02, + USB_TEST_SE0_NAK = 0x03, + USB_TEST_PACKET = 0x04, + USB_TEST_FORCE_ENABLE = 0x05 +}; + +/** + * \brief Standard USB descriptor types + */ +enum usb_descriptor_type { + USB_DT_DEVICE = 1, + USB_DT_CONFIG = 2, + USB_DT_STRING = 3, + USB_DT_INTERFACE = 4, + USB_DT_ENDPOINT = 5, + USB_DT_DEVICE_QUALIFIER = 6, + USB_DT_OTHER_SPEED_CONFIG = 7, + USB_DT_INTERFACE_POWER = 8, + USB_DT_OTG = 9, + USB_DT_DEBUG = 10, + USB_DT_IAD = 11, + USB_DT_BOS = 15, + USB_DT_DEV_CAP = 16, + USB_DT_SS_EP_COMPANION = 48 +}; + +/** + * \brief Capability types + */ +enum usb_capability_type { + USB_CAPT_WIRELESS = 1, + USB_CAPT_2_0_EXT = 2, + USB_CAPT_SUPER_SPEED = 3, + USB_CAPT_CONTAINER_ID = 4 +}; + +/** + * \brief USB 2.0 Extension attributes + */ +enum usb_2_0_ext_attr { USB_2_0_EXT_LPM_SP = 1 }; + +/** + * \brief USB SuperSpeed Capability attributes + */ +enum usb_ss_cap_attr { USB_SS_LTM_SP }; + +/** + * \brief USB Speed Supports + */ +enum usb_speed_sp { + USB_SPEED_LOW_SP = 1, + USB_SPEED_LS_SP = 1, + USB_SPEED_FULL_SP = 2, + USB_SPEED_FS_SP = 2, + USB_SPEED_HIGH_SP = 4, + USB_SPEED_HS_SP = 4, + USB_SPEED_SUPER_SP = 8, + USB_SPEED_SS_SP = 8 +}; + +/** + * \brief Standard USB endpoint transfer types + */ +enum usb_ep_type { + USB_EP_TYPE_CONTROL = 0x00, + USB_EP_TYPE_ISOCHRONOUS = 0x01, + USB_EP_TYPE_BULK = 0x02, + USB_EP_TYPE_INTERRUPT = 0x03, + USB_EP_TYPE_MASK = 0x03u +}; + +/** + * \brief USB endpoint interrupt types + */ +enum usb_ep_int_type { USB_EP_INT_T_PERIODIC = 0x00u, USB_EP_INT_T_NOTIFICATION = 0x01u, USB_EP_INT_T_MASK = 0x03u }; + +/** + * \brief Standard USB endpoint synchronization types + */ +enum usb_ep_sync_type { + USB_EP_SYNC_T_NO = 0x00u, + USB_EP_SYNC_T_ASYNC = 0x02u, + USB_EP_SYNC_T_ADAPTIVE = 0x02u, + USB_EP_SYNC_T_SYNC = 0x03u, + USB_EP_SYNC_T_MASK = 0x03u +}; + +/** + * \brief Standard USB endpoint usage types + */ +enum usb_ep_usage_type { + USB_EP_USAGE_T_DATA = 0x00u, + USB_EP_USAGE_T_FEEDBACK = 0x01u, + USB_EP_USAGE_T_FEEDBACK_DATA = 0x02u, + USB_EP_USAGE_T_MASK = 0x03u +}; + +/** + * \brief Standard USB language IDs for string descriptors + */ +enum usb_langid { + USB_LANGID_EN_US = 0x0409 /*!< English (United States) */ +}; + +/** + * \brief Mask selecting the index part of an endpoint address + */ +#define USB_EP_ADDR_MASK 0x0f +/** + * \brief Endpoint transfer direction is IN + */ +#define USB_EP_DIR_IN 0x80 +/** + * \brief Endpoint transfer direction is OUT + */ +#define USB_EP_DIR_OUT 0x00 + +/** + * \brief Maximum length in bytes of a USB descriptor + * + * The maximum length of a USB descriptor is limited by the 8-bit + * bLength field. + */ +#define USB_DESC_LEN_MAX 255 + +/* + * 2-byte alignment requested for all USB structures. + */ +COMPILER_PACK_SET(1) + +/** + * \brief A USB Device SETUP request + * + * The data payload of SETUP packets always follows this structure. + */ +typedef struct usb_req { + uint8_t bmRequestType; + uint8_t bRequest; + union { + le16_t wValue; + struct { + uint8_t l; + uint8_t h; + } wValueBytes; + }; + union { + le16_t wIndex; + struct { + uint8_t l; + uint8_t h; + } wIndexBytes; + }; + union { + le16_t wLength; + struct { + uint8_t l; + uint8_t h; + } wLengthBytes; + }; +} usb_req_t; + +/** + * \brief Standard USB device descriptor structure + */ +typedef struct usb_dev_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + le16_t idVendor; + le16_t idProduct; + le16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} usb_dev_desc_t; + +/** + * \brief Binary device Object Store (BOS) descriptor structure + */ +typedef struct usb_bos_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumDeviceCaps; +} usb_bos_desc_t; + +/** + * \brief Device Capability Descriptor structure + */ +typedef struct usb_cap_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t Vars[1]; +} usb_cap_desc_t; + +/** + * \brief USB 2.0 Extension Descriptor structure + */ +typedef struct usb_2_0_ext { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint32_t bmAttributes; +} usb_2_0_ext_t; + +/** + * \brief LPM Device Capabilities descriptor structure + */ +typedef struct usb_2_0_ext usb_lpm_cap_desc_t; + +/** + * \brief SuperSpeed USB Device Capability structure + */ +typedef struct usb_ss_cap_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bmAttributes; + le16_t wSpeedsSupported; + uint8_t bFunctionalitySupport; + uint8_t bU1DevExitLat; + uint8_t bU2DevExitLat; +} usb_ss_cap_desc_t; + +/** + * \brief USB Container ID Descriptor structure + */ +typedef struct usb_container_id_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t ContainerID[16]; +} usb_container_id_desc_t; + +/** + * \brief Standard USB device qualifier descriptor structure + * + * This descriptor contains information about the device when running at + * the "other" speed (i.e. if the device is currently operating at high + * speed, this descriptor can be used to determine what would change if + * the device was operating at full speed.) + */ +typedef struct usb_dev_qual_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} usb_dev_qual_desc_t; + +/** + * \brief Standard USB configuration descriptor structure + */ +typedef struct usb_config_desc { + uint8_t bLength; + uint8_t bDescriptorType; + le16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} usb_config_desc_t; + +#define USB_CONFIG_ATTR_MUST_SET (1 << 7) /*!< Must always be set */ +#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) /*!< Bus-powered */ +#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) /*!< Self-powered */ +#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) /*!< remote wakeup supported */ + +#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) /*!< Max power in mA */ + +/** + * \brief Standard USB association descriptor structure + */ +typedef struct usb_iad_desc { + uint8_t bLength; /*!< Size of this descriptor in bytes */ + uint8_t bDescriptorType; /*!< Interface descriptor type */ + uint8_t bFirstInterface; /*!< Number of interface */ + uint8_t bInterfaceCount; /*!< value to select alternate setting */ + uint8_t bFunctionClass; /*!< Class code assigned by the USB */ + uint8_t bFunctionSubClass; /*!< Sub-class code assigned by the USB */ + uint8_t bFunctionProtocol; /*!< Protocol code assigned by the USB */ + uint8_t iFunction; /*!< Index of string descriptor */ +} usb_iad_desc_t; + +/** + * \brief Standard USB interface descriptor structure + */ +typedef struct usb_iface_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_iface_desc_t; + +/** + * \brief Standard USB endpoint descriptor structure + */ +typedef struct usb_ep_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + le16_t wMaxPacketSize; + uint8_t bInterval; +} usb_ep_desc_t; + +/** + * \brief SuperSpeed Endpoint Companion descriptor structure + */ +typedef struct usb_ss_ep_comp_desc { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bMaxBurst; + uint8_t bmAttributes; + le16_t wBytesPerInterval; +} usb_ss_ep_comp_desc_t; + +/** + * \brief LPM Token bmAttributes structure + */ +typedef struct usb_lpm_attributes { + uint8_t bLinkState : 4; + uint8_t HIRD : 4; + uint8_t bRemoteWake : 1; + uint8_t Reserved : 2; +} usb_lpm_attributes_t; + +/** + * \brief A standard USB string descriptor structure + */ +typedef struct usb_str_desc { + uint8_t bLength; + uint8_t bDescriptorType; +} usb_str_desc_t; + +typedef struct usb_str_langid_desc { + usb_str_desc_t desc; + le16_t string[1]; +} usb_str_langid_desc_t; + +COMPILER_PACK_RESET() + +/** \name Macros to build USB standard descriptors */ +/*@{*/ + +/** Build bytes for USB device descriptor. */ +#define USB_DEV_DESC_BYTES(bcdUSB, \ + bDeviceClass, \ + bDeviceSubClass, \ + bDeviceProtocol, \ + bMaxPacketSize0, \ + idVendor, \ + idProduct, \ + bcdDevice, \ + iManufacturer, \ + iProduct, \ + iSerialNumber, \ + bNumConfigurations) \ + 18, /* bLength */ \ + 0x01, /* bDescriptorType: DEVICE */ \ + LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0, \ + LE_BYTE0(idVendor), LE_BYTE1(idVendor), LE_BYTE0(idProduct), LE_BYTE1(idProduct), LE_BYTE0(bcdDevice), \ + LE_BYTE1(bcdDevice), iManufacturer, iProduct, iSerialNumber, bNumConfigurations + +#define USB_DEV_DESC_LEN 18 + +/** Build bytes for USB configuration descriptor. */ +#define USB_CONFIG_DESC_BYTES( \ + wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower) \ + 9, /* bLength */ \ + 0x02, /* bDescriptorType: CONFIGURATION */ \ + LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration, \ + bmAttributes, bMaxPower + +#define USB_CONFIG_DESC_LEN 9 + +/** Build bytes for USB IAD descriptor. */ +#define USB_IAD_DESC_BYTES( \ + bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction) \ + 8, /* bLength */ \ + USB_DT_IAD, /* bDescriptorType */ \ + bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction + +#define USB_IAD_DESC_LEN 8 + +/** Build bytes for USB interface descriptor. */ +#define USB_IFACE_DESC_BYTES(bInterfaceNumber, \ + bAlternateSetting, \ + bNumEndpoints, \ + bInterfaceClass, \ + bInterfaceSubClass, \ + bInterfaceProtocol, \ + iInterface) \ + 9, /* bLength */ \ + 0x04, /* bDescriptorType: INTERFACE */ \ + bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, \ + iInterface + +#define USB_IFACE_DESC_LEN 9 + +/** Build bytes for USB endpoint descriptor. */ +#define USB_ENDP_DESC_BYTES(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 7, /* bLength */ \ + 0x05, /* bDescriptorType: ENDPOINT */ \ + bEndpointAddress, bmAttributes, LE_BYTE0(wMaxPacketSize), LE_BYTE1(wMaxPacketSize), bInterval + +#define USB_ENDP_DESC_LEN 7 + +/*@}*/ + +/** \brief Get a word (calculate by little endian 16-bit data) + * \param[in] ptr Byte pointer to the address to get data + * \return a 16-bit word + */ +static inline uint16_t usb_get_u16(const uint8_t *ptr) +{ + return (ptr[0] + (ptr[1] << 8)); +} + +/** \brief Get a double word (calculate by little endian 32-bit data) + * \param[in] ptr Byte pointer to the address to get data + * \return a 32-bit word + */ +static inline uint32_t usb_get_u32(const uint8_t *ptr) +{ + return (ptr[0] + (ptr[1] << 8) + (ptr[2] << 16) + (ptr[3] << 24)); +} + +/** \brief Get descriptor length + * \param[in] desc Byte pointer to the descriptor start address + * \return descriptor length + */ +static inline uint8_t usb_desc_len(const uint8_t *desc) +{ + return desc[0]; +} + +/** \brief Get descriptor type + * \param[in] desc Byte pointer to the descriptor start address + * \return descriptor type + */ +static inline uint8_t usb_desc_type(const uint8_t *desc) +{ + return desc[1]; +} + +/** \brief Get next USB descriptor + * \param[in] desc Byte pointer to the descriptor start address + * \return Byte pointer to the next descriptor + */ +static inline uint8_t *usb_desc_next(uint8_t *desc) +{ + return (desc + usb_desc_len(desc)); +} + +/** \brief Get idVendor of USB Device Descriptor + * \param[in] dev_desc Byte pointer to the descriptor start address + * \return 16-bit idVendor value + */ +static inline uint16_t usb_dev_desc_vid(const uint8_t *dev_desc) +{ + return usb_get_u16(dev_desc + 8); +} + +/** \brief Get idProduct of USB Device Descriptor + * \param[in] dev_desc Byte pointer to the descriptor start address + * \return 16-bit idProduct value + */ +static inline uint16_t usb_dev_desc_pid(const uint8_t *dev_desc) +{ + return usb_get_u16(dev_desc + 10); +} + +/** \brief Get wTotalLength of USB Configuration Descriptor + * \param[in] cfg_desc Byte pointer to the descriptor start address + * \return 16-bit total length of configuration list + */ +static inline uint16_t usb_cfg_desc_total_len(const uint8_t *cfg_desc) +{ + return usb_get_u16(cfg_desc + 2); +} + +/** \brief Get Next USB Descriptor After the Configuration Descriptors list + * \param[in] cfg_desc Byte pointer to the descriptor start address + * \return Byte pointer to descriptor after configuration end + */ +static inline uint8_t *usb_cfg_desc_next(uint8_t *cfg_desc) +{ + return (cfg_desc + usb_cfg_desc_total_len(cfg_desc)); +} + +/** \brief Find specific USB Descriptor by its type + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] type The descriptor type expected + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type); + +/** Get interface descriptor next to the specified one (by interface number) + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] iface_n The interface number to check + * \return Pointer to the descriptor + * \retval >= eof if not found + */ +uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n); + +/** Find endpoint descriptor, breaks if interface descriptor detected + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof); + +/** Find configuration descriptor by its configuration number + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] cfg_value The configure value expected + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value); + +/** Find string descriptor by its index + * \param[in] desc Byte pointer to the descriptor start address + * \param[in] eof Byte pointer to the descriptor end address + * \param[in] str_index The string index expected + * \return Pointer to the descriptor + * \retval NULL if not found + */ +uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index); + +#ifdef __cplusplus +} +#endif + +/*! @} */ + +#endif /* _USB_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd51/usb_start.c b/atmel-samd/asf4/samd51/usb_start.c new file mode 100644 index 0000000000000..1ccfaafb6be45 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb_start.c @@ -0,0 +1,50 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#include "atmel_start.h" +#include "usb_start.h" + +static uint8_t multi_desc_bytes[] = { + /* Device descriptors and Configuration descriptors list. */ + COMPOSITE_DESCES_LS_FS, +}; + +static struct usbd_descriptors multi_desc = {multi_desc_bytes, multi_desc_bytes + sizeof(multi_desc_bytes)}; + +/** Ctrl endpoint buffer */ +static uint8_t ctrl_buffer[64]; + +/** + * \brief Composite Init + */ +void composite_device_init(void) +{ + /* usb stack init */ + usbdc_init(ctrl_buffer); + + /* usbdc_register_funcion inside */ + + usbdc_start(&multi_desc); + usbdc_attach(); +} + +/** + * Example of using Composite Function. + * \note + * In this example, we will use a PC as a USB host: + * - Connect the DEBUG USB on XPLAINED board to PC for program download. + * - Connect the TARGET USB on XPLAINED board to PC for running program. + */ +void composite_device_example(void) +{ +} + +void usb_init(void) +{ + + composite_device_init(); +} diff --git a/atmel-samd/asf4/samd51/usb_start.h b/atmel-samd/asf4/samd51/usb_start.h new file mode 100644 index 0000000000000..9695f7ed78d69 --- /dev/null +++ b/atmel-samd/asf4/samd51/usb_start.h @@ -0,0 +1,33 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file or main.c + * to avoid loosing it when reconfiguring. + */ +#ifndef USB_DEVICE_MAIN_H +#define USB_DEVICE_MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +#include "cdcdf_acm.h" +#include "hiddf_mouse.h" +#include "hiddf_keyboard.h" +#include "hiddf_generic.h" +#include "composite_desc.h" + +void composite_device_init(void); +void composite_device_example(void); + +/** + * \berif Initialize USB + */ +void usb_init(void); + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif // USB_DEVICE_MAIN_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_dmac_config.h b/atmel-samd/asf4_conf/samd21/hpl_dmac_config.h new file mode 100644 index 0000000000000..3667e873ba303 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_dmac_config.h @@ -0,0 +1,3057 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 0 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif + +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 0 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif + +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 0 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif + +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 0 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif + +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 0 is enabled or not +// dmac_enable_0 +#ifndef CONF_DMAC_ENABLE_0 +#define CONF_DMAC_ENABLE_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 1 is enabled or not +// dmac_enable_1 +#ifndef CONF_DMAC_ENABLE_1 +#define CONF_DMAC_ENABLE_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 2 is enabled or not +// dmac_enable_2 +#ifndef CONF_DMAC_ENABLE_2 +#define CONF_DMAC_ENABLE_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 3 is enabled or not +// dmac_enable_3 +#ifndef CONF_DMAC_ENABLE_3 +#define CONF_DMAC_ENABLE_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 4 is enabled or not +// dmac_enable_4 +#ifndef CONF_DMAC_ENABLE_4 +#define CONF_DMAC_ENABLE_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 5 is enabled or not +// dmac_enable_5 +#ifndef CONF_DMAC_ENABLE_5 +#define CONF_DMAC_ENABLE_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 6 is enabled or not +// dmac_enable_6 +#ifndef CONF_DMAC_ENABLE_6 +#define CONF_DMAC_ENABLE_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 7 is enabled or not +// dmac_enable_7 +#ifndef CONF_DMAC_ENABLE_7 +#define CONF_DMAC_ENABLE_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 8 is enabled or not +// dmac_enable_8 +#ifndef CONF_DMAC_ENABLE_8 +#define CONF_DMAC_ENABLE_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 9 is enabled or not +// dmac_enable_9 +#ifndef CONF_DMAC_ENABLE_9 +#define CONF_DMAC_ENABLE_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 10 is enabled or not +// dmac_enable_10 +#ifndef CONF_DMAC_ENABLE_10 +#define CONF_DMAC_ENABLE_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 11 is enabled or not +// dmac_enable_11 +#ifndef CONF_DMAC_ENABLE_11 +#define CONF_DMAC_ENABLE_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 12 is enabled or not +// dmac_enable_12 +#ifndef CONF_DMAC_ENABLE_12 +#define CONF_DMAC_ENABLE_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 13 is enabled or not +// dmac_enable_13 +#ifndef CONF_DMAC_ENABLE_13 +#define CONF_DMAC_ENABLE_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 14 is enabled or not +// dmac_enable_14 +#ifndef CONF_DMAC_ENABLE_14 +#define CONF_DMAC_ENABLE_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Enable +// Indicates whether channel 15 is enabled or not +// dmac_enable_15 +#ifndef CONF_DMAC_ENABLE_15 +#define CONF_DMAC_ENABLE_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> SERCOM0 RX Trigger +// <0x02=> SERCOM0 TX Trigger +// <0x03=> SERCOM1 RX Trigger +// <0x04=> SERCOM1 TX Trigger +// <0x05=> SERCOM2 RX Trigger +// <0x06=> SERCOM2 TX Trigger +// <0x07=> SERCOM3 RX Trigger +// <0x08=> SERCOM3 TX Trigger +// <0x09=> SERCOM4 RX Trigger +// <0x0A=> SERCOM4 TX Trigger +// <0x0B=> SERCOM5 RX Trigger +// <0x0C=> SERCOM5 TX Trigger +// <0x0D=> TCC0 Overflow Trigger +// <0x0E=> TCC0 Match/Compare 0 Trigger +// <0x0F=> TCC0 Match/Compare 1 Trigger +// <0x10=> TCC0 Match/Compare 2 Trigger +// <0x11=> TCC0 Match/Compare 3 Trigger +// <0x12=> TCC1 Overflow Trigger +// <0x13=> TCC1 Match/Compare 0 Trigger +// <0x14=> TCC1 Match/Compare 1 Trigger +// <0x15=> TCC2 Overflow Trigger +// <0x16=> TCC2 Match/Compare 0 Trigger +// <0x17=> TCC2 Match/Compare 1 Trigger +// <0x18=> TC3 Overflow Trigger +// <0x19=> TC3 Match/Compare 0 Trigger +// <0x1A=> TC3 Match/Compare 1 Trigger +// <0x1B=> TC4 Overflow Trigger +// <0x1C=> TC4 Match/Compare 0 Trigger +// <0x1D=> TC4 Match/Compare 1 Trigger +// <0x1E=> TC5 Overflow Trigger +// <0x1F=> TC5 Match/Compare 0 Trigger +// <0x20=> TC5 Match/Compare 1 Trigger +// <0x21=> TC6 Overflow Trigger +// <0x22=> TC6 Match/Compare 0 Trigger +// <0x23=> TC6 Match/Compare 1 Trigger +// <0x24=> TC7 Overflow Trigger +// <0x25=> TC7 Match/Compare 0 Trigger +// <0x26=> TC7 Match/Compare 1 Trigger +// <0x27=> ADC Result Ready Trigger +// <0x28=> DAC Empty Trigger +// <0x29=> I2S Rx 0 Trigger +// <0x2A=> I2S Rx 1 Trigger +// <0x2B=> I2S Tx 0 Trigger +// <0x2C=> I2S Tx 1 Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h b/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h new file mode 100644 index 0000000000000..fa9bb661ccaa5 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_gclk_config.h @@ -0,0 +1,697 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_RUNSTDBY +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif + +// Generic clock generator 0 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// Generic clock generator 1 + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SRC +#define CONF_GCLK_GEN_0_SRC GCLK_GENCTRL_SRC_DFLL48M +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif + +// +// // Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_RUNSTDBY +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 1 +#endif + +// Generic clock generator 1 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SRC +#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC32K +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif + +// +// // Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_RUNSTDBY +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif + +// Generic clock generator 2 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// Generic clock generator 1 + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SRC +#define CONF_GCLK_GEN_2_SRC GCLK_GENCTRL_SRC_OSC32K +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif + +// +// // Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_RUNSTDBY +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif + +// Generic clock generator 3 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// Generic clock generator 1 + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SRC +#define CONF_GCLK_GEN_3_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif + +// +// // Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_RUNSTDBY +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif + +// Generic clock generator 4 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// Generic clock generator 1 + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SRC +#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif + +// +// // Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_RUNSTDBY +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif + +// Generic clock generator 5 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// Generic clock generator 1 + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SRC +#define CONF_GCLK_GEN_5_SRC GCLK_GENCTRL_SRC_OSC32K +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif + +// +// // Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_RUNSTDBY +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif + +// Generic clock generator 6 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// Generic clock generator 1 + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SRC +#define CONF_GCLK_GEN_6_SRC GCLK_GENCTRL_SRC_OSC32K +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif + +// +// // Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_RUNSTDBY +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif + +// Generic clock generator 7 source + +// External Crystal Oscillator 0.4-32MHz (XOSC) + +// Generic clock generator input pad + +// Generic clock generator 1 + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + +// 32kHz High Accuracy Internal Oscillator (OSC32K) + +// 32kHz External Crystal Oscillator (XOSC32K) + +// 8MHz Internal Oscillator (OSC8M) + +// Digital Frequency Locked Loop (DFLL48M) + +// Fractional Digital Phase Locked Loop (FDPLL96M) + +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SRC +#define CONF_GCLK_GEN_7_SRC GCLK_GENCTRL_SRC_OSC32K +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_pm_config.h b/atmel-samd/asf4_conf/samd21/hpl_pm_config.h new file mode 100644 index 0000000000000..1d24dffaa2b27 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_pm_config.h @@ -0,0 +1,134 @@ +/* Auto-generated config file hpl_pm_config.h */ +#ifndef HPL_PM_CONFIG_H +#define HPL_PM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// CPU Clock Settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// CPU clock Prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for Main CPU clock +// cpu_div +#ifndef CONF_CPU_DIV +#define CONF_CPU_DIV PM_CPUSEL_CPUDIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 2 +#endif + +// + +// APBA Clock Select +// APBA clock prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// APBA clock prescalar +// apba_div +#ifndef CONF_APBA_DIV +#define CONF_APBA_DIV PM_APBASEL_APBADIV_DIV1 +#endif +// + +#if CONF_APBA_DIV < CONF_CPU_DIV +#warning APBA DIV cannot less than CPU DIV +#endif + +// APBB Clock Select +// APBB clock prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// APBB clock prescalar +// apbb_div +#ifndef CONF_APBB_DIV +#define CONF_APBB_DIV PM_APBBSEL_APBBDIV_DIV1 +#endif +// + +#if CONF_APBB_DIV < CONF_CPU_DIV +#warning APBB DIV cannot less than CPU DIV +#endif + +// APBC Clock Select +// APBC clock prescalar +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// APBC clock prescalar +// apbc_div +#ifndef CONF_APBC_DIV +#define CONF_APBC_DIV PM_APBCSEL_APBCDIV_DIV1 +#endif +// + +#if CONF_APBC_DIV < CONF_CPU_DIV +#warning APBC DIV cannot less than CPU DIV +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_PM_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_rtc_config.h b/atmel-samd/asf4_conf/samd21/hpl_rtc_config.h new file mode 100644 index 0000000000000..929c70c8c67ea --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_rtc_config.h @@ -0,0 +1,117 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// Prescaler configuration +// <0x0=>Peripheral clock divided by 1 +// <0x1=>Peripheral clock divided by 2 +// <0x2=>Peripheral clock divided by 4 +// <0x3=>Peripheral clock divided by 8 +// <0x4=>Peripheral clock divided by 16 +// <0x5=>Peripheral clock divided by 32 +// <0x6=>Peripheral clock divided by 64 +// <0x7=>Peripheral clock divided by 128 +// <0x8=>Peripheral clock divided by 256 +// <0x9=>Peripheral clock divided by 512 +// <0xA=>Peripheral clock divided by 1024 +// These bits define the RTC clock relative to the peripheral clock +// rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0x0 + +#endif + +// Compare Value <1-4294967295> +// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// by default 1M clock input, 1 prescaler, 1024 compare value, the ticks period equals to 1ms. +// rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL +#define CONF_RTC_COMP_VAL 1024 + +#endif + +// Event control +// rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// Periodic Interval 0 Event Output +// This bit indicates whether Periodic interval 0 event is enabled and will be generated +// rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// Periodic Interval 1 Event Output +// This bit indicates whether Periodic interval 1 event is enabled and will be generated +// rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// Periodic Interval 2 Event Output +// This bit indicates whether Periodic interval 2 event is enabled and will be generated +// rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// Periodic Interval 3 Event Output +// This bit indicates whether Periodic interval 3 event is enabled and will be generated +// rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// Periodic Interval 4 Event Output +// This bit indicates whether Periodic interval 4 event is enabled and will be generated +// rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// Periodic Interval 5 Event Output +// This bit indicates whether Periodic interval 5 event is enabled and will be generated +// rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// Periodic Interval 6 Event Output +// This bit indicates whether Periodic interval 6 event is enabled and will be generated +// rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// Periodic Interval 7 Event Output +// This bit indicates whether Periodic interval 7 event is enabled and will be generated +// rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// Compare 0 Event Output +// This bit indicates whether Compare O event is enabled and will be generated +// rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// Overflow Event Output +// This bit indicates whether Overflow event is enabled and will be generated +// rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h b/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h new file mode 100644 index 0000000000000..389aefff3c8b3 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_sysctrl_config.h @@ -0,0 +1,678 @@ +/* Auto-generated config file hpl_sysctrl_config.h */ +#ifndef HPL_SYSCTRL_CONFIG_H +#define HPL_SYSCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_DFLL_OPEN_LOOP_MODE 0 +#define CONF_DFLL_CLOSED_LOOP_MODE 1 + +#define CONF_XOSC_STARTUP_TIME_31MCS 0 +#define CONF_XOSC_STARTUP_TIME_61MCS 1 +#define CONF_XOSC_STARTUP_TIME_122MCS 2 +#define CONF_XOSC_STARTUP_TIME_244MCS 3 +#define CONF_XOSC_STARTUP_TIME_488MCS 4 +#define CONF_XOSC_STARTUP_TIME_977MCS 5 +#define CONF_XOSC_STARTUP_TIME_1953MCS 6 +#define CONF_XOSC_STARTUP_TIME_3906MCS 7 +#define CONF_XOSC_STARTUP_TIME_7813MCS 8 +#define CONF_XOSC_STARTUP_TIME_15625MCS 9 +#define CONF_XOSC_STARTUP_TIME_31250MCS 10 +#define CONF_XOSC_STARTUP_TIME_62500MCS 11 +#define CONF_XOSC_STARTUP_TIME_125000MCS 12 +#define CONF_XOSC_STARTUP_TIME_250000MCS 13 +#define CONF_XOSC_STARTUP_TIME_500000MCS 14 +#define CONF_XOSC_STARTUP_TIME_1000000MCS 15 + +#define CONF_OSC_STARTUP_TIME_92MCS 0 +#define CONF_OSC_STARTUP_TIME_122MCS 1 +#define CONF_OSC_STARTUP_TIME_183MCS 2 +#define CONF_OSC_STARTUP_TIME_305MCS 3 +#define CONF_OSC_STARTUP_TIME_549MCS 4 +#define CONF_OSC_STARTUP_TIME_1038MCS 5 +#define CONF_OSC_STARTUP_TIME_2014MCS 6 +#define CONF_OSC_STARTUP_TIME_3967MCS 7 + +#define CONF_XOSC32K_STARTUP_TIME_122MCS 0 +#define CONF_XOSC32K_STARTUP_TIME_1068MCS 1 +#define CONF_XOSC32K_STARTUP_TIME_65592MCS 2 +#define CONF_XOSC32K_STARTUP_TIME_125092MCS 3 +#define CONF_XOSC32K_STARTUP_TIME_500092MCS 4 +#define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5 +#define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6 +#define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7 + +// 8MHz Internal Oscillator Configuration +// Indicates whether configuration for OSC8M is enabled or not +// enable_osc8m +#ifndef CONF_OSC8M_CONFIG +#define CONF_OSC8M_CONFIG 1 +#endif + +// 8MHz Internal Oscillator (OSC8M) Control +// Internal 8M Oscillator Enable +// Indicates whether Internal 8 Mhz Oscillator is enabled or not +// osc8m_arch_enable +#ifndef CONF_OSC8M_ENABLE +#define CONF_OSC8M_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not. +// If enabled, the oscillator will only be running when requested by a peripheral. +// If disabled, the oscillator will always be running when enabled. +// osc8m_arch_ondemand +#ifndef CONF_OSC8M_ONDEMAND +#define CONF_OSC8M_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// osc8m_arch_runstdby +#ifndef CONF_OSC8M_RUNSTDBY +#define CONF_OSC8M_RUNSTDBY 0 +#endif + +// Prescaler +// 1 +// 2 +// 4 +// 8 +// Prescaler for Internal 8Mhz OSC +// Default: No Prescaling +// osc8m_presc +#ifndef CONF_OSC8M_PRESC +#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val +#endif + +// Overwrite Default Osc Calibration +// Overwrite Default Osc Calibration +// osc8m_arch_overwrite_calibration +#ifndef CONF_OSC8M_OVERWRITE_CALIBRATION +#define CONF_OSC8M_OVERWRITE_CALIBRATION 0 +#endif + +// Osc Calibration Value <0-65535> +// Set the Oscillator Calibration Value +// Default: 1 +// osc8m_arch_calib +#ifndef CONF_OSC8M_CALIB +#define CONF_OSC8M_CALIB 0 +#endif + +// +// + +// 32kHz Internal Oscillator Configuration +// Indicates whether configuration for OSC32K is enabled or not +// enable_osc32k +#ifndef CONF_OSC32K_CONFIG +#define CONF_OSC32K_CONFIG 0 +#endif + +// 32kHz Internal Oscillator (OSC32K) Control +// Internal 32K Oscillator Enable +// Indicates whether Internal 32K Oscillator is enabled or not +// osc32k_arch_enable +#ifndef CONF_OSC32K_ENABLE +#define CONF_OSC32K_ENABLE 0 +#endif + +// On Demand Control +// Enable On Demand +// If this bit is 0: The oscillator is always on, if enabled. +// If this bit is 1, the oscillator will only be running when requested by a peripheral. +// osc32k_arch_ondemand +#ifndef CONF_OSC32K_ONDEMAND +#define CONF_OSC32K_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// osc32k_arch_runstdby +#ifndef CONF_OSC32K_RUNSTDBY +#define CONF_OSC32K_RUNSTDBY 0 +#endif + +// Enable 32Khz Output +// Enable 32 Khz Output +// osc32k_arch_en32k +#ifndef CONF_OSC32K_EN32K +#define CONF_OSC32K_EN32K 0 +#endif + +// Enable 1K +// Enable 1K +// osc32k_arch_en1k +#ifndef CONF_OSC32K_EN1K +#define CONF_OSC32K_EN1K 0 +#endif + +// Write Lock +// Write Lock +// osc32k_arch_wrtlock +#ifndef CONF_OSC32K_WRTLOCK +#define CONF_OSC32K_WRTLOCK 0 +#endif + +// Start up time for the 32K Oscillator +// 3 Clock Cycles (92us) +// 4 Clock Cycles (122us) +// 6 Clock Cycles (183us) +// 10 Clock Cycles (305us) +// 18 Clock Cycles (549us) +// 34 Clock Cycles (1038us) +// 66 Clock Cycles (2014us) +// 130 Clock Cycles (3967us) +// Start Up Time for the 32K Oscillator +// Default: 10 Clock Cycles (305us) +// osc32k_arch_startup +#ifndef CONF_OSC32K_STARTUP +#define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS +#endif + +// Overwrite Default Osc Calibration +// Overwrite Default Osc Calibration +// osc32k_arch_overwrite_calibration +#ifndef CONF_OSC32K_OVERWRITE_CALIBRATION +#define CONF_OSC32K_OVERWRITE_CALIBRATION 0 +#endif + +// Osc Calibration Value <0-65535> +// Set the Oscillator Calibration Value +// Default: 0 +// osc32k_arch_calib +#ifndef CONF_OSC32K_CALIB +#define CONF_OSC32K_CALIB 0 +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 0 +#endif + +// 32kHz External Crystal Oscillator (XOSC32K) Control +// External 32K Oscillator Enable +// Indicates whether External 32K Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 0 +#endif + +// On Demand +// Enable On Demand. +// If this bit is 0: The oscillator is always on, if enabled. +// If this bit is 1: the oscillator will only be running when requested by a peripheral. +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// Enable 1K +// Enable 1K +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// Enable 32Khz Output +// Enable 32 Khz Output +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Enable XTAL +// Enable XTAL +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 0 +#endif + +// Write Lock +// Write Lock +// xosc32k_arch_wrtlock +#ifndef CONF_XOSC32K_WRTLOCK +#define CONF_XOSC32K_WRTLOCK 0 +#endif + +// Automatic Amplitude Control Enable +// Indicates whether Automatic Amplitude Control is Enabled or not +// xosc32k_arch_aampen +#ifndef CONF_XOSC32K_AAMPEN +#define CONF_XOSC32K_AAMPEN 0 +#endif + +// Start up time for the 32K Oscillator +// 122 us +// 1068 us +// 62592 us +// 1125092 us +// 500092 us +// 1000092 us +// 2000092 us +// 4000092 us +// Start Up Time for the 32K Oscillator +// Default: 122 us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS +#endif + +// +// + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for External Multipurpose Osc is enabled or not +// enable_xosc +#ifndef CONF_XOSC_CONFIG +#define CONF_XOSC_CONFIG 0 +#endif + +// Frequency <400000-32000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC_FREQUENCY 400000 +#endif + +// External Multipurpose Crystal Oscillator (XOSC) Control +// Enable +// Indicates whether External Multipurpose Oscillator is enabled or not +// xosc_arch_enable +#ifndef CONF_XOSC_ENABLE +#define CONF_XOSC_ENABLE 0 +#endif + +// On Demand +// Enable On Demand +// If this bit is 0: The oscillator is always on, if enabled. +// If this bit is 1: the oscillator will only be running when requested by a peripheral. +// xosc_arch_ondemand +#ifndef CONF_XOSC_ONDEMAND +#define CONF_XOSC_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The oscillator is disabled in standby sleep mode. +// If this bit is 1: The oscillator is not stopped in standby sleep mode. +// xosc_arch_runstdby +#ifndef CONF_XOSC_RUNSTDBY +#define CONF_XOSC_RUNSTDBY 0 +#endif + +// Enable XTAL +// Enable XTAL +// xosc_arch_xtalen +#ifndef CONF_XOSC_XTALEN +#define CONF_XOSC_XTALEN 0 +#endif + +// Automatic Amplitude Control Enable +// Indicates whether Automatic Amplitude Control is Enabled or not +// xosc_arch_ampgc +#ifndef CONF_XOSC_AMPGC +#define CONF_XOSC_AMPGC 0 +#endif + +// Gain of the Oscillator +// 2Mhz +// 4Mhz +// 8Mhz +// 16Mhz +// 30Mhz +// Select the Gain of the oscillator +// xosc_arch_gain +#ifndef CONF_XOSC_GAIN +#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val +#endif + +// Start up time for the External Oscillator +// 31 us +// 61 us +// 122 us +// 244 us +// 488 us +// 977 us +// 1953 us +// 3906 us +// 7813 us +// 15625 us +// 31250 us +// 62500 us +// 125000 us +// 250000 us +// 500000 us +// 1000000 us +// Start Up Time for the External Oscillator +// Default: 31 us +// xosc_arch_startup +#ifndef CONF_XOSC_STARTUP +#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control +// Write Lock +// Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration +// osculp32k_arch_wrtlock +#ifndef CONF_OSCULP32K_WRTLOCK +#define CONF_OSCULP32K_WRTLOCK 0 +#endif + +// Overwrite Default Osc Calibration +// Overwrite Default Osc Calibration +// osculp32k_arch_overwrite_calibration +#ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION +#define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0 +#endif + +// Osc Calibration Value <0-255> +// Set the Oscillator Calibration Value +// Default: 0 +// osculp32k_arch_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0 +#endif + +// +// + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll48m +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 1 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// dfll48m_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK4_Val +#endif + +// DFLL Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll48m_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 1 +#endif + +// Wait Lock +// Indicates whether Wait Lock is Enables or not +// dfll48m_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 0 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass coarse lock is enabled or not +// dfll48m_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Quick Lock Disable +// dfll48m_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Chill Cycle Disable +// dfll48m_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 1 +#endif + +// On Demand +// Enable On Demand +// If this bit is 0: The DFLL is always on, if enabled. +// If this bit is 1: the DFLL will only be running when requested by a peripheral. +// dfll48m_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The DFLL is disabled in standby sleep mode. +// If this bit is 1: The DFLL is not stopped in standby sleep mode. +// dfll48m_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// USB Clock Recovery Mode +// dfll48m_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 1 +#endif + +#if CONF_DFLL_USBCRM == 1 +#if CONF_DFLL_QLDIS == 1 +#warning QLDIS must be cleared to speed up the lock phase +#endif +#if CONF_DFLL_CCDIS == 0 +#warning CCDIS should be set to speed up the lock phase +#endif +#endif + +// Lose Lock After Wake +// Lose Lock After Wake +// dfll48m_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Stable DFLL Frequency +// If 0: FINE calibration tracks changes in output frequency. +// If 1: FINE calibration register value will be fixed after a fine lock. +// dfll48m_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// Open Loop Mode +// Closed Loop Mode +// Mode +// dfll48m_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE CONF_DFLL_CLOSED_LOOP_MODE +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 1 +#endif + +// Fine Maximum Step <0x0-0x3FF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 1 +#endif + +// DFLL Multiply Factor<0-65535> +// Set the DFLL Multiply Factor +// Default: 0 +// dfll48m_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 48000 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll48m_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll48m_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f) +#endif + +// Fine Value <0x0-0x3FF> +// dfll48m_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x200) +#endif + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 +#define CONF_DEFAULT_CORASE \ + ((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos) + +#define CONF_DFLLVAL \ + SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \ + | SYSCTRL_DFLLVAL_FINE(512) + +#else +#define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE) + +#endif +// + +// +// + +// DPLL Configuration +// Indicates whether configuration for DPLL is enabled or not +// enable_fdpll96m +#ifndef CONF_DPLL_CONFIG +#define CONF_DPLL_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 0.4-32MHz (XOSC) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Select the clock source. +// fdpll96m_ref_clock +#ifndef CONF_DPLL_GCLK +#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +#if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K) +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val +#elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC) +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val +#else +#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val +#endif + +// DPLL Control +// ON Demand +// Enable On Demand +// If this bit is 0: The DFLL is always on, if enabled. +// If this bit is 1: the DFLL will only be running when requested by a peripheral. +// fdpll96m_arch_ondemand +#ifndef CONF_DPLL_ONDEMAND +#define CONF_DPLL_ONDEMAND 1 +#endif + +// Run In Standby +// Run In standby Mode +// If this bit is 0: The DFLL is disabled in standby sleep mode. +// If this bit is 1: The DFLL is not stopped in standby sleep mode. +// fdpll96m_arch_runstdby +#ifndef CONF_DPLL_RUNSTDBY +#define CONF_DPLL_RUNSTDBY 0 +#endif + +// DPLL Enable +// Indicates whether DPLL is enabled or not +// fdpll96m_arch_enable +#ifndef CONF_DPLL_ENABLE +#define CONF_DPLL_ENABLE 0 +#endif + +// Lock ByPass +// Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low +// fdpll96m_arch_lbypass +#ifndef CONF_DPLL_LBYPASS +#define CONF_DPLL_LBYPASS 0 +#endif + +// Clock Divider <0-2047> +// Clock Division Factor (Applicable if reference clock is XOSC) +// fdpll96m_clock_div +#ifndef CONF_DPLL_DIV +#define CONF_DPLL_DIV 0 +#endif + +// DPLL LDRFRAC<0-15> +// Set the fractional part of the frequency multiplier. +// fdpll96m_ldrfrac +#ifndef CONF_DPLL_LDRFRAC +#define CONF_DPLL_LDRFRAC 13 +#endif + +// DPLL LDR <0-4095> +// Set the integer part of the frequency multiplier. +// fdpll96m_ldr +#ifndef CONF_DPLL_LDR +#define CONF_DPLL_LDR 1463 +#endif + +// +// + +#define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val +#define CONF_DPLL_WUF 0 +#define CONF_DPLL_LPEN 0 +#define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val + +// <<< end of configuration section >>> + +#endif // HPL_SYSCTRL_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_systick_config.h b/atmel-samd/asf4_conf/samd21/hpl_systick_config.h new file mode 100644 index 0000000000000..a7f2f36208fa7 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_tc_config.h b/atmel-samd/asf4_conf/samd21/hpl_tc_config.h new file mode 100644 index 0000000000000..90e9b07357475 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_tc_config.h @@ -0,0 +1,181 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 1 +#endif + +// Basic settings + +// Prescaler +// No division +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 64 +// Divide by 256 +// Divide by 1024 +// This defines the prescaler value +// tc_prescaler +#ifndef CONF_TC3_PRESCALER +#define CONF_TC3_PRESCALER TC_CTRLA_PRESCALER_DIV8_Val +#endif + +// Period Value <0x00000000-0xFFFFFFFF> +// tc_per +#ifndef CONF_TC3_PER +#define CONF_TC3_PER 0x32 +#endif +// + +// PWM Waveform Output settings +// Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tc_arch_wave_per_val +#ifndef CONF_TC3_WAVE_PER_VAL +#define CONF_TC3_WAVE_PER_VAL 0x3e8 +#endif + +// Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tc_arch_wave_duty_val +#ifndef CONF_TC3_WAVE_DUTY_VAL +#define CONF_TC3_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC3_CC0 \ + ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) +#endif + +// + +// Advanced settings +// Mode +// Counter in 16-bit mode +// Counter in 32-bit mode +// These bits mode +// tc_arch_mode +#ifndef CONF_TC3_MODE +#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val +#endif +// + +// Advanced settings +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +// Run in standby +// Indicates whether the will continue running in standby sleep mode or not +// tc_arch_runstdby +#ifndef CONF_TC3_RUNSTDBY +#define CONF_TC3_RUNSTDBY 0 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC3_PRESCSYNC +#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_DIR 0 +//#define CONF_TC3_ONESHOT 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC3_INVEN0 0 +//#define CONF_TC3_INVEN1 0 +//#define CONF_TC3_CPTEN0 0 +//#define CONF_TC3_CPTEN1 0 + +// Debug Running Mode +// Indicates whether the Debug Running Mode is enabled or not +// tc_arch_dbgrun +#ifndef CONF_TC3_DBGRUN +#define CONF_TC3_DBGRUN 0 +#endif + +// + +// Event control +// timer_event_control +#ifndef CONF_TC3_EVENT_CONTROL_ENABLE +#define CONF_TC3_EVENT_CONTROL_ENABLE 0 +#endif + +// Overflow/Underflow Event Output +// Generates event for counter overflows/underflows +// tc_arch_ovfeo +#ifndef CONF_TC3_OVFEO +#define CONF_TC3_OVFEO 0 +#endif + +// TC Event Asynchronous input +// Enables Asynchronous input events to the TC +// tc_arch_tcei +#ifndef CONF_TC3_TCEI +#define CONF_TC3_TCEI 0 +#endif + +// TC Inverted Event Input Polarity +// Used to invert the asynchronous input event source +// tc_arch_tceinv +#ifndef CONF_TC3_TCINV +#define CONF_TC3_TCINV 0 +#endif + +// Event Action +// Defines the event action the TC will perform on an event +// Event action disabled +// Start, restart or retrigger TC on event +// Count on event +// Start TC on event +// Period captured in CC0, pulse width in CC1 +// Period captured in CC1, pulse width in CC0 +// tc_arch_evact +#ifndef CONF_TC3_EVACT +#define CONF_TC3_EVACT TC_EVCTRL_EVACT_OFF_Val +#endif + +// Match/Capture channel 0 Event +// Enables the generation of an event for every match or capture on channel 0 +// tc_arch_mceo0 +#ifndef CONF_TC3_MCEO0 +#define CONF_TC3_MCEO0 0 +#endif +// Match/Capture channel 1 Event +// Enables the generation of an event for every match or capture on channel 1 +// tc_arch_mceo1 +#ifndef CONF_TC3_MCEO1 +#define CONF_TC3_MCEO1 0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/hpl_usb_config.h b/atmel-samd/asf4_conf/samd21/hpl_usb_config.h new file mode 100644 index 0000000000000..b052887d6b1d3 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/hpl_usb_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// USB Device HAL Configuration + +// Max number of endpoints supported +// Limits the number of endpoints (described by EP address) can be used in app. +// 1 (EP0 only) +// 2 (EP0 + 1 endpoint) +// 3 (EP0 + 2 endpoints) +// 4 (EP0 + 3 endpoints) +// 5 (EP0 + 4 endpoints) +// 6 (EP0 + 5 endpoints) +// 7 (EP0 + 6 endpoints) +// 8 (EP0 + 7 endpoints) +// Max possible (by "Max Endpoint Number" config) +// usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 +#endif + +// + +// Max Endpoint Number supported +// Limits the max endpoint number. +// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// Reduce the value according to specific device design, to cut-off memory usage. +// 0 (only EP0) +// 1 (EP 0x81 or 0x01) +// 2 (EP 0x82 or 0x02) +// 3 (EP 0x83 or 0x03) +// 4 (EP 0x84 or 0x04) +// 5 (EP 0x85 or 0x05) +// 6 (EP 0x86 or 0x06) +// 7 (EP 0x87 or 0x07) +// Max possible (by HW) +// The number of physical endpoints - 1 +// usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 +#endif + +// USB Speed Limit +// Limits the working speed of the device. +// Full speed +// Low Speed +// usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// Cache buffer size for EP0 +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// Cache configuration EP1 +// Cache buffer size for EP1 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 64 +#endif + +// Cache buffer size for EP1 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 64 +#endif +// + +// Cache configuration EP2 +// Cache buffer size for EP2 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 64 +#endif + +// Cache buffer size for EP2 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// + +// Cache configuration EP3 +// Cache buffer size for EP3 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 64 +#endif + +// Cache buffer size for EP3 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// + +// Cache configuration EP4 +// Cache buffer size for EP4 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 64 +#endif + +// Cache buffer size for EP4 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// + +// Cache configuration EP5 +// Cache buffer size for EP5 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 64 +#endif + +// Cache buffer size for EP5 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// + +// Cache configuration EP6 +// Cache buffer size for EP6 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 64 +#endif + +// Cache buffer size for EP6 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// + +// Cache configuration EP7 +// Cache buffer size for EP7 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 64 +#endif + +// Cache buffer size for EP7 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h b/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h new file mode 100644 index 0000000000000..c0831aae9c146 --- /dev/null +++ b/atmel-samd/asf4_conf/samd21/peripheral_clk_config.h @@ -0,0 +1,369 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ADC Clock Source +// adc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for ADC. +#ifndef CONF_GCLK_ADC_SRC +#define CONF_GCLK_ADC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_ADC_FREQUENCY + * \brief ADC's Clock frequency + */ +#ifndef CONF_GCLK_ADC_FREQUENCY +#define CONF_GCLK_ADC_FREQUENCY 1000000 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM2_CORE_SRC +#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM2_SLOW_SRC +#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY + * \brief SERCOM2's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY +#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 1000000 +#endif + +/** + * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY + * \brief SERCOM2's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000 +#endif + +// RTC Clock Source +// rtc_clk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1000000 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC3_SRC +#define CONF_GCLK_TC3_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC3_FREQUENCY + * \brief TC3's Clock frequency + */ +#ifndef CONF_GCLK_TC3_FREQUENCY +#define CONF_GCLK_TC3_FREQUENCY 1000000 +#endif + +// DAC Clock Source +// dac_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 1000000 +#endif + +// USB Clock Source +// usb_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_CLKCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 48000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_dmac_config.h b/atmel-samd/asf4_conf/samd51/hpl_dmac_config.h new file mode 100644 index 0000000000000..90499fc27feac --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_dmac_config.h @@ -0,0 +1,7277 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 1 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 16 is running in standby mode or not +// dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 17 is running in standby mode or not +// dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 18 is running in standby mode or not +// dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 19 is running in standby mode or not +// dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 20 is running in standby mode or not +// dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 21 is running in standby mode or not +// dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 22 is running in standby mode or not +// dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 23 is running in standby mode or not +// dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// + +// Channel 24 settings +// dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 24 is running in standby mode or not +// dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// + +// Channel 25 settings +// dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 25 is running in standby mode or not +// dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// + +// Channel 26 settings +// dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 26 is running in standby mode or not +// dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// + +// Channel 27 settings +// dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 27 is running in standby mode or not +// dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// + +// Channel 28 settings +// dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 28 is running in standby mode or not +// dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// + +// Channel 29 settings +// dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 29 is running in standby mode or not +// dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// + +// Channel 30 settings +// dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 30 is running in standby mode or not +// dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// + +// Channel 31 settings +// dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 31 is running in standby mode or not +// dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h b/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h new file mode 100644 index 0000000000000..ca0e35a514533 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_gclk_config.h @@ -0,0 +1,914 @@ +// The clock tree starts with 48mhz DFLL48M based on USB. GCLK5 divides it down +// to 2mhz which DPLL0 boosts to 120mhz. This is then used by GCLK0 to clock the +// core and main bus. GCLK1 is 48mhz based on DFLL48M which is used for USB. +// GCLK4 also outputs the 120mhz clock for monitoring. + + +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 1 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 1 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 24 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// Generic clock generator 8 configuration +// Indicates whether generic clock 8 configuration is enabled or not +// enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 8 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 8 +// gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 8 division <0x0000-0xFFFF> +// gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// +// + +// Generic clock generator 9 configuration +// Indicates whether generic clock 9 configuration is enabled or not +// enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 9 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 9 +// gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 9 division <0x0000-0xFFFF> +// gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// +// + +// Generic clock generator 10 configuration +// Indicates whether generic clock 10 configuration is enabled or not +// enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 10 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 10 +// gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 10 division <0x0000-0xFFFF> +// gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// +// + +// Generic clock generator 11 configuration +// Indicates whether generic clock 11 configuration is enabled or not +// enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 11 source// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 11 +// gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 11 division <0x0000-0xFFFF> +// gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_mclk_config.h b/atmel-samd/asf4_conf/samd51/hpl_mclk_config.h new file mode 100644 index 0000000000000..a5a7de53c2596 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_mclk_config.h @@ -0,0 +1,104 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// High-Speed Clock Division +// Divide by 1 +// mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 0 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_osc32kctrl_config.h b/atmel-samd/asf4_conf/samd51/hpl_osc32kctrl_config.h new file mode 100644 index 0000000000000..ccb2627480292 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_osc32kctrl_config.h @@ -0,0 +1,163 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ +#define CONF_RTCCTRL_1KHZ 1 +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 1 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 0 +#endif + +// Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x3F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h b/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h new file mode 100644 index 0000000000000..cd11866059bc3 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_oscctrl_config.h @@ -0,0 +1,634 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC0 is enabled or not +// enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +// +// + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC1 is enabled or not +// enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 0 +#endif +// +// + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source +// dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 1 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 1 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// Fine Maximum Step <0x0-0xFF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0xFF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +// + +// + +// + +// FDPLL0 Configuration +// Indicates whether configuration for FDPLL0 is enabled or not +// enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 1 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_PCHCTRL_GEN_GCLK5_Val +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0x0 +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 59 +#endif + +// Clock Divider <0x0-0x7FF> +// fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x0 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +// +// +// FDPLL1 Configuration +// Indicates whether configuration for FDPLL1 is enabled or not +// enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_rtc_config.h b/atmel-samd/asf4_conf/samd51/hpl_rtc_config.h new file mode 100644 index 0000000000000..b99821da5b33c --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_rtc_config.h @@ -0,0 +1,137 @@ +/* Auto-generated config file hpl_rtc_config.h */ +#ifndef HPL_RTC_CONFIG_H +#define HPL_RTC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic settings + +#ifndef CONF_RTC_ENABLE +#define CONF_RTC_ENABLE 1 +#endif + +// Prescaler configuration +// <0x0=>OFF(Peripheral clock divided by 1) +// <0x1=>Peripheral clock divided by 1 +// <0x2=>Peripheral clock divided by 2 +// <0x3=>Peripheral clock divided by 4 +// <0x4=>Peripheral clock divided by 8 +// <0x5=>Peripheral clock divided by 16 +// <0x6=>Peripheral clock divided by 32 +// <0x7=>Peripheral clock divided by 64 +// <0x8=>Peripheral clock divided by 128 +// <0x9=>Peripheral clock divided by 256 +// <0xA=>Peripheral clock divided by 512 +// <0xB=>Peripheral clock divided by 1024 +// These bits define the RTC clock relative to the peripheral clock +// rtc_arch_prescaler +#ifndef CONF_RTC_PRESCALER +#define CONF_RTC_PRESCALER 0x0 + +#endif + +// Compare Value <1-4294967295> +// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), +// by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. +// rtc_arch_comp_val + +#ifndef CONF_RTC_COMP_VAL +#define CONF_RTC_COMP_VAL 1 + +#endif + +// Event control +// rtc_event_control +#ifndef CONF_RTC_EVENT_CONTROL_ENABLE +#define CONF_RTC_EVENT_CONTROL_ENABLE 0 +#endif + +// Periodic Interval 0 Event Output +// This bit indicates whether Periodic interval 0 event is enabled and will be generated +// rtc_pereo0 +#ifndef CONF_RTC_PEREO0 +#define CONF_RTC_PEREO0 0 +#endif +// Periodic Interval 1 Event Output +// This bit indicates whether Periodic interval 1 event is enabled and will be generated +// rtc_pereo1 +#ifndef CONF_RTC_PEREO1 +#define CONF_RTC_PEREO1 0 +#endif +// Periodic Interval 2 Event Output +// This bit indicates whether Periodic interval 2 event is enabled and will be generated +// rtc_pereo2 +#ifndef CONF_RTC_PEREO2 +#define CONF_RTC_PEREO2 0 +#endif +// Periodic Interval 3 Event Output +// This bit indicates whether Periodic interval 3 event is enabled and will be generated +// rtc_pereo3 +#ifndef CONF_RTC_PEREO3 +#define CONF_RTC_PEREO3 0 +#endif +// Periodic Interval 4 Event Output +// This bit indicates whether Periodic interval 4 event is enabled and will be generated +// rtc_pereo4 +#ifndef CONF_RTC_PEREO4 +#define CONF_RTC_PEREO4 0 +#endif +// Periodic Interval 5 Event Output +// This bit indicates whether Periodic interval 5 event is enabled and will be generated +// rtc_pereo5 +#ifndef CONF_RTC_PEREO5 +#define CONF_RTC_PEREO5 0 +#endif +// Periodic Interval 6 Event Output +// This bit indicates whether Periodic interval 6 event is enabled and will be generated +// rtc_pereo6 +#ifndef CONF_RTC_PEREO6 +#define CONF_RTC_PEREO6 0 +#endif +// Periodic Interval 7 Event Output +// This bit indicates whether Periodic interval 7 event is enabled and will be generated +// rtc_pereo7 +#ifndef CONF_RTC_PEREO7 +#define CONF_RTC_PEREO7 0 +#endif + +// Compare 0 Event Output +// This bit indicates whether Compare O event is enabled and will be generated +// rtc_cmpeo0 +#ifndef CONF_RTC_COMPE0 +#define CONF_RTC_COMPE0 0 +#endif + +// Compare 1 Event Output +// This bit indicates whether Compare 1 event is enabled and will be generated +// rtc_cmpeo1 +#ifndef CONF_RTC_COMPE1 +#define CONF_RTC_COMPE1 0 +#endif +// Overflow Event Output +// This bit indicates whether Overflow event is enabled and will be generated +// rtc_ovfeo +#ifndef CONF_RTC_OVFEO +#define CONF_RTC_OVFEO 0 +#endif + +// Tamper Event Output +// This bit indicates whether Tamper event output is enabled and will be generated +// rtc_tampereo +#ifndef CONF_RTC_TAMPEREO +#define CONF_RTC_TAMPEREO 0 +#endif + +// Tamper Event Input +// This bit indicates whether Tamper event input is enabled and will be generated +// rtc_tampevei +#ifndef CONF_RTC_TAMPEVEI +#define CONF_RTC_TAMPEVEI 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_RTC_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_systick_config.h b/atmel-samd/asf4_conf/samd51/hpl_systick_config.h new file mode 100644 index 0000000000000..a7f2f36208fa7 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_systick_config.h @@ -0,0 +1,18 @@ +/* Auto-generated config file hpl_systick_config.h */ +#ifndef HPL_SYSTICK_CONFIG_H +#define HPL_SYSTICK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Advanced settings +// SysTick exception request +// Indicates whether the generation of SysTick exception is enabled or not +// systick_arch_tickint +#ifndef CONF_SYSTICK_TICKINT +#define CONF_SYSTICK_TICKINT 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_SYSTICK_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_tc_config.h b/atmel-samd/asf4_conf/samd51/hpl_tc_config.h new file mode 100644 index 0000000000000..38d48e9b67c51 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_tc_config.h @@ -0,0 +1,209 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +// Basic settings +// Prescaler +// <0=> No division +// <1=> Divide by 2 +// <2=> Divide by 4 +// <3=> Divide by 8 +// <4=> Divide by 16 +// <5=> Divide by 64 +// <6=> Divide by 256 +// <7=> Divide by 1024 +// This defines the prescaler value +// tc_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0 +#endif +// + +// PWM Waveform Output settings +// Waveform Period Value (uS) <0x00-0xFFFFFFFF> +// The unit of this value is us. +// tc_arch_wave_per_val +#ifndef CONF_TC0_WAVE_PER_VAL +#define CONF_TC0_WAVE_PER_VAL 0x3e8 +#endif + +// Waveform Duty Value (0.1%) <0x00-0x03E8> +// The unit of this value is 1/1000. +// tc_arch_wave_duty_val +#ifndef CONF_TC0_WAVE_DUTY_VAL +#define CONF_TC0_WAVE_DUTY_VAL 0x1f4 +#endif + +/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ +#if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 \ + ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 64000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 256000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) + +#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val +#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1024000000 - 1)) +#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) +#endif + +// + +// Advanced settings +// Mode +// Counter in 16-bit mode +// Counter in 32-bit mode +// These bits mode +// tc_mode +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT16_Val +#endif + +// Period Value <0x00000000-0xFFFFFFFF> +// tc_per +#ifndef CONF_TC0_PER +#define CONF_TC0_PER 0x32 +#endif +// + +// Advanced settings +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the will continue running in standby sleep mode or not +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// On-Demand +// Indicates whether the TC0's on-demand mode is on or not +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// Auto Lock +// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event +// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event +// tc_arch_alock +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CAPTEN0 0 +//#define CONF_TC0_CAPTEN1 0 +//#define CONF_TC0_COPEN0 0 +//#define CONF_TC0_COPEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_DIR 0 +//#define CONF_TC0_ONESHOT 0 +//#define CONF_TC0_LUPD 0 + +// Debug Running Mode +// Indicates whether the Debug Running Mode is enabled or not +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_INVEN0 0 +//#define CONF_TC0_INVEN1 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_PERBUF 0 + +/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ +//#define CONF_TC0_CCBUF0 0 +//#define CONF_TC0_CCBUF1 0 + +// + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/hpl_usb_config.h b/atmel-samd/asf4_conf/samd51/hpl_usb_config.h new file mode 100644 index 0000000000000..b052887d6b1d3 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/hpl_usb_config.h @@ -0,0 +1,355 @@ +/* Auto-generated config file hpl_usb_config.h */ +#ifndef HPL_USB_CONFIG_H +#define HPL_USB_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#define CONF_USB_N_0 0 +#define CONF_USB_N_1 1 +#define CONF_USB_N_2 2 +#define CONF_USB_N_3 3 +#define CONF_USB_N_4 4 +#define CONF_USB_N_5 5 +#define CONF_USB_N_6 6 +#define CONF_USB_N_7 7 +#define CONF_USB_N_8 8 +#define CONF_USB_N_9 9 +#define CONF_USB_N_10 10 +#define CONF_USB_N_11 11 +#define CONF_USB_N_12 12 +#define CONF_USB_N_13 13 +#define CONF_USB_N_14 14 +#define CONF_USB_N_15 15 + +#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) +#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) + +// USB Device HAL Configuration + +// Max number of endpoints supported +// Limits the number of endpoints (described by EP address) can be used in app. +// 1 (EP0 only) +// 2 (EP0 + 1 endpoint) +// 3 (EP0 + 2 endpoints) +// 4 (EP0 + 3 endpoints) +// 5 (EP0 + 4 endpoints) +// 6 (EP0 + 5 endpoints) +// 7 (EP0 + 6 endpoints) +// 8 (EP0 + 7 endpoints) +// Max possible (by "Max Endpoint Number" config) +// usbd_num_ep_sp +#ifndef CONF_USB_D_NUM_EP_SP +#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 +#endif + +// + +// Max Endpoint Number supported +// Limits the max endpoint number. +// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. +// Reduce the value according to specific device design, to cut-off memory usage. +// 0 (only EP0) +// 1 (EP 0x81 or 0x01) +// 2 (EP 0x82 or 0x02) +// 3 (EP 0x83 or 0x03) +// 4 (EP 0x84 or 0x04) +// 5 (EP 0x85 or 0x05) +// 6 (EP 0x86 or 0x06) +// 7 (EP 0x87 or 0x07) +// Max possible (by HW) +// The number of physical endpoints - 1 +// usbd_arch_max_ep_n +#ifndef CONF_USB_D_MAX_EP_N +#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 +#endif + +// USB Speed Limit +// Limits the working speed of the device. +// Full speed +// Low Speed +// usbd_arch_speed +#ifndef CONF_USB_D_SPEED +#define CONF_USB_D_SPEED USB_SPEED_FS +#endif + +// Cache buffer size for EP0 +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// usb_arch_ep0_cache +#ifndef CONF_USB_EP0_CACHE +#define CONF_USB_EP0_CACHE 64 +#endif + +// Cache configuration EP1 +// Cache buffer size for EP1 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep1_cache +#ifndef CONF_USB_EP1_CACHE +#define CONF_USB_EP1_CACHE 64 +#endif + +// Cache buffer size for EP1 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep1_I_CACHE +#ifndef CONF_USB_EP1_I_CACHE +#define CONF_USB_EP1_I_CACHE 64 +#endif +// + +// Cache configuration EP2 +// Cache buffer size for EP2 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep2_cache +#ifndef CONF_USB_EP2_CACHE +#define CONF_USB_EP2_CACHE 64 +#endif + +// Cache buffer size for EP2 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep2_I_CACHE +#ifndef CONF_USB_EP2_I_CACHE +#define CONF_USB_EP2_I_CACHE 0 +#endif +// + +// Cache configuration EP3 +// Cache buffer size for EP3 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep3_cache +#ifndef CONF_USB_EP3_CACHE +#define CONF_USB_EP3_CACHE 64 +#endif + +// Cache buffer size for EP3 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep3_I_CACHE +#ifndef CONF_USB_EP3_I_CACHE +#define CONF_USB_EP3_I_CACHE 0 +#endif +// + +// Cache configuration EP4 +// Cache buffer size for EP4 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep4_cache +#ifndef CONF_USB_EP4_CACHE +#define CONF_USB_EP4_CACHE 64 +#endif + +// Cache buffer size for EP4 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep4_I_CACHE +#ifndef CONF_USB_EP4_I_CACHE +#define CONF_USB_EP4_I_CACHE 0 +#endif +// + +// Cache configuration EP5 +// Cache buffer size for EP5 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep5_cache +#ifndef CONF_USB_EP5_CACHE +#define CONF_USB_EP5_CACHE 64 +#endif + +// Cache buffer size for EP5 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep5_I_CACHE +#ifndef CONF_USB_EP5_I_CACHE +#define CONF_USB_EP5_I_CACHE 0 +#endif +// + +// Cache configuration EP6 +// Cache buffer size for EP6 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep6_cache +#ifndef CONF_USB_EP6_CACHE +#define CONF_USB_EP6_CACHE 64 +#endif + +// Cache buffer size for EP6 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep6_I_CACHE +#ifndef CONF_USB_EP6_I_CACHE +#define CONF_USB_EP6_I_CACHE 0 +#endif +// + +// Cache configuration EP7 +// Cache buffer size for EP7 OUT +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_arch_ep7_cache +#ifndef CONF_USB_EP7_CACHE +#define CONF_USB_EP7_CACHE 64 +#endif + +// Cache buffer size for EP7 IN +// Cache is used because the USB hardware always uses DMA which requires specific memory feature. +// This cache must not be allocated if you plan to use the endpoint as control endpoint. +// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size +// <0=> No cache +// <8=> Cached by 8 bytes buffer +// <16=> Cached by 16 bytes buffer +// <32=> Cached by 32 bytes buffer +// <64=> Cached by 64 bytes buffer +// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) +// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) +// usb_ep7_I_CACHE +#ifndef CONF_USB_EP7_I_CACHE +#define CONF_USB_EP7_I_CACHE 0 +#endif +// + +// <<< end of configuration section >>> + +#endif // HPL_USB_CONFIG_H diff --git a/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h b/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h new file mode 100644 index 0000000000000..631845dfbaf20 --- /dev/null +++ b/atmel-samd/asf4_conf/samd51/peripheral_clk_config.h @@ -0,0 +1,926 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// ADC Clock Source +// adc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for ADC. +#ifndef CONF_GCLK_ADC0_SRC +#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_ADC0_FREQUENCY + * \brief ADC0's Clock frequency + */ +#ifndef CONF_GCLK_ADC0_FREQUENCY +#define CONF_GCLK_ADC0_FREQUENCY 120000000 +#endif + +// DAC Clock Source + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// dac_gclk_selection +// Select the clock source for DAC. +#ifndef CONF_GCLK_DAC_SRC +#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_DAC_FREQUENCY + * \brief DAC's Clock frequency + */ +#ifndef CONF_GCLK_DAC_FREQUENCY +#define CONF_GCLK_DAC_FREQUENCY 120000000 +#endif + +// EVSYS Channel 0 Clock Source +// evsys_clk_selection_0 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 0. +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC +#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 1 Clock Source +// evsys_clk_selection_1 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 1. +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC +#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 2 Clock Source +// evsys_clk_selection_2 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 2. +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC +#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 3 Clock Source +// evsys_clk_selection_3 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 3. +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC +#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 4 Clock Source +// evsys_clk_selection_4 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 4. +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC +#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 5 Clock Source +// evsys_clk_selection_5 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 5. +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC +#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 6 Clock Source +// evsys_clk_selection_6 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 6. +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC +#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 7 Clock Source +// evsys_clk_selection_7 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 7. +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC +#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 8 Clock Source +// evsys_clk_selection_8 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 8. +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC +#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 9 Clock Source +// evsys_clk_selection_9 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 9. +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC +#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 10 Clock Source +// evsys_clk_selection_10 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 10. +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC +#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 120000000.0 +#endif + +// EVSYS Channel 11 Clock Source +// evsys_clk_selection_11 + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for channel 11. +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC +#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY + * \brief EVSYS's Clock frequency + */ + +#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY +#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 120000000.0 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 120000000 +#endif + +// RTC Clock Source +// rtc_clk_selection +// RTC source +// Select the clock source for RTC. +#ifndef CONF_GCLK_RTC_SRC +#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE +#endif + +/** + * \def CONF_GCLK_RTC_FREQUENCY + * \brief RTC's Clock frequency + */ +#ifndef CONF_GCLK_RTC_FREQUENCY +#define CONF_GCLK_RTC_FREQUENCY 1024 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM1_CORE_SRC +#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM1_SLOW_SRC +#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY + * \brief SERCOM1's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY +#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 12000000 +#endif + +/** + * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY + * \brief SERCOM1's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 12000000 +#endif + +// USB Clock Source +// usb_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for USB. +#ifndef CONF_GCLK_USB_SRC +#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK1_Val + +#endif + +/** + * \def CONF_GCLK_USB_FREQUENCY + * \brief USB's Clock frequency + */ +#ifndef CONF_GCLK_USB_FREQUENCY +#define CONF_GCLK_USB_FREQUENCY 48000000 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/atmel-samd/asf_conf/conf_clocks_crystalless.h b/atmel-samd/asf_conf/conf_clocks_crystalless.h deleted file mode 100644 index 5e7ad962db387..0000000000000 --- a/atmel-samd/asf_conf/conf_clocks_crystalless.h +++ /dev/null @@ -1,198 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Clock configuration - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -#ifndef CONF_CLOCKS_H_INCLUDED -# define CONF_CLOCKS_H_INCLUDED - -/* System clock bus configuration */ -# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false -# define CONF_CLOCK_FLASH_WAIT_STATES 2 -# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 - -/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */ -# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1 -# define CONF_CLOCK_OSC8M_ON_DEMAND true -# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ -# define CONF_CLOCK_XOSC_ENABLE false -# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL -# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 -# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true -# define CONF_CLOCK_XOSC_ON_DEMAND true -# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ -# define CONF_CLOCK_XOSC32K_ENABLE false -# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 -# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false -# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false -# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_XOSC32K_ON_DEMAND false -# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY true - -/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ -# define CONF_CLOCK_OSC32K_ENABLE false -# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 -# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ON_DEMAND true -# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ -// USB Clock Source fixed at DFLL. -# define CONF_CLOCK_DFLL_ENABLE true -# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_USB_RECOVERY -# define CONF_CLOCK_DFLL_ON_DEMAND true - -/* DFLL open loop mode configuration */ -# define CONF_CLOCK_DFLL_FINE_VALUE (512) - -/* DFLL closed loop mode configuration */ -# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 -# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768) -# define CONF_CLOCK_DFLL_QUICK_LOCK true -# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true -# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true -# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true -# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4) -# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4) - -/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ -# define CONF_CLOCK_DPLL_ENABLE false -# define CONF_CLOCK_DPLL_ON_DEMAND true -# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false -# define CONF_CLOCK_DPLL_LOCK_BYPASS false -# define CONF_CLOCK_DPLL_WAKE_UP_FAST false -# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false - -# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT -# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K -# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT - -# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 -# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 -# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 - -/* DPLL GCLK reference configuration */ -# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 -/* DPLL GCLK lock timer configuration */ -# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 - -/* Set this to true to configure the GCLK when running clocks_init. If set to - * false, none of the GCLK generators will be configured in clocks_init(). */ -# define CONF_CLOCK_CONFIGURE_GCLK true - -/* Configure GCLK generator 0 (Main Clock) */ -# define CONF_CLOCK_GCLK_0_ENABLE true -# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true -# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL -# define CONF_CLOCK_GCLK_0_PRESCALER 1 -# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false - -/* Configure GCLK generator 1 */ -# define CONF_CLOCK_GCLK_1_ENABLE false -# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_1_PRESCALER 1 -# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false - -/* Configure GCLK generator 2 (RTC) */ -# define CONF_CLOCK_GCLK_2_ENABLE false -# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K -# define CONF_CLOCK_GCLK_2_PRESCALER 32 -# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false - -/* Configure GCLK generator 3 */ -# define CONF_CLOCK_GCLK_3_ENABLE true -# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY true -# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_3_PRESCALER 1 -# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false - -/* Configure GCLK generator 4 */ -# define CONF_CLOCK_GCLK_4_ENABLE false -# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_4_PRESCALER 1 -# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false - -/* Configure GCLK generator 5 */ -# define CONF_CLOCK_GCLK_5_ENABLE false -# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_5_PRESCALER 1 -# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false - -/* Configure GCLK generator 6 */ -# define CONF_CLOCK_GCLK_6_ENABLE false -# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_6_PRESCALER 1 -# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false - -/* Configure GCLK generator 7 */ -# define CONF_CLOCK_GCLK_7_ENABLE false -# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_7_PRESCALER 1 -# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false - -/* Configure GCLK generator 8 */ -# define CONF_CLOCK_GCLK_8_ENABLE false -# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_8_PRESCALER 1 -# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false - -#endif /* CONF_CLOCKS_H_INCLUDED */ diff --git a/atmel-samd/asf_conf/conf_clocks_external_32k.h b/atmel-samd/asf_conf/conf_clocks_external_32k.h deleted file mode 100644 index 5af6ad4d6227f..0000000000000 --- a/atmel-samd/asf_conf/conf_clocks_external_32k.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Clock configuration - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#include - -#ifndef CONF_CLOCKS_H_INCLUDED -# define CONF_CLOCKS_H_INCLUDED - -/* System clock bus configuration */ -# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false -# define CONF_CLOCK_FLASH_WAIT_STATES 2 -# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 -# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1 - -/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */ -# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1 -# define CONF_CLOCK_OSC8M_ON_DEMAND true -# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */ -# define CONF_CLOCK_XOSC_ENABLE false -# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL -# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768 -# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true -# define CONF_CLOCK_XOSC_ON_DEMAND true -# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */ -# define CONF_CLOCK_XOSC32K_ENABLE true -# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL -# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536 -# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false -# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false -# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_XOSC32K_ON_DEMAND false -# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY true - -/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */ -# define CONF_CLOCK_OSC32K_ENABLE false -# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130 -# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true -# define CONF_CLOCK_OSC32K_ON_DEMAND true -# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false - -/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */ -# define CONF_CLOCK_DFLL_ENABLE true -# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_CLOSED -# define CONF_CLOCK_DFLL_ON_DEMAND true - -/* DFLL open loop mode configuration */ -# define CONF_CLOCK_DFLL_FINE_VALUE (512) - -/* DFLL closed loop mode configuration */ -# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1 -# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768) -# define CONF_CLOCK_DFLL_QUICK_LOCK true -# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true -# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true -# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true -# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4) -# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4) - -/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */ -# define CONF_CLOCK_DPLL_ENABLE false -# define CONF_CLOCK_DPLL_ON_DEMAND true -# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false -# define CONF_CLOCK_DPLL_LOCK_BYPASS false -# define CONF_CLOCK_DPLL_WAKE_UP_FAST false -# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false - -# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT -# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K -# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT - -# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768 -# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1 -# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000 - -/* DPLL GCLK reference configuration */ -# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1 -/* DPLL GCLK lock timer configuration */ -# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1 - -/* Set this to true to configure the GCLK when running clocks_init. If set to - * false, none of the GCLK generators will be configured in clocks_init(). */ -# define CONF_CLOCK_CONFIGURE_GCLK true - -/* Configure GCLK generator 0 (Main Clock) */ -# define CONF_CLOCK_GCLK_0_ENABLE true -# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY true -# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_DFLL -# define CONF_CLOCK_GCLK_0_PRESCALER 1 -# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false - -/* Configure GCLK generator 1 */ -# define CONF_CLOCK_GCLK_1_ENABLE true -# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K -# define CONF_CLOCK_GCLK_1_PRESCALER 1 -# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE true - -/* Configure GCLK generator 2 (RTC) */ -# define CONF_CLOCK_GCLK_2_ENABLE false -# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K -# define CONF_CLOCK_GCLK_2_PRESCALER 32 -# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false - -/* Configure GCLK generator 3 */ -# define CONF_CLOCK_GCLK_3_ENABLE true -# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY true -# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_3_PRESCALER 1 -# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false - -/* Configure GCLK generator 4 */ -# define CONF_CLOCK_GCLK_4_ENABLE false -# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_4_PRESCALER 1 -# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false - -/* Configure GCLK generator 5 */ -# define CONF_CLOCK_GCLK_5_ENABLE false -# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_5_PRESCALER 1 -# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false - -/* Configure GCLK generator 6 */ -# define CONF_CLOCK_GCLK_6_ENABLE false -# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_6_PRESCALER 1 -# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false - -/* Configure GCLK generator 7 */ -# define CONF_CLOCK_GCLK_7_ENABLE false -# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_7_PRESCALER 1 -# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false - -/* Configure GCLK generator 8 */ -# define CONF_CLOCK_GCLK_8_ENABLE false -# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false -# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M -# define CONF_CLOCK_GCLK_8_PRESCALER 1 -# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false - -#endif /* CONF_CLOCKS_H_INCLUDED */ diff --git a/atmel-samd/asf_conf/conf_dma.h b/atmel-samd/asf_conf/conf_dma.h deleted file mode 100644 index afe790a644936..0000000000000 --- a/atmel-samd/asf_conf/conf_dma.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Direct Memory Access Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_DMA_H_INCLUDED -#define CONF_DMA_H_INCLUDED - -# define CONF_MAX_USED_CHANNEL_NUM 3 - -#endif diff --git a/atmel-samd/asf_conf/conf_extint.h b/atmel-samd/asf_conf/conf_extint.h deleted file mode 100644 index abcbdb84dd07d..0000000000000 --- a/atmel-samd/asf_conf/conf_extint.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief SAM D21 External Interrupt Driver Configuration Header - * - * Copyright (C) 2013-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_EXTINT_H_INCLUDED -#define CONF_EXTINT_H_INCLUDED - -# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0 - -#endif diff --git a/atmel-samd/asf_conf/conf_sleepmgr.h b/atmel-samd/asf_conf/conf_sleepmgr.h deleted file mode 100644 index 281a360784868..0000000000000 --- a/atmel-samd/asf_conf/conf_sleepmgr.h +++ /dev/null @@ -1,52 +0,0 @@ -/** - * \file - * - * \brief Sleep manager configuration - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_SLEEPMGR_H_INCLUDED -#define CONF_SLEEPMGR_H_INCLUDED - -#define CONFIG_SLEEPMGR_ENABLE - -#endif /* CONF_SLEEPMGR_H_INCLUDED */ diff --git a/atmel-samd/asf_conf/conf_spi.h b/atmel-samd/asf_conf/conf_spi.h deleted file mode 100644 index d093a58c5f097..0000000000000 --- a/atmel-samd/asf_conf/conf_spi.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief SAM D21 SPI configuration - * - * Copyright (C) 2013-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - - -#ifndef CONF_SPI_H_INCLUDED -#define CONF_SPI_H_INCLUDED - -#define CONF_SPI_MASTER_ENABLE true -#define CONF_SPI_SLAVE_ENABLE false - -#endif /* CONF_SPI_H_INCLUDED */ diff --git a/atmel-samd/asf_conf/user_board.h b/atmel-samd/asf_conf/user_board.h deleted file mode 100644 index 39980a7d2e46b..0000000000000 --- a/atmel-samd/asf_conf/user_board.h +++ /dev/null @@ -1,40 +0,0 @@ -/** - * \file - * - * \brief User board definition template - * - */ - - /* This file is intended to contain definitions and configuration details for - * features and devices that are available on the board, e.g., frequency and - * startup time for an external crystal, external memory devices, LED and USART - * pins. - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef USER_BOARD_H -#define USER_BOARD_H - -#include - -// External oscillator settings. -// Uncomment and set correct values if external oscillator is used. - -// External oscillator frequency -//#define BOARD_XOSC_HZ 8000000 - -// External oscillator type. -//!< External clock signal -//#define BOARD_XOSC_TYPE XOSC_TYPE_EXTERNAL -//!< 32.768 kHz resonator on TOSC -//#define BOARD_XOSC_TYPE XOSC_TYPE_32KHZ -//!< 0.4 to 16 MHz resonator on XTALS -//#define BOARD_XOSC_TYPE XOSC_TYPE_XTAL - -// External oscillator startup time -//#define BOARD_XOSC_STARTUP_US 500000 - - -#endif // USER_BOARD_H diff --git a/atmel-samd/background.c b/atmel-samd/background.c index c205b6787cd60..cda39592fa57e 100644 --- a/atmel-samd/background.c +++ b/atmel-samd/background.c @@ -25,10 +25,9 @@ */ #include "background.h" -#include "asf/common/services/usb/class/msc/device/udi_msc.h" -#include "common-hal/audioio/AudioOut.h" +// #include "common-hal/audioio/AudioOut.h" void run_background_tasks(void) { - audioout_background(); - udi_msc_process_trans(); + // audioout_background(); + // udi_msc_process_trans(); } diff --git a/atmel-samd/bindings/samd/__init__.c b/atmel-samd/bindings/samd/__init__.c index 1634d8daaedbb..d2bc0e0c0045c 100644 --- a/atmel-samd/bindings/samd/__init__.c +++ b/atmel-samd/bindings/samd/__init__.c @@ -25,8 +25,8 @@ */ #include "py/obj.h" #include "py/runtime.h" - #include "autoreload.h" - #include "rgb_led_status.h" + #include "supervisor/shared/autoreload.h" + #include "supervisor/shared/rgb_led_status.h" //| :mod:`samd` --- SAMD implementation settings //| ================================================= diff --git a/atmel-samd/boards/arduino_zero/board.c b/atmel-samd/boards/arduino_zero/board.c index b5d7b328b7124..2dc1683eafd01 100644 --- a/atmel-samd/boards/arduino_zero/board.c +++ b/atmel-samd/boards/arduino_zero/board.c @@ -25,20 +25,18 @@ */ #include "boards/board.h" -#include "asf/sam0/drivers/port/port.h" #include "mpconfigboard.h" +#include "hal/include/hal_gpio.h" void board_init(void) { - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); + gpio_set_pin_function(MICROPY_HW_LED_TX, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(MICROPY_HW_LED_TX, GPIO_DIRECTION_OUT); + gpio_set_pin_level(MICROPY_HW_LED_TX, true); - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - port_pin_set_config(MICROPY_HW_LED_TX, &pin_conf); - port_pin_set_output_level(MICROPY_HW_LED_TX, true); - - port_pin_set_config(MICROPY_HW_LED_RX, &pin_conf); - port_pin_set_output_level(MICROPY_HW_LED_RX, true); + gpio_set_pin_function(MICROPY_HW_LED_RX, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(MICROPY_HW_LED_RX, GPIO_DIRECTION_OUT); + gpio_set_pin_level(MICROPY_HW_LED_RX, true); } bool board_requests_safe_mode(void) { diff --git a/atmel-samd/boards/arduino_zero/conf_access.h b/atmel-samd/boards/arduino_zero/conf_access.h deleted file mode 100644 index 25109b75cab63..0000000000000 --- a/atmel-samd/boards/arduino_zero/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"MicroPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/arduino_zero/conf_board.h b/atmel-samd/boards/arduino_zero/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/arduino_zero/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/arduino_zero/conf_clocks.h b/atmel-samd/boards/arduino_zero/conf_clocks.h deleted file mode 100644 index d3f3e6496d7fd..0000000000000 --- a/atmel-samd/boards/arduino_zero/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_external_32k.h" diff --git a/atmel-samd/boards/arduino_zero/conf_usb.h b/atmel-samd/boards/arduino_zero/conf_usb.h deleted file mode 100644 index 98c9abe8922c5..0000000000000 --- a/atmel-samd/boards/arduino_zero/conf_usb.h +++ /dev/null @@ -1,220 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Arduino LLC" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "Arduino Zero" -#endif -// #define USB_DEVICE_SERIAL_NAME "12...EF" -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/arduino_zero/mpconfigboard.h b/atmel-samd/boards/arduino_zero/mpconfigboard.h index 1499638402ad0..e17d599f495b7 100644 --- a/atmel-samd/boards/arduino_zero/mpconfigboard.h +++ b/atmel-samd/boards/arduino_zero/mpconfigboard.h @@ -9,6 +9,7 @@ #define MICROPY_PORT_A (PORT_PA24 | PORT_PA25 | PORT_PA27) #define MICROPY_PORT_B (PORT_PB03) +#define MICROPY_PORT_C (0) #include "internal_flash.h" diff --git a/atmel-samd/boards/arduino_zero/mpconfigboard.mk b/atmel-samd/boards/arduino_zero/mpconfigboard.mk index 9ea93525df4d1..d6621cada97d9 100644 --- a/atmel-samd/boards/arduino_zero/mpconfigboard.mk +++ b/atmel-samd/boards/arduino_zero/mpconfigboard.mk @@ -5,3 +5,4 @@ USB_PID = 0x824D FLASH_IMPL = internal_flash.c CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 diff --git a/atmel-samd/boards/circuitplayground_express/board.c b/atmel-samd/boards/circuitplayground_express/board.c index 58cc55a16cf2b..4467180c768bb 100644 --- a/atmel-samd/boards/circuitplayground_express/board.c +++ b/atmel-samd/boards/circuitplayground_express/board.c @@ -27,8 +27,8 @@ #include #include "boards/board.h" -#include "asf/sam0/drivers/port/port.h" #include "common-hal/microcontroller/Pin.h" +#include "hal/include/hal_gpio.h" #include "shared-bindings/digitalio/DigitalInOut.h" #include "shared-bindings/neopixel_write/__init__.h" #include "samd21_pins.h" @@ -40,14 +40,15 @@ void board_init(void) // Check the status of the two buttons on CircuitPlayground Express. If both are // pressed, then boot into user safe mode. bool board_requests_safe_mode(void) { - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - pin_conf.direction = PORT_PIN_DIR_INPUT; - pin_conf.input_pull = PORT_PIN_PULL_DOWN; - port_pin_set_config(PIN_PA14, &pin_conf); - port_pin_set_config(PIN_PA28, &pin_conf); - bool safe_mode = port_pin_get_input_level(PIN_PA14) && - port_pin_get_input_level(PIN_PA28); + gpio_set_pin_function(PIN_PA14, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(PIN_PA14, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(PIN_PA14, GPIO_PULL_DOWN); + + gpio_set_pin_function(PIN_PA28, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(PIN_PA28, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(PIN_PA28, GPIO_PULL_DOWN); + bool safe_mode = gpio_get_pin_level(PIN_PA14) && + gpio_get_pin_level(PIN_PA28); reset_pin(PIN_PA14); reset_pin(PIN_PA28); return safe_mode; @@ -60,6 +61,6 @@ void reset_board(void) { common_hal_digitalio_digitalinout_construct(&neopixel_pin, &pin_PB23); common_hal_digitalio_digitalinout_switch_to_output(&neopixel_pin, false, DRIVE_MODE_PUSH_PULL); - common_hal_neopixel_write(&neopixel_pin, empty, 30); + // common_hal_neopixel_write(&neopixel_pin, empty, 30); common_hal_digitalio_digitalinout_deinit(&neopixel_pin); } diff --git a/atmel-samd/boards/circuitplayground_express/conf_access.h b/atmel-samd/boards/circuitplayground_express/conf_access.h deleted file mode 100644 index 25109b75cab63..0000000000000 --- a/atmel-samd/boards/circuitplayground_express/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"MicroPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/circuitplayground_express/conf_board.h b/atmel-samd/boards/circuitplayground_express/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/circuitplayground_express/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/circuitplayground_express/conf_clocks.h b/atmel-samd/boards/circuitplayground_express/conf_clocks.h deleted file mode 100644 index 9e4f7876be43c..0000000000000 --- a/atmel-samd/boards/circuitplayground_express/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_crystalless.h" diff --git a/atmel-samd/boards/circuitplayground_express/conf_dma.h b/atmel-samd/boards/circuitplayground_express/conf_dma.h deleted file mode 100644 index ffb71f634fb8a..0000000000000 --- a/atmel-samd/boards/circuitplayground_express/conf_dma.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief SAM D21 Direct Memory Access Driver Configuration Header - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef CONF_DMA_H_INCLUDED -#define CONF_DMA_H_INCLUDED - -# define CONF_MAX_USED_CHANNEL_NUM 1 - -#endif diff --git a/atmel-samd/boards/circuitplayground_express/conf_usb.h b/atmel-samd/boards/circuitplayground_express/conf_usb.h deleted file mode 100644 index 971bee331f20a..0000000000000 --- a/atmel-samd/boards/circuitplayground_express/conf_usb.h +++ /dev/null @@ -1,220 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "CircuitPlayground Express" -#endif -// #define USB_DEVICE_SERIAL_NAME "12...EF" -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/circuitplayground_express/mpconfigboard.h b/atmel-samd/boards/circuitplayground_express/mpconfigboard.h index f9ff05084a266..a12ac51a0a454 100644 --- a/atmel-samd/boards/circuitplayground_express/mpconfigboard.h +++ b/atmel-samd/boards/circuitplayground_express/mpconfigboard.h @@ -20,6 +20,7 @@ // PA24 and PA25 are USB. #define MICROPY_PORT_A (PORT_PA16 | PORT_PA20 | PORT_PA21 | PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B (PORT_PB22) +#define MICROPY_PORT_C (0) #define SPEAKER_ENABLE_PIN (&pin_PA30) @@ -27,7 +28,8 @@ // If you change this, then make sure to update the linker scripts as well to // make sure you don't overwrite code. -#define CIRCUITPY_INTERNAL_NVM_SIZE 256 +// #define CIRCUITPY_INTERNAL_NVM_SIZE 256 +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 #define BOARD_FLASH_SIZE (0x00040000 - 0x2000 - CIRCUITPY_INTERNAL_NVM_SIZE) @@ -37,4 +39,4 @@ #define CALIBRATE_CRYSTALLESS 1 // Explanation of how a user got into safe mode. -#define BOARD_USER_SAFE_MODE "pressing both buttons at start up" +#define BOARD_USER_SAFE_MODE_ACTION "pressing both buttons at start up" diff --git a/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk b/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk index d773f2f600370..0a93ccddcd919 100644 --- a/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk +++ b/atmel-samd/boards/circuitplayground_express/mpconfigboard.mk @@ -5,6 +5,7 @@ USB_PID = 0x8019 FLASH_IMPL = spi_flash.c CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 # Include these Python libraries in firmware. FROZEN_MPY_DIRS += $(TOP)/frozen/Adafruit_CircuitPython_NeoPixel diff --git a/atmel-samd/boards/feather_m0_adalogger/conf_access.h b/atmel-samd/boards/feather_m0_adalogger/conf_access.h deleted file mode 100644 index 25109b75cab63..0000000000000 --- a/atmel-samd/boards/feather_m0_adalogger/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"MicroPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/feather_m0_adalogger/conf_board.h b/atmel-samd/boards/feather_m0_adalogger/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/feather_m0_adalogger/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/feather_m0_adalogger/conf_clocks.h b/atmel-samd/boards/feather_m0_adalogger/conf_clocks.h deleted file mode 100644 index d3f3e6496d7fd..0000000000000 --- a/atmel-samd/boards/feather_m0_adalogger/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_external_32k.h" diff --git a/atmel-samd/boards/feather_m0_adalogger/conf_usb.h b/atmel-samd/boards/feather_m0_adalogger/conf_usb.h deleted file mode 100644 index 8ec6f99dc5464..0000000000000 --- a/atmel-samd/boards/feather_m0_adalogger/conf_usb.h +++ /dev/null @@ -1,220 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "Feather M0 Adalogger" -#endif - -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h b/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h index 2a2d21dd3d4a7..d81f980c914d5 100644 --- a/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h +++ b/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.h @@ -8,6 +8,7 @@ #define MICROPY_PORT_A (PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #include "internal_flash.h" diff --git a/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk b/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk index 755157cb7e0ea..900b9f52e6864 100644 --- a/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk +++ b/atmel-samd/boards/feather_m0_adalogger/mpconfigboard.mk @@ -5,3 +5,4 @@ USB_PID = 0x8015 FLASH_IMPL = internal_flash.c CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 diff --git a/atmel-samd/boards/feather_m0_basic/conf_access.h b/atmel-samd/boards/feather_m0_basic/conf_access.h deleted file mode 100644 index 25109b75cab63..0000000000000 --- a/atmel-samd/boards/feather_m0_basic/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"MicroPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/feather_m0_basic/conf_board.h b/atmel-samd/boards/feather_m0_basic/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/feather_m0_basic/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/feather_m0_basic/conf_clocks.h b/atmel-samd/boards/feather_m0_basic/conf_clocks.h deleted file mode 100644 index d3f3e6496d7fd..0000000000000 --- a/atmel-samd/boards/feather_m0_basic/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_external_32k.h" diff --git a/atmel-samd/boards/feather_m0_basic/conf_usb.h b/atmel-samd/boards/feather_m0_basic/conf_usb.h deleted file mode 100644 index 940fc26bd4d5c..0000000000000 --- a/atmel-samd/boards/feather_m0_basic/conf_usb.h +++ /dev/null @@ -1,221 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "Feather M0 Basic" -#endif - -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Two interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 - -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/feather_m0_basic/mpconfigboard.h b/atmel-samd/boards/feather_m0_basic/mpconfigboard.h index a8a8247fa4f3c..829692ed3dfbb 100644 --- a/atmel-samd/boards/feather_m0_basic/mpconfigboard.h +++ b/atmel-samd/boards/feather_m0_basic/mpconfigboard.h @@ -8,6 +8,7 @@ #define MICROPY_PORT_A (PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #include "internal_flash.h" diff --git a/atmel-samd/boards/feather_m0_basic/mpconfigboard.mk b/atmel-samd/boards/feather_m0_basic/mpconfigboard.mk index 755157cb7e0ea..900b9f52e6864 100644 --- a/atmel-samd/boards/feather_m0_basic/mpconfigboard.mk +++ b/atmel-samd/boards/feather_m0_basic/mpconfigboard.mk @@ -5,3 +5,4 @@ USB_PID = 0x8015 FLASH_IMPL = internal_flash.c CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 diff --git a/atmel-samd/boards/feather_m0_express/conf_access.h b/atmel-samd/boards/feather_m0_express/conf_access.h deleted file mode 100644 index 2326bfcdf2e99..0000000000000 --- a/atmel-samd/boards/feather_m0_express/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"CircuitPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/feather_m0_express/conf_board.h b/atmel-samd/boards/feather_m0_express/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/feather_m0_express/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/feather_m0_express/conf_clocks.h b/atmel-samd/boards/feather_m0_express/conf_clocks.h deleted file mode 100644 index d3f3e6496d7fd..0000000000000 --- a/atmel-samd/boards/feather_m0_express/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_external_32k.h" diff --git a/atmel-samd/boards/feather_m0_express/conf_usb.h b/atmel-samd/boards/feather_m0_express/conf_usb.h deleted file mode 100644 index 54313030cb364..0000000000000 --- a/atmel-samd/boards/feather_m0_express/conf_usb.h +++ /dev/null @@ -1,220 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "Feather M0 Express" -#endif - -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/feather_m0_express/mpconfigboard.h b/atmel-samd/boards/feather_m0_express/mpconfigboard.h index 896a04dd832eb..9f9c25a7d3482 100644 --- a/atmel-samd/boards/feather_m0_express/mpconfigboard.h +++ b/atmel-samd/boards/feather_m0_express/mpconfigboard.h @@ -1,9 +1,7 @@ -#define USB_REPL - #define MICROPY_HW_BOARD_NAME "Adafruit Feather M0 Express" #define MICROPY_HW_MCU_NAME "samd21g18" -#define MICROPY_HW_NEOPIXEL (&pin_PA06) +// #define MICROPY_HW_NEOPIXEL (&pin_PA06) // Salae reads 12mhz which is the limit even though we set it to the safer 8mhz. #define SPI_FLASH_BAUDRATE (8000000) @@ -20,12 +18,14 @@ #define MICROPY_PORT_A (PORT_PA06 | PORT_PA08 | PORT_PA09 | PORT_PA14 | PORT_PA13 | PORT_PA14 | PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B ( 0 ) +#define MICROPY_PORT_C ( 0 ) #include "spi_flash.h" // If you change this, then make sure to update the linker scripts as well to // make sure you don't overwrite code. -#define CIRCUITPY_INTERNAL_NVM_SIZE 256 +// #define CIRCUITPY_INTERNAL_NVM_SIZE 256 +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 #define BOARD_FLASH_SIZE (0x00040000 - 0x2000 - CIRCUITPY_INTERNAL_NVM_SIZE) diff --git a/atmel-samd/boards/feather_m0_express/mpconfigboard.mk b/atmel-samd/boards/feather_m0_express/mpconfigboard.mk index bf8bd54f2d0d0..5840a5cf901af 100644 --- a/atmel-samd/boards/feather_m0_express/mpconfigboard.mk +++ b/atmel-samd/boards/feather_m0_express/mpconfigboard.mk @@ -5,3 +5,4 @@ USB_PID = 0x801b FLASH_IMPL = spi_flash.c CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 diff --git a/atmel-samd/boards/gemma_m0/conf_access.h b/atmel-samd/boards/gemma_m0/conf_access.h deleted file mode 100644 index 25109b75cab63..0000000000000 --- a/atmel-samd/boards/gemma_m0/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"MicroPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/gemma_m0/conf_board.h b/atmel-samd/boards/gemma_m0/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/gemma_m0/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/gemma_m0/conf_clocks.h b/atmel-samd/boards/gemma_m0/conf_clocks.h deleted file mode 100644 index 9e4f7876be43c..0000000000000 --- a/atmel-samd/boards/gemma_m0/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_crystalless.h" diff --git a/atmel-samd/boards/gemma_m0/conf_usb.h b/atmel-samd/boards/gemma_m0/conf_usb.h deleted file mode 100644 index dd5316b8fe550..0000000000000 --- a/atmel-samd/boards/gemma_m0/conf_usb.h +++ /dev/null @@ -1,220 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "Gemma M0" -#endif - -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/gemma_m0/mpconfigboard.h b/atmel-samd/boards/gemma_m0/mpconfigboard.h index 8988c9a630790..baa0b33954842 100644 --- a/atmel-samd/boards/gemma_m0/mpconfigboard.h +++ b/atmel-samd/boards/gemma_m0/mpconfigboard.h @@ -3,13 +3,14 @@ #define MICROPY_HW_BOARD_NAME "Adafruit Gemma M0" #define MICROPY_HW_MCU_NAME "samd21e18" -#define MICROPY_HW_APA102_MOSI (&pin_PA00) -#define MICROPY_HW_APA102_SCK (&pin_PA01) +// #define MICROPY_HW_APA102_MOSI (&pin_PA00) +// #define MICROPY_HW_APA102_SCK (&pin_PA01) // #define CIRCUITPY_BITBANG_APA102 #define MICROPY_PORT_A (PORT_PA00 | PORT_PA01 | PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #define CIRCUITPY_INTERNAL_NVM_SIZE 0 diff --git a/atmel-samd/boards/gemma_m0/mpconfigboard.mk b/atmel-samd/boards/gemma_m0/mpconfigboard.mk index 87a5e93c10752..0666da9a25837 100644 --- a/atmel-samd/boards/gemma_m0/mpconfigboard.mk +++ b/atmel-samd/boards/gemma_m0/mpconfigboard.mk @@ -5,3 +5,4 @@ USB_PID = 0x801D FLASH_IMPL = internal_flash.c CHIP_VARIANT = SAMD21E18A +CHIP_FAMILY = samd21 diff --git a/atmel-samd/boards/metro_m0_express/board.c b/atmel-samd/boards/metro_m0_express/board.c index b5d7b328b7124..bd63baa6fd558 100644 --- a/atmel-samd/boards/metro_m0_express/board.c +++ b/atmel-samd/boards/metro_m0_express/board.c @@ -25,20 +25,19 @@ */ #include "boards/board.h" -#include "asf/sam0/drivers/port/port.h" #include "mpconfigboard.h" void board_init(void) { - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - port_pin_set_config(MICROPY_HW_LED_TX, &pin_conf); - port_pin_set_output_level(MICROPY_HW_LED_TX, true); - - port_pin_set_config(MICROPY_HW_LED_RX, &pin_conf); - port_pin_set_output_level(MICROPY_HW_LED_RX, true); + // struct port_config pin_conf; + // port_get_config_defaults(&pin_conf); + // + // pin_conf.direction = PORT_PIN_DIR_OUTPUT; + // port_pin_set_config(MICROPY_HW_LED_TX, &pin_conf); + // port_pin_set_output_level(MICROPY_HW_LED_TX, true); + // + // port_pin_set_config(MICROPY_HW_LED_RX, &pin_conf); + // port_pin_set_output_level(MICROPY_HW_LED_RX, true); } bool board_requests_safe_mode(void) { diff --git a/atmel-samd/boards/metro_m0_express/conf_access.h b/atmel-samd/boards/metro_m0_express/conf_access.h deleted file mode 100644 index 25109b75cab63..0000000000000 --- a/atmel-samd/boards/metro_m0_express/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"MicroPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/metro_m0_express/conf_board.h b/atmel-samd/boards/metro_m0_express/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/metro_m0_express/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/metro_m0_express/conf_clocks.h b/atmel-samd/boards/metro_m0_express/conf_clocks.h deleted file mode 100644 index d3f3e6496d7fd..0000000000000 --- a/atmel-samd/boards/metro_m0_express/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_external_32k.h" diff --git a/atmel-samd/boards/metro_m0_express/conf_usb.h b/atmel-samd/boards/metro_m0_express/conf_usb.h deleted file mode 100644 index 0a623fa06fcdb..0000000000000 --- a/atmel-samd/boards/metro_m0_express/conf_usb.h +++ /dev/null @@ -1,221 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "Metro M0 Express" -#endif -// #define USB_DEVICE_SERIAL_NAME "12...EF" -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 - -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/metro_m0_express/mpconfigboard.h b/atmel-samd/boards/metro_m0_express/mpconfigboard.h index cbc28dc7815bc..291967c885231 100644 --- a/atmel-samd/boards/metro_m0_express/mpconfigboard.h +++ b/atmel-samd/boards/metro_m0_express/mpconfigboard.h @@ -4,9 +4,9 @@ #define MICROPY_HW_MCU_NAME "samd21g18" #define MICROPY_HW_LED_TX PIN_PA27 -#define MICROPY_HW_LED_RX PIN_PA31 +//#define MICROPY_HW_LED_RX PIN_PA31 -#define MICROPY_HW_NEOPIXEL (&pin_PA30) +//#define MICROPY_HW_NEOPIXEL (&pin_PA30) // Salae reads 12mhz which is the limit even though we set it to the safer 8mhz. #define SPI_FLASH_BAUDRATE (8000000) @@ -22,12 +22,14 @@ #define MICROPY_PORT_A (PORT_PA13 |PORT_PA24 | PORT_PA25 | PORT_PA27 | PORT_PA30 | PORT_PA31) #define MICROPY_PORT_B (PORT_PB03 | PORT_PB22 | PORT_PB23) +#define MICROPY_PORT_C (0) #include "spi_flash.h" // If you change this, then make sure to update the linker scripts as well to // make sure you don't overwrite code. -#define CIRCUITPY_INTERNAL_NVM_SIZE 256 +// #define CIRCUITPY_INTERNAL_NVM_SIZE 256 +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 #define BOARD_FLASH_SIZE (0x00040000 - 0x2000 - CIRCUITPY_INTERNAL_NVM_SIZE) diff --git a/atmel-samd/boards/metro_m0_express/mpconfigboard.mk b/atmel-samd/boards/metro_m0_express/mpconfigboard.mk index 436e56a60096e..7637387482a89 100644 --- a/atmel-samd/boards/metro_m0_express/mpconfigboard.mk +++ b/atmel-samd/boards/metro_m0_express/mpconfigboard.mk @@ -5,3 +5,4 @@ USB_PID = 0x8014 FLASH_IMPL = spi_flash.c CHIP_VARIANT = SAMD21G18A +CHIP_FAMILY = samd21 diff --git a/atmel-samd/boards/metro_m4_express/board.c b/atmel-samd/boards/metro_m4_express/board.c new file mode 100644 index 0000000000000..8096b9b8ea6d8 --- /dev/null +++ b/atmel-samd/boards/metro_m4_express/board.c @@ -0,0 +1,38 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "mpconfigboard.h" + +void board_init(void) { +} + +bool board_requests_safe_mode(void) { + return false; +} + +void reset_board(void) { +} diff --git a/atmel-samd/boards/metro_m4_express/mpconfigboard.h b/atmel-samd/boards/metro_m4_express/mpconfigboard.h new file mode 100644 index 0000000000000..4ce6fe9e433be --- /dev/null +++ b/atmel-samd/boards/metro_m4_express/mpconfigboard.h @@ -0,0 +1,38 @@ +#define MICROPY_HW_BOARD_NAME "Metro M4 Express" +#define MICROPY_HW_MCU_NAME "samd51j20" + +#define CIRCUITPY_MCU_FAMILY samd51 + +#define MICROPY_HW_LED_TX PIN_PA27 +#define MICROPY_HW_LED_RX PIN_PB06 + +// #define MICROPY_HW_NEOPIXEL (&pin_PB17) + +#define SPI_FLASH_BAUDRATE (1000000) + +// Rev F +#define SPI_FLASH_MUX_SETTING SPI_SIGNAL_MUX_SETTING_F +#define SPI_FLASH_PAD0_PINMUX PINMUX_PB08 // MOSI +// Use default pinmux for the chip select since we manage it ourselves. +#define SPI_FLASH_PAD1_PINMUX PINMUX_PB09 // SCK +#define SPI_FLASH_PAD2_PINMUX PINMUX_DEFAULT // CS +#define SPI_FLASH_PAD3_PINMUX PINMUX_PB11 // MISO +#define SPI_FLASH_CS PIN_PB10 +#define SPI_FLASH_SERCOM SERCOM5 + +#define MICROPY_PORT_A (PORT_PA27) +#define MICROPY_PORT_B (PORT_PB06 | PORT_PB08 | PORT_PB09 | PORT_PB11 | PORT_PB17) +#define MICROPY_PORT_C (0) +#define MICROPY_PORT_D (0) + +#define CONF_USB_COMPOSITE_CDC_ACM_EN 1 + +#define AUTORESET_DELAY_MS 500 + +#include "internal_flash.h" + +// If you change this, then make sure to update the linker scripts as well to +// make sure you don't overwrite code. +#define CIRCUITPY_INTERNAL_NVM_SIZE 0 + +#define BOARD_FLASH_SIZE (FLASH_SIZE - 0x4000) diff --git a/atmel-samd/boards/metro_m4_express/mpconfigboard.mk b/atmel-samd/boards/metro_m4_express/mpconfigboard.mk new file mode 100644 index 0000000000000..24557e3e090e9 --- /dev/null +++ b/atmel-samd/boards/metro_m4_express/mpconfigboard.mk @@ -0,0 +1,8 @@ +LD_FILE = boards/samd51x20-external-flash.ld +USB_VID = 0x239A +USB_PID = 0x8015 + +FLASH_IMPL = spi_flash.c + +CHIP_VARIANT = SAMD51J20A +CHIP_FAMILY = samd51 diff --git a/atmel-samd/boards/metro_m4_express/pins.c b/atmel-samd/boards/metro_m4_express/pins.c new file mode 100644 index 0000000000000..ea6bab9c1769f --- /dev/null +++ b/atmel-samd/boards/metro_m4_express/pins.c @@ -0,0 +1,42 @@ +#include "samd51_pins.h" + +// This mapping only includes functional names because pins broken +// out on connectors are labeled with their MCU name available from +// microcontroller.pin. +STATIC const mp_map_elem_t board_global_dict_table[] = { + { MP_OBJ_NEW_QSTR(MP_QSTR_A0), (mp_obj_t)&pin_PA02 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A1), (mp_obj_t)&pin_PA05 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A2), (mp_obj_t)&pin_PA06 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A3), (mp_obj_t)&pin_PA07 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A4), (mp_obj_t)&pin_PA11 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_A5), (mp_obj_t)&pin_PA04 }, + + + { MP_OBJ_NEW_QSTR(MP_QSTR_D0), (mp_obj_t)&pin_PA23 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D1), (mp_obj_t)&pin_PA22 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D2), (mp_obj_t)&pin_PA08 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D3), (mp_obj_t)&pin_PA10 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D4), (mp_obj_t)&pin_PB12 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D5), (mp_obj_t)&pin_PB14 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D6), (mp_obj_t)&pin_PB15 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D7), (mp_obj_t)&pin_PA14 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D8), (mp_obj_t)&pin_PA16 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D9), (mp_obj_t)&pin_PA17 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D10), (mp_obj_t)&pin_PA18 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D11), (mp_obj_t)&pin_PA19 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D12), (mp_obj_t)&pin_PA20 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_D13), (mp_obj_t)&pin_PA21 }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_SDA), (mp_obj_t)&pin_PB02 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_SCL), (mp_obj_t)&pin_PB03 }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_NEOPIXEL), (mp_obj_t)&pin_PB17 }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_SCK), (mp_obj_t)&pin_PA12 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_MOSI), (mp_obj_t)&pin_PA13 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_MISO), (mp_obj_t)&pin_PA15 }, + + { MP_OBJ_NEW_QSTR(MP_QSTR_LED_RX), (mp_obj_t)&pin_PB06 }, + { MP_OBJ_NEW_QSTR(MP_QSTR_LED_TX), (mp_obj_t)&pin_PA27 }, +}; +MP_DEFINE_CONST_DICT(board_module_globals, board_global_dict_table); diff --git a/atmel-samd/boards/samd51x18-bootloader-external-flash.ld b/atmel-samd/boards/samd51x18-bootloader-external-flash.ld new file mode 100644 index 0000000000000..b009de640a5bd --- /dev/null +++ b/atmel-samd/boards/samd51x18-bootloader-external-flash.ld @@ -0,0 +1,81 @@ +/* + GNU linker script for SAMD21 +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000 + 0x4000, LENGTH = 0x00040000 - 0x4000 /* Leave 16KiB for the bootloader. */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128 KiB */ +} + +/* top end of the stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* define output sections */ +SECTIONS +{ + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors)) /* isr vector table */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH + + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + _sidata = .; /* This is used by the startup in order to initialize the .data section */ + } > FLASH + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _srelocate = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.ramfunc) + *(.ramfunc*) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _erelocate = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; + _szero = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ezero = .; /* define a global symbol at bss end; used by startup code */ + _ebss = .; + } >RAM + + /* this just checks there is enough RAM for a minimal stack */ + .stack : + { + . = ALIGN(4); + . = . + 0x800; /* Reserve a minimum of 2K for the stack. */ + . = ALIGN(4); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/atmel-samd/boards/samd51x19-bootloader-external-flash.ld b/atmel-samd/boards/samd51x19-bootloader-external-flash.ld new file mode 100644 index 0000000000000..bea575797f396 --- /dev/null +++ b/atmel-samd/boards/samd51x19-bootloader-external-flash.ld @@ -0,0 +1,81 @@ +/* + GNU linker script for SAMD21 +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000 + 0x4000, LENGTH = 0x00080000 - 0x4000 /* Leave 16KiB for the bootloader. */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00030000 /* 192 KiB */ +} + +/* top end of the stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* define output sections */ +SECTIONS +{ + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors)) /* isr vector table */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH + + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + _sidata = .; /* This is used by the startup in order to initialize the .data section */ + } > FLASH + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _srelocate = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.ramfunc) + *(.ramfunc*) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _erelocate = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; + _szero = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ezero = .; /* define a global symbol at bss end; used by startup code */ + _ebss = .; + } >RAM + + /* this just checks there is enough RAM for a minimal stack */ + .stack : + { + . = ALIGN(4); + . = . + 0x800; /* Reserve a minimum of 2K for the stack. */ + . = ALIGN(4); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/atmel-samd/boards/samd51x20-bootloader-external-flash.ld b/atmel-samd/boards/samd51x20-bootloader-external-flash.ld new file mode 100644 index 0000000000000..e9c67de97b3bf --- /dev/null +++ b/atmel-samd/boards/samd51x20-bootloader-external-flash.ld @@ -0,0 +1,81 @@ +/* + GNU linker script for SAMD21 +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000 + 0x4000, LENGTH = 0x00100000 - 0x4000 /* Leave 16KiB for the bootloader. */ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00040000 /* 256 KiB */ +} + +/* top end of the stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* define output sections */ +SECTIONS +{ + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors)) /* isr vector table */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH + + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + _sidata = .; /* This is used by the startup in order to initialize the .data section */ + } > FLASH + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _srelocate = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.ramfunc) + *(.ramfunc*) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _erelocate = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; + _szero = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ezero = .; /* define a global symbol at bss end; used by startup code */ + _ebss = .; + } >RAM + + /* this just checks there is enough RAM for a minimal stack */ + .stack : + { + . = ALIGN(4); + . = . + 0x800; /* Reserve a minimum of 2K for the stack. */ + . = ALIGN(4); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/atmel-samd/boards/samd51x20-external-flash.ld b/atmel-samd/boards/samd51x20-external-flash.ld new file mode 100644 index 0000000000000..701e24762a67a --- /dev/null +++ b/atmel-samd/boards/samd51x20-external-flash.ld @@ -0,0 +1,81 @@ +/* + GNU linker script for SAMD21 +*/ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0x00040000 /* 256 KiB */ +} + +/* top end of the stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* define output sections */ +SECTIONS +{ + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors)) /* isr vector table */ + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + + . = ALIGN(4); + _etext = .; /* define a global symbol at end of code */ + } >FLASH + + .ARM.exidx : + { + *(.ARM.exidx*) + *(.gnu.linkonce.armexidx.*) + _sidata = .; /* This is used by the startup in order to initialize the .data section */ + } > FLASH + + /* This is the initialized data section + The program executes knowing that the data is in the RAM + but the loader puts the initial values in the FLASH (inidata). + It is one task of the startup to copy the initial values from FLASH to RAM. */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _srelocate = .; /* create a global symbol at data start; used by startup code in order to initialise the .data section in RAM */ + *(.ramfunc) + *(.ramfunc*) + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _erelocate = .; /* define a global symbol at data end; used by startup code in order to initialise the .data section in RAM */ + } >RAM + + /* Uninitialized data section */ + .bss : + { + . = ALIGN(4); + _sbss = .; + _szero = .; /* define a global symbol at bss start; used by startup code */ + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ezero = .; /* define a global symbol at bss end; used by startup code */ + _ebss = .; + } >RAM + + /* this just checks there is enough RAM for a minimal stack */ + .stack : + { + . = ALIGN(4); + . = . + 0x800; /* Reserve a minimum of 2K for the stack. */ + . = ALIGN(4); + } >RAM + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/atmel-samd/boards/trinket_m0/conf_access.h b/atmel-samd/boards/trinket_m0/conf_access.h deleted file mode 100644 index 25109b75cab63..0000000000000 --- a/atmel-samd/boards/trinket_m0/conf_access.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * \file - * - * \brief Memory access control configuration file. - * - * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _CONF_ACCESS_H_ -#define _CONF_ACCESS_H_ - -#include "compiler.h" -#include "board.h" - - -/*! \name Activation of Logical Unit Numbers - */ -//! @{ -#define LUN_0 ENABLE //!< On-Chip Virtual Memory. -#define LUN_1 DISABLE //!< AT45DBX Data Flash. -#define LUN_2 DISABLE //!< SD/MMC Card over SPI. -#define LUN_3 DISABLE //!< SD/MMC Card over MCI Slot 0. -#define LUN_4 DISABLE -#define LUN_5 DISABLE -#define LUN_6 DISABLE -#define LUN_7 DISABLE -#define LUN_USB DISABLE //!< Host Mass-Storage Memory. -//! @} - -/*! \name LUN 0 Definitions - */ -//! @{ -#define LUN_0_INCLUDE "access_vfs.h" -#define Lun_0_test_unit_ready vfs_test_unit_ready -#define Lun_0_read_capacity vfs_read_capacity -#define Lun_0_unload NULL -#define Lun_0_wr_protect vfs_wr_protect -#define Lun_0_removal vfs_removal -#define Lun_0_usb_read_10 vfs_usb_read_10 -#define Lun_0_usb_write_10 vfs_usb_write_10 -#define LUN_0_NAME "\"MicroPython VFS[0]\"" -//! @} - -#define MEM_USB LUN_USB - -/*! \name Actions Associated with Memory Accesses - * - * Write here the action to associate with each memory access. - * - * \warning Be careful not to waste time in order not to disturb the functions. - */ -//! @{ -#define memory_start_read_action(nb_sectors) -#define memory_stop_read_action() -#define memory_start_write_action(nb_sectors) -#define memory_stop_write_action() -//! @} - -/*! \name Activation of Interface Features - */ -//! @{ -#define ACCESS_USB true //!< MEM <-> USB interface. -#define ACCESS_MEM_TO_RAM false //!< MEM <-> RAM interface. -#define ACCESS_STREAM false //!< Streaming MEM <-> MEM interface. -#define ACCESS_STREAM_RECORD false //!< Streaming MEM <-> MEM interface in record mode. -#define ACCESS_MEM_TO_MEM false //!< MEM <-> MEM interface. -#define ACCESS_CODEC false //!< Codec interface. -//! @} - -/*! \name Specific Options for Access Control - */ -//! @{ -#define GLOBAL_WR_PROTECT false //!< Management of a global write protection. -//! @} - - -#endif // _CONF_ACCESS_H_ diff --git a/atmel-samd/boards/trinket_m0/conf_board.h b/atmel-samd/boards/trinket_m0/conf_board.h deleted file mode 100644 index 7b88c97fc205b..0000000000000 --- a/atmel-samd/boards/trinket_m0/conf_board.h +++ /dev/null @@ -1,14 +0,0 @@ -/** - * \file - * - * \brief User board configuration template - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef CONF_BOARD_H -#define CONF_BOARD_H - -#endif // CONF_BOARD_H diff --git a/atmel-samd/boards/trinket_m0/conf_clocks.h b/atmel-samd/boards/trinket_m0/conf_clocks.h deleted file mode 100644 index 9e4f7876be43c..0000000000000 --- a/atmel-samd/boards/trinket_m0/conf_clocks.h +++ /dev/null @@ -1 +0,0 @@ -#include "conf_clocks_crystalless.h" diff --git a/atmel-samd/boards/trinket_m0/conf_usb.h b/atmel-samd/boards/trinket_m0/conf_usb.h deleted file mode 100644 index 2e6cee1bc4ea8..0000000000000 --- a/atmel-samd/boards/trinket_m0/conf_usb.h +++ /dev/null @@ -1,221 +0,0 @@ - -#include -#include - -#include "asf/common/services/usb/class/cdc/usb_protocol_cdc.h" - -#ifndef CONF_USB_H_INCLUDED -#define CONF_USB_H_INCLUDED - -#define USB_DEVICE_MAJOR_VERSION 1 -#define USB_DEVICE_MINOR_VERSION 0 -#define USB_DEVICE_POWER 100 // Consumption on Vbus line (mA) -#define USB_DEVICE_ATTR \ - (USB_CONFIG_ATTR_BUS_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_SELF_POWERED) -// (USB_CONFIG_ATTR_REMOTE_WAKEUP|USB_CONFIG_ATTR_BUS_POWERED) - -//! USB Device string definitions (Optional) -#ifndef USB_DEVICE_MANUFACTURE_NAME -# define USB_DEVICE_MANUFACTURE_NAME "Adafruit Industries" -#endif - -#ifndef USB_DEVICE_PRODUCT_NAME -# define USB_DEVICE_PRODUCT_NAME "Trinket M0" -#endif -// #define USB_DEVICE_SERIAL_NAME "12...EF" -#define USB_DEVICE_GET_SERIAL_NAME_POINTER serial_number -#define USB_DEVICE_GET_SERIAL_NAME_LENGTH 32 -extern char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; - -//! Control endpoint size -#define USB_DEVICE_EP_CTRL_SIZE 64 - -//! Interfaces for this device (CDC COM + CDC DATA + MSC + HID mouse + HID kbd) -#define USB_DEVICE_NB_INTERFACE 5 - -// (3 | USB_EP_DIR_IN) // CDC Notify endpoint -// (4 | USB_EP_DIR_IN) // CDC TX -// (5 | USB_EP_DIR_OUT) // CDC RX -// (1 | USB_EP_DIR_IN) // MSC IN -// (2 | USB_EP_DIR_OUT) // MSC OUT -// (6 | USB_EP_DIR_IN) // HID mouse report -// (7 | USB_EP_DIR_IN) // HID keyboard report -#define USB_DEVICE_MAX_EP 7 - -#define UDI_CDC_PORT_NB 1 -#define UDI_CDC_ENABLE_EXT(port) mp_cdc_enable(port) -extern bool mp_cdc_enable(uint8_t port); -#define UDI_CDC_DISABLE_EXT(port) mp_cdc_disable(port) -extern void mp_cdc_disable(uint8_t port); -#define UDI_CDC_LOW_RATE - -#define UDI_CDC_DEFAULT_RATE 115200 -#define UDI_CDC_DEFAULT_STOPBITS CDC_STOP_BITS_1 -#define UDI_CDC_DEFAULT_PARITY CDC_PAR_NONE -#define UDI_CDC_DEFAULT_DATABITS 8 - -#define UDI_CDC_RX_NOTIFY(port) usb_rx_notify() -void usb_rx_notify(void); - -#define UDI_CDC_SET_CODING_EXT(port,cfg) usb_coding_notify(port, cfg) -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding); -#define UDI_CDC_SET_DTR_EXT(port,set) usb_dtr_notify(port, set) -void usb_dtr_notify(uint8_t port, bool set); -#define UDI_CDC_SET_RTS_EXT(port,set) usb_rts_notify(port, set) -void usb_rts_notify(uint8_t port, bool set); - -/** - * USB CDC low level configuration - * In standalone these configurations are defined by the CDC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition - -#define UDI_CDC_COMM_EP_0 (3 | USB_EP_DIR_IN) // Notify endpoint -#define UDI_CDC_DATA_EP_IN_0 (4 | USB_EP_DIR_IN) // TX -#define UDI_CDC_DATA_EP_OUT_0 (5 | USB_EP_DIR_OUT) // RX - -//! Interface numbers -#define UDI_CDC_COMM_IFACE_NUMBER_0 0 -#define UDI_CDC_DATA_IFACE_NUMBER_0 1 - -/** - * Configuration of MSC interface - * @{ - */ -//! Vendor name and Product version of MSC interface -#define UDI_MSC_GLOBAL_VENDOR_ID \ - 'A', 'T', 'M', 'E', 'L', ' ', ' ', ' ' -#define UDI_MSC_GLOBAL_PRODUCT_VERSION \ - '1', '.', '0', '0' - -//! Interface callback definition -#define UDI_MSC_ENABLE_EXT() mp_msc_enable() -extern bool mp_msc_enable(void); -#define UDI_MSC_DISABLE_EXT() mp_msc_disable() -extern void mp_msc_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_MSC_STRING_ID 5 - -/** - * USB MSC low level configuration - * In standalone these configurations are defined by the MSC module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_MSC_EP_IN (1 | USB_EP_DIR_IN) -#define UDI_MSC_EP_OUT (2 | USB_EP_DIR_OUT) - -//! Interface number -#define UDI_MSC_IFACE_NUMBER 2 -/** - * Configuration of HID Mouse interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_MOUSE_ENABLE_EXT() mp_mouse_enable() -extern bool mp_mouse_enable(void); -#define UDI_HID_MOUSE_DISABLE_EXT() mp_mouse_disable() -extern void mp_mouse_disable(void); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_MOUSE_STRING_ID 6 - -/** - * USB HID Mouse low level configuration - * In standalone these configurations are defined by the HID Mouse module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_MOUSE_EP_IN (6 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_MOUSE_IFACE_NUMBER 3 -//@} -//@} - -/** - * Configuration of HID Keyboard interface - * @{ - */ -//! Interface callback definition -#define UDI_HID_KBD_ENABLE_EXT() mp_keyboard_enable() -extern bool mp_keyboard_enable(void); -#define UDI_HID_KBD_DISABLE_EXT() mp_keyboard_disable() -extern void mp_keyboard_disable(void); -#define UDI_HID_KBD_CHANGE_LED(value) mp_keyboard_led(value) -extern void mp_keyboard_led(uint8_t); - -//! Enable id string of interface to add an extra USB string -#define UDI_HID_KBD_STRING_ID 7 - -/** - * USB HID Keyboard low level configuration - * In standalone these configurations are defined by the HID Keyboard module. - * For composite device, these configuration must be defined here - * @{ - */ -//! Endpoint numbers definition -#define UDI_HID_KBD_EP_IN (7 | USB_EP_DIR_IN) - -//! Interface number -#define UDI_HID_KBD_IFACE_NUMBER 4 - -/** - * Description of Composite Device - * @{ - */ -//! USB Interfaces descriptor structure -#define UDI_COMPOSITE_DESC_T \ - usb_iad_desc_t udi_cdc_iad; \ - udi_cdc_comm_desc_t udi_cdc_comm; \ - udi_cdc_data_desc_t udi_cdc_data; \ - udi_msc_desc_t udi_msc; \ - udi_hid_mouse_desc_t udi_hid_mouse; \ - udi_hid_kbd_desc_t udi_hid_kbd - -//! USB Interfaces descriptor value for Full Speed -#define UDI_COMPOSITE_DESC_FS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_FS, \ - .udi_msc = UDI_MSC_DESC_FS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interfaces descriptor value for High Speed -#define UDI_COMPOSITE_DESC_HS \ - .udi_cdc_iad = UDI_CDC_IAD_DESC_0, \ - .udi_cdc_comm = UDI_CDC_COMM_DESC_0, \ - .udi_cdc_data = UDI_CDC_DATA_DESC_0_HS, \ - .udi_msc = UDI_MSC_DESC_HS, \ - .udi_hid_mouse = UDI_HID_MOUSE_DESC, \ - .udi_hid_kbd = UDI_HID_KBD_DESC - -//! USB Interface APIs -#define UDI_COMPOSITE_API \ - &udi_api_cdc_comm, \ - &udi_api_cdc_data, \ - &udi_api_msc, \ - &udi_api_hid_mouse, \ - &udi_api_hid_kbd -//@} - -/** - * USB Device Driver Configuration - * @{ - */ -//@} - -//! The includes of classes and other headers must be done at the end of this file to avoid compile error -#include "udi_cdc.h" -#include "udi_msc.h" -#include "udi_hid_mouse.h" -#include "udi_hid_kbd.h" - -#endif diff --git a/atmel-samd/boards/trinket_m0/mpconfigboard.h b/atmel-samd/boards/trinket_m0/mpconfigboard.h index 8fc70f22d5b63..6d46d041435e4 100644 --- a/atmel-samd/boards/trinket_m0/mpconfigboard.h +++ b/atmel-samd/boards/trinket_m0/mpconfigboard.h @@ -4,11 +4,12 @@ #define MICROPY_HW_MCU_NAME "samd21e18" // Rev B - Black -#define MICROPY_HW_APA102_MOSI (&pin_PA00) -#define MICROPY_HW_APA102_SCK (&pin_PA01) +// #define MICROPY_HW_APA102_MOSI (&pin_PA00) +// #define MICROPY_HW_APA102_SCK (&pin_PA01) #define MICROPY_PORT_A (PORT_PA00 | PORT_PA01 | PORT_PA24 | PORT_PA25) #define MICROPY_PORT_B (0) +#define MICROPY_PORT_C (0) #include "internal_flash.h" diff --git a/atmel-samd/boards/trinket_m0/mpconfigboard.mk b/atmel-samd/boards/trinket_m0/mpconfigboard.mk index 4d2268c13cd78..16b75baa0e869 100644 --- a/atmel-samd/boards/trinket_m0/mpconfigboard.mk +++ b/atmel-samd/boards/trinket_m0/mpconfigboard.mk @@ -5,3 +5,4 @@ USB_PID = 0x801F FLASH_IMPL = internal_flash.c CHIP_VARIANT = SAMD21E18A +CHIP_FAMILY = samd21 diff --git a/atmel-samd/common-hal/analogio/AnalogIn.h b/atmel-samd/common-hal/analogio/AnalogIn.h index 3e9ddd76e47c6..7c988d909e6f3 100644 --- a/atmel-samd/common-hal/analogio/AnalogIn.h +++ b/atmel-samd/common-hal/analogio/AnalogIn.h @@ -29,13 +29,6 @@ #include "common-hal/microcontroller/Pin.h" -// Don't reorder these includes because they are dependencies of adc_feature.h. -// They should really be included by adc_feature.h. -#include -#include "asf/sam0/drivers/system/clock/gclk.h" -#include "asf/sam0/utils/cmsis/samd21/include/component/adc.h" -#include "asf/sam0/drivers/adc/adc_sam_d_r/adc_feature.h" - #include "py/obj.h" typedef struct { diff --git a/atmel-samd/common-hal/audioio/AudioOut.h b/atmel-samd/common-hal/audioio/AudioOut.h index 738a2aa6ccf07..78e4ffc77d060 100644 --- a/atmel-samd/common-hal/audioio/AudioOut.h +++ b/atmel-samd/common-hal/audioio/AudioOut.h @@ -28,7 +28,6 @@ #define MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_AUDIOIO_AUDIOOUT_H #include "common-hal/microcontroller/Pin.h" -#include "asf/sam0/drivers/tc/tc.h" #include "extmod/vfs_fat_file.h" #include "py/obj.h" diff --git a/atmel-samd/common-hal/digitalio/DigitalInOut.c b/atmel-samd/common-hal/digitalio/DigitalInOut.c index 3f178fac02cd9..37a4f709617cd 100644 --- a/atmel-samd/common-hal/digitalio/DigitalInOut.c +++ b/atmel-samd/common-hal/digitalio/DigitalInOut.c @@ -3,7 +3,7 @@ * * The MIT License (MIT) * - * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -31,23 +31,18 @@ #include "py/runtime.h" #include "py/mphal.h" +#include "hal/include/hal_gpio.h" + #include "common-hal/microcontroller/Pin.h" #include "shared-bindings/digitalio/DigitalInOut.h" -#include "asf/sam0/drivers/port/port.h" -#include "asf/sam0/drivers/system/pinmux/pinmux.h" - digitalinout_result_t common_hal_digitalio_digitalinout_construct( digitalio_digitalinout_obj_t* self, const mcu_pin_obj_t* pin) { claim_pin(pin); self->pin = pin; - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - pin_conf.direction = PORT_PIN_DIR_INPUT; - pin_conf.input_pull = PORT_PIN_PULL_NONE; - port_pin_set_config(self->pin->pin, &pin_conf); + gpio_set_pin_pull_mode(pin->pin, GPIO_PULL_OFF); + gpio_set_pin_direction(pin->pin, GPIO_DIRECTION_IN); return DIGITALINOUT_OK; } @@ -65,12 +60,8 @@ void common_hal_digitalio_digitalinout_switch_to_input( void common_hal_digitalio_digitalinout_switch_to_output( digitalio_digitalinout_obj_t* self, bool value, enum digitalio_drive_mode_t drive_mode) { - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - pin_conf.direction = PORT_PIN_DIR_INPUT; - pin_conf.input_pull = PORT_PIN_PULL_NONE; - port_pin_set_config(self->pin->pin, &pin_conf); + gpio_set_pin_pull_mode(self->pin->pin, GPIO_PULL_OFF); + gpio_set_pin_direction(self->pin->pin, GPIO_DIRECTION_OUT); self->output = true; self->open_drain = drive_mode == DRIVE_MODE_OPEN_DRAIN; @@ -84,36 +75,29 @@ enum digitalio_direction_t common_hal_digitalio_digitalinout_get_direction( void common_hal_digitalio_digitalinout_set_value( digitalio_digitalinout_obj_t* self, bool value) { - uint32_t pin = self->pin->pin; - PortGroup *const port_base = port_get_group_from_gpio_pin(pin); - uint32_t pin_mask = (1UL << (pin % 32)); - - /* Set the pin to high or low atomically based on the requested level */ if (value) { if (self->open_drain) { - port_base->DIRCLR.reg = pin_mask; + gpio_set_pin_direction(self->pin->pin, GPIO_DIRECTION_IN); } else { - port_base->DIRSET.reg = pin_mask; - port_base->OUTSET.reg = pin_mask; + gpio_set_pin_level(self->pin->pin, true); + gpio_set_pin_direction(self->pin->pin, GPIO_DIRECTION_OUT); } } else { - port_base->DIRSET.reg = pin_mask; - port_base->OUTCLR.reg = pin_mask; + gpio_set_pin_level(self->pin->pin, false); + gpio_set_pin_direction(self->pin->pin, GPIO_DIRECTION_OUT); } } bool common_hal_digitalio_digitalinout_get_value( digitalio_digitalinout_obj_t* self) { uint32_t pin = self->pin->pin; - PortGroup *const port_base = port_get_group_from_gpio_pin(pin); - uint32_t pin_mask = (1UL << (pin % 32)); if (!self->output) { - return (port_base->IN.reg & pin_mask); + return gpio_get_pin_level(self->pin->pin); } else { - if (self->open_drain && (port_base->DIR.reg & pin_mask) == 0) { + if (self->open_drain && hri_port_get_DIR_reg(PORT, (enum gpio_port)GPIO_PORT(pin), 1U << pin) == 0) { return true; } else { - return (port_base->OUT.reg & pin_mask); + return hri_port_get_OUT_reg(PORT, (enum gpio_port)GPIO_PORT(pin), 1U << pin); } } } @@ -141,38 +125,31 @@ enum digitalio_drive_mode_t common_hal_digitalio_digitalinout_get_drive_mode( void common_hal_digitalio_digitalinout_set_pull( digitalio_digitalinout_obj_t* self, enum digitalio_pull_t pull) { - enum port_pin_pull asf_pull = PORT_PIN_PULL_NONE; + enum gpio_pull_mode asf_pull = GPIO_PULL_OFF; switch (pull) { case PULL_UP: - asf_pull = PORT_PIN_PULL_UP; + asf_pull = GPIO_PULL_UP; break; case PULL_DOWN: - asf_pull = PORT_PIN_PULL_DOWN; + asf_pull = GPIO_PULL_DOWN; break; case PULL_NONE: default: break; } - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - pin_conf.direction = PORT_PIN_DIR_INPUT; - pin_conf.input_pull = asf_pull; - port_pin_set_config(self->pin->pin, &pin_conf); + gpio_set_pin_pull_mode(self->pin->pin, asf_pull); } enum digitalio_pull_t common_hal_digitalio_digitalinout_get_pull( digitalio_digitalinout_obj_t* self) { uint32_t pin = self->pin->pin; - PortGroup *const port_base = port_get_group_from_gpio_pin(pin); - uint32_t pin_mask = (1UL << (pin % 32)); if (self->output) { mp_raise_AttributeError("Cannot get pull while in output mode"); return PULL_NONE; } else { - if (port_base->PINCFG[pin % 32].bit.PULLEN == 0) { + if (hri_port_get_PINCFG_PULLEN_bit(PORT, (enum gpio_port)GPIO_PORT(pin), pin) == 0) { return PULL_NONE; - } if ((port_base->OUT.reg & pin_mask) > 0) { + } if (hri_port_get_OUT_reg(PORT, (enum gpio_port)GPIO_PORT(pin), 1U << pin) > 0) { return PULL_UP; } else { return PULL_DOWN; diff --git a/atmel-samd/common-hal/microcontroller/Pin.c b/atmel-samd/common-hal/microcontroller/Pin.c index d814eb89ca674..a7b494940f551 100644 --- a/atmel-samd/common-hal/microcontroller/Pin.c +++ b/atmel-samd/common-hal/microcontroller/Pin.c @@ -26,10 +26,16 @@ #include "shared-bindings/microcontroller/Pin.h" -#include "asf/sam0/drivers/port/port.h" +#include "atmel_start_pins.h" +#include "hal/include/hal_gpio.h" -#include "rgb_led_status.h" +#include "supervisor/shared/rgb_led_status.h" +#ifdef SAMD21 #include "samd21_pins.h" +#endif +#ifdef SAMD51 +#include "samd51_pins.h" +#endif #ifdef MICROPY_HW_NEOPIXEL bool neopixel_in_use; @@ -43,22 +49,39 @@ bool speaker_enable_in_use; #endif void reset_all_pins(void) { - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); - config.powersave = true; - - uint32_t pin_mask[2] = PORT_OUT_IMPLEMENTED; + uint32_t pin_mask[PORT_BITS / 32 + 1] = PORT_OUT_IMPLEMENTED; // Do not full reset USB or SWD lines. - pin_mask[0] &= ~(PORT_PA24 | PORT_PA25 | PORT_PA30 | PORT_PA31); + pin_mask[0] &= ~(PORT_PA24 | PORT_PA25 | PORT_PA30); - system_pinmux_group_set_config(&(PORT->Group[0]), pin_mask[0] & ~MICROPY_PORT_A, &config); - system_pinmux_group_set_config(&(PORT->Group[1]), pin_mask[1] & ~MICROPY_PORT_B, &config); + // The SWO pin changes between the 21 and 51. + #ifdef PORT_PB30H_CM4_SWO + pin_mask[1] &= ~(PORT_PB30); + #else + pin_mask[0] &= ~(PORT_PA31); + #endif + + //gpio_set_port_direction(GPIO_PORTA, pin_mask[0] & ~MICROPY_PORT_A, GPIO_DIRECTION_OFF); + gpio_set_port_direction(GPIO_PORTB, pin_mask[1] & ~MICROPY_PORT_B, GPIO_DIRECTION_OFF); + #if PORT_BITS > 64 + gpio_set_port_direction(GPIO_PORTC, pin_mask[2] & ~MICROPY_PORT_C, GPIO_DIRECTION_OFF); + #endif + #if PORT_BITS > 96 + gpio_set_port_direction(GPIO_PORTD, pin_mask[3] & ~MICROPY_PORT_D, GPIO_DIRECTION_OFF); + #endif // Configure SWD - system_pinmux_get_config_defaults(&config); - config.mux_position = 0x6; - system_pinmux_group_set_config(&(PORT->Group[0]), PORT_PA30 | PORT_PA31, &config); + gpio_set_pin_direction(PIN_PA30, GPIO_DIRECTION_OUT); + #ifdef SAMD51 + gpio_set_pin_function(PIN_PB30, MUX_PB30H_CM4_SWO); + gpio_set_pin_direction(PIN_PB30, GPIO_DIRECTION_OUT); + gpio_set_pin_function(PIN_PB30, MUX_PB30H_CM4_SWO); + #endif + #ifdef SAMD21 + //gpio_set_pin_function(PIN_PA30, GPIO_PIN_FUNCTION_G); + //gpio_set_pin_direction(PIN_PA31, GPIO_DIRECTION_OUT); + //gpio_set_pin_function(PIN_PA31, GPIO_PIN_FUNCTION_G); + #endif #ifdef MICROPY_HW_NEOPIXEL neopixel_in_use = false; @@ -71,12 +94,9 @@ void reset_all_pins(void) { // After configuring SWD because it may be shared. #ifdef SPEAKER_ENABLE_PIN speaker_enable_in_use = false; - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - port_pin_set_config(SPEAKER_ENABLE_PIN->pin, &pin_conf); - port_pin_set_output_level(SPEAKER_ENABLE_PIN->pin, false); + gpio_set_pin_function(SPEAKER_ENABLE_PIN->pin, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(SPEAKER_ENABLE_PIN->pin, GPIO_DIRECTION_OUT); + gpio_set_pin_level(SPEAKER_ENABLE_PIN->pin, false); #endif } @@ -104,24 +124,26 @@ void reset_pin(uint8_t pin) { } #endif - struct system_pinmux_config config; - system_pinmux_get_config_defaults(&config); - if (pin == PIN_PA30 || pin == PIN_PA31) { - config.mux_position = 0x6; + if (pin == PIN_PA30 + #ifdef SAMD51 + || pin == PIN_PB30) { + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_H); + #endif + #ifdef SAMD21 + || pin == PIN_PA31) { + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_G); + #endif } else { - config.powersave = true; + gpio_set_pin_direction(pin, GPIO_DIRECTION_OFF); + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); } - system_pinmux_pin_set_config(pin, &config); #ifdef SPEAKER_ENABLE_PIN if (pin == SPEAKER_ENABLE_PIN->pin) { speaker_enable_in_use = false; - struct port_config pin_conf; - port_get_config_defaults(&pin_conf); - - pin_conf.direction = PORT_PIN_DIR_OUTPUT; - port_pin_set_config(SPEAKER_ENABLE_PIN->pin, &pin_conf); - port_pin_set_output_level(SPEAKER_ENABLE_PIN->pin, false); + gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_OFF); + gpio_set_pin_direction(SPEAKER_ENABLE_PIN->pin, GPIO_DIRECTION_OUT); + gpio_set_pin_level(SPEAKER_ENABLE_PIN->pin, false); } #endif } @@ -169,8 +191,8 @@ bool common_hal_mcu_pin_is_free(const mcu_pin_obj_t* pin) { } #endif - PortGroup *const port = system_pinmux_get_group_from_gpio_pin(pin->pin); - uint32_t pin_index = (pin->pin); + PortGroup *const port = &PORT->Group[(enum gpio_port)GPIO_PORT(pin->pin)]; + uint8_t pin_index = GPIO_PIN(pin->pin); volatile PORT_PINCFG_Type *state = &port->PINCFG[pin_index]; volatile PORT_PMUX_Type *pmux = &port->PMUX[pin_index / 2]; diff --git a/atmel-samd/common-hal/microcontroller/Pin.h b/atmel-samd/common-hal/microcontroller/Pin.h index 31c0833116a6f..154ea1e47cae2 100644 --- a/atmel-samd/common-hal/microcontroller/Pin.h +++ b/atmel-samd/common-hal/microcontroller/Pin.h @@ -27,17 +27,11 @@ #ifndef MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_MICROCONTROLLER_PIN_H #define MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_MICROCONTROLLER_PIN_H -// Don't reorder these includes because they are dependencies of adc_feature.h. -// They should really be included by adc_feature.h. -#include "compiler.h" -#include "asf/sam0/drivers/system/clock/gclk.h" -#include "asf/sam0/utils/cmsis/samd21/include/component/adc.h" -#include "asf/sam0/drivers/adc/adc_sam_d_r/adc_feature.h" // for adc_positive_input +#include "py/obj.h" -#include "asf/sam0/drivers/tc/tc.h" -#include "asf/sam0/drivers/tcc/tcc.h" +#include "mpconfigport.h" -#include "py/obj.h" +#include "include/component/sercom.h" typedef struct { Sercom *const sercom; @@ -49,24 +43,32 @@ typedef struct { Tc *const tc; Tcc *const tcc; }; + #ifdef SAMD21 bool is_tc:1; - uint8_t channel:3; + #endif uint8_t wave_output:4; } pin_timer_t; +#ifdef SAMD21 + #define NUM_TIMERS_PER_PIN 2 + #define NUM_ADC_PER_PIN 1 +#endif +#ifdef SAMD51 + #define NUM_TIMERS_PER_PIN 3 + #define NUM_ADC_PER_PIN 2 +#endif #define NUM_SERCOMS_PER_PIN 2 + typedef struct { mp_obj_base_t base; qstr name; uint8_t pin; bool has_extint:1; uint8_t extint_channel:7; - bool has_adc:1; - enum adc_positive_input adc_input:7; bool has_touch:1; uint8_t touch_y_line:7; // 0 - 15. Assumed to be Y channel. - pin_timer_t primary_timer; - pin_timer_t secondary_timer; + uint8_t adc_input[NUM_ADC_PER_PIN]; + pin_timer_t timer[NUM_TIMERS_PER_PIN]; pin_sercom_t sercom[NUM_SERCOMS_PER_PIN]; } mcu_pin_obj_t; diff --git a/atmel-samd/common-hal/microcontroller/Processor.c b/atmel-samd/common-hal/microcontroller/Processor.c index c398c5e6fb27a..a037c42db678e 100644 --- a/atmel-samd/common-hal/microcontroller/Processor.c +++ b/atmel-samd/common-hal/microcontroller/Processor.c @@ -63,175 +63,169 @@ #include "common-hal/microcontroller/Processor.h" -// Don't reorder these includes because they are dependencies of adc_feature.h. -// They should really be included by adc_feature.h. -#include -#include "asf/sam0/drivers/system/clock/gclk.h" -#include "asf/sam0/utils/cmsis/samd21/include/component/adc.h" -#include "asf/sam0/drivers/adc/adc_sam_d_r/adc_feature.h" -#include "asf/sam0/drivers/adc/adc.h" - -#define ADC_TEMP_SAMPLE_LENGTH 4 -#define INT1V_VALUE_FLOAT 1.0 -#define INT1V_DIVIDER_1000 1000.0 -#define ADC_12BIT_FULL_SCALE_VALUE_FLOAT 4095.0 - -typedef struct nvm_calibration_data_t { - float tempR; // Production Room temperature - float tempH; // Production Hot temperature - float INT1VR; // Room temp 2's complement of the internal 1V reference value - float INT1VH; // Hot temp 2's complement of the internal 1V reference value - uint16_t ADCR; // Production Room temperature ADC value - uint16_t ADCH; // Production Hot temperature ADC value - float VADCR; // Room temperature ADC voltage - float VADCH; // Hot temperature ADC voltage -} nvm_calibration_data_t; +// #define ADC_TEMP_SAMPLE_LENGTH 4 +// #define INT1V_VALUE_FLOAT 1.0 +// #define INT1V_DIVIDER_1000 1000.0 +// #define ADC_12BIT_FULL_SCALE_VALUE_FLOAT 4095.0 +// +// typedef struct nvm_calibration_data_t { +// float tempR; // Production Room temperature +// float tempH; // Production Hot temperature +// float INT1VR; // Room temp 2's complement of the internal 1V reference value +// float INT1VH; // Hot temp 2's complement of the internal 1V reference value +// uint16_t ADCR; // Production Room temperature ADC value +// uint16_t ADCH; // Production Hot temperature ADC value +// float VADCR; // Room temperature ADC voltage +// float VADCH; // Hot temperature ADC voltage +// } nvm_calibration_data_t; // Decimal to fraction conversion. (adapted from ASF sample). -STATIC float convert_dec_to_frac(uint8_t val) { - float float_val = (float)val; - if (val < 10) { - return (float_val/10.0); - } else if (val < 100) { - return (float_val/100.0); - } else { - return (float_val/1000.0); - } -} - -STATIC void configure_adc_temp(struct adc_module *adc_instance) { - struct adc_config config_adc; - adc_get_config_defaults(&config_adc); - - // The parameters chosen here are from the temperature example in: - // http://www.atmel.com/images/Atmel-42645-ADC-Configurations-with-Examples_ApplicationNote_AT11481.pdf - // That note also recommends in general: - // "Discard the first conversion result whenever there is a change - // in ADC configuration like voltage reference / ADC channel change." - - config_adc.clock_prescaler = ADC_CLOCK_PRESCALER_DIV16; - config_adc.reference = ADC_REFERENCE_INT1V; - config_adc.positive_input = ADC_POSITIVE_INPUT_TEMP; - config_adc.negative_input = ADC_NEGATIVE_INPUT_GND; - config_adc.sample_length = ADC_TEMP_SAMPLE_LENGTH; - - adc_init(adc_instance, ADC, &config_adc); - - // Oversample and decimate. A higher samplenum produces a more stable result. - ADC->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(2) | ADC_AVGCTRL_SAMPLENUM_4; - //ADC->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(4) | ADC_AVGCTRL_SAMPLENUM_16; -} +// STATIC float convert_dec_to_frac(uint8_t val) { +// float float_val = (float)val; +// if (val < 10) { +// return (float_val/10.0); +// } else if (val < 100) { +// return (float_val/100.0); +// } else { +// return (float_val/1000.0); +// } +// } + +// STATIC void configure_adc_temp(struct adc_module *adc_instance) { +// struct adc_config config_adc; +// adc_get_config_defaults(&config_adc); +// +// // The parameters chosen here are from the temperature example in: +// // http://www.atmel.com/images/Atmel-42645-ADC-Configurations-with-Examples_ApplicationNote_AT11481.pdf +// // That note also recommends in general: +// // "Discard the first conversion result whenever there is a change +// // in ADC configuration like voltage reference / ADC channel change." +// +// config_adc.clock_prescaler = ADC_CLOCK_PRESCALER_DIV16; +// config_adc.reference = ADC_REFERENCE_INT1V; +// config_adc.positive_input = ADC_POSITIVE_INPUT_TEMP; +// config_adc.negative_input = ADC_NEGATIVE_INPUT_GND; +// config_adc.sample_length = ADC_TEMP_SAMPLE_LENGTH; +// +// adc_init(adc_instance, ADC, &config_adc); +// +// // Oversample and decimate. A higher samplenum produces a more stable result. +// ADC->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(2) | ADC_AVGCTRL_SAMPLENUM_4; +// //ADC->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(4) | ADC_AVGCTRL_SAMPLENUM_16; +// } // Extract the production calibration data information from NVM (adapted from ASF sample). // -STATIC void load_calibration_data(nvm_calibration_data_t *cal) { - volatile uint32_t val1; /* Temperature Log Row Content first 32 bits */ - volatile uint32_t val2; /* Temperature Log Row Content another 32 bits */ - uint8_t room_temp_val_int; /* Integer part of room temperature in °C */ - uint8_t room_temp_val_dec; /* Decimal part of room temperature in °C */ - uint8_t hot_temp_val_int; /* Integer part of hot temperature in °C */ - uint8_t hot_temp_val_dec; /* Decimal part of hot temperature in °C */ - int8_t room_int1v_val; /* internal 1V reference drift at room temperature */ - int8_t hot_int1v_val; /* internal 1V reference drift at hot temperature*/ - - uint32_t *temp_log_row_ptr = (uint32_t *)NVMCTRL_TEMP_LOG; - - val1 = *temp_log_row_ptr; - temp_log_row_ptr++; - val2 = *temp_log_row_ptr; - - room_temp_val_int = (uint8_t)((val1 & NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk) >> NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos); - room_temp_val_dec = (uint8_t)((val1 & NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk) >> NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos); - - hot_temp_val_int = (uint8_t)((val1 & NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk) >> NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos); - hot_temp_val_dec = (uint8_t)((val1 & NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk) >> NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos); - - room_int1v_val = (int8_t)((val1 & NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk) >> NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos); - hot_int1v_val = (int8_t)((val2 & NVMCTRL_FUSES_HOT_INT1V_VAL_Msk) >> NVMCTRL_FUSES_HOT_INT1V_VAL_Pos); - - cal->ADCR = (uint16_t)((val2 & NVMCTRL_FUSES_ROOM_ADC_VAL_Msk) >> NVMCTRL_FUSES_ROOM_ADC_VAL_Pos); - - cal->ADCH = (uint16_t)((val2 & NVMCTRL_FUSES_HOT_ADC_VAL_Msk) >> NVMCTRL_FUSES_HOT_ADC_VAL_Pos); - - cal->tempR = room_temp_val_int + convert_dec_to_frac(room_temp_val_dec); - cal->tempH = hot_temp_val_int + convert_dec_to_frac(hot_temp_val_dec); - - cal->INT1VR = 1 - ((float)room_int1v_val/INT1V_DIVIDER_1000); - cal->INT1VH = 1 - ((float)hot_int1v_val/INT1V_DIVIDER_1000); - - cal->VADCR = ((float)cal->ADCR * cal->INT1VR)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; - cal->VADCH = ((float)cal->ADCH * cal->INT1VH)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; -} +// STATIC void load_calibration_data(nvm_calibration_data_t *cal) { +// volatile uint32_t val1; /* Temperature Log Row Content first 32 bits */ +// volatile uint32_t val2; /* Temperature Log Row Content another 32 bits */ +// uint8_t room_temp_val_int; /* Integer part of room temperature in °C */ +// uint8_t room_temp_val_dec; /* Decimal part of room temperature in °C */ +// uint8_t hot_temp_val_int; /* Integer part of hot temperature in °C */ +// uint8_t hot_temp_val_dec; /* Decimal part of hot temperature in °C */ +// int8_t room_int1v_val; /* internal 1V reference drift at room temperature */ +// int8_t hot_int1v_val; /* internal 1V reference drift at hot temperature*/ +// +// uint32_t *temp_log_row_ptr = (uint32_t *)NVMCTRL_TEMP_LOG; +// +// val1 = *temp_log_row_ptr; +// temp_log_row_ptr++; +// val2 = *temp_log_row_ptr; +// +// room_temp_val_int = (uint8_t)((val1 & NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Msk) >> NVMCTRL_FUSES_ROOM_TEMP_VAL_INT_Pos); +// room_temp_val_dec = (uint8_t)((val1 & NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Msk) >> NVMCTRL_FUSES_ROOM_TEMP_VAL_DEC_Pos); +// +// hot_temp_val_int = (uint8_t)((val1 & NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Msk) >> NVMCTRL_FUSES_HOT_TEMP_VAL_INT_Pos); +// hot_temp_val_dec = (uint8_t)((val1 & NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Msk) >> NVMCTRL_FUSES_HOT_TEMP_VAL_DEC_Pos); +// +// room_int1v_val = (int8_t)((val1 & NVMCTRL_FUSES_ROOM_INT1V_VAL_Msk) >> NVMCTRL_FUSES_ROOM_INT1V_VAL_Pos); +// hot_int1v_val = (int8_t)((val2 & NVMCTRL_FUSES_HOT_INT1V_VAL_Msk) >> NVMCTRL_FUSES_HOT_INT1V_VAL_Pos); +// +// cal->ADCR = (uint16_t)((val2 & NVMCTRL_FUSES_ROOM_ADC_VAL_Msk) >> NVMCTRL_FUSES_ROOM_ADC_VAL_Pos); +// +// cal->ADCH = (uint16_t)((val2 & NVMCTRL_FUSES_HOT_ADC_VAL_Msk) >> NVMCTRL_FUSES_HOT_ADC_VAL_Pos); +// +// cal->tempR = room_temp_val_int + convert_dec_to_frac(room_temp_val_dec); +// cal->tempH = hot_temp_val_int + convert_dec_to_frac(hot_temp_val_dec); +// +// cal->INT1VR = 1 - ((float)room_int1v_val/INT1V_DIVIDER_1000); +// cal->INT1VH = 1 - ((float)hot_int1v_val/INT1V_DIVIDER_1000); +// +// cal->VADCR = ((float)cal->ADCR * cal->INT1VR)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; +// cal->VADCH = ((float)cal->ADCH * cal->INT1VH)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; +// } /* * Calculate fine temperature using Equation1 and Equation * 1b as mentioned in data sheet section "Temperature Sensor Characteristics" * of Electrical Characteristics. (adapted from ASF sample code). */ -STATIC float calculate_temperature(uint16_t raw_code, nvm_calibration_data_t *cal) -{ - float VADC; /* Voltage calculation using ADC result for Coarse Temp calculation */ - float VADCM; /* Voltage calculation using ADC result for Fine Temp calculation. */ - float INT1VM; /* Voltage calculation for reality INT1V value during the ADC conversion */ - - VADC = ((float)raw_code * INT1V_VALUE_FLOAT)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; - - // Hopefully compiler will remove common subepxressions here. - - /* Coarse Temp Calculation by assume INT1V=1V for this ADC conversion */ - float coarse_temp = cal->tempR + (((cal->tempH - cal->tempR)/(cal->VADCH - cal->VADCR)) * (VADC - cal->VADCR)); - - /* Calculation to find the real INT1V value during the ADC conversion */ - INT1VM = cal->INT1VR + (((cal->INT1VH - cal->INT1VR) * (coarse_temp - cal->tempR))/(cal->tempH - cal->tempR)); - - VADCM = ((float)raw_code * INT1VM)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; - - /* Fine Temp Calculation by replace INT1V=1V by INT1V = INT1Vm for ADC conversion */ - float fine_temp = cal->tempR + (((cal->tempH - cal->tempR)/(cal->VADCH - cal->VADCR)) * (VADCM - cal->VADCR)); - - return fine_temp; -} +// STATIC float calculate_temperature(uint16_t raw_code, nvm_calibration_data_t *cal) +// { +// float VADC; /* Voltage calculation using ADC result for Coarse Temp calculation */ +// float VADCM; /* Voltage calculation using ADC result for Fine Temp calculation. */ +// float INT1VM; /* Voltage calculation for reality INT1V value during the ADC conversion */ +// +// VADC = ((float)raw_code * INT1V_VALUE_FLOAT)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; +// +// // Hopefully compiler will remove common subepxressions here. +// +// /* Coarse Temp Calculation by assume INT1V=1V for this ADC conversion */ +// float coarse_temp = cal->tempR + (((cal->tempH - cal->tempR)/(cal->VADCH - cal->VADCR)) * (VADC - cal->VADCR)); +// +// /* Calculation to find the real INT1V value during the ADC conversion */ +// INT1VM = cal->INT1VR + (((cal->INT1VH - cal->INT1VR) * (coarse_temp - cal->tempR))/(cal->tempH - cal->tempR)); +// +// VADCM = ((float)raw_code * INT1VM)/ADC_12BIT_FULL_SCALE_VALUE_FLOAT; +// +// /* Fine Temp Calculation by replace INT1V=1V by INT1V = INT1Vm for ADC conversion */ +// float fine_temp = cal->tempR + (((cal->tempH - cal->tempR)/(cal->VADCH - cal->VADCR)) * (VADCM - cal->VADCR)); +// +// return fine_temp; +// } // External interface. // float common_hal_mcu_processor_get_temperature(void) { - struct adc_module adc_instance_struct; - - system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE); - configure_adc_temp(&adc_instance_struct); - nvm_calibration_data_t nvm_calibration_data; - load_calibration_data(&nvm_calibration_data); - - adc_enable(&adc_instance_struct); - - uint16_t data; - enum status_code status; - - // Read twice and discard first result, as recommended in section 14 of - // http://www.atmel.com/images/Atmel-42645-ADC-Configurations-with-Examples_ApplicationNote_AT11481.pdf - // "Discard the first conversion result whenever there is a change in ADC configuration - // like voltage reference / ADC channel change" - // Empirical observation shows the first reading is quite different than subsequent ones. - - adc_start_conversion(&adc_instance_struct); - do { - status = adc_read(&adc_instance_struct, &data); - } while (status == STATUS_BUSY); - - adc_start_conversion(&adc_instance_struct); - do { - status = adc_read(&adc_instance_struct, &data); - } while (status == STATUS_BUSY); - - // Disable so that someone else can use the adc with different settings. - adc_disable(&adc_instance_struct); - return calculate_temperature(data, &nvm_calibration_data); + // struct adc_module adc_instance_struct; + // + // system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_TEMPSENSE); + // configure_adc_temp(&adc_instance_struct); + // nvm_calibration_data_t nvm_calibration_data; + // load_calibration_data(&nvm_calibration_data); + // + // adc_enable(&adc_instance_struct); + // + // uint16_t data; + // enum status_code status; + // + // // Read twice and discard first result, as recommended in section 14 of + // // http://www.atmel.com/images/Atmel-42645-ADC-Configurations-with-Examples_ApplicationNote_AT11481.pdf + // // "Discard the first conversion result whenever there is a change in ADC configuration + // // like voltage reference / ADC channel change" + // // Empirical observation shows the first reading is quite different than subsequent ones. + // + // adc_start_conversion(&adc_instance_struct); + // do { + // status = adc_read(&adc_instance_struct, &data); + // } while (status == STATUS_BUSY); + // + // adc_start_conversion(&adc_instance_struct); + // do { + // status = adc_read(&adc_instance_struct, &data); + // } while (status == STATUS_BUSY); + // + // // Disable so that someone else can use the adc with different settings. + // adc_disable(&adc_instance_struct); + // return calculate_temperature(data, &nvm_calibration_data); + return 0; } uint32_t common_hal_mcu_processor_get_frequency(void) { - return system_cpu_clock_get_hz(); + return 0; + //return system_cpu_clock_get_hz(); } diff --git a/atmel-samd/common-hal/microcontroller/__init__.c b/atmel-samd/common-hal/microcontroller/__init__.c index 84cea008b8d22..5c119c439c5e0 100644 --- a/atmel-samd/common-hal/microcontroller/__init__.c +++ b/atmel-samd/common-hal/microcontroller/__init__.c @@ -26,6 +26,7 @@ #include "py/mphal.h" #include "py/obj.h" +#include "hal/include/hal_atomic.h" #include "samd21_pins.h" @@ -38,17 +39,13 @@ void common_hal_mcu_delay_us(uint32_t delay) { // Interrupt flags that will be saved and restored during disable/Enable // interrupt functions below. -static irqflags_t irq_flags; +volatile hal_atomic_t flags; void common_hal_mcu_disable_interrupts(void) { - // Disable all interrupt sources for timing critical sections. - // Disable ASF-based interrupts. - irq_flags = cpu_irq_save(); + atomic_enter_critical(&flags); } void common_hal_mcu_enable_interrupts(void) { - // Enable all interrupt sources after timing critical sections. - // Restore ASF-based interrupts. - cpu_irq_restore(irq_flags); + atomic_leave_critical(&flags); } // The singleton microcontroller.Processor object, bound to microcontroller.cpu @@ -62,13 +59,13 @@ mcu_processor_obj_t common_hal_mcu_processor_obj = { // NVM is only available on Express boards for now. #if CIRCUITPY_INTERNAL_NVM_SIZE > 0 // The singleton nvm.ByteArray object. -nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { - .base = { - .type = &nvm_bytearray_type, - }, - .len = NVMCTRL_ROW_SIZE, - .start_address = (uint8_t*) (FLASH_SIZE - NVMCTRL_ROW_SIZE) -}; +// nvm_bytearray_obj_t common_hal_mcu_nvm_obj = { +// .base = { +// .type = &nvm_bytearray_type, +// }, +// .len = NVMCTRL_ROW_SIZE, +// .start_address = (uint8_t*) (FLASH_SIZE - NVMCTRL_ROW_SIZE) +// }; #endif // This maps MCU pin names to pin objects. diff --git a/atmel-samd/common-hal/pulseio/PWMOut.h b/atmel-samd/common-hal/pulseio/PWMOut.h index 67eabd92e4567..d6af617a984f2 100644 --- a/atmel-samd/common-hal/pulseio/PWMOut.h +++ b/atmel-samd/common-hal/pulseio/PWMOut.h @@ -28,8 +28,6 @@ #define MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_PULSEIO_PWMOUT_H #include "common-hal/microcontroller/Pin.h" -#include "asf/sam0/drivers/tc/tc.h" -#include "asf/sam0/drivers/tcc/tcc.h" #include "py/obj.h" diff --git a/atmel-samd/common-hal/pulseio/PulseOut.h b/atmel-samd/common-hal/pulseio/PulseOut.h index 29690fdd183c7..4294d6d68d34d 100644 --- a/atmel-samd/common-hal/pulseio/PulseOut.h +++ b/atmel-samd/common-hal/pulseio/PulseOut.h @@ -28,8 +28,6 @@ #define MICROPY_INCLUDED_ATMEL_SAMD_COMMON_HAL_PULSEIO_PULSEOUT_H #include "common-hal/microcontroller/Pin.h" -#include "asf/sam0/drivers/tc/tc.h" -#include "asf/sam0/drivers/tcc/tcc.h" #include "py/obj.h" diff --git a/atmel-samd/common-hal/usb_hid/types.h b/atmel-samd/common-hal/usb_hid/types.h index 80e7ef0b514b8..c276ebd0de8c1 100644 --- a/atmel-samd/common-hal/usb_hid/types.h +++ b/atmel-samd/common-hal/usb_hid/types.h @@ -27,8 +27,6 @@ #ifndef MICROPY_INCLUDED_COMMON_HAL_USB_HID_TYPES_H #define MICROPY_INCLUDED_COMMON_HAL_USB_HID_TYPES_H -#include "conf_usb.h" - #include "py/obj.h" typedef struct { diff --git a/atmel-samd/main.c b/atmel-samd/main.c deleted file mode 100644 index 3a2d5a63c26d1..0000000000000 --- a/atmel-samd/main.c +++ /dev/null @@ -1,779 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2016 Scott Shawcroft for Adafruit Industries - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include -#include - -#include "py/nlr.h" -#include "py/compile.h" -#include "py/frozenmod.h" -#include "py/mphal.h" -#include "py/runtime.h" -#include "py/repl.h" -#include "py/gc.h" -#include "py/stackctrl.h" - -#include "extmod/vfs_fat.h" -#include "lib/oofatfs/ff.h" -#include "lib/oofatfs/diskio.h" -#include "lib/mp-readline/readline.h" -#include "lib/utils/pyexec.h" - -#include "asf/common/services/sleepmgr/sleepmgr.h" -#include "asf/common/services/usb/udc/udc.h" -#include "asf/common2/services/delay/delay.h" -#include "asf/sam0/drivers/nvm/nvm.h" -#include "asf/sam0/drivers/port/port.h" -#include "asf/sam0/drivers/sercom/usart/usart.h" -#include "asf/sam0/drivers/system/system.h" -#include - -#include "boards/board.h" - -#include "common-hal/analogio/AnalogIn.h" -#include "common-hal/audioio/AudioOut.h" -#include "common-hal/audiobusio/PDMIn.h" -#include "common-hal/pulseio/PulseIn.h" -#include "common-hal/pulseio/PulseOut.h" -#include "common-hal/pulseio/PWMOut.h" -#include "common-hal/usb_hid/__init__.h" - -#include "autoreload.h" -#include "flash_api.h" -#include "mpconfigboard.h" -#include "rgb_led_status.h" -#include "shared_dma.h" -#include "tick.h" - -#ifdef EXPRESS_BOARD -#include "common-hal/touchio/TouchIn.h" -#define INTERNAL_CIRCUITPY_CONFIG_START_ADDR (0x00040000 - 0x100 - CIRCUITPY_INTERNAL_NVM_SIZE) -#else -#define INTERNAL_CIRCUITPY_CONFIG_START_ADDR (0x00040000 - 0x010000 - 0x100 - CIRCUITPY_INTERNAL_NVM_SIZE) -#endif - -fs_user_mount_t fs_user_mount_flash; -mp_vfs_mount_t mp_vfs_mount_flash; - -typedef enum { - NO_SAFE_MODE = 0, - BROWNOUT, - HARD_CRASH, - USER_SAFE_MODE, -} safe_mode_t; - -void do_str(const char *src, mp_parse_input_kind_t input_kind) { - mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0); - if (lex == NULL) { - printf("MemoryError: lexer could not allocate memory\n"); - return; - } - - nlr_buf_t nlr; - if (nlr_push(&nlr) == 0) { - qstr source_name = lex->source_name; - mp_parse_tree_t parse_tree = mp_parse(lex, input_kind); - mp_obj_t module_fun = mp_compile(&parse_tree, source_name, MP_EMIT_OPT_NONE, true); - mp_call_function_0(module_fun); - nlr_pop(); - } else { - // uncaught exception - mp_obj_print_exception(&mp_plat_print, (mp_obj_t)nlr.ret_val); - } -} - -// we don't make this function static because it needs a lot of stack and we -// want it to be executed without using stack within main() function -void init_flash_fs(void) { - // init the vfs object - fs_user_mount_t *vfs_fat = &fs_user_mount_flash; - vfs_fat->flags = 0; - flash_init_vfs(vfs_fat); - - // try to mount the flash - FRESULT res = f_mount(&vfs_fat->fatfs); - - if (res == FR_NO_FILESYSTEM) { - // no filesystem so create a fresh one - - uint8_t working_buf[_MAX_SS]; - res = f_mkfs(&vfs_fat->fatfs, FM_FAT, 0, working_buf, sizeof(working_buf)); - // Flush the new file system to make sure its repaired immediately. - flash_flush(); - if (res != FR_OK) { - return; - } - - // set label - f_setlabel(&vfs_fat->fatfs, "CIRCUITPY"); - } else if (res != FR_OK) { - return; - } - mp_vfs_mount_t *vfs = &mp_vfs_mount_flash; - vfs->str = "/"; - vfs->len = 1; - vfs->obj = MP_OBJ_FROM_PTR(vfs_fat); - vfs->next = NULL; - MP_STATE_VM(vfs_mount_table) = vfs; - - // The current directory is used as the boot up directory. - // It is set to the internal flash filesystem by default. - MP_STATE_PORT(vfs_cur) = vfs; -} - -static char heap[16384 + 4096]; - -void reset_mp(void) { - reset_status_led(); - new_status_color(0x8f008f); - autoreload_stop(); - - // Sync the file systems in case any used RAM from the GC to cache. As soon - // as we re-init the GC all bets are off on the cache. - flash_flush(); - - // Clear the readline history. It references the heap we're about to destroy. - readline_init0(); - - #if MICROPY_ENABLE_GC - gc_init(heap, heap + sizeof(heap)); - #endif - mp_init(); - mp_obj_list_init(mp_sys_path, 0); - mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script) - mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_)); - mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_lib)); - // Frozen modules are in their own pseudo-dir, e.g., ".frozen". - mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_FROZEN_FAKE_DIR_QSTR)); - - mp_obj_list_init(mp_sys_argv, 0); -} - -extern volatile bool mp_msc_enabled; - -void reset_samd21(void) { - // Reset all SERCOMs except the one being used by the SPI flash. - Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS; - for (int i = 0; i < SERCOM_INST_NUM; i++) { - #ifdef SPI_FLASH_SERCOM - if (sercom_instances[i] == SPI_FLASH_SERCOM) { - continue; - } - #endif - #ifdef MICROPY_HW_APA102_SERCOM - if (sercom_instances[i] == MICROPY_HW_APA102_SERCOM) { - continue; - } - #endif - sercom_instances[i]->SPI.CTRLA.bit.SWRST = 1; - } - -#ifdef EXPRESS_BOARD - audioout_reset(); - touchin_reset(); - pdmin_reset(); - pulsein_reset(); - pulseout_reset(); - pwmout_reset(); -#endif - - analogin_reset(); - - - // Wait for the DAC to sync then reset. - while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {} - DAC->CTRLA.reg |= DAC_CTRLA_SWRST; - - reset_all_pins(); - - - usb_hid_reset(); - -#ifdef CALIBRATE_CRYSTALLESS - // If we are on USB lets double check our fine calibration for the clock and - // save the new value if its different enough. - if (mp_msc_enabled) { - SYSCTRL->DFLLSYNC.bit.READREQ = 1; - uint16_t saved_calibration = 0x1ff; - if (strcmp((char*) INTERNAL_CIRCUITPY_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) { - saved_calibration = ((uint16_t *) INTERNAL_CIRCUITPY_CONFIG_START_ADDR)[8]; - } - while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) { - // TODO(tannewt): Run the mass storage stuff if this takes a while. - } - int16_t current_calibration = SYSCTRL->DFLLVAL.bit.FINE; - if (abs(current_calibration - saved_calibration) > 10) { - enum status_code error_code; - uint8_t page_buffer[NVMCTRL_ROW_SIZE]; - for (int i = 0; i < NVMCTRL_ROW_PAGES; i++) { - do - { - error_code = nvm_read_buffer(INTERNAL_CIRCUITPY_CONFIG_START_ADDR + i * NVMCTRL_PAGE_SIZE, - page_buffer + i * NVMCTRL_PAGE_SIZE, - NVMCTRL_PAGE_SIZE); - } while (error_code == STATUS_BUSY); - } - // If this is the first write, include the header. - if (strcmp((char*) page_buffer, "CIRCUITPYTHON1") != 0) { - memcpy(page_buffer, "CIRCUITPYTHON1", 15); - } - // First 16 bytes (0-15) are ID. Little endian! - page_buffer[16] = current_calibration & 0xff; - page_buffer[17] = current_calibration >> 8; - do - { - error_code = nvm_erase_row(INTERNAL_CIRCUITPY_CONFIG_START_ADDR); - } while (error_code == STATUS_BUSY); - for (int i = 0; i < NVMCTRL_ROW_PAGES; i++) { - do - { - error_code = nvm_write_buffer(INTERNAL_CIRCUITPY_CONFIG_START_ADDR + i * NVMCTRL_PAGE_SIZE, - page_buffer + i * NVMCTRL_PAGE_SIZE, - NVMCTRL_PAGE_SIZE); - } while (error_code == STATUS_BUSY); - } - } - } -#endif -} - -bool maybe_run(const char* filename, pyexec_result_t* exec_result) { - mp_import_stat_t stat = mp_import_stat(filename); - if (stat != MP_IMPORT_STAT_FILE) { - return false; - } - mp_hal_stdout_tx_str(filename); - mp_hal_stdout_tx_str(" output:\r\n"); - pyexec_file(filename, exec_result); - return true; -} - -bool start_mp(safe_mode_t safe_mode) { - bool cdc_enabled_at_start = mp_cdc_enabled; - #ifdef CIRCUITPY_AUTORELOAD_DELAY_MS - if (cdc_enabled_at_start) { - mp_hal_stdout_tx_str("\r\n"); - if (autoreload_is_enabled()) { - mp_hal_stdout_tx_str("Auto-reload is on. Simply save files over USB to run them or enter REPL to disable.\r\n"); - } else if (safe_mode != NO_SAFE_MODE) { - mp_hal_stdout_tx_str("Running in safe mode! Auto-reload is off.\r\n"); - } else if (!autoreload_is_enabled()) { - mp_hal_stdout_tx_str("Auto-reload is off.\r\n"); - } - } - #endif - - pyexec_result_t result; - bool found_main = false; - if (safe_mode != NO_SAFE_MODE) { - mp_hal_stdout_tx_str("Running in safe mode! Not running saved code.\r\n"); - } else { - new_status_color(MAIN_RUNNING); - found_main = maybe_run("code.txt", &result) || - maybe_run("code.py", &result) || - maybe_run("main.py", &result) || - maybe_run("main.txt", &result); - reset_status_led(); - - if (result.return_code & PYEXEC_FORCED_EXIT) { - return reload_next_character; - } - - // If not is USB mode then do not skip the repl. - #ifndef USB_REPL - return false; - #endif - } - - // Wait for connection or character. - bool cdc_enabled_before = false; - #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) - new_status_color(ALL_DONE); - uint32_t pattern_start = ticks_ms; - - uint32_t total_exception_cycle = 0; - uint8_t ones = result.exception_line % 10; - ones += ones > 0 ? 1 : 0; - uint8_t tens = (result.exception_line / 10) % 10; - tens += tens > 0 ? 1 : 0; - uint8_t hundreds = (result.exception_line / 100) % 10; - hundreds += hundreds > 0 ? 1 : 0; - uint8_t thousands = (result.exception_line / 1000) % 10; - thousands += thousands > 0 ? 1 : 0; - uint8_t digit_sum = ones + tens + hundreds + thousands; - uint8_t num_places = 0; - uint16_t line = result.exception_line; - for (int i = 0; i < 4; i++) { - if ((line % 10) > 0) { - num_places++; - } - line /= 10; - } - if (result.return_code == PYEXEC_EXCEPTION) { - total_exception_cycle = EXCEPTION_TYPE_LENGTH_MS * 3 + LINE_NUMBER_TOGGLE_LENGTH * digit_sum + LINE_NUMBER_TOGGLE_LENGTH * num_places; - } - #endif - while (true) { - #ifdef MICROPY_VM_HOOK_LOOP - MICROPY_VM_HOOK_LOOP - #endif - if (reload_next_character) { - return true; - } - if (usb_rx_count > 0) { - // Skip REPL if reload was requested. - return receive_usb() == CHAR_CTRL_D; - } - - if (!cdc_enabled_before && mp_cdc_enabled) { - if (cdc_enabled_at_start) { - mp_hal_stdout_tx_str("\r\n\r\n"); - } - - if (!cdc_enabled_at_start) { - if (autoreload_is_enabled()) { - mp_hal_stdout_tx_str("Auto-reload is on. Simply save files over USB to run them or enter REPL to disable.\r\n"); - } else { - mp_hal_stdout_tx_str("Auto-reload is off.\r\n"); - } - } - // Output a user safe mode string if its set. - #ifdef BOARD_USER_SAFE_MODE - if (safe_mode == USER_SAFE_MODE) { - mp_hal_stdout_tx_str("\r\nYou requested starting safe mode by "); - mp_hal_stdout_tx_str(BOARD_USER_SAFE_MODE); - mp_hal_stdout_tx_str(".\r\nTo exit, please reset the board without "); - mp_hal_stdout_tx_str(BOARD_USER_SAFE_MODE); - mp_hal_stdout_tx_str(".\r\n"); - } else - #endif - if (safe_mode != NO_SAFE_MODE) { - mp_hal_stdout_tx_str("\r\nYou are running in safe mode which means something really bad happened.\r\n"); - if (safe_mode == HARD_CRASH) { - mp_hal_stdout_tx_str("Looks like our core CircuitPython code crashed hard. Whoops!\r\n"); - mp_hal_stdout_tx_str("Please file an issue here with the contents of your CIRCUITPY drive:\r\n"); - mp_hal_stdout_tx_str("https://github.com/adafruit/circuitpython/issues\r\n"); - } else if (safe_mode == BROWNOUT) { - mp_hal_stdout_tx_str("The microcontroller's power dipped. Please make sure your power supply provides \r\n"); - mp_hal_stdout_tx_str("enough power for the whole circuit and press reset (after ejecting CIRCUITPY).\r\n"); - } - } - mp_hal_stdout_tx_str("\r\nPress any key to enter the REPL. Use CTRL-D to reload.\r\n"); - } - if (cdc_enabled_before && !mp_cdc_enabled) { - cdc_enabled_at_start = false; - } - cdc_enabled_before = mp_cdc_enabled; - - #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) - uint32_t tick_diff = ticks_ms - pattern_start; - if (result.return_code != PYEXEC_EXCEPTION) { - // All is good. Ramp ALL_DONE up and down. - if (tick_diff > ALL_GOOD_CYCLE_MS) { - pattern_start = ticks_ms; - tick_diff = 0; - } - - uint16_t brightness = tick_diff * 255 / (ALL_GOOD_CYCLE_MS / 2); - if (brightness > 255) { - brightness = 511 - brightness; - } - if (safe_mode == NO_SAFE_MODE) { - new_status_color(color_brightness(ALL_DONE, brightness)); - } else { - new_status_color(color_brightness(SAFE_MODE, brightness)); - } - } else { - if (tick_diff > total_exception_cycle) { - pattern_start = ticks_ms; - tick_diff = 0; - } - // First flash the file color. - if (tick_diff < EXCEPTION_TYPE_LENGTH_MS) { - if (found_main) { - new_status_color(MAIN_RUNNING); - } else { - new_status_color(BOOT_RUNNING); - } - // Next flash the exception color. - } else if (tick_diff < EXCEPTION_TYPE_LENGTH_MS * 2) { - if (mp_obj_is_subclass_fast(result.exception_type, &mp_type_IndentationError)) { - new_status_color(INDENTATION_ERROR); - } else if (mp_obj_is_subclass_fast(result.exception_type, &mp_type_SyntaxError)) { - new_status_color(SYNTAX_ERROR); - } else if (mp_obj_is_subclass_fast(result.exception_type, &mp_type_NameError)) { - new_status_color(NAME_ERROR); - } else if (mp_obj_is_subclass_fast(result.exception_type, &mp_type_OSError)) { - new_status_color(OS_ERROR); - } else if (mp_obj_is_subclass_fast(result.exception_type, &mp_type_ValueError)) { - new_status_color(VALUE_ERROR); - } else { - new_status_color(OTHER_ERROR); - } - // Finally flash the line number digits from highest to lowest. - // Zeroes will not produce a flash but can be read by the absence of - // a color from the sequence. - } else if (tick_diff < (EXCEPTION_TYPE_LENGTH_MS * 2 + LINE_NUMBER_TOGGLE_LENGTH * digit_sum)) { - uint32_t digit_diff = tick_diff - EXCEPTION_TYPE_LENGTH_MS * 2; - if ((digit_diff % LINE_NUMBER_TOGGLE_LENGTH) < (LINE_NUMBER_TOGGLE_LENGTH / 2)) { - new_status_color(BLACK); - } else if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * thousands) { - if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH) { - new_status_color(BLACK); - } else { - new_status_color(THOUSANDS); - } - } else if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds)) { - if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + 1)) { - new_status_color(BLACK); - } else { - new_status_color(HUNDREDS); - } - } else if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds + tens)) { - if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds + 1)) { - new_status_color(BLACK); - } else { - new_status_color(TENS); - } - } else { - if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds + tens + 1)) { - new_status_color(BLACK); - } else { - new_status_color(ONES); - } - } - } else { - new_status_color(BLACK); - } - } - #else - (void) found_main; // Pretend to use found_main so the compiler doesn't complain. - #endif - } -} - -#ifdef UART_REPL -struct usart_module usart_instance; -#endif - -#ifdef ENABLE_MICRO_TRACE_BUFFER -// Stores 2 ^ TRACE_BUFFER_MAGNITUDE_PACKETS packets. -// 7 -> 128 packets -#define TRACE_BUFFER_MAGNITUDE_PACKETS 7 -// Size in uint32_t. Two per packet. -#define TRACE_BUFFER_SIZE (1 << (TRACE_BUFFER_MAGNITUDE_PACKETS + 1)) -// Size in bytes. 4 bytes per uint32_t. -#define TRACE_BUFFER_SIZE_BYTES (TRACE_BUFFER_SIZE << 2) -__attribute__((__aligned__(TRACE_BUFFER_SIZE_BYTES))) uint32_t mtb[TRACE_BUFFER_SIZE]; -#endif - -// Serial number as hex characters. -char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; -void load_serial_number(void) { - char nibble_to_hex[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', - 'B', 'C', 'D', 'E', 'F'}; - uint32_t* addresses[4] = {(uint32_t *) 0x0080A00C, (uint32_t *) 0x0080A040, - (uint32_t *) 0x0080A044, (uint32_t *) 0x0080A048}; - for (int i = 0; i < 4; i++) { - for (int j = 0; j < 8; j++) { - uint8_t nibble = (*(addresses[i]) >> j * 4) & 0xf; - serial_number[i * 8 + j] = nibble_to_hex[nibble]; - } - } -} - -// Provided by the linker; -extern uint32_t _ezero; - -safe_mode_t samd21_init(void) { -#ifdef ENABLE_MICRO_TRACE_BUFFER - REG_MTB_POSITION = ((uint32_t) (mtb - REG_MTB_BASE)) & 0xFFFFFFF8; - REG_MTB_FLOW = (((uint32_t) mtb - REG_MTB_BASE) + TRACE_BUFFER_SIZE_BYTES) & 0xFFFFFFF8; - REG_MTB_MASTER = 0x80000000 + (TRACE_BUFFER_MAGNITUDE_PACKETS - 1); -#else - // Triple check that the MTB is off. Switching between debug and non-debug - // builds can leave it set over reset and wreak havok as a result. - REG_MTB_MASTER = 0x00000000 + 6; -#endif - -// On power on start or external reset, set _ezero to the canary word. If it -// gets killed, we boot in safe mod. _ezero is the boundary between statically -// allocated memory including the fixed MicroPython heap and the stack. If either -// misbehaves, the canary will not be in tact after soft reset. -#ifdef CIRCUITPY_CANARY_WORD - if (PM->RCAUSE.bit.POR == 1 || PM->RCAUSE.bit.EXT == 1) { - _ezero = CIRCUITPY_CANARY_WORD; - } else if (PM->RCAUSE.bit.SYST == 1) { - // If we're starting from a system reset we're likely coming from the - // bootloader or hard fault handler. If we're coming from the handler - // the canary will be CIRCUITPY_SAFE_RESTART_WORD and we don't want to - // revive the canary so that a second hard fault won't restart. Resets - // from anywhere else are ok. - if (_ezero == CIRCUITPY_SAFE_RESTART_WORD) { - _ezero = ~CIRCUITPY_CANARY_WORD; - } else { - _ezero = CIRCUITPY_CANARY_WORD; - } - } -#endif - - load_serial_number(); - - irq_initialize_vectors(); - cpu_irq_enable(); - - // Initialize the sleep manager - sleepmgr_init(); - - uint16_t dfll_fine_calibration = 0x1ff; -#ifdef CALIBRATE_CRYSTALLESS - // This is stored in an NVM page after the text and data storage but before - // the optional file system. The first 16 bytes are the identifier for the - // section. - if (strcmp((char*) INTERNAL_CIRCUITPY_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) { - dfll_fine_calibration = ((uint16_t *) INTERNAL_CIRCUITPY_CONFIG_START_ADDR)[8]; - } -#endif - - // We pass in the DFLL fine calibration because we can't change it once the - // clock is going. - system_init(dfll_fine_calibration); - - delay_init(); - - board_init(); - - // Configure millisecond timer initialization. - tick_init(); - - // Uncomment to init PIN_PA17 for debugging. - // struct port_config pin_conf; - // port_get_config_defaults(&pin_conf); - // - // pin_conf.direction = PORT_PIN_DIR_OUTPUT; - // port_pin_set_config(MICROPY_HW_LED1, &pin_conf); - // port_pin_set_output_level(MICROPY_HW_LED1, false); - - rgb_led_status_init(); - - // Init the nvm controller. - struct nvm_config config_nvm; - nvm_get_config_defaults(&config_nvm); - config_nvm.manual_page_write = false; - nvm_set_config(&config_nvm); - - init_shared_dma(); - - #ifdef CIRCUITPY_CANARY_WORD - // Run in safe mode if the canary is corrupt. - if (_ezero != CIRCUITPY_CANARY_WORD) { - return HARD_CRASH; - } - #endif - - if (PM->RCAUSE.bit.BOD33 == 1 || PM->RCAUSE.bit.BOD12 == 1) { - return BROWNOUT; - } - - if (board_requests_safe_mode()) { - return USER_SAFE_MODE; - } - - #if CIRCUITPY_INTERNAL_NVM_SIZE > 0 - // Upgrade the nvm flash to include one sector for eeprom emulation. - struct nvm_fusebits fuses; - if (nvm_get_fuses(&fuses) == STATUS_OK && - fuses.eeprom_size == NVM_EEPROM_EMULATOR_SIZE_0) { - #ifdef INTERNAL_FLASH_FS - // Shift the internal file system up one row. - for (uint8_t row = 0; row < TOTAL_INTERNAL_FLASH_SIZE / NVMCTRL_ROW_SIZE; row++) { - uint32_t new_row_address = INTERNAL_FLASH_MEM_SEG1_START_ADDR + row * NVMCTRL_ROW_SIZE; - nvm_erase_row(new_row_address); - nvm_write_buffer(new_row_address, - (uint8_t*) (new_row_address + CIRCUITPY_INTERNAL_EEPROM_SIZE), - NVMCTRL_ROW_SIZE); - } - #endif - uint32_t nvm_size = CIRCUITPY_INTERNAL_NVM_SIZE; - uint8_t enum_value = 6; - while (nvm_size > 256 && enum_value != 255) { - nvm_size /= 2; - enum_value -= 1; - } - if (enum_value != 255 && nvm_size == 256) { - // Mark the last section as eeprom now. - fuses.eeprom_size = (enum nvm_eeprom_emulator_size) enum_value; - nvm_set_fuses(&fuses); - } - } - #endif - - return NO_SAFE_MODE; -} - -extern uint32_t _estack; -extern uint32_t _ebss; - -int main(void) { - // initialise the cpu and peripherals - safe_mode_t safe_mode = samd21_init(); - - // Stack limit should be less than real stack size, so we have a chance - // to recover from limit hit. (Limit is measured in bytes.) - mp_stack_ctrl_init(); - mp_stack_set_limit((char*)&_estack - (char*)&_ebss - 1024); - - -#if MICROPY_MAX_STACK_USAGE - // _ezero (same as _ebss) is an int, so start 4 bytes above it. - mp_stack_set_bottom(&_ezero + 1); - mp_stack_fill_with_sentinel(); -#endif - - init_flash_fs(); - - // Reset everything and prep MicroPython to run boot.py. - reset_samd21(); - reset_board(); - reset_mp(); - - // Turn on autoreload by default but before boot.py in case it wants to change it. - autoreload_enable(); - - // By default our internal flash is readonly to local python code and - // writeable over USB. Set it here so that boot.py can change it. - flash_set_usb_writeable(true); - - // If not in safe mode, run boot before initing USB and capture output in a - // file. - if (safe_mode == NO_SAFE_MODE && MP_STATE_VM(vfs_mount_table) != NULL) { - new_status_color(BOOT_RUNNING); - #ifdef CIRCUITPY_BOOT_OUTPUT_FILE - // Since USB isn't up yet we can cheat and let ourselves write the boot - // output file. - flash_set_usb_writeable(false); - FIL file_pointer; - boot_output_file = &file_pointer; - f_open(&((fs_user_mount_t *) MP_STATE_VM(vfs_mount_table)->obj)->fatfs, - boot_output_file, CIRCUITPY_BOOT_OUTPUT_FILE, FA_WRITE | FA_CREATE_ALWAYS); - flash_set_usb_writeable(true); - #endif - - // TODO(tannewt): Re-add support for flashing boot error output. - bool found_boot = maybe_run("settings.txt", NULL) || - maybe_run("settings.py", NULL) || - maybe_run("boot.py", NULL) || - maybe_run("boot.txt", NULL); - (void) found_boot; - - #ifdef CIRCUITPY_BOOT_OUTPUT_FILE - f_close(boot_output_file); - flash_flush(); - boot_output_file = NULL; - #endif - - // Reset to remove any state that boot.py setup. It should only be used to - // change internal state thats not in the heap. - reset_samd21(); - reset_mp(); - } - - usb_hid_init(); - - // Start USB after getting everything going. - #ifdef USB_REPL - udc_start(); - #endif - - // Boot script is finished, so now go into REPL/main mode. - int exit_code = PYEXEC_FORCED_EXIT; - bool skip_repl = true; - bool first_run = true; - for (;;) { - if (!skip_repl) { - // The REPL mode can change, or it can request a reload. - bool autoreload_on = autoreload_is_enabled(); - autoreload_disable(); - new_status_color(REPL_RUNNING); - if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) { - exit_code = pyexec_raw_repl(); - } else { - exit_code = pyexec_friendly_repl(); - } - if (autoreload_on) { - autoreload_enable(); - } - reset_samd21(); - reset_board(); - reset_mp(); - } - if (exit_code == PYEXEC_FORCED_EXIT) { - if (!first_run) { - mp_hal_stdout_tx_str("soft reboot\r\n"); - } - first_run = false; - skip_repl = start_mp(safe_mode); - reset_samd21(); - reset_board(); - reset_mp(); - } else if (exit_code != 0) { - break; - } - } - mp_deinit(); - return 0; -} - -void gc_collect(void) { - // WARNING: This gc_collect implementation doesn't try to get root - // pointers from CPU registers, and thus may function incorrectly. - void *dummy; - gc_collect_start(); - // This collects root pointers from the VFS mount table. Some of them may - // have lost their references in the VM even though they are mounted. - gc_collect_root((void**)&MP_STATE_VM(vfs_mount_table), sizeof(mp_vfs_mount_t) / sizeof(mp_uint_t)); - // This naively collects all object references from an approximate stack - // range. - gc_collect_root(&dummy, ((mp_uint_t)&_estack - (mp_uint_t)&dummy) / sizeof(mp_uint_t)); - gc_collect_end(); -} - -void NORETURN nlr_jump_fail(void *val) { - HardFault_Handler(); - while (true) {} -} - -void NORETURN __fatal_error(const char *msg) { - HardFault_Handler(); - while (true) {} -} - -#ifndef NDEBUG -void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) { - printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line); - __fatal_error("Assertion failed"); -} -#endif diff --git a/atmel-samd/mpconfigport.h b/atmel-samd/mpconfigport.h index e99d190be5ca5..96c0acd0030b5 100644 --- a/atmel-samd/mpconfigport.h +++ b/atmel-samd/mpconfigport.h @@ -3,6 +3,8 @@ #ifndef __INCLUDED_MPCONFIGPORT_H #define __INCLUDED_MPCONFIGPORT_H +#define PORT_HEAP_SIZE (16384 + 4096) + #define MICROPY_PY_SYS_PLATFORM "Atmel SAMD21" #define MICROPY_OBJ_REPR (MICROPY_OBJ_REPR_C) @@ -132,6 +134,15 @@ typedef long mp_off_t; // board specific definitions #include "mpconfigboard.h" +#include "include/sam.h" + +#ifdef SAMD21 +#define CIRCUITPY_MCU_FAMILY samd21 +#endif + +#ifdef SAMD51 +#define CIRCUITPY_MCU_FAMILY samd51 +#endif // extra built in modules to add to the list of known ones extern const struct _mp_obj_module_t microcontroller_module; @@ -172,12 +183,11 @@ extern const struct _mp_obj_module_t usb_hid_module; #define MICROPY_PY_SYS_MAXSIZE (1) #define MICROPY_CPYTHON_COMPAT (1) - #define EXTRA_BUILTIN_MODULES \ - { MP_OBJ_NEW_QSTR(MP_QSTR_audioio), (mp_obj_t)&audioio_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_audiobusio), (mp_obj_t)&audiobusio_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_nvm), (mp_obj_t)&cpy_nvm_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_pulseio), (mp_obj_t)&pulseio_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_bitbangio), (mp_obj_t)&bitbangio_module } + #define EXTRA_BUILTIN_MODULES +// { MP_OBJ_NEW_QSTR(MP_QSTR_audioio), (mp_obj_t)&audioio_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_audiobusio), (mp_obj_t)&audiobusio_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_pulseio), (mp_obj_t)&pulseio_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_bitbangio), (mp_obj_t)&bitbangio_module } #define EXPRESS_BOARD #else #define MICROPY_PY_BUILTINS_REVERSED (0) @@ -189,30 +199,29 @@ extern const struct _mp_obj_module_t usb_hid_module; #define MICROPY_CPYTHON_COMPAT (0) #endif +// Disabled for now. +// { MP_OBJ_NEW_QSTR(MP_QSTR_touchio), (mp_obj_t)&touchio_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_analogio), (mp_obj_t)&analogio_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_busio), (mp_obj_t)&busio_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&time_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_neopixel_write),(mp_obj_t)&neopixel_write_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_usb_hid),(mp_obj_t)&usb_hid_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_os), (mp_obj_t)&os_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_random), (mp_obj_t)&random_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_storage), (mp_obj_t)&storage_module }, +// { MP_OBJ_NEW_QSTR(MP_QSTR_samd),(mp_obj_t)&samd_module }, + + #define MICROPY_PORT_BUILTIN_MODULES \ - { MP_OBJ_NEW_QSTR(MP_QSTR_touchio), (mp_obj_t)&touchio_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_microcontroller), (mp_obj_t)µcontroller_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_analogio), (mp_obj_t)&analogio_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_digitalio), (mp_obj_t)&digitalio_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_busio), (mp_obj_t)&busio_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_board), (mp_obj_t)&board_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_os), (mp_obj_t)&os_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_random), (mp_obj_t)&random_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_storage), (mp_obj_t)&storage_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_time), (mp_obj_t)&time_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_neopixel_write),(mp_obj_t)&neopixel_write_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_samd),(mp_obj_t)&samd_module }, \ - { MP_OBJ_NEW_QSTR(MP_QSTR_usb_hid),(mp_obj_t)&usb_hid_module }, \ EXTRA_BUILTIN_MODULES #define MICROPY_PORT_BUILTIN_DEBUG_MODULES \ { MP_OBJ_NEW_QSTR(MP_QSTR_uheap),(mp_obj_t)&uheap_module }, \ { MP_OBJ_NEW_QSTR(MP_QSTR_ustack),(mp_obj_t)&ustack_module } -#ifndef MICROPY_PIN_DEFS_PORT_H -#define MICROPY_PIN_DEFS_PORT_H "pins.h" -#endif - // We need to provide a declaration/definition of alloca() #include diff --git a/atmel-samd/mphalport.c b/atmel-samd/mphalport.c index c1aebe08a4c08..dc23c7190bbc9 100644 --- a/atmel-samd/mphalport.c +++ b/atmel-samd/mphalport.c @@ -1,51 +1,35 @@ #include -#include "autoreload.h" -#include "compiler.h" -#include "asf/common/services/sleepmgr/sleepmgr.h" -#include "asf/common/services/usb/class/cdc/device/udi_cdc.h" -#include "asf/common2/services/delay/delay.h" -#include "asf/sam0/drivers/port/port.h" -#include "asf/sam0/drivers/sercom/usart/usart.h" #include "lib/mp-readline/readline.h" #include "lib/utils/interrupt_char.h" #include "py/mphal.h" #include "py/mpstate.h" #include "py/runtime.h" #include "py/smallint.h" +#include "shared-bindings/microcontroller/__init__.h" #include "shared-bindings/time/__init__.h" +#include "supervisor/shared/autoreload.h" + +#include "hal/include/hal_atomic.h" +#include "hal/include/hal_delay.h" +#include "hal/include/hal_gpio.h" +#include "hal/include/hal_sleep.h" #include "mpconfigboard.h" #include "mphalport.h" - -// Store received characters on our own so that we can filter control characters -// and act immediately on CTRL-C for example. -// This is adapted from asf/thirdparty/wireless/addons/sio2host - -// Receive buffer -static uint8_t usb_rx_buf[USB_RX_BUF_SIZE]; - -// Receive buffer head -static volatile uint8_t usb_rx_buf_head; - -// Receive buffer tail -static volatile uint8_t usb_rx_buf_tail; - -// Number of bytes in receive buffer -volatile uint8_t usb_rx_count; - -volatile bool mp_cdc_enabled = false; +#include "reset.h" +#include "usb.h" extern struct usart_module usart_instance; // Read by main to know when USB is connected. volatile bool mp_msc_enabled = false; -bool mp_msc_enable() { +bool mp_msc_enable(void) { mp_msc_enabled = true; return true; } -void mp_msc_disable() { +void mp_msc_disable(void) { mp_msc_enabled = false; } @@ -71,165 +55,33 @@ void usb_rts_notify(uint8_t port, bool set) { return; } -void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding) { - reset_on_disconnect = coding->dwDTERate == 1200; -} - -void usb_rx_notify(void) { - irqflags_t flags; - if (mp_cdc_enabled) { - while (udi_cdc_is_rx_ready()) { - uint8_t c; - - // Introduce a critical section to avoid buffer corruption. We use - // cpu_irq_save instead of cpu_irq_disable because we don't know the - // current state of IRQs. They may have been turned off already and - // we don't want to accidentally turn them back on. - flags = cpu_irq_save(); - // If our buffer is full, then don't get another character otherwise - // we'll lose a previous character. - if (usb_rx_count >= USB_RX_BUF_SIZE) { - cpu_irq_restore(flags); - break; - } - - uint8_t current_tail = usb_rx_buf_tail; - // Pretend we've received a character so that any nested calls to - // this function have to consider the spot we've reserved. - if ((USB_RX_BUF_SIZE - 1) == usb_rx_buf_tail) { - // Reached the end of buffer, revert back to beginning of - // buffer. - usb_rx_buf_tail = 0x00; - } else { - usb_rx_buf_tail++; - } - // The count of characters present in receive buffer is - // incremented. - usb_rx_count++; - // WARNING(tannewt): This call can call us back with the next - // character! - c = udi_cdc_getc(); - - if (c == mp_interrupt_char) { - // We consumed a character rather than adding it to the rx - // buffer so undo the modifications we made to count and the - // tail. - usb_rx_count--; - usb_rx_buf_tail = current_tail; - cpu_irq_restore(flags); - mp_keyboard_interrupt(); - // Don't put the interrupt into the buffer, just continue. - continue; - } - - // We put the next character where we expected regardless of whether - // the next character was already loaded in the buffer. - usb_rx_buf[current_tail] = c; - - cpu_irq_restore(flags); - } - } -} - -int receive_usb(void) { - if (usb_rx_count == 0) { - return 0; - } - - // Copy from head. - cpu_irq_disable(); - int data = usb_rx_buf[usb_rx_buf_head]; - usb_rx_buf_head++; - usb_rx_count--; - if ((USB_RX_BUF_SIZE) == usb_rx_buf_head) { - usb_rx_buf_head = 0; - } - cpu_irq_enable(); - - // Call usb_rx_notify if we just emptied a spot in the buffer. - if (usb_rx_count == USB_RX_BUF_SIZE - 1) { - usb_rx_notify(); - } - return data; -} +// void usb_coding_notify(uint8_t port, usb_cdc_line_coding_t* coding) { +// reset_on_disconnect = coding->dwDTERate == 1200; +// } int mp_hal_stdin_rx_chr(void) { for (;;) { #ifdef MICROPY_VM_HOOK_LOOP MICROPY_VM_HOOK_LOOP #endif - // Check to see if we've been CTRL-Ced by autoreload or the user. Raise the exception if so. - if(MP_STATE_VM(mp_pending_exception) == MP_OBJ_FROM_PTR(&MP_STATE_VM(mp_kbd_exception))) { - mp_handle_pending(); - } - - #ifdef USB_REPL - if (reload_next_character) { - return CHAR_CTRL_D; - } - if (usb_rx_count > 0) { + // if (reload_next_character) { + // return CHAR_CTRL_D; + // } + if (usb_bytes_available()) { #ifdef MICROPY_HW_LED_RX - port_pin_toggle_output_level(MICROPY_HW_LED_RX); + gpio_toggle_pin_level(MICROPY_HW_LED_RX); #endif - return receive_usb(); + return usb_read(); } - #endif - #ifdef UART_REPL - uint16_t temp; - if (usart_read_wait(&usart_instance, &temp) == STATUS_OK) { - #ifdef MICROPY_HW_LED_RX - port_pin_toggle_output_level(MICROPY_HW_LED_RX); - #endif - return temp; - } - #endif - // TODO(tannewt): Switch to callback/interrupt based UART so it can work - // with the sleepmgr. - sleepmgr_enter_sleep(); } } void mp_hal_stdout_tx_strn(const char *str, size_t len) { #ifdef MICROPY_HW_LED_TX - port_pin_toggle_output_level(MICROPY_HW_LED_TX); + gpio_toggle_pin_level(MICROPY_HW_LED_TX); #endif - #ifdef UART_REPL - usart_write_buffer_wait(&usart_instance, (uint8_t*) str, len); - #endif - - #ifdef CIRCUITPY_BOOT_OUTPUT_FILE - if (boot_output_file != NULL) { - UINT bytes_written = 0; - f_write(boot_output_file, str, len, &bytes_written); - } - #endif - - #ifdef USB_REPL - // Always make sure there is enough room in the usb buffer for the outgoing - // string. If there isn't we risk getting caught in a loop within the usb - // code as it tries to send all the characters it can't buffer. - uint32_t start = 0; - uint64_t start_tick = common_hal_time_monotonic(); - uint64_t duration = 0; - if (mp_cdc_enabled) { - while (start < len && duration < 10) { - uint8_t buffer_space = udi_cdc_get_free_tx_buffer(); - uint8_t transmit = min(len - start, buffer_space); - if (transmit > 0) { - if (udi_cdc_write_buf(str + start, transmit) > 0) { - // It didn't transmit successfully so give up. - break; - } - } - start += transmit; - #ifdef MICROPY_VM_HOOK_LOOP - MICROPY_VM_HOOK_LOOP - #endif - duration = (common_hal_time_monotonic() - start_tick); - } - } - #endif + usb_write(str, len); } void mp_hal_delay_ms(mp_uint_t delay) { @@ -252,18 +104,10 @@ void mp_hal_delay_us(mp_uint_t delay) { delay_us(delay); } -// Interrupt flags that will be saved and restored during disable/Enable -// interrupt functions below. -static irqflags_t irq_flags; - void mp_hal_disable_all_interrupts(void) { - // Disable all interrupt sources for timing critical sections. - // Disable ASF-based interrupts. - irq_flags = cpu_irq_save(); + common_hal_mcu_disable_interrupts(); } void mp_hal_enable_all_interrupts(void) { - // Enable all interrupt sources after timing critical sections. - // Restore ASF-based interrupts. - cpu_irq_restore(irq_flags); + common_hal_mcu_enable_interrupts(); } diff --git a/atmel-samd/mphalport.h b/atmel-samd/mphalport.h index 939bbf64a8ca0..3b5955a4ffc65 100644 --- a/atmel-samd/mphalport.h +++ b/atmel-samd/mphalport.h @@ -31,8 +31,6 @@ #include "lib/oofatfs/ff.h" -#define USB_RX_BUF_SIZE 128 - // Global millisecond tick count (driven by SysTick interrupt). extern volatile uint64_t ticks_ms; diff --git a/atmel-samd/pins.h b/atmel-samd/pins.h new file mode 100644 index 0000000000000..5c9a36a4e4da0 --- /dev/null +++ b/atmel-samd/pins.h @@ -0,0 +1,39 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __MICROPY_INCLUDED_ATMEL_SAMD_PINS_H__ +#define __MICROPY_INCLUDED_ATMEL_SAMD_PINS_H__ + +#include "mpconfigport.h" + +#ifdef SAMD21 +#include "samd21_pins.h" +#endif +#ifdef SAMD51 +#include "samd51_pins.h" +#endif + +#endif // __MICROPY_INCLUDED_ATMEL_SAMD_PINS_H__ diff --git a/atmel-samd/reset.c b/atmel-samd/reset.c index 442774a5f4b70..0aef56d4c14a6 100644 --- a/atmel-samd/reset.c +++ b/atmel-samd/reset.c @@ -27,10 +27,16 @@ #include "flash_api.h" #include "reset.h" -#include "asf/sam0/utils/cmsis/samd21/include/samd21.h" +#include "include/sam.h" // Copied from inc/uf2.h in https://github.com/Microsoft/uf2-samd21 +#ifdef SAMD21 #define DBL_TAP_PTR ((volatile uint32_t *)(HMCRAMC0_ADDR + HMCRAMC0_SIZE - 4)) +#else + #ifdef SAMD51 + #define DBL_TAP_PTR ((volatile uint32_t *)(HSRAM_ADDR + HSRAM_SIZE - 4)) + #endif +#endif #define DBL_TAP_MAGIC 0xf01669ef // Randomly selected, adjusted to have first and last bit set void reset_to_bootloader(void) { diff --git a/atmel-samd/rgb_led_status.c b/atmel-samd/rgb_led_status.c deleted file mode 100644 index 83d3f9916b581..0000000000000 --- a/atmel-samd/rgb_led_status.c +++ /dev/null @@ -1,178 +0,0 @@ -#include "asf/common2/services/delay/delay.h" -#include "asf/sam0/drivers/port/port.h" - -#include "mphalport.h" - -#include "common-hal/microcontroller/Pin.h" -#include "shared-bindings/bitbangio/SPI.h" -#include "shared-bindings/busio/SPI.h" -#include "shared-bindings/digitalio/DigitalInOut.h" -#include "shared-bindings/neopixel_write/__init__.h" -#include "shared-module/bitbangio/types.h" -#include "rgb_led_status.h" -#include "samd21_pins.h" - -uint8_t rgb_status_brightness = 255; -#ifdef MICROPY_HW_NEOPIXEL -static uint8_t status_neopixel_color[3]; -static digitalio_digitalinout_obj_t status_neopixel; -#endif - - -#if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) -static uint8_t status_apa102_color[12] = {0, 0, 0, 0, 0xff, 0, 0, 0}; -#ifdef CIRCUITPY_BITBANG_APA102 -static bitbangio_spi_obj_t status_apa102; -#else -busio_spi_obj_t status_apa102; -#endif -#endif - -#if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) -static uint32_t current_status_color = 0; -#endif - - -void rgb_led_status_init() { - #ifdef MICROPY_HW_NEOPIXEL - common_hal_digitalio_digitalinout_construct(&status_neopixel, MICROPY_HW_NEOPIXEL); - // Pretend we aren't using the pins. digitalio.DigitalInOut - // will mark them as used. - neopixel_in_use = false; - common_hal_digitalio_digitalinout_switch_to_output(&status_neopixel, false, DRIVE_MODE_PUSH_PULL); - #endif - #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) - #ifdef CIRCUITPY_BITBANG_APA102 - shared_module_bitbangio_spi_construct(&status_apa102, - MICROPY_HW_APA102_SCK, - MICROPY_HW_APA102_MOSI, - mp_const_none); - #else - if (status_apa102.current_baudrate > 0) { - // Don't use spi_deinit because that leads to infinite - // recursion because reset_pin may call - // rgb_led_status_init. - spi_disable(&status_apa102.spi_master_instance); - } - common_hal_busio_spi_construct(&status_apa102, - MICROPY_HW_APA102_SCK, - MICROPY_HW_APA102_MOSI, - mp_const_none); - #endif - // Pretend we aren't using the pins. bitbangio.SPI will - // mark them as used. - apa102_mosi_in_use = false; - apa102_sck_in_use = false; - #ifdef CIRCUITPY_BITBANG_APA102 - shared_module_bitbangio_spi_try_lock(&status_apa102); - shared_module_bitbangio_spi_configure(&status_apa102, 100000, 0, 1, 8); - #else - common_hal_busio_spi_try_lock(&status_apa102); - common_hal_busio_spi_configure(&status_apa102, 100000, 0, 1, 8); - #endif - #endif - - #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) - // Force a write of the current status color. - uint32_t rgb = current_status_color; - current_status_color = 0; - new_status_color(rgb); - #endif -} - -void reset_status_led() { - #ifdef MICROPY_HW_NEOPIXEL - reset_pin(MICROPY_HW_NEOPIXEL->pin); - #endif - #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) - reset_pin(MICROPY_HW_APA102_MOSI->pin); - reset_pin(MICROPY_HW_APA102_SCK->pin); - #endif -} - -void new_status_color(uint32_t rgb) { - #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) - if (current_status_color == rgb) { - return; - } - uint32_t rgb_adjusted = color_brightness(rgb, rgb_status_brightness); - current_status_color = rgb_adjusted; - #endif - - #ifdef MICROPY_HW_NEOPIXEL - if (neopixel_in_use) { - return; - } - status_neopixel_color[0] = (rgb_adjusted >> 8) & 0xff; - status_neopixel_color[1] = (rgb_adjusted >> 16) & 0xff; - status_neopixel_color[2] = rgb_adjusted & 0xff; - common_hal_neopixel_write(&status_neopixel, status_neopixel_color, 3); - #endif - #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) - if (apa102_mosi_in_use || apa102_sck_in_use) { - return; - } - status_apa102_color[5] = rgb_adjusted & 0xff; - status_apa102_color[6] = (rgb_adjusted >> 8) & 0xff; - status_apa102_color[7] = (rgb_adjusted >> 16) & 0xff; - - #ifdef CIRCUITPY_BITBANG_APA102 - shared_module_bitbangio_spi_write(&status_apa102, status_apa102_color, 8); - #else - common_hal_busio_spi_write(&status_apa102, status_apa102_color, 8); - #endif - #endif -} - -void temp_status_color(uint32_t rgb) { - #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) - uint32_t rgb_adjusted = rgb; - rgb_adjusted = color_brightness(rgb, rgb_status_brightness); - #endif - #ifdef MICROPY_HW_NEOPIXEL - if (neopixel_in_use) { - return; - } - uint8_t colors[3] = {(rgb_adjusted >> 8) & 0xff, (rgb_adjusted >> 16) & 0xff, rgb_adjusted & 0xff}; - common_hal_neopixel_write(&status_neopixel, colors, 3); - #endif - #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) - if (apa102_mosi_in_use || apa102_sck_in_use) { - return; - } - uint8_t colors[12] = {0, 0, 0, 0, 0xff, rgb_adjusted & 0xff, (rgb_adjusted >> 8) & 0xff, (rgb_adjusted >> 16) & 0xff, 0x0, 0x0, 0x0, 0x0}; - #ifdef CIRCUITPY_BITBANG_APA102 - shared_module_bitbangio_spi_write(&status_apa102, colors, 12); - #else - common_hal_busio_spi_write(&status_apa102, colors, 12); - #endif - #endif -} - -void clear_temp_status() { - #ifdef MICROPY_HW_NEOPIXEL - common_hal_neopixel_write(&status_neopixel, status_neopixel_color, 3); - #endif - #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) - #ifdef CIRCUITPY_BITBANG_APA102 - shared_module_bitbangio_spi_write(&status_apa102, status_apa102_color, 8); - #else - common_hal_busio_spi_write(&status_apa102, status_apa102_color, 8); - #endif - #endif -} - -uint32_t color_brightness(uint32_t color, uint8_t brightness) { - #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) - uint32_t result = ((color & 0xff0000) * brightness / 255) & 0xff0000; - result += ((color & 0xff00) * brightness / 255) & 0xff00; - result += ((color & 0xff) * brightness / 255) & 0xff; - return result; - #else - return color; - #endif -} - -void set_rgb_status_brightness(uint8_t level){ - rgb_status_brightness = level; -} diff --git a/atmel-samd/rgb_led_status.h b/atmel-samd/rgb_led_status.h deleted file mode 100644 index 35bebda858bf7..0000000000000 --- a/atmel-samd/rgb_led_status.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the MicroPython project, http://micropython.org/ - * - * The MIT License (MIT) - * - * Copyright (c) 2013, 2014 Damien P. George - * Copyright (c) 2014 Paul Sokolovsky - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#ifndef MICROPY_INCLUDED_ATMEL_SAMD_RGB_LED_STATUS_H -#define MICROPY_INCLUDED_ATMEL_SAMD_RGB_LED_STATUS_H - -#include -#include - -#include "mpconfigport.h" -#include "rgb_led_colors.h" - -#if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) && !defined(CIRCUITPY_BITBANG_APA102) -#include "common-hal/busio/SPI.h" -extern busio_spi_obj_t status_apa102; -#endif - -void rgb_led_status_init(void); -void reset_status_led(void); -void new_status_color(uint32_t rgb); -void temp_status_color(uint32_t rgb); -void clear_temp_status(void); - -uint32_t color_brightness(uint32_t color, uint8_t brightness); -void set_rgb_status_brightness(uint8_t level); - -#endif // MICROPY_INCLUDED_ATMEL_SAMD_RGB_LED_STATUS_H diff --git a/atmel-samd/samd21_pins.c b/atmel-samd/samd21_pins.c index cd66b41ee7d57..2b151e7b3d679 100644 --- a/atmel-samd/samd21_pins.c +++ b/atmel-samd/samd21_pins.c @@ -1,3 +1,29 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + #include "shared-bindings/microcontroller/Pin.h" #include "samd21_pins.h" @@ -10,23 +36,21 @@ #define NO_SERCOM SERCOM(0, 0) -#define TCC(p_tcc, p_channel, p_wave_output) \ +#define TCC(p_tcc, p_wave_output) \ { \ .tcc = p_tcc, \ .is_tc = false, \ - .channel = p_channel, \ .wave_output = p_wave_output \ } -#define TC(p_tc, p_channel, p_wave_output) \ +#define TC(p_tc, p_wave_output) \ { \ .tc = p_tc, \ .is_tc = true, \ - .channel = p_channel, \ .wave_output = p_wave_output \ } -#define NO_TIMER TCC(0, 0, 0) +#define NO_TIMER TCC(0, 0) #define TOUCH(y_line) \ .has_touch = true, \ @@ -42,25 +66,22 @@ #define NO_EXTINT \ .has_extint = false, -#define ADC_INPUT(input) \ - .has_adc = true, \ - .adc_input = input, +#define ADC_INPUT(input) input -#define NO_ADC \ - .has_adc = false, +#define NO_ADC 0xff // This macro is used to simplify pin definition in boards//pins.c -#define PIN(p_name, p_adc, p_extint, p_touch, p_primary_timer, \ - p_secondary_timer, p_primary_sercom, p_secondary_sercom) \ +#define PIN(p_name, p_extint, p_adc, p_touch, \ + p_primary_sercom, p_secondary_sercom, \ + p_primary_timer, p_secondary_timer) \ const mcu_pin_obj_t pin_## p_name = { \ { &mcu_pin_type }, \ - .name = MP_QSTR_ ## p_name, \ + .name = MP_QSTR_## p_name, \ .pin = (PIN_## p_name), \ p_extint \ - p_adc \ p_touch \ - .primary_timer = p_primary_timer, \ - .secondary_timer = p_secondary_timer, \ + .adc_input = {p_adc}, \ + .timer = { p_primary_timer, p_secondary_timer}, \ .sercom = {p_primary_sercom, p_secondary_sercom}, \ } @@ -71,437 +92,431 @@ const mcu_pin_obj_t pin_## p_name = { \ // used to vary the 16 bit timer's frequency. #ifdef PIN_PA00 PIN(PA00, EXTINT_CHANNEL(0), NO_ADC, NO_TOUCH, - TCC(TCC2, 0, 0), - NO_TIMER, NO_SERCOM, - SERCOM(SERCOM1, 0)); + SERCOM(SERCOM1, 0), + TCC(TCC2, 0), + NO_TIMER); #endif #ifdef PIN_PA01 PIN(PA01, EXTINT_CHANNEL(1), NO_ADC, NO_TOUCH, - TCC(TCC2, 1, 1), - NO_TIMER, NO_SERCOM, - SERCOM(SERCOM1, 1)); + SERCOM(SERCOM1, 1), + TCC(TCC2, 1), + NO_TIMER); #endif #ifdef PIN_PA02 -PIN(PA02, EXTINT_CHANNEL(2), ADC_INPUT(ADC_POSITIVE_INPUT_PIN0), TOUCH(0), - NO_TIMER, - NO_TIMER, +PIN(PA02, EXTINT_CHANNEL(2), ADC_INPUT(0), TOUCH(0), + NO_SERCOM, NO_SERCOM, - NO_SERCOM); + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PA03 -PIN(PA03, EXTINT_CHANNEL(3), ADC_INPUT(ADC_POSITIVE_INPUT_PIN1), TOUCH(1), - NO_TIMER, - NO_TIMER, +PIN(PA03, EXTINT_CHANNEL(3), ADC_INPUT(1), TOUCH(1), + NO_SERCOM, NO_SERCOM, - NO_SERCOM); + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PB04 -PIN(PB04, EXTINT_CHANNEL(4), ADC_INPUT(ADC_POSITIVE_INPUT_PIN12), TOUCH(10), - NO_TIMER, - NO_TIMER, +PIN(PB04, EXTINT_CHANNEL(4), ADC_INPUT(12), TOUCH(10), + NO_SERCOM, NO_SERCOM, - NO_SERCOM); + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PB05 -PIN(PB05, EXTINT_CHANNEL(5), ADC_INPUT(ADC_POSITIVE_INPUT_PIN13), TOUCH(11), - NO_TIMER, - NO_TIMER, +PIN(PB05, EXTINT_CHANNEL(5), ADC_INPUT(13), TOUCH(11), + NO_SERCOM, NO_SERCOM, - NO_SERCOM); + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PB06 -PIN(PB06, EXTINT_CHANNEL(6), ADC_INPUT(ADC_POSITIVE_INPUT_PIN14), TOUCH(12), - NO_TIMER, - NO_TIMER, +PIN(PB06, EXTINT_CHANNEL(6), ADC_INPUT(14), TOUCH(12), + NO_SERCOM, NO_SERCOM, - NO_SERCOM); + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PB07 -PIN(PB07, EXTINT_CHANNEL(7), ADC_INPUT(ADC_POSITIVE_INPUT_PIN15), TOUCH(13), - NO_TIMER, - NO_TIMER, +PIN(PB07, EXTINT_CHANNEL(7), ADC_INPUT(15), TOUCH(13), + NO_SERCOM, NO_SERCOM, - NO_SERCOM); + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PB08 -PIN(PB08, EXTINT_CHANNEL(8), ADC_INPUT(ADC_POSITIVE_INPUT_PIN2), TOUCH(14), - NO_TIMER, // TC(TC4, 0, 0), - NO_TIMER, +PIN(PB08, EXTINT_CHANNEL(8), ADC_INPUT(2), TOUCH(14), NO_SERCOM, - SERCOM(SERCOM4, 0)); + SERCOM(SERCOM4, 0), + TC(TC4, 0), + NO_TIMER); #endif #ifdef PIN_PB09 -PIN(PB09, EXTINT_CHANNEL(9), ADC_INPUT(ADC_POSITIVE_INPUT_PIN3), TOUCH(15), - TC(TC4, 1, 1), - NO_TIMER, +PIN(PB09, EXTINT_CHANNEL(9), ADC_INPUT(3), TOUCH(15), NO_SERCOM, - SERCOM(SERCOM4, 1)); + SERCOM(SERCOM4, 1), + TC(TC4, 1), + NO_TIMER); #endif #ifdef PIN_PA04 -PIN(PA04, EXTINT_CHANNEL(4), ADC_INPUT(ADC_POSITIVE_INPUT_PIN4), TOUCH(2), - TCC(TCC0, 0, 0), - NO_TIMER, +PIN(PA04, EXTINT_CHANNEL(4), ADC_INPUT(4), TOUCH(2), NO_SERCOM, - SERCOM(SERCOM0, 0)); + SERCOM(SERCOM0, 0), + TCC(TCC0, 0), + NO_TIMER); #endif #ifdef PIN_PA05 -PIN(PA05, EXTINT_CHANNEL(5), ADC_INPUT(ADC_POSITIVE_INPUT_PIN5), TOUCH(3), - TCC(TCC0, 1, 1), - NO_TIMER, +PIN(PA05, EXTINT_CHANNEL(5), ADC_INPUT(5), TOUCH(3), NO_SERCOM, - SERCOM(SERCOM0, 1)); + SERCOM(SERCOM0, 1), + TCC(TCC0, 1), + NO_TIMER); #endif #ifdef PIN_PA06 -PIN(PA06, EXTINT_CHANNEL(6), ADC_INPUT(ADC_POSITIVE_INPUT_PIN6), TOUCH(4), - TCC(TCC1, 0, 0), - NO_TIMER, +PIN(PA06, EXTINT_CHANNEL(6), ADC_INPUT(6), TOUCH(4), NO_SERCOM, - SERCOM(SERCOM0, 2)); + SERCOM(SERCOM0, 2), + TCC(TCC1, 0), + NO_TIMER); #endif #ifdef PIN_PA07 -PIN(PA07, EXTINT_CHANNEL(7), ADC_INPUT(ADC_POSITIVE_INPUT_PIN7), TOUCH(5), - TCC(TCC1, 1, 1), - NO_TIMER, +PIN(PA07, EXTINT_CHANNEL(7), ADC_INPUT(7), TOUCH(5), NO_SERCOM, - SERCOM(SERCOM0, 3)); + SERCOM(SERCOM0, 3), + TCC(TCC1, 1), + NO_TIMER); #endif #ifdef PIN_PA08 -PIN(PA08, NO_EXTINT, ADC_INPUT(ADC_POSITIVE_INPUT_PIN16), NO_TOUCH, - TCC(TCC0, 0, 0), - TCC(TCC1, 0, 2), +PIN(PA08, NO_EXTINT, ADC_INPUT(16), NO_TOUCH, SERCOM(SERCOM0, 0), - SERCOM(SERCOM2, 0)); + SERCOM(SERCOM2, 0), + TCC(TCC0, 0), + TCC(TCC1, 2)); #endif #ifdef PIN_PA09 -PIN(PA09, EXTINT_CHANNEL(9), ADC_INPUT(ADC_POSITIVE_INPUT_PIN17), NO_TOUCH, - TCC(TCC0, 1, 1), - TCC(TCC1, 1, 3), +PIN(PA09, EXTINT_CHANNEL(9), ADC_INPUT(17), NO_TOUCH, SERCOM(SERCOM0, 1), - SERCOM(SERCOM2, 1)); + SERCOM(SERCOM2, 1), + TCC(TCC0, 1), + TCC(TCC1, 3)); #endif #ifdef PIN_PA10 -PIN(PA10, EXTINT_CHANNEL(10), ADC_INPUT(ADC_POSITIVE_INPUT_PIN18), NO_TOUCH, - TCC(TCC1, 0, 0), - TCC(TCC0, 2, 2), +PIN(PA10, EXTINT_CHANNEL(10), ADC_INPUT(18), NO_TOUCH, SERCOM(SERCOM0, 2), - SERCOM(SERCOM2, 2)); + SERCOM(SERCOM2, 2), + TCC(TCC1, 0), + TCC(TCC0, 2)); #endif #ifdef PIN_PA11 -PIN(PA11, EXTINT_CHANNEL(11), ADC_INPUT(ADC_POSITIVE_INPUT_PIN19), NO_TOUCH, - TCC(TCC1, 1, 1), - TCC(TCC0, 3, 3), +PIN(PA11, EXTINT_CHANNEL(11), ADC_INPUT(19), NO_TOUCH, SERCOM(SERCOM0, 3), - SERCOM(SERCOM2, 3)); + SERCOM(SERCOM2, 3), + TCC(TCC1, 1), + TCC(TCC0, 3)); #endif #ifdef PIN_PB10 PIN(PB10, EXTINT_CHANNEL(10), NO_ADC, NO_TOUCH, - NO_TIMER, // TC(TC5, 0, 0), - TCC(TCC0, 0, 4), NO_SERCOM, - SERCOM(SERCOM4, 2)); + SERCOM(SERCOM4, 2), + TC(TC5, 0), + TCC(TCC0, 4)); #endif #ifdef PIN_PB11 PIN(PB11, EXTINT_CHANNEL(11), NO_ADC, NO_TOUCH, - TC(TC5, 1, 1), - TCC(TCC0, 1, 5), NO_SERCOM, - SERCOM(SERCOM4, 3)); + SERCOM(SERCOM4, 3), + TC(TC5, 1), + TCC(TCC0, 5)); #endif #ifdef PIN_PB12 PIN(PB12, EXTINT_CHANNEL(12), NO_ADC, NO_TOUCH, - NO_TIMER, // TC(TC4, 0, 0), - TCC(TCC0, 2, 6), SERCOM(SERCOM4, 0), - NO_SERCOM); + NO_SERCOM, + TC(TC4, 0), + TCC(TCC0, 6)); #endif #ifdef PIN_PB13 PIN(PB13, EXTINT_CHANNEL(13), NO_ADC, NO_TOUCH, - TC(TC4, 1, 1), - TCC(TCC0, 3, 7), SERCOM(SERCOM4, 1), - NO_SERCOM); + NO_SERCOM, + TC(TC4, 1), + TCC(TCC0, 7)); #endif #ifdef PIN_PB14 PIN(PB14, EXTINT_CHANNEL(14), NO_ADC, NO_TOUCH, - NO_TIMER, // TC(TC5, 0, 0), - NO_TIMER, SERCOM(SERCOM4, 2), - NO_SERCOM); + NO_SERCOM, + TC(TC5, 0), + NO_TIMER); #endif // Second page. #ifdef PIN_PB15 PIN(PB15, EXTINT_CHANNEL(15), NO_ADC, NO_TOUCH, - TC(TC5, 1, 1), - NO_TIMER, SERCOM(SERCOM4, 3), - NO_SERCOM); + NO_SERCOM, + TC(TC5, 1), + NO_TIMER); #endif #ifdef PIN_PA12 PIN(PA12, EXTINT_CHANNEL(12), NO_ADC, NO_TOUCH, - TCC(TCC2, 0, 0), - TCC(TCC0, 2, 6), SERCOM(SERCOM2, 0), - SERCOM(SERCOM4, 0)); + SERCOM(SERCOM4, 0), + TCC(TCC2, 0), + TCC(TCC0, 6)); #endif #ifdef PIN_PA13 PIN(PA13, EXTINT_CHANNEL(13), NO_ADC, NO_TOUCH, - TCC(TCC2, 1, 1), - TCC(TCC0, 3, 7), SERCOM(SERCOM2, 1), - SERCOM(SERCOM4, 1)); + SERCOM(SERCOM4, 1), + TCC(TCC2, 1), + TCC(TCC0, 7)); #endif #ifdef PIN_PA14 PIN(PA14, EXTINT_CHANNEL(14), NO_ADC, NO_TOUCH, - NO_TIMER, // TC(TC3, 0, 0), - TCC(TCC0, 0, 4), SERCOM(SERCOM2, 2), #ifdef SERCOM4 - SERCOM(SERCOM4, 2) + SERCOM(SERCOM4, 2), #else - NO_SERCOM + NO_SERCOM, #endif - ); + TC(TC3, 0), + TCC(TCC0, 4)); #endif #ifdef PIN_PA15 PIN(PA15, EXTINT_CHANNEL(15), NO_ADC, NO_TOUCH, - TC(TC3, 1, 1), - TCC(TCC0, 1, 5), SERCOM(SERCOM2, 3), #ifdef SERCOM4 - SERCOM(SERCOM4, 3) + SERCOM(SERCOM4, 3), #else - NO_SERCOM + NO_SERCOM, #endif - ); + TC(TC3, 1), + TCC(TCC0, 5)); #endif #ifdef PIN_PA16 PIN(PA16, EXTINT_CHANNEL(0), NO_ADC, NO_TOUCH, - TCC(TCC2, 0, 0), - TCC(TCC0, 2, 6), SERCOM(SERCOM1, 0), - SERCOM(SERCOM3, 0)); + SERCOM(SERCOM3, 0), + TCC(TCC2, 0), + TCC(TCC0, 6)); #endif #ifdef PIN_PA17 PIN(PA17, EXTINT_CHANNEL(1), NO_ADC, NO_TOUCH, - TCC(TCC2, 1, 1), - TCC(TCC0, 3, 7), SERCOM(SERCOM1, 1), - SERCOM(SERCOM3, 1)); + SERCOM(SERCOM3, 1), + TCC(TCC2, 1), + TCC(TCC0, 7)); #endif #ifdef PIN_PA18 PIN(PA18, EXTINT_CHANNEL(2), NO_ADC, NO_TOUCH, - NO_TIMER, // TC(TC3, 0, 0), - TCC(TCC0, 2, 2), SERCOM(SERCOM1, 2), - SERCOM(SERCOM3, 2)); + SERCOM(SERCOM3, 2), + TC(TC3, 0), + TCC(TCC0, 2)); #endif #ifdef PIN_PA19 PIN(PA19, EXTINT_CHANNEL(3), NO_ADC, NO_TOUCH, - TC(TC3, 1, 1), - TCC(TCC0, 3, 3), SERCOM(SERCOM1, 3), - SERCOM(SERCOM3, 3)); + SERCOM(SERCOM3, 3), + TC(TC3, 1), + TCC(TCC0, 3)); #endif #ifdef PIN_PB16 PIN(PB16, EXTINT_CHANNEL(0), NO_ADC, NO_TOUCH, - #ifdef _SAMD21_TC6_INSTANCE_ - NO_TIMER, // TC(TC6, 0, 0), + SERCOM(SERCOM5, 0), + NO_SERCOM, + #ifdef TC6 + TC(TC6, 0), #else NO_TIMER, #endif - TCC(TCC0, 0, 4), - SERCOM(SERCOM5, 0), - NO_SERCOM); + TCC(TCC0, 4)); #endif #ifdef PIN_PB17 PIN(PB17, EXTINT_CHANNEL(1), NO_ADC, NO_TOUCH, - #ifdef _SAMD21_TC6_INSTANCE_ - TC(TC6, 1, 1), + SERCOM(SERCOM5, 1), + NO_SERCOM, + #ifdef TC6 + TC(TC6, 1), #else NO_TIMER, #endif - TCC(TCC0, 1, 5), - SERCOM(SERCOM5, 1), - NO_SERCOM); + TCC(TCC0, 5)); #endif #ifdef PIN_PA20 PIN(PA20, EXTINT_CHANNEL(4), NO_ADC, NO_TOUCH, - #ifdef _SAMD21_TC7_INSTANCE_ - NO_TIMER, // TC(TC7, 0, 0), + SERCOM(SERCOM5, 2), + SERCOM(SERCOM3, 2), + #ifdef TC7 + TC(TC7, 0), #else NO_TIMER, #endif - TCC(TCC0, 2, 6), - SERCOM(SERCOM5, 2), - SERCOM(SERCOM3, 2)); + TCC(TCC0, 6)); #endif #ifdef PIN_PA21 PIN(PA21, EXTINT_CHANNEL(5), NO_ADC, NO_TOUCH, - #ifdef _SAMD21_TC7_INSTANCE_ - TC(TC7, 1, 1), + SERCOM(SERCOM5, 3), + SERCOM(SERCOM3, 3), + #ifdef TC7 + TC(TC7, 1), #else NO_TIMER, #endif - TCC(TCC0, 3, 7), - SERCOM(SERCOM5, 3), - SERCOM(SERCOM3, 3)); + TCC(TCC0, 7)); #endif #ifdef PIN_PA22 PIN(PA22, EXTINT_CHANNEL(6), NO_ADC, NO_TOUCH, - NO_TIMER, // TC(TC4, 0, 0), - TCC(TCC0, 0, 4), SERCOM(SERCOM3, 0), #ifdef SERCOM5 - SERCOM(SERCOM5, 0) + SERCOM(SERCOM5, 0), #else - NO_SERCOM - #endif - ); + NO_SERCOM, + #endif, + TC(TC4, 0), + TCC(TCC0, 4)); #endif #ifdef PIN_PA23 PIN(PA23, EXTINT_CHANNEL(7), NO_ADC, NO_TOUCH, - TC(TC4, 1, 1), - TCC(TCC0, 1, 5), SERCOM(SERCOM3, 1), #ifdef SERCOM5 - SERCOM(SERCOM5, 1) + SERCOM(SERCOM5, 1), #else - NO_SERCOM + NO_SERCOM, #endif - ); + TC(TC4, 1), + TCC(TCC0, 5)); #endif #ifdef PIN_PA24 PIN(PA24, EXTINT_CHANNEL(12), NO_ADC, NO_TOUCH, - NO_TIMER, // TC(TC5, 0, 0), - TCC(TCC0, 2, 2), SERCOM(SERCOM3, 2), #ifdef SERCOM5 - SERCOM(SERCOM5, 2) + SERCOM(SERCOM5, 2), #else - NO_SERCOM + NO_SERCOM, #endif - ); + TC(TC5, 0), + TCC(TCC0, 2)); #endif #ifdef PIN_PA25 PIN(PA25, EXTINT_CHANNEL(13), NO_ADC, NO_TOUCH, - TC(TC5, 1, 1), - TCC(TCC1, 1, 3), SERCOM(SERCOM3, 3), #ifdef SERCOM5 - SERCOM(SERCOM5, 3) + SERCOM(SERCOM5, 3), #else - NO_SERCOM + NO_SERCOM, #endif - ); + TC(TC5, 1), + TCC(TCC1, 3)); #endif #ifdef PIN_PB22 PIN(PB22, EXTINT_CHANNEL(6), NO_ADC, NO_TOUCH, - #ifdef _SAMD21_TC7_INSTANCE_ - NO_TIMER, // TC(TC7, 0, 0), + NO_SERCOM, + SERCOM(SERCOM5, 2), + #ifdef TC7 + TC(TC7, 0, 0), #else NO_TIMER, #endif - NO_TIMER, - NO_SERCOM, - SERCOM(SERCOM5, 2)); + NO_TIMER); #endif #ifdef PIN_PB23 PIN(PB23, EXTINT_CHANNEL(7), NO_ADC, NO_TOUCH, - #ifdef _SAMD21_TC7_INSTANCE_ + NO_SERCOM, + SERCOM(SERCOM5, 3), + #ifdef TC7 TC(TC7, 1, 1), #else NO_TIMER, #endif - NO_TIMER, - NO_SERCOM, - SERCOM(SERCOM5, 3)); + NO_TIMER); #endif #ifdef PIN_PA27 PIN(PA27, EXTINT_CHANNEL(15), NO_ADC, NO_TOUCH, - NO_TIMER, - NO_TIMER, NO_SERCOM, - NO_SERCOM); + NO_SERCOM, + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PA28 PIN(PA28, EXTINT_CHANNEL(8), NO_ADC, NO_TOUCH, - NO_TIMER, - NO_TIMER, NO_SERCOM, - NO_SERCOM); + NO_SERCOM, + NO_TIMER, + NO_TIMER); #endif #ifdef PIN_PA30 PIN(PA30, EXTINT_CHANNEL(10), NO_ADC, NO_TOUCH, - TCC(TCC1, 0, 0), - NO_TIMER, NO_SERCOM, - SERCOM(SERCOM1, 2)); + SERCOM(SERCOM1, 2), + TCC(TCC1, 0), + NO_TIMER); #endif #ifdef PIN_PA31 PIN(PA31, EXTINT_CHANNEL(11), NO_ADC, NO_TOUCH, - TCC(TCC1, 1, 1), - NO_TIMER, NO_SERCOM, - SERCOM(SERCOM1, 3)); + SERCOM(SERCOM1, 3), + TCC(TCC1, 1), + NO_TIMER); #endif #ifdef PIN_PB30 PIN(PB30, EXTINT_CHANNEL(14), NO_ADC, NO_TOUCH, - TCC(TCC0, 0, 0), - TCC(TCC1, 0, 2), NO_SERCOM, - SERCOM(SERCOM5, 0)); + SERCOM(SERCOM5, 0), + TCC(TCC0, 0), + TCC(TCC1, 2)); #endif #ifdef PIN_PB31 PIN(PB31, EXTINT_CHANNEL(15), NO_ADC, NO_TOUCH, - TCC(TCC0, 1, 1), - TCC(TCC1, 1, 3), NO_SERCOM, - SERCOM(SERCOM5, 1)); + SERCOM(SERCOM5, 1), + TCC(TCC0, 1), + TCC(TCC1, 3)); #endif #ifdef PIN_PB00 -PIN(PB00, EXTINT_CHANNEL(0), ADC_INPUT(ADC_POSITIVE_INPUT_PIN8), TOUCH(6), - #ifdef _SAMD21_TC7_INSTANCE_ - NO_TIMER, // TC(TC7, 0, 0), +PIN(PB00, EXTINT_CHANNEL(0), ADC_INPUT(8), TOUCH(6), + NO_SERCOM, + SERCOM(SERCOM5, 2), + #ifdef TC7 + TC(TC7, 0, 0), #else NO_TIMER, #endif - NO_TIMER, - NO_SERCOM, - SERCOM(SERCOM5, 2)); + NO_TIMER); #endif #ifdef PIN_PB01 -PIN(PB01, EXTINT_CHANNEL(1), ADC_INPUT(ADC_POSITIVE_INPUT_PIN9), TOUCH(7), - #ifdef _SAMD21_TC7_INSTANCE_ - TC(TC7, 1, 1), +PIN(PB01, EXTINT_CHANNEL(1), ADC_INPUT(9), TOUCH(7), + NO_SERCOM, + SERCOM(SERCOM5, 3)), + #ifdef TC7 + TC(TC7, 1), #else NO_TIMER, #endif - NO_TIMER, - NO_SERCOM, - SERCOM(SERCOM5, 3)); + NO_TIMER; #endif #ifdef PIN_PB02 -PIN(PB02, EXTINT_CHANNEL(2), ADC_INPUT(ADC_POSITIVE_INPUT_PIN10), TOUCH(8), - #ifdef _SAMD21_TC6_INSTANCE_ - NO_TIMER, // TC(TC6, 0, 0), +PIN(PB02, EXTINT_CHANNEL(2), ADC_INPUT(10), TOUCH(8), + NO_SERCOM, + SERCOM(SERCOM5, 0), + #ifdef TC6 + TC(TC6, 0), #else NO_TIMER, #endif - NO_TIMER, - NO_SERCOM, - SERCOM(SERCOM5, 0)); + NO_TIMER); #endif #ifdef PIN_PB03 -PIN(PB03, EXTINT_CHANNEL(3), ADC_INPUT(ADC_POSITIVE_INPUT_PIN11), TOUCH(9), - #ifdef _SAMD21_TC6_INSTANCE_ - TC(TC6, 1, 1), +PIN(PB03, EXTINT_CHANNEL(3), ADC_INPUT(11), TOUCH(9), + NO_SERCOM, + SERCOM(SERCOM5, 1), + #ifdef TC6 + TC(TC6, 1), #else NO_TIMER, #endif - NO_TIMER, - NO_SERCOM, - SERCOM(SERCOM5, 1)); + NO_TIMER); #endif diff --git a/atmel-samd/samd21_pins.h b/atmel-samd/samd21_pins.h index 4562ccf8d51be..522563ef11454 100644 --- a/atmel-samd/samd21_pins.h +++ b/atmel-samd/samd21_pins.h @@ -27,6 +27,8 @@ #ifndef MICROPY_INCLUDED_ATMEL_SAMD_BOARDS_SAMD21_PINS_H #define MICROPY_INCLUDED_ATMEL_SAMD_BOARDS_SAMD21_PINS_H +#include "include/sam.h" + #include "common-hal/microcontroller/Pin.h" void reset_pin(uint8_t pin); diff --git a/atmel-samd/samd51_pins.c b/atmel-samd/samd51_pins.c new file mode 100644 index 0000000000000..f33582b4ceb36 --- /dev/null +++ b/atmel-samd/samd51_pins.c @@ -0,0 +1,1222 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "shared-bindings/microcontroller/Pin.h" + +#include "samd51_pins.h" + +#define SERCOM(p_sercom, p_pad) \ +{ \ + .sercom = p_sercom, \ + .pad = p_pad \ +} + +#define NO_SERCOM SERCOM(0, 0) + +#define TCC(p_tcc, p_wave_output) \ +{ \ + .tcc = p_tcc, \ + .wave_output = p_wave_output \ +} + +#define TC(p_tc, p_wave_output) \ +{ \ + .tc = p_tc, \ + .wave_output = p_wave_output \ +} + +#define NO_TIMER TCC(0, 0) + +#define TOUCH(y_line) \ + .has_touch = true, \ + .touch_y_line = y_line, + +#define NO_TOUCH \ + .has_touch = false, + +#define EXTINT_CHANNEL(channel) \ + .has_extint = true, \ + .extint_channel = channel, + +#define NO_EXTINT \ + .has_extint = false, + +#define ADC_INPUT(input) (input) + +#define NO_ADC 0xff + +// This macro is used to simplify pin definition in boards//pins.c +#define PIN(p_name, p_extint, p_adc0, p_adc1, p_touch, \ + p_primary_sercom, p_secondary_sercom, \ + p_primary_timer, p_secondary_timer, p_tertiary_timer) \ +const mcu_pin_obj_t pin_## p_name = { \ + { &mcu_pin_type }, \ + .name = MP_QSTR_## p_name, \ + .pin = (PIN_## p_name), \ + p_extint \ + p_touch \ + .adc_input = {p_adc0, p_adc1}, \ + .timer = {p_primary_timer, p_secondary_timer, p_tertiary_timer}, \ + .sercom = {p_primary_sercom, p_secondary_sercom}, \ +} + +#define NO_ADC_INPUT (0) + +// Pins in datasheet order. +// NOTE(tannewt): TC wave out 0 is commented out because the first channel is +// used to vary the 16 bit timer's frequency. +#ifdef PIN_PB03 +PIN(PB03, EXTINT_CHANNEL(3), ADC_INPUT(15), NO_ADC, + TOUCH(21), + NO_SERCOM, + SERCOM(SERCOM5, 1), + #ifdef TC6 + TC(TC6, 1), + #else + NO_TIMER, + #endif + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA00 +PIN(PA00, EXTINT_CHANNEL(0), NO_ADC, NO_ADC, + NO_TOUCH, + NO_SERCOM, + SERCOM(SERCOM1, 0), + TC(TC2, 0), + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA01 +PIN(PA01, EXTINT_CHANNEL(1), NO_ADC, NO_ADC, + NO_TOUCH, + NO_SERCOM, + SERCOM(SERCOM1, 1), + TC(TC2, 0), + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC00 +PIN(PC00, EXTINT_CHANNEL(0), NO_ADC, ADC_INPUT(10), + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC01 +PIN(PC01, EXTINT_CHANNEL(1), NO_ADC, ADC_INPUT(11), + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC02 +PIN(PC02, EXTINT_CHANNEL(2), NO_ADC, ADC_INPUT(4), + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC03 +PIN(PC03, EXTINT_CHANNEL(3), NO_ADC, ADC_INPUT(5), + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA02 +PIN(PA02, EXTINT_CHANNEL(2), ADC_INPUT(0), NO_ADC, + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA03 +PIN(PA03, EXTINT_CHANNEL(3), ADC_INPUT(1), NO_ADC, + TOUCH(0), + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB04 +PIN(PB04, EXTINT_CHANNEL(4), NO_ADC, ADC_INPUT(6), + #ifdef PINMUX_PB04B_ADC0_PTCXY22 + TOUCH(22), + #else + NO_TOUCH, + #endif + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB05 +PIN(PB05, EXTINT_CHANNEL(5), NO_ADC, ADC_INPUT(7), + #ifdef PINMUX_PB05B_ADC0_PTCXY23 + TOUCH(23), + #else + NO_TOUCH, + #endif + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PD00 +PIN(PD00, EXTINT_CHANNEL(0), NO_ADC, ADC_INPUT(14), NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PD01 +PIN(PD01, EXTINT_CHANNEL(1), NO_ADC, ADC_INPUT(15), NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB06 +PIN(PB06, EXTINT_CHANNEL(6), NO_ADC, ADC_INPUT(8), + #ifdef PINMUX_PB06B_ADC0_PTCXY24 + TOUCH(24), + #else + NO_TOUCH, + #endif + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB07 +PIN(PB07, EXTINT_CHANNEL(7), NO_ADC, ADC_INPUT(9), + #ifdef PINMUX_PB07B_ADC0_PTCXY25 + TOUCH(25), + #else + NO_TOUCH, + #endif + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB08 +PIN(PB08, EXTINT_CHANNEL(8), ADC_INPUT(2), ADC_INPUT(0), TOUCH(1), + NO_SERCOM, + SERCOM(SERCOM4, 0), + TC(TC4, 0), + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB09 +PIN(PB09, EXTINT_CHANNEL(9), ADC_INPUT(3), ADC_INPUT(1), TOUCH(2), + NO_SERCOM, + SERCOM(SERCOM4, 1), + TC(TC4, 1), + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA04 +PIN(PA04, EXTINT_CHANNEL(4), ADC_INPUT(4), NO_ADC, TOUCH(3), + NO_SERCOM, + SERCOM(SERCOM0, 0), + TC(TC0, 0), + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA05 +PIN(PA05, EXTINT_CHANNEL(5), ADC_INPUT(5), NO_ADC, NO_TOUCH, + NO_SERCOM, + SERCOM(SERCOM0, 1), + TC(TC0, 1), + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA06 +PIN(PA06, EXTINT_CHANNEL(6), ADC_INPUT(6), NO_ADC, TOUCH(4), + NO_SERCOM, + SERCOM(SERCOM0, 2), + TC(TC1, 0), + NO_TIMER, + NO_TIMER); +#endif + +// Second page +#ifdef PIN_PA07 +PIN(PA07, EXTINT_CHANNEL(7), ADC_INPUT(7), NO_ADC, TOUCH(5), + NO_SERCOM, + SERCOM(SERCOM0, 3), + TC(TC1, 1), + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC04 +PIN(PC04, EXTINT_CHANNEL(4), NO_ADC, NO_ADC, NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 0), + #else + NO_SERCOM, + #endif + NO_SERCOM, + NO_TIMER, + TCC(TCC0, 0), + NO_TIMER); +#endif +#ifdef PIN_PC05 +PIN(PC05, EXTINT_CHANNEL(5), NO_ADC, NO_ADC, NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 1), + #else + NO_SERCOM, + #endif + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC06 +PIN(PC06, EXTINT_CHANNEL(6), NO_ADC, NO_ADC, NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 2), + #else + NO_SERCOM, + #endif + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC07 +PIN(PC07, EXTINT_CHANNEL(7), NO_ADC, NO_ADC, NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 3), + #else + NO_SERCOM, + #endif + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA08 +PIN(PA08, NO_EXTINT, ADC_INPUT(8), ADC_INPUT(2), TOUCH(6), + SERCOM(SERCOM0, 0), + SERCOM(SERCOM2, 1), + TC(TC0, 0), + TCC(TCC0, 0), + TCC(TCC1, 4)); +#endif +#ifdef PIN_PA09 +PIN(PA09, EXTINT_CHANNEL(9), ADC_INPUT(9), ADC_INPUT(3), TOUCH(7), + SERCOM(SERCOM0, 1), + SERCOM(SERCOM2, 0), + TC(TC0, 1), + TCC(TCC0, 1), + TCC(TCC1, 5)); +#endif +#ifdef PIN_PA10 +PIN(PA10, EXTINT_CHANNEL(10), ADC_INPUT(10), NO_ADC, TOUCH(8), + SERCOM(SERCOM0, 2), + SERCOM(SERCOM2, 2), + TC(TC1, 0), + TCC(TCC0, 2), + TCC(TCC1, 6)); +#endif +#ifdef PIN_PA11 +PIN(PA11, EXTINT_CHANNEL(11), ADC_INPUT(11), NO_ADC, TOUCH(9), + SERCOM(SERCOM0, 3), + SERCOM(SERCOM2, 3), + TC(TC1, 0), + TCC(TCC0, 3), + TCC(TCC1, 7)); +#endif +#ifdef PIN_PB10 +PIN(PB10, EXTINT_CHANNEL(10), NO_ADC, NO_ADC, NO_TOUCH, + NO_SERCOM, + SERCOM(SERCOM4, 2), + #ifdef TC5 + TC(TC5, 0), + #else + NO_TIMER, + #endif + TCC(TCC0, 4), + TCC(TCC1, 0)); +#endif +#ifdef PIN_PB11 +PIN(PB11, EXTINT_CHANNEL(11), NO_ADC, NO_ADC, NO_TOUCH, + NO_SERCOM, + SERCOM(SERCOM4, 3), + #ifdef TC5 + TC(TC5, 1), + #else + NO_TIMER, + #endif + TCC(TCC0, 5), + TCC(TCC1, 1)); +#endif +#ifdef PIN_PB12 +PIN(PB12, EXTINT_CHANNEL(12), NO_ADC, NO_ADC, + #ifdef PINMUX_PB12B_ADC0_PTCXY26 + TOUCH(26), + #else + NO_TOUCH, + #endif + SERCOM(SERCOM4, 0), + NO_SERCOM, + #ifdef TC4 + TC(TC4, 0), + #else + NO_TIMER, + #endif + #ifdef TCC3 + TCC(TCC3, 0), + #else + NO_TIMER, + #endif + TCC(TCC0, 0)); +#endif +#ifdef PIN_PB13 +PIN(PB13, EXTINT_CHANNEL(13), NO_ADC, NO_ADC, + #ifdef PINMUX_PB13B_ADC0_PTCXY27 + TOUCH(27), + #else + NO_TOUCH, + #endif + SERCOM(SERCOM4, 1), + NO_SERCOM, + #ifdef TC4 + TC(TC4, 1), + #else + NO_TIMER, + #endif + #ifdef TCC3 + TCC(TCC3, 1), + #else + NO_TIMER, + #endif + TCC(TCC0, 1)); +#endif +#ifdef PIN_PB14 +PIN(PB14, EXTINT_CHANNEL(14), NO_ADC, NO_ADC, + #ifdef PINMUX_PB14B_ADC0_PTCXY28 + TOUCH(28), + #else + NO_TOUCH, + #endif + SERCOM(SERCOM4, 2), + NO_SERCOM, + #ifdef TC5 + TC(TC5, 0), + #else + NO_TIMER, + #endif + #ifdef TCC4 + TCC(TCC4, 0), + #else + NO_TIMER, + #endif + TCC(TCC0, 2)); +#endif +#ifdef PIN_PB15 +PIN(PB15, EXTINT_CHANNEL(15), NO_ADC, NO_ADC, + #ifdef PINMUX_PB15B_ADC0_PTCXY29 + TOUCH(28), + #else + NO_TOUCH, + #endif + SERCOM(SERCOM4, 3), + NO_SERCOM, + #ifdef TC5 + TC(TC5, 1), + #else + NO_TIMER, + #endif + #ifdef TCC4 + TCC(TCC4, 1), + #else + NO_TIMER, + #endif + TCC(TCC0, 3)); +#endif +#ifdef PIN_PD08 +PIN(PD08, EXTINT_CHANNEL(3), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 0), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 1), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 1), + NO_TIMER); +#endif +#ifdef PIN_PD09 +PIN(PD09, EXTINT_CHANNEL(4), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 1), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 0), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 2), + NO_TIMER); +#endif +#ifdef PIN_PD10 +PIN(PD10, EXTINT_CHANNEL(5), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 2), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 2), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 3), + NO_TIMER); +#endif +#ifdef PIN_PD11 +PIN(PD11, EXTINT_CHANNEL(6), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 3), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 3), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 4), + NO_TIMER); +#endif +#ifdef PIN_PD12 +PIN(PD12, EXTINT_CHANNEL(7), NO_ADC, NO_ADC, + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + TCC(TCC0, 5), + NO_TIMER); +#endif +#ifdef PIN_PC10 +PIN(PC10, EXTINT_CHANNEL(10), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 2), + #else + NO_SERCOM, + #endif + #ifdef SERCOM7 + SERCOM(SERCOM7, 2), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 0), + TCC(TCC1, 4)); +#endif +#ifdef PIN_PC11 +PIN(PC11, EXTINT_CHANNEL(11), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 3), + #else + NO_SERCOM, + #endif + #ifdef SERCOM7 + SERCOM(SERCOM7, 3), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 1), + TCC(TCC1, 5)); +#endif +#ifdef PIN_PC12 +PIN(PC12, EXTINT_CHANNEL(12), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 0), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 1), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 2), + TCC(TCC1, 6)); +#endif +#ifdef PIN_PC13 +PIN(PC13, EXTINT_CHANNEL(13), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 1), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 0), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 3), + TCC(TCC1, 7)); +#endif +#ifdef PIN_PC14 +PIN(PC14, EXTINT_CHANNEL(14), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 2), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 2), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 4), + TCC(TCC1, 0)); +#endif +#ifdef PIN_PC15 +PIN(PC15, EXTINT_CHANNEL(15), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 3), + #else + NO_SERCOM, + #endif + #ifdef SERCOM6 + SERCOM(SERCOM6, 3), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC0, 5), + TCC(TCC1, 1)); +#endif +#ifdef PIN_PA12 +PIN(PA12, EXTINT_CHANNEL(12), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 0), + SERCOM(SERCOM4, 1), + TC(TC2, 0), + TCC(TCC0, 6), + TCC(TCC1, 2)); +#endif +#ifdef PIN_PA13 +PIN(PA13, EXTINT_CHANNEL(13), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 1), + SERCOM(SERCOM4, 0), + TC(TC2, 1), + TCC(TCC0, 7), + TCC(TCC1, 3)); +#endif + +// Third page +#ifdef PIN_PA14 +PIN(PA14, EXTINT_CHANNEL(14), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 2), + SERCOM(SERCOM4, 2), + TC(TC3, 0), + TCC(TCC2, 0), + TCC(TCC1, 2)); +#endif +#ifdef PIN_PA15 +PIN(PA15, EXTINT_CHANNEL(15), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 3), + SERCOM(SERCOM4, 3), + TC(TC3, 1), + TCC(TCC2, 1), + TCC(TCC1, 3)); +#endif +#ifdef PIN_PA16 +PIN(PA16, EXTINT_CHANNEL(0), NO_ADC, NO_ADC, TOUCH(10), + SERCOM(SERCOM1, 0), + SERCOM(SERCOM3, 1), + TC(TC2, 0), + TCC(TCC1, 0), + TCC(TCC0, 4)); +#endif +#ifdef PIN_PA17 +PIN(PA17, EXTINT_CHANNEL(1), NO_ADC, NO_ADC, TOUCH(11), + SERCOM(SERCOM1, 1), + SERCOM(SERCOM3, 0), + TC(TC2, 1), + TCC(TCC1, 1), + TCC(TCC0, 5)); +#endif +#ifdef PIN_PA18 +PIN(PA18, EXTINT_CHANNEL(2), NO_ADC, NO_ADC, TOUCH(12), + SERCOM(SERCOM1, 2), + SERCOM(SERCOM3, 2), + TC(TC3, 0), + TCC(TCC1, 2), + TCC(TCC0, 6)); +#endif +#ifdef PIN_PA19 +PIN(PA19, EXTINT_CHANNEL(3), NO_ADC, NO_ADC, TOUCH(13), + SERCOM(SERCOM1, 3), + SERCOM(SERCOM3, 3), + TC(TC3, 1), + TCC(TCC1, 3), + TCC(TCC0, 7)); +#endif +#ifdef PIN_PC16 +PIN(PC16, EXTINT_CHANNEL(0), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 0), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM0, 1), + NO_TIMER, + TCC(TCC0, 0), + NO_TIMER); +#endif +#ifdef PIN_PC17 +PIN(PC17, EXTINT_CHANNEL(1), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 1), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM0, 0), + NO_TIMER, + TCC(TCC0, 1), + NO_TIMER); +#endif +#ifdef PIN_PC18 +PIN(PC18, EXTINT_CHANNEL(2), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 2), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM0, 2), + NO_TIMER, + TCC(TCC0, 2), + NO_TIMER); +#endif +#ifdef PIN_PC19 +PIN(PC19, EXTINT_CHANNEL(3), NO_ADC, NO_ADC, + NO_TOUCH, + #ifdef SERCOM6 + SERCOM(SERCOM6, 3), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM0, 3), + NO_TIMER, + TCC(TCC0, 3), + NO_TIMER); +#endif +#ifdef PIN_PC20 +PIN(PC20, EXTINT_CHANNEL(4), NO_ADC, NO_ADC, + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + TCC(TCC0, 4), + NO_TIMER); +#endif +#ifdef PIN_PC21 +PIN(PC21, EXTINT_CHANNEL(5), NO_ADC, NO_ADC, + NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + TCC(TCC0, 5), + NO_TIMER); +#endif +#ifdef PIN_PC22 +PIN(PC22, EXTINT_CHANNEL(6), NO_ADC, NO_ADC, + NO_TOUCH, + SERCOM(SERCOM1, 0), + SERCOM(SERCOM3, 1), + NO_TIMER, + TCC(TCC0, 6), + NO_TIMER); +#endif +#ifdef PIN_PC23 +PIN(PC23, EXTINT_CHANNEL(7), NO_ADC, NO_ADC, + NO_TOUCH, + SERCOM(SERCOM1, 1), + SERCOM(SERCOM3, 0), + NO_TIMER, + TCC(TCC0, 7), + NO_TIMER); +#endif +#ifdef PIN_PD20 +PIN(PD20, EXTINT_CHANNEL(10), NO_ADC, NO_ADC, + NO_TOUCH, + SERCOM(SERCOM1, 2), + SERCOM(SERCOM3, 2), + NO_TIMER, + TCC(TCC1, 0), + NO_TIMER); +#endif +#ifdef PIN_PD21 +PIN(PD21, EXTINT_CHANNEL(11), NO_ADC, NO_ADC, + NO_TOUCH, + SERCOM(SERCOM1, 3), + SERCOM(SERCOM3, 3), + NO_TIMER, + TCC(TCC1, 1), + NO_TIMER); +#endif + + + + +#ifdef PIN_PB16 +PIN(PB16, EXTINT_CHANNEL(0), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM5, 0), + NO_SERCOM, + #ifdef TC6 + TC(TC6, 0), + #else + NO_TIMER, + #endif + TCC(TCC3, 0), + TCC(TCC0, 4)); +#endif +#ifdef PIN_PB17 +PIN(PB17, EXTINT_CHANNEL(1), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM5, 1), + NO_SERCOM, + #ifdef TC6 + TC(TC6, 1), + #else + NO_TIMER, + #endif + TCC(TCC3, 1), + TCC(TCC0, 5)); +#endif +#ifdef PIN_PB18 +PIN(PB18, EXTINT_CHANNEL(2), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM5, 2), + #ifdef SERCOM7 + SERCOM(SERCOM7, 2), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC1, 0), + NO_TIMER); +#endif +#ifdef PIN_PB19 +PIN(PB19, EXTINT_CHANNEL(3), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM5, 3), + #ifdef SERCOM7 + SERCOM(SERCOM7, 3), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC1, 1), + NO_TIMER); +#endif +#ifdef PIN_PB20 +PIN(PB20, EXTINT_CHANNEL(4), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM5, 0), + #ifdef SERCOM7 + SERCOM(SERCOM7, 1), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC1, 2), + NO_TIMER); +#endif +#ifdef PIN_PB21 +PIN(PB21, EXTINT_CHANNEL(5), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM5, 1), + #ifdef SERCOM7 + SERCOM(SERCOM7, 0), + #else + NO_SERCOM, + #endif + NO_TIMER, + TCC(TCC1, 3), + NO_TIMER); +#endif +#ifdef PIN_PA20 +PIN(PA20, EXTINT_CHANNEL(4), NO_ADC, NO_ADC, TOUCH(14), + SERCOM(SERCOM5, 2), + SERCOM(SERCOM3, 2), + #ifdef TC7 + TC(TC7, 0), + #else + NO_TIMER, + #endif + TCC(TCC1, 4), + TCC(TCC0, 0)); +#endif +#ifdef PIN_PA21 +PIN(PA21, EXTINT_CHANNEL(5), NO_ADC, NO_ADC, TOUCH(15), + SERCOM(SERCOM5, 3), + SERCOM(SERCOM3, 3), + #ifdef TC7 + TC(TC7, 1), + #else + NO_TIMER, + #endif + TCC(TCC1, 5), + TCC(TCC0, 1)); +#endif +#ifdef PIN_PA22 +PIN(PA22, EXTINT_CHANNEL(6), NO_ADC, NO_ADC, TOUCH(16), + SERCOM(SERCOM3, 0), + SERCOM(SERCOM5, 1), + #ifdef TC4 + TC(TC4, 0), + #else + NO_TIMER, + #endif + TCC(TCC1, 6), + TCC(TCC0, 2)); +#endif +#ifdef PIN_PA23 +PIN(PA23, EXTINT_CHANNEL(7), NO_ADC, NO_ADC, TOUCH(17), + SERCOM(SERCOM3, 1), + SERCOM(SERCOM5, 0), + #ifdef TC4 + TC(TC4, 1), + #else + NO_TIMER, + #endif + TCC(TCC1, 7), + TCC(TCC0, 3)); +#endif +#ifdef PIN_PA24 +PIN(PA24, EXTINT_CHANNEL(8), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM3, 2), + SERCOM(SERCOM5, 2), + #ifdef TC5 + TC(TC5, 0), + #else + NO_TIMER, + #endif + TCC(TCC2, 2), + NO_TIMER); +#endif +#ifdef PIN_PA25 +PIN(PA25, EXTINT_CHANNEL(9), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM3, 3), + SERCOM(SERCOM5, 3), + #ifdef TC5 + TC(TC5, 1), + #else + NO_TIMER, + #endif + NO_TIMER, + NO_TIMER); +#endif + +// Fourth page +#ifdef PIN_PB22 +PIN(PB22, EXTINT_CHANNEL(6), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM1, 2), + SERCOM(SERCOM5, 2), + #ifdef TC7 + TC(TC7, 0), + #else + NO_TIMER, + #endif + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB23 +PIN(PB23, EXTINT_CHANNEL(7), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM1, 3), + SERCOM(SERCOM5, 3), + #ifdef TC7 + TC(TC7, 1), + #else + NO_TIMER, + #endif + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB24 +PIN(PB24, EXTINT_CHANNEL(8), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM0, 0), + SERCOM(SERCOM2, 1), + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB25 +PIN(PB25, EXTINT_CHANNEL(9), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM0, 1), + SERCOM(SERCOM2, 0), + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB26 +PIN(PB26, EXTINT_CHANNEL(12), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 0), + SERCOM(SERCOM4, 1), + NO_TIMER, + TCC(TCC1, 2), + NO_TIMER); +#endif +#ifdef PIN_PB27 +PIN(PB27, EXTINT_CHANNEL(13), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 1), + SERCOM(SERCOM4, 0), + NO_TIMER, + TCC(TCC1, 3), + NO_TIMER); +#endif +#ifdef PIN_PB28 +PIN(PB28, EXTINT_CHANNEL(14), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 2), + SERCOM(SERCOM4, 2), + NO_TIMER, + TCC(TCC1, 4), + NO_TIMER); +#endif +#ifdef PIN_PB29 +PIN(PB29, EXTINT_CHANNEL(15), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM2, 3), + SERCOM(SERCOM4, 3), + NO_TIMER, + TCC(TCC1, 5), + NO_TIMER); +#endif +#ifdef PIN_PC24 +PIN(PC24, EXTINT_CHANNEL(8), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM0, 2), + SERCOM(SERCOM2, 2), + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC25 +PIN(PC25, EXTINT_CHANNEL(9), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM0, 3), + SERCOM(SERCOM2, 3), + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC26 +PIN(PC26, EXTINT_CHANNEL(10), NO_ADC, NO_ADC, NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC27 +PIN(PC27, EXTINT_CHANNEL(11), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM1, 0), + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC28 +PIN(PC28, EXTINT_CHANNEL(12), NO_ADC, NO_ADC, NO_TOUCH, + SERCOM(SERCOM1, 1), + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA27 +PIN(PA27, EXTINT_CHANNEL(11), NO_ADC, NO_ADC, TOUCH(18), + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PA30 +PIN(PA30, EXTINT_CHANNEL(14), NO_ADC, NO_ADC, TOUCH(19), + #ifdef SERCOM7 + SERCOM(SERCOM7, 2), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM1, 2), + #ifdef TC6 + TC(TC6, 0), + #else + NO_TIMER, + #endif + TCC(TCC2, 0), + NO_TIMER); +#endif +#ifdef PIN_PA31 +PIN(PA31, EXTINT_CHANNEL(15), NO_ADC, NO_ADC, NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 3), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM1, 23), + #ifdef TC6 + TC(TC6, 1), + #else + NO_TIMER, + #endif + TCC(TCC2, 1), + NO_TIMER); +#endif +#ifdef PIN_PB30 +PIN(PB30, EXTINT_CHANNEL(14), NO_ADC, NO_ADC, NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 0), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM5, 1), + TC(TC0, 0), + TCC(TCC4, 0), + TCC(TCC0, 6)); +#endif +#ifdef PIN_PB31 +PIN(PB31, EXTINT_CHANNEL(15), NO_ADC, NO_ADC, NO_TOUCH, + #ifdef SERCOM7 + SERCOM(SERCOM7, 1), + #else + NO_SERCOM, + #endif + SERCOM(SERCOM5, 0), + TC(TC0, 1), + TCC(TCC4, 1), + TCC(TCC0, 7)); +#endif +#ifdef PIN_PC30 +PIN(PC30, EXTINT_CHANNEL(14), NO_ADC, ADC_INPUT(12), NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PC31 +PIN(PC31, EXTINT_CHANNEL(15), NO_ADC, ADC_INPUT(13), NO_TOUCH, + NO_SERCOM, + NO_SERCOM, + NO_TIMER, + NO_TIMER, + NO_TIMER); +#endif + + +#ifdef PIN_PB00 +PIN(PB00, EXTINT_CHANNEL(0), ADC_INPUT(12), NO_ADC, + #ifdef PINMUX_PB00B_ADC0_PTCXY30 + TOUCH(30), + #else + NO_TOUCH, + #endif + NO_SERCOM, + SERCOM(SERCOM5, 2), + #ifdef TC7 + TC(TC7, 0), + #else + NO_TIMER, + #endif + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB01 +PIN(PB01, EXTINT_CHANNEL(1), ADC_INPUT(13), NO_ADC, + #ifdef PINMUX_PB01B_ADC0_PTCXY31 + TOUCH(31), + #else + NO_TOUCH, + #endif + NO_SERCOM, + SERCOM(SERCOM5, 3), + #ifdef TC7 + TC(TC7, 1), + #else + NO_TIMER, + #endif + NO_TIMER, + NO_TIMER); +#endif +#ifdef PIN_PB02 +PIN(PB02, EXTINT_CHANNEL(2), ADC_INPUT(14), NO_ADC, TOUCH(20), + NO_SERCOM, + SERCOM(SERCOM5, 0), + #ifdef TC6 + TC(TC6, 0), + #else + NO_TIMER, + #endif + TCC(TCC2, 2), + NO_TIMER); +#endif diff --git a/atmel-samd/samd51_pins.h b/atmel-samd/samd51_pins.h new file mode 100644 index 0000000000000..2425f4adce196 --- /dev/null +++ b/atmel-samd/samd51_pins.h @@ -0,0 +1,348 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __MICROPY_INCLUDED_ATMEL_SAMD_SAMD51_PINS_H__ +#define __MICROPY_INCLUDED_ATMEL_SAMD_SAMD51_PINS_H__ + +#include "include/sam.h" + +#include "common-hal/microcontroller/Pin.h" + +void reset_pin(uint8_t pin); + +#define MUX_C 2 +#define MUX_D 3 +#define MUX_E 4 +#define MUX_F 5 +#define PINMUX(pin, mux) ((((uint32_t) pin) << 16) | (mux)) + +#define NO_PIN PORT_BITS + +// Pins in datasheet order. +#ifdef PIN_PB03 +extern const mcu_pin_obj_t pin_PB03; +#endif +#ifdef PIN_PA00 +extern const mcu_pin_obj_t pin_PA00; +#endif +#ifdef PIN_PA01 +extern const mcu_pin_obj_t pin_PA01; +#endif +#ifdef PIN_PC00 +extern const mcu_pin_obj_t pin_PC00; +#endif +#ifdef PIN_PC01 +extern const mcu_pin_obj_t pin_PC01; +#endif +#ifdef PIN_PC02 +extern const mcu_pin_obj_t pin_PC02; +#endif +#ifdef PIN_PC03 +extern const mcu_pin_obj_t pin_PC03; +#endif +#ifdef PIN_PA02 +extern const mcu_pin_obj_t pin_PA02; +#endif +#ifdef PIN_PA03 +extern const mcu_pin_obj_t pin_PA03; +#endif +#ifdef PIN_PB04 +extern const mcu_pin_obj_t pin_PB04; +#endif +#ifdef PIN_PB05 +extern const mcu_pin_obj_t pin_PB05; +#endif +#ifdef PIN_PD00 +extern const mcu_pin_obj_t pin_PD00; +#endif +#ifdef PIN_PD01 +extern const mcu_pin_obj_t pin_PD01; +#endif +#ifdef PIN_PB06 +extern const mcu_pin_obj_t pin_PB06; +#endif +#ifdef PIN_PB07 +extern const mcu_pin_obj_t pin_PB07; +#endif +#ifdef PIN_PB08 +extern const mcu_pin_obj_t pin_PB08; +#endif +#ifdef PIN_PB09 +extern const mcu_pin_obj_t pin_PB09; +#endif +#ifdef PIN_PA04 +extern const mcu_pin_obj_t pin_PA04; +#endif +#ifdef PIN_PA05 +extern const mcu_pin_obj_t pin_PA05; +#endif +#ifdef PIN_PA06 +extern const mcu_pin_obj_t pin_PA06; +#endif + +// Second page +#ifdef PIN_PA07 +extern const mcu_pin_obj_t pin_PA07; +#endif +#ifdef PIN_PC04 +extern const mcu_pin_obj_t pin_PC04; +#endif +#ifdef PIN_PC05 +extern const mcu_pin_obj_t pin_PC05; +#endif +#ifdef PIN_PC06 +extern const mcu_pin_obj_t pin_PC06; +#endif +#ifdef PIN_PC07 +extern const mcu_pin_obj_t pin_PC07; +#endif +#ifdef PIN_PA08 +extern const mcu_pin_obj_t pin_PA08; +#endif +#ifdef PIN_PA09 +extern const mcu_pin_obj_t pin_PA09; +#endif +#ifdef PIN_PA10 +extern const mcu_pin_obj_t pin_PA10; +#endif +#ifdef PIN_PA11 +extern const mcu_pin_obj_t pin_PA11; +#endif +#ifdef PIN_PB10 +extern const mcu_pin_obj_t pin_PB10; +#endif +#ifdef PIN_PB11 +extern const mcu_pin_obj_t pin_PB11; +#endif +#ifdef PIN_PB12 +extern const mcu_pin_obj_t pin_PB12; +#endif +#ifdef PIN_PB13 +extern const mcu_pin_obj_t pin_PB13; +#endif +#ifdef PIN_PB14 +extern const mcu_pin_obj_t pin_PB14; +#endif +#ifdef PIN_PB15 +extern const mcu_pin_obj_t pin_PB15; +#endif +#ifdef PIN_PD08 +extern const mcu_pin_obj_t pin_PD08; +#endif +#ifdef PIN_PD09 +extern const mcu_pin_obj_t pin_PD09; +#endif +#ifdef PIN_PD10 +extern const mcu_pin_obj_t pin_PD10; +#endif +#ifdef PIN_PD11 +extern const mcu_pin_obj_t pin_PD11; +#endif +#ifdef PIN_PD12 +extern const mcu_pin_obj_t pin_PD12; +#endif +#ifdef PIN_PC10 +extern const mcu_pin_obj_t pin_PC10; +#endif +#ifdef PIN_PC11 +extern const mcu_pin_obj_t pin_PC11; +#endif +#ifdef PIN_PC12 +extern const mcu_pin_obj_t pin_PC12; +#endif +#ifdef PIN_PC13 +extern const mcu_pin_obj_t pin_PC13; +#endif +#ifdef PIN_PC14 +extern const mcu_pin_obj_t pin_PC14; +#endif +#ifdef PIN_PC15 +extern const mcu_pin_obj_t pin_PC15; +#endif +#ifdef PIN_PA12 +extern const mcu_pin_obj_t pin_PA12; +#endif +#ifdef PIN_PA13 +extern const mcu_pin_obj_t pin_PA13; +#endif + +// Third page +#ifdef PIN_PA14 +extern const mcu_pin_obj_t pin_PA14; +#endif +#ifdef PIN_PA15 +extern const mcu_pin_obj_t pin_PA15; +#endif +#ifdef PIN_PA16 +extern const mcu_pin_obj_t pin_PA16; +#endif +#ifdef PIN_PA17 +extern const mcu_pin_obj_t pin_PA17; +#endif +#ifdef PIN_PA18 +extern const mcu_pin_obj_t pin_PA18; +#endif +#ifdef PIN_PA19 +extern const mcu_pin_obj_t pin_PA19; +#endif +#ifdef PIN_PC16 +extern const mcu_pin_obj_t pin_PC16; +#endif +#ifdef PIN_PC17 +extern const mcu_pin_obj_t pin_PC17; +#endif +#ifdef PIN_PC18 +extern const mcu_pin_obj_t pin_PC18; +#endif +#ifdef PIN_PC19 +extern const mcu_pin_obj_t pin_PC19; +#endif +#ifdef PIN_PC20 +extern const mcu_pin_obj_t pin_PC20; +#endif +#ifdef PIN_PC21 +extern const mcu_pin_obj_t pin_PC21; +#endif +#ifdef PIN_PC22 +extern const mcu_pin_obj_t pin_PC22; +#endif +#ifdef PIN_PC23 +extern const mcu_pin_obj_t pin_PC23; +#endif +#ifdef PIN_PD20 +extern const mcu_pin_obj_t pin_PD20; +#endif +#ifdef PIN_PD21 +extern const mcu_pin_obj_t pin_PD21; +#endif +#ifdef PIN_PB16 +extern const mcu_pin_obj_t pin_PB16; +#endif +#ifdef PIN_PB17 +extern const mcu_pin_obj_t pin_PB17; +#endif +#ifdef PIN_PB18 +extern const mcu_pin_obj_t pin_PB18; +#endif +#ifdef PIN_PB19 +extern const mcu_pin_obj_t pin_PB19; +#endif +#ifdef PIN_PB20 +extern const mcu_pin_obj_t pin_PB20; +#endif +#ifdef PIN_PB21 +extern const mcu_pin_obj_t pin_PB21; +#endif +#ifdef PIN_PA20 +extern const mcu_pin_obj_t pin_PA20; +#endif +#ifdef PIN_PA21 +extern const mcu_pin_obj_t pin_PA21; +#endif +#ifdef PIN_PA22 +extern const mcu_pin_obj_t pin_PA22; +#endif +#ifdef PIN_PA23 +extern const mcu_pin_obj_t pin_PA23; +#endif +#ifdef PIN_PA24 +extern const mcu_pin_obj_t pin_PA24; +#endif +#ifdef PIN_PA25 +extern const mcu_pin_obj_t pin_PA25; +#endif + +// Fourth page +#ifdef PIN_PB22 +extern const mcu_pin_obj_t pin_PB22; +#endif +#ifdef PIN_PB23 +extern const mcu_pin_obj_t pin_PB23; +#endif +#ifdef PIN_PB24 +extern const mcu_pin_obj_t pin_PB24; +#endif +#ifdef PIN_PB25 +extern const mcu_pin_obj_t pin_PB25; +#endif +#ifdef PIN_PB26 +extern const mcu_pin_obj_t pin_PB26; +#endif +#ifdef PIN_PB27 +extern const mcu_pin_obj_t pin_PB27; +#endif +#ifdef PIN_PB28 +extern const mcu_pin_obj_t pin_PB28; +#endif +#ifdef PIN_PB29 +extern const mcu_pin_obj_t pin_PB29; +#endif +#ifdef PIN_PC24 +extern const mcu_pin_obj_t pin_PC24; +#endif +#ifdef PIN_PC25 +extern const mcu_pin_obj_t pin_PC25; +#endif +#ifdef PIN_PC26 +extern const mcu_pin_obj_t pin_PC26; +#endif +#ifdef PIN_PC27 +extern const mcu_pin_obj_t pin_PC27; +#endif +#ifdef PIN_PC28 +extern const mcu_pin_obj_t pin_PC28; +#endif +#ifdef PIN_PA27 +extern const mcu_pin_obj_t pin_PA27; +#endif +#ifdef PIN_PA30 +extern const mcu_pin_obj_t pin_PA30; +#endif +#ifdef PIN_PA31 +extern const mcu_pin_obj_t pin_PA31; +#endif +#ifdef PIN_PB30 +extern const mcu_pin_obj_t pin_PB30; +#endif +#ifdef PIN_PB31 +extern const mcu_pin_obj_t pin_PB31; +#endif +#ifdef PIN_PC30 +extern const mcu_pin_obj_t pin_PC30; +#endif +#ifdef PIN_PC31 +extern const mcu_pin_obj_t pin_PC31; +#endif +#ifdef PIN_PB00 +extern const mcu_pin_obj_t pin_PB00; +#endif +#ifdef PIN_PB01 +extern const mcu_pin_obj_t pin_PB01; +#endif +#ifdef PIN_PB02 +extern const mcu_pin_obj_t pin_PB02; +#endif +#endif // __MICROPY_INCLUDED_ATMEL_SAMD_SAMD51_PINS_H__ diff --git a/atmel-samd/shared_dma.c b/atmel-samd/shared_dma.c index 46179836667d6..5dc8cde4304ed 100644 --- a/atmel-samd/shared_dma.c +++ b/atmel-samd/shared_dma.c @@ -23,15 +23,13 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ + +#include #include "shared_dma.h" #include "py/gc.h" #include "py/mpstate.h" -#include "asf/sam0/drivers/events/events.h" -#include "asf/sam0/drivers/system/interrupt/system_interrupt.h" -#include "asf/sam0/drivers/tc/tc.h" - #undef ENABLE // We allocate two DMA resources for the entire lifecycle of the board (not the diff --git a/atmel-samd/shared_dma.h b/atmel-samd/shared_dma.h index 7aa45547d0aaa..1e9240338f6cc 100644 --- a/atmel-samd/shared_dma.h +++ b/atmel-samd/shared_dma.h @@ -27,8 +27,6 @@ #ifndef MICROPY_INCLUDED_ATMEL_SAMD_SHARED_DMA_H #define MICROPY_INCLUDED_ATMEL_SAMD_SHARED_DMA_H -#include "asf/sam0/drivers/dma/dma.h" - extern struct dma_resource audio_dma; extern struct dma_resource general_dma_tx; extern struct dma_resource general_dma_rx; diff --git a/atmel-samd/spi_flash.c b/atmel-samd/spi_flash.c index d74007a836f09..8191887e4b36e 100644 --- a/atmel-samd/spi_flash.c +++ b/atmel-samd/spi_flash.c @@ -28,10 +28,13 @@ #include #include +<<<<<<< HEAD #include "asf/sam0/drivers/sercom/spi/spi.h" #include "extmod/vfs.h" #include "extmod/vfs_fat.h" +======= +>>>>>>> WIP #include "py/gc.h" #include "py/obj.h" #include "py/runtime.h" diff --git a/atmel-samd/supervisor/filesystem.c b/atmel-samd/supervisor/filesystem.c new file mode 100644 index 0000000000000..a25a4b9e5b50b --- /dev/null +++ b/atmel-samd/supervisor/filesystem.c @@ -0,0 +1,78 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "extmod/vfs_fat.h" +#include "lib/oofatfs/ff.h" +#include "lib/oofatfs/diskio.h" + +#ifdef EXPRESS_BOARD +// #include "common-hal/touchio/TouchIn.h" +#define INTERNAL_CIRCUITPY_CONFIG_START_ADDR (0x00040000 - 0x100 - CIRCUITPY_INTERNAL_NVM_SIZE) +#else +#define INTERNAL_CIRCUITPY_CONFIG_START_ADDR (0x00040000 - 0x010000 - 0x100 - CIRCUITPY_INTERNAL_NVM_SIZE) +#endif + +fs_user_mount_t fs_user_mount_flash; +mp_vfs_mount_t mp_vfs_mount_flash; + +// we don't make this function static because it needs a lot of stack and we +// want it to be executed without using stack within main() function +void filesystem_init(void) { + // // init the vfs object + // fs_user_mount_t *vfs_fat = &fs_user_mount_flash; + // vfs_fat->flags = 0; + // flash_init_vfs(vfs_fat); + // + // // try to mount the flash + // FRESULT res = f_mount(&vfs_fat->fatfs); + // + // if (res == FR_NO_FILESYSTEM) { + // // no filesystem so create a fresh one + // + // uint8_t working_buf[_MAX_SS]; + // res = f_mkfs(&vfs_fat->fatfs, FM_FAT, 0, working_buf, sizeof(working_buf)); + // // Flush the new file system to make sure its repaired immediately. + // flash_flush(); + // if (res != FR_OK) { + // return; + // } + // + // // set label + // f_setlabel(&vfs_fat->fatfs, "CIRCUITPY"); + // } else if (res != FR_OK) { + // return; + // } + // mp_vfs_mount_t *vfs = &mp_vfs_mount_flash; + // vfs->str = "/"; + // vfs->len = 1; + // vfs->obj = MP_OBJ_FROM_PTR(vfs_fat); + // vfs->next = NULL; + // MP_STATE_VM(vfs_mount_table) = vfs; + // + // // The current directory is used as the boot up directory. + // // It is set to the internal flash filesystem by default. + // MP_STATE_PORT(vfs_cur) = vfs; +} diff --git a/atmel-samd/supervisor/port.c b/atmel-samd/supervisor/port.c new file mode 100644 index 0000000000000..998ad59a4dce8 --- /dev/null +++ b/atmel-samd/supervisor/port.c @@ -0,0 +1,266 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "boards/board.h" +#include "supervisor/port.h" + +// ASF 4 +#include "atmel_start_pins.h" +#include "hal/include/hal_delay.h" +#include "hal/include/hal_gpio.h" +#include "hal/include/hal_init.h" +#include "hal/include/hal_usb_device.h" +#include "hpl/gclk/hpl_gclk_base.h" +#include "hpl/pm/hpl_pm_base.h" + +#include "tick.h" + +extern volatile bool mp_msc_enabled; + +#if defined(SAMD21) && defined(ENABLE_MICRO_TRACE_BUFFER) +// Stores 2 ^ TRACE_BUFFER_MAGNITUDE_PACKETS packets. +// 7 -> 128 packets +#define TRACE_BUFFER_MAGNITUDE_PACKETS 7 +// Size in uint32_t. Two per packet. +#define TRACE_BUFFER_SIZE (1 << (TRACE_BUFFER_MAGNITUDE_PACKETS + 1)) +// Size in bytes. 4 bytes per uint32_t. +#define TRACE_BUFFER_SIZE_BYTES (TRACE_BUFFER_SIZE << 2) +__attribute__((__aligned__(TRACE_BUFFER_SIZE_BYTES))) uint32_t mtb[TRACE_BUFFER_SIZE]; +#endif + +safe_mode_t port_init(void) { +#if defined(SAMD21) + #ifdef ENABLE_MICRO_TRACE_BUFFER + REG_MTB_POSITION = ((uint32_t) (mtb - REG_MTB_BASE)) & 0xFFFFFFF8; + REG_MTB_FLOW = (((uint32_t) mtb - REG_MTB_BASE) + TRACE_BUFFER_SIZE_BYTES) & 0xFFFFFFF8; + REG_MTB_MASTER = 0x80000000 + (TRACE_BUFFER_MAGNITUDE_PACKETS - 1); + #else + // Triple check that the MTB is off. Switching between debug and non-debug + // builds can leave it set over reset and wreak havok as a result. + REG_MTB_MASTER = 0x00000000 + 6; + #endif +#endif + +// // On power on start or external reset, set _ezero to the canary word. If it +// // gets killed, we boot in safe mod. _ezero is the boundary between statically +// // allocated memory including the fixed MicroPython heap and the stack. If either +// // misbehaves, the canary will not be in tact after soft reset. +// #ifdef CIRCUITPY_CANARY_WORD +// if (PM->RCAUSE.bit.POR == 1 || PM->RCAUSE.bit.EXT == 1) { +// _ezero = CIRCUITPY_CANARY_WORD; +// } else if (PM->RCAUSE.bit.SYST == 1) { +// // If we're starting from a system reset we're likely coming from the +// // bootloader or hard fault handler. If we're coming from the handler +// // the canary will be CIRCUITPY_SAFE_RESTART_WORD and we don't want to +// // revive the canary so that a second hard fault won't restart. Resets +// // from anywhere else are ok. +// if (_ezero == CIRCUITPY_SAFE_RESTART_WORD) { +// _ezero = ~CIRCUITPY_CANARY_WORD; +// } else { +// _ezero = CIRCUITPY_CANARY_WORD; +// } +// } +// #endif +// +// load_serial_number(); + + init_mcu(); + + delay_init(SysTick); + + board_init(); + + // Configure millisecond timer initialization. + tick_init(); + + // Uncomment to init PIN_PA17 for debugging. + // struct port_config pin_conf; + // port_get_config_defaults(&pin_conf); + // + // pin_conf.direction = PORT_PIN_DIR_OUTPUT; + // port_pin_set_config(MICROPY_HW_LED1, &pin_conf); + // port_pin_set_output_level(MICROPY_HW_LED1, false); + + // Output clocks for debugging. + #ifdef SAMD51 + gpio_set_pin_function(PIN_PA10, GPIO_PIN_FUNCTION_M); // GCLK4, D3 + gpio_set_pin_function(PIN_PA11, GPIO_PIN_FUNCTION_M); // GCLK5, A4 + gpio_set_pin_function(PIN_PB14, GPIO_PIN_FUNCTION_M); // GCLK0, D5 + gpio_set_pin_function(PIN_PB15, GPIO_PIN_FUNCTION_M); // GCLK1, D6 + #endif + + // Init the nvm controller. + // struct nvm_config config_nvm; + // nvm_get_config_defaults(&config_nvm); + // config_nvm.manual_page_write = false; + // nvm_set_config(&config_nvm); + + // init_shared_dma(); + #ifdef CIRCUITPY_CANARY_WORD + // Run in safe mode if the canary is corrupt. + if (_ezero != CIRCUITPY_CANARY_WORD) { + return HARD_CRASH; + } + #endif + + // if (PM->RCAUSE.bit.BOD33 == 1 || PM->RCAUSE.bit.BOD12 == 1) { + // return BROWNOUT; + // } + + if (board_requests_safe_mode()) { + return USER_SAFE_MODE; + } + + // #if CIRCUITPY_INTERNAL_NVM_SIZE > 0 + // // Upgrade the nvm flash to include one sector for eeprom emulation. + // struct nvm_fusebits fuses; + // if (nvm_get_fuses(&fuses) == STATUS_OK && + // fuses.eeprom_size == NVM_EEPROM_EMULATOR_SIZE_0) { + // #ifdef INTERNAL_FLASH_FS + // // Shift the internal file system up one row. + // for (uint8_t row = 0; row < TOTAL_INTERNAL_FLASH_SIZE / NVMCTRL_ROW_SIZE; row++) { + // uint32_t new_row_address = INTERNAL_FLASH_MEM_SEG1_START_ADDR + row * NVMCTRL_ROW_SIZE; + // nvm_erase_row(new_row_address); + // nvm_write_buffer(new_row_address, + // (uint8_t*) (new_row_address + CIRCUITPY_INTERNAL_EEPROM_SIZE), + // NVMCTRL_ROW_SIZE); + // } + // #endif + // uint32_t nvm_size = CIRCUITPY_INTERNAL_NVM_SIZE; + // uint8_t enum_value = 6; + // while (nvm_size > 256 && enum_value != 255) { + // nvm_size /= 2; + // enum_value -= 1; + // } + // if (enum_value != 255 && nvm_size == 256) { + // // Mark the last section as eeprom now. + // fuses.eeprom_size = (enum nvm_eeprom_emulator_size) enum_value; + // nvm_set_fuses(&fuses); + // } + // } + // #endif + + return NO_SAFE_MODE; +} + +void reset_port(void) { + // Reset all SERCOMs except the one being used by the SPI flash. +// Sercom *sercom_instances[SERCOM_INST_NUM] = SERCOM_INSTS; +// for (int i = 0; i < SERCOM_INST_NUM; i++) { +// #ifdef SPI_FLASH_SERCOM +// if (sercom_instances[i] == SPI_FLASH_SERCOM) { +// continue; +// } +// #endif +// #ifdef MICROPY_HW_APA102_SERCOM +// if (sercom_instances[i] == MICROPY_HW_APA102_SERCOM) { +// continue; +// } +// #endif +// sercom_instances[i]->SPI.CTRLA.bit.SWRST = 1; +// } +// +// #ifdef EXPRESS_BOARD +// audioout_reset(); +// touchin_reset(); +// pdmin_reset(); +// pulsein_reset(); +// pulseout_reset(); +// pwmout_reset(); +// #endif +// +// analogin_reset(); +// +// +// // Wait for the DAC to sync then reset. +// while (DAC->STATUS.reg & DAC_STATUS_SYNCBUSY) {} +// DAC->CTRLA.reg |= DAC_CTRLA_SWRST; +// +// reset_all_pins(); +// +// +// usb_hid_reset(); +// +// #ifdef CALIBRATE_CRYSTALLESS +// // If we are on USB lets double check our fine calibration for the clock and +// // save the new value if its different enough. +// if (mp_msc_enabled) { +// SYSCTRL->DFLLSYNC.bit.READREQ = 1; +// uint16_t saved_calibration = 0x1ff; +// if (strcmp((char*) INTERNAL_CIRCUITPY_CONFIG_START_ADDR, "CIRCUITPYTHON1") == 0) { +// saved_calibration = ((uint16_t *) INTERNAL_CIRCUITPY_CONFIG_START_ADDR)[8]; +// } +// while (SYSCTRL->PCLKSR.bit.DFLLRDY == 0) { +// // TODO(tannewt): Run the mass storage stuff if this takes a while. +// } +// int16_t current_calibration = SYSCTRL->DFLLVAL.bit.FINE; +// if (abs(current_calibration - saved_calibration) > 10) { +// enum status_code error_code; +// uint8_t page_buffer[NVMCTRL_ROW_SIZE]; +// for (int i = 0; i < NVMCTRL_ROW_PAGES; i++) { +// do +// { +// error_code = nvm_read_buffer(INTERNAL_CIRCUITPY_CONFIG_START_ADDR + i * NVMCTRL_PAGE_SIZE, +// page_buffer + i * NVMCTRL_PAGE_SIZE, +// NVMCTRL_PAGE_SIZE); +// } while (error_code == STATUS_BUSY); +// } +// // If this is the first write, include the header. +// if (strcmp((char*) page_buffer, "CIRCUITPYTHON1") != 0) { +// memcpy(page_buffer, "CIRCUITPYTHON1", 15); +// } +// // First 16 bytes (0-15) are ID. Little endian! +// page_buffer[16] = current_calibration & 0xff; +// page_buffer[17] = current_calibration >> 8; +// do +// { +// error_code = nvm_erase_row(INTERNAL_CIRCUITPY_CONFIG_START_ADDR); +// } while (error_code == STATUS_BUSY); +// for (int i = 0; i < NVMCTRL_ROW_PAGES; i++) { +// do +// { +// error_code = nvm_write_buffer(INTERNAL_CIRCUITPY_CONFIG_START_ADDR + i * NVMCTRL_PAGE_SIZE, +// page_buffer + i * NVMCTRL_PAGE_SIZE, +// NVMCTRL_PAGE_SIZE); +// } while (error_code == STATUS_BUSY); +// } +// } +// } +// #endif +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +__attribute__((used)) void HardFault_Handler(void) +{ + while (true) { + asm(""); + } + for (uint32_t i = 0; i < 100000; i++) { + asm("noop;"); + } +} diff --git a/atmel-samd/supervisor/serial.c b/atmel-samd/supervisor/serial.c new file mode 100644 index 0000000000000..40c0f5212fa8d --- /dev/null +++ b/atmel-samd/supervisor/serial.c @@ -0,0 +1,66 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + +#include "supervisor/serial.h" + +#include "usb.h" + +// Serial number as hex characters. +// char serial_number[USB_DEVICE_GET_SERIAL_NAME_LENGTH]; +// void load_serial_number(void) { +// char nibble_to_hex[16] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', +// 'B', 'C', 'D', 'E', 'F'}; +// uint32_t* addresses[4] = {(uint32_t *) 0x0080A00C, (uint32_t *) 0x0080A040, +// (uint32_t *) 0x0080A044, (uint32_t *) 0x0080A048}; +// for (int i = 0; i < 4; i++) { +// for (int j = 0; j < 8; j++) { +// uint8_t nibble = (*(addresses[i]) >> j * 4) & 0xf; +// serial_number[i * 8 + j] = nibble_to_hex[nibble]; +// } +// } +// } + +void serial_init(void) { + init_usb(); +} + +bool serial_connected(void) { + return usb_connected(); +} + +char serial_read(void) { + return usb_read(); +} + +bool serial_bytes_available(void) { + return usb_bytes_available(); +} + +void serial_write(const char* text) { + usb_write(text, strlen(text)); +} diff --git a/atmel-samd/tick.c b/atmel-samd/tick.c index cbe72abc6e197..1828341e5ebfc 100644 --- a/atmel-samd/tick.c +++ b/atmel-samd/tick.c @@ -1,15 +1,24 @@ -#include "autoreload.h" -#include "tick.h" -#include "asf/sam0/drivers/tc/tc_interrupt.h" +#include + +#include "hal/include/hal_timer.h" +#include "hpl/pm/hpl_pm_base.h" +#include "hpl/tc/hpl_tc_base.h" +#include "hpl/gclk/hpl_gclk_base.h" +#include "include/component/gclk.h" + +#include "supervisor/shared/autoreload.h" + +#include "tick.h" // Global millisecond tick count volatile uint64_t ticks_ms = 0; -struct tc_module ms_timer; +struct timer_descriptor ms_timer; +//static struct timer_task task; -static void ms_tick(struct tc_module *const module_inst) { +void timer_tick(const struct timer_task *const timer_task) { // SysTick interrupt handler called when the SysTick timer reaches zero // (every millisecond). ticks_ms += 1; @@ -20,16 +29,18 @@ static void ms_tick(struct tc_module *const module_inst) { } void tick_init() { - struct tc_config config_tc; - tc_get_config_defaults(&config_tc); - config_tc.counter_size = TC_COUNTER_SIZE_16BIT; - config_tc.wave_generation = TC_WAVE_GENERATION_MATCH_FREQ; - config_tc.clock_prescaler = TC_CLOCK_PRESCALER_DIV1; - tc_init(&ms_timer, TC5, &config_tc); - - tc_set_top_value(&ms_timer, system_cpu_clock_get_hz() / 1000 - 1); - tc_enable(&ms_timer); - tc_register_callback(&ms_timer, ms_tick, TC_CALLBACK_OVERFLOW); - tc_enable_callback(&ms_timer, TC_CALLBACK_OVERFLOW); - tc_start_counter(&ms_timer); + #ifdef SAMD21 + _pm_enable_bus_clock(PM_BUS_APBC, TC5); + #endif + // _gclk_enable_channel(TC5_GCLK_ID, GCLK_SOURCE_DFLL48M); + + // timer_init(&ms_timer, TC5, _tc_get_timer()); + + // timer_set_clock_cycles_per_tick(&ms_timer, 48000000 / 1000 - 1); + // task.cb = timer_tick; + // task.interval = 1; + // task.mode = TIMER_TASK_REPEAT; + // timer_add_task(&ms_timer, &task); + // + // timer_start(&ms_timer); } diff --git a/atmel-samd/tick.h b/atmel-samd/tick.h index db386aeb2f1c1..f842fd2855603 100644 --- a/atmel-samd/tick.h +++ b/atmel-samd/tick.h @@ -30,7 +30,7 @@ extern volatile uint64_t ticks_ms; -extern struct tc_module ms_timer; +extern struct timer_descriptor ms_timer; void tick_init(void); diff --git a/atmel-samd/tools/samd21.json b/atmel-samd/tools/samd21.json new file mode 100644 index 0000000000000..8a2b098a13395 --- /dev/null +++ b/atmel-samd/tools/samd21.json @@ -0,0 +1 @@ +{"jsonForm":"=1","formatVersion":2,"board":{"identifier":"CustomBoard","device":"SAMD21G18A-MF"},"identifier":"","name":"My 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software/event triggers","dmac_lvl_6":"Channel priority 0","dmac_evoe_6":false,"dmac_evie_6":false,"dmac_evact_6":"No action","dmac_stepsize_6":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_6":"Step size settings apply to the destination address","dmac_srcinc_6":false,"dmac_dstinc_6":false,"dmac_beatsize_6":"8-bit bus transfer","dmac_blockact_6":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_6":"Event generation disabled","dmac_channel_7_settings":false,"dmac_runstdby_7":false,"dmac_trigact_7":"One trigger required for each block transfer","dmac_trifsrc_7":"Only software/event triggers","dmac_lvl_7":"Channel priority 0","dmac_evoe_7":false,"dmac_evie_7":false,"dmac_evact_7":"No action","dmac_stepsize_7":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_7":"Step size settings apply to the destination address","dmac_srcinc_7":false,"dmac_dstinc_7":false,"dmac_beatsize_7":"8-bit bus transfer","dmac_blockact_7":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_7":"Event generation disabled","dmac_channel_8_settings":false,"dmac_runstdby_8":false,"dmac_trigact_8":"One trigger required for each block transfer","dmac_trifsrc_8":"Only software/event triggers","dmac_lvl_8":"Channel priority 0","dmac_evoe_8":false,"dmac_evie_8":false,"dmac_evact_8":"No action","dmac_stepsize_8":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_8":"Step size settings apply to the destination address","dmac_srcinc_8":false,"dmac_dstinc_8":false,"dmac_beatsize_8":"8-bit bus transfer","dmac_blockact_8":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_8":"Event generation disabled","dmac_channel_9_settings":false,"dmac_runstdby_9":false,"dmac_trigact_9":"One trigger required for each block transfer","dmac_trifsrc_9":"Only software/event triggers","dmac_lvl_9":"Channel priority 0","dmac_evoe_9":false,"dmac_evie_9":false,"dmac_evact_9":"No action","dmac_stepsize_9":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_9":"Step size settings apply to the destination address","dmac_srcinc_9":false,"dmac_dstinc_9":false,"dmac_beatsize_9":"8-bit bus transfer","dmac_blockact_9":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_9":"Event generation disabled","dmac_channel_10_settings":false,"dmac_runstdby_10":false,"dmac_trigact_10":"One trigger required for each block transfer","dmac_trifsrc_10":"Only software/event triggers","dmac_lvl_10":"Channel priority 0","dmac_evoe_10":false,"dmac_evie_10":false,"dmac_evact_10":"No action","dmac_stepsize_10":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_10":"Step size settings apply to the destination address","dmac_srcinc_10":false,"dmac_dstinc_10":false,"dmac_beatsize_10":"8-bit bus transfer","dmac_blockact_10":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_10":"Event generation disabled","dmac_channel_11_settings":false,"dmac_runstdby_11":false,"dmac_trigact_11":"One trigger required for each block transfer","dmac_trifsrc_11":"Only software/event triggers","dmac_lvl_11":"Channel priority 0","dmac_evoe_11":false,"dmac_evie_11":false,"dmac_evact_11":"No action","dmac_stepsize_11":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_11":"Step size settings apply to the destination address","dmac_srcinc_11":false,"dmac_dstinc_11":false,"dmac_beatsize_11":"8-bit bus transfer","dmac_blockact_11":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_11":"Event generation disabled","dmac_channel_12_settings":false,"dmac_runstdby_12":false,"dmac_trigact_12":"One trigger required for each block transfer","dmac_trifsrc_12":"Only software/event triggers","dmac_lvl_12":"Channel priority 0","dmac_evoe_12":false,"dmac_evie_12":false,"dmac_evact_12":"No action","dmac_stepsize_12":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_12":"Step size settings apply to the destination address","dmac_srcinc_12":false,"dmac_dstinc_12":false,"dmac_beatsize_12":"8-bit bus transfer","dmac_blockact_12":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_12":"Event generation disabled","dmac_channel_13_settings":false,"dmac_runstdby_13":false,"dmac_trigact_13":"One trigger required for each block transfer","dmac_trifsrc_13":"Only software/event triggers","dmac_lvl_13":"Channel priority 0","dmac_evoe_13":false,"dmac_evie_13":false,"dmac_evact_13":"No action","dmac_stepsize_13":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_13":"Step size settings apply to the destination address","dmac_srcinc_13":false,"dmac_dstinc_13":false,"dmac_beatsize_13":"8-bit bus transfer","dmac_blockact_13":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_13":"Event generation disabled","dmac_channel_14_settings":false,"dmac_runstdby_14":false,"dmac_trigact_14":"One trigger required for each block transfer","dmac_trifsrc_14":"Only software/event triggers","dmac_lvl_14":"Channel priority 0","dmac_evoe_14":false,"dmac_evie_14":false,"dmac_evact_14":"No action","dmac_stepsize_14":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_14":"Step size settings apply to the destination address","dmac_srcinc_14":false,"dmac_dstinc_14":false,"dmac_beatsize_14":"8-bit bus transfer","dmac_blockact_14":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_14":"Event generation disabled","dmac_channel_15_settings":false,"dmac_runstdby_15":false,"dmac_trigact_15":"One trigger required for each block transfer","dmac_trifsrc_15":"Only software/event triggers","dmac_lvl_15":"Channel priority 0","dmac_evoe_15":false,"dmac_evie_15":false,"dmac_evact_15":"No action","dmac_stepsize_15":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_15":"Step size settings apply to the destination address","dmac_srcinc_15":false,"dmac_dstinc_15":false,"dmac_beatsize_15":"8-bit bus transfer","dmac_blockact_15":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_15":"Event generation disabled","dmac_channel_16_settings":false,"dmac_runstdby_16":false,"dmac_trigact_16":"One trigger required for each block transfer","dmac_trifsrc_16":"Only software/event triggers","dmac_lvl_16":"Channel priority 0","dmac_evoe_16":false,"dmac_evie_16":false,"dmac_evact_16":"No action","dmac_stepsize_16":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_16":"Step size settings apply to the destination address","dmac_srcinc_16":false,"dmac_dstinc_16":false,"dmac_beatsize_16":"8-bit bus transfer","dmac_blockact_16":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_16":"Event generation disabled","dmac_channel_17_settings":false,"dmac_runstdby_17":false,"dmac_trigact_17":"One trigger required for each block transfer","dmac_trifsrc_17":"Only software/event triggers","dmac_lvl_17":"Channel priority 0","dmac_evoe_17":false,"dmac_evie_17":false,"dmac_evact_17":"No action","dmac_stepsize_17":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_17":"Step size settings apply to the destination address","dmac_srcinc_17":false,"dmac_dstinc_17":false,"dmac_beatsize_17":"8-bit bus transfer","dmac_blockact_17":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_17":"Event generation disabled","dmac_channel_18_settings":false,"dmac_runstdby_18":false,"dmac_trigact_18":"One trigger required for each block transfer","dmac_trifsrc_18":"Only software/event triggers","dmac_lvl_18":"Channel priority 0","dmac_evoe_18":false,"dmac_evie_18":false,"dmac_evact_18":"No action","dmac_stepsize_18":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_18":"Step size settings apply to the destination address","dmac_srcinc_18":false,"dmac_dstinc_18":false,"dmac_beatsize_18":"8-bit bus transfer","dmac_blockact_18":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_18":"Event generation disabled","dmac_channel_19_settings":false,"dmac_runstdby_19":false,"dmac_trigact_19":"One trigger required for each block transfer","dmac_trifsrc_19":"Only software/event triggers","dmac_lvl_19":"Channel priority 0","dmac_evoe_19":false,"dmac_evie_19":false,"dmac_evact_19":"No action","dmac_stepsize_19":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_19":"Step size settings apply to the destination address","dmac_srcinc_19":false,"dmac_dstinc_19":false,"dmac_beatsize_19":"8-bit bus transfer","dmac_blockact_19":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_19":"Event generation disabled","dmac_channel_20_settings":false,"dmac_runstdby_20":false,"dmac_trigact_20":"One trigger required for each block transfer","dmac_trifsrc_20":"Only software/event triggers","dmac_lvl_20":"Channel priority 0","dmac_evoe_20":false,"dmac_evie_20":false,"dmac_evact_20":"No action","dmac_stepsize_20":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_20":"Step size settings apply to the destination address","dmac_srcinc_20":false,"dmac_dstinc_20":false,"dmac_beatsize_20":"8-bit bus transfer","dmac_blockact_20":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_20":"Event generation disabled","dmac_channel_21_settings":false,"dmac_runstdby_21":false,"dmac_trigact_21":"One trigger required for each block transfer","dmac_trifsrc_21":"Only software/event triggers","dmac_lvl_21":"Channel priority 0","dmac_evoe_21":false,"dmac_evie_21":false,"dmac_evact_21":"No action","dmac_stepsize_21":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_21":"Step size settings apply to the destination address","dmac_srcinc_21":false,"dmac_dstinc_21":false,"dmac_beatsize_21":"8-bit bus transfer","dmac_blockact_21":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_21":"Event generation disabled","dmac_channel_22_settings":false,"dmac_runstdby_22":false,"dmac_trigact_22":"One trigger required for each block transfer","dmac_trifsrc_22":"Only software/event triggers","dmac_lvl_22":"Channel priority 0","dmac_evoe_22":false,"dmac_evie_22":false,"dmac_evact_22":"No action","dmac_stepsize_22":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_22":"Step size settings apply to the destination address","dmac_srcinc_22":false,"dmac_dstinc_22":false,"dmac_beatsize_22":"8-bit bus transfer","dmac_blockact_22":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_22":"Event generation disabled","dmac_channel_23_settings":false,"dmac_runstdby_23":false,"dmac_trigact_23":"One trigger required for each block transfer","dmac_trifsrc_23":"Only software/event triggers","dmac_lvl_23":"Channel priority 0","dmac_evoe_23":false,"dmac_evie_23":false,"dmac_evact_23":"No action","dmac_stepsize_23":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_23":"Step size settings apply to the destination address","dmac_srcinc_23":false,"dmac_dstinc_23":false,"dmac_beatsize_23":"8-bit bus transfer","dmac_blockact_23":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_23":"Event generation disabled","dmac_channel_24_settings":false,"dmac_runstdby_24":false,"dmac_trigact_24":"One trigger required for each block transfer","dmac_trifsrc_24":"Only software/event triggers","dmac_lvl_24":"Channel priority 0","dmac_evoe_24":false,"dmac_evie_24":false,"dmac_evact_24":"No action","dmac_stepsize_24":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_24":"Step size settings apply to the destination address","dmac_srcinc_24":false,"dmac_dstinc_24":false,"dmac_beatsize_24":"8-bit bus transfer","dmac_blockact_24":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_24":"Event generation disabled","dmac_channel_25_settings":false,"dmac_runstdby_25":false,"dmac_trigact_25":"One trigger required for each block transfer","dmac_trifsrc_25":"Only software/event triggers","dmac_lvl_25":"Channel priority 0","dmac_evoe_25":false,"dmac_evie_25":false,"dmac_evact_25":"No action","dmac_stepsize_25":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_25":"Step size settings apply to the destination address","dmac_srcinc_25":false,"dmac_dstinc_25":false,"dmac_beatsize_25":"8-bit bus transfer","dmac_blockact_25":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_25":"Event generation disabled","dmac_channel_26_settings":false,"dmac_runstdby_26":false,"dmac_trigact_26":"One trigger required for each block transfer","dmac_trifsrc_26":"Only software/event triggers","dmac_lvl_26":"Channel priority 0","dmac_evoe_26":false,"dmac_evie_26":false,"dmac_evact_26":"No action","dmac_stepsize_26":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_26":"Step size settings apply to the destination address","dmac_srcinc_26":false,"dmac_dstinc_26":false,"dmac_beatsize_26":"8-bit bus transfer","dmac_blockact_26":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_26":"Event generation disabled","dmac_channel_27_settings":false,"dmac_runstdby_27":false,"dmac_trigact_27":"One trigger required for each block transfer","dmac_trifsrc_27":"Only software/event triggers","dmac_lvl_27":"Channel priority 0","dmac_evoe_27":false,"dmac_evie_27":false,"dmac_evact_27":"No action","dmac_stepsize_27":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_27":"Step size settings apply to the destination address","dmac_srcinc_27":false,"dmac_dstinc_27":false,"dmac_beatsize_27":"8-bit bus transfer","dmac_blockact_27":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_27":"Event generation disabled","dmac_channel_28_settings":false,"dmac_runstdby_28":false,"dmac_trigact_28":"One trigger required for each block transfer","dmac_trifsrc_28":"Only software/event triggers","dmac_lvl_28":"Channel priority 0","dmac_evoe_28":false,"dmac_evie_28":false,"dmac_evact_28":"No action","dmac_stepsize_28":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_28":"Step size settings apply to the destination address","dmac_srcinc_28":false,"dmac_dstinc_28":false,"dmac_beatsize_28":"8-bit bus transfer","dmac_blockact_28":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_28":"Event generation disabled","dmac_channel_29_settings":false,"dmac_runstdby_29":false,"dmac_trigact_29":"One trigger required for each block transfer","dmac_trifsrc_29":"Only software/event triggers","dmac_lvl_29":"Channel priority 0","dmac_evoe_29":false,"dmac_evie_29":false,"dmac_evact_29":"No action","dmac_stepsize_29":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_29":"Step size settings apply to the destination address","dmac_srcinc_29":false,"dmac_dstinc_29":false,"dmac_beatsize_29":"8-bit bus transfer","dmac_blockact_29":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_29":"Event generation disabled","dmac_channel_30_settings":false,"dmac_runstdby_30":false,"dmac_trigact_30":"One trigger required for each block transfer","dmac_trifsrc_30":"Only software/event triggers","dmac_lvl_30":"Channel priority 0","dmac_evoe_30":false,"dmac_evie_30":false,"dmac_evact_30":"No action","dmac_stepsize_30":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_30":"Step size settings apply to the destination address","dmac_srcinc_30":false,"dmac_dstinc_30":false,"dmac_beatsize_30":"8-bit bus transfer","dmac_blockact_30":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_30":"Event generation disabled","dmac_channel_31_settings":false,"dmac_runstdby_31":false,"dmac_trigact_31":"One trigger required for each block transfer","dmac_trifsrc_31":"Only software/event triggers","dmac_lvl_31":"Channel priority 0","dmac_evoe_31":false,"dmac_evie_31":false,"dmac_evact_31":"No action","dmac_stepsize_31":"Next ADDR = ADDR + (BEATSIZE + 1) * 1","dmac_stepsel_31":"Step size settings apply to the destination address","dmac_srcinc_31":false,"dmac_dstinc_31":false,"dmac_beatsize_31":"8-bit bus transfer","dmac_blockact_31":"Channel will be disabled if it is the last block transfer in the transaction","dmac_evosel_31":"Event generation disabled"},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::DMAC::driver_definition::DMAC::HAL:HPL:DMAC","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC","module":"DMAC"}},{"functionality":null,"identifier":"RAMECC","user_label":"RAMECC","api":"HAL:HPL:RAMECC","configuration":{},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::RAMECC::driver_definition::RAMECC::HAL:HPL:RAMECC","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC","module":"RAMECC"}},{"functionality":null,"identifier":"OSCCTRL","user_label":"OSCCTRL","api":"HAL:HPL:OSCCTRL","configuration":{"enable_xosc0":false,"xosc0_frequency":12000000,"xosc0_arch_enable":false,"xosc0_arch_startup":"31us","xosc0_arch_swben":false,"xosc0_arch_cfden":false,"xosc0_arch_enalc":false,"xosc0_arch_lowbufgain":false,"xosc0_arch_ondemand":false,"xosc0_arch_runstdby":false,"xosc0_arch_xtalen":false,"enable_xosc1":true,"xosc1_frequency":12000000,"xosc1_arch_enable":true,"xosc1_arch_startup":"31us","xosc1_arch_swben":false,"xosc1_arch_cfden":false,"xosc1_arch_enalc":false,"xosc1_arch_lowbufgain":false,"xosc1_arch_ondemand":false,"xosc1_arch_runstdby":false,"xosc1_arch_xtalen":true,"enable_dfll":false,"dfll_ref_clock":"Generic clock generator 3","dfll_arch_enable":false,"dfll_arch_ondemand":false,"dfll_arch_runstdby":false,"dfll_arch_usbcrm":false,"dfll_arch_waitlock":true,"dfll_arch_bplckc":false,"dfll_arch_qldis":false,"dfll_arch_ccdis":false,"dfll_arch_llaw":false,"dfll_arch_stable":false,"dfll_mode":"Open Loop Mode","dfll_arch_cstep":1,"dfll_arch_fstep":1,"dfll_mul":0,"dfll_arch_calibration":false,"dfll_arch_coarse":31,"dfll_arch_fine":128,"enable_fdpll0":false,"fdpll0_ref_clock":"32kHz External Crystal Oscillator (XOSC32K)","fdpll0_arch_enable":false,"fdpll0_arch_ondemand":false,"fdpll0_arch_runstdby":false,"fdpll0_ldrfrac":13,"fdpll0_ldr":1463,"fdpll0_clock_div":0,"fdpll0_arch_dcoen":false,"fdpll0_clock_dcofilter":0,"fdpll0_arch_lbypass":false,"fdpll0_arch_ltime":"No time-out, automatic lock","fdpll0_arch_refclk":"XOSC32K clock reference","fdpll0_arch_wuf":false,"fdpll0_arch_filter":0,"enable_fdpll1":false,"fdpll1_ref_clock":"32kHz External Crystal Oscillator (XOSC32K)","fdpll1_arch_enable":false,"fdpll1_arch_ondemand":false,"fdpll1_arch_runstdby":false,"fdpll1_ldrfrac":13,"fdpll1_ldr":1463,"fdpll1_clock_div":0,"fdpll1_arch_dcoen":false,"fdpll1_clock_dcofilter":0,"fdpll1_arch_lbypass":false,"fdpll1_arch_ltime":"No time-out, automatic lock","fdpll1_arch_refclk":"XOSC32K clock reference","fdpll1_arch_wuf":false,"fdpll1_arch_filter":0},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::OSCCTRL::driver_definition::OSCCTRL::HAL:HPL:OSCCTRL","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL","module":"OSCCTRL"}},{"functionality":"ADC","identifier":"ADC_0","user_label":"ADC_0","api":"HAL:Driver:ADC_Sync","configuration":{"adc_resolution":"12-bit","adc_reference":"Internal bandgap reference","adc_prescaler":"Peripheral clock divided by 2","adc_freerunning_mode":false,"adc_differential_mode":false,"adc_pinmux_positive":"ADC AIN0 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3"}}}},{"functionality":"I2C","identifier":"I2C_0","user_label":"I2C_0","api":"HAL:Driver:I2C_Master_Sync","configuration":{"i2c_master_baud_rate":100000,"i2c_master_advanced":false,"i2c_master_arch_trise":215,"i2c_master_arch_mexttoen":false,"i2c_master_arch_sexttoen":false,"i2c_master_arch_lowtout":false,"i2c_master_arch_inactout":"Disabled","i2c_master_arch_sdahold":"300-600ns hold time","i2c_master_arch_runstdby":false,"i2c_master_arch_dbgstop":"Keep running"},"dependencies":{},"optional_signals":[],"variant":{"specification":"SDA=0, SCL=1","required_signals":[{"label":"SDA","identifier":"I2C_0:SDA","name":"SERCOM0/PAD/0","pad":"PA08","configuration":null,"definition":"","mode":"Enabled"},{"label":"SCL","identifier":"I2C_0:SCL","name":"SERCOM0/PAD/1","pad":"PA09","configuration":null,"definition":"","mode":"Enabled"}]},"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::SERCOM::driver_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync","module":"SERCOM0"},"clocks":{"domain_group":{"nodes":[{"name":"Slow","input":"Generic clock generator 3"},{"name":"Core","input":"Generic clock generator 0"}],"configuration":{"core_gclk_selection":"Generic clock generator 0","slow_gclk_selection":"Generic clock generator 3"}}}},{"functionality":"Timer","identifier":"TIMER_0","user_label":"TIMER_0","api":"HAL:Driver:Timer","configuration":{"rtc_arch_prescaler":"OFF(Peripheral clock divided by 1)","rtc_arch_comp_val":1,"rtc_event_control":false,"rtc_pereo0":false,"rtc_pereo1":false,"rtc_pereo2":false,"rtc_pereo3":false,"rtc_pereo4":false,"rtc_pereo5":false,"rtc_pereo6":false,"rtc_pereo7":false,"rtc_cmpeo0":false,"rtc_cmpeo1":false,"rtc_ovfeo":false,"rtc_tampereo":false,"rtc_tampevei":false},"dependencies":{},"optional_signals":[],"variant":null,"definition":{"base":"Atmel:SAMD51_Drivers:0.0.1::RTC::driver_definition::Timer::HAL:Driver:Timer","identifier":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RTC::driver_config_definition::Timer::HAL:Driver:Timer","module":"RTC"},"clocks":{"domain_group":{"nodes":[{"name":"RTC","input":"RTC source"}],"configuration":{"rtc_clk_selection":"RTC source"}}}}],"pads":[{"name":"PA00","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA00","mode":"Peripheral IO","configuration":null},{"name":"PA01","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA01","mode":"Peripheral IO","configuration":null},{"name":"PA04","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA04","mode":"Digital output","configuration":null},{"name":"PA05","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA05","mode":"Digital output","configuration":null},{"name":"PA06","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA06","mode":"Digital input","configuration":null},{"name":"PA08","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA08","mode":"Peripheral IO","configuration":null},{"name":"PA09","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA09","mode":"Peripheral IO","configuration":null},{"name":"PA24","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA24","mode":"Advanced","configuration":null},{"name":"PA25","user_label":"","definition":"Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA25","mode":"Advanced","configuration":null}]} diff --git a/atmel-samd/tools/update_asf.py b/atmel-samd/tools/update_asf.py new file mode 100644 index 0000000000000..20868532b4c18 --- /dev/null +++ b/atmel-samd/tools/update_asf.py @@ -0,0 +1,54 @@ +import requests +import zipfile +import os.path +import sys + +for chip in ["samd21", "samd51"]: + r = None + filename = chip + ".zip" + if not os.path.isfile(filename): + with open("tools/" + chip + ".json", "r") as project_json: + headers = {"content-type": "text/plain"} + r = requests.post("http://start.atmel.com/api/v1/generate/?format=atzip&compilers=[make]&file_name_base=My%20Project", headers=headers, data=project_json) + if not r.ok: + # Double check that the JSON is minified. If its not, you'll get a 404. + print(r.text) + sys.exit(1) + with open(filename, "wb") as out: + out.write(r.content) + z = zipfile.ZipFile(filename) + z.extractall("asf4/" + chip) + print(z) + + # delete the zip on success + #os.remove(filename) + +# Remove LITTLE_ENDIAN define from ASF because it conflicts with GCC. +for fn in os.listdir("asf4/samd51/include"): + contents = [] + path = "asf4/samd51/include/" + fn + if not os.path.isfile(path): + continue + with open(path, "r") as f: + for line in f: + if line.startswith("#define LITTLE_ENDIAN"): + contents.append("//" + line) + else: + contents.append(line) + with open(path, "w") as f: + for line in contents: + f.write(line) + +# Replace ASF's assert with asf_assert so it doesn't conflict with the C macro. + +for chip in ["samd21", "samd51"]: + contents = [] + path = "asf4/" + chip + "/hal/utils/include/utils_assert.h" + with open(path, "r") as f: + for line in f: + contents.append(line.replace(" assert(", " asf_assert(")) + with open(path, "w") as f: + for line in contents: + f.write(line) + +# samd21/samd21a/include is copied to samd21/include to match samd51 diff --git a/atmel-samd/usb.c b/atmel-samd/usb.c new file mode 100644 index 0000000000000..11be282a2bc20 --- /dev/null +++ b/atmel-samd/usb.c @@ -0,0 +1,256 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "usb.h" + +#include + +#include "hal/include/hal_gpio.h" +#include "usb/class/cdc/device/cdcdf_acm.h" +// #include "hiddf_mouse.h" +// #include "hiddf_keyboard.h" +#include "usb/class/hid/device/hiddf_generic.h" +#include "usb/class/composite/device/composite_desc.h" +#include "peripheral_clk_config.h" +#include "hpl/pm/hpl_pm_base.h" +#include "hpl/gclk/hpl_gclk_base.h" + +#include "lib/utils/interrupt_char.h" + +#include "supervisor/shared/autoreload.h" + +// Store received characters on our own so that we can filter control characters +// and act immediately on CTRL-C for example. + +// Receive buffer +static uint8_t usb_rx_buf[USB_RX_BUF_SIZE]; + +// Receive buffer head +static volatile uint8_t usb_rx_buf_head; + +// Receive buffer tail +static volatile uint8_t usb_rx_buf_tail; + +// Number of bytes in receive buffer +volatile uint8_t usb_rx_count; + +volatile bool mp_cdc_enabled = false; + +static uint8_t multi_desc_bytes[] = { + /* Device descriptors and Configuration descriptors list. */ + COMPOSITE_DESCES_LS_FS, +}; + +static struct usbd_descriptors multi_desc = {multi_desc_bytes, multi_desc_bytes + sizeof(multi_desc_bytes)}; + +/** Ctrl endpoint buffer */ +static uint8_t ctrl_buffer[64]; + +static void init_hardware(void) { + #ifdef SAMD21 + _pm_enable_bus_clock(PM_BUS_APBB, USB); + _pm_enable_bus_clock(PM_BUS_AHB, USB); + _gclk_enable_channel(USB_GCLK_ID, GCLK_CLKCTRL_GEN_GCLK0_Val); + #endif + + #ifdef SAMD51 + hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, CONF_GCLK_USB_SRC | GCLK_PCHCTRL_CHEN); + hri_mclk_set_AHBMASK_USB_bit(MCLK); + hri_mclk_set_APBBMASK_USB_bit(MCLK); + #endif + + usb_d_init(); + + gpio_set_pin_direction(PIN_PA24, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA24, false); + gpio_set_pin_pull_mode(PIN_PA24, GPIO_PULL_OFF); + gpio_set_pin_direction(PIN_PA25, GPIO_DIRECTION_OUT); + gpio_set_pin_level(PIN_PA25, false); + gpio_set_pin_pull_mode(PIN_PA25, GPIO_PULL_OFF); + #ifdef SAMD21 + gpio_set_pin_function(PIN_PA24, PINMUX_PA24G_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25G_USB_DP); + #endif + #ifdef SAMD51 + gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM); + gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); + #endif +} + +extern uint32_t *_usb_ep1_cache; +static bool usb_device_cb_bulk_out(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) +{ + volatile hal_atomic_t flags; + atomic_enter_critical(&flags); + // If our buffer can't fit the data received, then error out. + if (count > (uint8_t) (USB_RX_BUF_SIZE - usb_rx_count)) { + atomic_leave_critical(&flags); + return true; + } + + // We read the data but ignore it later. The data itself isn't correct but + // it does mark it as read so further data is received ok. + // TODO(tannewt): Get ASF4 fixed so the data is correct and then stop using + // _usb_ep1_cache directly below. + uint8_t buf[count]; + int32_t result = cdcdf_acm_read(buf, count); + if (result != ERR_NONE) { + return true; + } + + for (uint16_t i = 0; i < count; i++) { + uint8_t c = ((uint8_t*) &_usb_ep1_cache)[i]; + if (c == mp_interrupt_char) { + atomic_leave_critical(&flags); + mp_keyboard_interrupt(); + // Don't put the interrupt into the buffer, just continue. + return false; + } else { + // The count of characters present in receive buffer is + // incremented. + usb_rx_count++; + usb_rx_buf[usb_rx_buf_tail] = c; + usb_rx_buf_tail++; + if (usb_rx_buf_tail == USB_RX_BUF_SIZE) { + // Reached the end of buffer, revert back to beginning of + // buffer. + usb_rx_buf_tail = 0x00; + } + } + } + atomic_leave_critical(&flags); + + /* No error. */ + return false; +} + +static bool usb_device_cb_bulk_in(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) +{ + /* No error. */ + return false; +} + +static bool usb_device_cb_state_c(usb_cdc_control_signal_t state) +{ + //uint8_t buf[64]; + if (state.rs232.DTR) { + // Start Rx and throw away packet. + //cdcdf_acm_read((uint8_t *)buf, 64); + } + + /* No error. */ + return false; +} + +// static void usbd_sof_event(void) +// { +// // Triggers button state checks and HID response. +// } + +void init_usb(void) { + init_hardware(); + + usbdc_init(ctrl_buffer); + + /* usbdc_register_funcion inside */ + cdcdf_acm_init(); + // hiddf_mouse_init(); + // hiddf_keyboard_init(); + + int32_t result = usbdc_start(&multi_desc); + while (result != ERR_NONE) {} + usbdc_attach(); +} + +static inline bool cdc_enabled(void) { + if (mp_cdc_enabled) { + return true; + } + if (!cdcdf_acm_is_enabled()) { + return false; + } + cdcdf_acm_register_callback(CDCDF_ACM_CB_READ, (FUNC_PTR)usb_device_cb_bulk_out); + cdcdf_acm_register_callback(CDCDF_ACM_CB_WRITE, (FUNC_PTR)usb_device_cb_bulk_in); + cdcdf_acm_register_callback(CDCDF_ACM_CB_STATE_C, (FUNC_PTR)usb_device_cb_state_c); + mp_cdc_enabled = true; + + // Ignored read. + uint8_t buf[64]; + cdcdf_acm_read(buf, 64); + return true; +} + +bool usb_bytes_available(void) { + if (usb_rx_count == 0) { + cdc_enabled(); + return false; + } + return usb_rx_count > 0; +} + +int usb_read(void) { + if (!cdc_enabled() || usb_rx_count == 0) { + return 0; + } + + // Disable autoreload if someone is using the repl. + // TODO(tannewt): Check that we're actually in the REPL. It could be an + // input() call from a script. + autoreload_disable(); + + // Copy from head. + int data; + CRITICAL_SECTION_ENTER(); + data = usb_rx_buf[usb_rx_buf_head]; + usb_rx_buf_head++; + usb_rx_count--; + if ((USB_RX_BUF_SIZE) == usb_rx_buf_head) { + usb_rx_buf_head = 0; + } + CRITICAL_SECTION_LEAVE(); + + //usb_write((uint8_t *)&data, 1); + + return data; +} + +void usb_write(const char* buffer, uint32_t len) { + if (!cdc_enabled()) { + return; + } + int32_t result = cdcdf_acm_write((uint8_t *)buffer, len); + while (result == USB_BUSY) { + #ifdef MICROPY_VM_HOOK_LOOP + MICROPY_VM_HOOK_LOOP + #endif + result = cdcdf_acm_write((uint8_t *)buffer, len); + } + while (result != ERR_NONE) {} +} + +bool usb_connected(void) { + return cdc_enabled(); +} diff --git a/atmel-samd/usb.h b/atmel-samd/usb.h new file mode 100644 index 0000000000000..754331211d6a1 --- /dev/null +++ b/atmel-samd/usb.h @@ -0,0 +1,41 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef __MICROPY_INCLUDED_ATMEL_SAMD_USB_H__ +#define __MICROPY_INCLUDED_ATMEL_SAMD_USB_H__ + +#include +#include + +#define USB_RX_BUF_SIZE 128 + +void init_usb(void); +int usb_read(void); +void usb_write(const char* buffer, uint32_t len); +bool usb_bytes_available(void); +bool usb_connected(void); + +#endif // __MICROPY_INCLUDED_ATMEL_SAMD_USB_H__ diff --git a/docs/porting.rst b/docs/porting.rst new file mode 100644 index 0000000000000..f46160b7d7013 --- /dev/null +++ b/docs/porting.rst @@ -0,0 +1,68 @@ +We love CircuitPython and would love to see it come to more microcontroller +platforms. With 3.0 we've reworked CircuitPython to make it easier than ever to +add support. While there are some major differences between ports, this page +covers the similarities that make CircuitPython what it is and how that core +fits into a variety of microcontrollers. + +Architecture +============ + +There are three core pieces to CircuitPython: + +The first is the Python VM that the awesome MicroPython devs have created. +These VMs are written to be portable so there is not much needed when moving to +a different microcontroller, especially if it is ARM based. + +The second is the infrastructure around those VMs which provides super basic +operating system functionality such as initializing hardware, running USB, +prepping file systems and automatically running user code on boot. In +CircuitPython we've dubbed this component the supervisor because it monitors +and facilitates the VMs which run user Python code. Porting involves the +supervisor because many of the tasks it does while interfacing with the +hardware. Once its going though, the REPL works and debugging can migrate to a +Python based approach rather than C. + +The third core piece is the plethora of low level APIs that CircuitPython +provides as the foundation for higher level libraries including device drivers. +These APIs are called from within the running VMs through the Python interfaces +defined in ``shared-bindings``. These bindings rely on the underlying +``common_hal`` C API to implement the functionality needed for the Python API. +By splitting the two, we work to ensure standard functionality across which +means that libraries and examples apply across ports with minimal changes. + +Porting +======= + +Step 1: Getting building +------------------------ +The first step to porting to a new microcontroller is getting a build running. +The primary goal of it should be to get ``main.c`` compiling with the assistance +of the ``supervisor/supervisor.mk`` file. Port specific code should be isolated +to the port's directory (in the top level until the ``ports`` directory is +present). This includes the Makefile and any C library resources. Make sure +these resources are compatible with the MIT License of the rest of the code! + +Step 2: Init +-------------- +Once your build is setup, the next step should be to get your clocks going as +you expect from the supervisor. The supervisor calls `port_init` to allow for +initialization at the beginning of main. This function also has the ability to +request a safe mode state which prevents the supervisor from running user code +while still allowing access to the REPL and other resources. + +The core port initialization and reset methods are defined in +``supervisor/port.c`` and should be the first to be implemented. Its required +that they be implemented in the ``supervisor`` directory within the port +directory. That way, they are always in the expected place. + +The supervisor also uses three linker variables, ``_ezero``, ``_estack`` and +``_ebss`` to determine memory layout for stack overflow checking. + +Step 3: REPL +------------ +Getting the REPL going is a huge step. It involves a bunch of initialization to +be done correctly and is a good sign you are well on your porting way. To get +the REPL going you must implement the functions and definitions from +``supervisor/serial.h`` with a corresponding ``supervisor/serial.c`` in the port +directory. This involves sending and receiving characters over some sort of +serial connection. It could be UART or USB for example. diff --git a/main.c b/main.c new file mode 100644 index 0000000000000..dd9b1bd6e67a6 --- /dev/null +++ b/main.c @@ -0,0 +1,341 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016-2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include +#include + +#include "extmod/vfs.h" +#include "extmod/vfs_fat.h" + +#include "py/nlr.h" +#include "py/compile.h" +#include "py/frozenmod.h" +#include "py/mphal.h" +#include "py/runtime.h" +#include "py/repl.h" +#include "py/gc.h" +#include "py/stackctrl.h" + +#include "lib/mp-readline/readline.h" +#include "lib/utils/pyexec.h" + +#include "mpconfigboard.h" +#include "supervisor/port.h" +#include "supervisor/filesystem.h" +// TODO(tannewt): Figure out how to choose language at compile time. +#include "supervisor/messages/en-US.h" +#include "supervisor/shared/autoreload.h" +#include "supervisor/shared/rgb_led_status.h" +#include "supervisor/serial.h" + +void do_str(const char *src, mp_parse_input_kind_t input_kind) { + mp_lexer_t *lex = mp_lexer_new_from_str_len(MP_QSTR__lt_stdin_gt_, src, strlen(src), 0); + if (lex == NULL) { + //printf("MemoryError: lexer could not allocate memory\n"); + return; + } + + nlr_buf_t nlr; + if (nlr_push(&nlr) == 0) { + qstr source_name = lex->source_name; + mp_parse_tree_t parse_tree = mp_parse(lex, input_kind); + mp_obj_t module_fun = mp_compile(&parse_tree, source_name, MP_EMIT_OPT_NONE, true); + mp_call_function_0(module_fun); + nlr_pop(); + } else { + // uncaught exception + mp_obj_print_exception(&mp_plat_print, (mp_obj_t)nlr.ret_val); + } +} + +static char heap[PORT_HEAP_SIZE]; + +void reset_mp(void) { + reset_status_led(); + new_status_color(0x8f008f); + autoreload_stop(); + + // Sync the file systems in case any used RAM from the GC to cache. As soon + // as we re-init the GC all bets are off on the cache. + filesystem_flush(); + + // Clear the readline history. It references the heap we're about to destroy. + readline_init0(); + + #if MICROPY_ENABLE_GC + gc_init(heap, heap + sizeof(heap)); + #endif + mp_init(); + mp_obj_list_init(mp_sys_path, 0); + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_)); // current dir (or base dir of the script) + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_)); + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_lib)); + // Frozen modules are in their own pseudo-dir, e.g., ".frozen". + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_FROZEN_FAKE_DIR_QSTR)); + + mp_obj_list_init(mp_sys_argv, 0); +} + +bool maybe_run(const char* filename, pyexec_result_t* exec_result) { + mp_import_stat_t stat = mp_import_stat(filename); + if (stat != MP_IMPORT_STAT_FILE) { + return false; + } + serial_write(filename); + serial_write(MSG_OUTPUT_SUFFIX); + pyexec_file(filename, exec_result); + return true; +} + +bool start_mp(safe_mode_t safe_mode) { + bool serial_connected_at_start = serial_connected(); + #ifdef CIRCUITPY_AUTORELOAD_DELAY_MS + if (serial_connected_at_start) { + serial_write(MSG_NEWLINE); + if (autoreload_is_enabled()) { + serial_write(MSG_AUTORELOAD_ON); + } else if (safe_mode != NO_SAFE_MODE) { + serial_write(MSG_SAFE_MODE_ON); + } else if (!autoreload_is_enabled()) { + serial_write(MSG_AUTORELOAD_OFF); + } + } + #endif + + pyexec_result_t result; + bool found_main = false; + if (safe_mode != NO_SAFE_MODE) { + serial_write(MSG_SAFE_MODE_NO_MAIN); + } else { + new_status_color(MAIN_RUNNING); + found_main = maybe_run("code.txt", &result) || + maybe_run("code.py", &result) || + maybe_run("main.py", &result) || + maybe_run("main.txt", &result); + reset_status_led(); + + if (result.return_code & PYEXEC_FORCED_EXIT) { + return reload_next_character; + } + } + + // Wait for connection or character. + bool serial_connected_before_animation = false; + rgb_status_animation_t animation; + prep_rgb_status_animation(&result, found_main, &animation); + while (true) { + #ifdef MICROPY_VM_HOOK_LOOP + MICROPY_VM_HOOK_LOOP + #endif + if (reload_next_character) { + return true; + } + if (serial_connected() && serial_bytes_available()) { + // Skip REPL if reload was requested. + return serial_read() == CHAR_CTRL_D; + } + + if (!serial_connected_before_animation && serial_connected()) { + if (serial_connected_at_start) { + serial_write(MSG_NEWLINE MSG_NEWLINE); + } + + if (!serial_connected_at_start) { + if (autoreload_is_enabled()) { + serial_write(MSG_AUTORELOAD_ON); + } else { + serial_write(MSG_AUTORELOAD_OFF); + } + } + // Output a user safe mode string if its set. + #ifdef BOARD_USER_SAFE_MODE + if (safe_mode == USER_SAFE_MODE) { + serial_write(MSG_NEWLINE MSG_SAFE_MODE_USER_REQUESTED); + serial_write(BOARD_USER_SAFE_MODE_ACTION); + serial_write(MSG_NEWLINE MSG_SAFE_MODE_USER_EXIT); + serial_write(BOARD_USER_SAFE_MODE_ACTION); + serial_write(MSG_NEWLINE); + } else + #endif + if (safe_mode != NO_SAFE_MODE) { + serial_write(MSG_NEWLINE MSG_BAD_SAFE_MODE MSG_NEWLINE); + if (safe_mode == HARD_CRASH) { + serial_write(MSG_SAFE_MODE_CRASH MSG_NEWLINE); + serial_write(MSG_SAFE_MODE_FILE_ISSUE MSG_NEWLINE); + serial_write(MSG_SAFE_MODE_ISSUE_LINK MSG_NEWLINE); + } else if (safe_mode == BROWNOUT) { + serial_write(MSG_SAFE_MODE_BROWN_OUT_LINE_1 MSG_NEWLINE); + serial_write(MSG_SAFE_MODE_BROWN_OUT_LINE_2 MSG_NEWLINE); + } + } + serial_write(MSG_NEWLINE MSG_WAIT_BEFORE_REPL MSG_NEWLINE); + } + if (serial_connected_before_animation && !serial_connected()) { + serial_connected_at_start = false; + } + serial_connected_before_animation = serial_connected(); + + tick_rgb_status_animation(&animation); + } +} + +int __attribute__((used)) main(void) { + // initialise the cpu and peripherals + safe_mode_t safe_mode = port_init(); + + rgb_led_status_init(); + + // Stack limit should be less than real stack size, so we have a chance + // to recover from limit hit. (Limit is measured in bytes.) + mp_stack_ctrl_init(); + mp_stack_set_limit((char*)&_estack - (char*)&_ebss - 1024); + +#if MICROPY_MAX_STACK_USAGE + // _ezero (same as _ebss) is an int, so start 4 bytes above it. + mp_stack_set_bottom(&_ezero + 1); + mp_stack_fill_with_sentinel(); +#endif + + filesystem_init(); + + // Reset everything and prep MicroPython to run boot.py. + reset_port(); + reset_board(); + reset_mp(); + + // Turn on autoreload by default but before boot.py in case it wants to change it. + autoreload_enable(); + + // By default our internal flash is readonly to local python code and + // writeable over USB. Set it here so that boot.py can change it. + filesystem_default_writeable(false); + + // If not in safe mode, run boot before initing USB and capture output in a + // file. + if (filesystem_present() && safe_mode == NO_SAFE_MODE && MP_STATE_VM(vfs_mount_table) != NULL) { + new_status_color(BOOT_RUNNING); + #ifdef CIRCUITPY_BOOT_OUTPUT_FILE + // Since USB isn't up yet we can cheat and let ourselves write the boot + // output file. + filesystem_default_writeable(true); + FIL file_pointer; + boot_output_file = &file_pointer; + f_open(&((fs_user_mount_t *) MP_STATE_VM(vfs_mount_table)->obj)->fatfs, + boot_output_file, CIRCUITPY_BOOT_OUTPUT_FILE, FA_WRITE | FA_CREATE_ALWAYS); + filesystem_default_writeable(false); + #endif + + // TODO(tannewt): Re-add support for flashing boot error output. + bool found_boot = maybe_run("settings.txt", NULL) || + maybe_run("settings.py", NULL) || + maybe_run("boot.py", NULL) || + maybe_run("boot.txt", NULL); + (void) found_boot; + + #ifdef CIRCUITPY_BOOT_OUTPUT_FILE + f_close(boot_output_file); + filesystem_flush(); + boot_output_file = NULL; + #endif + + // Reset to remove any state that boot.py setup. It should only be used to + // change internal state thats not in the heap. + reset_port(); + reset_mp(); + } + + // Start serial after giving boot.py a chance to tweak behavior. + serial_init(); + + // Boot script is finished, so now go into REPL/main mode. + int exit_code = PYEXEC_FORCED_EXIT; + bool skip_repl = true; + bool first_run = true; + for (;;) { + if (!skip_repl) { + // The REPL mode can change, or it can request a reload. + bool autoreload_on = autoreload_is_enabled(); + autoreload_disable(); + new_status_color(REPL_RUNNING); + if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) { + exit_code = pyexec_raw_repl(); + } else { + exit_code = pyexec_friendly_repl(); + } + if (autoreload_on) { + autoreload_enable(); + } + reset_port(); + reset_board(); + reset_mp(); + } + if (exit_code == PYEXEC_FORCED_EXIT) { + if (!first_run) { + serial_write(MSG_SOFT_REBOOT MSG_NEWLINE); + } + first_run = false; + skip_repl = start_mp(safe_mode); + reset_port(); + reset_board(); + reset_mp(); + } else if (exit_code != 0) { + break; + } + } + mp_deinit(); + return 0; +} + +void gc_collect(void) { + // WARNING: This gc_collect implementation doesn't try to get root + // pointers from CPU registers, and thus may function incorrectly. + void *dummy; + gc_collect_start(); + // This collects root pointers from the VFS mount table. Some of them may + // have lost their references in the VM even though they are mounted. + gc_collect_root((void**)&MP_STATE_VM(vfs_mount_table), sizeof(mp_vfs_mount_t) / sizeof(mp_uint_t)); + // This naively collects all object references from an approximate stack + // range. + gc_collect_root(&dummy, ((mp_uint_t)&_estack - (mp_uint_t)&dummy) / sizeof(mp_uint_t)); + gc_collect_end(); +} + +void NORETURN nlr_jump_fail(void *val) { + HardFault_Handler(); + while (true) {} +} + +void NORETURN __fatal_error(const char *msg) { + HardFault_Handler(); + while (true) {} +} + +#ifndef NDEBUG +void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) { + printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line); + __fatal_error("Assertion failed"); +} +#endif diff --git a/supervisor/filesystem.h b/supervisor/filesystem.h new file mode 100644 index 0000000000000..38923c6f598b0 --- /dev/null +++ b/supervisor/filesystem.h @@ -0,0 +1,37 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_SUPERVISOR_FILESYSTEM_H +#define MICROPY_INCLUDED_SUPERVISOR_FILESYSTEM_H + +#include + +void filesystem_init(void); +void filesystem_flush(void); +void filesystem_default_writeable(bool writeable); +bool filesystem_present(void); + +#endif // MICROPY_INCLUDED_SUPERVISOR_FILESYSTEM_H diff --git a/supervisor/messages/default.h b/supervisor/messages/default.h new file mode 100644 index 0000000000000..b69d49537af1d --- /dev/null +++ b/supervisor/messages/default.h @@ -0,0 +1,95 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_SUPERVISOR_MESSAGES_DEFAULT_H +#define MICROPY_SUPERVISOR_MESSAGES_DEFAULT_H + +#ifndef MSG_OUTPUT_SUFFIX +#define MSG_OUTPUT_SUFFIX " output:\r\n" +#endif + +#ifndef MSG_NEWLINE +#define MSG_NEWLINE "\r\n" +#endif + +#ifndef MSG_AUTORELOAD_ON +#define MSG_AUTORELOAD_ON "Auto-reload is on. Simply save files over USB to run them or enter REPL to disable.\r\n" +#endif + +#ifndef MSG_AUTORELOAD_OFF +#define MSG_AUTORELOAD_OFF "Auto-reload is off.\r\n" +#endif + +#ifndef MSG_SAFE_MODE_ON +#define MSG_SAFE_MODE_ON "Running in safe mode! Auto-reload is off.\r\n" +#endif + +#ifndef MSG_SAFE_MODE_NO_MAIN +#define MSG_SAFE_MODE_NO_MAIN "Running in safe mode! Not running saved code.\r\n" +#endif + +#ifndef MSG_SAFE_MODE_USER_REQUESTED +#define MSG_SAFE_MODE_USER_REQUESTED "You requested starting safe mode by " +#endif + +#ifndef MSG_SAFE_MODE_USER_EXIT +#define MSG_SAFE_MODE_USER_EXIT "To exit, please reset the board without " +#endif + +#ifndef MSG_BAD_SAFE_MODE +#define MSG_BAD_SAFE_MODE "You are running in safe mode which means something really bad happened." +#endif + +#ifndef MSG_SAFE_MODE_CRASH +#define MSG_SAFE_MODE_CRASH "Looks like our core CircuitPython code crashed hard. Whoops!" +#endif + +#ifndef MSG_SAFE_MODE_FILE_ISSUE +#define MSG_SAFE_MODE_FILE_ISSUE "Please file an issue here with the contents of your CIRCUITPY drive:" +#endif + +#ifndef MSG_SAFE_MODE_ISSUE_LINK +#define MSG_SAFE_MODE_ISSUE_LINK "https://github.com/adafruit/circuitpython/issues" +#endif + +#ifndef MSG_SAFE_MODE_BROWN_OUT_LINE_1 +#define MSG_SAFE_MODE_BROWN_OUT_LINE_1 "The microcontroller's power dipped. Please make sure your power supply provides" +#endif + +#ifndef MSG_SAFE_MODE_BROWN_OUT_LINE_2 +#define MSG_SAFE_MODE_BROWN_OUT_LINE_2 "enough power for the whole circuit and press reset (after ejecting CIRCUITPY)." +#endif + +#ifndef MSG_WAIT_BEFORE_REPL +#define MSG_WAIT_BEFORE_REPL "Press any key to enter the REPL. Use CTRL-D to reload." +#endif + +// Be careful, some tools depend on this. +#ifndef MSG_SOFT_REBOOT +#define MSG_SOFT_REBOOT "soft reboot" +#endif + +#endif // MICROPY_SUPERVISOR_MESSAGES_DEFAULT_H diff --git a/supervisor/messages/en-US.h b/supervisor/messages/en-US.h new file mode 100644 index 0000000000000..d31e3b67ae1ac --- /dev/null +++ b/supervisor/messages/en-US.h @@ -0,0 +1,35 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_SUPERVISOR_MESSAGES_EN_US_H +#define MICROPY_SUPERVISOR_MESSAGES_EN_US_H + +// Place override messages here. + +// Leave this at the bottom. +#include "supervisor/messages/default.h" + +#endif // MICROPY_SUPERVISOR_MESSAGES_EN_US_H diff --git a/supervisor/port.h b/supervisor/port.h new file mode 100644 index 0000000000000..465b5a27d06f6 --- /dev/null +++ b/supervisor/port.h @@ -0,0 +1,56 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016-2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_SUPERVISOR_PORT_H +#define MICROPY_INCLUDED_SUPERVISOR_PORT_H + +#include "py/mpconfig.h" + +#ifndef PORT_HEAP_SIZE +#error "Please define PORT_HEAP_SIZE to specify heap size in bytes." +#endif + +typedef enum { + NO_SAFE_MODE = 0, + BROWNOUT, + HARD_CRASH, + USER_SAFE_MODE, +} safe_mode_t; + +// Provided by the linker; +extern uint32_t _ezero; + +// This file defines core methods that must be implemented by a port. +extern uint32_t _estack; + +// Stored at the end of the bss section (which includes the heap). +extern uint32_t _ebss; + +safe_mode_t port_init(void); +void reset_port(void); +void reset_board(void); + +#endif // MICROPY_INCLUDED_SUPERVISOR_PORT_H diff --git a/supervisor/serial.h b/supervisor/serial.h new file mode 100644 index 0000000000000..9446ee71cf25c --- /dev/null +++ b/supervisor/serial.h @@ -0,0 +1,39 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_SUPERVISOR_SERIAL_H +#define MICROPY_INCLUDED_SUPERVISOR_SERIAL_H + +#include +#include + +void serial_init(void); +void serial_write(const char* text); +char serial_read(void); +bool serial_bytes_available(void); +bool serial_connected(void); + +#endif // MICROPY_INCLUDED_SUPERVISOR_SERIAL_H diff --git a/atmel-samd/autoreload.c b/supervisor/shared/autoreload.c similarity index 97% rename from atmel-samd/autoreload.c rename to supervisor/shared/autoreload.c index 86de646e9224b..b1d0f05a9445d 100644 --- a/atmel-samd/autoreload.c +++ b/supervisor/shared/autoreload.c @@ -26,7 +26,6 @@ #include "autoreload.h" -#include "asf/sam0/drivers/tc/tc_interrupt.h" #include "lib/utils/interrupt_char.h" #include "py/mphal.h" diff --git a/atmel-samd/autoreload.h b/supervisor/shared/autoreload.h similarity index 90% rename from atmel-samd/autoreload.h rename to supervisor/shared/autoreload.h index 10ff364643c68..bc3c6d21d817a 100644 --- a/atmel-samd/autoreload.h +++ b/supervisor/shared/autoreload.h @@ -24,8 +24,8 @@ * THE SOFTWARE. */ -#ifndef MICROPY_INCLUDED_ATMEL_SAMD_AUTORELOAD_H -#define MICROPY_INCLUDED_ATMEL_SAMD_AUTORELOAD_H +#ifndef MICROPY_INCLUDED_SUPERVISOR_AUTORELOAD_H +#define MICROPY_INCLUDED_SUPERVISOR_AUTORELOAD_H #include @@ -39,4 +39,4 @@ void autoreload_enable(void); void autoreload_disable(void); bool autoreload_is_enabled(void); -#endif // MICROPY_INCLUDED_ATMEL_SAMD_AUTORELOAD_H +#endif // MICROPY_INCLUDED_SUPERVISOR_AUTORELOAD_H diff --git a/atmel-samd/rgb_led_colors.h b/supervisor/shared/rgb_led_colors.h similarity index 100% rename from atmel-samd/rgb_led_colors.h rename to supervisor/shared/rgb_led_colors.h diff --git a/supervisor/shared/rgb_led_status.c b/supervisor/shared/rgb_led_status.c new file mode 100644 index 0000000000000..15150f18be92f --- /dev/null +++ b/supervisor/shared/rgb_led_status.c @@ -0,0 +1,316 @@ +/* + * This file is part of the Micro Python project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "mphalport.h" +#include "common-hal/microcontroller/Pin.h" +#include "rgb_led_status.h" +#include "pins.h" + +uint8_t rgb_status_brightness = 255; +#ifdef MICROPY_HW_NEOPIXEL +#include "shared-bindings/digitalio/DigitalInOut.h" +#include "shared-bindings/neopixel_write/__init__.h" +static uint8_t status_neopixel_color[3]; +static digitalio_digitalinout_obj_t status_neopixel; +#endif + + +#if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) + +static uint8_t status_apa102_color[12] = {0, 0, 0, 0, 0xff, 0, 0, 0}; +#ifdef CIRCUITPY_BITBANG_APA102 +#include "shared-bindings/bitbangio/SPI.h" +#include "shared-module/bitbangio/types.h" +static bitbangio_spi_obj_t status_apa102; +#else +#include "shared-bindings/busio/SPI.h" +busio_spi_obj_t status_apa102; +#endif +#endif + +#if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) +static uint32_t current_status_color = 0; +#endif + +void rgb_led_status_init() { + #ifdef MICROPY_HW_NEOPIXEL + common_hal_digitalio_digitalinout_construct(&status_neopixel, MICROPY_HW_NEOPIXEL); + // Pretend we aren't using the pins. digitalio.DigitalInOut + // will mark them as used. + neopixel_in_use = false; + common_hal_digitalio_digitalinout_switch_to_output(&status_neopixel, false, DRIVE_MODE_PUSH_PULL); + #endif + #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) + #ifdef CIRCUITPY_BITBANG_APA102 + shared_module_bitbangio_spi_construct(&status_apa102, + MICROPY_HW_APA102_SCK, + MICROPY_HW_APA102_MOSI, + mp_const_none); + #else + if (status_apa102.current_baudrate > 0) { + // Don't use spi_deinit because that leads to infinite + // recursion because reset_pin may call + // rgb_led_status_init. + spi_disable(&status_apa102.spi_master_instance); + } + common_hal_busio_spi_construct(&status_apa102, + MICROPY_HW_APA102_SCK, + MICROPY_HW_APA102_MOSI, + mp_const_none); + #endif + // Pretend we aren't using the pins. bitbangio.SPI will + // mark them as used. + apa102_mosi_in_use = false; + apa102_sck_in_use = false; + #ifdef CIRCUITPY_BITBANG_APA102 + shared_module_bitbangio_spi_try_lock(&status_apa102); + shared_module_bitbangio_spi_configure(&status_apa102, 100000, 0, 1, 8); + #else + common_hal_busio_spi_try_lock(&status_apa102); + common_hal_busio_spi_configure(&status_apa102, 100000, 0, 1, 8); + #endif + #endif + + #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) + // Force a write of the current status color. + uint32_t rgb = current_status_color; + current_status_color = 0; + new_status_color(rgb); + #endif +} + +void reset_status_led() { + #ifdef MICROPY_HW_NEOPIXEL + reset_pin(MICROPY_HW_NEOPIXEL->pin); + #endif + #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) + reset_pin(MICROPY_HW_APA102_MOSI->pin); + reset_pin(MICROPY_HW_APA102_SCK->pin); + #endif +} + +void new_status_color(uint32_t rgb) { + #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) + if (current_status_color == rgb) { + return; + } + uint32_t rgb_adjusted = color_brightness(rgb, rgb_status_brightness); + current_status_color = rgb_adjusted; + #endif + + #ifdef MICROPY_HW_NEOPIXEL + if (neopixel_in_use) { + return; + } + status_neopixel_color[0] = (rgb_adjusted >> 8) & 0xff; + status_neopixel_color[1] = (rgb_adjusted >> 16) & 0xff; + status_neopixel_color[2] = rgb_adjusted & 0xff; + common_hal_neopixel_write(&status_neopixel, status_neopixel_color, 3); + #endif + #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) + if (apa102_mosi_in_use || apa102_sck_in_use) { + return; + } + status_apa102_color[5] = rgb_adjusted & 0xff; + status_apa102_color[6] = (rgb_adjusted >> 8) & 0xff; + status_apa102_color[7] = (rgb_adjusted >> 16) & 0xff; + + #ifdef CIRCUITPY_BITBANG_APA102 + shared_module_bitbangio_spi_write(&status_apa102, status_apa102_color, 8); + #else + common_hal_busio_spi_write(&status_apa102, status_apa102_color, 8); + #endif + #endif +} + +void temp_status_color(uint32_t rgb) { + #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) + uint32_t rgb_adjusted = rgb; + rgb_adjusted = color_brightness(rgb, rgb_status_brightness); + #endif + #ifdef MICROPY_HW_NEOPIXEL + if (neopixel_in_use) { + return; + } + uint8_t colors[3] = {(rgb_adjusted >> 8) & 0xff, (rgb_adjusted >> 16) & 0xff, rgb_adjusted & 0xff}; + common_hal_neopixel_write(&status_neopixel, colors, 3); + #endif + #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) + if (apa102_mosi_in_use || apa102_sck_in_use) { + return; + } + uint8_t colors[12] = {0, 0, 0, 0, 0xff, rgb_adjusted & 0xff, (rgb_adjusted >> 8) & 0xff, (rgb_adjusted >> 16) & 0xff, 0x0, 0x0, 0x0, 0x0}; + #ifdef CIRCUITPY_BITBANG_APA102 + shared_module_bitbangio_spi_write(&status_apa102, colors, 12); + #else + common_hal_busio_spi_write(&status_apa102, colors, 12); + #endif + #endif +} + +void clear_temp_status() { + #ifdef MICROPY_HW_NEOPIXEL + common_hal_neopixel_write(&status_neopixel, status_neopixel_color, 3); + #endif + #if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) + #ifdef CIRCUITPY_BITBANG_APA102 + shared_module_bitbangio_spi_write(&status_apa102, status_apa102_color, 8); + #else + common_hal_busio_spi_write(&status_apa102, status_apa102_color, 8); + #endif + #endif +} + +uint32_t color_brightness(uint32_t color, uint8_t brightness) { + #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) + uint32_t result = ((color & 0xff0000) * brightness / 255) & 0xff0000; + result += ((color & 0xff00) * brightness / 255) & 0xff00; + result += ((color & 0xff) * brightness / 255) & 0xff; + return result; + #else + return color; + #endif +} + +void set_rgb_status_brightness(uint8_t level){ + rgb_status_brightness = level; +} + +void prep_rgb_status_animation(const pyexec_result_t* result, bool found_main, rgb_status_animation_t* status) { + #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) + new_status_color(ALL_DONE); + status->pattern_start = ticks_ms; + + uint32_t total_exception_cycle = 0; + status->ones = result->exception_line % 10; + status->ones += status->ones > 0 ? 1 : 0; + status->tens = (result->exception_line / 10) % 10; + status->tens += status->tens > 0 ? 1 : 0; + status->hundreds = (result->exception_line / 100) % 10; + status->hundreds += status->hundreds > 0 ? 1 : 0; + status->thousands = (result->exception_line / 1000) % 10; + status->thousands += status->thousands > 0 ? 1 : 0; + status->digit_sum = status->ones + status->tens + status->hundreds + status->thousands; + uint8_t num_places = 0; + uint16_t line = result->exception_line; + for (int i = 0; i < 4; i++) { + if ((line % 10) > 0) { + num_places++; + } + line /= 10; + } + status->ok = result->return_code != PYEXEC_EXCEPTION; + if (!status->ok) { + status->total_exception_cycle = EXCEPTION_TYPE_LENGTH_MS * 3 + LINE_NUMBER_TOGGLE_LENGTH * digit_sum + LINE_NUMBER_TOGGLE_LENGTH * num_places; + } + if (mp_obj_is_subclass_fast(result->exception_type, &mp_type_IndentationError)) { + status->exception_color = INDENTATION_ERROR; + } else if (mp_obj_is_subclass_fast(result->exception_type, &mp_type_SyntaxError)) { + status->exception_color = SYNTAX_ERROR; + } else if (mp_obj_is_subclass_fast(result->exception_type, &mp_type_NameError)) { + status->exception_color = NAME_ERROR; + } else if (mp_obj_is_subclass_fast(result->exception_type, &mp_type_OSError)) { + status->exception_color = OS_ERROR; + } else if (mp_obj_is_subclass_fast(result->exception_type, &mp_type_ValueError)) { + status->exception_color = VALUE_ERROR; + } else { + status->exception_color = OTHER_ERROR; + } + #endif +} + +void tick_rgb_status_animation(rgb_status_animation_t* status) { + #if defined(MICROPY_HW_NEOPIXEL) || (defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK)) + uint32_t tick_diff = ticks_ms - pattern_start; + if (status->ok) { + // All is good. Ramp ALL_DONE up and down. + if (tick_diff > ALL_GOOD_CYCLE_MS) { + pattern_start = ticks_ms; + tick_diff = 0; + } + + uint16_t brightness = tick_diff * 255 / (ALL_GOOD_CYCLE_MS / 2); + if (brightness > 255) { + brightness = 511 - brightness; + } + if (safe_mode == NO_SAFE_MODE) { + new_status_color(color_brightness(ALL_DONE, brightness)); + } else { + new_status_color(color_brightness(SAFE_MODE, brightness)); + } + } else { + if (tick_diff > total_exception_cycle) { + pattern_start = ticks_ms; + tick_diff = 0; + } + // First flash the file color. + if (tick_diff < EXCEPTION_TYPE_LENGTH_MS) { + if (status->found_main) { + new_status_color(MAIN_RUNNING); + } else { + new_status_color(BOOT_RUNNING); + } + // Next flash the exception color. + } else if (tick_diff < EXCEPTION_TYPE_LENGTH_MS * 2) { + new_status_color(exception_color); + // Finally flash the line number digits from highest to lowest. + // Zeroes will not produce a flash but can be read by the absence of + // a color from the sequence. + } else if (tick_diff < (EXCEPTION_TYPE_LENGTH_MS * 2 + LINE_NUMBER_TOGGLE_LENGTH * digit_sum)) { + uint32_t digit_diff = tick_diff - EXCEPTION_TYPE_LENGTH_MS * 2; + if ((digit_diff % LINE_NUMBER_TOGGLE_LENGTH) < (LINE_NUMBER_TOGGLE_LENGTH / 2)) { + new_status_color(BLACK); + } else if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * thousands) { + if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH) { + new_status_color(BLACK); + } else { + new_status_color(THOUSANDS); + } + } else if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds)) { + if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + 1)) { + new_status_color(BLACK); + } else { + new_status_color(HUNDREDS); + } + } else if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds + tens)) { + if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds + 1)) { + new_status_color(BLACK); + } else { + new_status_color(TENS); + } + } else { + if (digit_diff < LINE_NUMBER_TOGGLE_LENGTH * (thousands + hundreds + tens + 1)) { + new_status_color(BLACK); + } else { + new_status_color(ONES); + } + } + } else { + new_status_color(BLACK); + } + } + #endif +} diff --git a/supervisor/shared/rgb_led_status.h b/supervisor/shared/rgb_led_status.h new file mode 100644 index 0000000000000..2ea00f4fef6f6 --- /dev/null +++ b/supervisor/shared/rgb_led_status.h @@ -0,0 +1,73 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_SUPERVISOR_RGB_LED_STATUS_H +#define MICROPY_INCLUDED_SUPERVISOR_RGB_LED_STATUS_H + +#include +#include + +#include "lib/utils/pyexec.h" + +#include "mpconfigport.h" +#include "rgb_led_colors.h" + +// Overall, the time module must be implemented. +// To work with a DotStar, one must have MICROPY_HW_APA102_SCK and +// MICROPY_HW_APA102_MOSI defined and bitbangio.SPI or busio.SPI implemented. +// To work with a NeoPixel, one must have MICROPY_HW_NEOPIXEL defined and +// neopixel_write implemented. + +#if defined(MICROPY_HW_APA102_MOSI) && defined(MICROPY_HW_APA102_SCK) && !defined(CIRCUITPY_BITBANG_APA102) +#include "common-hal/busio/SPI.h" +extern busio_spi_obj_t status_apa102; +#endif + +void rgb_led_status_init(void); +void reset_status_led(void); +void new_status_color(uint32_t rgb); +void temp_status_color(uint32_t rgb); +void clear_temp_status(void); + +uint32_t color_brightness(uint32_t color, uint8_t brightness); +void set_rgb_status_brightness(uint8_t level); + +typedef struct { + bool ok; + uint32_t pattern_start; + uint32_t total_exception_cycle; + uint8_t ones; + uint8_t tens; + uint8_t hundreds; + uint8_t thousands; + uint32_t exception_color; + bool found_main; +} rgb_status_animation_t; + +void prep_rgb_status_animation(const pyexec_result_t* result, bool found_main, rgb_status_animation_t* status); +void tick_rgb_status_animation(rgb_status_animation_t* status); + +#endif // MICROPY_INCLUDED_SUPERVISOR_RGB_LED_STATUS_H diff --git a/supervisor/stub/filesystem.c b/supervisor/stub/filesystem.c new file mode 100644 index 0000000000000..462ee62a4ef79 --- /dev/null +++ b/supervisor/stub/filesystem.c @@ -0,0 +1,40 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "supervisor/filesystem.h" + +void filesystem_init(void) { +} + +void filesystem_flush(void) { +} + +void filesystem_default_writeable(bool writeable) { +} + +bool filesystem_present(void) { + return false; +} diff --git a/supervisor/stub/serial.c b/supervisor/stub/serial.c new file mode 100644 index 0000000000000..4f0e11873a2db --- /dev/null +++ b/supervisor/stub/serial.c @@ -0,0 +1,46 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Scott Shawcroft for Adafruit Industries + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "supervisor/serial.h" + +void serial_init(void) { + +} + +bool serial_connected(void) { + return false; +} + +char serial_read(void) { + return 0; +} + +bool serial_bytes_available(void) { + return false; +} + +void serial_write(const char* text) { +} diff --git a/supervisor/supervisor.mk b/supervisor/supervisor.mk new file mode 100644 index 0000000000000..f67439a97e60f --- /dev/null +++ b/supervisor/supervisor.mk @@ -0,0 +1,19 @@ +SRC_SUPERVISOR = \ + main.c \ + supervisor/port.c \ + supervisor/shared/autoreload.c \ + supervisor/shared/rgb_led_status.c + +ifeq ($(wildcard supervisor/filesystem.c),) + SRC_SUPERVISOR += supervisor/filesystem.c +else + SRC_SUPERVISOR += supervisor/stub/filesystem.c +endif + +ifeq ($(wildcard atmel-samd/supervisor/serial.c),) + SRC_SUPERVISOR += supervisor/serial.c +else + SRC_SUPERVISOR += supervisor/stub/serial.c +endif + +SUPERVISOR_O = $(addprefix $(BUILD)/, $(SRC_SUPERVISOR:.c=.o)) diff --git a/tools/build_adafruit_bins.sh b/tools/build_adafruit_bins.sh index 462ec97113201..e075b5f69cb46 100755 --- a/tools/build_adafruit_bins.sh +++ b/tools/build_adafruit_bins.sh @@ -1,7 +1,7 @@ rm -rf atmel-samd/build* rm -rf esp8266/build* -ATMEL_BOARDS="arduino_zero circuitplayground_express feather_m0_basic feather_m0_adalogger feather_m0_express metro_m0_express trinket_m0 gemma_m0" +ATMEL_BOARDS="arduino_zero circuitplayground_express feather_m0_basic feather_m0_adalogger feather_m0_express metro_m0_express metro_m4_express trinket_m0 gemma_m0" ROSIE_SETUPS="rosie-ci" for board in $ATMEL_BOARDS; do